Jim, I agree.

Of course there are still some designs being done that aren't high speed and
for which HSDD tools wouldn't help.  Maybe the CEO is still imagining PCB
design is what it was a decade or two ago.  After all, when was the last
time the CEO probably laid out a HSDD board?  (Or likely any board for that
matter?)  Maybe what we need to do is somehow focus on convincing the CEO of
the magnitude of this paradigm shift in the industry and the impact it has
on overall productivity.  I have spent 100's of hours balancing differential
traces and serpentine busses in complex designs of high density.  If it is
understood how huge the need is and how common it is becoming, it should
also become clear why designers without such tools cannot be competitive and
so for survival must mandatorily switch to another tool.  When over half the
designs you do involve HSDD, you won't win any if your bid is based on twice
as many hours as people with proper tools; and you can't just no bid them or
arbitrarily cut your bid in half to win it: you'll go out of business.

Jeff Condit

----- Original Message ----- 
From: "Jim Monroe" <[EMAIL PROTECTED]>
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Thursday, September 09, 2004 1:31 PM
Subject: Re: [PEDA] High Speed Design (was: 99SE Find Files Found)


> Mike- that was my point. DXP has not added or improved ANY high speed
> design capabilities. DXP is nearly unchanged from 99se. In fact, I'd
> venture to say that more capability had been removed than added.
>
> The 99se high speed rules and length matching were an okay start when they
> were introduced many years ago, but I was expecting those features to be
> polished and additional capabilities to be added. That hasn't happened.
>
> Here's an abbreviated list of what I need in the realm of high speed
design:
>
> * All nets and classes must have a skew length factor to compensate for
the
> various in-chip lengths of different signals.
>
> * Length matching must support series caps and resistors.
>
> * Length matching parameters must include WIDTH (frequency?), not just gap
> and amplitude.
>
> * The length matching amplitude parameter must be a maximum setting (not
> fixed) so that the length matching can reduce amplitude as needed to fit
> the zig-zagging within the available space around each net.
>
> * Length matching must run in batch mode. Manually running each pass to
add
> just one amplitude section at a time is ridiculous. Would any EDA vendor
> dream of making an autorouter that only partially routed each net before
it
> had to be re-started (yeah, maybe Altium)? Ideally, the length matching
> would automatically regenerate (much like polygons) if a net were
rerouted.
>
> * Must have design rules specific to differential pairs.
>
> * Must have Interactive routing of differential pairs (both nets are
placed
> simultaneously with correct width and spacing per rules).
>
> I could make this list much longer but these are the basics. These
features
> could easily save me 20-30 hours per board!
>
> There was an article recently pointed out by another forum member (sorry I
> don't remember who or when exactly) which seemed to indicate that Altium's
> CEO doesn't think high speed design features are very important (at least
> that was my interpretation). Given that, and the fact that DXP has added
> very little design capability to PCB layout, I am very rapidly loosing
hope
> that DXP is a platform that I will be able to continue using much longer.
>
> JM
>
>
> At 05:59 AM 9/9/2004, Mike Reagan wrote:
> >Jim wrote:
> >
> >.....DXP is now moving toward it's 2nd birthday and I think most of us
> >feel its not nearly as usable or productive as its predecessor. 99se was
> >showing its age in it's lack of many high speed design features.
> >
> >Jim
> >I would be interested in hearing one high speed feature that was
> >implemented in DXP.  I have yet to find any.  I use both DXP and 99SE.
If
> >anything 99SE has a huge advantage over DXP with ease of use in the
design
> >rules menu.   Try to set up maximum parallel rules between net classes in
> >DXP sometime,  it becomes an experiment in programming. Actually,  I
found
> >a bug in DXP that it doesnt support more than three different levels of
> >layer rules when exporting to a dsn file. This is hardlly a high speed
> >advancement.
> >
> >Mike Reagan
> >EDSI Frederick MD
>
>
>
>





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