Marcel Kilgus via Ql-Users wrote:
> As I've understood your chip is 3.3V and the lines (or GND) is too
> noisy so that logic level 0 could be interpreted as 1 before the lines
Yes this is one of the aspects, but it's not a 3.3V versus 5V issue.
(The relevant logic levels are the same.)
The rise and fall timings of the SGC (and to a smaller degree GC)
are too fast for the QL mainboard, which creates too much crosstalk
and ringing. Even without QL-SD, illegal levels occur and can be
seen on oscilloscope. The QL itself only works because it's hardware
is too slow to "see" these illegal levels.
> because the chip samples them faster as older chips would, is
> that about right?
Roughly. A 400 MHz chip inside an ancient 8 MHz design.
> Would it help to put a 74-style Schmitt-trigger in
> front of ROMOEH or something like that?
-> qlromext-sch.pdf, see U4 ;)
Unfortunately this was not good enough to get the SGC working.
I guess the best solution would be another QL-SD design with an old,
slow PLD. Second best: Experimenting with serial resitors in all
lines. A different place (e.g. external ROM port) might also help,
but it is hard to predict.
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