Marcel Kilgus via Ql-Users wrote:
> I've already started putting together a clone using an Xilinx
> XC9572XL, which I have lying around. The Verilog file compiled from
> the get-go, I just had to remove the additional SS lines because of
> Pin restrictions in the small chip on my eval board. The long lines to
> the board might not exactly help, though... might take a while, but I
> will try to make a GoldCard compatible QL-SD one way or another, now
> that I have your release to base it on :-)

Well, I said I'd do it and apparently I did it:

Now I'm looking forward to test the fix on the original hardware, as
the clone is still a bit unwieldly ;-)


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