Re: VarIabLe DD names in VSAM

[Sharuff Morsa3]

Referring to Chris's comment -...extensively commented assembler programs
...-  I'm all in favour of well commented code - I believe 'good
comments' should be mandatory. But what is a 'good comment'?  Who hasn't
seen something like:

MVCC89FLA,C60MGT   move C60MGT to C89FLA
or even (shock horror!)
MVCC89FLA,C60MGT   move C89FLA to C60MGT

Is that a useful comment ? It does describe the instruction, but how
useful is the comment ?

Would anyone want to share good/bad comments they've seen ?

Sharuff

smo...@uk.ibm.com

Sent from my laptop





--

Date:Thu, 9 Feb 2012 11:01:21 +0100
From:Chris Mason chrisma...@belgacom.net
Subject: Re: VarIabLe DD names in VSAM.

Tony


snip 
[1] I believe there are some in this list to whom this approach is some
sort
of heresy! (Actually it's probably this sort of mind-set that caused John
actually to try to use the xxxCB macros!) My excuse is contained in a
comment one of my managers made to the effect, he had never seen such
extensively commented assembler programs and he was one of those managers
who really used to be happier as a technician. He was responsible for
installing - in the SE sense of the word - one of the first 360/67s.
... snips
-

Chris Mason


End of ASSEMBLER-LIST Digest - 8 Feb 2012 to 9 Feb 2012 (#2012-30)
**








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MVC with 2nd operand length

[Sharuff Morsa3]

I have raised a requirement on HLASM to see what they can do to
improve/change the behavior raised in this thread.

You can find the RFE at
http://www.ibm.com/developerworks/rfe/execute?use_case=viewRfeCR_ID=22828


Please add your comments to the RFE.
Sharuff

Sharuff Morsa - IBM Hursley Labs
HLASM Product Architect
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DCLEN -- V1R6 Language Ref : SC26-4940-05

[Sharuff Morsa3]

Paul wrote

Hello, MHVRCFS

(I can find no email contact information in this publication.
This has worked for other publications.  Will it work for this?)

In:

Title: V1R6 Language Ref
Document Number: SC26-4940-05

The last few pages of the manual (
http://publibfp.boulder.ibm.com/cgi-bin/bookmgr/download/asmr1020.pdf -
pages 437) enables you to print and then mail (USA FREEPOST) a readers
comment to us at IBM. However, you may find the web interface easier to
use.
Web based readers comments can be submitted via this IBM web page:
  http://www-03.ibm.com/systems/z/os/zos/webqs.html

Sharuff

Sharuff Morsa
HLASM Product Architect

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741598.
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MVC with 2nd operand length

[Sharuff Morsa3]

This is an interesting discussion with lots of useful information and code
snippets.  The Request For Enhancement has been submitted to the HLASM
team at IBM.  Please use this URL
http://www.ibm.com/developerworks/rfe/execute?use_case=viewRfeCR_ID=22828
 to add your cements to the request. The RFE also allows you to add
attachments.
Sharuff

Sharuff Morsa
IBM Hursley
Unless stated otherwise above:
IBM United Kingdom Limited - Registered in England and Wales with number
741598.
Registered office: PO Box 41, North Harbour, Portsmouth, Hampshire PO6 3AU

Re: Opinions? Syntax enhancement to numeric literals.

[Sharuff Morsa3]

John wrote:

 Date:Mon, 4 Jun 2012 21:16:35 -0400
 From:John Gilmore johnwgilmore0...@gmail.com
 Subject: Re: Opinions? Syntax enhancement to numeric literals.

 I have taxed other people with not having mastered details, but I must
 admit that I did not know that

 |  DCF'2 147 483 647'

 was licit.  In the interests of coherence, it should be possible to
write

 |  DCF'2_147_483_647'

 if it is possible to write

 |FMAX EQU   2_147_483_647


 John Gilmore, Ashland, MA 01721 - USA



I've submitted a request for the HLASM team to consider this. Please go
read the RFE and add comments
https://www.ibm.com/developerworks/rfe/execute?use_case=viewRfeCR_ID=23186


Sharuff

Sharuf Morsa smo...@uk.ibm.com

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Re: ASSEMBLER-LIST Digest - 17 Jun 2012 to 18 Jun 2012 (#2012-113)

[Sharuff Morsa3]

This is a good idea - I've raised an RFE:

http://www.ibm.com/developerworks/rfe/execute?use_case=viewRfeCR_ID=23635


If you also believe this is useful, please add comment/votes to the RFE
entry

Sharuff

Sharuff Morsa - IBM Hursley


IBM Mainframe Assembler List ASSEMBLER-LIST@listserv.uga.edu wrote on
19/06/2012 05:00:37:
 --

 Date:Mon, 18 Jun 2012 09:16:35 -0600
 From:Paul Gilmartin paulgboul...@aim.com
 Subject: YA wishlist item.

 Excerpted from IBM-MAIN:

 The assembly uses the BATCH option. There are multiple assembly steps
and
 the RETURN CODE you are quoting is from the LAST batched assemble.
 
 The OP and several followups (including mine) were misled
 by this.  It would be a useful enhancement if HLASM provided
 a summary summary line:

 Number of assemblies: nnn  Highest return code: 12

 If you search through the listing you'll find the non-zero return code.
 
 Well, yah, I usually do that.

 -- gil

 --

 Date:Mon, 18 Jun 2012 10:30:31 -0500
 From:McKown, John john.mck...@healthmarkets.com
 Subject: Re: Base registers

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ADATA

[Sharuff Morsa3]

I should also say:
Ed make a useful suggestion - make some of these items Share requests.

Also, John and I will be in San Francisco at the spring Share conference.
We (am taking a liberty here - I've not asked John, but I'm sure the
answer is yes) can sort out a conference room to discuss ADATA or other
topics.

Sharuff

Sharuff Morsa - IBM Hursley
Unless stated otherwise above:
IBM United Kingdom Limited - Registered in England and Wales with number
741598.
Registered office: PO Box 41, North Harbour, Portsmouth, Hampshire PO6 3AU

Use of sequence numbering in current HLASM

[Sharuff Morsa3]

Sequence numbers is one of those topics where opinions divide.  HLASM -
written in HLASM, has had their sequence numbers stripped and stored in
UTF8 on a Jazz server.  We use RTC and Jazz for HLASM. Its an integrated
system - source control and project management, all together in RTC.  Not
only internal project management, but the RFE requests come through to my
RTC as well - and they are all linked together.  Its not just about source
code. All these pieces fit together - provide development, test and
management with a consistent  coherent view. I get security and auditing
for free. I'm sure its no secret, but the other products at the lab have
also moved to RTC - and are using RTC as an integrated system - and other
products at our sister labs are doing the same.  There is flexibility in
what we do, I know some teams have chosen subversion.

Thinking about sequence numbers is just the tip of the iceberg.

Sharuff

Sharuff Morsa - IBM Hursley
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Extended Mnemonics After Unsigned Arithmetic

[Sharuff Morsa3]

Ed,
I think a SHARE requirement would be a useful start to discussing
additional extended mnemonics.  I'd follow that up with a HLASM RFE
request.
How do we start the SHARE requirement ? and would you expect to discuss
this at Boston or before ?

Sharuff

Sharuff Morsa
HLASM IBM Hursley


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IBM United Kingdom Limited - Registered in England and Wales with number
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Registered office: PO Box 41, North Harbour, Portsmouth, Hampshire PO6 3AU

Re: 64 bit question

[Sharuff Morsa3]

 Scott mentions customers and 24-bit and yestedrday Paul Gilmartin mention
'during the transition from 370 to XA'
and...
I'm interested about what assembler code 'out there' (zOS,zVM or zVSE)
still contained (probably as dual code path?) XA or 370 or 390 only code
path/instructions - and why.  I understand that not all would like to
discuss that information on the forum, but if you do wish to share
information/stories off list then please email me at smo...@uk.ibm.com
Thanks
Sharuff
Sharuff Morsa - IBM Hursley Labs
.. and a quick plug for...
http://www.ibm.com/support/docview.wss?uid=swg21577670 - for HLASM
requirements
http://www.ibm.com/support/docview.wss?uid=swg21595123 - for HLASM readers
comments



Date:Thu, 13 Jun 2013 13:56:12 -0400
.From:Scott Ford scott_j_f...@yahoo.com
Subject: Re: 64 bit question

John,

As a vendor I won't assume ..I have customers who still think we should
write our code in 24 bit mode. So don't get me started. I know your right
from my experience , but I would rather be safe than sorry

Scott ford
www.identityforge.com
from my IPAD






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Re: PDSE and HLASM together in z/OS 2.1

[Sharuff Morsa3]

Miklos Szigetvari wrote:

Subject: PDSE and HLASM together in z/OS 2.1
...
After a PMR it turned out that the PDSE has not enough storage.
We are using the default assembler OPTION SIZE(MAX) . In this case ,
according the book , the assembler gives back 128 K byte storage, but it
is not big enough for PDSE.
I will change the default SIZE, but maybe the assembler would gives back
something more as 128K ?

SIZE=MAX is the default.

Reading the HLASM Install guide SC26-3494-05
http://publibfp.boulder.ibm.com/cgi-bin/bookmgr/download/asmi1021.pdf
page 170, note 4 says: '4. When you specify the MAX suboption, the
assembler releases 128 K back to the user region (z/OS), virtual machine
(CMS), or the partition GETVIS (z/VSE), for system usage. When you specify
the  MAX suboption, there might not be enough storage remaining in the
user region (z/OS), virtual machine (CMS), or the partition GETVIS
(z/VSE), to load any exits you specify, or any external functions you use
in your assembly.

I also found the HLASM V1.4 pdf (dated Sept 2000) - and it has the same
words - and I'd put good money on the older versions saying the same.

Richard (the HLASM developer) has asked whether this is the time to change
the 128k value  increase it a little rather than have everyone change
their procedures. If an RFE or request appears - I'm sure an APAR will
soon turn up. (An RFE would be a good place for all to suggest what value
should be used in place of 128k)

Sharuff
smo...@uk.ibm.com



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Re: PDSE and HLASM together in z/OS 2.1

[Sharuff Morsa3]

After a bit of (archaeological) digging, it appears our manuals are
incorrect and that we've visited this issue before.
When HLASM 1.4 development was in full flight, the CODEPAGE option was
added. This appears to have fallen victim to the short-on-os-storage issue
- and the coded 128k value was changed to a whopping 132K! - the books
never caught up with this modification.

I agree with Miklos, and we will look to change this value - Richard will
be on the case when he returns from SHARE.

Sharuff
smo...@uk.ibm.com

btw - anyone going to SHARE ? If so, go say hello to Richard Cebula - its
his first SHARE conference!


From:Miklos Szigetvari miklos.szigetv...@isis-papyrus.com
Subject: Re: PDSE and HLASM together in z/OS 2.1

 Hi

Thank you Sharuff.
We have closed the PMR76555.010.618, as with REGION=1000M it worked,
I think it would be not bad if the SIZE default would be a little less.


On 27.02.2014 13:38, Sharuff Morsa3 wrote:




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PTF level in SYSPRINT

[Sharuff Morsa3]

Gil

If you (or anyone on the list) would like to see the PTF level in a GBLC
symbol, or indeed, any other useful piece of information in a system GBLC,
simply raise a requirement (go read
http://www.ibm.com/support/docview.wss?uid=swg21577670 on how to do raise
one).

And as Jonathan mentioned, ASMA9Z does contain the PTF number - and I'm
sure some will go look and decode the entries. But remember, it is (as we
say) 'NOT Programming Interface Information' - it may change.

Maintenance levels, for our products is the domain of SMP/e - its the
source of information on what is applied, on co-req and pre-req chains.

It is interesting to note that the IBM Installation manager is fast
catching up on installing, tracking products and service levels - and is
being used by WAS on z - see:
http://www.ibm.com/support/techdocs/atsmastr.nsf/WebIndex/WP102014
http://www.youtube.com/watch?v=Pi7F0QTT7oo
Session 10633 given by Mike Loos at  SHARE back in 2012 (available at
SHARE web site)

Will it replace smp/e for all products ? - no (probably not - but I can't
predict the future), but for cross platform products, it simplifies
installation and maintenance.

Sharuff


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Re: Macros -- was: EDit mask for floating minus (negative)

[Sharuff Morsa3]

I work regularly with Steve. It is, and has been, a please and a delight. 
I've always respected his views, many of which I agree with. 
Sharuff 

smo...@uk.ibm.com

 
 Date:Tue, 22 Jul 2014 16:35:36 -0400
 From:Tony Thigpen t...@vse2pdf.com
 Subject: Re: Macros -- was: EDit mask for floating minus (negative)
 
 There is just so much wrong with several things you mentioned.
 But, based on your last statement, you don't care anyway, so I, for one, 

 will not bother.
 
 I just pity the poor people you work with.
 
 Tony Thigpen
 
 -Original Message -
   From: Steve Hobson
   Sent: 07/22/2014 04:25 PM

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Re: What does the 'end' address on a USING statement mean?

[Sharuff Morsa3]

USING ought to be as helpful as possible. 
HLASM - like other products can be driven by user requests. The more
requests/votes we have - the higher up the list the requirement goes. 
If the community feels this change is important/useful/desirable 
then please raise a requirement and vote for it. 
It will certainly get my vote. 

see http://www.ibm.com/support/docview.wss?uid=swg21577670

Sharuff 


 Date:Tue, 4 Nov 2014 08:41:10 -0700
 From:Paul Gilmartin paulgboul...@aim.com
 Subject: Re: What does the 'end' address on a USING statement mean?
 
 On 2014-11-04, at 05:54, Peter Relson wrote:
  
  Since the construct pre-dated long-displacement, it's quite possible 
that 
  it means very little with respect to long displacement. Or perhaps, 
for 
  long displacement, the end is to some extent ignored (although it 
might 
  be used to select from among multiple choices).
  ...
  As opposed to
  USING (*,*+1000),RegA
  USING *+1000,RegB
  
 It seems to me to be even more important to enforce END with long
 displacements because in many cases base register combinations
 which produce unique resolutions with 12-bit displacements may
 produce ambiguous resolutions with long displacements.
 
 I suspect that HLASM development merely overlooked the design
 changes necessary to accommodate long displacements fully.
 
 -- gil
 
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Registered office: PO Box 41, North Harbour, Portsmouth, Hampshire PO6 3AU

Re: 8 character mnemonics

[Sharuff Morsa3]

Ain't progress wonderful?

Anyone know how to stop it ? (progress that is) 

I would not rule out  8 character mnemonics nor  8 character HLASM 
assembler directives (not that I'm currently planning any). 

Because of the very large number of mnemonics and extended mnemonics which 
have been added, there are some ISPF SuperC commands to assist users in 
searching their source, copybook and macro libraries to see if they may be 
affected (http://www.ibm.com/support/docview.wss?uid=swg21694301). 

The new instructions have highlighted a problem for which we have to 
strike a balance.  Several of the new instructions have the same mnemonics 
but differing instruction formats.  Who can successfully execute ESA/390 
vector instructions ? But some users will have these mnemonics are coded 
in their applications (anyone want to own up having some?). 

Should we always (100%) maintain the ability for users programs to 
assemble programs cleanly even though they would not execute successfully? 
How much can a product change (or evolve) without users having to make 
some or consider those changes ? 

IBM z Systems have a very long history of minimising the affect of changes 
on users - but products and their usage change over time.  How customers 
use our products changes over time.  Is that progress ? 

Sharuff

Sharuff Morsa IBM Hursley Labs 


 
 Date:Wed, 21 Jan 2015 11:03:34 -0800
 From:John Ehrman ehr...@us.ibm.com
 Subject: Re: 8 character mnemonics
 
 Paul Gilmartin asked...
 But are new mnemonics vetted against all member names in all maclibs 
of 
 all IBM products? (Do significant ISVs count?)
 
 That was indeed done many moons ago, but the number of products with 
 private macro libraries grew far beyond the capabilities of the 
 vetters so it's not done any longer.
 
 John Ehrman
 
 --
 
 Date:Wed, 21 Jan 2015 15:18:27 -0700
 From:Paul Gilmartin paulgboul...@aim.com
 Subject: Re: 8 character mnemonics
 
 On 2015-01-21 12:03, John Ehrman wrote:
  Paul Gilmartin asked...
  But are new mnemonics vetted against all member names in all maclibs 
of 
  all IBM products? (Do significant ISVs count?)
  
  That was indeed done many moons ago, but the number of products with 
  private macro libraries grew far beyond the capabilities of the 
  vetters so it's not done any longer.
  
 Ain't progress wonderful?
 
 -- gil
 
 --
 
 End of ASSEMBLER-LIST Digest - 20 Jan 2015 to 21 Jan 2015 (#2015-12)
 
 

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Registered office: PO Box 41, North Harbour, Portsmouth, Hampshire PO6 3AU

Re: Questions about Invoking the Assembler Dynamically

[Sharuff Morsa3]

Joe
If you specify (or default to) NOADATA, the file is not opened 
and
the book HLASM V1R6 Programmer's Guide - Table 24. Invoking the assembler 
dynamically) says:
ddnamelist
Specifies the address of a variable-length list containing alternative 
ddnames for the data sets
used during assembler processing. If standard ddnames are used, this 
operand can be omitted

regards 
Sharuff 

IBM Mainframe Assembler List  wrote on 
16/09/2016 00:12:13:

> From: Joe Reichman 
> To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
> Date: 16/09/2016 00:12
> Subject: Questions about Invoking the Assembler Dynamically
> Sent by: IBM Mainframe Assembler List 
> 
> Hi
> 
> 
> 
> I am invoking ASMA90 Dynamically two questions
> 
> 
> 
> If I  am using the standard DDNAMES I don't have to specify a second 
param
> only a options list correct ?
> 
> 
> 
> Also If I don't specify a ADATA param do I have to allocate a SYSADATA ? 
 
> 
> 
> 

Unless stated otherwise above:
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Registered office: PO Box 41, North Harbour, Portsmouth, Hampshire PO6 3AU

Re: Rif: Re: EXECUTE Instruction and location of its target instruction

[Sharuff Morsa3]

The closet instruction is HLASM has for what Gil asked is CNOP - updated a 
couple of years ago by apar PI17455 - but you do need to know what your 
cache lines are. 
see http://www.ibm.com/support/docview.wss?uid=isg1PI17455 
and http://www.ibm.com/support/docview.wss?uid=swg21687009 
Where the OPTABLE value is not one of DOS, 370 or XA, the CNOP generated 
no-operation instructions are BRC or BRCL instructions. 
Sharuff 


IBM Mainframe Assembler List  wrote on 
24/11/2016 00:50:16:

> From: Paul Gilmartin <0014e0e4a59b-dmarc-requ...@listserv.uga.edu>
> To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
> Date: 24/11/2016 00:50
> Subject: Re: Rif: Re: EXECUTE Instruction and location of its target
> instruction
> Sent by: IBM Mainframe Assembler List 
> 
> On 2016-11-23 07:19, aldo.cro...@csebo.it wrote:
> > I think it is appropriate to use a EXRL (execute remote) intest a EX.
> > I also think that it is appropriate to place the subject of education
> > execute close to the EX, preferably after a statement of unconditional
> > branch.
> > 
> Is it recommended for legibility/maintainability that the subject appear
> adjacent to the EX rather than after a nearby unrelated branch?
> 
> What effect does an unconditional branch have on branch 
prediction/pipelining?
> http://www.wrenvironmental.com/commercial/services/pipelining/
> 
> Is LOCTR a help?  I can imagine the frustration of a programmer trying 
to
> correlate a dump with a listing where the author has used LOCTR heavily
> and wishing that HLASM had an option to generate SYSPRINT in address 
order
> rather than in source order.
> 
> Does HLASM have an instruction to cause cache line alignment?  Such an
> instruction would need to be model-sensitive, perhaps governed by 
OPTABLE.
> 
> -- gil
> 

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Registered office: PO Box 41, North Harbour, Portsmouth, Hampshire PO6 3AU

Re: Rif: Re: Rif: Re: EXECUTE Instruction and location of its target instruction

[Sharuff Morsa3]

Your listing confused me. At the latest HLASM version (UI42852) I get:
 
  LocObject Code  Addr1Addr2Stmt  Source Statement  
   1 * from ASSEMBLER-LIST 
24/11/2016
 0032  2 PREXRL   RSECT  
 B240 00E0 3  BAKR  14,0  
0004 C600  0013  002A  4  EXRL  0,A  
000A C600  0013  0030  5  EXRL  0,B  
0010 C600  0014  0038  6  EXRL  0,C  
0016 C600  0013  003C  7  EXRL  0,D  
001C C010  FFF2    8  LARL  1,PREXRL   
 
0022   9  DC X''   

0026 17FF 10  XR15,15   
0028 0101 11  PR  
002A 1711 12 AXR1,1  
002C 404040   13  DCCL3' '   
002F 00  
0030 1711 15 BXR1,1  
00380038 0006 16 PRXX RSECT  
0038 1711 17 CXR1,1  
003A 40   18  DCCL1' '   
003B 00  
003C 1711 20 DXR1,1  
  21  END  
with RLD xref correctly showing: 
Relocation Dictionary
  Pos.Id   Rel.Id   Address  TypeLength  Action 
 0004 0009 0012  RI 4   + 
 0004 0009 0018  RI 4   +
 
The data in ADDR2 is correct (and useful), as well as the instructions 
printed. 
 
Sharuff 

IBM Mainframe Assembler List  wrote on 
24/11/2016 11:12:52:

> From: aldo.cro...@csebo.it
> To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
> Date: 24/11/2016 11:13
> Subject: Rif: Re: Rif: Re: EXECUTE Instruction and location of its 
> target instruction
> Sent by: IBM Mainframe Assembler List 
> 
> > What effect does an unconditional branch have on branch
> prediction/pipelining?
> > Is LOCTR a help?  I can imagine the frustration of a programmer trying
> to
> > Does HLASM have an instruction to cause cache line alignment?  Such an
> > instruction would need to be model-sensitive, perhaps governed by
> OPTABLE.
> 
> 
> 
> the object is placed near the EXRL to improve the readability of the
> program.
> unconditional branch can be one already present more near (before or 
after
> the exrl)
> 
> when an instruction is encoded this is always aligned at half word
> 
> ctive Usings: hash,R4  cnv$$,R11  CEECAA,R12  CEEDSA,R13
> ocObject Code  Addr1Addr2Stmt  Source Statement
> 00234 715ds  0f
> 00234 A7  716dc  cl1'x'
> 00235 00
> 00236 D200 1000 2000  717 exobj  mvc 0(1,1),0
> (2)
> 0023C 81  718dc  cl1'a'
> 0023D 00
> 0023E D200 1000 2000  719 exobj1 mvc 0(1,1),0
> (2)
> 
> 
> 
> 
> 
> 
> the subject of EXRL can be positioned anywhere in the "not writable"
> encoding. even within a CSECT / RSECT different from the primary.
> the possible use of LOCTR does not affect relative addressing.
> in case of statement object to another csect the relative address is
> calculated by the linkage editor
> 
> Active Usings: None
> LocObject Code  Addr1Addr2Stmt  Source Statement
> 00 0032  1 PREXRL   RSECT
> 00 B240 00E0 2  BAKR  14,0
> 04 C600  0013  002A  3  EXRL  0,A
> 0A C600  0013  0030  4  EXRL  0,B
> 10 C600  FFF8    5  EXRL  0,C
> 16 C600  FFF7  0004  6  EXRL  0,D
> 1C C010  FFF2    7  LARL  1,PREXRL
> 22   8  DC X''
> 26 17FF  9  XR15,15
> 28 0101 10  PR
> 2A 1711 11 AXR1,1
> 2C 404040   12  DCCL3' '
> 2F 00
> 30 1711 13 BXR1,1
> 00 0006 14 PRXX RSECT
> 00 1711 15 CXR1,1
> 02 40   16  DCCL1' '
> 03 00
> 04 1711 17 DXR1,1
> 18 

Re: random quest

[Sharuff Morsa3]

.. am I the only one who is beginning to feel that 'random quest' needs 
its own forum ? 
Sharuff 


IBM Mainframe Assembler List  wrote on 
18/05/2017 15:35:57:

> From: Paul Gilmartin <0014e0e4a59b-dmarc-requ...@listserv.uga.edu>
> To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
> Date: 18/05/2017 15:36
> Subject: Re: random quest
> Sent by: IBM Mainframe Assembler List 
> 
> On 2017-05-18, at 08:07, Martin Ward wrote:
> 
> > On 18/05/2017 11:57, Martin Ward wrote:
> >> 
> >> The "random bit probe" algorithm is an example of
> >> a "coupon collector's problem":
> >> 
> >> https://en.wikipedia.org/wiki/Coupon_collector%27s_problem
> >> 
> >> The expected number of trials (and therefore runtime)
> >> is n log n (plus smaller terms). This might still
> >> take too long on a mainframe of the era we are talking about,
> >> given that it took over two seconds on a modern PC.
> > 
> > Also: for those who worry about such things, the "worst case runtime"
> > is infinite :-)
> > 
> In many practical applications the constant coefficient overwhelms
> the theoritical asymptotic behavior.  And DFSORT designers took
> pains to accommodate real DASD characteristics.
> 
> Might "random bit probe" fail surprisingly early because of the
> "Birthday paradox"?
> 
> It's disappoinging that the Rexx RANDOM() function does not
> accommodate the NUMERIC DIGITS setting.
> 
> -- gil
> 

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