date:20120319

[gem5-dev] changeset in gem5: Garnet: Stats at vnet granularity + code cleanup

2012-03-19 Thread Tushar Krishna

changeset c739a3a829f5 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=c739a3a829f5
description:
Garnet: Stats at vnet granularity + code cleanup

This patch
(1) Moves redundant code from fixed and flexible networks to 
BaseGarnetNetwork.
(2) Prints network stats at vnet granularity.

diffstat:

 src/mem/ruby/network/garnet/BaseGarnetNetwork.cc  |  96 
+-
 src/mem/ruby/network/garnet/BaseGarnetNetwork.hh  |  42 +++-
 src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc |  56 +
 src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.hh |  30 +--
 src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc  |   9 +-
 src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc|  72 ++-
 src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.hh|  38 +---
 src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc |   9 +-
 8 files changed, 179 insertions(+), 173 deletions(-)

diffs (truncated from 573 to 300 lines):

diff -r 75b524b64c28 -r c739a3a829f5 
src/mem/ruby/network/garnet/BaseGarnetNetwork.cc
--- a/src/mem/ruby/network/garnet/BaseGarnetNetwork.cc  Mon Mar 19 06:36:09 
2012 -0400
+++ b/src/mem/ruby/network/garnet/BaseGarnetNetwork.cc  Mon Mar 19 17:34:17 
2012 -0400
@@ -43,10 +43,6 @@
 fault_model = p->fault_model;
 
 m_ruby_start = 0;
-m_flits_received = 0;
-m_flits_injected = 0;
-m_network_latency = 0.0;
-m_queueing_latency = 0.0;
 
 // Currently Garnet only supports uniform bandwidth for all
 // links and network interfaces.
@@ -77,9 +73,17 @@
 
 m_in_use.resize(m_virtual_networks);
 m_ordered.resize(m_virtual_networks);
+m_flits_received.resize(m_virtual_networks);
+m_flits_injected.resize(m_virtual_networks);
+m_network_latency.resize(m_virtual_networks);
+m_queueing_latency.resize(m_virtual_networks);
 for (int i = 0; i < m_virtual_networks; i++) {
 m_in_use[i] = false;
 m_ordered[i] = false;
+m_flits_received[i] = 0;
+m_flits_injected[i] = 0;
+m_network_latency[i] = 0.0;
+m_queueing_latency[i] = 0.0;
 }
 
 for (int node = 0; node < m_nodes; node++) {
@@ -101,3 +105,87 @@
 {
 Network::init();
 }
+
+MessageBuffer*
+BaseGarnetNetwork::getToNetQueue(NodeID id, bool ordered, int network_num,
+ string vnet_type)
+{
+checkNetworkAllocation(id, ordered, network_num, vnet_type);
+return m_toNetQueues[id][network_num];
+}
+
+MessageBuffer*
+BaseGarnetNetwork::getFromNetQueue(NodeID id, bool ordered, int network_num,  
+   string vnet_type)
+{
+checkNetworkAllocation(id, ordered, network_num, vnet_type);
+return m_fromNetQueues[id][network_num];
+}
+
+void
+BaseGarnetNetwork::clearStats()
+{
+m_ruby_start = g_eventQueue_ptr->getTime();
+}
+
+Time
+BaseGarnetNetwork::getRubyStartTime()
+{
+return m_ruby_start;
+}
+
+void
+BaseGarnetNetwork::printStats(ostream& out) const
+{
+out << endl;
+out << "Network Stats" << endl;
+out << "-" << endl;
+out << endl;
+printPerformanceStats(out);
+printLinkStats(out);
+printPowerStats(out);
+m_topology_ptr->printStats(out);
+}
+
+void
+BaseGarnetNetwork::printPerformanceStats(ostream& out) const
+{
+int total_flits_injected = 0;
+int total_flits_received = 0;
+int total_network_latency = 0.0;
+int total_queueing_latency = 0.0;
+
+for (int i = 0; i < m_virtual_networks; i++) {
+if (!m_in_use[i])
+continue;
+
+out << "[Vnet " << i << "]: flits injected = "
+<< m_flits_injected[i] << endl;
+out << "[Vnet " << i << "]: flits received = "
+<< m_flits_received[i] << endl;
+out << "[Vnet " << i << "]: average network latency = "
+<< ((double) m_network_latency[i] / (double) m_flits_received[i])
+<< endl;
+out << "[Vnet " << i << "]: average queueing (at source NI) latency = "
+<< ((double) m_queueing_latency[i] / (double) m_flits_received[i])
+<< endl;
+
+out << endl;
+total_flits_injected += m_flits_injected[i];
+total_flits_received += m_flits_received[i];
+total_network_latency += m_network_latency[i];
+total_queueing_latency += m_queueing_latency[i];
+}
+out << "Total flits injected = " << total_flits_injected << endl;
+out << "Total flits received = " << total_flits_received << endl;
+out << "Average network latency = "
+<< ((double) total_network_latency/ (double) total_flits_received) << 
endl;
+out << "Average queueing (at source NI) latency = "
+<< ((double) total_queueing_latency/ (double) total_flits_received) << 
endl;
+out << "Average latency = "
+<< ((double)  (total_queueing_latency + total_network_latency) /
+(double) tota

Re: [gem5-dev] Review Request: Interface to integrate TOPAZ network simulator (http://code.google.com/p/tpzsimul/) within GEM5-RUBY

2012-03-19 Thread Brad Beckmann


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It looks much better.  I just a few more comments for improvement.  They all 
should be pretty easy to take care of.


src/mem/ruby/network/Network.hh


Minor comment:

Instead of defining the emtpy function as "{return;};", I believe the 
common convention is to leave it empty "{}"



src/mem/ruby/network/topaz/SConscript


For all new files, please modify the copywrite owner to the correct 
institution.



src/mem/ruby/network/topaz/TopazNetwork.hh


Update copywrite holder



src/mem/ruby/network/topaz/TopazNetwork.hh


Remove all the "//BEGIN TOPAZ" and "//END TOPAZ" comments.  They seem 
needless and confusing.





src/mem/ruby/network/topaz/TopazNetwork.hh


Now that you've added more Topaz files to this patch, do you still need to 
include the separate TPZSimulator header file?

If so, I suspect you make this work by using scons EXTRAS and turning on 
the USE_TOPAZ command line variable.  Can you briefly describe that process 
here?



src/mem/ruby/network/topaz/TopazNetwork.py


Add copywrite and license to this file



src/mem/ruby/network/topaz/TopazSwitch.hh


Update comment



src/mem/ruby/network/topaz/TopazSwitchFlow.hh


update comment



src/mem/ruby/profiler/Profiler.cc


Why did you have to include this file?



src/mem/ruby/profiler/Profiler.cc


Why did you remove this line?  It seems like the changes you make to 
Profiler.cc are unnecessary.


- Brad Beckmann


On March 19, 2012, 12:11 p.m., Valentin Puente wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/1095/
> ---
> 
> (Updated March 19, 2012, 12:11 p.m.)
> 
> 
> Review request for Default, Nilay Vaish and Brad Beckmann.
> 
> 
> Description
> ---
> 
> Interface to integrate TOPAZ network simulator 
> (http://code.google.com/p/tpzsimul/)  within GEM5-RUBY. Does not replace 
> ruby's interconnection network simulators (garnet and simple-network). It 
> just adds the hookups required to connect ruby and TOPAZ. You have to 
> download as "ext" TOPAZ from an external repo. 
> 
> To have a better perspective of the changes, you can follow the guide 
> provided in http://code.google.com/p/tpzsimul/wiki/GEM5Integration. In order 
> to integrate the compilation process of both simulators we have to slightly 
> modify main SConstruct and ruby SCons files.  All the remaining changes are 
> constrained to Ruby. Main modifications have been done in  
> "src/mem/ruby/network/simple/PerfectSwitch.cc"
> 
> 
> Diffs
> -
> 
>   SConstruct be4990a2c764 
>   build_opts/ALPHA_Network_Topaz_test PRE-CREATION 
>   build_opts/ALPHA_directory_topaz PRE-CREATION 
>   build_opts/ALPHA_token_topaz PRE-CREATION 
>   configs/ruby/Ruby.py be4990a2c764 
>   src/mem/ruby/buffers/MessageBuffer.hh be4990a2c764 
>   src/mem/ruby/buffers/MessageBuffer.cc be4990a2c764 
>   src/mem/ruby/network/Network.hh be4990a2c764 
>   src/mem/ruby/network/Topology.cc be4990a2c764 
>   src/mem/ruby/network/topaz/SConscript PRE-CREATION 
>   src/mem/ruby/network/topaz/SConsopts PRE-CREATION 
>   src/mem/ruby/network/topaz/TopazNetwork.hh PRE-CREATION 
>   src/mem/ruby/network/topaz/TopazNetwork.cc PRE-CREATION 
>   src/mem/ruby/network/topaz/TopazNetwork.py PRE-CREATION 
>   src/mem/ruby/network/topaz/TopazSwitch.hh PRE-CREATION 
>   src/mem/ruby/network/topaz/TopazSwitch.cc PRE-CREATION 
>   src/mem/ruby/network/topaz/TopazSwitchFlow.hh PRE-CREATION 
>   src/mem/ruby/network/topaz/TopazSwitchFlow.cc PRE-CREATION 
>   src/mem/ruby/profiler/Profiler.cc be4990a2c764 
> 
> Diff: http://reviews.gem5.org/r/1095/diff/
> 
> 
> Testing
> ---
> 
> Regression test seems to be working for the ruby protocols provided 
> 
> 
> Thanks,
> 
> Valentin Puente
> 
>

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Re: [gem5-dev] Review Request: Garnet: Stats at vnet granularity + code cleanup

2012-03-19 Thread Brad Beckmann


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Ship it!


Other than my minor comment, this looks good to me.


src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc


Minor comment: this seems like a needless change and is in constrast with 
the coding style used in this file.


- Brad Beckmann


On March 19, 2012, 12:28 p.m., Tushar Krishna wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/1106/
> ---
> 
> (Updated March 19, 2012, 12:28 p.m.)
> 
> 
> Review request for Default, Nilay Vaish and Brad Beckmann.
> 
> 
> Description
> ---
> 
> Garnet: Stats at vnet granularity + code cleanup
> 
> This patch
> (1) Moves redundant code from fixed and flexible networks to 
> BaseGarnetNetwork.
> (2) Prints network stats at vnet granularity.
> 
> 
> Diffs
> -
> 
>   src/mem/ruby/network/garnet/BaseGarnetNetwork.hh 75b524b64c28 
>   src/mem/ruby/network/garnet/BaseGarnetNetwork.cc 75b524b64c28 
>   src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.hh 75b524b64c28 
>   src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc 75b524b64c28 
>   src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc 
> 75b524b64c28 
>   src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.hh 75b524b64c28 
>   src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc 75b524b64c28 
>   src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc 
> 75b524b64c28 
> 
> Diff: http://reviews.gem5.org/r/1106/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Tushar Krishna
> 
>

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[gem5-dev] Review Request: Garnet: Stats at vnet granularity + code cleanup

2012-03-19 Thread Tushar Krishna


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---

Review request for Default, Nilay Vaish and Brad Beckmann.


Description
---

Garnet: Stats at vnet granularity + code cleanup

This patch
(1) Moves redundant code from fixed and flexible networks to BaseGarnetNetwork.
(2) Prints network stats at vnet granularity.


Diffs
-

  src/mem/ruby/network/garnet/BaseGarnetNetwork.hh 75b524b64c28 
  src/mem/ruby/network/garnet/BaseGarnetNetwork.cc 75b524b64c28 
  src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.hh 75b524b64c28 
  src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc 75b524b64c28 
  src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc 75b524b64c28 
  src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.hh 75b524b64c28 
  src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc 75b524b64c28 
  src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc 
75b524b64c28 

Diff: http://reviews.gem5.org/r/1106/diff/


Testing
---


Thanks,

Tushar Krishna

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Re: [gem5-dev] Review Request: inorder: add timing translation

2012-03-19 Thread Erik Tomusk



> On March 8, 2012, 9:14 a.m., Ali Saidi wrote:
> > src/cpu/inorder/cpu.cc, line 1821
> > 
> >
> > what about doing the access?

I think it's meant to try the cache access again once the translation is done. 
There should be a doCacheAccess(WholeTranslationState *) function that will 
doCacheAccess(DynInstPtr, uint64_t*, CacheReqPtr) based on the values stored in 
WholeTranslationState. Is that right, Korey?


- Erik


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On March 8, 2012, 7:42 a.m., Korey Sewell wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/1089/
> ---
> 
> (Updated March 8, 2012, 7:42 a.m.)
> 
> 
> Review request for Default.
> 
> 
> Description
> ---
> 
> inorder: add timing translation
> This is Erik Tomusk's patch to add timing translation to InOrder. It's the 
> next step
> in getting InOrder to work for ARM.
> 
> 
> Diffs
> -
> 
>   src/cpu/inorder/cpu.hh 87cafa076695 
>   src/cpu/inorder/cpu.cc 87cafa076695 
>   src/cpu/inorder/resources/cache_unit.cc 87cafa076695 
>   src/cpu/inorder/resources/inorder_translation.hh PRE-CREATION 
> 
> Diff: http://reviews.gem5.org/r/1089/diff/
> 
> 
> Testing
> ---
> 
> This is not fully tested yet but a work in progress.
> 
> 
> Thanks,
> 
> Korey Sewell
> 
>

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Re: [gem5-dev] Review Request: inorder: add timing translation

2012-03-19 Thread Erik Tomusk


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src/cpu/inorder/cpu.cc


Can inst be of type InOrderDynInst? Is WholeTranslationState only used on 
CPUs that use InOrderDynInst?


- Erik Tomusk


On March 8, 2012, 7:42 a.m., Korey Sewell wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/1089/
> ---
> 
> (Updated March 8, 2012, 7:42 a.m.)
> 
> 
> Review request for Default.
> 
> 
> Description
> ---
> 
> inorder: add timing translation
> This is Erik Tomusk's patch to add timing translation to InOrder. It's the 
> next step
> in getting InOrder to work for ARM.
> 
> 
> Diffs
> -
> 
>   src/cpu/inorder/cpu.hh 87cafa076695 
>   src/cpu/inorder/cpu.cc 87cafa076695 
>   src/cpu/inorder/resources/cache_unit.cc 87cafa076695 
>   src/cpu/inorder/resources/inorder_translation.hh PRE-CREATION 
> 
> Diff: http://reviews.gem5.org/r/1089/diff/
> 
> 
> Testing
> ---
> 
> This is not fully tested yet but a work in progress.
> 
> 
> Thanks,
> 
> Korey Sewell
> 
>

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Re: [gem5-dev] Debugging New Translating Ports / PortProxy

2012-03-19 Thread Andreas Hansson

As we already saw with one of the Ruby regressions, the changes in the port 
proxies did expose similar issues already (see changeset f2ac0bca75df). In 
short, I am fairly confident that the port proxies are not the source of the 
problem.

I think it boils down to the access permissions in Ruby, but wouldn't know 
how/what to change. Nilay?

Andreas


-Original Message-
From: gem5-dev-boun...@gem5.org [mailto:gem5-dev-boun...@gem5.org] On Behalf Of 
Gabe Black
Sent: 19 March 2012 06:42
To: gem5-dev@gem5.org
Subject: Re: [gem5-dev] Debugging New Translating Ports / PortProxy

Somewhat tangential to the problem you're having, the SE/FS merge and
the change to how ports work were pretty much entirely unrelated, they
just happened to go in around the same time. What you describe sounds
like it could be from the ports change, but, at least from what you've
described, I don't think the SE/FS merge is a factor.

Gabe

On 03/18/12 14:54, Nilay Vaish wrote:
> On Fri, 16 Mar 2012, Joel Hestness wrote:
>
>> Hey guys,
>>  I just updated my repo to the gem5 head, and I'm trying to merge my old
>> patches.  It looks like the TranslatingPort that used to be the O3CPU
>> funcport has changed, and I run into a fatal when trying to run the new
>> code.
>>
>>  I'm trying to run simulation with x86 O3CPU, full_system=False (SE
>> mode),
>> and using a Ruby cache hierarchy.  With the old code, the O3CPU would
>> simply use the funcport (before the FS/SE merge) to read from the
>> physmem
>> directly (::aside:: this already confuses me, since if the data is
>> modified
>> in a cache, shouldn't that data be read?).  With the updated gem5
>> code, the
>> functional access uses the O3CPU's data port, which is connected to a
>> Ruby
>> sequencer (more as I would expect), which checks to see if the data
>> is in a
>> cache before grabbing the data for the read.
>
> I think the first thing that you need look at is as to why the O3 CPU
> is trying to make functional accesses. I rolled back the repo to look
> if there is any entity by the name funcport, but grep did not provide
> any results. Which code are you referring to?
>
>>
>>  The problem that I'm running into is in RubyPort.cc: When the
>> functional
>> read gets to the cache hierarchy, Ruby finds that the
>> AccessPermission on
>> the data it's looking for is in the Busy state (in
>> RubyPort::M5Port::doFunctionalRead(PacketPtr pkt) the num_busy value
>> is 2
>> since the data is currently in the process of being transferred up the
>> cache hierarchy in a timing request).  Because it's in the busy state,
>> doFunctionalRead returns false, which
>> causes RubyPort::M5Port::recvFunctional to fall into the if-statement
>> checking if the access failed (line 445).
>>
>>  In this case, couldn't the functional read just grab the data from
>> memory?  If so, shouldn't there be better signalling between the
>> doFunctional functions and recvFunctional in RubyPort::M5Port to
>> indicate the access permissions on the data?  Suggestions on how this
>> might
>> be fixed?
>
> It is possible that the data in the memory is not up to date, as you
> mentioned before. In fact, busy = 2 means that there are two
> controllers in transient states, so the data might be in the network.
> You might want to look at the access permissions of the transient
> states and decide if it would be safe to read data from one of the
> controllers. If it is, then you can change the access permissions
> accordingly.
>
> --
> Nilay
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Re: [gem5-dev] Review Request: inorder: add timing translation

2012-03-19 Thread Erik Tomusk

There are a couple of compile errors with this patch, so I will try to 
sort those out before I get to the comments.


When I need to update the patch, do I just hg postreview -u -e 1089 -o? 
I'm still new to this.


I have a small patch that fixes an Alpha compile error caused by this 
patch. Should I merge that patch into this one or submit it separately, 
given that the current patch is intended for ARM?


Thanks,
Erik

On 08/03/12 17:14, Ali Saidi wrote:

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src/cpu/inorder/cpu.cc


 should you still get the fault if it's a prefetch?



src/cpu/inorder/cpu.cc


 what about doing the access?



src/cpu/inorder/resources/cache_unit.cc


 probably should delete it then


- Ali Saidi


On March 8, 2012, 7:42 a.m., Korey Sewell wrote:

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---

(Updated March 8, 2012, 7:42 a.m.)


Review request for Default.


Description
---

inorder: add timing translation
This is Erik Tomusk's patch to add timing translation to InOrder. It's the next 
step
in getting InOrder to work for ARM.


Diffs
-

   src/cpu/inorder/cpu.hh 87cafa076695
   src/cpu/inorder/cpu.cc 87cafa076695
   src/cpu/inorder/resources/cache_unit.cc 87cafa076695
   src/cpu/inorder/resources/inorder_translation.hh PRE-CREATION

Diff: http://reviews.gem5.org/r/1089/diff/


Testing
---

This is not fully tested yet but a work in progress.


Thanks,

Korey Sewell



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Re: [gem5-dev] Review Request: Scons: Remove Werror=False in SConscript files

2012-03-19 Thread Steve Reinhardt


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Ship it!


Ship It!

- Steve Reinhardt


On March 6, 2012, 9:18 a.m., Andreas Hansson wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/1082/
> ---
> 
> (Updated March 6, 2012, 9:18 a.m.)
> 
> 
> Review request for Default.
> 
> 
> Description
> ---
> 
> Scons: Remove Werror=False in SConscript files
> 
> This patch removes the overriding of "-Werror" in a handful of
> cases. The code compiles with gcc 4.6.3 and clang 3.0 without any
> warnings, and thus without any errors. There are no functional changes
> introduced by this patch. In the future, rather than ypassing
> "-Werror", address the warnings.
> 
> 
> Diffs
> -
> 
>   src/cpu/testers/networktest/SConscript b5d80698c948 
>   src/mem/ruby/common/SConscript b5d80698c948 
>   src/mem/ruby/network/garnet/fixed-pipeline/SConscript b5d80698c948 
> 
> Diff: http://reviews.gem5.org/r/1082/diff/
> 
> 
> Testing
> ---
> 
> util/regress all passing (disregarding t1000 and eio)
> 
> 
> Thanks,
> 
> Andreas Hansson
> 
>

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[gem5-dev] changeset in gem5: gcc: Clean-up of non-C++0x compliant code, fi...

2012-03-19 Thread Andreas Hansson

changeset 75b524b64c28 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=75b524b64c28
description:
gcc: Clean-up of non-C++0x compliant code, first steps

This patch cleans up a number of minor issues aiming to get closer to
compliance with the C++0x standard as interpreted by gcc and clang
(compile with std=c++0x and -pedantic-errors). In particular, the
patch cleans up enums where the last item was succeded by a comma,
namespaces closed by a curcly brace followed by a semi-colon, and the
use of the GNU-extension typeof (replaced by templated functions). It
does not address variable-length arrays, zero-size arrays, anonymous
structs, range expressions in switch statements, and the use of long
long. The generated CPU code also has a large number of issues that
remain to be fixed, mainly related to overflows in implicit constant
conversion (due to shifts).

diffstat:

 src/arch/alpha/isa/main.isa |2 +-
 src/arch/alpha/isa_traits.hh|2 +-
 src/arch/alpha/types.hh |2 +-
 src/arch/arm/intregs.hh |2 +-
 src/arch/arm/isa/templates/neon.isa |   18 ++-
 src/arch/arm/linux/atag.hh  |2 +-
 src/arch/arm/miscregs.cc|2 +-
 src/arch/arm/miscregs.hh|2 +-
 src/arch/arm/nativetrace.cc |2 +-
 src/arch/arm/pagetable.hh   |2 +-
 src/arch/arm/predecoder.hh  |2 +-
 src/arch/arm/table_walker.hh|2 +-
 src/arch/arm/utility.hh |2 +-
 src/arch/arm/vtophys.hh |2 +-
 src/arch/x86/bios/e820.hh   |2 +-
 src/arch/x86/emulenv.hh |2 +-
 src/arch/x86/faults.hh  |2 +-
 src/arch/x86/isa/macroop.isa|2 +-
 src/arch/x86/isa_traits.hh  |2 +-
 src/arch/x86/locked_mem.hh  |2 +-
 src/arch/x86/mmapped_ipr.hh |2 +-
 src/arch/x86/nativetrace.cc |2 +-
 src/arch/x86/predecoder.hh  |2 +-
 src/arch/x86/regs/float.hh  |2 +-
 src/arch/x86/regs/int.hh|2 +-
 src/arch/x86/regs/misc.hh   |2 +-
 src/arch/x86/regs/segment.hh|2 +-
 src/arch/x86/tlb.cc |2 +-
 src/arch/x86/types.hh   |2 +-
 src/arch/x86/utility.hh |2 +-
 src/arch/x86/vtophys.hh |2 +-
 src/base/bitmap.cc  |   12 +-
 src/base/callback.cc|2 +-
 src/base/range.cc   |   20 +-
 src/base/range_map.hh   |3 +-
 src/base/str.cc |   22 ++--
 src/base/vnc/convert.hh |2 +-
 src/cpu/base_dyn_inst.hh|2 +-
 src/cpu/exetrace.cc |2 +-
 src/cpu/inorder/inorder_dyn_inst.hh |2 +-
 src/cpu/inorder/pipeline_traits.hh  |2 +-
 src/cpu/inorder/resource.hh |2 +-
 src/cpu/inteltrace.cc   |2 +-
 src/cpu/o3/dyn_inst.hh  |2 +-
 src/cpu/o3/thread_context.hh|2 +-
 src/cpu/simple_thread.hh|4 +-
 src/cpu/static_inst.hh  |2 +-
 src/cpu/thread_context.hh   |4 +-
 src/cpu/thread_state.hh |4 +-
 src/dev/i8254xGBe.hh|2 +-
 src/dev/ide_atareg.h|2 +-
 src/dev/sinicreg.hh |  190 ++--
 src/python/m5/params.py |2 +-
 src/sim/byteswap.hh |8 +-
 src/sim/eventq.hh   |2 +-
 src/sim/serialize.hh|   15 ++-
 56 files changed, 204 insertions(+), 186 deletions(-)

diffs (truncated from 986 to 300 lines):

diff -r bba76d164f9e -r 75b524b64c28 src/arch/alpha/isa/main.isa
--- a/src/arch/alpha/isa/main.isa   Mon Mar 19 06:35:04 2012 -0400
+++ b/src/arch/alpha/isa/main.isa   Mon Mar 19 06:36:09 2012 -0400
@@ -222,7 +222,7 @@
 /// this class and derived classes.  Maybe these should really
 /// live here and not in the AlphaISA namespace.
 enum DependenceTags {
-FP_Base_DepTag = AlphaISA::FP_Base_DepTag,
+FP_Base_DepTag = AlphaISA::FP_Base_DepTag
 };
 
 /// Constructor.
diff -r bba76d164f9e -r 75b524b64c28 src/arch/alpha/isa_traits.hh
--- a/src/arch/alpha/isa_traits.hh  Mon Mar 19 06:35:04 2012 -0400
+++ b/src/arch/alpha/isa_traits.hh  Mon Mar 19 06:36:09 2012 -0400
@@ -119,7 +119,7 @@
 MachineBytes = 8,
 WordBytes = 4,
 HalfwordBytes = 2,
-ByteBytes = 1,
+ByteBytes = 1
 };
 
 // return a no-op instruction... used for instruction fetch faults
diff -r bba76d164f9e -r 75b524b64c28 src/arch/alpha/types.hh
--- a/src/arch/alpha/types.hh   Mon Mar 19 06:35:04 2012 -0400
+++ b/src/arch/alpha/types.hh   Mon Mar 19 06:36:09 2012 -0400
@@ -48,7 +48,7 @@
 {
 ANNOTE_NONE = 0,
 // An impossible number for instruction annotations
-

Re: [gem5-dev] Review Request: Scons: Remove Werror=False in SConscript files

2012-03-19 Thread Andreas Hansson



> On March 9, 2012, 11:36 a.m., Steve Reinhardt wrote:
> > So did these files get changed to remove the warning?  Or are there 
> > warnings with other versions of gcc?  I'm curious about the history here... 
> > it seems a little dangerous to take these off unless we know that the 
> > reasons for having them there have been addresses.
> 
> Andreas Hansson wrote:
> There are no warnings with any version of gcc >= 4.2 at least. That's all 
> I've been able to test. 
> 
> Was a -Wno- flag added at some point perhaps? I 
> cannot imagine that any older version of gcc would have problems when the 
> more recent ones don't. Plus, if they do, then let's fix the code rather than 
> disable -Werror. Agreed?

Any additional thoughts on this one?


- Andreas


---
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/1082/#review2293
---


On March 6, 2012, 9:18 a.m., Andreas Hansson wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/1082/
> ---
> 
> (Updated March 6, 2012, 9:18 a.m.)
> 
> 
> Review request for Default.
> 
> 
> Description
> ---
> 
> Scons: Remove Werror=False in SConscript files
> 
> This patch removes the overriding of "-Werror" in a handful of
> cases. The code compiles with gcc 4.6.3 and clang 3.0 without any
> warnings, and thus without any errors. There are no functional changes
> introduced by this patch. In the future, rather than ypassing
> "-Werror", address the warnings.
> 
> 
> Diffs
> -
> 
>   src/cpu/testers/networktest/SConscript b5d80698c948 
>   src/mem/ruby/common/SConscript b5d80698c948 
>   src/mem/ruby/network/garnet/fixed-pipeline/SConscript b5d80698c948 
> 
> Diff: http://reviews.gem5.org/r/1082/diff/
> 
> 
> Testing
> ---
> 
> util/regress all passing (disregarding t1000 and eio)
> 
> 
> Thanks,
> 
> Andreas Hansson
> 
>

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[gem5-dev] changeset in gem5: clang: Fix recently introduced clang compilat...

2012-03-19 Thread Andreas Hansson

changeset bba76d164f9e in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=bba76d164f9e
description:
clang: Fix recently introduced clang compilation errors

This patch makes the code compile with clang 2.9 and 3.0 again by
making two very minor changes. Firt, it maintains a strict typing in
the forward declaration of the BaseCPUParams. Second, it adds a
FullSystemInt flag of the type unsigned int next to the boolean
FullSystem flag. The FullSystemInt variable can be used in
decode-statements (expands to switch statements) in the instruction
decoder.

diffstat:

 src/arch/alpha/isa/decoder.isa|   6 +++---
 src/arch/mips/isa/decoder.isa |   4 ++--
 src/arch/x86/isa/decoder/one_byte_opcodes.isa |   2 +-
 src/arch/x86/isa/decoder/two_byte_opcodes.isa |   4 ++--
 src/cpu/base.hh   |   2 +-
 src/sim/full_system.hh|  12 
 src/sim/root.cc   |   2 ++
 7 files changed, 23 insertions(+), 9 deletions(-)

diffs (136 lines):

diff -r 7d74a97c525f -r bba76d164f9e src/arch/alpha/isa/decoder.isa
--- a/src/arch/alpha/isa/decoder.isaMon Mar 19 06:34:02 2012 -0400
+++ b/src/arch/alpha/isa/decoder.isaMon Mar 19 06:35:04 2012 -0400
@@ -805,14 +805,14 @@
 0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp);
 }
 
-0xe000: decode FullSystem {
+0xe000: decode FullSystemInt {
 0: FailUnimpl::rc_se();
 default: BasicOperate::rc({{
 Ra = IntrFlag;
 IntrFlag = 0;
 }}, IsNonSpeculative, IsUnverifiable);
 }
-0xf000: decode FullSystem {
+0xf000: decode FullSystemInt {
 0: FailUnimpl::rs_se();
 default: BasicOperate::rs({{
 Ra = IntrFlag;
@@ -821,7 +821,7 @@
 }
 }
 
-0x00: decode FullSystem {
+0x00: decode FullSystemInt {
 0: decode PALFUNC {
 format EmulatedCallPal {
 0x00: halt ({{
diff -r 7d74a97c525f -r bba76d164f9e src/arch/mips/isa/decoder.isa
--- a/src/arch/mips/isa/decoder.isa Mon Mar 19 06:34:02 2012 -0400
+++ b/src/arch/mips/isa/decoder.isa Mon Mar 19 06:35:04 2012 -0400
@@ -163,7 +163,7 @@
 format BasicOp {
 0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }});
 0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }});
-0x4: decode FullSystem {
+0x4: decode FullSystemInt {
 0: syscall_se({{ xc->syscall(R2); }},
 IsSerializeAfter, IsNonSpeculative);
 default: syscall({{ fault = new SystemCallFault(); }});
@@ -2431,7 +2431,7 @@
 }
 }
 0x3: decode OP default FailUnimpl::rdhwr() {
-0x0: decode FullSystem {
+0x0: decode FullSystemInt {
 0: decode RD {
 29: BasicOp::rdhwr_se({{ Rt = TpValue; }});
 }
diff -r 7d74a97c525f -r bba76d164f9e 
src/arch/x86/isa/decoder/one_byte_opcodes.isa
--- a/src/arch/x86/isa/decoder/one_byte_opcodes.isa Mon Mar 19 06:34:02 
2012 -0400
+++ b/src/arch/x86/isa/decoder/one_byte_opcodes.isa Mon Mar 19 06:35:04 
2012 -0400
@@ -394,7 +394,7 @@
 default: Inst::RET_FAR();
 }
 0x4: int3();
-0x5: decode FullSystem default int_Ib() {
+0x5: decode FullSystemInt default int_Ib() {
 0: decode IMMEDIATE {
 // Really only the LSB matters, but the predecoder
 // will sign extend it, and there's no easy way to
diff -r 7d74a97c525f -r bba76d164f9e 
src/arch/x86/isa/decoder/two_byte_opcodes.isa
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa Mon Mar 19 06:34:02 
2012 -0400
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa Mon Mar 19 06:35:04 
2012 -0400
@@ -216,7 +216,7 @@
 default: Inst::UD2();
 }
 }
-0x05: decode FullSystem {
+0x05: decode FullSystemInt {
 0: SyscallInst::syscall('xc->syscall(Rax)',
 IsSyscall, IsNonSpeculative, IsSerializeAfter);
 default: decode MODE_MODE {
@@ -398,7 +398,7 @@
 0x1: Inst::RDTSC();
 0x2: Inst::RDMSR();
 0x3: rdpmc();
-0x4: decode FullSystem {
+0x4: decode FullSystemInt {
 0: SyscallInst::sysenter('xc->syscall(Rax)',
 IsSyscall, IsNonSpeculative, IsSerializeAfter);
 default: sysenter();
diff -r 7d74a97c525f -r bba76d164f9e src/cpu/base.hh
--- a/src/cpu/base.hh   Mon Mar

[gem5-dev] changeset in gem5: scripts: Fix to ensure that port connection c...

2012-03-19 Thread Andreas Hansson

changeset 7d74a97c525f in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=7d74a97c525f
description:
scripts: Fix to ensure that port connection count is always set

This patch ensures that the port connection count is set to zero in 
those
cases when the port is not connected.

diffstat:

 src/python/m5/SimObject.py |  5 ++---
 1 files changed, 2 insertions(+), 3 deletions(-)

diffs (15 lines):

diff -r 0541a014b811 -r 7d74a97c525f src/python/m5/SimObject.py
--- a/src/python/m5/SimObject.pyFri Mar 16 07:47:03 2012 -0500
+++ b/src/python/m5/SimObject.pyMon Mar 19 06:34:02 2012 -0400
@@ -993,9 +993,8 @@
 port_names.sort()
 for port_name in port_names:
 port = self._port_refs.get(port_name, None)
-if port != None:
-setattr(cc_params, 'port_' + port_name + '_connection_count',
-len(port))
+setattr(cc_params, 'port_' + port_name + '_connection_count',
+len(port) if port != None else 0)
 self._ccParams = cc_params
 return self._ccParams
 
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[gem5-dev] Cron /z/m5/regression/do-regression quick

2012-03-19 Thread Cron Daemon

* build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic 
FAILED!
* build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing 
FAILED!
* build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp 
FAILED!
* build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp 
FAILED!
scons: `build/ALPHA_MOESI_hammer/gem5.debug' is up to date.
scons: `build/ALPHA_MESI_CMP_directory/gem5.debug' is up to date.
scons: `build/ALPHA_MOESI_CMP_directory/gem5.debug' is up to date.
scons: `build/ALPHA_MOESI_CMP_token/gem5.debug' is up to date.
scons: `build/MIPS/gem5.debug' is up to date.
scons: `build/POWER/gem5.debug' is up to date.
scons: `build/SPARC/gem5.debug' is up to date.
scons: `build/X86/gem5.debug' is up to date.
scons: `build/ARM/gem5.debug' is up to date.
scons: `build/ALPHA_MOESI_hammer/gem5.fast' is up to date.
scons: `build/ALPHA_MESI_CMP_directory/gem5.fast' is up to date.
scons: `build/ALPHA_MOESI_CMP_directory/gem5.fast' is up to date.
scons: `build/ALPHA_MOESI_CMP_token/gem5.fast' is up to date.
scons: `build/MIPS/gem5.fast' is up to date.
scons: `build/POWER/gem5.fast' is up to date.
scons: `build/SPARC/gem5.fast' is up to date.
scons: `build/X86/gem5.fast' is up to date.
scons: `build/ARM/gem5.fast' is up to date.
scons: `build/ALPHA_MOESI_hammer/tests/opt/quick/fs' is up to date.
scons: `build/ALPHA_MESI_CMP_directory/tests/opt/quick/fs' is up to date.
scons: `build/ALPHA_MOESI_CMP_directory/tests/opt/quick/fs' is up to date.
scons: `build/ALPHA_MOESI_CMP_token/tests/opt/quick/fs' is up to date.
scons: `build/MIPS/tests/opt/quick/fs' is up to date.
scons: `build/POWER/tests/opt/quick/fs' is up to date.
scons: *** Error 1
scons: *** Error 1
scons: *** Error 1
scons: *** Error 1
* 
build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer
 passed.
* 
build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer
 passed.
* 
build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer
 passed.
* 
build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer
 passed.
* 
build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory
 passed.
* 
build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory
 passed.
* 
build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory
 passed.
* 
build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory
 passed.
* 
build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory
 passed.
* 
build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory
 passed.
* 
build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory
 passed.
* 
build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory
 passed.
* 
build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token
 passed.
* 
build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token
 passed.
* 
build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token
 passed.
* 
build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token
 passed.
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing passed.
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing passed.
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing passed.
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby 
passed.
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic passed.
* build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing passed.
* build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic passed.
* build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing passed.
* build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic passed.
* build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing passed.
* build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby 
passed.
* build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/inorder-timing 
passed.
* build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing passed.
* build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic 
passed.
* build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing 
passed.
* 
build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
 passed.
* 
build/S

[gem5-dev] changeset in gem5: Garnet: Stats at vnet granularity + code cleanup

Re: [gem5-dev] Review Request: Interface to integrate TOPAZ network simulator (http://code.google.com/p/tpzsimul/) within GEM5-RUBY

Re: [gem5-dev] Review Request: Garnet: Stats at vnet granularity + code cleanup

[gem5-dev] Review Request: Garnet: Stats at vnet granularity + code cleanup

Re: [gem5-dev] Review Request: inorder: add timing translation

Re: [gem5-dev] Review Request: inorder: add timing translation

Re: [gem5-dev] Debugging New Translating Ports / PortProxy

Re: [gem5-dev] Review Request: inorder: add timing translation

Re: [gem5-dev] Review Request: Scons: Remove Werror=False in SConscript files

[gem5-dev] changeset in gem5: gcc: Clean-up of non-C++0x compliant code, fi...

Re: [gem5-dev] Review Request: Scons: Remove Werror=False in SConscript files

[gem5-dev] changeset in gem5: clang: Fix recently introduced clang compilat...

[gem5-dev] changeset in gem5: scripts: Fix to ensure that port connection c...

[gem5-dev] Cron /z/m5/regression/do-regression quick

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