> On March 8, 2012, 9:14 a.m., Ali Saidi wrote: > > src/cpu/inorder/cpu.cc, line 1821 > > <http://reviews.gem5.org/r/1089/diff/3/?file=23972#file23972line1821> > > > > what about doing the access?
I think it's meant to try the cache access again once the translation is done. There should be a doCacheAccess(WholeTranslationState *) function that will doCacheAccess(DynInstPtr, uint64_t*, CacheReqPtr) based on the values stored in WholeTranslationState. Is that right, Korey? - Erik ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1089/#review2285 ----------------------------------------------------------- On March 8, 2012, 7:42 a.m., Korey Sewell wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1089/ > ----------------------------------------------------------- > > (Updated March 8, 2012, 7:42 a.m.) > > > Review request for Default. > > > Description > ------- > > inorder: add timing translation > This is Erik Tomusk's patch to add timing translation to InOrder. It's the > next step > in getting InOrder to work for ARM. > > > Diffs > ----- > > src/cpu/inorder/cpu.hh 87cafa076695 > src/cpu/inorder/cpu.cc 87cafa076695 > src/cpu/inorder/resources/cache_unit.cc 87cafa076695 > src/cpu/inorder/resources/inorder_translation.hh PRE-CREATION > > Diff: http://reviews.gem5.org/r/1089/diff/ > > > Testing > ------- > > This is not fully tested yet but a work in progress. > > > Thanks, > > Korey Sewell > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
