Re: [gem5-dev] include order style checker bug

[Gabe Black]

Here's another potentially related bug. There was an extra space between
the final header and the using at the top of a .cc, and the style fixer
decided to move the include of the corresponding .hh from the top where it
belonged down into the list of includes in alphabetic order. It still
complained about the headers after, but when told to fix it it made no
changes. It seems the fixer doesn't always recognize when the
.hh corresponding to a .cc needs to be at the top.

Gabe

On Thu, May 2, 2019 at 10:50 PM Gabe Black  wrote:

> Hey folks. I just ran into a bug in the style checker/fixer, and since I
> wanted to make sure I kept track of those so they can be fixed I thought I
> would describe it here for the record. I have a cc file which had a single
> system include (#include ) and the include for its .hh file
> (#include "base/loader/loader.hh"), but they were in the wrong order,
> system and then .hh. The style checker correctly complained about the order
> and offered to fix it, but when I said yes it didn't actually change
> anything or print any messages. FYI in case somebody wants to investigate.
>
> Gabe
>
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] include order style checker bug

[Gabe Black]

Hey folks. I just ran into a bug in the style checker/fixer, and since I
wanted to make sure I kept track of those so they can be fixed I thought I
would describe it here for the record. I have a cc file which had a single
system include (#include ) and the include for its .hh file
(#include "base/loader/loader.hh"), but they were in the wrong order,
system and then .hh. The style checker correctly complained about the order
and offered to fix it, but when I said yes it didn't actually change
anything or print any messages. FYI in case somebody wants to investigate.

Gabe
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in gem5/gem5[master]: arch, base, cpu, dev, mem, sim: Remove #if 0-ed out code.

[Gabe Black (Gerrit)]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18608



Change subject: arch, base, cpu, dev, mem, sim: Remove #if 0-ed out code.
..

arch, base, cpu, dev, mem, sim: Remove #if 0-ed out code.

This code will be preserved through version control, but otherwise
creates clutter and will rot in place since it's never compiled.

Change-Id: Id265f6deac445116843956ea5cf1210d8127274e
---
M src/arch/alpha/linux/system.cc
M src/arch/alpha/linux/system.hh
M src/arch/alpha/osfpal.cc
M src/base/loader/coff_sym.h
M src/base/statistics.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/fetch_impl.hh
M src/cpu/o3/inst_queue_impl.hh
M src/cpu/pred/2bit_local.cc
M src/dev/alpha/tsunami_pchip.cc
M src/dev/net/ns_gige.cc
M src/dev/net/ns_gige.hh
M src/dev/net/sinic.cc
M src/dev/storage/simple_disk.cc
M src/gpu-compute/gpu_tlb.cc
M src/kern/linux/printk.cc
M src/mem/cache/base.cc
M src/mem/cache/base.hh
M src/mem/ruby/system/RubySystem.cc
M src/sim/process.cc
20 files changed, 0 insertions(+), 434 deletions(-)



diff --git a/src/arch/alpha/linux/system.cc b/src/arch/alpha/linux/system.cc
index 33e760f..950b773 100644
--- a/src/arch/alpha/linux/system.cc
+++ b/src/arch/alpha/linux/system.cc
@@ -123,10 +123,6 @@
 #ifndef NDEBUG
 kernelPanicEvent = addKernelFuncEventOrPanic("panic");

-#if 0
-kernelDieEvent =  
addKernelFuncEventOrPanic("die_if_kernel");

-#endif
-
 #endif

 /**
diff --git a/src/arch/alpha/linux/system.hh b/src/arch/alpha/linux/system.hh
index 4f030c9..8ea387e 100644
--- a/src/arch/alpha/linux/system.hh
+++ b/src/arch/alpha/linux/system.hh
@@ -89,11 +89,6 @@
 /** Event to halt the simulator if the kernel calls panic()  */
 BreakPCEvent *kernelPanicEvent;

-#if 0
-/** Event to halt the simulator if the kernel calls die_if_kernel  */
-BreakPCEvent *kernelDieEvent;
-#endif
-
 #endif

 /**
diff --git a/src/arch/alpha/osfpal.cc b/src/arch/alpha/osfpal.cc
index 58a3d31..741189f 100644
--- a/src/arch/alpha/osfpal.cc
+++ b/src/arch/alpha/osfpal.cc
@@ -229,72 +229,6 @@
 0,  // 0xbd
 "nphalt",   // 0xbe
 "copypal",  // 0xbf
-#if 0
-0,  // 0xc0
-0,  // 0xc1
-0,  // 0xc2
-0,  // 0xc3
-0,  // 0xc4
-0,  // 0xc5
-0,  // 0xc6
-0,  // 0xc7
-0,  // 0xc8
-0,  // 0xc9
-0,  // 0xca
-0,  // 0xcb
-0,  // 0xcc
-0,  // 0xcd
-0,  // 0xce
-0,  // 0xcf
-0,  // 0xd0
-0,  // 0xd1
-0,  // 0xd2
-0,  // 0xd3
-0,  // 0xd4
-0,  // 0xd5
-0,  // 0xd6
-0,  // 0xd7
-0,  // 0xd8
-0,  // 0xd9
-0,  // 0xda
-0,  // 0xdb
-0,  // 0xdc
-0,  // 0xdd
-0,  // 0xde
-0,  // 0xdf
-0,  // 0xe0
-0,  // 0xe1
-0,  // 0xe2
-0,  // 0xe3
-0,  // 0xe4
-0,  // 0xe5
-0,  // 0xe6
-0,  // 0xe7
-0,  // 0xe8
-0,  // 0xe9
-0,  // 0xea
-0,  // 0xeb
-0,  // 0xec
-0,  // 0xed
-0,  // 0xee
-0,  // 0xef
-0,  // 0xf0
-0,  // 0xf1
-0,  // 0xf2
-0,  // 0xf3
-0,  // 0xf4
-0,  // 0xf5
-0,  // 0xf6
-0,  // 0xf7
-0,  // 0xf8
-0,  // 0xf9
-0,  // 0xfa
-0,  // 0xfb
-0,  // 0xfc
-0,  // 0xfd
-0,  // 0xfe
-0   // 0xff
-#endif
 };

 if (index > NumCodes || index < 0)
diff --git a/src/base/loader/coff_sym.h b/src/base/loader/coff_sym.h
index be06311..acca2f1 100644
--- a/src/base/loader/coff_sym.h
+++ b/src/base/loader/coff_sym.h
@@ -216,32 +216,6 @@
 #define ipdNil  -1

 /*
- * The structure of the runtime procedure descriptor created by the loader
- * for use by the static exception system.
- */
-/*
- * If 0'd out because exception_info chokes Visual C++ and because there
- * don't seem to be any references to this structure elsewhere in gdb.
- */
-#if 0
-typedef struct runtime_pdr {
-coff_addr   adr;/* memory address of start of 

Re: [gem5-dev] Continuous integration is live!

[Jason Lowe-Power]

Hi Giacomo,

In tests/main.py we call scons and use the current environment defaults to
build gem5. I don't know if the kokoro infrastructure supports other
compilers. This might be something that Rahul can address.

I'm also not sure if we can find a way to run more compilations in parallel
on Kokoro. I'm happy to refactor the test scripts to do this. However, as
it is, we are currently compiling at least 4 binaries mostly sequentially,
which is making the testing take a significant amount of time. If we add
more compilers (and more Ruby protocols), this is going to begin to get out
of hand. It would also be good to compile .fast, .opt, and .debug, but I
believe we're only compiling .opt right now.

Cheers,
Jason

On Thu, May 2, 2019 at 5:53 AM Giacomo Travaglini <
giacomo.travagl...@arm.com> wrote:

> Hi Jason,
>
> I understand; Another thing I would like to ask:
>
> Which script is building gem5 in jenkins? Ideally it would be nice to
> build with BOTH gcc and clang (so that we avoid
> periodic "fix clang build" patches. I would also make the version
> configurable/visible from the script so that
> we can track changes in compiler support and people can compare failures
> in case they managed to build
> seamlessly on their local workspace
>
> Giacomo
> --
> *From:* Jason Lowe-Power 
> *Sent:* 26 April 2019 17:49
> *To:* Giacomo Travaglini
> *Cc:* gem5 Developer List
> *Subject:* Re: [gem5-dev] Continuous integration is live!
>
> Hi Giacomo,
>
> You *do* have permission :). Anyone can modify tests/jenkins/presubmit.cfg
> and presubmit.sh. In fact, if you look at the history of the presubmit.sh,
> it *was* running the old tests. See
> https://gem5-review.googlesource.com/c/testing/jenkins-gem5-prod/+/18028,
> for instance.
>
> The problem is that we can't distribute most of the binaries (e.g., SPEC
> binaries). We could probably upload them to a private location on the
> Google Cloud and have jenkins consume them that way, but I believe that
> will be more work than it's worth.
>
> I personally believe that putting effort into porting tests is more worth
> everyone's time than trying to get the old tests to run, but that's just
> my opinion. I'm happy to merge changes to run the old tests. I personally
> believe we should only merge tests into the verification tester which
> everyone can run locally, but I'm open to proprietary tests, especially in
> the short term if we have a plan to make them not proprietary.
>
> Cheers,
> Jason
>
> On Fri, Apr 26, 2019 at 9:36 AM Giacomo Travaglini <
> giacomo.travagl...@arm.com> wrote:
>
> Hi Jason,
>
> It's really amazing that we have a testing framework in place, thanks for
> your effort!
> At the moment as far as I can tell we are only running tests registered
> within the new
> testing library.
>
> I was wondering if we could temporarily enable the system to run legacy
> quick regressions as well,
> while waiting for porting those to the new library. I guess it is
> something that shouldn't require a lot of work
>
> (just calling .util/regress I guess)
>
> I am saying this since a patch recently merged broke some syscall
> emulation tests and I think it would
> be beneficial for us to run the entire test suite straightaway while
> porting tests manually.
> I could even handle it myself if I had permission to configure the system.
>
> Let me know your thoughts,
>
> Giacomo
>
> --
> *From:* gem5-dev  on behalf of Jason
> Lowe-Power 
> *Sent:* 16 April 2019 16:30
> *To:* gem5 Developer List; Rahul Thakur
> *Subject:* [gem5-dev] Continuous integration is live!
>
> Hi all,
>
> We now have initial support for continuous integration testing! We should
> all thank Google for donating the CPU time and infrastructure to run these
> tests. Specifically, Rahul Thakur has been incredibly helpful for the past
> two years in getting this off the ground. Thanks, Rahul and the rest of the
> team at Google who has been helping us set this up!
>
> Now, if you submit a patch to gerrit and receive a maintainer +1, "kokoro"
> will kick off a build / test of gem5. Once that is complete, you will
> receive a verified +1. If it fails, you will receive a verified -1. The
> logs can be viewed by anyone once the job is completed by following the
> link posted by kokoro (the https://source.cloud.google.com, not the sponge
> link). You can see an example on a patch I recently submitted here:
> https://gem5-review.googlesource.com/c/public/gem5/+/18068. Note that the
> tests take a couple of hours to run. However, I believe there is no limit
> to the number of different changes that can be tested at the same time.
>
> Soon, we are going to enable commit gating with the verified +1 tag. I.e.,
> you will have to pass the continuous integration tests before you can
> commit your code.
>
> Note that this is using the "new" testing infrastructure. You can run this
> locally by running "./main.py" in the tests directory. More information
> 

[gem5-dev] Change in gem5/gem5[master]: mem-cache: Support for page crossing prefetches

[Javier Bueno Hedo (Gerrit)]

Hello Andreas Sandberg, Daniel Carvalho, Giacomo Travaglini, Jason  
Lowe-Power, Nikos Nikoleris,


I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/14620

to look at the new patch set (#13).

Change subject: mem-cache: Support for page crossing prefetches
..

mem-cache: Support for page crossing prefetches

Prefetchers can now issue hardware prefetch requests that go beyond
the boundaries of the system page. Page crossing references will need
to look up the TLBs to be able to compute the physical address to be
prefetched.

Change-Id: Ib56374097e3b7dc87414139d210ea9272f96b06b
---
M src/arch/arm/tlb.cc
M src/mem/cache/prefetch/Prefetcher.py
M src/mem/cache/prefetch/base.cc
M src/mem/cache/prefetch/base.hh
M src/mem/cache/prefetch/queued.cc
M src/mem/cache/prefetch/queued.hh
6 files changed, 396 insertions(+), 112 deletions(-)


--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/14620
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ib56374097e3b7dc87414139d210ea9272f96b06b
Gerrit-Change-Number: 14620
Gerrit-PatchSet: 13
Gerrit-Owner: Javier Bueno Hedo 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Javier Bueno Hedo 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-CC: Ivan Pizarro 
Gerrit-MessageType: newpatchset
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in gem5/gem5[master]: mem-cache: Support for page crossing prefetches

[Javier Bueno Hedo (Gerrit)]

Hello Andreas Sandberg, Daniel Carvalho, Giacomo Travaglini, Jason  
Lowe-Power, Nikos Nikoleris,


I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/14620

to look at the new patch set (#12).

Change subject: mem-cache: Support for page crossing prefetches
..

mem-cache: Support for page crossing prefetches

Prefetchers can now issue hardware prefetch requests that go beyond
the boundaries of the system page. Page crossing references will need
to look up the TLBs to be able to compute the physical address to be
prefetched.

Change-Id: Ib56374097e3b7dc87414139d210ea9272f96b06b
---
M src/arch/arm/tlb.cc
M src/mem/cache/prefetch/Prefetcher.py
M src/mem/cache/prefetch/base.cc
M src/mem/cache/prefetch/base.hh
M src/mem/cache/prefetch/queued.cc
M src/mem/cache/prefetch/queued.hh
6 files changed, 395 insertions(+), 112 deletions(-)


--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/14620
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ib56374097e3b7dc87414139d210ea9272f96b06b
Gerrit-Change-Number: 14620
Gerrit-PatchSet: 12
Gerrit-Owner: Javier Bueno Hedo 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Javier Bueno Hedo 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-CC: Ivan Pizarro 
Gerrit-MessageType: newpatchset
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in gem5/gem5[master]: mem: Use a const T & in write<> to avoid an unnecessary copy.

[Gabe Black (Gerrit)]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18573



Change subject: mem: Use a const T & in write<> to avoid an unnecessary  
copy.

..

mem: Use a const T & in write<> to avoid an unnecessary copy.

If the type T is complex/large, the it makes sense to access it in place
and not copy it and then not modify it.

Change-Id: Idd24be4fbba636375637ff72b1ba5ee32eb76215
---
M src/mem/port_proxy.hh
1 file changed, 2 insertions(+), 2 deletions(-)



diff --git a/src/mem/port_proxy.hh b/src/mem/port_proxy.hh
index 096f826..469273f 100644
--- a/src/mem/port_proxy.hh
+++ b/src/mem/port_proxy.hh
@@ -195,7 +195,7 @@
  * Write object T to address. Writes sizeof(T) bytes.
  */
 template 
-void write(Addr address, T data) const;
+void write(Addr address, const T ) const;

 /**
  * Read sizeof(T) bytes from address and return as object T.
@@ -256,7 +256,7 @@

 template 
 void
-PortProxy::write(Addr address, T data) const
+PortProxy::write(Addr address, const T ) const
 {
 writeBlob(address, , sizeof(T));
 }

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/18573
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Idd24be4fbba636375637ff72b1ba5ee32eb76215
Gerrit-Change-Number: 18573
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
Gerrit-MessageType: newchange
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in gem5/gem5[master]: arch, base, dev, sim: Remove now unnecessary casts from PortProxy met...

[Gabe Black (Gerrit)]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18572



Change subject: arch, base, dev, sim: Remove now unnecessary casts from  
PortProxy methods.

..

arch, base, dev, sim: Remove now unnecessary casts from PortProxy methods.

Change-Id: Ia73b2d86a10d02fa09c924a4571477bb5f200eb7
---
M src/arch/alpha/linux/system.cc
M src/arch/alpha/process.cc
M src/arch/alpha/system.cc
M src/arch/arm/linux/process.cc
M src/arch/arm/process.cc
M src/arch/arm/semihosting.cc
M src/arch/generic/linux/threadinfo.hh
M src/arch/mips/process.cc
M src/arch/power/process.cc
M src/arch/sparc/process.cc
M src/arch/x86/bios/e820.cc
M src/arch/x86/bios/intelmp.cc
M src/arch/x86/bios/smbios.cc
M src/arch/x86/linux/system.cc
M src/arch/x86/process.cc
M src/arch/x86/pseudo_inst.cc
M src/arch/x86/system.cc
M src/base/loader/hex_file.cc
M src/base/remote_gdb.cc
M src/dev/alpha/tsunami_pchip.cc
M src/dev/arm/gic_v3_redistributor.cc
M src/dev/virtio/base.cc
M src/dev/virtio/base.hh
M src/sim/process_impl.hh
M src/sim/syscall_emul.hh
25 files changed, 111 insertions(+), 135 deletions(-)



diff --git a/src/arch/alpha/linux/system.cc b/src/arch/alpha/linux/system.cc
index 33e760f..9cc839e 100644
--- a/src/arch/alpha/linux/system.cc
+++ b/src/arch/alpha/linux/system.cc
@@ -90,8 +90,8 @@
  * kernel arguments directly into the kernel's memory.
  */
 virtProxy.writeBlob(CommandLine(),
-(uint8_t*)params()->boot_osflags.c_str(),
-params()->boot_osflags.length()+1);
+params()->boot_osflags.c_str(),
+params()->boot_osflags.length() + 1);

 /**
  * find the address of the est_cycle_freq variable and insert it
diff --git a/src/arch/alpha/process.cc b/src/arch/alpha/process.cc
index a7822a3..83c4c26 100644
--- a/src/arch/alpha/process.cc
+++ b/src/arch/alpha/process.cc
@@ -162,7 +162,7 @@
 else
 panic("Unknown int size");

-initVirtMem.writeBlob(memState->getStackMin(), (uint8_t*),  
intSize);

+initVirtMem.writeBlob(memState->getStackMin(), , intSize);

 copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem);
 copyStringArray(envp, envp_array_base, env_data_base, initVirtMem);
diff --git a/src/arch/alpha/system.cc b/src/arch/alpha/system.cc
index 3029429..b72821e 100644
--- a/src/arch/alpha/system.cc
+++ b/src/arch/alpha/system.cc
@@ -119,7 +119,7 @@
  * others do.)
  */
 if (consoleSymtab->findAddress("env_booted_osflags", addr)) {
-virtProxy.writeBlob(addr, (uint8_t*)params()->boot_osflags.c_str(),
+virtProxy.writeBlob(addr, params()->boot_osflags.c_str(),
 strlen(params()->boot_osflags.c_str()));
 }

diff --git a/src/arch/arm/linux/process.cc b/src/arch/arm/linux/process.cc
index 99f4b2c..2084578 100644
--- a/src/arch/arm/linux/process.cc
+++ b/src/arch/arm/linux/process.cc
@@ -106,7 +106,7 @@
 uint32_t tlsPtr = process->getSyscallArg(tc, index);

 tc->getMemProxy().writeBlob(ArmLinuxProcess32::commPage + 0x0ff0,
- (uint8_t *), sizeof(tlsPtr));
+, sizeof(tlsPtr));
 tc->setMiscReg(MISCREG_TPIDRURO,tlsPtr);
 return 0;
 }
diff --git a/src/arch/arm/process.cc b/src/arch/arm/process.cc
index baa861f..8e3cfd9 100644
--- a/src/arch/arm/process.cc
+++ b/src/arch/arm/process.cc
@@ -415,8 +415,7 @@

 //Write out the sentry void *
 IntType sentry_NULL = 0;
-initVirtMem.writeBlob(sentry_base,
-(uint8_t*)_NULL, sentry_size);
+initVirtMem.writeBlob(sentry_base, _NULL, sentry_size);

 //Fix up the aux vectors which point to other data
 for (int i = auxv.size() - 1; i >= 0; i--) {
@@ -446,7 +445,7 @@
 copyStringArray(envp, envp_array_base, env_data_base, initVirtMem);
 copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem);

-initVirtMem.writeBlob(argc_base, (uint8_t*), intSize);
+initVirtMem.writeBlob(argc_base, , intSize);

 ThreadContext *tc = system->getThreadContext(contextIds[0]);
 //Set the stack pointer register
diff --git a/src/arch/arm/semihosting.cc b/src/arch/arm/semihosting.cc
index 08310fb..4890fc1 100644
--- a/src/arch/arm/semihosting.cc
+++ b/src/arch/arm/semihosting.cc
@@ -272,7 +272,7 @@
 std::vector buf(len + 1);

 buf[len] = '\0';
-physProxy(tc).readBlob(ptr, (uint8_t *)buf.data(), len);
+physProxy(tc).readBlob(ptr, buf.data(), len);

 return std::string(buf.data());
 }
@@ -479,8 +479,7 @@
 if (path_len >= max_len)
 return retError(ENOSPC);

-physProxy(tc).writeBlob(
-guest_buf, (const uint8_t *)path, path_len + 1);
+physProxy(tc).writeBlob(guest_buf, path, path_len + 1);
 return retOK(0);
 }

@@ -551,9 +550,7 @@
 if (cmdLine.size() + 1 < argv[2]) {
 PortProxy  = physProxy(tc);
 ByteOrder 

[gem5-dev] Change in gem5/gem5[master]: kern: Replace an explicitly instantiated port proxy with one from the...

[Gabe Black (Gerrit)]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18578



Change subject: kern: Replace an explicitly instantiated port proxy with  
one from the tc.

..

kern: Replace an explicitly instantiated port proxy with one from the tc.

That avoids having to know what type of proxy to create.

Change-Id: I311e770ab720061b52f29df0dcc2273e028aa34a
---
M src/kern/linux/helpers.cc
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/kern/linux/helpers.cc b/src/kern/linux/helpers.cc
index ed58427..e514ef8 100644
--- a/src/kern/linux/helpers.cc
+++ b/src/kern/linux/helpers.cc
@@ -94,7 +94,7 @@
 {
 System *system = tc->getSystemPtr();
 const SymbolTable *symtab = system->kernelSymtab;
-FSTranslatingPortProxy proxy(tc);
+PortProxy  = tc->getVirtProxy();

 Addr addr_lb = 0, addr_lb_len = 0, addr_first = 0, addr_next = 0;
 const bool found_symbols =

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/18578
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I311e770ab720061b52f29df0dcc2273e028aa34a
Gerrit-Change-Number: 18578
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
Gerrit-MessageType: newchange
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in gem5/gem5[master]: mem: Remove the now unused Copy* methods from the FS port proxy.

[Gabe Black (Gerrit)]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18576



Change subject: mem: Remove the now unused Copy* methods from the FS port  
proxy.

..

mem: Remove the now unused Copy* methods from the FS port proxy.

Change-Id: Ie433a9e4c9ee748911060eb7b1b47e617aa297a6
---
M src/mem/fs_translating_port_proxy.cc
M src/mem/fs_translating_port_proxy.hh
2 files changed, 0 insertions(+), 49 deletions(-)



diff --git a/src/mem/fs_translating_port_proxy.cc  
b/src/mem/fs_translating_port_proxy.cc

index 2e17cbf..6a25d11 100644
--- a/src/mem/fs_translating_port_proxy.cc
+++ b/src/mem/fs_translating_port_proxy.cc
@@ -119,47 +119,3 @@
 }
 return true;
 }
-
-void
-CopyOut(ThreadContext *tc, void *dest, Addr src, size_t cplen)
-{
-uint8_t *dst = (uint8_t *)dest;
-tc->getVirtProxy().readBlob(src, dst, cplen);
-}
-
-void
-CopyIn(ThreadContext *tc, Addr dest, const void *source, size_t cplen)
-{
-uint8_t *src = (uint8_t *)source;
-tc->getVirtProxy().writeBlob(dest, src, cplen);
-}
-
-void
-CopyStringOut(ThreadContext *tc, char *dst, Addr vaddr, size_t maxlen)
-{
-char *start = dst;
-FSTranslatingPortProxy  = tc->getVirtProxy();
-
-bool foundNull = false;
-while ((dst - start + 1) < maxlen && !foundNull) {
-vp.readBlob(vaddr++, (uint8_t*)dst, 1);
-if (*dst == '\0')
-foundNull = true;
-dst++;
-}
-
-if (!foundNull)
-*dst = '\0';
-}
-
-void
-CopyStringIn(ThreadContext *tc, const char *src, Addr vaddr)
-{
-FSTranslatingPortProxy  = tc->getVirtProxy();
-for (ChunkGenerator gen(vaddr, strlen(src),  
TheISA::PageBytes); !gen.done();

- gen.next())
-{
-vp.writeBlob(gen.addr(), (uint8_t*)src, gen.size());
-src += gen.size();
-}
-}
diff --git a/src/mem/fs_translating_port_proxy.hh  
b/src/mem/fs_translating_port_proxy.hh

index 78adf1a..410eb7d 100644
--- a/src/mem/fs_translating_port_proxy.hh
+++ b/src/mem/fs_translating_port_proxy.hh
@@ -97,9 +97,4 @@
 bool tryMemsetBlob(Addr address, uint8_t  v, int size) const override;
 };

-void CopyOut(ThreadContext *tc, void *dest, Addr src, size_t cplen);
-void CopyIn(ThreadContext *tc, Addr dest, const void *source, size_t  
cplen);
-void CopyStringOut(ThreadContext *tc, char *dst, Addr vaddr, size_t  
maxlen);

-void CopyStringIn(ThreadContext *tc, const char *src, Addr vaddr);
-
 #endif //__MEM_FS_TRANSLATING_PORT_PROXY_HH__

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/18576
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ie433a9e4c9ee748911060eb7b1b47e617aa297a6
Gerrit-Change-Number: 18576
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
Gerrit-MessageType: newchange
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in gem5/gem5[master]: arch, base, cpu, gpu, sim: Merge getMemProxy and getVirtProxy.

[Gabe Black (Gerrit)]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18581



Change subject: arch, base, cpu, gpu, sim: Merge getMemProxy and  
getVirtProxy.

..

arch, base, cpu, gpu, sim: Merge getMemProxy and getVirtProxy.

These two functions were performing the same function but had two
different names for historical reasons. This change merges them
together, keeping the getVirtProxy name to be consistent with the
getPhysProxy method used to get a non-translating proxy port.

Change-Id: Idd83c6b899f9343795075b030ccbc723a79e52a4
---
M src/arch/alpha/linux/process.cc
M src/arch/arm/freebsd/process.cc
M src/arch/arm/linux/process.cc
M src/arch/mips/linux/process.cc
M src/arch/power/linux/process.cc
M src/arch/riscv/linux/process.cc
M src/arch/sparc/linux/syscalls.cc
M src/arch/sparc/process.cc
M src/arch/sparc/solaris/process.cc
M src/arch/x86/linux/process.cc
M src/arch/x86/pseudo_inst.cc
M src/base/remote_gdb.cc
M src/cpu/checker/thread_context.hh
M src/cpu/o3/thread_context.hh
M src/cpu/simple_thread.hh
M src/cpu/thread_context.hh
M src/cpu/thread_state.cc
M src/cpu/thread_state.hh
M src/gpu-compute/cl_driver.cc
M src/sim/process.cc
M src/sim/syscall_emul.cc
M src/sim/syscall_emul.hh
22 files changed, 178 insertions(+), 213 deletions(-)



diff --git a/src/arch/alpha/linux/process.cc  
b/src/arch/alpha/linux/process.cc

index c1162ba..6e0f075 100644
--- a/src/arch/alpha/linux/process.cc
+++ b/src/arch/alpha/linux/process.cc
@@ -58,7 +58,7 @@
 strcpy(name->version, "#1 Mon Aug 18 11:32:15 EDT 2003");
 strcpy(name->machine, "alpha");

-name.copyOut(tc->getMemProxy());
+name.copyOut(tc->getVirtProxy());
 return 0;
 }

@@ -80,7 +80,7 @@
   TypedBufferArg fpcr(bufPtr);
   // I don't think this exactly matches the HW FPCR
   *fpcr = 0;
-  fpcr.copyOut(tc->getMemProxy());
+  fpcr.copyOut(tc->getVirtProxy());
   return 0;
   }

@@ -108,7 +108,7 @@
   case 14: { // SSI_IEEE_FP_CONTROL
   TypedBufferArg fpcr(bufPtr);
   // I don't think this exactly matches the HW FPCR
-  fpcr.copyIn(tc->getMemProxy());
+  fpcr.copyIn(tc->getVirtProxy());
   DPRINTFR(SyscallVerbose, "osf_setsysinfo(SSI_IEEE_FP_CONTROL): "
" setting FPCR to 0x%x\n", gtoh(*(uint64_t*)fpcr));
   return 0;
diff --git a/src/arch/arm/freebsd/process.cc  
b/src/arch/arm/freebsd/process.cc

index e6aa740..a563e4d 100644
--- a/src/arch/arm/freebsd/process.cc
+++ b/src/arch/arm/freebsd/process.cc
@@ -79,13 +79,13 @@
 BufferArg buf3(oldlenp, sizeof(size_t));
 BufferArg buf4(newp, sizeof(size_t));

-buf.copyIn(tc->getMemProxy());
-buf2.copyIn(tc->getMemProxy());
-buf3.copyIn(tc->getMemProxy());
+buf.copyIn(tc->getVirtProxy());
+buf2.copyIn(tc->getVirtProxy());
+buf3.copyIn(tc->getVirtProxy());

 void *hnewp = NULL;
 if (newp) {
-buf4.copyIn(tc->getMemProxy());
+buf4.copyIn(tc->getVirtProxy());
 hnewp = (void *)buf4.bufferPtr();
 }

@@ -95,11 +95,11 @@

 ret = sysctl((int *)hnamep, namelen, holdp, holdlenp, hnewp, newlen);

-buf.copyOut(tc->getMemProxy());
-buf2.copyOut(tc->getMemProxy());
-buf3.copyOut(tc->getMemProxy());
+buf.copyOut(tc->getVirtProxy());
+buf2.copyOut(tc->getVirtProxy());
+buf3.copyOut(tc->getVirtProxy());
 if (newp)
-buf4.copyOut(tc->getMemProxy());
+buf4.copyOut(tc->getVirtProxy());

 return (ret);
 }
diff --git a/src/arch/arm/linux/process.cc b/src/arch/arm/linux/process.cc
index 2084578..bb78b40 100644
--- a/src/arch/arm/linux/process.cc
+++ b/src/arch/arm/linux/process.cc
@@ -75,7 +75,7 @@
 strcpy(name->version, "#1 SMP Sat Dec  1 00:00:00 GMT 2012");
 strcpy(name->machine, "armv7l");

-name.copyOut(tc->getMemProxy());
+name.copyOut(tc->getVirtProxy());
 return 0;
 }

@@ -93,7 +93,7 @@
 strcpy(name->version, "#1 SMP Sat Dec  1 00:00:00 GMT 2012");
 strcpy(name->machine, "armv8l");

-name.copyOut(tc->getMemProxy());
+name.copyOut(tc->getVirtProxy());
 return 0;
 }

@@ -105,7 +105,7 @@
 int index = 0;
 uint32_t tlsPtr = process->getSyscallArg(tc, index);

-tc->getMemProxy().writeBlob(ArmLinuxProcess32::commPage + 0x0ff0,
+tc->getVirtProxy().writeBlob(ArmLinuxProcess32::commPage + 0x0ff0,
 , sizeof(tlsPtr));
 tc->setMiscReg(MISCREG_TPIDRURO,tlsPtr);
 return 0;
@@ -1695,8 +1695,8 @@

 // Fill this page with swi -1 so we'll no if we land in it somewhere.
 for (Addr addr = 0; addr < PageBytes; addr += sizeof(swiNeg1)) {
-tc->getMemProxy().writeBlob(commPage + addr,
-swiNeg1, sizeof(swiNeg1));
+tc->getVirtProxy().writeBlob(commPage + addr,
+ swiNeg1, sizeof(swiNeg1));
 }

 uint8_t 

[gem5-dev] Change in gem5/gem5[master]: mem, arm: Replace the pointer type in PortProxy with void *.

[Gabe Black (Gerrit)]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18571



Change subject: mem, arm: Replace the pointer type in PortProxy with void *.
..

mem, arm: Replace the pointer type in PortProxy with void *.

The void * type is for pointers which point to an unknown type. We
should use that when handling anonymous buffers in the PortProxy
functions, instead of uint8_t * which points to bytes.

Importantly, C/C++ doesn't require you to do any casting to turn an
arbitrary pointer type into a void *. This will get rid of lots of
tedious, verbose casting throughout the code base.

Change-Id: Id1adecc283c866d8e24524efd64f37b079088bd9
---
M src/arch/arm/secure_port_proxy.cc
M src/arch/arm/secure_port_proxy.hh
M src/mem/fs_translating_port_proxy.cc
M src/mem/fs_translating_port_proxy.hh
M src/mem/port_proxy.cc
M src/mem/port_proxy.hh
M src/mem/se_translating_port_proxy.cc
M src/mem/se_translating_port_proxy.hh
8 files changed, 35 insertions(+), 34 deletions(-)



diff --git a/src/arch/arm/secure_port_proxy.cc  
b/src/arch/arm/secure_port_proxy.cc

index 319d1f1..e697b96 100644
--- a/src/arch/arm/secure_port_proxy.cc
+++ b/src/arch/arm/secure_port_proxy.cc
@@ -40,14 +40,14 @@
 #include "arch/arm/secure_port_proxy.hh"

 bool
-SecurePortProxy::tryReadBlob(Addr addr, uint8_t *p, int size) const
+SecurePortProxy::tryReadBlob(Addr addr, void *p, int size) const
 {
 readBlobPhys(addr, Request::SECURE, p, size);
 return true;
 }

 bool
-SecurePortProxy::tryWriteBlob(Addr addr, const uint8_t *p, int size) const
+SecurePortProxy::tryWriteBlob(Addr addr, const void *p, int size) const
 {
 writeBlobPhys(addr, Request::SECURE, p, size);
 return true;
diff --git a/src/arch/arm/secure_port_proxy.hh  
b/src/arch/arm/secure_port_proxy.hh

index a3e50be..566b918 100644
--- a/src/arch/arm/secure_port_proxy.hh
+++ b/src/arch/arm/secure_port_proxy.hh
@@ -73,8 +73,8 @@
 SecurePortProxy(MasterPort , unsigned int cache_line_size)
 : PortProxy(port, cache_line_size) {}

-bool tryReadBlob(Addr addr, uint8_t *p, int size) const override;
-bool tryWriteBlob(Addr addr, const uint8_t *p, int size) const  
override;

+bool tryReadBlob(Addr addr, void *p, int size) const override;
+bool tryWriteBlob(Addr addr, const void *p, int size) const override;
 bool tryMemsetBlob(Addr addr, uint8_t val, int size) const override;
 };

diff --git a/src/mem/fs_translating_port_proxy.cc  
b/src/mem/fs_translating_port_proxy.cc

index a21d328..2e17cbf 100644
--- a/src/mem/fs_translating_port_proxy.cc
+++ b/src/mem/fs_translating_port_proxy.cc
@@ -67,7 +67,7 @@
 }

 bool
-FSTranslatingPortProxy::tryReadBlob(Addr addr, uint8_t *p, int size) const
+FSTranslatingPortProxy::tryReadBlob(Addr addr, void *p, int size) const
 {
 Addr paddr;
 for (ChunkGenerator gen(addr, size, TheISA::PageBytes); !gen.done();
@@ -79,14 +79,14 @@
 paddr = TheISA::vtophys(gen.addr());

 PortProxy::readBlobPhys(paddr, 0, p, gen.size());
-p += gen.size();
+p = static_cast(p) + gen.size();
 }
 return true;
 }

 bool
 FSTranslatingPortProxy::tryWriteBlob(
-Addr addr, const uint8_t *p, int size) const
+Addr addr, const void *p, int size) const
 {
 Addr paddr;
 for (ChunkGenerator gen(addr, size, TheISA::PageBytes); !gen.done();
@@ -98,7 +98,7 @@
 paddr = TheISA::vtophys(gen.addr());

 PortProxy::writeBlobPhys(paddr, 0, p, gen.size());
-p += gen.size();
+p = static_cast(p) + gen.size();
 }
 return true;
 }
diff --git a/src/mem/fs_translating_port_proxy.hh  
b/src/mem/fs_translating_port_proxy.hh

index 5ae8700..78adf1a 100644
--- a/src/mem/fs_translating_port_proxy.hh
+++ b/src/mem/fs_translating_port_proxy.hh
@@ -85,11 +85,11 @@

 /** Version of tryReadblob that translates virt->phys and deals
   * with page boundries. */
-bool tryReadBlob(Addr addr, uint8_t *p, int size) const override;
+bool tryReadBlob(Addr addr, void *p, int size) const override;

 /** Version of tryWriteBlob that translates virt->phys and deals
   * with page boundries. */
-bool tryWriteBlob(Addr addr, const uint8_t *p, int size) const  
override;

+bool tryWriteBlob(Addr addr, const void *p, int size) const override;

 /**
  * Fill size bytes starting at addr with byte value val.
diff --git a/src/mem/port_proxy.cc b/src/mem/port_proxy.cc
index 97eb67e..f56bfeb 100644
--- a/src/mem/port_proxy.cc
+++ b/src/mem/port_proxy.cc
@@ -43,7 +43,7 @@

 void
 PortProxy::readBlobPhys(Addr addr, Request::Flags flags,
-uint8_t *p, int size) const
+void *p, int size) const
 {
 for (ChunkGenerator gen(addr, size, _cacheLineSize); !gen.done();
  gen.next()) {
@@ -52,15 +52,15 @@
 gen.addr(), gen.size(), flags, Request::funcMasterId);

 

[gem5-dev] Change in gem5/gem5[master]: cpu, sim: Return PortProxy from all the proxy accessors.

[Gabe Black (Gerrit)]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18579



Change subject: cpu, sim: Return PortProxy  from all the proxy accessors.
..

cpu, sim: Return PortProxy  from all the proxy accessors.

This is a step towards merging the accessors for SE and FS modes.

Change-Id: I76818ab88b97097ac363e243be9cc1911b283090
---
M src/cpu/checker/thread_context.hh
M src/cpu/o3/thread_context.hh
M src/cpu/o3/thread_context_impl.hh
M src/cpu/simple_thread.hh
M src/cpu/thread_context.hh
M src/cpu/thread_state.cc
M src/cpu/thread_state.hh
M src/sim/process.cc
8 files changed, 19 insertions(+), 20 deletions(-)



diff --git a/src/cpu/checker/thread_context.hh  
b/src/cpu/checker/thread_context.hh

index ed8add6..46ade24 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -146,7 +146,7 @@

 PortProxy () override { return actualTC->getPhysProxy(); }

-FSTranslatingPortProxy &
+PortProxy &
 getVirtProxy() override
 {
 return actualTC->getVirtProxy();
@@ -164,7 +164,7 @@
 actualTC->connectMemPorts(tc);
 }

-SETranslatingPortProxy &
+PortProxy &
 getMemProxy() override
 {
 return actualTC->getMemProxy();
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index e5f0187..a3698cf 100644
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -132,7 +132,7 @@

 PortProxy () override { return thread->getPhysProxy(); }

-FSTranslatingPortProxy () override;
+PortProxy () override;

 void
 initMemProxies(ThreadContext *tc) override
@@ -140,7 +140,7 @@
 thread->initMemProxies(tc);
 }

-SETranslatingPortProxy &
+PortProxy &
 getMemProxy() override
 {
 return thread->getMemProxy();
diff --git a/src/cpu/o3/thread_context_impl.hh  
b/src/cpu/o3/thread_context_impl.hh

index 58dee98..e05721b 100644
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -54,7 +54,7 @@
 #include "debug/O3CPU.hh"

 template 
-FSTranslatingPortProxy&
+PortProxy&
 O3ThreadContext::getVirtProxy()
 {
 return thread->getVirtProxy();
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 733047f..b044f53 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -213,18 +213,14 @@
 }

 PortProxy () override { return  
ThreadState::getPhysProxy(); }

-FSTranslatingPortProxy &
-getVirtProxy() override
-{
-return ThreadState::getVirtProxy();
-}
+PortProxy () override { return  
ThreadState::getVirtProxy(); }


 void initMemProxies(ThreadContext *tc) override
 {
 ThreadState::initMemProxies(tc);
 }

-SETranslatingPortProxy &
+PortProxy &
 getMemProxy() override
 {
 return ThreadState::getMemProxy();
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index bdf5a00..f8b69d0 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -65,8 +65,6 @@
 class CheckerCPU;
 class Checkpoint;
 class EndQuiesceEvent;
-class SETranslatingPortProxy;
-class FSTranslatingPortProxy;
 class PortProxy;
 class Process;
 class System;
@@ -152,7 +150,7 @@

 virtual PortProxy () = 0;

-virtual FSTranslatingPortProxy () = 0;
+virtual PortProxy () = 0;

 /**
  * Initialise the physical and virtual port proxies and tie them to
@@ -162,7 +160,7 @@
  */
 virtual void initMemProxies(ThreadContext *tc) = 0;

-virtual SETranslatingPortProxy () = 0;
+virtual PortProxy () = 0;

 virtual Process *getProcessPtr() = 0;

diff --git a/src/cpu/thread_state.cc b/src/cpu/thread_state.cc
index acb2971..c9fc564 100644
--- a/src/cpu/thread_state.cc
+++ b/src/cpu/thread_state.cc
@@ -133,7 +133,7 @@
 return *physProxy;
 }

-FSTranslatingPortProxy &
+PortProxy &
 ThreadState::getVirtProxy()
 {
 assert(FullSystem);
@@ -141,7 +141,7 @@
 return *virtProxy;
 }

-SETranslatingPortProxy &
+PortProxy &
 ThreadState::getMemProxy()
 {
 assert(!FullSystem);
diff --git a/src/cpu/thread_state.hh b/src/cpu/thread_state.hh
index 2006339..e00c86f 100644
--- a/src/cpu/thread_state.hh
+++ b/src/cpu/thread_state.hh
@@ -47,6 +47,9 @@

 class Checkpoint;

+class FSTranslatingPortProxy;
+class SETranslatingPortProxy;
+
 /**
  *  Struct for holding general thread state that is needed across CPU
  *  models.  This includes things such as pointers to the process,
@@ -100,7 +103,7 @@

 PortProxy ();

-FSTranslatingPortProxy ();
+PortProxy ();

 Process *getProcessPtr() { return process; }

@@ -119,7 +122,7 @@
 }
 }

-SETranslatingPortProxy ();
+PortProxy ();

 /** Reads the number of instructions functionally executed and
  * committed.
diff --git a/src/sim/process.cc b/src/sim/process.cc
index d400b5d..1249814 100644
--- a/src/sim/process.cc
+++ 

[gem5-dev] Change in gem5/gem5[master]: arch, base, sim: Replace Copy(String)?(In|Out) with equivalent code.

[Gabe Black (Gerrit)]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18575



Change subject: arch, base, sim: Replace Copy(String)?(In|Out) with  
equivalent code.

..

arch, base, sim: Replace Copy(String)?(In|Out) with equivalent code.

This expands those functions into code which extracts the virt proxy
and then uses the appropriate method on it. This has two benefits.
First, the Copy* functions where mostly redundant wrappers around the
methods the proxy port already had. Second, using them forced a
particular port which might not actually be what the user wanted.

Change-Id: I62084631dd080061e3c74997125164f40da2d77c
---
M src/arch/alpha/stacktrace.cc
M src/arch/arm/stacktrace.cc
M src/arch/generic/linux/threadinfo.hh
M src/arch/mips/stacktrace.cc
M src/arch/x86/stacktrace.cc
M src/base/cp_annotate.cc
M src/sim/arguments.hh
M src/sim/pseudo_inst.cc
8 files changed, 48 insertions(+), 72 deletions(-)



diff --git a/src/arch/alpha/stacktrace.cc b/src/arch/alpha/stacktrace.cc
index dfe7474..f5833b0 100644
--- a/src/arch/alpha/stacktrace.cc
+++ b/src/arch/alpha/stacktrace.cc
@@ -111,7 +111,7 @@
 return "console";

 char comm[256];
-CopyStringOut(tc, comm, task + name_off, sizeof(comm));
+tc->getVirtProxy().readString(comm, task + name_off, sizeof(comm));
 if (!comm[0])
 return "startup";

@@ -311,8 +311,7 @@
 ra = 0;

 for (Addr pc = func; pc < callpc; pc += sizeof(MachInst)) {
-MachInst inst;
-CopyOut(tc, (uint8_t *), pc, sizeof(MachInst));
+MachInst inst = tc->getVirtProxy().read(pc);

 int reg, disp;
 if (decodeStack(inst, disp)) {
@@ -323,7 +322,7 @@
 size += disp;
 } else if (decodeSave(inst, reg, disp)) {
 if (!ra && reg == ReturnAddressReg) {
-CopyOut(tc, (uint8_t *), sp + disp, sizeof(Addr));
+ra = tc->getVirtProxy().read(sp + disp);
 if (!ra) {
 // panic("no return address value pc=%#x\n", pc);
 return false;
diff --git a/src/arch/arm/stacktrace.cc b/src/arch/arm/stacktrace.cc
index b4dbf72..837b6ad 100644
--- a/src/arch/arm/stacktrace.cc
+++ b/src/arch/arm/stacktrace.cc
@@ -104,7 +104,7 @@
 return "unknown";

 char comm[256];
-CopyStringOut(tc, comm, task + name_off, sizeof(comm));
+tc->getVirtProxy().readString(comm, task + name_off, sizeof(comm));
 if (!comm[0])
 return "startup";

diff --git a/src/arch/generic/linux/threadinfo.hh  
b/src/arch/generic/linux/threadinfo.hh

index 1595da4..626de58 100644
--- a/src/arch/generic/linux/threadinfo.hh
+++ b/src/arch/generic/linux/threadinfo.hh
@@ -58,9 +58,7 @@
 return false;
 }

-CopyOut(tc, , addr, sizeof(T));
-
-data = TheISA::gtoh(data);
+data = tc->getVirtProxy().read(addr, TheISA::GuestByteOrder);

 return true;
 }
@@ -98,29 +96,23 @@
 // Note that in Linux 4.10 the thread_info struct will no longer  
have a

 // pointer to the task_struct for arm64. See:
 // https://patchwork.kernel.org/patch/9333699/
-int32_t offset;
+int32_t offset = 0;
 if (!get_data("thread_info_task", offset))
 return 0;

 if (!thread_info)
 thread_info = curThreadInfo();

-Addr addr;
-CopyOut(tc, , thread_info + offset, sizeof(addr));
-
-return addr;
+return tc->getVirtProxy().read(thread_info + offset);
 }

 int32_t
 curTaskPIDFromTaskStruct(Addr task_struct) {
-int32_t offset;
+int32_t offset = 0;
 if (!get_data("task_struct_pid", offset))
 return -1;

-int32_t pid;
-CopyOut(tc, , task_struct + offset, sizeof(pid));
-
-return pid;
+return tc->getVirtProxy().read(task_struct + offset);
 }

 int32_t
@@ -132,14 +124,11 @@
 int32_t
 curTaskTGIDFromTaskStruct(Addr task_struct)
 {
-int32_t offset;
+int32_t offset = 0;
 if (!get_data("task_struct_tgid", offset))
 return -1;

-int32_t tgid;
-CopyOut(tc, , task_struct + offset, sizeof(tgid));
-
-return tgid;
+return tc->getVirtProxy().read(task_struct + offset);
 }

 int32_t
@@ -151,16 +140,13 @@
 int64_t
 curTaskStartFromTaskStruct(Addr task_struct)
 {
-int32_t offset;
+int32_t offset = 0;
 if (!get_data("task_struct_start_time", offset))
 return -1;

-int64_t data;
 // start_time is actually of type timespec, but if we just
 // grab the first long, we'll get the seconds out of it
-CopyOut(tc, , task_struct + offset, sizeof(data));
-
-return data;
+return tc->getVirtProxy().read(task_struct + offset);
 }

 int64_t
@@ -172,8 +158,8 @@
 std::string
 

[gem5-dev] Change in gem5/gem5[master]: arch, base, sim: Demote (SE|FS)TranslatingPortProxy to PortProxy .

[Gabe Black (Gerrit)]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18577



Change subject: arch, base, sim: Demote (SE|FS)TranslatingPortProxy  to  
PortProxy 

..

arch, base, sim: Demote (SE|FS)TranslatingPortProxy  to PortProxy 

Al(most) all of the interesting differences between the two classes
have been removed. There are some control methods which are still
specific to each type which may require treating them as their true
type, but most code that consumes them doesn't need to worry about
which is which.

Change-Id: Ie592676f1e496c7940605b66e55cd7fae18e59d6
---
M src/arch/alpha/linux/system.cc
M src/arch/alpha/stacktrace.cc
M src/arch/alpha/utility.cc
M src/arch/arm/stacktrace.cc
M src/arch/arm/utility.cc
M src/arch/mips/stacktrace.cc
M src/arch/sparc/utility.cc
M src/arch/x86/linux/process.cc
M src/arch/x86/pseudo_inst.cc
M src/arch/x86/stacktrace.cc
M src/base/remote_gdb.cc
M src/sim/process_impl.hh
M src/sim/syscall_emul.cc
M src/sim/syscall_emul.hh
M src/sim/syscall_emul_buf.hh
M src/sim/vptr.hh
16 files changed, 38 insertions(+), 37 deletions(-)



diff --git a/src/arch/alpha/linux/system.cc b/src/arch/alpha/linux/system.cc
index 9cc839e..cebd264 100644
--- a/src/arch/alpha/linux/system.cc
+++ b/src/arch/alpha/linux/system.cc
@@ -180,7 +180,7 @@
 if (kernelSymtab->findAddress("loops_per_jiffy", addr)) {
 Tick cpuFreq = tc->getCpuPtr()->frequency();
 assert(intrFreq);
-FSTranslatingPortProxy  = tc->getVirtProxy();
+PortProxy  = tc->getVirtProxy();
 vp.write(addr, (uint32_t)((cpuFreq / intrFreq) * 0.9988),
  GuestByteOrder);
 }
diff --git a/src/arch/alpha/stacktrace.cc b/src/arch/alpha/stacktrace.cc
index f5833b0..bf2d5b3 100644
--- a/src/arch/alpha/stacktrace.cc
+++ b/src/arch/alpha/stacktrace.cc
@@ -49,7 +49,7 @@
 : tc(_tc)
 {
 Addr addr = 0;
-FSTranslatingPortProxy  = tc->getVirtProxy();
+PortProxy  = tc->getVirtProxy();
 SymbolTable *symtab = tc->getSystemPtr()->kernelSymtab;

 if (!symtab->findAddress("thread_info_size", addr))
@@ -82,7 +82,7 @@

 Addr tsk;

-FSTranslatingPortProxy  = tc->getVirtProxy();
+PortProxy  = tc->getVirtProxy();
 tsk = vp.read(base + task_off, GuestByteOrder);

 return tsk;
@@ -97,7 +97,7 @@

 uint16_t pd;

-FSTranslatingPortProxy  = tc->getVirtProxy();
+PortProxy  = tc->getVirtProxy();
 pd = vp.read(task + pid_off, GuestByteOrder);

 return pd;
diff --git a/src/arch/alpha/utility.cc b/src/arch/alpha/utility.cc
index c644911..8264c94 100644
--- a/src/arch/alpha/utility.cc
+++ b/src/arch/alpha/utility.cc
@@ -53,7 +53,7 @@
 return tc->readIntReg(16 + number);
 } else {
 Addr sp = tc->readIntReg(StackPointerReg);
-FSTranslatingPortProxy  = tc->getVirtProxy();
+PortProxy  = tc->getVirtProxy();
 uint64_t arg = vp.read(sp +
  (number-NumArgumentRegs) *
  sizeof(uint64_t));
diff --git a/src/arch/arm/stacktrace.cc b/src/arch/arm/stacktrace.cc
index 837b6ad..8fadb81 100644
--- a/src/arch/arm/stacktrace.cc
+++ b/src/arch/arm/stacktrace.cc
@@ -47,7 +47,7 @@
 static int32_t
 readSymbol(ThreadContext *tc, const std::string name)
 {
-FSTranslatingPortProxy  = tc->getVirtProxy();
+PortProxy  = tc->getVirtProxy();
 SymbolTable *symtab = tc->getSystemPtr()->kernelSymtab;

 Addr addr;
@@ -75,7 +75,7 @@

 Addr tsk;

-FSTranslatingPortProxy  = tc->getVirtProxy();
+PortProxy  = tc->getVirtProxy();
 tsk = vp.read(base + task_off, GuestByteOrder);

 return tsk;
@@ -90,7 +90,7 @@

 uint16_t pd;

-FSTranslatingPortProxy  = tc->getVirtProxy();
+PortProxy  = tc->getVirtProxy();
 pd = vp.read(task + pid_off, GuestByteOrder);

 return pd;
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index 29b39b8..6e34056 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -107,7 +107,7 @@
 }
 } else {
 Addr sp = tc->readIntReg(StackPointerReg);
-FSTranslatingPortProxy  = tc->getVirtProxy();
+PortProxy  = tc->getVirtProxy();
 uint64_t arg;
 if (size == sizeof(uint64_t)) {
 // If the argument is even it must be aligned
diff --git a/src/arch/mips/stacktrace.cc b/src/arch/mips/stacktrace.cc
index 7517b9d..fe464e3 100644
--- a/src/arch/mips/stacktrace.cc
+++ b/src/arch/mips/stacktrace.cc
@@ -55,7 +55,7 @@

 Addr tsk;

-FSTranslatingPortProxy  = tc->getVirtProxy();
+PortProxy  = tc->getVirtProxy();
 tsk = vp.read(base + task_off, GuestByteOrder);

 return tsk;
@@ -70,7 +70,7 @@

 uint16_t pd;

-FSTranslatingPortProxy  = tc->getVirtProxy();
+PortProxy  = tc->getVirtProxy();
 pd = vp.read(task + pid_off, GuestByteOrder);

 return pd;

[gem5-dev] Change in gem5/gem5[master]: mem, arm: Move some helper methods into the base PortProxy class.

[Gabe Black (Gerrit)]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18570



Change subject: mem, arm: Move some helper methods into the base PortProxy  
class.

..

mem, arm: Move some helper methods into the base PortProxy class.

These were originally in the SETranslatingPortProxy class, but they're
not specific to SE mode in any way and are an unnecessary divergence
between the SE and FS mode translating port proxies.

Change-Id: I8cb77531cc287bd15b2386410ffa7b43cdfa67d0
---
M src/arch/arm/secure_port_proxy.cc
M src/arch/arm/secure_port_proxy.hh
M src/mem/fs_translating_port_proxy.cc
M src/mem/fs_translating_port_proxy.hh
M src/mem/port_proxy.cc
M src/mem/port_proxy.hh
M src/mem/se_translating_port_proxy.cc
M src/mem/se_translating_port_proxy.hh
8 files changed, 159 insertions(+), 145 deletions(-)



diff --git a/src/arch/arm/secure_port_proxy.cc  
b/src/arch/arm/secure_port_proxy.cc

index f82c6cb..319d1f1 100644
--- a/src/arch/arm/secure_port_proxy.cc
+++ b/src/arch/arm/secure_port_proxy.cc
@@ -39,20 +39,23 @@

 #include "arch/arm/secure_port_proxy.hh"

-void
-SecurePortProxy::readBlob(Addr addr, uint8_t *p, int size) const
+bool
+SecurePortProxy::tryReadBlob(Addr addr, uint8_t *p, int size) const
 {
 readBlobPhys(addr, Request::SECURE, p, size);
+return true;
 }

-void
-SecurePortProxy::writeBlob(Addr addr, const uint8_t *p, int size) const
+bool
+SecurePortProxy::tryWriteBlob(Addr addr, const uint8_t *p, int size) const
 {
 writeBlobPhys(addr, Request::SECURE, p, size);
+return true;
 }

-void
-SecurePortProxy::memsetBlob(Addr addr, uint8_t v, int size) const
+bool
+SecurePortProxy::tryMemsetBlob(Addr addr, uint8_t v, int size) const
 {
 memsetBlobPhys(addr, Request::SECURE, v, size);
+return true;
 }
diff --git a/src/arch/arm/secure_port_proxy.hh  
b/src/arch/arm/secure_port_proxy.hh

index df2204f..a3e50be 100644
--- a/src/arch/arm/secure_port_proxy.hh
+++ b/src/arch/arm/secure_port_proxy.hh
@@ -73,9 +73,9 @@
 SecurePortProxy(MasterPort , unsigned int cache_line_size)
 : PortProxy(port, cache_line_size) {}

-void readBlob(Addr addr, uint8_t *p, int size) const override;
-void writeBlob(Addr addr, const uint8_t *p, int size) const override;
-void memsetBlob(Addr addr, uint8_t val, int size) const override;
+bool tryReadBlob(Addr addr, uint8_t *p, int size) const override;
+bool tryWriteBlob(Addr addr, const uint8_t *p, int size) const  
override;

+bool tryMemsetBlob(Addr addr, uint8_t val, int size) const override;
 };

 #endif // __ARCH_ARM_PORT_PROXY_HH__
diff --git a/src/mem/fs_translating_port_proxy.cc  
b/src/mem/fs_translating_port_proxy.cc

index 15ad823..a21d328 100644
--- a/src/mem/fs_translating_port_proxy.cc
+++ b/src/mem/fs_translating_port_proxy.cc
@@ -66,12 +66,8 @@
 {
 }

-FSTranslatingPortProxy::~FSTranslatingPortProxy()
-{
-}
-
-void
-FSTranslatingPortProxy::readBlob(Addr addr, uint8_t *p, int size) const
+bool
+FSTranslatingPortProxy::tryReadBlob(Addr addr, uint8_t *p, int size) const
 {
 Addr paddr;
 for (ChunkGenerator gen(addr, size, TheISA::PageBytes); !gen.done();
@@ -85,10 +81,12 @@
 PortProxy::readBlobPhys(paddr, 0, p, gen.size());
 p += gen.size();
 }
+return true;
 }

-void
-FSTranslatingPortProxy::writeBlob(Addr addr, const uint8_t *p, int size)  
const

+bool
+FSTranslatingPortProxy::tryWriteBlob(
+Addr addr, const uint8_t *p, int size) const
 {
 Addr paddr;
 for (ChunkGenerator gen(addr, size, TheISA::PageBytes); !gen.done();
@@ -102,10 +100,11 @@
 PortProxy::writeBlobPhys(paddr, 0, p, gen.size());
 p += gen.size();
 }
+return true;
 }

-void
-FSTranslatingPortProxy::memsetBlob(Addr address, uint8_t v, int size) const
+bool
+FSTranslatingPortProxy::tryMemsetBlob(Addr address, uint8_t v, int size)  
const

 {
 Addr paddr;
 for (ChunkGenerator gen(address, size, TheISA::PageBytes); !gen.done();
@@ -118,6 +117,7 @@

 PortProxy::memsetBlobPhys(paddr, 0, v, gen.size());
 }
+return true;
 }

 void
diff --git a/src/mem/fs_translating_port_proxy.hh  
b/src/mem/fs_translating_port_proxy.hh

index d4b4eb5..5ae8700 100644
--- a/src/mem/fs_translating_port_proxy.hh
+++ b/src/mem/fs_translating_port_proxy.hh
@@ -81,20 +81,20 @@

 FSTranslatingPortProxy(MasterPort , unsigned int cacheLineSize);

-~FSTranslatingPortProxy();
+~FSTranslatingPortProxy() {}

-/** Version of readblob that translates virt->phys and deals
+/** Version of tryReadblob that translates virt->phys and deals
   * with page boundries. */
-void readBlob(Addr addr, uint8_t *p, int size) const override;
+bool tryReadBlob(Addr addr, uint8_t *p, int size) const override;

-/** Version of writeBlob that translates virt->phys and deals
+/** Version of tryWriteBlob that translates virt->phys and deals
   * with page 

[gem5-dev] Change in gem5/gem5[master]: arm, mem: Move the SecurePortProxy subclass into arch/arm.

[Gabe Black (Gerrit)]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18569



Change subject: arm, mem: Move the SecurePortProxy subclass into arch/arm.
..

arm, mem: Move the SecurePortProxy subclass into arch/arm.

The idea of a "secure" memory area/access is specific to ARM and
shouldn't be in the common mem directory.

Change-Id: I140d4566ee2deded784adb04bcf6f11755a85c0c
---
M src/arch/arm/SConscript
A src/arch/arm/secure_port_proxy.cc
A src/arch/arm/secure_port_proxy.hh
M src/arch/arm/semihosting.cc
M src/mem/port_proxy.cc
M src/mem/port_proxy.hh
6 files changed, 141 insertions(+), 37 deletions(-)



diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript
index 58a13cd..85d8453 100644
--- a/src/arch/arm/SConscript
+++ b/src/arch/arm/SConscript
@@ -78,6 +78,7 @@
 Source('pmu.cc')
 Source('process.cc')
 Source('remote_gdb.cc')
+Source('secure_port_proxy.cc')
 Source('semihosting.cc')
 Source('stacktrace.cc')
 Source('system.cc')
diff --git a/src/arch/arm/secure_port_proxy.cc  
b/src/arch/arm/secure_port_proxy.cc

new file mode 100644
index 000..f82c6cb
--- /dev/null
+++ b/src/arch/arm/secure_port_proxy.cc
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2012, 2018 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Andreas Hansson
+ */
+
+#include "arch/arm/secure_port_proxy.hh"
+
+void
+SecurePortProxy::readBlob(Addr addr, uint8_t *p, int size) const
+{
+readBlobPhys(addr, Request::SECURE, p, size);
+}
+
+void
+SecurePortProxy::writeBlob(Addr addr, const uint8_t *p, int size) const
+{
+writeBlobPhys(addr, Request::SECURE, p, size);
+}
+
+void
+SecurePortProxy::memsetBlob(Addr addr, uint8_t v, int size) const
+{
+memsetBlobPhys(addr, Request::SECURE, v, size);
+}
diff --git a/src/arch/arm/secure_port_proxy.hh  
b/src/arch/arm/secure_port_proxy.hh

new file mode 100644
index 000..df2204f
--- /dev/null
+++ b/src/arch/arm/secure_port_proxy.hh
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2011-2013, 2018 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, 

[gem5-dev] Change in gem5/gem5[master]: cpu: Store the translating proxy with the same pointer in SE or FS mode.

[Gabe Black (Gerrit)]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18580



Change subject: cpu: Store the translating proxy with the same pointer in  
SE or FS mode.

..

cpu: Store the translating proxy with the same pointer in SE or FS mode.

Only one is active at a time, so they can share the same pointer.

Change-Id: Ie4ae1f0ffbf9448f6730f9c7d072bc85d6d423da
---
M src/cpu/thread_state.cc
M src/cpu/thread_state.hh
2 files changed, 9 insertions(+), 12 deletions(-)



diff --git a/src/cpu/thread_state.cc b/src/cpu/thread_state.cc
index c9fc564..3396c75 100644
--- a/src/cpu/thread_state.cc
+++ b/src/cpu/thread_state.cc
@@ -49,7 +49,7 @@
   _contextId(0), _threadId(_tid), lastActivate(0), lastSuspend(0),
   profile(NULL), profileNode(NULL), profilePC(0), quiesceEvent(NULL),
   kernelStats(NULL), process(_process), physProxy(NULL),  
virtProxy(NULL),

-  proxy(NULL), funcExeInst(0), storeCondFailures(0)
+  funcExeInst(0), storeCondFailures(0)
 {
 }

@@ -59,8 +59,6 @@
 delete physProxy;
 if (virtProxy != NULL)
 delete virtProxy;
-if (proxy != NULL)
-delete proxy;
 }

 void
@@ -118,8 +116,8 @@
 assert(virtProxy == NULL);
 virtProxy = new FSTranslatingPortProxy(tc);
 } else {
-assert(proxy == NULL);
-proxy = new SETranslatingPortProxy(baseCpu->getDataPort(),
+assert(virtProxy == NULL);
+virtProxy = new SETranslatingPortProxy(baseCpu->getDataPort(),
process,
 
SETranslatingPortProxy::NextPage);

 }
@@ -145,8 +143,8 @@
 ThreadState::getMemProxy()
 {
 assert(!FullSystem);
-assert(proxy != NULL);
-return *proxy;
+assert(virtProxy != NULL);
+return *virtProxy;
 }

 void
diff --git a/src/cpu/thread_state.hh b/src/cpu/thread_state.hh
index e00c86f..db4a3f4 100644
--- a/src/cpu/thread_state.hh
+++ b/src/cpu/thread_state.hh
@@ -115,9 +115,9 @@
  * the se translating port proxy needs to be reinitialized since it
  * holds a pointer to the process class.
  */
-if (proxy) {
-delete proxy;
-proxy = NULL;
+if (virtProxy) {
+delete virtProxy;
+virtProxy = NULL;
 initMemProxies(NULL);
 }
 }
@@ -197,8 +197,7 @@

 /** A translating port proxy, outgoing only, for functional
  * accesse to virtual addresses. */
-FSTranslatingPortProxy *virtProxy;
-SETranslatingPortProxy *proxy;
+PortProxy *virtProxy;

   public:
 /*

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/18580
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ie4ae1f0ffbf9448f6730f9c7d072bc85d6d423da
Gerrit-Change-Number: 18580
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
Gerrit-MessageType: newchange
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in gem5/gem5[master]: mem: Add a readString method to the PortProxy which takes a char *.

[Gabe Black (Gerrit)]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18574



Change subject: mem: Add a readString method to the PortProxy which takes a  
char *.

..

mem: Add a readString method to the PortProxy which takes a char *.

This version takes a char * instead of an std::string &, and a maximum
length to fill in like strncpy. This is intended to be a replacement
for the CopyStringOut function.

Change-Id: Ib661924a3fa7e05761d572ffecbe2c0cc8659d48
---
M src/mem/port_proxy.cc
M src/mem/port_proxy.hh
2 files changed, 34 insertions(+), 0 deletions(-)



diff --git a/src/mem/port_proxy.cc b/src/mem/port_proxy.cc
index f56bfeb..60f79e3 100644
--- a/src/mem/port_proxy.cc
+++ b/src/mem/port_proxy.cc
@@ -110,3 +110,18 @@
 str += c;
 }
 }
+
+bool
+PortProxy::tryReadString(char *str, Addr addr, size_t maxlen) const
+{
+assert(maxlen);
+while (maxlen--) {
+if (!tryReadBlob(addr++, str, 1))
+return false;
+if (!*str++)
+return true;
+}
+// We ran out of room, so back up and add a terminator.
+*--str = '\0';
+return true;
+}
diff --git a/src/mem/port_proxy.hh b/src/mem/port_proxy.hh
index 469273f..61a2071 100644
--- a/src/mem/port_proxy.hh
+++ b/src/mem/port_proxy.hh
@@ -59,6 +59,8 @@
 #ifndef __MEM_PORT_PROXY_HH__
 #define __MEM_PORT_PROXY_HH__

+#include 
+
 #include "mem/port.hh"
 #include "sim/byteswap.hh"

@@ -242,6 +244,23 @@
 if (!tryReadString(str, addr))
 fatal("readString(%#x, ...) failed", addr);
 }
+
+/**
+ * Reads the string at guest address addr into the char * str, reading  
up

+ * to maxlen characters. The last character read is always a nul
+ * terminator. Returns true on success and false on failure.
+ */
+bool tryReadString(char *str, Addr addr, size_t maxlen) const;
+
+/**
+ * Same as tryReadString, but insists on success.
+ */
+void
+readString(char *str, Addr addr, size_t maxlen) const
+{
+if (!tryReadString(str, addr, maxlen))
+fatal("readString(%#x, ...) failed", addr);
+}
 };



--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/18574
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ib661924a3fa7e05761d572ffecbe2c0cc8659d48
Gerrit-Change-Number: 18574
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
Gerrit-MessageType: newchange
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in gem5/gem5[master]: tests: There is no architecture called "timing".

[Gabe Black (Gerrit)]

Gabe Black has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18568 )


Change subject: tests: There is no architecture called "timing".
..

tests: There is no architecture called "timing".

I'm sure that's supposed to be "x86". By switching it over, the x86
regression tests became runnable again.

Change-Id: I9505703a0be71047ef3dd312ae83e76c2b32fdb5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18568
Reviewed-by: Daniel Carvalho 
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Anthony Gutierrez 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M tests/testing/tests.py
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Anthony Gutierrez: Looks good to me, approved
  Daniel Carvalho: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/tests/testing/tests.py b/tests/testing/tests.py
index 00f3e5a..df8ef36 100755
--- a/tests/testing/tests.py
+++ b/tests/testing/tests.py
@@ -126,7 +126,7 @@
 't1000-simple-x86',
 ),

-("timing", None) : (
+("x86", None) : (
 'pc-simple-atomic',
 'pc-simple-timing',
 'pc-o3-timing',

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/18568
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I9505703a0be71047ef3dd312ae83e76c2b32fdb5
Gerrit-Change-Number: 18568
Gerrit-PatchSet: 2
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Anthony Gutierrez 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in gem5/gem5[master]: sim-se: add eventfd system call

[Brandon Potter (Gerrit)]

Hello Ciro Santilli, Alexandru Duțu, John Alsop, Andrea Mondelli,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/12125

to look at the new patch set (#23).

Change subject: sim-se: add eventfd system call
..

sim-se: add eventfd system call

Change-Id: I7aeb4fe808d0c8f2fb8041e3662d330d8458f09c
---
M src/arch/x86/linux/process.cc
M src/sim/fd_entry.hh
M src/sim/syscall_emul.cc
M src/sim/syscall_emul.hh
4 files changed, 64 insertions(+), 33 deletions(-)


--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/12125
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I7aeb4fe808d0c8f2fb8041e3662d330d8458f09c
Gerrit-Change-Number: 12125
Gerrit-PatchSet: 23
Gerrit-Owner: Brandon Potter 
Gerrit-Reviewer: Alexandru Duțu 
Gerrit-Reviewer: Andrea Mondelli 
Gerrit-Reviewer: Brandon Potter 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: John Alsop 
Gerrit-CC: Andreas Sandberg 
Gerrit-CC: Jason Lowe-Power 
Gerrit-MessageType: newpatchset
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in gem5/gem5[master]: dev-arm: Store a PhysProxy port in Gicv3Redist

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18600 )


Change subject: dev-arm: Store a PhysProxy port in Gicv3Redist
..

dev-arm: Store a PhysProxy port in Gicv3Redist

This spares us from retrieving the TC pointer every time we want to
write/read to memory (LPIs)

Change-Id: Iad76b5e69188fa0ac5c6777a3b2664b0fc66b12f
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18600
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/dev/arm/gic_v3_redistributor.cc
M src/dev/arm/gic_v3_redistributor.hh
2 files changed, 16 insertions(+), 15 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/dev/arm/gic_v3_redistributor.cc  
b/src/dev/arm/gic_v3_redistributor.cc

index 0ee6b8a..de6bd63 100644
--- a/src/dev/arm/gic_v3_redistributor.cc
+++ b/src/dev/arm/gic_v3_redistributor.cc
@@ -44,6 +44,7 @@
   distributor(nullptr),
   cpuInterface(nullptr),
   cpuId(cpu_id),
+  memProxy(nullptr),
   irqGroup(Gicv3::SGI_MAX + Gicv3::PPI_MAX),
   irqEnabled(Gicv3::SGI_MAX + Gicv3::PPI_MAX),
   irqPending(Gicv3::SGI_MAX + Gicv3::PPI_MAX),
@@ -61,6 +62,8 @@
 {
 distributor = gic->getDistributor();
 cpuInterface = gic->getCPUInterface(cpuId);
+
+memProxy = >getSystem()->physProxy;
 }

 void
@@ -804,7 +807,6 @@

 // Check LPIs
 if (EnableLPIs) {
-ThreadContext * tc = gic->getSystem()->getThreadContext(cpuId);

 const uint32_t largest_lpi_id = 1 << (lpiIDBits + 1);
 const uint32_t number_lpis = largest_lpi_id - SMALLEST_LPI_ID + 1;
@@ -812,13 +814,13 @@
 uint8_t lpi_pending_table[largest_lpi_id / 8];
 uint8_t lpi_config_table[number_lpis];

-tc->getPhysProxy().readBlob(lpiPendingTablePtr,
-(uint8_t *) lpi_pending_table,
-sizeof(lpi_pending_table));
+memProxy->readBlob(lpiPendingTablePtr,
+   (uint8_t *) lpi_pending_table,
+   sizeof(lpi_pending_table));

-tc->getPhysProxy().readBlob(lpiConfigurationTablePtr,
-(uint8_t*) lpi_config_table,
-sizeof(lpi_config_table));
+memProxy->readBlob(lpiConfigurationTablePtr,
+   (uint8_t*) lpi_config_table,
+   sizeof(lpi_config_table));

 for (int lpi_id = SMALLEST_LPI_ID; lpi_id < largest_lpi_id;
  lpi_id++) {
@@ -866,10 +868,9 @@
 Addr lpi_pending_entry_ptr = lpiPendingTablePtr + (lpi_id / 8);

 uint8_t lpi_pending_entry;
-ThreadContext * tc = gic->getSystem()->getThreadContext(cpuId);
-tc->getPhysProxy().readBlob(lpi_pending_entry_ptr,
-(uint8_t*) _pending_entry,
-sizeof(lpi_pending_entry));
+memProxy->readBlob(lpi_pending_entry_ptr,
+   (uint8_t*) _pending_entry,
+   sizeof(lpi_pending_entry));

 return lpi_pending_entry;
 }
@@ -879,10 +880,9 @@
 {
 Addr lpi_pending_entry_ptr = lpiPendingTablePtr + (lpi_id / 8);

-ThreadContext * tc = gic->getSystem()->getThreadContext(cpuId);
-tc->getPhysProxy().writeBlob(lpi_pending_entry_ptr,
-(uint8_t*) _pending_entry,
-sizeof(lpi_pending_entry));
+memProxy->writeBlob(lpi_pending_entry_ptr,
+(uint8_t*) _pending_entry,
+sizeof(lpi_pending_entry));
 }

 bool
diff --git a/src/dev/arm/gic_v3_redistributor.hh  
b/src/dev/arm/gic_v3_redistributor.hh

index 6aff91d..8d7de3d 100644
--- a/src/dev/arm/gic_v3_redistributor.hh
+++ b/src/dev/arm/gic_v3_redistributor.hh
@@ -51,6 +51,7 @@
 Gicv3Distributor * distributor;
 Gicv3CPUInterface * cpuInterface;
 uint32_t cpuId;
+PortProxy * memProxy;

 /*
  * GICv3 defines 2 contiguous 64KB frames for each redistributor.

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/18600
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Iad76b5e69188fa0ac5c6777a3b2664b0fc66b12f
Gerrit-Change-Number: 18600
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in gem5/gem5[master]: dev-arm: Add named variable for GICD_TYPER.IDBits

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18599 )


Change subject: dev-arm: Add named variable for GICD_TYPER.IDBits
..

dev-arm: Add named variable for GICD_TYPER.IDBits

This could be used by other GICv3 components to query the maximum
number of implemented interrupt identifiers

Change-Id: I132e50de331aea22523260bcefba7e961b53eccd
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18599
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/dev/arm/gic_v3_distributor.cc
M src/dev/arm/gic_v3_distributor.hh
2 files changed, 2 insertions(+), 1 deletion(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/dev/arm/gic_v3_distributor.cc  
b/src/dev/arm/gic_v3_distributor.cc

index f261b29..a048d18 100644
--- a/src/dev/arm/gic_v3_distributor.cc
+++ b/src/dev/arm/gic_v3_distributor.cc
@@ -472,7 +472,7 @@
 {
 int max_spi_int_id = itLines - 1;
 int it_lines_number = ceil((max_spi_int_id + 1) / 32.0) - 1;
-return (1 << 26) | (1 << 25) | (1 << 24) | (0xf << 19) |
+return (1 << 26) | (1 << 25) | (1 << 24) | (IDBITS << 19) |
 (1 << 17) | (gic->getSystem()->haveSecurity() << 10) |
 (it_lines_number << 0);
 }
diff --git a/src/dev/arm/gic_v3_distributor.hh  
b/src/dev/arm/gic_v3_distributor.hh

index 86e53a3..c231438 100644
--- a/src/dev/arm/gic_v3_distributor.hh
+++ b/src/dev/arm/gic_v3_distributor.hh
@@ -140,6 +140,7 @@
   public:

 static const uint32_t ADDR_RANGE_SIZE = 0x1;
+static const uint32_t IDBITS = 0xf;

   protected:


--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/18599
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I132e50de331aea22523260bcefba7e961b53eccd
Gerrit-Change-Number: 18599
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in gem5/gem5[master]: dev-arm: Add several LPI methods in Gicv3Redistributor

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18596 )


Change subject: dev-arm: Add several LPI methods in Gicv3Redistributor
..

dev-arm: Add several LPI methods in Gicv3Redistributor

Refactoring the existing in code in smaller methods will be crucial when
adding the ITS module, which is a client for the redistributor class and
which will require it to take different actions depending on the command
it receives from software.

List of methods:

* read/writeEntryLPI
Reading/Writing a byte from the LPI pending table

* isPendingLPI
Checks if the pINTID LPI is set. Knowing if an LPI is set is needed by
the MOVI command, which is transfering the pending state from one
redistributor to the other only if the LPI is pending.

Change-Id: If14b1c28ff7f2aa20b12dcd822bf6a490cbe0270
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18596
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/dev/arm/gic_v3_redistributor.cc
M src/dev/arm/gic_v3_redistributor.hh
2 files changed, 51 insertions(+), 9 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/dev/arm/gic_v3_redistributor.cc  
b/src/dev/arm/gic_v3_redistributor.cc

index 79de7d5..0ee6b8a 100644
--- a/src/dev/arm/gic_v3_redistributor.cc
+++ b/src/dev/arm/gic_v3_redistributor.cc
@@ -860,6 +860,43 @@
 }
 }

+uint8_t
+Gicv3Redistributor::readEntryLPI(uint32_t lpi_id)
+{
+Addr lpi_pending_entry_ptr = lpiPendingTablePtr + (lpi_id / 8);
+
+uint8_t lpi_pending_entry;
+ThreadContext * tc = gic->getSystem()->getThreadContext(cpuId);
+tc->getPhysProxy().readBlob(lpi_pending_entry_ptr,
+(uint8_t*) _pending_entry,
+sizeof(lpi_pending_entry));
+
+return lpi_pending_entry;
+}
+
+void
+Gicv3Redistributor::writeEntryLPI(uint32_t lpi_id, uint8_t  
lpi_pending_entry)

+{
+Addr lpi_pending_entry_ptr = lpiPendingTablePtr + (lpi_id / 8);
+
+ThreadContext * tc = gic->getSystem()->getThreadContext(cpuId);
+tc->getPhysProxy().writeBlob(lpi_pending_entry_ptr,
+(uint8_t*) _pending_entry,
+sizeof(lpi_pending_entry));
+}
+
+bool
+Gicv3Redistributor::isPendingLPI(uint32_t lpi_id)
+{
+// Fetch the LPI pending entry from memory
+uint8_t lpi_pending_entry = readEntryLPI(lpi_id);
+
+uint8_t lpi_pending_entry_bit_position = lpi_id % 8;
+bool is_set = lpi_pending_entry & (1 <<  
lpi_pending_entry_bit_position);

+
+return is_set;
+}
+
 void
 Gicv3Redistributor::setClrLPI(uint64_t data, bool set)
 {
@@ -878,12 +915,9 @@
 return;
 }

-Addr lpi_pending_entry_ptr = lpiPendingTablePtr + (lpi_id / 8);
-uint8_t lpi_pending_entry;
-ThreadContext * tc = gic->getSystem()->getThreadContext(cpuId);
-tc->getPhysProxy().readBlob(lpi_pending_entry_ptr,
-(uint8_t*) _pending_entry,
-sizeof(lpi_pending_entry));
+// Fetch the LPI pending entry from memory
+uint8_t lpi_pending_entry = readEntryLPI(lpi_id);
+
 uint8_t lpi_pending_entry_bit_position = lpi_id % 8;
 bool is_set = lpi_pending_entry & (1 <<  
lpi_pending_entry_bit_position);


@@ -905,9 +939,8 @@
 lpi_pending_entry &= ~(1 << (lpi_pending_entry_bit_position));
 }

-tc->getPhysProxy().writeBlob(lpi_pending_entry_ptr,
-(uint8_t*) _pending_entry,
-sizeof(lpi_pending_entry));
+writeEntryLPI(lpi_id, lpi_pending_entry);
+
 updateAndInformCPUInterface();
 }

diff --git a/src/dev/arm/gic_v3_redistributor.hh  
b/src/dev/arm/gic_v3_redistributor.hh

index 0e99b74..6aff91d 100644
--- a/src/dev/arm/gic_v3_redistributor.hh
+++ b/src/dev/arm/gic_v3_redistributor.hh
@@ -190,8 +190,17 @@
 return cpuInterface;
 }

+uint32_t
+processorNumber() const
+{
+return cpuId;
+}
+
 Gicv3::GroupId getIntGroup(int int_id) const;
 Gicv3::IntStatus intStatus(uint32_t int_id) const;
+uint8_t readEntryLPI(uint32_t intid);
+void writeEntryLPI(uint32_t intid, uint8_t lpi_entry);
+bool isPendingLPI(uint32_t intid);
 void setClrLPI(uint64_t data, bool set);
 void reset();
 void sendSGI(uint32_t int_id, Gicv3::GroupId group, bool ns);

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/18596
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: If14b1c28ff7f2aa20b12dcd822bf6a490cbe0270
Gerrit-Change-Number: 18596
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
___
gem5-dev mailing list

[gem5-dev] Change in gem5/gem5[master]: dev-arm: Get a Gicv3Redistributor ptr from phys address

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18597 )


Change subject: dev-arm: Get a Gicv3Redistributor ptr from phys address
..

dev-arm: Get a Gicv3Redistributor ptr from phys address

The patch is adding the following method to Gicv3:

* Gicv3::getRedistributorByAddr
This will be needed by the ITS when trying to select the target
redistributor after decoding the collection table entry (RDBase).

Change-Id: I40e2c155f2fdc8ca6d3c20ff7a27702e02499f20
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18597
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/dev/arm/gic_v3.cc
M src/dev/arm/gic_v3.hh
2 files changed, 33 insertions(+), 20 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/dev/arm/gic_v3.cc b/src/dev/arm/gic_v3.cc
index 2832d33..9004f65 100644
--- a/src/dev/arm/gic_v3.cc
+++ b/src/dev/arm/gic_v3.cc
@@ -110,19 +110,15 @@
 "size %d is_secure_access %d (value %#x)\n",
 pkt->req->contextId(), daddr, size, is_secure_access,  
resp);

 } else if (redistRange.contains(addr)) {
-Addr daddr = addr - redistRange.start();
-uint32_t redistributor_id =
-daddr / redistSize;
-daddr = daddr % redistSize;
-panic_if(redistributor_id >= redistributors.size(),
- "Invalid redistributor_id!");
-panic_if(!redistributors[redistributor_id], "Redistributor is  
null!");

-resp = redistributors[redistributor_id]->read(daddr, size,
-  is_secure_access);
+Addr daddr = (addr - redistRange.start()) % redistSize;
+
+Gicv3Redistributor *redist = getRedistributorByAddr(addr);
+resp = redist->read(daddr, size, is_secure_access);
+
 delay = params()->redist_pio_delay;
 DPRINTF(GIC, "Gicv3::read(): (redistributor %d) context_id %d "
 "register %#x size %d is_secure_access %d (value %#x)\n",
-redistributor_id, pkt->req->contextId(), daddr, size,
+redist->processorNumber(), pkt->req->contextId(), daddr,  
size,

 is_secure_access, resp);
 } else {
 panic("Gicv3::read(): unknown address %#x\n", addr);
@@ -151,19 +147,16 @@
 distributor->write(daddr, data, size, is_secure_access);
 delay = params()->dist_pio_delay;
 } else if (redistRange.contains(addr)) {
-Addr daddr = addr - redistRange.start();
-uint32_t redistributor_id =
-daddr / redistSize;
-daddr = daddr % redistSize;
-panic_if(redistributor_id >= redistributors.size(),
- "Invalid redistributor_id!");
-panic_if(!redistributors[redistributor_id], "Redistributor is  
null!");

+Addr daddr = (addr - redistRange.start()) % redistSize;
+
+Gicv3Redistributor *redist = getRedistributorByAddr(addr);
 DPRINTF(GIC, "Gicv3::write(): (redistributor %d) context_id %d "
 "register %#x size %d is_secure_access %d value %#x\n",
-redistributor_id, pkt->req->contextId(), daddr, size,
+redist->processorNumber(), pkt->req->contextId(), daddr,  
size,

 is_secure_access, data);
-redistributors[redistributor_id]->write(daddr, data, size,
-is_secure_access);
+
+redist->write(daddr, data, size, is_secure_access);
+
 delay = params()->redist_pio_delay;
 } else {
 panic("Gicv3::write(): unknown address %#x\n", addr);
@@ -228,6 +221,22 @@
 return nullptr;
 }

+Gicv3Redistributor *
+Gicv3::getRedistributorByAddr(Addr addr) const
+{
+panic_if(!redistRange.contains(addr),
+"Address not pointing to a valid redistributor\n");
+
+const Addr daddr = addr - redistRange.start();
+const uint32_t redistributor_id = daddr / redistSize;
+
+panic_if(redistributor_id >= redistributors.size(),
+ "Invalid redistributor_id!");
+panic_if(!redistributors[redistributor_id], "Redistributor is null!");
+
+return redistributors[redistributor_id];
+}
+
 void
 Gicv3::serialize(CheckpointOut & cp) const
 {
diff --git a/src/dev/arm/gic_v3.hh b/src/dev/arm/gic_v3.hh
index 48cc520..5a13a74 100644
--- a/src/dev/arm/gic_v3.hh
+++ b/src/dev/arm/gic_v3.hh
@@ -141,6 +141,10 @@

 Gicv3Redistributor *
 getRedistributorByAffinity(uint32_t affinity) const;
+
+Gicv3Redistributor *
+getRedistributorByAddr(Addr address) const;
+
 void postInt(uint32_t cpu, ArmISA::InterruptTypes int_type);
 };


--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/18597
To unsubscribe, or for help writing mail filters, 

[gem5-dev] Change in gem5/gem5[master]: dev-arm: Read correct version of ICC_BPR register

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18598 )


Change subject: dev-arm: Read correct version of ICC_BPR register
..

dev-arm: Read correct version of ICC_BPR register

Some methods like groupPriorityMask check for the value of binary point
registers. Those registers have a minimum value.  Writing to those
register is taking this into account, but the problem with the minimum
value arises when the value is checked before sw is writing to them.
In this case the minimum value won't be considered if the read is
directly forwarded to the ISA class.

Change-Id: Id432a37f1634b02bc478d65c52ffb88323d4bb77
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18598
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/dev/arm/gic_v3_cpu_interface.cc
M src/dev/arm/gic_v3_cpu_interface.hh
2 files changed, 11 insertions(+), 6 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/dev/arm/gic_v3_cpu_interface.cc  
b/src/dev/arm/gic_v3_cpu_interface.cc

index 3598f34..4a0a8e3 100644
--- a/src/dev/arm/gic_v3_cpu_interface.cc
+++ b/src/dev/arm/gic_v3_cpu_interface.cc
@@ -36,6 +36,9 @@
 #include "dev/arm/gic_v3_distributor.hh"
 #include "dev/arm/gic_v3_redistributor.hh"

+const uint8_t Gicv3CPUInterface::GIC_MIN_BPR;
+const uint8_t Gicv3CPUInterface::GIC_MIN_BPR_NS;
+
 Gicv3CPUInterface::Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id)
 : BaseISADevice(),
   gic(gic),
@@ -322,6 +325,8 @@
 bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR0_EL1);
 } else {
 bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR1_EL1);
+bpr = std::max(bpr, group == Gicv3::G1S ?
+GIC_MIN_BPR : GIC_MIN_BPR_NS);
 }

 if (sat_inc) {
@@ -1844,7 +1849,7 @@
  * GroupBits() Pseudocode from spec.
  */
 uint32_t
-Gicv3CPUInterface::groupPriorityMask(Gicv3::GroupId group) const
+Gicv3CPUInterface::groupPriorityMask(Gicv3::GroupId group)
 {
 ICC_CTLR_EL1 icc_ctlr_el1_s =
 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S);
@@ -1859,9 +1864,9 @@
 int bpr;

 if (group == Gicv3::G0S) {
-bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR0_EL1) & 0x7;
+bpr = readMiscReg(MISCREG_ICC_BPR0_EL1) & 0x7;
 } else {
-bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR1_EL1) & 0x7;
+bpr = readMiscReg(MISCREG_ICC_BPR1_EL1) & 0x7;
 }

 if (group == Gicv3::G1NS) {
@@ -2165,7 +2170,7 @@
 }

 bool
-Gicv3CPUInterface::hppiCanPreempt() const
+Gicv3CPUInterface::hppiCanPreempt()
 {
 if (hppi.prio == 0xff) {
 // there is no pending interrupt
diff --git a/src/dev/arm/gic_v3_cpu_interface.hh  
b/src/dev/arm/gic_v3_cpu_interface.hh

index 931eb1d..e6dcb51 100644
--- a/src/dev/arm/gic_v3_cpu_interface.hh
+++ b/src/dev/arm/gic_v3_cpu_interface.hh
@@ -296,11 +296,11 @@
 uint32_t getHPPIR1() const;
 int getHPPVILR() const;
 bool groupEnabled(Gicv3::GroupId group) const;
-uint32_t groupPriorityMask(Gicv3::GroupId group) const;
+uint32_t groupPriorityMask(Gicv3::GroupId group);
 bool haveEL(ArmISA::ExceptionLevel el) const;
 int highestActiveGroup() const;
 uint8_t highestActivePriority() const;
-bool hppiCanPreempt() const;
+bool hppiCanPreempt();
 bool hppviCanPreempt(int lrIdx) const;
 bool inSecureState() const;
 ArmISA::InterruptTypes intSignalType(Gicv3::GroupId group) const;

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/18598
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Id432a37f1634b02bc478d65c52ffb88323d4bb77
Gerrit-Change-Number: 18598
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in gem5/gem5[master]: dev-arm: Take LPIs into account when interacting with CPUIF regs

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18595 )


Change subject: dev-arm: Take LPIs into account when interacting with CPUIF  
regs

..

dev-arm: Take LPIs into account when interacting with CPUIF regs

Previous code was not handling LPIs when it came to
activation/deactivation of interrupts.

Change-Id: Ie38f83c66afdc42132679d7e2e5823990f1710d0
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18595
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/dev/arm/gic_v3_cpu_interface.cc
M src/dev/arm/gic_v3_redistributor.cc
2 files changed, 15 insertions(+), 6 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/dev/arm/gic_v3_cpu_interface.cc  
b/src/dev/arm/gic_v3_cpu_interface.cc

index 577442e..3598f34 100644
--- a/src/dev/arm/gic_v3_cpu_interface.cc
+++ b/src/dev/arm/gic_v3_cpu_interface.cc
@@ -409,7 +409,8 @@
   int_id = getHPPIR0();

   // avoid activation for special interrupts
-  if (int_id < Gicv3::INTID_SECURE) {
+  if (int_id < Gicv3::INTID_SECURE ||
+  int_id >= Gicv3Redistributor::SMALLEST_LPI_ID) {
   activateIRQ(int_id, hppi.group);
   }
   } else {
@@ -464,7 +465,8 @@
   int_id = getHPPIR1();

   // avoid activation for special interrupts
-  if (int_id < Gicv3::INTID_SECURE) {
+  if (int_id < Gicv3::INTID_SECURE ||
+  int_id >= Gicv3Redistributor::SMALLEST_LPI_ID) {
   activateIRQ(int_id, hppi.group);
   }
   } else {
@@ -778,7 +780,8 @@
   int int_id = val & 0xff;

   // avoid activation for special interrupts
-  if (int_id >= Gicv3::INTID_SECURE) {
+  if (int_id >= Gicv3::INTID_SECURE &&
+  int_id <= Gicv3::INTID_SPURIOUS) {
   return;
   }

@@ -847,7 +850,8 @@
   int int_id = val & 0xff;

   // avoid deactivation for special interrupts
-  if (int_id >= Gicv3::INTID_SECURE) {
+  if (int_id >= Gicv3::INTID_SECURE &&
+  int_id <= Gicv3::INTID_SPURIOUS) {
   return;
   }

@@ -1770,6 +1774,9 @@
 // SPI, distributor
 distributor->activateIRQ(int_id);
 distributor->updateAndInformCPUInterfaces();
+} else if (int_id >= Gicv3Redistributor::SMALLEST_LPI_ID) {
+// LPI, Redistributor
+redistributor->setClrLPI(int_id, false);
 }
 }

@@ -1806,7 +1813,8 @@
 distributor->deactivateIRQ(int_id);
 distributor->updateAndInformCPUInterfaces();
 } else {
-return;
+// LPI, redistributor, shouldn't deactivate
+redistributor->updateAndInformCPUInterface();
 }
 }

diff --git a/src/dev/arm/gic_v3_redistributor.cc  
b/src/dev/arm/gic_v3_redistributor.cc

index e22d830..79de7d5 100644
--- a/src/dev/arm/gic_v3_redistributor.cc
+++ b/src/dev/arm/gic_v3_redistributor.cc
@@ -854,7 +854,8 @@
 }

 if (!new_hppi && cpuInterface->hppi.prio != 0xff &&
-cpuInterface->hppi.intid < Gicv3::SGI_MAX + Gicv3::PPI_MAX) {
+(cpuInterface->hppi.intid < Gicv3::SGI_MAX + Gicv3::PPI_MAX ||
+ cpuInterface->hppi.intid > SMALLEST_LPI_ID)) {
 distributor->fullUpdate();
 }
 }

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/18595
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ie38f83c66afdc42132679d7e2e5823990f1710d0
Gerrit-Change-Number: 18595
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

Re: [gem5-dev] Internship at Arm

[Giacomo Travaglini]

+ Juha on CC

From: gem5-dev  on behalf of Giacomo Travaglini 

Sent: 02 May 2019 12:56
To: gem5 Developer List
Cc: Reiley Jeyapaul
Subject: [gem5-dev] Internship at Arm

Hello devs,

We are looking for internship candidates to work on gem5 at Arm. If you know 
(or are one yourself!) of any keen students with gem5 experience (this is 
essential) who may want to do an internship (start dates flexible), please ask 
them to get in touch with either Juha or Reiley (in cc).

The intern can be based either in the UK or US, and paid according to standard 
Arm intern salary.

Regards,

Giacomo

IMPORTANT NOTICE: The contents of this email and any attachments are 
confidential and may also be privileged. If you are not the intended recipient, 
please notify the sender immediately and do not disclose the contents to any 
other person, use it for any purpose, or store or copy the information in any 
medium. Thank you.
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
IMPORTANT NOTICE: The contents of this email and any attachments are 
confidential and may also be privileged. If you are not the intended recipient, 
please notify the sender immediately and do not disclose the contents to any 
other person, use it for any purpose, or store or copy the information in any 
medium. Thank you.
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in gem5/gem5[master]: mem-cache: Mark block as dirty after a SWPrefetchEXResp

[Nikos Nikoleris (Gerrit)]

Nikos Nikoleris has uploaded a new patch set (#2). (  
https://gem5-review.googlesource.com/c/public/gem5/+/17729 )


Change subject: mem-cache: Mark block as dirty after a SWPrefetchEXResp
..

mem-cache: Mark block as dirty after a SWPrefetchEXResp

This is a workaround for a bug introduced from the change:
59e3585a8 arch-arm: We add PRFM PST instruction for arm
which can cause deadlocks in the memory system.

The design of the classic memory system in gem5 makes the folloing two
assumptions:
* A cache that fetches a block with an intention to modify it, becomes
  the point of ordering and therefore commits to respond to any snoop
  requests [1].
* A cache that fetches an exclusive copy of the block, does so with
  the intention to modify it [2]. Immediately after it receives the
  block, it will write to it and mark it as dirty. As the point of
  ordering, it responds to any outstanding snoops.

The current implementation of prefetch exclusive request breaks the
second assumption. A cache can fetch an exclusive block without an
immediate intention to modify it. If the block is not modified, it
will not be marked as dirty. However, the cache has committed to
respond to outstanding snoops, and if the block is clean it
won't. This can result in deadlocks where a snoop gets stuck waiting
for responses.

One solution (implemented by this patch) is to unconditionally mark
the block dirty when filling due to a prefetch exclusive request.
This makes the PrefetchExReq behave like a WriteReq. However, as it
may mark as dirty a clean block, it creates the requirement for an
uncessary WritebackDirty in the future. In practice, this shouldn't be
a big problem unless the application is unnecessarily using prefetch
exclusive instructions.

Other solutions, would require deeper changes to the design of the
memory system to handle this properly.

[1]: When a cache commits to respond, it "informs" the xbar/PoC (point
of coherence) and the other caches of its intention to respond. As a
result the request will not be send to the main memory.
[2]: In fact the assumption is that in the needsWritable MSHR there is
at least one WriteReq before any snoops from other caches.

Change-Id: I378d3c0dadf25fc52e430b67102347b44d2f18ea
Signed-off-by: Nikos Nikoleris 
---
M src/mem/cache/base.cc
1 file changed, 26 insertions(+), 1 deletion(-)


--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/17729
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I378d3c0dadf25fc52e430b67102347b44d2f18ea
Gerrit-Change-Number: 17729
Gerrit-PatchSet: 2
Gerrit-Owner: Nikos Nikoleris 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-CC: Daniel Carvalho 
Gerrit-CC: Jason Lowe-Power 
Gerrit-MessageType: newpatchset
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

Re: [gem5-dev] Continuous integration is live!

[Giacomo Travaglini]

Hi Jason,

I understand; Another thing I would like to ask:

Which script is building gem5 in jenkins? Ideally it would be nice to build 
with BOTH gcc and clang (so that we avoid
periodic "fix clang build" patches. I would also make the version 
configurable/visible from the script so that
we can track changes in compiler support and people can compare failures in 
case they managed to build
seamlessly on their local workspace

Giacomo

From: Jason Lowe-Power 
Sent: 26 April 2019 17:49
To: Giacomo Travaglini
Cc: gem5 Developer List
Subject: Re: [gem5-dev] Continuous integration is live!

Hi Giacomo,

You *do* have permission :). Anyone can modify tests/jenkins/presubmit.cfg and 
presubmit.sh. In fact, if you look at the history of the presubmit.sh, it *was* 
running the old tests. See 
https://gem5-review.googlesource.com/c/testing/jenkins-gem5-prod/+/18028, for 
instance.

The problem is that we can't distribute most of the binaries (e.g., SPEC 
binaries). We could probably upload them to a private location on the Google 
Cloud and have jenkins consume them that way, but I believe that will be more 
work than it's worth.

I personally believe that putting effort into porting tests is more worth 
everyone's time than trying to get the old tests to run, but that's just my 
opinion. I'm happy to merge changes to run the old tests. I personally believe 
we should only merge tests into the verification tester which everyone can run 
locally, but I'm open to proprietary tests, especially in the short term if we 
have a plan to make them not proprietary.

Cheers,
Jason

On Fri, Apr 26, 2019 at 9:36 AM Giacomo Travaglini 
mailto:giacomo.travagl...@arm.com>> wrote:
Hi Jason,

It's really amazing that we have a testing framework in place, thanks for your 
effort!
At the moment as far as I can tell we are only running tests registered within 
the new
testing library.

I was wondering if we could temporarily enable the system to run legacy quick 
regressions as well,
while waiting for porting those to the new library. I guess it is something 
that shouldn't require a lot of work

(just calling .util/regress I guess)

I am saying this since a patch recently merged broke some syscall emulation 
tests and I think it would
be beneficial for us to run the entire test suite straightaway while porting 
tests manually.
I could even handle it myself if I had permission to configure the system.

Let me know your thoughts,

Giacomo


From: gem5-dev mailto:gem5-dev-boun...@gem5.org>> on 
behalf of Jason Lowe-Power mailto:ja...@lowepower.com>>
Sent: 16 April 2019 16:30
To: gem5 Developer List; Rahul Thakur
Subject: [gem5-dev] Continuous integration is live!

Hi all,

We now have initial support for continuous integration testing! We should
all thank Google for donating the CPU time and infrastructure to run these
tests. Specifically, Rahul Thakur has been incredibly helpful for the past
two years in getting this off the ground. Thanks, Rahul and the rest of the
team at Google who has been helping us set this up!

Now, if you submit a patch to gerrit and receive a maintainer +1, "kokoro"
will kick off a build / test of gem5. Once that is complete, you will
receive a verified +1. If it fails, you will receive a verified -1. The
logs can be viewed by anyone once the job is completed by following the
link posted by kokoro (the https://source.cloud.google.com, not the sponge
link). You can see an example on a patch I recently submitted here:
https://gem5-review.googlesource.com/c/public/gem5/+/18068. Note that the
tests take a couple of hours to run. However, I believe there is no limit
to the number of different changes that can be tested at the same time.

Soon, we are going to enable commit gating with the verified +1 tag. I.e.,
you will have to pass the continuous integration tests before you can
commit your code.

Note that this is using the "new" testing infrastructure. You can run this
locally by running "./main.py" in the tests directory. More information
about how to run tests and add tests can be found in the TESTING.md file.
If there are any questions/issues do not hesitate to contact me or the
list. The documentation for the new infrastructure can still be improved.
Right now, we're running about 30 tests. You can find the tests that we are
running in the tests/gem5 directory.

We are looking for volunteers to help us port more of the old tests to the
new infrastructure and to expand the coverage of our tests. I'm happy to
help anyone get started on this and point out which tests still need to be
migrated, where our biggest coverage holes are, etc.

Cheers,
Jason
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
IMPORTANT NOTICE: The contents of this email and any attachments are 
confidential and may also be privileged. If you are not the intended 

[gem5-dev] Change in gem5/gem5[master]: dev-arm: Disable LPI Configuration Table caching

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18593 )


Change subject: dev-arm: Disable LPI Configuration Table caching
..

dev-arm: Disable LPI Configuration Table caching

This is done since caching is not done correctly, and we don't care for
now about performance degradations since the redistributor is using
PhysProxy ports.
Caching will make sense once the magical accesses will be replaced by
real atomic/timing transactions.

Change-Id: Iafe2a7843210111efc82c265bd0d5ec3cd9abb5a
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18593
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/dev/arm/gic_v3_redistributor.cc
M src/dev/arm/gic_v3_redistributor.hh
2 files changed, 20 insertions(+), 38 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/dev/arm/gic_v3_redistributor.cc  
b/src/dev/arm/gic_v3_redistributor.cc

index 2b73c57..be28d3a 100644
--- a/src/dev/arm/gic_v3_redistributor.cc
+++ b/src/dev/arm/gic_v3_redistributor.cc
@@ -675,9 +675,6 @@
   lpiIDBits = 0xf;
   }

-  uint32_t largest_lpi_id = 1 << (lpiIDBits + 1);
-  uint32_t number_lpis = largest_lpi_id - SMALLEST_LPI_ID + 1;
-  lpiConfigurationTable.resize(number_lpis);
   break;
   }

@@ -698,25 +695,12 @@
 break;

   case GICR_INVLPIR: { // Redistributor Invalidate LPI Register
-  uint32_t lpi_id = data & 0x;
-  uint32_t largest_lpi_id = 1 << (lpiIDBits + 1);
-
-  if (lpi_id > largest_lpi_id) {
-  return;
-  }
-
-  uint32_t lpi_table_entry_index = lpi_id - SMALLEST_LPI_ID;
-  invalLpiConfig(lpi_table_entry_index);
+  // Do nothing: no caching supported
   break;
   }

   case GICR_INVALLR: { // Redistributor Invalidate All Register
-  for (int lpi_table_entry_index = 0;
-   lpi_table_entry_index < lpiConfigurationTable.size();
-   lpi_table_entry_index++) {
-  invalLpiConfig(lpi_table_entry_index);
-  }
-
+  // Do nothing: no caching supported
   break;
   }

@@ -727,17 +711,6 @@
 }

 void
-Gicv3Redistributor::invalLpiConfig(uint32_t lpi_entry_index)
-{
-Addr lpi_table_entry_ptr = lpiConfigurationTablePtr +
-lpi_entry_index * sizeof(LPIConfigurationTableEntry);
-ThreadContext * tc = gic->getSystem()->getThreadContext(cpuId);
-tc->getPhysProxy().readBlob(lpi_table_entry_ptr,
-(uint8_t*) [lpi_entry_index],
-sizeof(LPIConfigurationTableEntry));
-}
-
-void
 Gicv3Redistributor::sendPPInt(uint32_t int_id)
 {
 assert((int_id >= Gicv3::SGI_MAX) &&
@@ -831,13 +804,22 @@

 // Check LPIs
 if (EnableLPIs) {
-const uint32_t largest_lpi_id = 1 << (lpiIDBits + 1);
-char lpi_pending_table[largest_lpi_id / 8];
 ThreadContext * tc = gic->getSystem()->getThreadContext(cpuId);
+
+const uint32_t largest_lpi_id = 1 << (lpiIDBits + 1);
+const uint32_t number_lpis = largest_lpi_id - SMALLEST_LPI_ID + 1;
+
+uint8_t lpi_pending_table[largest_lpi_id / 8];
+uint8_t lpi_config_table[number_lpis];
+
 tc->getPhysProxy().readBlob(lpiPendingTablePtr,
 (uint8_t *) lpi_pending_table,
 sizeof(lpi_pending_table));

+tc->getPhysProxy().readBlob(lpiConfigurationTablePtr,
+(uint8_t*) lpi_config_table,
+sizeof(lpi_config_table));
+
 for (int lpi_id = SMALLEST_LPI_ID; lpi_id < largest_lpi_id;
  lpi_id++) {
 uint32_t lpi_pending_entry_byte = lpi_id / 8;
@@ -845,16 +827,19 @@
 bool lpi_is_pending =  
lpi_pending_table[lpi_pending_entry_byte] &

   1 << lpi_pending_entry_bit_position;
 uint32_t lpi_configuration_entry_index = lpi_id -  
SMALLEST_LPI_ID;

-bool lpi_is_enable =
- 
lpiConfigurationTable[lpi_configuration_entry_index].enable;

+
+LPIConfigurationTableEntry config_entry =
+lpi_config_table[lpi_configuration_entry_index];
+
+bool lpi_is_enable = config_entry.enable;
+
 // LPIs are always Non-secure Group 1 interrupts,
 // in a system where two Security states are enabled.
 Gicv3::GroupId lpi_group = Gicv3::G1NS;
 bool group_enabled = distributor->groupEnabled(lpi_group);

 if (lpi_is_pending && lpi_is_enable && group_enabled) {
-uint8_t lpi_priority =
- 
lpiConfigurationTable[lpi_configuration_entry_index].priority;

+uint8_t 

[gem5-dev] Change in gem5/gem5[master]: dev-arm: Fix Bitwise operation in GICv3

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18589 )


Change subject: dev-arm: Fix Bitwise operation in GICv3
..

dev-arm: Fix Bitwise operation in GICv3

GICv3 LPI code is wrongly using the xor operator (^) in order to
evaluate powers of two.

Change-Id: Ib1131fd5940d334967a3741f8fd15d86625be356
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18589
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/dev/arm/gic_v3_redistributor.cc
1 file changed, 4 insertions(+), 4 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/dev/arm/gic_v3_redistributor.cc  
b/src/dev/arm/gic_v3_redistributor.cc

index eb5767a..348cd96 100644
--- a/src/dev/arm/gic_v3_redistributor.cc
+++ b/src/dev/arm/gic_v3_redistributor.cc
@@ -675,7 +675,7 @@
   lpiIDBits = 0xf;
   }

-  uint32_t largest_lpi_id = 2 ^ (lpiIDBits + 1);
+  uint32_t largest_lpi_id = 1 << (lpiIDBits + 1);
   uint32_t number_lpis = largest_lpi_id - SMALLEST_LPI_ID + 1;
   lpiConfigurationTable.resize(number_lpis);
   break;
@@ -699,7 +699,7 @@

   case GICR_INVLPIR: { // Redistributor Invalidate LPI Register
   uint32_t lpi_id = data & 0x;
-  uint32_t largest_lpi_id = 2 ^ (lpiIDBits + 1);
+  uint32_t largest_lpi_id = 1 << (lpiIDBits + 1);

   if (lpi_id > largest_lpi_id) {
   return;
@@ -830,7 +830,7 @@
 }

 // Check LPIs
-uint32_t largest_lpi_id = 2 ^ (lpiIDBits + 1);
+uint32_t largest_lpi_id = 1 << (lpiIDBits + 1);
 char lpi_pending_table[largest_lpi_id / 8];
 ThreadContext * tc = gic->getSystem()->getThreadContext(cpuId);
 tc->getVirtProxy().readBlob(lpiPendingTablePtr,
@@ -881,7 +881,7 @@
 }

 uint32_t lpi_id = data & 0x;
-uint32_t largest_lpi_id = 2 ^ (lpiIDBits + 1);
+uint32_t largest_lpi_id = 1 << (lpiIDBits + 1);

 if (lpi_id > largest_lpi_id) {
 // Writes to GICR_SETLPIR or GICR_CLRLPIR have not effect if

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/18589
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ib1131fd5940d334967a3741f8fd15d86625be356
Gerrit-Change-Number: 18589
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in gem5/gem5[master]: dev-arm: Check EnableLPIs before checking for pending LPIs

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18592 )


Change subject: dev-arm: Check EnableLPIs before checking for pending LPIs
..

dev-arm: Check EnableLPIs before checking for pending LPIs

Before reading the tables, GICR_PENDBASER and GICR_PROPBASER need to be
properly set, and those will have a consistent value only once sw
enables LPIs.

Change-Id: Ifb87944a491045e7a13ce7a280c555cb0c1e47f4
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18592
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/dev/arm/gic_v3_redistributor.cc
1 file changed, 31 insertions(+), 29 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/dev/arm/gic_v3_redistributor.cc  
b/src/dev/arm/gic_v3_redistributor.cc

index d5a405a..2b73c57 100644
--- a/src/dev/arm/gic_v3_redistributor.cc
+++ b/src/dev/arm/gic_v3_redistributor.cc
@@ -830,38 +830,40 @@
 }

 // Check LPIs
-const uint32_t largest_lpi_id = 1 << (lpiIDBits + 1);
-char lpi_pending_table[largest_lpi_id / 8];
-ThreadContext * tc = gic->getSystem()->getThreadContext(cpuId);
-tc->getPhysProxy().readBlob(lpiPendingTablePtr,
-(uint8_t *) lpi_pending_table,
-sizeof(lpi_pending_table));
+if (EnableLPIs) {
+const uint32_t largest_lpi_id = 1 << (lpiIDBits + 1);
+char lpi_pending_table[largest_lpi_id / 8];
+ThreadContext * tc = gic->getSystem()->getThreadContext(cpuId);
+tc->getPhysProxy().readBlob(lpiPendingTablePtr,
+(uint8_t *) lpi_pending_table,
+sizeof(lpi_pending_table));

-for (int lpi_id = SMALLEST_LPI_ID; lpi_id < largest_lpi_id;
- lpi_id++) {
-uint32_t lpi_pending_entry_byte = lpi_id / 8;
-uint8_t lpi_pending_entry_bit_position = lpi_id % 8;
-bool lpi_is_pending = lpi_pending_table[lpi_pending_entry_byte] &
-  1 << lpi_pending_entry_bit_position;
-uint32_t lpi_configuration_entry_index = lpi_id - SMALLEST_LPI_ID;
-bool lpi_is_enable =
-lpiConfigurationTable[lpi_configuration_entry_index].enable;
-// LPIs are always Non-secure Group 1 interrupts,
-// in a system where two Security states are enabled.
-Gicv3::GroupId lpi_group = Gicv3::G1NS;
-bool group_enabled = distributor->groupEnabled(lpi_group);
+for (int lpi_id = SMALLEST_LPI_ID; lpi_id < largest_lpi_id;
+ lpi_id++) {
+uint32_t lpi_pending_entry_byte = lpi_id / 8;
+uint8_t lpi_pending_entry_bit_position = lpi_id % 8;
+bool lpi_is_pending =  
lpi_pending_table[lpi_pending_entry_byte] &

+  1 << lpi_pending_entry_bit_position;
+uint32_t lpi_configuration_entry_index = lpi_id -  
SMALLEST_LPI_ID;

+bool lpi_is_enable =
+ 
lpiConfigurationTable[lpi_configuration_entry_index].enable;

+// LPIs are always Non-secure Group 1 interrupts,
+// in a system where two Security states are enabled.
+Gicv3::GroupId lpi_group = Gicv3::G1NS;
+bool group_enabled = distributor->groupEnabled(lpi_group);

-if (lpi_is_pending && lpi_is_enable && group_enabled) {
-uint8_t lpi_priority =
- 
lpiConfigurationTable[lpi_configuration_entry_index].priority;

+if (lpi_is_pending && lpi_is_enable && group_enabled) {
+uint8_t lpi_priority =
+ 
lpiConfigurationTable[lpi_configuration_entry_index].priority;


-if ((lpi_priority < cpuInterface->hppi.prio) ||
-(lpi_priority == cpuInterface->hppi.prio &&
- lpi_id < cpuInterface->hppi.intid)) {
-cpuInterface->hppi.intid = lpi_id;
-cpuInterface->hppi.prio = lpi_priority;
-cpuInterface->hppi.group = lpi_group;
-new_hppi = true;
+if ((lpi_priority < cpuInterface->hppi.prio) ||
+(lpi_priority == cpuInterface->hppi.prio &&
+ lpi_id < cpuInterface->hppi.intid)) {
+cpuInterface->hppi.intid = lpi_id;
+cpuInterface->hppi.prio = lpi_priority;
+cpuInterface->hppi.group = lpi_group;
+new_hppi = true;
+}
 }
 }
 }

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/18592
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: master

[gem5-dev] Change in gem5/gem5[master]: dev-arm: GICv3 LPI tables are using physical addresses

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18591 )


Change subject: dev-arm: GICv3 LPI tables are using physical addresses
..

dev-arm: GICv3 LPI tables are using physical addresses

Change-Id: I439112f318720ae74c43a374fd3a524c607b3a23
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18591
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/dev/arm/gic_v3_redistributor.cc
1 file changed, 5 insertions(+), 4 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/dev/arm/gic_v3_redistributor.cc  
b/src/dev/arm/gic_v3_redistributor.cc

index 3039e1e..d5a405a 100644
--- a/src/dev/arm/gic_v3_redistributor.cc
+++ b/src/dev/arm/gic_v3_redistributor.cc
@@ -732,7 +732,7 @@
 Addr lpi_table_entry_ptr = lpiConfigurationTablePtr +
 lpi_entry_index * sizeof(LPIConfigurationTableEntry);
 ThreadContext * tc = gic->getSystem()->getThreadContext(cpuId);
-tc->getVirtProxy().readBlob(lpi_table_entry_ptr,
+tc->getPhysProxy().readBlob(lpi_table_entry_ptr,
 (uint8_t*) [lpi_entry_index],
 sizeof(LPIConfigurationTableEntry));
 }
@@ -833,9 +833,10 @@
 const uint32_t largest_lpi_id = 1 << (lpiIDBits + 1);
 char lpi_pending_table[largest_lpi_id / 8];
 ThreadContext * tc = gic->getSystem()->getThreadContext(cpuId);
-tc->getVirtProxy().readBlob(lpiPendingTablePtr,
+tc->getPhysProxy().readBlob(lpiPendingTablePtr,
 (uint8_t *) lpi_pending_table,
 sizeof(lpi_pending_table));
+
 for (int lpi_id = SMALLEST_LPI_ID; lpi_id < largest_lpi_id;
  lpi_id++) {
 uint32_t lpi_pending_entry_byte = lpi_id / 8;
@@ -892,7 +893,7 @@
 Addr lpi_pending_entry_ptr = lpiPendingTablePtr + (lpi_id / 8);
 uint8_t lpi_pending_entry;
 ThreadContext * tc = gic->getSystem()->getThreadContext(cpuId);
-tc->getVirtProxy().readBlob(lpi_pending_entry_ptr,
+tc->getPhysProxy().readBlob(lpi_pending_entry_ptr,
 (uint8_t*) _pending_entry,
 sizeof(lpi_pending_entry));
 uint8_t lpi_pending_entry_bit_position = lpi_id % 8;
@@ -916,7 +917,7 @@
 lpi_pending_entry &= ~(1 << (lpi_pending_entry_bit_position));
 }

-tc->getVirtProxy().writeBlob(lpi_pending_entry_ptr,
+tc->getPhysProxy().writeBlob(lpi_pending_entry_ptr,
 (uint8_t*) _pending_entry,
 sizeof(lpi_pending_entry));
 updateAndInformCPUInterface();

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/18591
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I439112f318720ae74c43a374fd3a524c607b3a23
Gerrit-Change-Number: 18591
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Internship at Arm

[Giacomo Travaglini]

Hello devs,

We are looking for internship candidates to work on gem5 at Arm. If you know 
(or are one yourself!) of any keen students with gem5 experience (this is 
essential) who may want to do an internship (start dates flexible), please ask 
them to get in touch with either Juha or Reiley (in cc).

The intern can be based either in the UK or US, and paid according to standard 
Arm intern salary.

Regards,

Giacomo

IMPORTANT NOTICE: The contents of this email and any attachments are 
confidential and may also be privileged. If you are not the intended recipient, 
please notify the sender immediately and do not disclose the contents to any 
other person, use it for any purpose, or store or copy the information in any 
medium. Thank you.
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Long regression broken

[Giacomo Travaglini]

Hi all,

As I have already posted few weeks ago, there is a set of patches for MinorCPU 
which are breaking switcheroo long regressions.

https://gem5-review.googlesource.com/c/8182
https://gem5-review.googlesource.com/c/9625
https://gem5-review.googlesource.com/c/9626

Is there anybody willing to take care of these? Otherwise my proposal would be 
to revert them until someone decides to fix them
and re-apply them. This is making very hard for us (and to anybody) to run 
regressions, since we have to manually revert them for every feature we
develop if we want regressions to succeed.

You can find here the reverts under review

https://gem5-review.googlesource.com/c/public/gem5/+/18602/1
https://gem5-review.googlesource.com/c/public/gem5/+/18603/1
https://gem5-review.googlesource.com/c/public/gem5/+/18604/1

Please let me know your thoughts, I'd like to merge them asap

Giacomo
IMPORTANT NOTICE: The contents of this email and any attachments are 
confidential and may also be privileged. If you are not the intended recipient, 
please notify the sender immediately and do not disclose the contents to any 
other person, use it for any purpose, or store or copy the information in any 
medium. Thank you.
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in gem5/gem5[master]: Revert "cpu: fix branching when thread is suspended in MinorCPU"

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18602



Change subject: Revert "cpu: fix branching when thread is suspended in  
MinorCPU"

..

Revert "cpu: fix branching when thread is suspended in MinorCPU"

This reverts commit e437086341712f1435db655b3527ea29b3311f4e.
The commit was part of a patchset which broke MinorCPU regressions
(switcheroo)

Change-Id: Ib8482034c2402008ccfa552325a8eb31e731b619
Signed-off-by: Giacomo Travaglini 
---
M src/cpu/minor/execute.cc
1 file changed, 3 insertions(+), 9 deletions(-)



diff --git a/src/cpu/minor/execute.cc b/src/cpu/minor/execute.cc
index 47f3cbc..f26c77f 100644
--- a/src/cpu/minor/execute.cc
+++ b/src/cpu/minor/execute.cc
@@ -248,14 +248,7 @@
 pc_before, target);
 }

-if (thread->status() == ThreadContext::Suspended) {
-/* Thread got suspended */
-DPRINTF(Branch, "Thread got suspended: branch from 0x%x to 0x%x "
-"inst: %s\n",
-inst->pc.instAddr(), target.instAddr(), *inst);
-
-reason = BranchData::SuspendThread;
-} else if (inst->predictedTaken && !force_branch) {
+if (inst->predictedTaken && !force_branch) {
 /* Predicted to branch */
 if (!must_branch) {
 /* No branch was taken, change stream to get us back to the
@@ -1062,7 +1055,8 @@
 !branch.isStreamChange() && /* No real branch */
 fault == NoFault && /* No faults */
 completed_inst && /* Still finding instructions to execute */
-num_insts_committed != commitLimit /* Not reached commit limit */
+num_insts_committed != commitLimit && /* Not reached commit limit  
*/

+cpu.getContext(thread_id)->status() != ThreadContext::Suspended
 )
 {
 if (only_commit_microops) {

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/18602
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ib8482034c2402008ccfa552325a8eb31e731b619
Gerrit-Change-Number: 18602
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-MessageType: newchange
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in gem5/gem5[master]: Revert "cpu: fix how a thread starts up in MinorCPU"

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18604



Change subject: Revert "cpu: fix how a thread starts up in MinorCPU"
..

Revert "cpu: fix how a thread starts up in MinorCPU"

This reverts commit 02dafc5498750d9734ba8f2a1608a846f90b71d1.
The commit was part of a patchset which broke MinorCPU regressions
(switcheroo)

Change-Id: I0a8098fc71abe5838014e587dbe372b258d8aa9f
Signed-off-by: Giacomo Travaglini 
---
M src/cpu/minor/cpu.cc
M src/cpu/minor/cpu.hh
M src/cpu/minor/execute.cc
M src/cpu/minor/fetch2.cc
M src/cpu/minor/fetch2.hh
M src/cpu/minor/pipeline.cc
6 files changed, 16 insertions(+), 54 deletions(-)



diff --git a/src/cpu/minor/cpu.cc b/src/cpu/minor/cpu.cc
index 484457b..63efde2 100644
--- a/src/cpu/minor/cpu.cc
+++ b/src/cpu/minor/cpu.cc
@@ -49,7 +49,6 @@

 MinorCPU::MinorCPU(MinorCPUParams *params) :
 BaseCPU(params),
-pipelineStartupEvent([this]{ wakeupPipeline(); }, name()),
 threadPolicy(params->threadPolicy)
 {
 /* This is only written for one thread at the moment */
@@ -280,43 +279,20 @@
 void
 MinorCPU::activateContext(ThreadID thread_id)
 {
-/* Remember to wake up this thread_id by scheduling the
- * pipelineStartup event.
- * We can't wakeupFetch the thread right away because its context may
- * not have been fully initialized. For example, in the case of clone
- * syscall, this activateContext function is called in the middle of
- * the syscall and before the new thread context is initialized.
- * If we start fetching right away, the new thread will fetch from an
- * invalid address (i.e., pc is not initialized yet), which could lead
- * to a page fault. Instead, we remember which threads to wake up and
- * schedule an event to wake all them up after their contexts are
- * fully initialized */
-readyThreads.push_back(thread_id);
-if (!pipelineStartupEvent.scheduled())
-schedule(pipelineStartupEvent, clockEdge(Cycles(0)));
-}
+DPRINTF(MinorCPU, "ActivateContext thread: %d\n", thread_id);

-void
-MinorCPU::wakeupPipeline()
-{
-for (auto thread_id : readyThreads) {
-DPRINTF(MinorCPU, "ActivateContext thread: %d\n", thread_id);
+/* Do some cycle accounting.  lastStopped is reset to stop the
+ *  wakeup call on the pipeline from adding the quiesce period
+ *  to BaseCPU::numCycles */
+stats.quiesceCycles += pipeline->cyclesSinceLastStopped();
+pipeline->resetLastStopped();

-/* Do some cycle accounting.  lastStopped is reset to stop the
- *  wakeup call on the pipeline from adding the quiesce period
- *  to BaseCPU::numCycles */
-stats.quiesceCycles += pipeline->cyclesSinceLastStopped();
-pipeline->resetLastStopped();
+/* Wake up the thread, wakeup the pipeline tick */
+threads[thread_id]->activate();
+wakeupOnEvent(Minor::Pipeline::CPUStageId);
+pipeline->wakeupFetch(thread_id);

-/* Wake up the thread, wakeup the pipeline tick */
-threads[thread_id]->activate();
-wakeupOnEvent(Minor::Pipeline::CPUStageId);
-
-pipeline->wakeupFetch(thread_id);
-BaseCPU::activateContext(thread_id);
-}
-
-readyThreads.clear();
+BaseCPU::activateContext(thread_id);
 }

 void
diff --git a/src/cpu/minor/cpu.hh b/src/cpu/minor/cpu.hh
index 606a401..4e47623 100644
--- a/src/cpu/minor/cpu.hh
+++ b/src/cpu/minor/cpu.hh
@@ -83,13 +83,6 @@
  *  Elements of pipeline call TheISA to implement the model. */
 Minor::Pipeline *pipeline;

-/** An event that wakes up the pipeline when a thread context is
- * activated */
-EventFunctionWrapper pipelineStartupEvent;
-
-/** List of threads that are ready to wake up and run */
-std::vector readyThreads;
-
   public:
 /** Activity recording for pipeline.  This belongs to Pipeline but
  *  stages will access it through the CPU as the MinorCPU object
@@ -172,9 +165,6 @@
 void activateContext(ThreadID thread_id) override;
 void suspendContext(ThreadID thread_id) override;

-/** Wake up ready-to-run threads */
-void wakeupPipeline();
-
 /** Thread scheduling utility functions */
 std::vector roundRobinPriority(ThreadID priority)
 {
diff --git a/src/cpu/minor/execute.cc b/src/cpu/minor/execute.cc
index 16a3a29..6f7eecf 100644
--- a/src/cpu/minor/execute.cc
+++ b/src/cpu/minor/execute.cc
@@ -1055,8 +1055,7 @@
 !branch.isStreamChange() && /* No real branch */
 fault == NoFault && /* No faults */
 completed_inst && /* Still finding instructions to execute */
-num_insts_committed != commitLimit && /* Not reached commit limit  
*/

-cpu.getContext(thread_id)->status() != ThreadContext::Suspended
+num_insts_committed != commitLimit /* Not reached commit limit */
 )
 {
 if (only_commit_microops) {
diff 

[gem5-dev] Change in gem5/gem5[master]: Revert "cpu: stop scheduling suspended threads in MinorCPU"

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18603



Change subject: Revert "cpu: stop scheduling suspended threads in MinorCPU"
..

Revert "cpu: stop scheduling suspended threads in MinorCPU"

This reverts commit 6a6668bbc4b038b98eb3ee64ffb034719316afd9.
The commit was part of a patchset which broke MinorCPU regressions
(switcheroo)

Change-Id: I3c16a6478ba44b9d27cdd3d64a710a356999df05
Signed-off-by: Giacomo Travaglini 
---
M src/cpu/minor/decode.cc
M src/cpu/minor/execute.cc
M src/cpu/minor/fetch2.cc
3 files changed, 4 insertions(+), 14 deletions(-)



diff --git a/src/cpu/minor/decode.cc b/src/cpu/minor/decode.cc
index 94d3dec..390ca5f 100644
--- a/src/cpu/minor/decode.cc
+++ b/src/cpu/minor/decode.cc
@@ -314,9 +314,7 @@
 }

 for (auto tid : priority_list) {
-if (cpu.getContext(tid)->status() == ThreadContext::Active &&
-getInput(tid) &&
-!decodeInfo[tid].blocked) {
+if (getInput(tid) && !decodeInfo[tid].blocked) {
 threadPriority = tid;
 return tid;
 }
diff --git a/src/cpu/minor/execute.cc b/src/cpu/minor/execute.cc
index f26c77f..16a3a29 100644
--- a/src/cpu/minor/execute.cc
+++ b/src/cpu/minor/execute.cc
@@ -1677,12 +1677,7 @@

 for (auto tid : priority_list) {
 ExecuteThreadInfo _info = executeInfo[tid];
-
-bool is_thread_active =
-cpu.getContext(tid)->status() == ThreadContext::Active;
-bool can_commit_insts = !ex_info.inFlightInsts->empty() &&
-is_thread_active;
-
+bool can_commit_insts = !ex_info.inFlightInsts->empty();
 if (can_commit_insts) {
 QueuedInst *head_inflight_inst =  
&(ex_info.inFlightInsts->front());

 MinorDynInstPtr inst = head_inflight_inst->inst;
@@ -1748,8 +1743,7 @@
 }

 for (auto tid : priority_list) {
-if (cpu.getContext(tid)->status() == ThreadContext::Active &&
-getInput(tid)) {
+if (getInput(tid)) {
 issuePriority = tid;
 return tid;
 }
diff --git a/src/cpu/minor/fetch2.cc b/src/cpu/minor/fetch2.cc
index 9347e4c..b374ee9 100644
--- a/src/cpu/minor/fetch2.cc
+++ b/src/cpu/minor/fetch2.cc
@@ -586,9 +586,7 @@
 }

 for (auto tid : priority_list) {
-if (cpu.getContext(tid)->status() == ThreadContext::Active &&
-getInput(tid) &&
-!fetchInfo[tid].blocked) {
+if (getInput(tid) && !fetchInfo[tid].blocked) {
 threadPriority = tid;
 return tid;
 }

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/18603
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I3c16a6478ba44b9d27cdd3d64a710a356999df05
Gerrit-Change-Number: 18603
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-MessageType: newchange
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in gem5/gem5[master]: dev-arm: Provide a GICv3 ITS Implementation

[Giacomo Travaglini (Gerrit)]

Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/18601

to review the following change.


Change subject: dev-arm: Provide a GICv3 ITS Implementation
..

dev-arm: Provide a GICv3 ITS Implementation

This patch introduces the GICv3 ITS module, which is in charge of
translating MSIs into physical (GICv3) and virtual (GICv4) LPIs.  The
patch is only GICv3 compliant, which means that there is no direct
virtual LPI injection (this also means V* commands are unimplemented)
Other missing features are:

* No 2level ITS tables (only flat table supported)

* Command errors: when there is an error in the ITS, it is
IMPLEMENTATION DEFINED on how the ITS behaves.  There are three possible
scenarios (see GICv3 TRM) and this implementation only supports one of
these (which is, aborting the command and jumping to the next one).
Furter patches could make it possible to select different reactions

* Invalidation commands (INV, INVALL) are only doing the memory table
walks, assuming the current Gicv3Redistributor is not caching any
configuration table entry.

Change-Id: If4ae9267ac1de7b20a04986a2af3ca3109743211
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M src/dev/arm/Gic.py
M src/dev/arm/RealView.py
M src/dev/arm/SConscript
M src/dev/arm/gic_v3.cc
M src/dev/arm/gic_v3.hh
A src/dev/arm/gic_v3_its.cc
A src/dev/arm/gic_v3_its.hh
M src/dev/arm/gic_v3_redistributor.hh
8 files changed, 1,759 insertions(+), 4 deletions(-)



diff --git a/src/dev/arm/Gic.py b/src/dev/arm/Gic.py
index 011e238..d31a582 100644
--- a/src/dev/arm/Gic.py
+++ b/src/dev/arm/Gic.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2012-2013, 2017-2018 ARM Limited
+# Copyright (c) 2012-2013, 2017-2019 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -40,7 +40,7 @@
 from m5.util.fdthelper import *
 from m5.SimObject import SimObject

-from m5.objects.Device import PioDevice
+from m5.objects.Device import PioDevice, BasicPioDevice
 from m5.objects.Platform import Platform

 class BaseGic(PioDevice):
@@ -162,10 +162,24 @@

 yield node

+class Gicv3Its(BasicPioDevice):
+type = 'Gicv3Its'
+cxx_header = "dev/arm/gic_v3_its.hh"
+
+dma = MasterPort("DMA port")
+pio_size = Param.Unsigned(0x2, "Gicv3Its pio size")
+
+# CIL [36] = 0: ITS supports 16-bit CollectionID
+# Devbits [17:13] = 0b100011: ITS supports 23 DeviceID bits
+# ID_bits [12:8] = 0b1: ITS supports 31 EventID bits
+gits_typer = Param.UInt64(0x30023F01, "GITS_TYPER RO value")
+
 class Gicv3(BaseGic):
 type = 'Gicv3'
 cxx_header = "dev/arm/gic_v3.hh"

+its = Param.Gicv3Its(Gicv3Its(), "GICv3 Interrupt Translation Service")
+
 dist_addr = Param.Addr("Address for distributor")
 dist_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to  
distributor")

 redist_addr = Param.Addr("Address for redistributors")
diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index 186d6df..b34ab00 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -1084,14 +1084,15 @@

 class VExpress_GEM5_V2_Base(VExpress_GEM5_Base):
 gic = Gicv3(dist_addr=0x2c00, redist_addr=0x2c01,
-maint_int=ArmPPI(num=25))
+maint_int=ArmPPI(num=25),
+its=Gicv3Its(pio_addr=0x2c12))

 # Limiting to 128 since it will otherwise overlap with PCI space
 gic.cpu_max = 128

 def _on_chip_devices(self):
 return super(VExpress_GEM5_V2_Base,self)._on_chip_devices() + [
-self.gic,
+self.gic, self.gic.its
 ]

 def setupBootLoader(self, mem_bus, cur_sys, loc):
diff --git a/src/dev/arm/SConscript b/src/dev/arm/SConscript
index c4aa521..7d14abe 100644
--- a/src/dev/arm/SConscript
+++ b/src/dev/arm/SConscript
@@ -61,6 +61,7 @@
 Source('gic_v3_cpu_interface.cc')
 Source('gic_v3_distributor.cc')
 Source('gic_v3_redistributor.cc')
+Source('gic_v3_its.cc')
 Source('pl011.cc')
 Source('pl111.cc')
 Source('hdlcd.cc')
@@ -85,6 +86,7 @@
 DebugFlag('GICV2M')
 DebugFlag('Pl050')
 DebugFlag('GIC')
+DebugFlag('ITS')
 DebugFlag('RVCTRL')
 DebugFlag('EnergyCtrl')
 DebugFlag('UFSHostDevice')
diff --git a/src/dev/arm/gic_v3.cc b/src/dev/arm/gic_v3.cc
index 9004f65..6f4312b 100644
--- a/src/dev/arm/gic_v3.cc
+++ b/src/dev/arm/gic_v3.cc
@@ -35,6 +35,7 @@
 #include "debug/Interrupt.hh"
 #include "dev/arm/gic_v3_cpu_interface.hh"
 #include "dev/arm/gic_v3_distributor.hh"
+#include "dev/arm/gic_v3_its.hh"
 #include "dev/arm/gic_v3_redistributor.hh"
 #include "dev/platform.hh"
 #include "mem/packet.hh"
@@ -78,6 +79,8 @@
 cpuInterfaces[i]->init();
 }

+params()->its->setGIC(this);
+
 BaseGic::init();
 }

diff --git a/src/dev/arm/gic_v3.hh b/src/dev/arm/gic_v3.hh

[gem5-dev] Change in gem5/gem5[master]: dev-arm: Add named variable for GICD_TYPER.IDBits

[Giacomo Travaglini (Gerrit)]

Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/18599

to review the following change.


Change subject: dev-arm: Add named variable for GICD_TYPER.IDBits
..

dev-arm: Add named variable for GICD_TYPER.IDBits

This could be used by other GICv3 components to query the maximum
number of implemented interrupt identifiers

Change-Id: I132e50de331aea22523260bcefba7e961b53eccd
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M src/dev/arm/gic_v3_distributor.cc
M src/dev/arm/gic_v3_distributor.hh
2 files changed, 2 insertions(+), 1 deletion(-)



diff --git a/src/dev/arm/gic_v3_distributor.cc  
b/src/dev/arm/gic_v3_distributor.cc

index f261b29..a048d18 100644
--- a/src/dev/arm/gic_v3_distributor.cc
+++ b/src/dev/arm/gic_v3_distributor.cc
@@ -472,7 +472,7 @@
 {
 int max_spi_int_id = itLines - 1;
 int it_lines_number = ceil((max_spi_int_id + 1) / 32.0) - 1;
-return (1 << 26) | (1 << 25) | (1 << 24) | (0xf << 19) |
+return (1 << 26) | (1 << 25) | (1 << 24) | (IDBITS << 19) |
 (1 << 17) | (gic->getSystem()->haveSecurity() << 10) |
 (it_lines_number << 0);
 }
diff --git a/src/dev/arm/gic_v3_distributor.hh  
b/src/dev/arm/gic_v3_distributor.hh

index 86e53a3..c231438 100644
--- a/src/dev/arm/gic_v3_distributor.hh
+++ b/src/dev/arm/gic_v3_distributor.hh
@@ -140,6 +140,7 @@
   public:

 static const uint32_t ADDR_RANGE_SIZE = 0x1;
+static const uint32_t IDBITS = 0xf;

   protected:


--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/18599
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I132e50de331aea22523260bcefba7e961b53eccd
Gerrit-Change-Number: 18599
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-MessageType: newchange
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in gem5/gem5[master]: dev-arm: Fix Bitwise operation in GICv3

[Giacomo Travaglini (Gerrit)]

Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/18589

to review the following change.


Change subject: dev-arm: Fix Bitwise operation in GICv3
..

dev-arm: Fix Bitwise operation in GICv3

GICv3 LPI code is wrongly using the xor operator (^) in order to
evaluate powers of two.

Change-Id: Ib1131fd5940d334967a3741f8fd15d86625be356
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M src/dev/arm/gic_v3_redistributor.cc
1 file changed, 4 insertions(+), 4 deletions(-)



diff --git a/src/dev/arm/gic_v3_redistributor.cc  
b/src/dev/arm/gic_v3_redistributor.cc

index eb5767a..348cd96 100644
--- a/src/dev/arm/gic_v3_redistributor.cc
+++ b/src/dev/arm/gic_v3_redistributor.cc
@@ -675,7 +675,7 @@
   lpiIDBits = 0xf;
   }

-  uint32_t largest_lpi_id = 2 ^ (lpiIDBits + 1);
+  uint32_t largest_lpi_id = 1 << (lpiIDBits + 1);
   uint32_t number_lpis = largest_lpi_id - SMALLEST_LPI_ID + 1;
   lpiConfigurationTable.resize(number_lpis);
   break;
@@ -699,7 +699,7 @@

   case GICR_INVLPIR: { // Redistributor Invalidate LPI Register
   uint32_t lpi_id = data & 0x;
-  uint32_t largest_lpi_id = 2 ^ (lpiIDBits + 1);
+  uint32_t largest_lpi_id = 1 << (lpiIDBits + 1);

   if (lpi_id > largest_lpi_id) {
   return;
@@ -830,7 +830,7 @@
 }

 // Check LPIs
-uint32_t largest_lpi_id = 2 ^ (lpiIDBits + 1);
+uint32_t largest_lpi_id = 1 << (lpiIDBits + 1);
 char lpi_pending_table[largest_lpi_id / 8];
 ThreadContext * tc = gic->getSystem()->getThreadContext(cpuId);
 tc->getVirtProxy().readBlob(lpiPendingTablePtr,
@@ -881,7 +881,7 @@
 }

 uint32_t lpi_id = data & 0x;
-uint32_t largest_lpi_id = 2 ^ (lpiIDBits + 1);
+uint32_t largest_lpi_id = 1 << (lpiIDBits + 1);

 if (lpi_id > largest_lpi_id) {
 // Writes to GICR_SETLPIR or GICR_CLRLPIR have not effect if

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/18589
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ib1131fd5940d334967a3741f8fd15d86625be356
Gerrit-Change-Number: 18589
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-MessageType: newchange
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in gem5/gem5[master]: dev-arm: GICv3 LPI tables are using physical addresses

[Giacomo Travaglini (Gerrit)]

Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/18591

to review the following change.


Change subject: dev-arm: GICv3 LPI tables are using physical addresses
..

dev-arm: GICv3 LPI tables are using physical addresses

Change-Id: I439112f318720ae74c43a374fd3a524c607b3a23
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M src/dev/arm/gic_v3_redistributor.cc
1 file changed, 5 insertions(+), 4 deletions(-)



diff --git a/src/dev/arm/gic_v3_redistributor.cc  
b/src/dev/arm/gic_v3_redistributor.cc

index 3039e1e..d5a405a 100644
--- a/src/dev/arm/gic_v3_redistributor.cc
+++ b/src/dev/arm/gic_v3_redistributor.cc
@@ -732,7 +732,7 @@
 Addr lpi_table_entry_ptr = lpiConfigurationTablePtr +
 lpi_entry_index * sizeof(LPIConfigurationTableEntry);
 ThreadContext * tc = gic->getSystem()->getThreadContext(cpuId);
-tc->getVirtProxy().readBlob(lpi_table_entry_ptr,
+tc->getPhysProxy().readBlob(lpi_table_entry_ptr,
 (uint8_t*) [lpi_entry_index],
 sizeof(LPIConfigurationTableEntry));
 }
@@ -833,9 +833,10 @@
 const uint32_t largest_lpi_id = 1 << (lpiIDBits + 1);
 char lpi_pending_table[largest_lpi_id / 8];
 ThreadContext * tc = gic->getSystem()->getThreadContext(cpuId);
-tc->getVirtProxy().readBlob(lpiPendingTablePtr,
+tc->getPhysProxy().readBlob(lpiPendingTablePtr,
 (uint8_t *) lpi_pending_table,
 sizeof(lpi_pending_table));
+
 for (int lpi_id = SMALLEST_LPI_ID; lpi_id < largest_lpi_id;
  lpi_id++) {
 uint32_t lpi_pending_entry_byte = lpi_id / 8;
@@ -892,7 +893,7 @@
 Addr lpi_pending_entry_ptr = lpiPendingTablePtr + (lpi_id / 8);
 uint8_t lpi_pending_entry;
 ThreadContext * tc = gic->getSystem()->getThreadContext(cpuId);
-tc->getVirtProxy().readBlob(lpi_pending_entry_ptr,
+tc->getPhysProxy().readBlob(lpi_pending_entry_ptr,
 (uint8_t*) _pending_entry,
 sizeof(lpi_pending_entry));
 uint8_t lpi_pending_entry_bit_position = lpi_id % 8;
@@ -916,7 +917,7 @@
 lpi_pending_entry &= ~(1 << (lpi_pending_entry_bit_position));
 }

-tc->getVirtProxy().writeBlob(lpi_pending_entry_ptr,
+tc->getPhysProxy().writeBlob(lpi_pending_entry_ptr,
 (uint8_t*) _pending_entry,
 sizeof(lpi_pending_entry));
 updateAndInformCPUInterface();

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/18591
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I439112f318720ae74c43a374fd3a524c607b3a23
Gerrit-Change-Number: 18591
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-MessageType: newchange
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in gem5/gem5[master]: dev-arm: Fix GICv3 LPI loop

[Giacomo Travaglini (Gerrit)]

Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/18590

to review the following change.


Change subject: dev-arm: Fix GICv3 LPI loop
..

dev-arm: Fix GICv3 LPI loop

Loop was mistakenly increasing the upper bound of the iteration rather
than the index variable itself.

Change-Id: I0a5a7bc189bc0954a8a6d9581032c2ed902030da
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M src/dev/arm/gic_v3_redistributor.cc
1 file changed, 2 insertions(+), 2 deletions(-)



diff --git a/src/dev/arm/gic_v3_redistributor.cc  
b/src/dev/arm/gic_v3_redistributor.cc

index 348cd96..3039e1e 100644
--- a/src/dev/arm/gic_v3_redistributor.cc
+++ b/src/dev/arm/gic_v3_redistributor.cc
@@ -830,14 +830,14 @@
 }

 // Check LPIs
-uint32_t largest_lpi_id = 1 << (lpiIDBits + 1);
+const uint32_t largest_lpi_id = 1 << (lpiIDBits + 1);
 char lpi_pending_table[largest_lpi_id / 8];
 ThreadContext * tc = gic->getSystem()->getThreadContext(cpuId);
 tc->getVirtProxy().readBlob(lpiPendingTablePtr,
 (uint8_t *) lpi_pending_table,
 sizeof(lpi_pending_table));
 for (int lpi_id = SMALLEST_LPI_ID; lpi_id < largest_lpi_id;
- largest_lpi_id++) {
+ lpi_id++) {
 uint32_t lpi_pending_entry_byte = lpi_id / 8;
 uint8_t lpi_pending_entry_bit_position = lpi_id % 8;
 bool lpi_is_pending = lpi_pending_table[lpi_pending_entry_byte] &

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/18590
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I0a5a7bc189bc0954a8a6d9581032c2ed902030da
Gerrit-Change-Number: 18590
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-MessageType: newchange
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in gem5/gem5[master]: dev-arm: Disable LPI Configuration Table caching

[Giacomo Travaglini (Gerrit)]

Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/18593

to review the following change.


Change subject: dev-arm: Disable LPI Configuration Table caching
..

dev-arm: Disable LPI Configuration Table caching

This is done since caching is not done correctly, and we don't care for
now about performance degradations since the redistributor is using
PhysProxy ports.
Caching will make sense once the magical accesses will be replaced by
real atomic/timing transactions.

Change-Id: Iafe2a7843210111efc82c265bd0d5ec3cd9abb5a
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M src/dev/arm/gic_v3_redistributor.cc
M src/dev/arm/gic_v3_redistributor.hh
2 files changed, 20 insertions(+), 38 deletions(-)



diff --git a/src/dev/arm/gic_v3_redistributor.cc  
b/src/dev/arm/gic_v3_redistributor.cc

index 2b73c57..be28d3a 100644
--- a/src/dev/arm/gic_v3_redistributor.cc
+++ b/src/dev/arm/gic_v3_redistributor.cc
@@ -675,9 +675,6 @@
   lpiIDBits = 0xf;
   }

-  uint32_t largest_lpi_id = 1 << (lpiIDBits + 1);
-  uint32_t number_lpis = largest_lpi_id - SMALLEST_LPI_ID + 1;
-  lpiConfigurationTable.resize(number_lpis);
   break;
   }

@@ -698,25 +695,12 @@
 break;

   case GICR_INVLPIR: { // Redistributor Invalidate LPI Register
-  uint32_t lpi_id = data & 0x;
-  uint32_t largest_lpi_id = 1 << (lpiIDBits + 1);
-
-  if (lpi_id > largest_lpi_id) {
-  return;
-  }
-
-  uint32_t lpi_table_entry_index = lpi_id - SMALLEST_LPI_ID;
-  invalLpiConfig(lpi_table_entry_index);
+  // Do nothing: no caching supported
   break;
   }

   case GICR_INVALLR: { // Redistributor Invalidate All Register
-  for (int lpi_table_entry_index = 0;
-   lpi_table_entry_index < lpiConfigurationTable.size();
-   lpi_table_entry_index++) {
-  invalLpiConfig(lpi_table_entry_index);
-  }
-
+  // Do nothing: no caching supported
   break;
   }

@@ -727,17 +711,6 @@
 }

 void
-Gicv3Redistributor::invalLpiConfig(uint32_t lpi_entry_index)
-{
-Addr lpi_table_entry_ptr = lpiConfigurationTablePtr +
-lpi_entry_index * sizeof(LPIConfigurationTableEntry);
-ThreadContext * tc = gic->getSystem()->getThreadContext(cpuId);
-tc->getPhysProxy().readBlob(lpi_table_entry_ptr,
-(uint8_t*) [lpi_entry_index],
-sizeof(LPIConfigurationTableEntry));
-}
-
-void
 Gicv3Redistributor::sendPPInt(uint32_t int_id)
 {
 assert((int_id >= Gicv3::SGI_MAX) &&
@@ -831,13 +804,22 @@

 // Check LPIs
 if (EnableLPIs) {
-const uint32_t largest_lpi_id = 1 << (lpiIDBits + 1);
-char lpi_pending_table[largest_lpi_id / 8];
 ThreadContext * tc = gic->getSystem()->getThreadContext(cpuId);
+
+const uint32_t largest_lpi_id = 1 << (lpiIDBits + 1);
+const uint32_t number_lpis = largest_lpi_id - SMALLEST_LPI_ID + 1;
+
+uint8_t lpi_pending_table[largest_lpi_id / 8];
+uint8_t lpi_config_table[number_lpis];
+
 tc->getPhysProxy().readBlob(lpiPendingTablePtr,
 (uint8_t *) lpi_pending_table,
 sizeof(lpi_pending_table));

+tc->getPhysProxy().readBlob(lpiConfigurationTablePtr,
+(uint8_t*) lpi_config_table,
+sizeof(lpi_config_table));
+
 for (int lpi_id = SMALLEST_LPI_ID; lpi_id < largest_lpi_id;
  lpi_id++) {
 uint32_t lpi_pending_entry_byte = lpi_id / 8;
@@ -845,16 +827,19 @@
 bool lpi_is_pending =  
lpi_pending_table[lpi_pending_entry_byte] &

   1 << lpi_pending_entry_bit_position;
 uint32_t lpi_configuration_entry_index = lpi_id -  
SMALLEST_LPI_ID;

-bool lpi_is_enable =
- 
lpiConfigurationTable[lpi_configuration_entry_index].enable;

+
+LPIConfigurationTableEntry config_entry =
+lpi_config_table[lpi_configuration_entry_index];
+
+bool lpi_is_enable = config_entry.enable;
+
 // LPIs are always Non-secure Group 1 interrupts,
 // in a system where two Security states are enabled.
 Gicv3::GroupId lpi_group = Gicv3::G1NS;
 bool group_enabled = distributor->groupEnabled(lpi_group);

 if (lpi_is_pending && lpi_is_enable && group_enabled) {
-uint8_t lpi_priority =
- 
lpiConfigurationTable[lpi_configuration_entry_index].priority;

+uint8_t lpi_priority =config_entry.priority;

 if ((lpi_priority < cpuInterface->hppi.prio) ||
 (lpi_priority == cpuInterface->hppi.prio &&
diff --git 

[gem5-dev] Change in gem5/gem5[master]: dev-arm: Store a PhysProxy port in Gicv3Redist

[Giacomo Travaglini (Gerrit)]

Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/18600

to review the following change.


Change subject: dev-arm: Store a PhysProxy port in Gicv3Redist
..

dev-arm: Store a PhysProxy port in Gicv3Redist

This spares us from retrieving the TC pointer every time we want to
write/read to memory (LPIs)

Change-Id: Iad76b5e69188fa0ac5c6777a3b2664b0fc66b12f
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M src/dev/arm/gic_v3_redistributor.cc
M src/dev/arm/gic_v3_redistributor.hh
2 files changed, 16 insertions(+), 15 deletions(-)



diff --git a/src/dev/arm/gic_v3_redistributor.cc  
b/src/dev/arm/gic_v3_redistributor.cc

index 0ee6b8a..de6bd63 100644
--- a/src/dev/arm/gic_v3_redistributor.cc
+++ b/src/dev/arm/gic_v3_redistributor.cc
@@ -44,6 +44,7 @@
   distributor(nullptr),
   cpuInterface(nullptr),
   cpuId(cpu_id),
+  memProxy(nullptr),
   irqGroup(Gicv3::SGI_MAX + Gicv3::PPI_MAX),
   irqEnabled(Gicv3::SGI_MAX + Gicv3::PPI_MAX),
   irqPending(Gicv3::SGI_MAX + Gicv3::PPI_MAX),
@@ -61,6 +62,8 @@
 {
 distributor = gic->getDistributor();
 cpuInterface = gic->getCPUInterface(cpuId);
+
+memProxy = >getSystem()->physProxy;
 }

 void
@@ -804,7 +807,6 @@

 // Check LPIs
 if (EnableLPIs) {
-ThreadContext * tc = gic->getSystem()->getThreadContext(cpuId);

 const uint32_t largest_lpi_id = 1 << (lpiIDBits + 1);
 const uint32_t number_lpis = largest_lpi_id - SMALLEST_LPI_ID + 1;
@@ -812,13 +814,13 @@
 uint8_t lpi_pending_table[largest_lpi_id / 8];
 uint8_t lpi_config_table[number_lpis];

-tc->getPhysProxy().readBlob(lpiPendingTablePtr,
-(uint8_t *) lpi_pending_table,
-sizeof(lpi_pending_table));
+memProxy->readBlob(lpiPendingTablePtr,
+   (uint8_t *) lpi_pending_table,
+   sizeof(lpi_pending_table));

-tc->getPhysProxy().readBlob(lpiConfigurationTablePtr,
-(uint8_t*) lpi_config_table,
-sizeof(lpi_config_table));
+memProxy->readBlob(lpiConfigurationTablePtr,
+   (uint8_t*) lpi_config_table,
+   sizeof(lpi_config_table));

 for (int lpi_id = SMALLEST_LPI_ID; lpi_id < largest_lpi_id;
  lpi_id++) {
@@ -866,10 +868,9 @@
 Addr lpi_pending_entry_ptr = lpiPendingTablePtr + (lpi_id / 8);

 uint8_t lpi_pending_entry;
-ThreadContext * tc = gic->getSystem()->getThreadContext(cpuId);
-tc->getPhysProxy().readBlob(lpi_pending_entry_ptr,
-(uint8_t*) _pending_entry,
-sizeof(lpi_pending_entry));
+memProxy->readBlob(lpi_pending_entry_ptr,
+   (uint8_t*) _pending_entry,
+   sizeof(lpi_pending_entry));

 return lpi_pending_entry;
 }
@@ -879,10 +880,9 @@
 {
 Addr lpi_pending_entry_ptr = lpiPendingTablePtr + (lpi_id / 8);

-ThreadContext * tc = gic->getSystem()->getThreadContext(cpuId);
-tc->getPhysProxy().writeBlob(lpi_pending_entry_ptr,
-(uint8_t*) _pending_entry,
-sizeof(lpi_pending_entry));
+memProxy->writeBlob(lpi_pending_entry_ptr,
+(uint8_t*) _pending_entry,
+sizeof(lpi_pending_entry));
 }

 bool
diff --git a/src/dev/arm/gic_v3_redistributor.hh  
b/src/dev/arm/gic_v3_redistributor.hh

index 6aff91d..8d7de3d 100644
--- a/src/dev/arm/gic_v3_redistributor.hh
+++ b/src/dev/arm/gic_v3_redistributor.hh
@@ -51,6 +51,7 @@
 Gicv3Distributor * distributor;
 Gicv3CPUInterface * cpuInterface;
 uint32_t cpuId;
+PortProxy * memProxy;

 /*
  * GICv3 defines 2 contiguous 64KB frames for each redistributor.

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/18600
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Iad76b5e69188fa0ac5c6777a3b2664b0fc66b12f
Gerrit-Change-Number: 18600
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-MessageType: newchange
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in gem5/gem5[master]: dev-arm: Fix GICv3 LPIs priority value

[Giacomo Travaglini (Gerrit)]

Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/18594

to review the following change.


Change subject: dev-arm: Fix GICv3 LPIs priority value
..

dev-arm: Fix GICv3 LPIs priority value

Priority bits in the LPI configuration table entry are only the MSBits
([7:2]) and need to be shifted in order to get the real LPI priority
value.

Change-Id: Id04dd4fa9113a32712c73a7094df498de3c0d2b5
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M src/dev/arm/gic_v3_redistributor.cc
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/dev/arm/gic_v3_redistributor.cc  
b/src/dev/arm/gic_v3_redistributor.cc

index be28d3a..e22d830 100644
--- a/src/dev/arm/gic_v3_redistributor.cc
+++ b/src/dev/arm/gic_v3_redistributor.cc
@@ -839,7 +839,7 @@
 bool group_enabled = distributor->groupEnabled(lpi_group);

 if (lpi_is_pending && lpi_is_enable && group_enabled) {
-uint8_t lpi_priority =config_entry.priority;
+uint8_t lpi_priority = config_entry.priority << 2;

 if ((lpi_priority < cpuInterface->hppi.prio) ||
 (lpi_priority == cpuInterface->hppi.prio &&

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/18594
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Id04dd4fa9113a32712c73a7094df498de3c0d2b5
Gerrit-Change-Number: 18594
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-MessageType: newchange
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in gem5/gem5[master]: dev-arm: Take LPIs into account when interacting with CPUIF regs

[Giacomo Travaglini (Gerrit)]

Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/18595

to review the following change.


Change subject: dev-arm: Take LPIs into account when interacting with CPUIF  
regs

..

dev-arm: Take LPIs into account when interacting with CPUIF regs

Previous code was not handling LPIs when it came to
activation/deactivation of interrupts.

Change-Id: Ie38f83c66afdc42132679d7e2e5823990f1710d0
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M src/dev/arm/gic_v3_cpu_interface.cc
M src/dev/arm/gic_v3_redistributor.cc
2 files changed, 15 insertions(+), 6 deletions(-)



diff --git a/src/dev/arm/gic_v3_cpu_interface.cc  
b/src/dev/arm/gic_v3_cpu_interface.cc

index 577442e..3598f34 100644
--- a/src/dev/arm/gic_v3_cpu_interface.cc
+++ b/src/dev/arm/gic_v3_cpu_interface.cc
@@ -409,7 +409,8 @@
   int_id = getHPPIR0();

   // avoid activation for special interrupts
-  if (int_id < Gicv3::INTID_SECURE) {
+  if (int_id < Gicv3::INTID_SECURE ||
+  int_id >= Gicv3Redistributor::SMALLEST_LPI_ID) {
   activateIRQ(int_id, hppi.group);
   }
   } else {
@@ -464,7 +465,8 @@
   int_id = getHPPIR1();

   // avoid activation for special interrupts
-  if (int_id < Gicv3::INTID_SECURE) {
+  if (int_id < Gicv3::INTID_SECURE ||
+  int_id >= Gicv3Redistributor::SMALLEST_LPI_ID) {
   activateIRQ(int_id, hppi.group);
   }
   } else {
@@ -778,7 +780,8 @@
   int int_id = val & 0xff;

   // avoid activation for special interrupts
-  if (int_id >= Gicv3::INTID_SECURE) {
+  if (int_id >= Gicv3::INTID_SECURE &&
+  int_id <= Gicv3::INTID_SPURIOUS) {
   return;
   }

@@ -847,7 +850,8 @@
   int int_id = val & 0xff;

   // avoid deactivation for special interrupts
-  if (int_id >= Gicv3::INTID_SECURE) {
+  if (int_id >= Gicv3::INTID_SECURE &&
+  int_id <= Gicv3::INTID_SPURIOUS) {
   return;
   }

@@ -1770,6 +1774,9 @@
 // SPI, distributor
 distributor->activateIRQ(int_id);
 distributor->updateAndInformCPUInterfaces();
+} else if (int_id >= Gicv3Redistributor::SMALLEST_LPI_ID) {
+// LPI, Redistributor
+redistributor->setClrLPI(int_id, false);
 }
 }

@@ -1806,7 +1813,8 @@
 distributor->deactivateIRQ(int_id);
 distributor->updateAndInformCPUInterfaces();
 } else {
-return;
+// LPI, redistributor, shouldn't deactivate
+redistributor->updateAndInformCPUInterface();
 }
 }

diff --git a/src/dev/arm/gic_v3_redistributor.cc  
b/src/dev/arm/gic_v3_redistributor.cc

index e22d830..79de7d5 100644
--- a/src/dev/arm/gic_v3_redistributor.cc
+++ b/src/dev/arm/gic_v3_redistributor.cc
@@ -854,7 +854,8 @@
 }

 if (!new_hppi && cpuInterface->hppi.prio != 0xff &&
-cpuInterface->hppi.intid < Gicv3::SGI_MAX + Gicv3::PPI_MAX) {
+(cpuInterface->hppi.intid < Gicv3::SGI_MAX + Gicv3::PPI_MAX ||
+ cpuInterface->hppi.intid > SMALLEST_LPI_ID)) {
 distributor->fullUpdate();
 }
 }

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/18595
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ie38f83c66afdc42132679d7e2e5823990f1710d0
Gerrit-Change-Number: 18595
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-MessageType: newchange
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in gem5/gem5[master]: dev-arm: Add several LPI methods in Gicv3Redistributor

[Giacomo Travaglini (Gerrit)]

Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/18596

to review the following change.


Change subject: dev-arm: Add several LPI methods in Gicv3Redistributor
..

dev-arm: Add several LPI methods in Gicv3Redistributor

Refactoring the existing in code in smaller methods will be crucial when
adding the ITS module, which is a client for the redistributor class and
which will require it to take different actions depending on the command
it receives from software.

List of methods:

* read/writeEntryLPI
Reading/Writing a byte from the LPI pending table

* isPendingLPI
Checks if the pINTID LPI is set. Knowing if an LPI is set is needed by
the MOVI command, which is transfering the pending state from one
redistributor to the other only if the LPI is pending.

Change-Id: If14b1c28ff7f2aa20b12dcd822bf6a490cbe0270
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M src/dev/arm/gic_v3_redistributor.cc
M src/dev/arm/gic_v3_redistributor.hh
2 files changed, 51 insertions(+), 9 deletions(-)



diff --git a/src/dev/arm/gic_v3_redistributor.cc  
b/src/dev/arm/gic_v3_redistributor.cc

index 79de7d5..0ee6b8a 100644
--- a/src/dev/arm/gic_v3_redistributor.cc
+++ b/src/dev/arm/gic_v3_redistributor.cc
@@ -860,6 +860,43 @@
 }
 }

+uint8_t
+Gicv3Redistributor::readEntryLPI(uint32_t lpi_id)
+{
+Addr lpi_pending_entry_ptr = lpiPendingTablePtr + (lpi_id / 8);
+
+uint8_t lpi_pending_entry;
+ThreadContext * tc = gic->getSystem()->getThreadContext(cpuId);
+tc->getPhysProxy().readBlob(lpi_pending_entry_ptr,
+(uint8_t*) _pending_entry,
+sizeof(lpi_pending_entry));
+
+return lpi_pending_entry;
+}
+
+void
+Gicv3Redistributor::writeEntryLPI(uint32_t lpi_id, uint8_t  
lpi_pending_entry)

+{
+Addr lpi_pending_entry_ptr = lpiPendingTablePtr + (lpi_id / 8);
+
+ThreadContext * tc = gic->getSystem()->getThreadContext(cpuId);
+tc->getPhysProxy().writeBlob(lpi_pending_entry_ptr,
+(uint8_t*) _pending_entry,
+sizeof(lpi_pending_entry));
+}
+
+bool
+Gicv3Redistributor::isPendingLPI(uint32_t lpi_id)
+{
+// Fetch the LPI pending entry from memory
+uint8_t lpi_pending_entry = readEntryLPI(lpi_id);
+
+uint8_t lpi_pending_entry_bit_position = lpi_id % 8;
+bool is_set = lpi_pending_entry & (1 <<  
lpi_pending_entry_bit_position);

+
+return is_set;
+}
+
 void
 Gicv3Redistributor::setClrLPI(uint64_t data, bool set)
 {
@@ -878,12 +915,9 @@
 return;
 }

-Addr lpi_pending_entry_ptr = lpiPendingTablePtr + (lpi_id / 8);
-uint8_t lpi_pending_entry;
-ThreadContext * tc = gic->getSystem()->getThreadContext(cpuId);
-tc->getPhysProxy().readBlob(lpi_pending_entry_ptr,
-(uint8_t*) _pending_entry,
-sizeof(lpi_pending_entry));
+// Fetch the LPI pending entry from memory
+uint8_t lpi_pending_entry = readEntryLPI(lpi_id);
+
 uint8_t lpi_pending_entry_bit_position = lpi_id % 8;
 bool is_set = lpi_pending_entry & (1 <<  
lpi_pending_entry_bit_position);


@@ -905,9 +939,8 @@
 lpi_pending_entry &= ~(1 << (lpi_pending_entry_bit_position));
 }

-tc->getPhysProxy().writeBlob(lpi_pending_entry_ptr,
-(uint8_t*) _pending_entry,
-sizeof(lpi_pending_entry));
+writeEntryLPI(lpi_id, lpi_pending_entry);
+
 updateAndInformCPUInterface();
 }

diff --git a/src/dev/arm/gic_v3_redistributor.hh  
b/src/dev/arm/gic_v3_redistributor.hh

index 0e99b74..6aff91d 100644
--- a/src/dev/arm/gic_v3_redistributor.hh
+++ b/src/dev/arm/gic_v3_redistributor.hh
@@ -190,8 +190,17 @@
 return cpuInterface;
 }

+uint32_t
+processorNumber() const
+{
+return cpuId;
+}
+
 Gicv3::GroupId getIntGroup(int int_id) const;
 Gicv3::IntStatus intStatus(uint32_t int_id) const;
+uint8_t readEntryLPI(uint32_t intid);
+void writeEntryLPI(uint32_t intid, uint8_t lpi_entry);
+bool isPendingLPI(uint32_t intid);
 void setClrLPI(uint64_t data, bool set);
 void reset();
 void sendSGI(uint32_t int_id, Gicv3::GroupId group, bool ns);

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/18596
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: If14b1c28ff7f2aa20b12dcd822bf6a490cbe0270
Gerrit-Change-Number: 18596
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-MessageType: newchange
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in gem5/gem5[master]: dev-arm: Check EnableLPIs before checking for pending LPIs

[Giacomo Travaglini (Gerrit)]

Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/18592

to review the following change.


Change subject: dev-arm: Check EnableLPIs before checking for pending LPIs
..

dev-arm: Check EnableLPIs before checking for pending LPIs

Before reading the tables, GICR_PENDBASER and GICR_PROPBASER need to be
properly set, and those will have a consistent value only once sw
enables LPIs.

Change-Id: Ifb87944a491045e7a13ce7a280c555cb0c1e47f4
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M src/dev/arm/gic_v3_redistributor.cc
1 file changed, 31 insertions(+), 29 deletions(-)



diff --git a/src/dev/arm/gic_v3_redistributor.cc  
b/src/dev/arm/gic_v3_redistributor.cc

index d5a405a..2b73c57 100644
--- a/src/dev/arm/gic_v3_redistributor.cc
+++ b/src/dev/arm/gic_v3_redistributor.cc
@@ -830,38 +830,40 @@
 }

 // Check LPIs
-const uint32_t largest_lpi_id = 1 << (lpiIDBits + 1);
-char lpi_pending_table[largest_lpi_id / 8];
-ThreadContext * tc = gic->getSystem()->getThreadContext(cpuId);
-tc->getPhysProxy().readBlob(lpiPendingTablePtr,
-(uint8_t *) lpi_pending_table,
-sizeof(lpi_pending_table));
+if (EnableLPIs) {
+const uint32_t largest_lpi_id = 1 << (lpiIDBits + 1);
+char lpi_pending_table[largest_lpi_id / 8];
+ThreadContext * tc = gic->getSystem()->getThreadContext(cpuId);
+tc->getPhysProxy().readBlob(lpiPendingTablePtr,
+(uint8_t *) lpi_pending_table,
+sizeof(lpi_pending_table));

-for (int lpi_id = SMALLEST_LPI_ID; lpi_id < largest_lpi_id;
- lpi_id++) {
-uint32_t lpi_pending_entry_byte = lpi_id / 8;
-uint8_t lpi_pending_entry_bit_position = lpi_id % 8;
-bool lpi_is_pending = lpi_pending_table[lpi_pending_entry_byte] &
-  1 << lpi_pending_entry_bit_position;
-uint32_t lpi_configuration_entry_index = lpi_id - SMALLEST_LPI_ID;
-bool lpi_is_enable =
-lpiConfigurationTable[lpi_configuration_entry_index].enable;
-// LPIs are always Non-secure Group 1 interrupts,
-// in a system where two Security states are enabled.
-Gicv3::GroupId lpi_group = Gicv3::G1NS;
-bool group_enabled = distributor->groupEnabled(lpi_group);
+for (int lpi_id = SMALLEST_LPI_ID; lpi_id < largest_lpi_id;
+ lpi_id++) {
+uint32_t lpi_pending_entry_byte = lpi_id / 8;
+uint8_t lpi_pending_entry_bit_position = lpi_id % 8;
+bool lpi_is_pending =  
lpi_pending_table[lpi_pending_entry_byte] &

+  1 << lpi_pending_entry_bit_position;
+uint32_t lpi_configuration_entry_index = lpi_id -  
SMALLEST_LPI_ID;

+bool lpi_is_enable =
+ 
lpiConfigurationTable[lpi_configuration_entry_index].enable;

+// LPIs are always Non-secure Group 1 interrupts,
+// in a system where two Security states are enabled.
+Gicv3::GroupId lpi_group = Gicv3::G1NS;
+bool group_enabled = distributor->groupEnabled(lpi_group);

-if (lpi_is_pending && lpi_is_enable && group_enabled) {
-uint8_t lpi_priority =
- 
lpiConfigurationTable[lpi_configuration_entry_index].priority;

+if (lpi_is_pending && lpi_is_enable && group_enabled) {
+uint8_t lpi_priority =
+ 
lpiConfigurationTable[lpi_configuration_entry_index].priority;


-if ((lpi_priority < cpuInterface->hppi.prio) ||
-(lpi_priority == cpuInterface->hppi.prio &&
- lpi_id < cpuInterface->hppi.intid)) {
-cpuInterface->hppi.intid = lpi_id;
-cpuInterface->hppi.prio = lpi_priority;
-cpuInterface->hppi.group = lpi_group;
-new_hppi = true;
+if ((lpi_priority < cpuInterface->hppi.prio) ||
+(lpi_priority == cpuInterface->hppi.prio &&
+ lpi_id < cpuInterface->hppi.intid)) {
+cpuInterface->hppi.intid = lpi_id;
+cpuInterface->hppi.prio = lpi_priority;
+cpuInterface->hppi.group = lpi_group;
+new_hppi = true;
+}
 }
 }
 }

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/18592
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ifb87944a491045e7a13ce7a280c555cb0c1e47f4
Gerrit-Change-Number: 18592
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-MessageType: 

[gem5-dev] Change in gem5/gem5[master]: dev-arm: Get a Gicv3Redistributor ptr from phys address

[Giacomo Travaglini (Gerrit)]

Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/18597

to review the following change.


Change subject: dev-arm: Get a Gicv3Redistributor ptr from phys address
..

dev-arm: Get a Gicv3Redistributor ptr from phys address

The patch is adding the following method to Gicv3:

* Gicv3::getRedistributorByAddr
This will be needed by the ITS when trying to select the target
redistributor after decoding the collection table entry (RDBase).

Change-Id: I40e2c155f2fdc8ca6d3c20ff7a27702e02499f20
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M src/dev/arm/gic_v3.cc
M src/dev/arm/gic_v3.hh
2 files changed, 33 insertions(+), 20 deletions(-)



diff --git a/src/dev/arm/gic_v3.cc b/src/dev/arm/gic_v3.cc
index 2832d33..9004f65 100644
--- a/src/dev/arm/gic_v3.cc
+++ b/src/dev/arm/gic_v3.cc
@@ -110,19 +110,15 @@
 "size %d is_secure_access %d (value %#x)\n",
 pkt->req->contextId(), daddr, size, is_secure_access,  
resp);

 } else if (redistRange.contains(addr)) {
-Addr daddr = addr - redistRange.start();
-uint32_t redistributor_id =
-daddr / redistSize;
-daddr = daddr % redistSize;
-panic_if(redistributor_id >= redistributors.size(),
- "Invalid redistributor_id!");
-panic_if(!redistributors[redistributor_id], "Redistributor is  
null!");

-resp = redistributors[redistributor_id]->read(daddr, size,
-  is_secure_access);
+Addr daddr = (addr - redistRange.start()) % redistSize;
+
+Gicv3Redistributor *redist = getRedistributorByAddr(addr);
+resp = redist->read(daddr, size, is_secure_access);
+
 delay = params()->redist_pio_delay;
 DPRINTF(GIC, "Gicv3::read(): (redistributor %d) context_id %d "
 "register %#x size %d is_secure_access %d (value %#x)\n",
-redistributor_id, pkt->req->contextId(), daddr, size,
+redist->processorNumber(), pkt->req->contextId(), daddr,  
size,

 is_secure_access, resp);
 } else {
 panic("Gicv3::read(): unknown address %#x\n", addr);
@@ -151,19 +147,16 @@
 distributor->write(daddr, data, size, is_secure_access);
 delay = params()->dist_pio_delay;
 } else if (redistRange.contains(addr)) {
-Addr daddr = addr - redistRange.start();
-uint32_t redistributor_id =
-daddr / redistSize;
-daddr = daddr % redistSize;
-panic_if(redistributor_id >= redistributors.size(),
- "Invalid redistributor_id!");
-panic_if(!redistributors[redistributor_id], "Redistributor is  
null!");

+Addr daddr = (addr - redistRange.start()) % redistSize;
+
+Gicv3Redistributor *redist = getRedistributorByAddr(addr);
 DPRINTF(GIC, "Gicv3::write(): (redistributor %d) context_id %d "
 "register %#x size %d is_secure_access %d value %#x\n",
-redistributor_id, pkt->req->contextId(), daddr, size,
+redist->processorNumber(), pkt->req->contextId(), daddr,  
size,

 is_secure_access, data);
-redistributors[redistributor_id]->write(daddr, data, size,
-is_secure_access);
+
+redist->write(daddr, data, size, is_secure_access);
+
 delay = params()->redist_pio_delay;
 } else {
 panic("Gicv3::write(): unknown address %#x\n", addr);
@@ -228,6 +221,22 @@
 return nullptr;
 }

+Gicv3Redistributor *
+Gicv3::getRedistributorByAddr(Addr addr) const
+{
+panic_if(!redistRange.contains(addr),
+"Address not pointing to a valid redistributor\n");
+
+const Addr daddr = addr - redistRange.start();
+const uint32_t redistributor_id = daddr / redistSize;
+
+panic_if(redistributor_id >= redistributors.size(),
+ "Invalid redistributor_id!");
+panic_if(!redistributors[redistributor_id], "Redistributor is null!");
+
+return redistributors[redistributor_id];
+}
+
 void
 Gicv3::serialize(CheckpointOut & cp) const
 {
diff --git a/src/dev/arm/gic_v3.hh b/src/dev/arm/gic_v3.hh
index 48cc520..5a13a74 100644
--- a/src/dev/arm/gic_v3.hh
+++ b/src/dev/arm/gic_v3.hh
@@ -141,6 +141,10 @@

 Gicv3Redistributor *
 getRedistributorByAffinity(uint32_t affinity) const;
+
+Gicv3Redistributor *
+getRedistributorByAddr(Addr address) const;
+
 void postInt(uint32_t cpu, ArmISA::InterruptTypes int_type);
 };


--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/18597
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I40e2c155f2fdc8ca6d3c20ff7a27702e02499f20
Gerrit-Change-Number: 18597

[gem5-dev] Change in gem5/gem5[master]: dev-arm: Read correct version of ICC_BPR register

[Giacomo Travaglini (Gerrit)]

Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/18598

to review the following change.


Change subject: dev-arm: Read correct version of ICC_BPR register
..

dev-arm: Read correct version of ICC_BPR register

Some methods like groupPriorityMask check for the value of binary point
registers. Those registers have a minimum value.  Writing to those
register is taking this into account, but the problem with the minimum
value arises when the value is checked before sw is writing to them.
In this case the minimum value won't be considered if the read is
directly forwarded to the ISA class.

Change-Id: Id432a37f1634b02bc478d65c52ffb88323d4bb77
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M src/dev/arm/gic_v3_cpu_interface.cc
M src/dev/arm/gic_v3_cpu_interface.hh
2 files changed, 11 insertions(+), 6 deletions(-)



diff --git a/src/dev/arm/gic_v3_cpu_interface.cc  
b/src/dev/arm/gic_v3_cpu_interface.cc

index 3598f34..4a0a8e3 100644
--- a/src/dev/arm/gic_v3_cpu_interface.cc
+++ b/src/dev/arm/gic_v3_cpu_interface.cc
@@ -36,6 +36,9 @@
 #include "dev/arm/gic_v3_distributor.hh"
 #include "dev/arm/gic_v3_redistributor.hh"

+const uint8_t Gicv3CPUInterface::GIC_MIN_BPR;
+const uint8_t Gicv3CPUInterface::GIC_MIN_BPR_NS;
+
 Gicv3CPUInterface::Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id)
 : BaseISADevice(),
   gic(gic),
@@ -322,6 +325,8 @@
 bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR0_EL1);
 } else {
 bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR1_EL1);
+bpr = std::max(bpr, group == Gicv3::G1S ?
+GIC_MIN_BPR : GIC_MIN_BPR_NS);
 }

 if (sat_inc) {
@@ -1844,7 +1849,7 @@
  * GroupBits() Pseudocode from spec.
  */
 uint32_t
-Gicv3CPUInterface::groupPriorityMask(Gicv3::GroupId group) const
+Gicv3CPUInterface::groupPriorityMask(Gicv3::GroupId group)
 {
 ICC_CTLR_EL1 icc_ctlr_el1_s =
 isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S);
@@ -1859,9 +1864,9 @@
 int bpr;

 if (group == Gicv3::G0S) {
-bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR0_EL1) & 0x7;
+bpr = readMiscReg(MISCREG_ICC_BPR0_EL1) & 0x7;
 } else {
-bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR1_EL1) & 0x7;
+bpr = readMiscReg(MISCREG_ICC_BPR1_EL1) & 0x7;
 }

 if (group == Gicv3::G1NS) {
@@ -2165,7 +2170,7 @@
 }

 bool
-Gicv3CPUInterface::hppiCanPreempt() const
+Gicv3CPUInterface::hppiCanPreempt()
 {
 if (hppi.prio == 0xff) {
 // there is no pending interrupt
diff --git a/src/dev/arm/gic_v3_cpu_interface.hh  
b/src/dev/arm/gic_v3_cpu_interface.hh

index 931eb1d..e6dcb51 100644
--- a/src/dev/arm/gic_v3_cpu_interface.hh
+++ b/src/dev/arm/gic_v3_cpu_interface.hh
@@ -296,11 +296,11 @@
 uint32_t getHPPIR1() const;
 int getHPPVILR() const;
 bool groupEnabled(Gicv3::GroupId group) const;
-uint32_t groupPriorityMask(Gicv3::GroupId group) const;
+uint32_t groupPriorityMask(Gicv3::GroupId group);
 bool haveEL(ArmISA::ExceptionLevel el) const;
 int highestActiveGroup() const;
 uint8_t highestActivePriority() const;
-bool hppiCanPreempt() const;
+bool hppiCanPreempt();
 bool hppviCanPreempt(int lrIdx) const;
 bool inSecureState() const;
 ArmISA::InterruptTypes intSignalType(Gicv3::GroupId group) const;

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/18598
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Id432a37f1634b02bc478d65c52ffb88323d4bb77
Gerrit-Change-Number: 18598
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-MessageType: newchange
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in gem5/gem5[master]: base: Add argument to Coroutine class to not run on creation

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18588



Change subject: base: Add argument to Coroutine class to not run on creation
..

base: Add argument to Coroutine class to not run on creation

In some cases, the point where you create a Coroutine is not the same as
where you want to start running it (and want it to switch back to). This
leads to the unnecessary overhead of switching in and out of the
Coroutine. This change adds an optional boolean argument to the
constructor for the Coroutine class to allow for overriding the default
behavior of running the Coroutine upon creation, which in specific cases
can be used to avoid the unnecessary overhead and improve simulator
performance.

Change-Id: I044698f85e81ee4144208aee30d133bcb462d35d
---
M src/base/coroutine.hh
1 file changed, 10 insertions(+), 3 deletions(-)



diff --git a/src/base/coroutine.hh b/src/base/coroutine.hh
index d288892..35c3ab9 100644
--- a/src/base/coroutine.hh
+++ b/src/base/coroutine.hh
@@ -161,14 +161,21 @@
  * it needs to run. The first argument of the function should be a
  * reference to the Coroutine::caller_type which the
  * routine will use as a way for yielding to the caller.
+ * The optional second boolean argument controls if the Coroutine
+ * should be run on creation, which mimics Boost's Coroutine
+ * semantics by default. This can be disabled as an optimization to
+ * avoid unnecessary context switches on Coroutine creation.
  *
  * @param f task run by the coroutine
+ * @param run_coroutine set to false to disable running the coroutine
+ *  immediately after it is created
  */
-Coroutine(std::function f)
+Coroutine(std::function f, bool run_coroutine =  
true)

   : Fiber(), task(f), caller(*this)
 {
-// Create and Run the Coroutine
-this->call();
+// When desired, run the Coroutine after it is created
+if (run_coroutine)
+this->call();
 }

 virtual ~Coroutine() {}

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/18588
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I044698f85e81ee4144208aee30d133bcb462d35d
Gerrit-Change-Number: 18588
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-MessageType: newchange
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Cron /z/m5/regression/do-regression quick

[Cron Daemon]

* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic: 
FAILED!
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual:
 FAILED!
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing: 
FAILED!
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual:
 FAILED!
* 
build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic:
 FAILED!
* build/NULL/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby: FAILED!
* 
build/NULL_MOESI_hammer/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_hammer:
 FAILED!
* 
build/NULL_MESI_Two_Level/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MESI_Two_Level:
 FAILED!
* 
build/NULL_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_directory:
 FAILED!
* 
build/NULL_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_token:
 FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/minor-timing: 
FAILED!
* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/o3-timing: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-atomic: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing-ruby:
 FAILED!
* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/o3-timing: 
FAILED!
* build/HSAIL_X86/tests/opt/quick/se/04.gpu/x86/linux/gpu-ruby-GPU_RfO: 
FAILED!
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing: CHANGED!
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing: CHANGED!
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby: 
CHANGED!
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic: 
CHANGED!
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing: 
CHANGED!
* build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt: 
CHANGED!
* 
build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple:
 CHANGED!
* 
build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level:
 CHANGED!
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic: CHANGED!
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing: CHANGED!
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing: CHANGED!
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby: 
CHANGED!
* 
build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple:
 CHANGED!
* 
build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level:
 CHANGED!
* build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem: CHANGED!
* build/NULL/tests/opt/quick/se/80.dram-closepage/null/none/dram-lowp: 
CHANGED!* 
build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest-filter: passed.
* build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl: CHANGED!
* build/NULL/tests/opt/quick/se/80.dram-openpage/null/none/dram-lowp: 
CHANGED!
* build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing: CHANGED!
* build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic: 
CHANGED!
* build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic: 
CHANGED!
* build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing: 
CHANGED!
* build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby: 
CHANGED!
* build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing: CHANGED!
* build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic: 
CHANGED!
* build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing: 
CHANGED!
* 
build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple:
 CHANGED!
* 
build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level:
 CHANGED!
* build/SPARC/tests/opt/quick/se/10.mcf/sparc/linux/simple-atomic: CHANGED!
* build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic: 
CHANGED!
* build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing: 
CHANGED!
* 
build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp:
 CHANGED!
* 
build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp:
 CHANGED!
* 
build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp:
 CHANGED!
* build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-atomic: 
CHANGED!
* build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-timing: 
CHANGED!
* build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing: CHANGED!
* 

[gem5-dev] Change in gem5/gem5[master]: tests: Add missing kernels to system creation

[Daniel Carvalho (Gerrit)]

Daniel Carvalho has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18528 )


Change subject: tests: Add missing kernels to system creation
..

tests: Add missing kernels to system creation

Change 149c1fc2d070a8ce073263880ecf2ccf7535e569 removed the
default value of the kernels, and fs tests rely on those.

Change-Id: I6d83420af5881ab59c2d223a9915f363dd8a1c69
Signed-off-by: Daniel R. Carvalho 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18528
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M tests/configs/alpha_generic.py
M tests/configs/pc-simple-timing-ruby.py
M tests/configs/twosys-tsunami-simple-atomic.py
M tests/configs/x86_generic.py
4 files changed, 9 insertions(+), 5 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/tests/configs/alpha_generic.py b/tests/configs/alpha_generic.py
index a5be4f2..3547f69 100644
--- a/tests/configs/alpha_generic.py
+++ b/tests/configs/alpha_generic.py
@@ -40,7 +40,7 @@
 from m5.objects import *
 from m5.proxy import *
 m5.util.addToPath('../configs/')
-from common import FSConfig
+from common import FSConfig, SysPaths
 from common.Caches import *
 from base_config import *

@@ -60,6 +60,7 @@

 def create_system(self):
 system = FSConfig.makeLinuxAlphaSystem(self.mem_mode)
+system.kernel = SysPaths.binary('vmlinux')
 self.init_system(system)
 return system

diff --git a/tests/configs/pc-simple-timing-ruby.py  
b/tests/configs/pc-simple-timing-ruby.py

index 18c9909..ffac062 100644
--- a/tests/configs/pc-simple-timing-ruby.py
+++ b/tests/configs/pc-simple-timing-ruby.py
@@ -30,7 +30,7 @@
 from m5.objects import *
 m5.util.addToPath('../configs/')
 from common.Benchmarks import SysConfig
-from common import FSConfig
+from common import FSConfig, SysPaths
 from ruby import Ruby
 from common import Options

@@ -54,6 +54,7 @@
 mdesc = SysConfig(disk = 'linux-x86.img')
 system = FSConfig.makeLinuxX86System('timing', options.num_cpus,
  mdesc=mdesc, Ruby=True)
+system.kernel = SysPaths.binary('x86_64-vmlinux-2.6.22.9')
 # Dummy voltage domain for all our clock domains
 system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)

diff --git a/tests/configs/twosys-tsunami-simple-atomic.py  
b/tests/configs/twosys-tsunami-simple-atomic.py

index 7d0768e..3892745 100644
--- a/tests/configs/twosys-tsunami-simple-atomic.py
+++ b/tests/configs/twosys-tsunami-simple-atomic.py
@@ -29,11 +29,11 @@
 import m5
 from m5.objects import *
 m5.util.addToPath('../configs/')
-from common.FSConfig import *
-from common.Benchmarks import *
+from common import Benchmarks, FSConfig, SysPaths

 test_sys = makeLinuxAlphaSystem('atomic',
 SysConfig('netperf-stream-client.rcS'))
+test_sys.kernel = SysPaths.binary('vmlinux')

 # Dummy voltage domain for all test_sys clock domains
 test_sys.voltage_domain = VoltageDomain()
@@ -70,6 +70,7 @@

 drive_sys = makeLinuxAlphaSystem('atomic',
  SysConfig('netperf-server.rcS'))
+drive_sys.kernel = SysPaths.binary('vmlinux')
 # Dummy voltage domain for all drive_sys clock domains
 drive_sys.voltage_domain = VoltageDomain()
 # Create the system clock domain
diff --git a/tests/configs/x86_generic.py b/tests/configs/x86_generic.py
index 53c046a..e280fc5 100644
--- a/tests/configs/x86_generic.py
+++ b/tests/configs/x86_generic.py
@@ -41,7 +41,7 @@
 from m5.proxy import *
 m5.util.addToPath('../configs/')
 from common.Benchmarks import SysConfig
-from common import FSConfig
+from common import FSConfig, SysPaths
 from common.Caches import *
 from base_config import *

@@ -60,6 +60,7 @@
 system = FSConfig.makeLinuxX86System(self.mem_mode,
  numCPUs=self.num_cpus,
  mdesc=mdesc)
+system.kernel = SysPaths.binary('x86_64-vmlinux-2.6.22.9')

 self.init_system(system)
 return system

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/18528
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I6d83420af5881ab59c2d223a9915f363dd8a1c69
Gerrit-Change-Number: 18528
Gerrit-PatchSet: 2
Gerrit-Owner: Daniel Carvalho 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev