date:20210927

[gem5-dev] Re: failing ARM dual CPU tests?

2021-09-27 Thread Gabe Black via gem5-dev

I tried deleting the resources directory again, and this time when I re-ran
the normal tests they all passed. There must have been some file which got
caught crossways, or I thought I had deleted but the ownership of the
directory was wrong, or etc, etc. Anyways, I think the mysterious failures
may be gone now. I'm running the long tests to make sure those also are now
working at ToT, and then I'll run them again on the locked mem change to
see if that's ok.

It's always a little unnerving to now know *how* a mysterious failure like
this got resolved, but at least it seems to have which is good?

Gabe

On Fri, Sep 24, 2021 at 2:55 PM Bobby Bruce  wrote:

> Hey Gabe,
>
> This is very strange and I can't say I've seen this issue before. The
> problem shouldn't be docker, none of these tests spin up an instance. I was
> going to suggest deleting the resources (`tests/gem5/resources`) and trying
> again, but it seems like you've tried that. My only sensible guess at this
> point is your not downloading the resources needed (network issues?), as,
> unfortunately, the TestLib downloader fails silently (e.g. if the download
> fails it tends to continue to try to run the test). Though if this is the
> case. it'd be weird to just see these tests failing as we download quite a
> few things to get testing working.
>
> Have you looked into the output under `tests/testing-results` to see
> what's printing to stdout/stderr for these tests? Do you notice anything
> unusual there?
>
> Kind regards,
> Bobby
> --
> Dr. Bobby R. Bruce
> Room 3050,
> Kemper Hall, UC Davis
> Davis,
> CA, 95616
>
> web: https://www.bobbybruce.net
>
>
> On Wed, Sep 22, 2021 at 5:23 PM Gabe Black  wrote:
>
>> Thanks Giacomo, I *think* since these are running as part of the testing
>> infrastructure that they are downloading the files they need, and I hope
>> they are downloading current ones. Clearly *something* is out of whack, but
>> since this should all be handled automatically I don't know where or what
>> to look at to try to find what's out of date. I know once upon a time I had
>> an out of date docker that was causing problems, but I'm not using a docker
>> for this and so I don't think that's the problem(?).
>>
>> Do you have any ideas Bobby? I've tried deleting the resources directory
>> it downloads under tests, but that didn't seem to fix it.
>>
>> Gabe
>>
>> On Wed, Sep 22, 2021 at 9:17 AM Giacomo Travaglini <
>> giacomo.travagl...@arm.com> wrote:
>>
>>> Hi Gabe,
>>>
>>> From an Arm perspective, could you make sure you are using the latest
>>> bootloader?
>>> I remember there was a change some time ago which required the
>>> bootloader to be rebuilt
>>>
>>> You could either download latest tarball from
>>> https://www.gem5.org/documentation/general_docs/fullsystem/guest_binaries
>>>
>>> Or rebuild the bootloader yourself
>>>
>>> Kind Regards
>>>
>>> Giacomo
>>>
>>>
>>> > -Original Message-
>>> > From: Jason Lowe-Power via gem5-dev 
>>> > Sent: 22 September 2021 17:12
>>> > To: gem5 Developer List 
>>> > Cc: Gabe Black ; Jason Lowe-Power
>>> > 
>>> > Subject: [gem5-dev] Re: failing ARM dual CPU tests?
>>> >
>>> > Hey Gabe,
>>> >
>>> >
>>> > To solve this and the x86 test issue you've been having, I think there
>>> are a
>>> > couple of possibilities:
>>> >
>>> > 1. Can you use the docker images that kokoro uses? This will guarantee
>>> that
>>> > you are using the *exact* same "host" setup when running gem5. I think
>>> this
>>> > is the only way to have a consistent set of tests without something
>>> like
>>> > Bazel's reproducible build and test.
>>> > 2. We're open to modifying and improving the tests. If the tests don't
>>> work
>>> > for you, they probably don't work for others as well. Improving the
>>> > documentation so it's more clear how to use the tests or improving the
>>> > testing infrastructure or modifying the tests so that they work more
>>> easily for
>>> > more people would be a *very* welcome contribution.
>>> >
>>> > Cheers,
>>> > Jason
>>> >
>>> > On Tue, Sep 21, 2021 at 6:22 PM Gabe Black via gem5-dev >> > d...@gem5.org  > wrote:
>>> >
>>> >
>>> >   Hi folks. When I run the test script main.py locally on an
>>> otherwise
>>> > passing tree, I get 8 test failures. 6 of those are from x86 dynamic
>>> linking tests
>>> > which use a host library which uses a system call gem5 doesn't
>>> implement.
>>> > That is annoying, but I understand that problem.
>>> >
>>> >   The other 2 are from ARM dual CPU tests (like realview64-simple-
>>> > timing-dual-ARM-x86_64-opt-MatchFileRegex) which fail because the
>>> > second CPU doesn't come up, and the check doesn't see the message it
>>> > expects.
>>> >
>>> >   This is very surprising to me, since I don't think these tests
>>> would
>>> > have any host dependence, and I'm *pretty* sure that the files they use
>>> > would come from the resources thing and should be up to date, etc. The
>>> > system in the test seems to otherwise

[gem5-dev] Change in gem5/gem5[develop]: arch-vega: Fix VEGA_X86 build issues

2021-09-27 Thread Matthew Poremba (Gerrit) via gem5-dev

Matthew Poremba has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/47105 )


Change subject: arch-vega: Fix VEGA_X86 build issues
..

arch-vega: Fix VEGA_X86 build issues

The registerManager was not being dereferenced properly. Also remove
non-existant include file.

Change-Id: I5dac692abedc327ed83ee904e4c6ac5dac811e4c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47105
Reviewed-by: Matt Sinclair 
Maintainer: Matt Sinclair 
Tested-by: kokoro 
---
M src/arch/amdgpu/vega/insts/gpu_static_inst.cc
M src/arch/amdgpu/vega/insts/instructions.cc
M src/arch/amdgpu/vega/operand.hh
3 files changed, 25 insertions(+), 25 deletions(-)

Approvals:
  Matt Sinclair: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/amdgpu/vega/insts/gpu_static_inst.cc  
b/src/arch/amdgpu/vega/insts/gpu_static_inst.cc

index ffaffab..35819f0 100644
--- a/src/arch/amdgpu/vega/insts/gpu_static_inst.cc
+++ b/src/arch/amdgpu/vega/insts/gpu_static_inst.cc
@@ -36,7 +36,6 @@
 #include "arch/amdgpu/vega/gpu_decoder.hh"
 #include "arch/amdgpu/vega/insts/instructions.hh"
 #include "debug/GPUExec.hh"
-#include "gpu-compute/flexible_pool_manager.hh"
 #include "gpu-compute/shader.hh"

 namespace gem5
diff --git a/src/arch/amdgpu/vega/insts/instructions.cc  
b/src/arch/amdgpu/vega/insts/instructions.cc

index 96ef031..999eeac 100644
--- a/src/arch/amdgpu/vega/insts/instructions.cc
+++ b/src/arch/amdgpu/vega/insts/instructions.cc
@@ -1903,11 +1903,12 @@
 Inst_SOPK__S_MULK_I32::execute(GPUDynInstPtr gpuDynInst)
 {
 ScalarRegI16 simm16 = instData.SIMM16;
+ConstScalarOperandI32 src(gpuDynInst, instData.SDST);
 ScalarOperandI32 sdst(gpuDynInst, instData.SDST);

-sdst.read();
+src.read();

-sdst = sdst.rawData() * (ScalarRegI32)simm16;
+sdst = src.rawData() * (ScalarRegI32)simm16;

 sdst.write();
 } // execute
@@ -4172,7 +4173,7 @@
 DPRINTF(GPUExec, "CU%d: decrease ref ctr WG[%d] to [%d]\n",
 wf->computeUnit->cu_id, wf->wgId, refCount);

-wf->computeUnit->registerManager.freeRegisters(wf);
+wf->computeUnit->registerManager->freeRegisters(wf);
 wf->computeUnit->stats.completedWfs++;
 wf->computeUnit->activeWaves--;

@@ -5641,7 +5642,7 @@
 sdata.read();

 std::memcpy((void*)gpuDynInst->scalar_data, sdata.rawDataPtr(),
-4 * sizeof(ScalarRegU32));
+sizeof(gpuDynInst->scalar_data));

 if (instData.IMM) {
 offset = extData.OFFSET;
diff --git a/src/arch/amdgpu/vega/operand.hh  
b/src/arch/amdgpu/vega/operand.hh

index 1c37a0f..e9e1fd0 100644
--- a/src/arch/amdgpu/vega/operand.hh
+++ b/src/arch/amdgpu/vega/operand.hh
@@ -154,7 +154,7 @@
 ComputeUnit *cu = _gpuDynInst->computeUnit();

 for (auto i = 0; i < NumDwords; ++i) {
-int vgprIdx = cu->registerManager.mapVgpr(wf, _opIdx + i);
+int vgprIdx = cu->registerManager->mapVgpr(wf, _opIdx + i);
 vrfData[i] = >vrf[wf->simdId]->readWriteable(vgprIdx);

 DPRINTF(GPUVRF, "Read v[%d]\n", vgprIdx);
@@ -208,7 +208,7 @@
 ? _gpuDynInst->exec_mask : wf->execMask();

 if (NumDwords == 1) {
-int vgprIdx = cu->registerManager.mapVgpr(wf, _opIdx);
+int vgprIdx = cu->registerManager->mapVgpr(wf, _opIdx);
 vrfData[0] = >vrf[wf->simdId]->readWriteable(vgprIdx);
 assert(vrfData[0]);
 auto reg_file_vgpr = vrfData[0]->template as();
@@ -224,8 +224,8 @@
 DPRINTF(GPUVRF, "Write v[%d]\n", vgprIdx);
 cu->vrf[wf->simdId]->printReg(wf, vgprIdx);
 } else if (NumDwords == 2) {
-int vgprIdx0 = cu->registerManager.mapVgpr(wf, _opIdx);
-int vgprIdx1 = cu->registerManager.mapVgpr(wf, _opIdx + 1);
+int vgprIdx0 = cu->registerManager->mapVgpr(wf, _opIdx);
+int vgprIdx1 = cu->registerManager->mapVgpr(wf, _opIdx +  
1);

 vrfData[0] = >vrf[wf->simdId]->readWriteable(vgprIdx0);
 vrfData[1] = >vrf[wf->simdId]->readWriteable(vgprIdx1);
 assert(vrfData[0]);
@@ -521,7 +521,7 @@
 ScalarRegU64 exec_mask = _gpuDynInst->wavefront()->
 execMask().to_ullong();
 std::memcpy((void*)srfData.data(), (void*)_mask,
-sizeof(srfData));
+sizeof(exec_mask));
 DPRINTF(GPUSRF, "Read EXEC\n");
 DPRINTF(GPUSRF, "EXEC = %#x\n", exec_mask);
 }
@@ -538,7 +538,7 @@

 ScalarRegU32 exec_mask_hi = bits(exec_mask, 63, 32);
 std::memcpy((void*)srfData.data(),  
(void*)_mask_hi,

[gem5-dev] Change in gem5/gem5[develop]: arch-vega: Issue flat insts using on executedAs()

2021-09-27 Thread Matthew Poremba (Gerrit) via gem5-dev

Matthew Poremba has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/50827 )


Change subject: arch-vega: Issue flat insts using on executedAs()
..

arch-vega: Issue flat insts using on executedAs()

Similar to the flags issue in the previous patch, the FlatGlobal flag
does not exist. Change all of the flat instructions to use the same
issue logic as GCN3. A helper function is also added as loads and stores
use the same interface. The helper function can be more easily updated
to support global and scratch subtypes of flat instructions.

Change-Id: I394f1d4c59b029201fe2f6075c9dedb3a37dbe31
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50827
Reviewed-by: Matt Sinclair 
Reviewed-by: Kyle Roarty 
Maintainer: Matt Sinclair 
Tested-by: kokoro 
---
M src/arch/amdgpu/vega/insts/instructions.cc
M src/arch/amdgpu/vega/insts/op_encodings.hh
2 files changed, 36 insertions(+), 108 deletions(-)

Approvals:
  Matt Sinclair: Looks good to me, approved; Looks good to me, approved
  Kyle Roarty: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/amdgpu/vega/insts/instructions.cc  
b/src/arch/amdgpu/vega/insts/instructions.cc

index afd750a..cf5c415 100644
--- a/src/arch/amdgpu/vega/insts/instructions.cc
+++ b/src/arch/amdgpu/vega/insts/instructions.cc
@@ -42814,12 +42814,7 @@

 calcAddr(gpuDynInst, addr, instData.OFFSET);

-if (isFlatGlobal()) {
-gpuDynInst->computeUnit()->globalMemoryPipe
-.issueRequest(gpuDynInst);
-} else {
-fatal("Non global flat instructions not implemented yet.\n");
-}
+issueRequestHelper(gpuDynInst);
 } // execute

 void
@@ -42907,12 +42902,7 @@

 calcAddr(gpuDynInst, addr, instData.OFFSET);

-if (isFlatGlobal()) {
-gpuDynInst->computeUnit()->globalMemoryPipe
-.issueRequest(gpuDynInst);
-} else {
-fatal("Non global flat instructions not implemented yet.\n");
-}
+issueRequestHelper(gpuDynInst);
 } // execute

 void
@@ -43001,12 +42991,7 @@

 calcAddr(gpuDynInst, addr, instData.OFFSET);

-if (isFlatGlobal()) {
-gpuDynInst->computeUnit()->globalMemoryPipe
-.issueRequest(gpuDynInst);
-} else {
-fatal("Non global flat instructions not implemented yet.\n");
-}
+issueRequestHelper(gpuDynInst);
 } // execute

 void
@@ -43065,12 +43050,7 @@

 calcAddr(gpuDynInst, addr, instData.OFFSET);

-if (isFlatGlobal()) {
-gpuDynInst->computeUnit()->globalMemoryPipe
-.issueRequest(gpuDynInst);
-} else {
-fatal("Non global flat instructions not implemented yet.\n");
-}
+issueRequestHelper(gpuDynInst);
 } // execute

 void
@@ -43129,12 +43109,7 @@

 calcAddr(gpuDynInst, addr, instData.OFFSET);

-if (isFlatGlobal()) {
-gpuDynInst->computeUnit()->globalMemoryPipe
-.issueRequest(gpuDynInst);
-} else {
-fatal("Non global flat instructions not implemented yet.\n");
-}
+issueRequestHelper(gpuDynInst);
 } // execute

 void
@@ -43202,12 +43177,7 @@

 calcAddr(gpuDynInst, addr, instData.OFFSET);

-if (isFlatGlobal()) {
-gpuDynInst->computeUnit()->globalMemoryPipe
-.issueRequest(gpuDynInst);
-} else {
-fatal("Non global flat instructions not implemented yet.\n");
-}
+issueRequestHelper(gpuDynInst);
 } // execute

 void
@@ -43279,7 +43249,6 @@
 addr.read();
 data.read();

-
 calcAddr(gpuDynInst, addr, instData.OFFSET);

 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
@@ -43289,12 +43258,7 @@
 }
 }

-if (isFlatGlobal()) {
-gpuDynInst->computeUnit()->globalMemoryPipe
-.issueRequest(gpuDynInst);
-} else {
-fatal("Non global flat instructions not implemented yet.\n");
-}
+issueRequestHelper(gpuDynInst);
 } // execute

 void
@@ -43353,12 +43317,7 @@
 }
 }

-if (isFlatGlobal()) {
-gpuDynInst->computeUnit()->globalMemoryPipe
-.issueRequest(gpuDynInst);
-} else {
-fatal("Non global flat instructions not implemented yet.\n");
-}
+issueRequestHelper(gpuDynInst);
 } // execute

 void
@@ -43417,12 +43376,7 @@
 }
 }

-if (isFlatGlobal()) {
-gpuDynInst->computeUnit()->globalMemoryPipe
-.issueRequest(gpuDynInst);
-} else {
-fatal("Non global flat instructions not implemented yet.\n");
-}
+issueRequestHelper(gpuDynInst);
 } // execute

 void
@@

[gem5-dev] Change in gem5/gem5[develop]: arch-vega: Add missing functions referenced by insts

2021-09-27 Thread Matthew Poremba (Gerrit) via gem5-dev

Matthew Poremba has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/47103 )




6 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

Change subject: arch-vega: Add missing functions referenced by insts
..

arch-vega: Add missing functions referenced by insts

Some instructions were referencing pc() and isExecMaskRegister() which
were not defined.

Change-Id: Ic5b3fa9057950ff85603fcb87447a81b6c7f274b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47103
Tested-by: kokoro 
Reviewed-by: Matt Sinclair 
Maintainer: Matt Sinclair 
---
M src/arch/amdgpu/vega/insts/gpu_static_inst.hh
M src/gpu-compute/gpu_dyn_inst.cc
M src/gpu-compute/gpu_dyn_inst.hh
3 files changed, 21 insertions(+), 0 deletions(-)

Approvals:
  Matt Sinclair: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/amdgpu/vega/insts/gpu_static_inst.hh  
b/src/arch/amdgpu/vega/insts/gpu_static_inst.hh

index 64151f7..fa2a8e1 100644
--- a/src/arch/amdgpu/vega/insts/gpu_static_inst.hh
+++ b/src/arch/amdgpu/vega/insts/gpu_static_inst.hh
@@ -60,6 +60,12 @@
 return isFlatScratchReg(opIdx);
 }

+bool
+isExecMaskRegister(int opIdx) override
+{
+return isExecMask(opIdx);
+}
+
 void initOperandInfo() override { return; }
 int getOperandSize(int opIdx) override { return 0; }

diff --git a/src/gpu-compute/gpu_dyn_inst.cc  
b/src/gpu-compute/gpu_dyn_inst.cc

index 937e572..1eadfa9 100644
--- a/src/gpu-compute/gpu_dyn_inst.cc
+++ b/src/gpu-compute/gpu_dyn_inst.cc
@@ -284,6 +284,18 @@
 return _seqNum;
 }

+Addr
+GPUDynInst::pc()
+{
+return wavefront()->pc();
+}
+
+void
+GPUDynInst::pc(Addr _pc)
+{
+wavefront()->pc(_pc);
+}
+
 enums::StorageClassType
 GPUDynInst::executedAs()
 {
diff --git a/src/gpu-compute/gpu_dyn_inst.hh  
b/src/gpu-compute/gpu_dyn_inst.hh

index ae8260e..f673afe 100644
--- a/src/gpu-compute/gpu_dyn_inst.hh
+++ b/src/gpu-compute/gpu_dyn_inst.hh
@@ -162,6 +162,9 @@

 InstSeqNum seqNum() const;

+Addr pc();
+void pc(Addr _pc);
+
 enums::StorageClassType executedAs();

 // virtual address for scalar memory operations

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/47103
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic5b3fa9057950ff85603fcb87447a81b6c7f274b
Gerrit-Change-Number: 47103
Gerrit-PatchSet: 8
Gerrit-Owner: Matthew Poremba 
Gerrit-Reviewer: Alex Dutu 
Gerrit-Reviewer: Kyle Roarty 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Jason Lowe-Power 
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: arch-vega: Update instruction stats

2021-09-27 Thread Matthew Poremba (Gerrit) via gem5-dev

Matthew Poremba has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/47104 )




4 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

Change subject: arch-vega: Update instruction stats
..

arch-vega: Update instruction stats

These stats were moved to a Stats::Group but the instructions were not
updated to use the stats struct.

Change-Id: I49348e30bc0988a2a873f51bd7079c1f315649b4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47104
Tested-by: kokoro 
Reviewed-by: Matt Sinclair 
Maintainer: Matt Sinclair 
---
M src/arch/amdgpu/vega/insts/instructions.cc
1 file changed, 4 insertions(+), 4 deletions(-)

Approvals:
  Matt Sinclair: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/amdgpu/vega/insts/instructions.cc  
b/src/arch/amdgpu/vega/insts/instructions.cc

index cf5c415..96ef031 100644
--- a/src/arch/amdgpu/vega/insts/instructions.cc
+++ b/src/arch/amdgpu/vega/insts/instructions.cc
@@ -4173,7 +4173,7 @@
 wf->computeUnit->cu_id, wf->wgId, refCount);

 wf->computeUnit->registerManager.freeRegisters(wf);
-wf->computeUnit->completedWfs++;
+wf->computeUnit->stats.completedWfs++;
 wf->computeUnit->activeWaves--;

 panic_if(wf->computeUnit->activeWaves < 0, "CU[%d] Active waves  
less "

@@ -4184,7 +4184,7 @@

 for (int i = 0; i < wf->vecReads.size(); i++) {
 if (wf->rawDist.find(i) != wf->rawDist.end()) {
-wf->readsPerWrite.sample(wf->vecReads.at(i));
+wf->stats.readsPerWrite.sample(wf->vecReads.at(i));
 }
 }
 wf->vecReads.clear();
@@ -4226,7 +4226,7 @@
 if (!kernelEnd || !relNeeded) {
 wf->computeUnit->shader->dispatcher().notifyWgCompl(wf);
 wf->setStatus(Wavefront::S_STOPPED);
-wf->computeUnit->completedWGs++;
+wf->computeUnit->stats.completedWGs++;

 return;
 }
@@ -4254,7 +4254,7 @@
 // call shader to prepare the flush operations
 wf->computeUnit->shader->prepareFlush(gpuDynInst);

-wf->computeUnit->completedWGs++;
+wf->computeUnit->stats.completedWGs++;
 } else {
 wf->computeUnit->shader->dispatcher().scheduleDispatch();
 }

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/47104
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I49348e30bc0988a2a873f51bd7079c1f315649b4
Gerrit-Change-Number: 47104
Gerrit-PatchSet: 8
Gerrit-Owner: Matthew Poremba 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: tests: update nightly tests to document square

2021-09-27 Thread Matt Sinclair (Gerrit) via gem5-dev

Matt Sinclair has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/50949 )


Change subject: tests: update nightly tests to document square
..

tests: update nightly tests to document square

Add some information and comments on why square is included in the
nightly tests.

Change-Id: I80b61fb90f16ad0d693ec29975908549e8102382
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50949
Maintainer: Matt Sinclair 
Tested-by: kokoro 
Reviewed-by: Bobby R. Bruce 
---
M tests/nightly.sh
1 file changed, 20 insertions(+), 0 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved
  Matt Sinclair: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/tests/nightly.sh b/tests/nightly.sh
index 3ffdbcd..91b19f5 100755
--- a/tests/nightly.sh
+++ b/tests/nightly.sh
@@ -91,10 +91,14 @@
 "scons build/GCN3_X86/gem5.opt -j${threads} \
 || (rm -rf build && scons build/GCN3_X86/gem5.opt -j${threads})"

+# get square
 wget -qN http://dist.gem5.org/dist/develop/test-progs/square/square

 mkdir -p tests/testing-results

+# Square is the simplest, fastest, more heavily tested GPU application
+# Thus, we always want to run this in the nightly regressions to make sure
+# basic GPU functionality is working.
 docker run --rm -u $UID:$GUID --volume "${gem5_root}":"${gem5_root}" -w \
 "${gem5_root}" gcr.io/gem5-test/gcn-gpu:latest build/GCN3_X86/gem5.opt  
\

 configs/example/apu_se.py -n3 -c square

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/50949
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I80b61fb90f16ad0d693ec29975908549e8102382
Gerrit-Change-Number: 50949
Gerrit-PatchSet: 2
Gerrit-Owner: Matt Sinclair 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Add missing Armv8.2 extensions to the enum

2021-09-27 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/51017 )



Change subject: arch-arm: Add missing Armv8.2 extensions to the enum
..

arch-arm: Add missing Armv8.2 extensions to the enum

Change-Id: Ie98d06909fada7ca1370f2283ef0fce61b6dc953
Signed-off-by: Giacomo Travaglini 
---
M src/arch/arm/ArmSystem.py
M src/arch/arm/isa.cc
M src/arch/arm/system.cc
3 files changed, 32 insertions(+), 3 deletions(-)



diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index fbb2cff..4ec0838 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -55,6 +55,9 @@

 # Armv8.2
 'FEAT_SVE',
+'FEAT_UAO',
+'FEAT_LVA', # Optional in Armv8.2
+'FEAT_LPA', # Optional in Armv8.2

 # Armv8.4
 'FEAT_SEL2',
@@ -100,8 +103,12 @@

 class ArmDefaultRelease(Armv8):
 extensions = Armv8.extensions + [
-'FEAT_SVE', 'FEAT_LSE', 'FEAT_PAN',
-'FEAT_HPDS', 'FEAT_VMID16', 'FEAT_RDM', 'FEAT_SEL2'
+# Armv8.1
+'FEAT_LSE', 'FEAT_PAN', 'FEAT_HPDS', 'FEAT_VMID16', 'FEAT_RDM',
+# Armv8.2
+'FEAT_UAO', 'FEAT_LVA', 'FEAT_LPA', 'FEAT_SVE',
+# Armv8.4
+'FEAT_SEL2'
 ]

 class Armv81(Armv8):
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 84d9e51..6691901 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -455,6 +455,16 @@
 miscRegs[MISCREG_ID_AA64MMFR1_EL1], 23, 20,
 release->has(ArmExtension::FEAT_PAN) ? 0x1 : 0x0);

+/** MISCREG_ID_AA64MMFR2_EL1 */
+// UAO
+miscRegs[MISCREG_ID_AA64MMFR2_EL1] = insertBits(
+miscRegs[MISCREG_ID_AA64MMFR2_EL1], 7, 4,
+release->has(ArmExtension::FEAT_UAO) ? 0x1 : 0x0);
+// LVA
+miscRegs[MISCREG_ID_AA64MMFR2_EL1] = insertBits(
+miscRegs[MISCREG_ID_AA64MMFR2_EL1], 19, 16,
+release->has(ArmExtension::FEAT_LVA) ? 0x1 : 0x0);
+

 // TME
 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
diff --git a/src/arch/arm/system.cc b/src/arch/arm/system.cc
index 4edc350..747695f 100644
--- a/src/arch/arm/system.cc
+++ b/src/arch/arm/system.cc
@@ -102,7 +102,9 @@
 if (_highestELIs64 && (
 _physAddrRange64 < 32 ||
 _physAddrRange64 > MaxPhysAddrRange ||
-(_physAddrRange64 % 4 != 0 && _physAddrRange64 != 42))) {
+(_physAddrRange64 % 4 != 0 && _physAddrRange64 != 42) ||
+(_physAddrRange64 == 52  
&& !release->has(ArmExtension::FEAT_LPA

+{
 fatal("Invalid physical address range (%d)\n", _physAddrRange64);
 }
 }

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/51017
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie98d06909fada7ca1370f2283ef0fce61b6dc953
Gerrit-Change-Number: 51017
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Add an Armv8.3 ArmRelease object

2021-09-27 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/51020 )



Change subject: arch-arm: Add an Armv8.3 ArmRelease object
..

arch-arm: Add an Armv8.3 ArmRelease object

Change-Id: I7bd5fee4a5958f6669e1d0ac29e0c62f8f019204
Signed-off-by: Giacomo Travaglini 
---
M src/arch/arm/ArmSystem.py
1 file changed, 15 insertions(+), 0 deletions(-)



diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index 9ac533c..5bd03dc 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -129,6 +129,11 @@
 'FEAT_UAO', 'FEAT_LVA', 'FEAT_LPA', 'FEAT_SVE'
 ]

+class Armv83(Armv82):
+extensions = Armv82.extensions + [
+'FEAT_FCMA', 'FEAT_JSCVT', 'FEAT_PAuth',
+]
+
 class ArmSystem(System):
 type = 'ArmSystem'
 cxx_header = "arch/arm/system.hh"

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/51020
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I7bd5fee4a5958f6669e1d0ac29e0c62f8f019204
Gerrit-Change-Number: 51020
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Add an Armv8.4 ArmRelease object

2021-09-27 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/51021 )



Change subject: arch-arm: Add an Armv8.4 ArmRelease object
..

arch-arm: Add an Armv8.4 ArmRelease object

Change-Id: I0fc4301be2b4f3fa29c4320ab747bfa88132d434
Signed-off-by: Giacomo Travaglini 
---
M src/arch/arm/ArmSystem.py
1 file changed, 15 insertions(+), 0 deletions(-)



diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index 5bd03dc..f9df791 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -134,6 +134,11 @@
 'FEAT_FCMA', 'FEAT_JSCVT', 'FEAT_PAuth',
 ]

+class Armv84(Armv83):
+extensions = Armv83.extensions + [
+'FEAT_SEL2'
+]
+
 class ArmSystem(System):
 type = 'ArmSystem'
 cxx_header = "arch/arm/system.hh"

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/51021
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I0fc4301be2b4f3fa29c4320ab747bfa88132d434
Gerrit-Change-Number: 51021
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Add missing Armv8.3 extensions to the enum

2021-09-27 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/51019 )



Change subject: arch-arm: Add missing Armv8.3 extensions to the enum
..

arch-arm: Add missing Armv8.3 extensions to the enum

Change-Id: Id3897c59a12189f4aac6a3923f656e1f6b8f6723
Signed-off-by: Giacomo Travaglini 
---
M src/arch/arm/ArmSystem.py
M src/arch/arm/isa.cc
M src/arch/arm/ArmISA.py
3 files changed, 53 insertions(+), 1 deletion(-)



diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index e98041c..66133bf 100644
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -47,7 +47,15 @@

 class ArmDefaultSERelease(ArmRelease):
 extensions = [
-'CRYPTO', 'FEAT_SVE', 'FEAT_LSE', 'FEAT_RDM', 'TME'
+'CRYPTO',
+# Armv8.1
+'FEAT_LSE', 'FEAT_RDM',
+# Armv8.2
+'FEAT_SVE',
+# Armv8.3
+'FEAT_FCMA', 'FEAT_JSCVT', 'FEAT_PAuth',
+# Other
+'TME'
 ]

 class ArmISA(BaseISA):
diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index 837124b..9ac533c 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -59,6 +59,11 @@
 'FEAT_LVA', # Optional in Armv8.2
 'FEAT_LPA', # Optional in Armv8.2

+# Armv8.3
+'FEAT_FCMA',
+'FEAT_JSCVT',
+'FEAT_PAuth',
+
 # Armv8.4
 'FEAT_SEL2',

@@ -107,6 +112,8 @@
 'FEAT_LSE', 'FEAT_PAN', 'FEAT_HPDS', 'FEAT_VMID16', 'FEAT_RDM',
 # Armv8.2
 'FEAT_UAO', 'FEAT_LVA', 'FEAT_LPA', 'FEAT_SVE',
+# Armv8.3
+'FEAT_FCMA', 'FEAT_JSCVT', 'FEAT_PAuth',
 # Armv8.4
 'FEAT_SEL2'
 ]
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 6691901..c1be1a7 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -361,6 +361,15 @@
 miscRegs[MISCREG_ID_ISAR5] = insertBits(
 miscRegs[MISCREG_ID_ISAR5], 27, 24,
 release->has(ArmExtension::FEAT_RDM) ? 0x1 : 0x0);
+// FCMA
+miscRegs[MISCREG_ID_ISAR5] = insertBits(
+miscRegs[MISCREG_ID_ISAR5], 31, 28,
+release->has(ArmExtension::FEAT_FCMA) ? 0x1 : 0x0);
+
+/** ID_ISAR6 */
+miscRegs[MISCREG_ID_ISAR6] = insertBits(
+miscRegs[MISCREG_ID_ISAR6], 3, 0,
+release->has(ArmExtension::FEAT_JSCVT) ? 0x1 : 0x0);
 }

 void
@@ -437,6 +446,24 @@
 miscRegs[MISCREG_ID_AA64ISAR0_EL1], 31, 28,
 release->has(ArmExtension::FEAT_RDM) ? 0x1 : 0x0);

+/** MISCREG_ID_AA64ISAR1_EL1 */
+// PAuth, APA
+miscRegs[MISCREG_ID_AA64ISAR1_EL1] = insertBits(
+miscRegs[MISCREG_ID_AA64ISAR1_EL1], 7, 4,
+release->has(ArmExtension::FEAT_PAuth) ? 0x1 : 0x0);
+// JSCVT
+miscRegs[MISCREG_ID_AA64ISAR1_EL1] = insertBits(
+miscRegs[MISCREG_ID_AA64ISAR1_EL1], 15, 12,
+release->has(ArmExtension::FEAT_JSCVT) ? 0x1 : 0x0);
+// FCMA
+miscRegs[MISCREG_ID_AA64ISAR1_EL1] = insertBits(
+miscRegs[MISCREG_ID_AA64ISAR1_EL1], 19, 16,
+release->has(ArmExtension::FEAT_FCMA) ? 0x1 : 0x0);
+// PAuth, GPA
+miscRegs[MISCREG_ID_AA64ISAR1_EL1] = insertBits(
+miscRegs[MISCREG_ID_AA64ISAR1_EL1], 27, 24,
+release->has(ArmExtension::FEAT_PAuth) ? 0x1 : 0x0);
+
 /** MISCREG_ID_AA64MMFR1_EL1 */
 // VMID16
 miscRegs[MISCREG_ID_AA64MMFR1_EL1] = insertBits(

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/51019
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id3897c59a12189f4aac6a3923f656e1f6b8f6723
Gerrit-Change-Number: 51019
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Add an Armv8.2 ArmRelease object

2021-09-27 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/51018 )



Change subject: arch-arm: Add an Armv8.2 ArmRelease object
..

arch-arm: Add an Armv8.2 ArmRelease object

Change-Id: I731dde9687b36dc769b18cadcffe07a70868e965
Signed-off-by: Giacomo Travaglini 
---
M src/arch/arm/ArmSystem.py
1 file changed, 15 insertions(+), 0 deletions(-)



diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index 4ec0838..837124b 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -117,6 +117,11 @@
 'FEAT_HPDS', 'FEAT_VMID16', 'FEAT_RDM'
 ]

+class Armv82(Armv81):
+extensions = Armv81.extensions + [
+'FEAT_UAO', 'FEAT_LVA', 'FEAT_LPA', 'FEAT_SVE'
+]
+
 class ArmSystem(System):
 type = 'ArmSystem'
 cxx_header = "arch/arm/system.hh"

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/51018
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I731dde9687b36dc769b18cadcffe07a70868e965
Gerrit-Change-Number: 51018
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Use ArmRelease in the ISA class

2021-09-27 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/51012 )



Change subject: arch-arm: Use ArmRelease in the ISA class
..

arch-arm: Use ArmRelease in the ISA class

This is removing the cached boolean variables from the ISA class.
The ISA is now using a release object.

It is importing it from the ArmSystem in case of a FS simulation,
and it is using its own ArmRelease object in SE mode

This allows us to add/remove SE extensions from python, rather than
hardcoding them in the ISA constructor (in case of SE)

Change-Id: I2b0b2f113e7bb9e28ac86bf2139413e2a71eeb01
Signed-off-by: Giacomo Travaglini 
---
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
M src/arch/arm/regs/misc.cc
M src/arch/arm/ArmISA.py
4 files changed, 182 insertions(+), 127 deletions(-)



diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index 23338d1..0a2bbc6 100644
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -38,13 +38,18 @@

 from m5.SimObject import SimObject
 from m5.objects.ArmPMU import ArmPMU
-from m5.objects.ArmSystem import SveVectorLength
+from m5.objects.ArmSystem import SveVectorLength, ArmRelease
 from m5.objects.BaseISA import BaseISA
 from m5.objects.ISACommon import VecRegRenameMode

 # Enum for DecoderFlavor
 class DecoderFlavor(Enum): vals = ['Generic']

+class ArmDefaultSERelease(ArmRelease):
+extensions = [
+'CRYPTO', 'FEAT_SVE', 'FEAT_LSE', 'TME', 'FEAT_SEL2'
+]
+
 class ArmISA(BaseISA):
 type = 'ArmISA'
 cxx_class = 'gem5::ArmISA::ISA'
@@ -56,6 +61,9 @@
 decoderFlavor = Param.DecoderFlavor(
 'Generic', "Decoder flavor specification")

+release_se = Param.ArmRelease(ArmDefaultSERelease(),
+"Set of features/extensions to use in SE mode")
+
 # If no MIDR value is provided, 0x0 is treated by gem5 as follows:
 # When 'highest_el_is_64' (AArch64 support) is:
 #   True  -> Cortex-A57 TRM r0p0 MIDR is used
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index ee9c556..54e574d 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -103,32 +103,18 @@
 // Cache system-level properties
 if (FullSystem && system) {
 highestELIs64 = system->highestELIs64();
-haveSecurity = system->has(ArmExtension::SECURITY);
-haveLPAE = system->has(ArmExtension::LPAE);
-haveCrypto = system->has(ArmExtension::CRYPTO);
-haveVirtualization = system->has(ArmExtension::VIRTUALIZATION);
 haveLargeAsid64 = system->haveLargeAsid64();
 physAddrRange = system->physAddrRange();
-haveSVE = system->has(ArmExtension::FEAT_SVE);
-haveVHE = system->has(ArmExtension::FEAT_VHE);
-havePAN = system->has(ArmExtension::FEAT_PAN);
-haveSecEL2 = system->has(ArmExtension::FEAT_SEL2);
 sveVL = system->sveVL();
-haveLSE = system->has(ArmExtension::FEAT_LSE);
-haveTME = system->has(ArmExtension::TME);
+
+release = system->releaseFS();
 } else {
 highestELIs64 = true; // ArmSystem::highestELIs64 does the same
-haveSecurity = haveLPAE = haveVirtualization = false;
-haveCrypto = true;
 haveLargeAsid64 = false;
 physAddrRange = 32;  // dummy value
-haveSVE = true;
-haveVHE = false;
-havePAN = false;
-haveSecEL2 = true;
 sveVL = p.sve_vl_se;
-haveLSE = true;
-haveTME = true;
+
+release = p.release_se;
 }

 selfDebug = new SelfDebug();
@@ -264,7 +250,7 @@

 miscRegs[MISCREG_FPSID] = p.fpsid;

-if (haveLPAE) {
+if (release->has(ArmExtension::LPAE)) {
 TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS];
 ttbcr.eae = 0;
 miscRegs[MISCREG_TTBCR_NS] = ttbcr;
@@ -272,7 +258,7 @@
 miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) |  
0x5;

 }

-if (haveSecurity) {
+if (release->has(ArmExtension::SECURITY)) {
 miscRegs[MISCREG_SCTLR_S] = sctlr;
 miscRegs[MISCREG_SCR] = 0;
 miscRegs[MISCREG_VBAR_S] = 0;
@@ -319,10 +305,10 @@

 // Initialize other control registers
 miscRegs[MISCREG_MPIDR_EL1] = 0x8000;
-if (haveSecurity) {
+if (release->has(ArmExtension::SECURITY)) {
 miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830;
 miscRegs[MISCREG_SCR_EL3]   = 0x0030;  // RES1 fields
-} else if (haveVirtualization) {
+} else if (release->has(ArmExtension::VIRTUALIZATION)) {
 // also  MISCREG_SCTLR_EL2 (by mapping)
 miscRegs[MISCREG_HSCTLR] = 0x30c50830;
 } else {
@@ -368,7 +354,7 @@

 miscRegs[MISCREG_ID_ISAR5] = insertBits(
 miscRegs[MISCREG_ID_ISAR5], 19, 4,
-haveCrypto ? 0x1112 : 0x0);
+release->has(ArmExtension::CRYPTO) ? 0x1112 : 0x0);
 }

 void
@@ -395,9 +381,9 @@

 // SVE
 miscRegs[MISCREG_ID_AA64ZFR0_EL1] = 0;  // SVEver 0
-if (haveSecurity) {

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Define an ArmRelease class to handle ISA extensions

2021-09-27 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/51010 )



Change subject: arch-arm: Define an ArmRelease class to handle ISA  
extensions

..

arch-arm: Define an ArmRelease class to handle ISA extensions

Signed-off-by: Giacomo Travaglini 
Change-Id: I3240853bd2123a6f24b2bb64c90ad457696f0d93
---
M src/arch/arm/ArmSystem.py
M src/arch/arm/mmu.cc
M configs/example/arm/baremetal.py
M src/dev/arm/gic_v3_distributor.cc
M src/arch/arm/isa.cc
M src/arch/arm/utility.cc
M src/dev/arm/generic_timer.cc
M src/arch/arm/table_walker.cc
M src/arch/arm/system.cc
M src/arch/arm/system.hh
M src/dev/arm/gic_v3_cpu_interface.cc
M src/dev/arm/RealView.py
12 files changed, 157 insertions(+), 184 deletions(-)



diff --git a/configs/example/arm/baremetal.py  
b/configs/example/arm/baremetal.py

index 9a56c11..9655bb1 100644
--- a/configs/example/arm/baremetal.py
+++ b/configs/example/arm/baremetal.py
@@ -143,8 +143,8 @@
 system.realview.gic.gicv4 = False

 system.highest_el_is_64 = True
-system.have_virtualization = True
-system.have_security = True
+system.release.add(ArmExtension('SECURITY'))
+system.release.add(ArmExtension('VIRTUALIZATION'))

 workload_class = workloads.workload_list.get(args.workload)
 system.workload = workload_class(
diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index 585df3b..6c42db0 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -43,20 +43,72 @@

 class SveVectorLength(UInt8): min = 1; max = 16

+class ArmExtension(ScopedEnum):
+vals = [
+# Armv8.1
+'FEAT_VHE',
+'FEAT_PAN',
+'FEAT_LSE',
+
+# Armv8.2
+'FEAT_SVE',
+
+# Armv8.4
+'FEAT_SEL2',
+
+# Others
+'SECURITY',
+'LPAE',
+'VIRTUALIZATION',
+'CRYPTO',
+'TME'
+]
+
+class ArmRelease(SimObject):
+type = 'ArmRelease'
+cxx_header = "arch/arm/system.hh"
+cxx_class = 'gem5::ArmRelease'
+
+extensions = VectorParam.ArmExtension([], "ISA extensions")
+
+def add(self, new_ext: ArmExtension) -> None:
+"""
+Add the provided extension (ArmExtension) to the system
+The method is discarding pre-existing values
+"""
+if (new_ext.value not in
+[ ext.value for ext in self.extensions ]):
+self.extensions.append(new_ext)
+
+def has(self, new_ext: ArmExtension) -> bool:
+"""
+Is the system implementing the provided extension (ArmExtension) ?
+"""
+if (new_ext.value not in
+[ ext.value for ext in self.extensions ]):
+return False
+else:
+return True
+
+class Armv8(ArmRelease):
+extensions = [
+'LPAE'
+]
+
+class ArmDefaultRelease(Armv8):
+extensions = Armv8.extensions + [
+'FEAT_SVE', 'FEAT_LSE', 'FEAT_PAN', 'FEAT_SEL2'
+]
+
 class ArmSystem(System):
 type = 'ArmSystem'
 cxx_header = "arch/arm/system.hh"
 cxx_class = 'gem5::ArmSystem'

+release = Param.ArmRelease(ArmDefaultRelease(), "Arm Release")
+
 multi_proc = Param.Bool(True, "Multiprocessor system?")
 gic_cpu_addr = Param.Addr(0, "Addres of the GIC CPU interface")
-have_security = Param.Bool(False,
-"True if Security Extensions are implemented")
-have_virtualization = Param.Bool(False,
-"True if Virtualization Extensions are implemented")
-have_crypto = Param.Bool(False,
-"True if Crypto Extensions is implemented")
-have_lpae = Param.Bool(True, "True if LPAE is implemented")
 reset_addr = Param.Addr(0x0,
 "Reset address (ARMv8)")
 auto_reset_addr = Param.Bool(True,
@@ -68,20 +120,8 @@
 "Supported physical address range in bits when using AArch64  
(ARMv8)")

 have_large_asid_64 = Param.Bool(False,
 "True if ASID is 16 bits in AArch64 (ARMv8)")
-have_sve = Param.Bool(True,
-"True if SVE is implemented (ARMv8)")
 sve_vl = Param.SveVectorLength(1,
 "SVE vector length in quadwords (128-bit)")
-have_lse = Param.Bool(True,
-"True if LSE is implemented (ARMv8.1)")
-have_vhe = Param.Bool(False,
-"True if FEAT_VHE (Virtualization Host Extensions) is implemented")
-have_pan = Param.Bool(True,
-"True if Priviledge Access Never is implemented (ARMv8.1)")
-have_secel2 = Param.Bool(True,
-"True if Secure EL2 is implemented (ARMv8)")
-have_tme = Param.Bool(False,
-"True if transactional memory extension (TME) is implemented")
 semihosting = Param.ArmSemihosting(NULL,
 "Enable support for the Arm semihosting by settings this  
parameter")


diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 3b485ed..ee9c556 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -103,19 +103,19 @@
 // Cache

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Prefer haveEL over haveSecurity and haveVirtualization

2021-09-27 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/51009 )



Change subject: arch-arm: Prefer haveEL over haveSecurity and  
haveVirtualization

..

arch-arm: Prefer haveEL over haveSecurity and haveVirtualization

The Arm architecture reference manual pseudocode checks for the presence
of an exception level (EL) over "security" and "virtualization"

Change-Id: Ia91a9d1848eddc40776627208386a13afdaafda3
Signed-off-by: Giacomo Travaglini 
---
M src/arch/arm/insts/static_inst.cc
M src/arch/arm/insts/static_inst.hh
M src/arch/arm/mmu.cc
M src/arch/arm/isa/insts/branch.isa
M src/arch/arm/utility.cc
M src/arch/arm/faults.cc
M src/arch/arm/regs/misc.cc
M src/arch/arm/insts/misc64.cc
M src/arch/arm/isa/insts/misc.isa
M src/arch/arm/isa/insts/misc64.isa
M src/arch/arm/isa/insts/data64.isa
11 files changed, 59 insertions(+), 46 deletions(-)



diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index 1bddd04..c82373a 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -314,8 +314,8 @@

 // Check for invalid modes
 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
-assert(ArmSystem::haveSecurity(tc) || cpsr.mode != MODE_MON);
-assert(ArmSystem::haveVirtualization(tc) || cpsr.mode != MODE_HYP);
+assert(ArmSystem::haveEL(tc, EL3) || cpsr.mode != MODE_MON);
+assert(ArmSystem::haveEL(tc, EL2) || cpsr.mode != MODE_HYP);

 switch (cpsr.mode)
 {
@@ -330,7 +330,7 @@
 if (sctlr.v) {
 base = HighVecs;
 } else {
-base = ArmSystem::haveSecurity(tc) ?
+base = ArmSystem::haveEL(tc, EL3) ?
 tc->readMiscReg(MISCREG_VBAR) : 0;
 }
 break;
@@ -345,11 +345,11 @@
 Addr vbar;
 switch (toEL) {
   case EL3:
-assert(ArmSystem::haveSecurity(tc));
+assert(ArmSystem::haveEL(tc, EL3));
 vbar = tc->readMiscReg(MISCREG_VBAR_EL3);
 break;
   case EL2:
-assert(ArmSystem::haveVirtualization(tc));
+assert(ArmSystem::haveEL(tc, EL2));
 vbar = tc->readMiscReg(MISCREG_VBAR_EL2);
 break;
   case EL1:
@@ -448,10 +448,10 @@

 // Determine target exception level (aarch64) or target execution
 // mode (aarch32).
-if (ArmSystem::haveSecurity(tc) && routeToMonitor(tc)) {
+if (ArmSystem::haveEL(tc, EL3) && routeToMonitor(tc)) {
 toMode = MODE_MON;
 toEL = EL3;
-} else if (ArmSystem::haveVirtualization(tc) && routeToHyp(tc)) {
+} else if (ArmSystem::haveEL(tc, EL2) && routeToHyp(tc)) {
 toMode = MODE_HYP;
 toEL = EL2;
 hypRouted = true;
@@ -510,7 +510,7 @@
 return;

 // ARMv7 (ARM ARM issue C B1.9)
-bool have_security = ArmSystem::haveSecurity(tc);
+bool have_security = ArmSystem::haveEL(tc, EL3);

 FaultBase::invoke(tc);
 if (!FullSystem)
@@ -613,7 +613,7 @@
 setSyndrome(tc, MISCREG_HSR);
 break;
   case MODE_HYP:
-assert(ArmSystem::haveVirtualization(tc));
+assert(ArmSystem::haveEL(tc, EL2));
 tc->setMiscReg(MISCREG_SPSR_HYP, saved_cpsr);
 setSyndrome(tc, MISCREG_HSR);
 break;
@@ -648,12 +648,12 @@
 spsr_idx = MISCREG_SPSR_EL1;
 break;
   case EL2:
-assert(ArmSystem::haveVirtualization(tc));
+assert(ArmSystem::haveEL(tc, EL2));
 elr_idx = MISCREG_ELR_EL2;
 spsr_idx = MISCREG_SPSR_EL2;
 break;
   case EL3:
-assert(ArmSystem::haveSecurity(tc));
+assert(ArmSystem::haveEL(tc, EL3));
 elr_idx = MISCREG_ELR_EL3;
 spsr_idx = MISCREG_SPSR_EL3;
 break;
@@ -766,8 +766,8 @@

 // Check for invalid modes
 [[maybe_unused]] CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
-assert(ArmSystem::haveSecurity(tc) || cpsr.mode != MODE_MON);
-assert(ArmSystem::haveVirtualization(tc) || cpsr.mode != MODE_HYP);
+assert(ArmSystem::haveEL(tc, EL3) || cpsr.mode != MODE_MON);
+assert(ArmSystem::haveEL(tc, EL2) || cpsr.mode != MODE_HYP);

 // RVBAR is aliased (implemented as) MVBAR in gem5, since the two
 // are mutually exclusive; there is no need to check here for
@@ -790,8 +790,8 @@
 
getMPIDR(dynamic_cast(tc->getSystemPtr()), tc));


 // Unless we have SMC code to get us there, boot in HYP!
-if (ArmSystem::haveVirtualization(tc) &&
-!ArmSystem::haveSecurity(tc)) {
+if (ArmSystem::haveEL(tc, EL2) &&
+!ArmSystem::haveEL(tc, EL3)) {
 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
 cpsr.mode = MODE_HYP;
 tc->setMiscReg(MISCREG_CPSR, cpsr);
@@ -1215,7 +1215,7 @@
 bool
 AbortFault::abortDisable(ThreadContext *tc)
 {
-if (ArmSystem::haveSecurity(tc)) {
+if (ArmSystem::haveEL(tc, EL3)) {
 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Turn on EL2/EL3 support by default in ArmSystem

2021-09-27 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/51011 )



Change subject: arch-arm: Turn on EL2/EL3 support by default in ArmSystem
..

arch-arm: Turn on EL2/EL3 support by default in ArmSystem

In order to turn them off a user needs to explicitly do so
by providing a different ArmRelease objec

Change-Id: I227cee80c5517cdd50cf07c62d9a131ce261310f
Signed-off-by: Giacomo Travaglini 
---
M src/arch/arm/ArmSystem.py
M configs/example/arm/baremetal.py
2 files changed, 14 insertions(+), 3 deletions(-)



diff --git a/configs/example/arm/baremetal.py  
b/configs/example/arm/baremetal.py

index 9655bb1..952e9bb 100644
--- a/configs/example/arm/baremetal.py
+++ b/configs/example/arm/baremetal.py
@@ -143,8 +143,6 @@
 system.realview.gic.gicv4 = False

 system.highest_el_is_64 = True
-system.release.add(ArmExtension('SECURITY'))
-system.release.add(ArmExtension('VIRTUALIZATION'))

 workload_class = workloads.workload_list.get(args.workload)
 system.workload = workload_class(
diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index 6c42db0..f4834d2 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -92,7 +92,7 @@

 class Armv8(ArmRelease):
 extensions = [
-'LPAE'
+'LPAE', 'VIRTUALIZATION', 'SECURITY'
 ]

 class ArmDefaultRelease(Armv8):

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/51011
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I227cee80c5517cdd50cf07c62d9a131ce261310f
Gerrit-Change-Number: 51011
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Do not use FEAT_SEL2 in SE mode

2021-09-27 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/51013 )



Change subject: arch-arm: Do not use FEAT_SEL2 in SE mode
..

arch-arm: Do not use FEAT_SEL2 in SE mode

SecureEL2 doesn't make sense for a userspace only simulation

Change-Id: Ieda56cc6684f7c011b31ca754e971fb9a9fb6899
Signed-off-by: Giacomo Travaglini 
---
M src/arch/arm/ArmISA.py
1 file changed, 13 insertions(+), 1 deletion(-)



diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index 0a2bbc6..298d8c3 100644
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -47,7 +47,7 @@

 class ArmDefaultSERelease(ArmRelease):
 extensions = [
-'CRYPTO', 'FEAT_SVE', 'FEAT_LSE', 'TME', 'FEAT_SEL2'
+'CRYPTO', 'FEAT_SVE', 'FEAT_LSE', 'TME'
 ]

 class ArmISA(BaseISA):

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/51013
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ieda56cc6684f7c011b31ca754e971fb9a9fb6899
Gerrit-Change-Number: 51013
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: FEAT_SEL2 is not part of ID_AA64ISAR0_EL1

2021-09-27 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/51015 )



Change subject: arch-arm: FEAT_SEL2 is not part of ID_AA64ISAR0_EL1
..

arch-arm: FEAT_SEL2 is not part of ID_AA64ISAR0_EL1

Change-Id: I81cb3e8f400eaf8abc1dea61f592239e52501ab1
Signed-off-by: Giacomo Travaglini 
---
M src/arch/arm/isa.cc
1 file changed, 11 insertions(+), 3 deletions(-)



diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index a671274..84d9e51 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -413,9 +413,7 @@
 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
 miscRegs[MISCREG_ID_AA64PFR0_EL1], 39, 36,
 release->has(ArmExtension::FEAT_SEL2) ? 0x1 : 0x0);
-miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
-miscRegs[MISCREG_ID_AA64ISAR0_EL1], 39, 36,
-release->has(ArmExtension::FEAT_SEL2) ? 0x1 : 0x0);
+
 // Large ASID support
 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4,

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/51015
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I81cb3e8f400eaf8abc1dea61f592239e52501ab1
Gerrit-Change-Number: 51015
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Add missing Armv8.1 extensions to the enum

2021-09-27 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/51014 )



Change subject: arch-arm: Add missing Armv8.1 extensions to the enum
..

arch-arm: Add missing Armv8.1 extensions to the enum

Change-Id: I90c7eb2b22d317f5a60b020c731948681e9f91a1
Signed-off-by: Giacomo Travaglini 
---
M src/arch/arm/ArmSystem.py
M src/arch/arm/isa.cc
M src/arch/arm/ArmISA.py
3 files changed, 40 insertions(+), 2 deletions(-)



diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index 298d8c3..e98041c 100644
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -47,7 +47,7 @@

 class ArmDefaultSERelease(ArmRelease):
 extensions = [
-'CRYPTO', 'FEAT_SVE', 'FEAT_LSE', 'TME'
+'CRYPTO', 'FEAT_SVE', 'FEAT_LSE', 'FEAT_RDM', 'TME'
 ]

 class ArmISA(BaseISA):
diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index f4834d2..c2411a3 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -49,6 +49,9 @@
 'FEAT_VHE',
 'FEAT_PAN',
 'FEAT_LSE',
+'FEAT_HPDS',
+'FEAT_VMID16',
+'FEAT_RDM',

 # Armv8.2
 'FEAT_SVE',
@@ -97,7 +100,8 @@

 class ArmDefaultRelease(Armv8):
 extensions = Armv8.extensions + [
-'FEAT_SVE', 'FEAT_LSE', 'FEAT_PAN', 'FEAT_SEL2'
+'FEAT_SVE', 'FEAT_LSE', 'FEAT_PAN',
+'FEAT_HPDS', 'FEAT_VMID16', 'FEAT_RDM', 'FEAT_SEL2'
 ]

 class ArmSystem(System):
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 54e574d..a671274 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -352,9 +352,15 @@
 miscRegs[MISCREG_ID_MMFR3] = p.id_mmfr3;
 miscRegs[MISCREG_ID_MMFR4] = p.id_mmfr4;

+/** MISCREG_ID_ISAR5 */
+// Crypto
 miscRegs[MISCREG_ID_ISAR5] = insertBits(
 miscRegs[MISCREG_ID_ISAR5], 19, 4,
 release->has(ArmExtension::CRYPTO) ? 0x1112 : 0x0);
+// RDM
+miscRegs[MISCREG_ID_ISAR5] = insertBits(
+miscRegs[MISCREG_ID_ISAR5], 27, 24,
+release->has(ArmExtension::FEAT_RDM) ? 0x1 : 0x0);
 }

 void
@@ -418,6 +424,8 @@
 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0,
 encodePhysAddrRange64(physAddrRange));
+
+/** MISCREG_ID_AA64ISAR0_EL1 */
 // Crypto
 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
 miscRegs[MISCREG_ID_AA64ISAR0_EL1], 19, 4,
@@ -426,14 +434,30 @@
 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
 miscRegs[MISCREG_ID_AA64ISAR0_EL1], 23, 20,
 release->has(ArmExtension::FEAT_LSE) ? 0x2 : 0x0);
+// RDM
+miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
+miscRegs[MISCREG_ID_AA64ISAR0_EL1], 31, 28,
+release->has(ArmExtension::FEAT_RDM) ? 0x1 : 0x0);
+
+/** MISCREG_ID_AA64MMFR1_EL1 */
+// VMID16
+miscRegs[MISCREG_ID_AA64MMFR1_EL1] = insertBits(
+miscRegs[MISCREG_ID_AA64MMFR1_EL1], 7, 4,
+release->has(ArmExtension::FEAT_VMID16) ? 0x2 : 0x0);
 // VHE
 miscRegs[MISCREG_ID_AA64MMFR1_EL1] = insertBits(
 miscRegs[MISCREG_ID_AA64MMFR1_EL1], 11, 8,
 release->has(ArmExtension::FEAT_VHE) ? 0x1 : 0x0);
+// HPDS
+miscRegs[MISCREG_ID_AA64MMFR1_EL1] = insertBits(
+miscRegs[MISCREG_ID_AA64MMFR1_EL1], 15, 12,
+release->has(ArmExtension::FEAT_HPDS) ? 0x1 : 0x0);
 // PAN
 miscRegs[MISCREG_ID_AA64MMFR1_EL1] = insertBits(
 miscRegs[MISCREG_ID_AA64MMFR1_EL1], 23, 20,
 release->has(ArmExtension::FEAT_PAN) ? 0x1 : 0x0);
+
+
 // TME
 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
 miscRegs[MISCREG_ID_AA64ISAR0_EL1], 27, 24,

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/51014
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I90c7eb2b22d317f5a60b020c731948681e9f91a1
Gerrit-Change-Number: 51014
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: configs: Remove lpae and virtualisation options

2021-09-27 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/51007 )



Change subject: configs: Remove lpae and virtualisation options
..

configs: Remove lpae and virtualisation options

lpae is already defaulting to True in the ArmSystem, so the check is
useless (args.lpae cannot clear system.lpae)

If you want to run an hypervisor, you shouldn't be using fs.py in the
first place

Change-Id: I4d631561d62399b946106a90c14454115040c206
Signed-off-by: Giacomo Travaglini 
---
M configs/common/Options.py
M configs/example/fs.py
2 files changed, 16 insertions(+), 9 deletions(-)



diff --git a/configs/common/Options.py b/configs/common/Options.py
index 7d72d4a..4e696ef 100644
--- a/configs/common/Options.py
+++ b/configs/common/Options.py
@@ -260,9 +260,6 @@
   Elastic Trace probe in a capture simulation and
   Trace CPU in a replay simulation""", default="")

-parser.add_argument("-l", "--lpae", action="store_true")
-parser.add_argument("-V", "--virtualisation", action="store_true")
-
 # dist-gem5 options
 parser.add_argument("--dist", action="store_true",
 help="Parallel distributed gem5 simulation.")
diff --git a/configs/example/fs.py b/configs/example/fs.py
index dab28b1..cdb2a49 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -132,12 +132,6 @@
 if args.script is not None:
 test_sys.readfile = args.script

-if args.lpae:
-test_sys.have_lpae = True
-
-if args.virtualisation:
-test_sys.have_virtualization = True
-
 test_sys.init_param = args.init_param

 # For now, assign all the CPUs to the same clock domain

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/51007
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I4d631561d62399b946106a90c14454115040c206
Gerrit-Change-Number: 51007
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Add an Armv8.1 ArmRelease object

2021-09-27 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/51016 )



Change subject: arch-arm: Add an Armv8.1 ArmRelease object
..

arch-arm: Add an Armv8.1 ArmRelease object

Change-Id: I5638deb77a165bec1ee47d8f1b2bac31647f173a
Signed-off-by: Giacomo Travaglini 
---
M src/arch/arm/ArmSystem.py
1 file changed, 16 insertions(+), 0 deletions(-)



diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index c2411a3..fbb2cff 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -104,6 +104,12 @@
 'FEAT_HPDS', 'FEAT_VMID16', 'FEAT_RDM', 'FEAT_SEL2'
 ]

+class Armv81(Armv8):
+extensions = Armv8.extensions + [
+'FEAT_LSE', 'FEAT_VHE', 'FEAT_PAN',
+'FEAT_HPDS', 'FEAT_VMID16', 'FEAT_RDM'
+]
+
 class ArmSystem(System):
 type = 'ArmSystem'
 cxx_header = "arch/arm/system.hh"

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/51016
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I5638deb77a165bec1ee47d8f1b2bac31647f173a
Gerrit-Change-Number: 51016
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: configs: Remove security option

2021-09-27 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/51008 )



Change subject: configs: Remove security option
..

configs: Remove security option

If willing to run a secure software stack, we recommend to use
the baremetal.py platform
See [1] on how to run gem5 with TF-A

[1]: https://community.arm.com/developer/research/b/articles/\
posts/running-trusted-firmware-a-on-gem5

Change-Id: I69f6d672b24cb588c522c6a468e3b19332c9367b
Signed-off-by: Giacomo Travaglini 
---
M configs/common/FSConfig.py
M configs/common/Options.py
M configs/example/fs.py
3 files changed, 18 insertions(+), 7 deletions(-)



diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index e85d225..efb0af6 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -173,7 +173,7 @@

 def makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None,
   dtb_filename=None, bare_metal=False, cmdline=None,
-  external_memory="", ruby=False, security=False,
+  external_memory="", ruby=False,
   vio_9p=None, bootloader=None):
 assert machine_type

@@ -236,8 +236,6 @@
   " the amount of DRAM you've selected. Please try" \
   " another platform")

-self.have_security = security
-
 if bare_metal:
 # EOT character on UART will end the simulation
 self.realview.uart[0].end_on_eot = True
diff --git a/configs/common/Options.py b/configs/common/Options.py
index 4e696ef..a63cc7b 100644
--- a/configs/common/Options.py
+++ b/configs/common/Options.py
@@ -491,9 +491,6 @@
 help="Specifies device tree blob file to use with device-tree-"
 "enabled kernels")
 parser.add_argument(
-"--enable-security-extensions", action="store_true",
-help="Turn on the ARM Security Extensions")
-parser.add_argument(
 "--enable-context-switch-stats-dump", action="store_true",
 help="Enable stats dump at context "
 "switches and dump tasks file (required for Streamline)")
diff --git a/configs/example/fs.py b/configs/example/fs.py
index cdb2a49..a39d2b3 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -97,7 +97,6 @@
 cmdline=cmdline,
 external_memory=args.external_memory_system,
 ruby=args.ruby,
-security=args.enable_security_extensions,
 vio_9p=args.vio_9p,
 bootloader=args.bootloader,
 )

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/51008
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I69f6d672b24cb588c522c6a468e3b19332c9367b
Gerrit-Change-Number: 51008
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Re: failing ARM dual CPU tests?

[gem5-dev] Change in gem5/gem5[develop]: arch-vega: Fix VEGA_X86 build issues

[gem5-dev] Change in gem5/gem5[develop]: arch-vega: Issue flat insts using on executedAs()

[gem5-dev] Change in gem5/gem5[develop]: arch-vega: Add missing functions referenced by insts

[gem5-dev] Change in gem5/gem5[develop]: arch-vega: Update instruction stats

[gem5-dev] Change in gem5/gem5[develop]: tests: update nightly tests to document square

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Add missing Armv8.2 extensions to the enum

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Add an Armv8.3 ArmRelease object

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Add an Armv8.4 ArmRelease object

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Add missing Armv8.3 extensions to the enum

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Add an Armv8.2 ArmRelease object

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Use ArmRelease in the ISA class

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Define an ArmRelease class to handle ISA extensions

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Prefer haveEL over haveSecurity and haveVirtualization

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Turn on EL2/EL3 support by default in ArmSystem

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Do not use FEAT_SEL2 in SE mode

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: FEAT_SEL2 is not part of ID_AA64ISAR0_EL1

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Add missing Armv8.1 extensions to the enum

[gem5-dev] Change in gem5/gem5[develop]: configs: Remove lpae and virtualisation options

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Add an Armv8.1 ArmRelease object

[gem5-dev] Change in gem5/gem5[develop]: configs: Remove security option

21 matches

Site Navigation

Mail list logo

Footer information