[gem5-dev] Change in public/gem5[master]: dev: Add a dummy serial device

[Andreas Sandberg (Gerrit)]

Hello Gabe Black, Jason Lowe-Power, Curtis Dunham,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/4290

to look at the new patch set (#2).

Change subject: dev: Add a dummy serial device
..

dev: Add a dummy serial device

Add a dummy serial device that discards any output and doesn't provide
any input. This device can be used to terminate UARTs that don't have
a default device (e.g., a terminal) attached.

Change-Id: I4a6b0b5037ce360f59bfb5c566e1698d113a1d26
Signed-off-by: Andreas Sandberg 
Reviewed-by: Curtis Dunham 
---
M src/dev/Serial.py
M src/dev/serial.cc
M src/dev/serial.hh
3 files changed, 41 insertions(+), 0 deletions(-)


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Gerrit-Change-Id: I4a6b0b5037ce360f59bfb5c566e1698d113a1d26
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[gem5-dev] Change in public/gem5[master]: dev: Move generic serial devices to src/dev/serial

[Andreas Sandberg (Gerrit)]

Hello Gabe Black, Jason Lowe-Power, Curtis Dunham,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/4291

to look at the new patch set (#2).

Change subject: dev: Move generic serial devices to src/dev/serial
..

dev: Move generic serial devices to src/dev/serial

Change-Id: I104227fc460f8b561e7375b329a541c1fce881b2
Signed-off-by: Andreas Sandberg 
Reviewed-by: Curtis Dunham 
---
M src/dev/SConscript
M src/dev/alpha/backdoor.cc
M src/dev/alpha/tsunami.cc
M src/dev/arm/gic_pl390.cc
M src/dev/arm/pl011.hh
M src/dev/arm/realview.cc
M src/dev/arm/vgic.cc
M src/dev/mips/malta.cc
C src/dev/serial/SConscript
R src/dev/serial/Serial.py
R src/dev/serial/Terminal.py
R src/dev/serial/Uart.py
R src/dev/serial/serial.cc
R src/dev/serial/serial.hh
R src/dev/serial/terminal.cc
R src/dev/serial/terminal.hh
R src/dev/serial/uart.cc
R src/dev/serial/uart.hh
R src/dev/serial/uart8250.cc
R src/dev/serial/uart8250.hh
M src/dev/sparc/t1000.cc
M src/dev/virtio/block.hh
M src/dev/virtio/console.hh
M src/dev/x86/pc.cc
24 files changed, 37 insertions(+), 48 deletions(-)


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[gem5-dev] Change in public/gem5[master]: dev: Refactor UART->Terminal interface

[Andreas Sandberg (Gerrit)]

Hello Gabe Black, Jason Lowe-Power, Curtis Dunham,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/4289

to look at the new patch set (#2).

Change subject: dev: Refactor UART->Terminal interface
..

dev: Refactor UART->Terminal interface

The UART models currently assume that they are always wired to a
terminal. While true at the moment, this isn't necessarily a valid
assumption. This change introduces the SerialDevice class that defines
the interface for serial devices. Currently, Terminal is the only
class that implements this interface.

Change-Id: I74fefafbbaf5ac1ec0d4ec0b5a0f4b246fdad305
Signed-off-by: Andreas Sandberg 
Reviewed-by: Curtis Dunham 
---
M src/dev/SConscript
A src/dev/Serial.py
M src/dev/Terminal.py
M src/dev/Uart.py
M src/dev/alpha/backdoor.cc
M src/dev/arm/pl011.cc
A src/dev/serial.cc
A src/dev/serial.hh
M src/dev/terminal.cc
M src/dev/terminal.hh
M src/dev/uart.cc
M src/dev/uart.hh
M src/dev/uart8250.cc
M src/dev/virtio/VirtIOConsole.py
M src/dev/virtio/console.cc
M src/dev/virtio/console.hh
16 files changed, 309 insertions(+), 77 deletions(-)


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Gerrit-Change-Number: 4289
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[gem5-dev] Change in public/gem5[master]: arch-arm: Fix inverted 32/64-bit check in GDB

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/4720 )


Change subject: arch-arm: Fix inverted 32/64-bit check in GDB
..

arch-arm: Fix inverted 32/64-bit check in GDB

Change-Id: Ided438af19c9b8504d4624119c4d9fb5157c7cf0
Reviewed-on: https://gem5-review.googlesource.com/4720
Reviewed-by: Paul Rosenfeld 
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
---
M src/arch/arm/remote_gdb.cc
1 file changed, 2 insertions(+), 2 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  Paul Rosenfeld: Looks good to me, approved



diff --git a/src/arch/arm/remote_gdb.cc b/src/arch/arm/remote_gdb.cc
index d934d53..6dc68b1 100644
--- a/src/arch/arm/remote_gdb.cc
+++ b/src/arch/arm/remote_gdb.cc
@@ -305,7 +305,7 @@
 RemoteGDB::gdbRegs()
 {
 if (inAArch64(context))
-return 
-else
 return 
+else
+return 
 }

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Gerrit-MessageType: merged
Gerrit-Change-Id: Ided438af19c9b8504d4624119c4d9fb5157c7cf0
Gerrit-Change-Number: 4720
Gerrit-PatchSet: 2
Gerrit-Owner: Boris Shingarov 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Paul Rosenfeld 
Gerrit-CC: Gabe Black 
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[gem5-dev] Change in public/gem5[master]: util: Remove support for hg patches in patch creation script

[Andreas Sandberg (Gerrit)]

Hello Nikos Nikoleris, Curtis Dunham,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/5162

to review the following change.


Change subject: util: Remove support for hg patches in patch creation script
..

util: Remove support for hg patches in patch creation script

Simplify the patch creation helper script by removing support for
automatic conversion to Mercurial's patch format. We no longer use
Mercurial as a primary repository, so this support is not likely to be
needed again.

Change-Id: I83f6efb9ccaee9c548b33257a4d6128153750c76
Signed-off-by: Andreas Sandberg 
Reviewed-by: Nikos Nikoleris 
Reviewed-by: Curtis Dunham 
---
M util/maint/create_patches.sh
D util/maint/git-patch-to-hg-patch
2 files changed, 2 insertions(+), 167 deletions(-)



diff --git a/util/maint/create_patches.sh b/util/maint/create_patches.sh
index 7c1655f..339136a 100755
--- a/util/maint/create_patches.sh
+++ b/util/maint/create_patches.sh
@@ -44,11 +44,9 @@
 SCRIPT_NAME=`basename "$0"`
 SCRIPT_DIR=$(cd "$REL_SCRIPT_DIR" && echo "$(pwd -P)")
 MSG_FILTER="$SCRIPT_DIR"/upstream_msg_filter.sed
-CONV_HG="$SCRIPT_DIR"/git-patch-to-hg-patch

 PATCH_DIR="./patches/"
 UPSTREAM="upstream/master"
-PATCH_FORMAT=

 usage()
 {
@@ -59,7 +57,6 @@
 Options:
   -u BRANCH  Upstream branch
   -d DIR Patch directory
-  -f FMT Patch format (hg or git)
   -h Show this help string.

 This script creates a series of patches suitable from upstream
@@ -70,7 +67,7 @@
   1. Rebase the patches in the current branch onto the upstream
  branch.
   2. Filter commit messages.
-  3. Generate a set of patches in git format or Mercurial format.
+  3. Generate a set of patches in git format.
 EOF
 }

@@ -79,7 +76,7 @@
 git rev-parse --verify -q "$1" > /dev/null
 }

-while getopts ":u:d:f:h" OPT; do
+while getopts ":u:d:h" OPT; do
 case $OPT in
 d)
 PATCH_DIR="$OPTARG"
@@ -87,9 +84,6 @@
 u)
 UPSTREAM="$OPTARG"
 ;;
-f)
-PATCH_FORMAT="$OPTARG"
-;;
 h)
 usage
 exit 0
@@ -117,21 +111,6 @@

 BRANCH="${1:-HEAD}"

-case "$PATCH_FORMAT" in
-git|hg)
-;;
-
-"")
-echo "Error: No patch format specified" >&2
-exit 1
-;;
-
-*)
-echo "Error: Illegal patch format specified: '$PATCH_FORMAT'" >&2
-exit 1
-esac
-
-
 if ! branch_exists "$BRANCH"; then
 echo "Error: Patch branch '$BRANCH' doesn't exist" 1>&2
 exit 2
@@ -168,10 +147,3 @@

 echo "Creating patches..."
 git format-patch -p -o "$PATCH_DIR" "$UPSTREAM"
-
-if [ "$PATCH_FORMAT" == "hg" ]; then
-echo "Converting patches..."
-for P in "$PATCH_DIR"/*.patch; do
-"$CONV_HG" $P
-done
-fi
diff --git a/util/maint/git-patch-to-hg-patch  
b/util/maint/git-patch-to-hg-patch

deleted file mode 100755
index 1b9e05d..000
--- a/util/maint/git-patch-to-hg-patch
+++ /dev/null
@@ -1,137 +0,0 @@
-#!/usr/bin/env python2
-#
-# This file originated from the moz-git-tools repo on GitHub
-# (https://github.com/mozilla/moz-git-tools), which contains the
-# following LICENSE notice:
-#
-# 
-# Except for git-new-workdir, which is covered under GPLv2, the code
-# in this repository is placed into the public domain via CC0.
-#
-# http://creativecommons.org/publicdomain/zero/1.0/legalcode
-# 
-
-r"""Git format-patch to hg importable patch.
-
-(Who knew this was so complicated?)
-
->>> process(StringIO('From 3ce1ccc06 Mon Sep 17 00:00:00 2001\nFrom:  
fromuser\nSubject: subject\n\nRest of patch.\nMore patch.\n'))
-'# HG changeset patch\n# User fromuser\n\nsubject\n\nRest of patch.\nMore  
patch.\n'

-
->>> process(StringIO('From: fromuser\nSubject: A very long subject line.   
Lorem ipsum dolor sit amet, consectetur adipiscing elit. Morbi faucibus,  
arcu sit amet\n\nRest of patch.\nMore patch.\n'))
-'# HG changeset patch\n# User fromuser\n\nA very long subject line.  Lorem  
ipsum dolor sit amet, consectetur adipiscing elit. Morbi faucibus, arcu sit  
amet\n\nRest of patch.\nMore patch.\n'

-
->>> process(StringIO('From: f\nSubject:  
=?UTF-8?q?Bug=20655877=20-=20Dont=20treat=20SVG=20text=20frames=20?=  
=?UTF-8?q?as=20being=20positioned.=20r=3D=3F?=\n\nPatch.'))
-'# HG changeset patch\n# User f\n\nBug 655877 - Dont treat SVG text frames  
as being positioned. r=?\n\nPatch.'

-"""
-
-# Original author: bholley
-
-import sys
-import re
-import fileinput
-import email, email.parser, email.header, email.utils
-import math
-from cStringIO import StringIO
-from itertools import takewhile
-
-def decode_header(hdr_string):
-  r"""Clean up weird encoding crap.
-
-  >>> clean_header('[PATCH] =?UTF-8?q?Bug=20655877=20r=3D=3F?=')
-  '[PATCH] Bug 655877 r=?'
-  """
-  rv = []
-  hdr = email.header.Header(hdr_string, maxlinelen=float('inf'))

[gem5-dev] Change in public/gem5[master]: util: Optionally search entire history when listing changes

[Andreas Sandberg (Gerrit)]

Hello Nikos Nikoleris, Curtis Dunham,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/5161

to review the following change.


Change subject: util: Optionally search entire history when listing changes
..

util: Optionally search entire history when listing changes

The helper script to list changes currently only looks at the changes
between a branch point and two heads. This helps performance, but
sometimes misclassifies changes that exist both in the upstream
branch before the branch point and in a feature branch. Such changes
should normally not exist, but can be the product of an incorrect
rebase.

This change adds an option to the helper script to search the entire
upstream repo history when determining the set of upstream
changes. When this option is provided, the script lists the changes
that exist upstream before the branch point and in the feature branch
as "Incorrectly rebased changes".

Change-Id: I4cb72cea2152c49d0317dc43613be94a0a2de1e5
Signed-off-by: Andreas Sandberg 
Reviewed-by: Nikos Nikoleris 
Reviewed-by: Curtis Dunham 
---
M util/maint/list_changes.py
1 file changed, 26 insertions(+), 5 deletions(-)



diff --git a/util/maint/list_changes.py b/util/maint/list_changes.py
index 5cbcf59..78e4442 100755
--- a/util/maint/list_changes.py
+++ b/util/maint/list_changes.py
@@ -105,16 +105,21 @@
 def __str__(self):
 return "%s: %s" % (self.rev[0:8], self.log[0])

-def list_revs(upstream, branch):
-"""Get a generator that lists git revisions that exist in 'branch' but
-not in 'upstream'.
+def list_revs(branch, baseline=None):
+"""Get a generator that lists git revisions that exist in 'branch'. If
+the optional parameter 'baseline' is specified, the generator
+excludes commits that exist on that branch.

 Returns: Generator of Commit objects

 """

-changes = subprocess.check_output(
-[ "git", "rev-list", "%s..%s" % (upstream, branch) ])
+if baseline is not None:
+query = "%s..%s" % (branch, baseline)
+else:
+query = str(branch)
+
+changes = subprocess.check_output([ "git", "rev-list", query ])

 if changes == "":
 return
@@ -165,6 +170,9 @@
 help="Print changes without Change-Id tags")
 parser.add_argument("--show-common", action="store_true",
 help="Print common changes")
+parser.add_argument("--deep-search", action="store_true",
+help="Use a deep search to find incorrectly " \
+"rebased changes")

 args = parser.parse_args()

@@ -200,6 +208,19 @@
 for rev in feature_unknown:
 print rev

+if args.deep_search:
+print "Incorrectly rebased changes:"
+all_upstream_revs = list_revs(args.upstream)
+all_upstream_cids = dict([
+(c.change_id, c) for c in all_upstream_revs \
+if c.change_id is not None ])
+incorrect_outgoing = filter(
+lambda r: r.change_id in all_upstream_cids,
+outgoing)
+for rev in incorrect_outgoing:
+print rev
+
+


 if __name__ == "__main__":

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[gem5-dev] Change in public/gem5[master]: util: Filter out the For-Upstream commit message tag

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/5141 )


Change subject: util: Filter out the For-Upstream commit message tag
..

util: Filter out the For-Upstream commit message tag

Some internal review flows, e.g. the flow used by ARM Research, uses
the For-Upstream tag to indicate that a change has been approved for
upstream. This tag isn't meaningful outside of the internal review
system. Remove it automatically when running the maintainer script to
prepare patches to be posted upstream.

Change-Id: Ie3745d0e8ad7a1bfddc5ec68ff3e6ff3f91ca8d8
Signed-off-by: Andreas Sandberg 
Reviewed-by: Curtis Dunham 
Reviewed-on: https://gem5-review.googlesource.com/5141
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M util/maint/upstream_msg_filter.sed
1 file changed, 1 insertion(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved



diff --git a/util/maint/upstream_msg_filter.sed  
b/util/maint/upstream_msg_filter.sed

index 5fe01cf..5e5a0e7 100755
--- a/util/maint/upstream_msg_filter.sed
+++ b/util/maint/upstream_msg_filter.sed
@@ -44,3 +44,4 @@
 /Tested-by:/d;
 /Copyright-Check:/d;
 /Style-Check:/d;
+/For-Upstream:/d;

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Gerrit-Change-Id: Ie3745d0e8ad7a1bfddc5ec68ff3e6ff3f91ca8d8
Gerrit-Change-Number: 5141
Gerrit-PatchSet: 2
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[gem5-dev] Change in public/gem5[master]: util: Filter out the For-Upstream commit message tag

[Andreas Sandberg (Gerrit)]

Hello Curtis Dunham,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/5141

to review the following change.


Change subject: util: Filter out the For-Upstream commit message tag
..

util: Filter out the For-Upstream commit message tag

Some internal review flows, e.g. the flow used by ARM Research, uses
the For-Upstream tag to indicate that a change has been approved for
upstream. This tag isn't meaningful outside of the internal review
system. Remove it automatically when running the maintainer script to
prepare patches to be posted upstream.

Change-Id: Ie3745d0e8ad7a1bfddc5ec68ff3e6ff3f91ca8d8
Signed-off-by: Andreas Sandberg 
Reviewed-by: Curtis Dunham 
---
M util/maint/upstream_msg_filter.sed
1 file changed, 1 insertion(+), 0 deletions(-)



diff --git a/util/maint/upstream_msg_filter.sed  
b/util/maint/upstream_msg_filter.sed

index 5fe01cf..5e5a0e7 100755
--- a/util/maint/upstream_msg_filter.sed
+++ b/util/maint/upstream_msg_filter.sed
@@ -44,3 +44,4 @@
 /Tested-by:/d;
 /Copyright-Check:/d;
 /Style-Check:/d;
+/For-Upstream:/d;

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[gem5-dev] Change in public/gem5[master]: cpu, probe: Fix elastic trace register dependency

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/5121



Change subject: cpu, probe: Fix elastic trace register dependency
..

cpu, probe: Fix elastic trace register dependency

Change-Id: I017852eac183fac3f914fdb96d7e72a56ea9d682
Reviewed-by: Nathanael Premillieu 
Reviewed-by: Andreas Sandberg 
---
M src/cpu/o3/probe/elastic_trace.cc
1 file changed, 24 insertions(+), 16 deletions(-)



diff --git a/src/cpu/o3/probe/elastic_trace.cc  
b/src/cpu/o3/probe/elastic_trace.cc

index 08ef665..508140e 100644
--- a/src/cpu/o3/probe/elastic_trace.cc
+++ b/src/cpu/o3/probe/elastic_trace.cc
@@ -238,23 +238,31 @@
 // dependency on the last writer.
 int8_t max_regs = dyn_inst->numSrcRegs();
 for (int src_idx = 0; src_idx < max_regs; src_idx++) {
-// Get the physical register index of the i'th source register.
-PhysRegIdPtr src_reg = dyn_inst->renamedSrcRegIdx(src_idx);
-DPRINTFR(ElasticTrace, "[sn:%lli] Check map for src reg"
- " %i (%s)\n", seq_num,
- src_reg->index(), src_reg->className());
-auto itr_last_writer = physRegDepMap.find(src_reg->flatIndex());
-if (itr_last_writer != physRegDepMap.end()) {
-InstSeqNum last_writer = itr_last_writer->second;
-// Additionally the dependency distance is kept less than the  
window
-// size parameter to limit the memory allocation to nodes in  
the
-// graph. If the window were tending to infinite we would have  
to

-// load a large number of node objects during replay.
-if (seq_num - last_writer < depWindowSize) {
-// Record a physical register dependency.
-exec_info_ptr->physRegDepSet.insert(last_writer);
+
+const RegId& src_reg = dyn_inst->srcRegIdx(src_idx);
+if (!src_reg.isMiscReg() &&
+!src_reg.isZeroReg()) {
+// Get the physical register index of the i'th source register.
+PhysRegIdPtr phys_src_reg =  
dyn_inst->renamedSrcRegIdx(src_idx);

+DPRINTFR(ElasticTrace, "[sn:%lli] Check map for src reg"
+ " %i (%s)\n", seq_num,
+ phys_src_reg->flatIndex(), phys_src_reg->className());
+auto itr_writer =  
physRegDepMap.find(phys_src_reg->flatIndex());

+if (itr_writer != physRegDepMap.end()) {
+InstSeqNum last_writer = itr_writer->second;
+// Additionally the dependency distance is kept less than  
the

+// window size parameter to limit the memory allocation to
+// nodes in the graph. If the window were tending to  
infinite
+// we would have to load a large number of node objects  
during

+// replay.
+if (seq_num - last_writer < depWindowSize) {
+// Record a physical register dependency.
+exec_info_ptr->physRegDepSet.insert(last_writer);
+}
 }
+
 }
+
 }

 // Loop through the destination registers of this instruction and  
update

@@ -270,7 +278,7 @@
 // register.
 PhysRegIdPtr phys_dest_reg =  
dyn_inst->renamedDestRegIdx(dest_idx);

 DPRINTFR(ElasticTrace, "[sn:%lli] Update map for dest reg"
- " %i (%s)\n", seq_num, dest_reg.index(),
+ " %i (%s)\n", seq_num, phys_dest_reg->flatIndex(),
  dest_reg.className());
 physRegDepMap[phys_dest_reg->flatIndex()] = seq_num;
 }

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[gem5-dev] Change in public/gem5[master]: arch-arm: Add missing override keywords in fault.hh

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/4284 )


Change subject: arch-arm: Add missing override keywords in fault.hh
..

arch-arm: Add missing override keywords in fault.hh

Change-Id: I94a4bf4a633aeed550f8c01ccae824add3b85eb0
Signed-off-by: Andreas Sandberg 
Reviewed-by: Nikos Nikoleris 
Reviewed-on: https://gem5-review.googlesource.com/4284
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Curtis Dunham 
---
M src/arch/arm/faults.hh
1 file changed, 67 insertions(+), 63 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve
  Curtis Dunham: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved



diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh
index 6e7c92c..8d72dee 100644
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -183,7 +183,7 @@
 MiscRegIndex getFaultAddrReg64() const;

 void invoke(ThreadContext *tc, const StaticInstPtr  =
-StaticInst::nullStaticInstPtr);
+StaticInst::nullStaticInstPtr) override;
 void invoke64(ThreadContext *tc, const StaticInstPtr  =
   StaticInst::nullStaticInstPtr);
 virtual void annotate(AnnotationIDs id, uint64_t val) {}
@@ -215,13 +215,11 @@
   public:
 ArmFaultVals(ExtMachInst _machInst = 0, uint32_t _iss = 0) :
 ArmFault(_machInst, _iss) {}
-FaultName name() const { return vals.name; }
-FaultStat & countStat() { return vals.count; }
-FaultOffset offset(ThreadContext *tc);
+FaultName name() const override { return vals.name; }
+FaultStat & countStat() override { return vals.count; }
+FaultOffset offset(ThreadContext *tc) override;

-FaultOffset
-offset64()
-{
+FaultOffset offset64() override {
 if (toEL == fromEL) {
 if (opModeIsT(fromMode))
 return vals.currELTOffset;
@@ -233,25 +231,31 @@
 }
 }

-OperatingMode nextMode() { return vals.nextMode; }
-virtual bool routeToMonitor(ThreadContext *tc) const { return false; }
-uint8_t armPcOffset(bool isHyp)   { return isHyp ? vals.armPcElrOffset
- : vals.armPcOffset; }
-uint8_t thumbPcOffset(bool isHyp) { return isHyp ?  
vals.thumbPcElrOffset
- : vals.thumbPcOffset;  
}

-uint8_t armPcElrOffset() { return vals.armPcElrOffset; }
-uint8_t thumbPcElrOffset() { return vals.thumbPcElrOffset; }
-virtual bool abortDisable(ThreadContext* tc) { return  
vals.abortDisable; }

-virtual bool fiqDisable(ThreadContext* tc) { return vals.fiqDisable; }
-virtual ExceptionClass ec(ThreadContext *tc) const { return vals.ec; }
-virtual uint32_t iss() const { return issRaw; }
+OperatingMode nextMode() override { return vals.nextMode; }
+virtual bool routeToMonitor(ThreadContext *tc) const override {
+return false;
+}
+uint8_t armPcOffset(bool isHyp) override {
+return isHyp ? vals.armPcElrOffset
+ : vals.armPcOffset;
+}
+uint8_t thumbPcOffset(bool isHyp) override {
+return isHyp ? vals.thumbPcElrOffset
+ : vals.thumbPcOffset;
+}
+uint8_t armPcElrOffset() override { return vals.armPcElrOffset; }
+uint8_t thumbPcElrOffset() override { return vals.thumbPcElrOffset; }
+bool abortDisable(ThreadContext* tc) override { return  
vals.abortDisable; }

+bool fiqDisable(ThreadContext* tc) override { return vals.fiqDisable; }
+ExceptionClass ec(ThreadContext *tc) const override { return vals.ec; }
+uint32_t iss() const override { return issRaw; }
 };

 class Reset : public ArmFaultVals
 {
   public:
 void invoke(ThreadContext *tc, const StaticInstPtr  =
-StaticInst::nullStaticInstPtr);
+StaticInst::nullStaticInstPtr) override;
 };

 class UndefinedInstruction : public ArmFaultVals
@@ -279,10 +283,10 @@
 {}

 void invoke(ThreadContext *tc, const StaticInstPtr  =
-StaticInst::nullStaticInstPtr);
-bool routeToHyp(ThreadContext *tc) const;
-ExceptionClass ec(ThreadContext *tc) const;
-uint32_t iss() const;
+StaticInst::nullStaticInstPtr) override;
+bool routeToHyp(ThreadContext *tc) const override;
+ExceptionClass ec(ThreadContext *tc) const override;
+uint32_t iss() const override;
 };

 class SupervisorCall : public ArmFaultVals
@@ -297,10 +301,10 @@
 {}

 void invoke(ThreadContext *tc, const StaticInstPtr  =
-StaticInst::nullStaticInstPtr);
-bool routeToHyp(ThreadContext *tc) const;
-ExceptionClass ec(ThreadContext *tc) const;
-uint32_t iss() const;
+StaticInst::nullStaticInstPtr) override;
+

[gem5-dev] Change in public/gem5[master]: arch-sparc: Add a FaultVals instantiation for VecDisabled

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/4282 )


Change subject: arch-sparc: Add a FaultVals instantiation for VecDisabled
..

arch-sparc: Add a FaultVals instantiation for VecDisabled

Recent gcc versions complain about a missing VecDisabled not having an
explicit FaultVals instantiation.

Change-Id: I439e7b3a7d5cad20590f52b3f374ead3f3f070a6
Signed-off-by: Andreas Sandberg 
Reviewed-by: Nikos Nikoleris 
Reviewed-on: https://gem5-review.googlesource.com/4282
Reviewed-by: Jason Lowe-Power 
---
M src/arch/sparc/faults.hh
1 file changed, 1 insertion(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved



diff --git a/src/arch/sparc/faults.hh b/src/arch/sparc/faults.hh
index aa270fa..86f8c5b 100644
--- a/src/arch/sparc/faults.hh
+++ b/src/arch/sparc/faults.hh
@@ -294,6 +294,7 @@
 template<> SparcFaultBase::FaultVals SparcFault::vals;
 template<> SparcFaultBase::FaultVals SparcFault::vals;
 template<> SparcFaultBase::FaultVals SparcFault::vals;
+template<> SparcFaultBase::FaultVals SparcFault::vals;
 template<> SparcFaultBase::FaultVals SparcFault::vals;
 template<> SparcFaultBase::FaultVals SparcFault::vals;
 template<> SparcFaultBase::FaultVals SparcFault::vals;

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Gerrit-MessageType: merged
Gerrit-Change-Id: I439e7b3a7d5cad20590f52b3f374ead3f3f070a6
Gerrit-Change-Number: 4282
Gerrit-PatchSet: 2
Gerrit-Owner: Andreas Sandberg 
Gerrit-Reviewer: Andreas Sandberg 
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[gem5-dev] Change in public/gem5[master]: arch-x86: Add missing override in the X86 TLB

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/4283 )


Change subject: arch-x86: Add missing override in the X86 TLB
..

arch-x86: Add missing override in the X86 TLB

Change-Id: Ie5ef1aaaef46cf8ef8fa4b0fc8f7efb8cde9b489
Signed-off-by: Andreas Sandberg 
Reviewed-by: Nikos Nikoleris 
Reviewed-on: https://gem5-review.googlesource.com/4283
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Gabe Black 
Maintainer: Jason Lowe-Power 
---
M src/arch/x86/tlb.hh
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Gabe Black: Looks good to me, approved



diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh
index 09cd6ed..d036b74 100644
--- a/src/arch/x86/tlb.hh
+++ b/src/arch/x86/tlb.hh
@@ -151,7 +151,7 @@
 /*
  * Function to register Stats
  */
-void regStats();
+void regStats() override;

 // Checkpointing
 void serialize(CheckpointOut ) const override;

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Gerrit-Change-Id: Ie5ef1aaaef46cf8ef8fa4b0fc8f7efb8cde9b489
Gerrit-Change-Number: 4283
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[gem5-dev] Change in public/gem5[master]: arch-arm: Only increment SW PMU counters on writes to PMSWINC

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/4285 )


Change subject: arch-arm: Only increment SW PMU counters on writes to  
PMSWINC

..

arch-arm: Only increment SW PMU counters on writes to PMSWINC

When writing a bitmask of counters to PMSWINC, the PMU currently
increments the corresponding counters regardless of what they are
configured to count. According to the ARM ARM (D5.10.4), counters
should only be updated if they have been configured to count
software events (event type 0).

Change-Id: I5b2bc1fae55faa342b863721c9838342442831a9
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/4285
Reviewed-by: Jason Lowe-Power 
Maintainer: Andreas Sandberg 
---
M src/arch/arm/pmu.cc
1 file changed, 3 insertions(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved



diff --git a/src/arch/arm/pmu.cc b/src/arch/arm/pmu.cc
index 14b1b50..f1ff6cb 100644
--- a/src/arch/arm/pmu.cc
+++ b/src/arch/arm/pmu.cc
@@ -147,8 +147,10 @@
   case MISCREG_PMSWINC:
 for (int i = 0; i < counters.size(); ++i) {
 CounterState (getCounter(i));
-if (ctr.enabled && (val & (1 << i)))
+if (ctr.enabled && (val & (1 << i))
+&& ctr.eventId == ARCH_EVENT_SW_INCR ) {
 ++ctr.value;
+}
 }
 break;


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Gerrit-Change-Number: 4285
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[gem5-dev] Change in public/gem5[master]: arch-alpha: Add missing overrides

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/4281 )


Change subject: arch-alpha: Add missing overrides
..

arch-alpha: Add missing overrides

Change-Id: I3a52fcdb449c7df1612466270aa2c9b0a0f3afef
Reviewed-by: Nikos Nikoleris 
Reviewed-on: https://gem5-review.googlesource.com/4281
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Gabe Black 
Maintainer: Andreas Sandberg 
---
M src/arch/alpha/remote_gdb.hh
1 file changed, 3 insertions(+), 3 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved



diff --git a/src/arch/alpha/remote_gdb.hh b/src/arch/alpha/remote_gdb.hh
index 38ff919..c8ed709 100644
--- a/src/arch/alpha/remote_gdb.hh
+++ b/src/arch/alpha/remote_gdb.hh
@@ -50,8 +50,8 @@
 {
   protected:
 // Machine memory
-bool acc(Addr addr, size_t len);
-bool write(Addr addr, size_t size, const char *data);
+bool acc(Addr addr, size_t len) override;
+bool write(Addr addr, size_t size, const char *data) override;

 void insertHardBreak(Addr addr, size_t len) override;

@@ -75,7 +75,7 @@

   public:
 RemoteGDB(System *system, ThreadContext *context);
-BaseGdbRegCache *gdbRegs();
+BaseGdbRegCache *gdbRegs() override;
 };

 } // namespace AlphaISA

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Gerrit-Change-Id: I3a52fcdb449c7df1612466270aa2c9b0a0f3afef
Gerrit-Change-Number: 4281
Gerrit-PatchSet: 2
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[gem5-dev] Change in public/gem5[master]: python: Make GlobalExitEvent.getCode() return an int

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/4280 )


Change subject: python: Make GlobalExitEvent.getCode() return an int
..

python: Make GlobalExitEvent.getCode() return an int

PyBind normally casts integers returned from the C to long in
Python. This is normally fine since long in most cases behaves just
like an int. However, when passing the return value from getcode() to
sys.exit, unexpected behavior ensues. Due to the way the function is
defined, any type other than int (with the exception of None) will be
treated as an error and be equivalent to sys.exit(1).

Since we frequently use the sys.exit(event.getCode()) pattern, we need
to ensure that the function returns an integer. This change adds an
explicit type conversion to a Python integer in the wrapper code.

Change-Id: I73d6b881025064afa2b2e6eb4512fa2a4b0a87da
Signed-off-by: Andreas Sandberg 
Reviewed-by: Jose Marinho 
Reviewed-by: Curtis Dunham 
Reviewed-on: https://gem5-review.googlesource.com/4280
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Joe Gross 
---
M src/python/pybind11/event.cc
1 file changed, 4 insertions(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Joe Gross: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved



diff --git a/src/python/pybind11/event.cc b/src/python/pybind11/event.cc
index f9e6568..88ee699 100644
--- a/src/python/pybind11/event.cc
+++ b/src/python/pybind11/event.cc
@@ -135,7 +135,10 @@
std::unique_ptr>(
m, "GlobalSimLoopExitEvent")
 .def("getCause", ::getCause)
-.def("getCode", ::getCode)
+.def("getCode", [](GlobalSimLoopExitEvent *e) {
+return py::reinterpret_steal(
+PyInt_FromLong(e->getCode()));
+})
 ;

 // Event base class. These should never be returned directly to

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Gerrit-Change-Id: I73d6b881025064afa2b2e6eb4512fa2a4b0a87da
Gerrit-Change-Number: 4280
Gerrit-PatchSet: 2
Gerrit-Owner: Andreas Sandberg 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bradford Beckmann 
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Gerrit-Reviewer: Nathan Binkert 
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[gem5-dev] Change in public/gem5[master]: configs, arm: Fix incorrect use of mem_range in bL example

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/4380 )


Change subject: configs, arm: Fix incorrect use of mem_range in bL example
..

configs, arm: Fix incorrect use of mem_range in bL example

The change "config: Change mem_range attribute naming in ARM
SimpleSystem" modified the SimpleSystem class to be compatible with
the MemConfig utility script. While doing so, the way we report the
memory ranges supported by the system changed, which broke the bL
example configration. This changeset introduces the necessary changes
to make the script work again.

Change-Id: I789987950ff04b6c5ae1c8b807355bcba34f6b3c
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/4380
Reviewed-by: Jason Lowe-Power 
---
M configs/example/arm/fs_bigLITTLE.py
1 file changed, 2 insertions(+), 2 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved



diff --git a/configs/example/arm/fs_bigLITTLE.py  
b/configs/example/arm/fs_bigLITTLE.py

index a6110b5..489bc53 100644
--- a/configs/example/arm/fs_bigLITTLE.py
+++ b/configs/example/arm/fs_bigLITTLE.py
@@ -117,8 +117,8 @@
kernel=SysPaths.binary(kernel),
readfile=bootscript)

-sys.mem_ctrls = SimpleMemory(range=sys._mem_range)
-sys.mem_ctrls.port = sys.membus.master
+sys.mem_ctrls = [ SimpleMemory(range=r, port=sys.membus.master)
+  for r in sys.mem_ranges ]

 sys.connect()


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[gem5-dev] Change in public/gem5[master]: arm, config: Fix CPU names in ARM example configs

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/4360 )


Change subject: arm, config: Fix CPU names in ARM example configs
..

arm, config: Fix CPU names in ARM example configs

The ARM example configs used to rely on CPU aliases for the
AtomicSimpleCPU and KVM when configuring clusters. This broken when
support for CPU aliases was removed ('config: Remove support for CPU
aliases.'). This change updates the config scripts to use the full
class names instead.

Change-Id: If36c46207f39ca1897ecf77d9588f1c059819e63
Signed-off-by: Andreas Sandberg 
Reviewed-by: Nikos Nikoleris 
Reviewed-on: https://gem5-review.googlesource.com/4360
Reviewed-by: Jason Lowe-Power 
---
M configs/example/arm/devices.py
1 file changed, 3 insertions(+), 3 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved



diff --git a/configs/example/arm/devices.py b/configs/example/arm/devices.py
index 467d2b9..15492cb 100644
--- a/configs/example/arm/devices.py
+++ b/configs/example/arm/devices.py
@@ -44,7 +44,7 @@
 from common.Caches import *
 from common import CpuConfig

-have_kvm = "kvm" in CpuConfig.cpu_names()
+have_kvm = "ArmV8KvmCPU" in CpuConfig.cpu_names()

 class L1I(L1_ICache):
 tag_latency = 1
@@ -166,7 +166,7 @@

 class AtomicCluster(CpuCluster):
 def __init__(self, system, num_cpus, cpu_clock, cpu_voltage="1.0V"):
-cpu_config = [ CpuConfig.get("atomic"), None, None, None, None ]
+cpu_config = [ CpuConfig.get("AtomicSimpleCPU"), None, None, None,  
None ]

 super(AtomicCluster, self).__init__(system, num_cpus, cpu_clock,
 cpu_voltage, *cpu_config)
 def addL1(self):
@@ -174,7 +174,7 @@

 class KvmCluster(CpuCluster):
 def __init__(self, system, num_cpus, cpu_clock, cpu_voltage="1.0V"):
-cpu_config = [ CpuConfig.get("kvm"), None, None, None, None ]
+cpu_config = [ CpuConfig.get("ArmV8KvmCPU"), None, None, None,  
None ]

 super(KvmCluster, self).__init__(system, num_cpus, cpu_clock,
  cpu_voltage, *cpu_config)
 def addL1(self):

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Gerrit-Change-Number: 4360
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[gem5-dev] Change in public/gem5[master]: configs, arm: Fix incorrect use of mem_range in bL example

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/4380



Change subject: configs, arm: Fix incorrect use of mem_range in bL example
..

configs, arm: Fix incorrect use of mem_range in bL example

The change "config: Change mem_range attribute naming in ARM
SimpleSystem" modified the SimpleSystem class to be compatible with
the MemConfig utility script. While doing so, the way we report the
memory ranges supported by the system changed, which broke the bL
example configration. This changeset introduces the necessary changes
to make the script work again.

Change-Id: I789987950ff04b6c5ae1c8b807355bcba34f6b3c
Signed-off-by: Andreas Sandberg 
---
M configs/example/arm/fs_bigLITTLE.py
1 file changed, 2 insertions(+), 2 deletions(-)



diff --git a/configs/example/arm/fs_bigLITTLE.py  
b/configs/example/arm/fs_bigLITTLE.py

index a6110b5..489bc53 100644
--- a/configs/example/arm/fs_bigLITTLE.py
+++ b/configs/example/arm/fs_bigLITTLE.py
@@ -117,8 +117,8 @@
kernel=SysPaths.binary(kernel),
readfile=bootscript)

-sys.mem_ctrls = SimpleMemory(range=sys._mem_range)
-sys.mem_ctrls.port = sys.membus.master
+sys.mem_ctrls = [ SimpleMemory(range=r, port=sys.membus.master)
+  for r in sys.mem_ranges ]

 sys.connect()


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Gerrit-Owner: Andreas Sandberg 
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[gem5-dev] Change in public/gem5[master]: arm, config: Fix CPU names in ARM example configs

[Andreas Sandberg (Gerrit)]

Hello Nikos Nikoleris,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/4360

to review the following change.


Change subject: arm, config: Fix CPU names in ARM example configs
..

arm, config: Fix CPU names in ARM example configs

The ARM example configs used to rely on CPU aliases for the
AtomicSimpleCPU and KVM when configuring clusters. This broken when
support for CPU aliases was removed ('config: Remove support for CPU
aliases.'). This change updates the config scripts to use the full
class names instead.

Change-Id: If36c46207f39ca1897ecf77d9588f1c059819e63
Signed-off-by: Andreas Sandberg 
Reviewed-by: Nikos Nikoleris 
---
M configs/example/arm/devices.py
1 file changed, 3 insertions(+), 3 deletions(-)



diff --git a/configs/example/arm/devices.py b/configs/example/arm/devices.py
index 467d2b9..15492cb 100644
--- a/configs/example/arm/devices.py
+++ b/configs/example/arm/devices.py
@@ -44,7 +44,7 @@
 from common.Caches import *
 from common import CpuConfig

-have_kvm = "kvm" in CpuConfig.cpu_names()
+have_kvm = "ArmV8KvmCPU" in CpuConfig.cpu_names()

 class L1I(L1_ICache):
 tag_latency = 1
@@ -166,7 +166,7 @@

 class AtomicCluster(CpuCluster):
 def __init__(self, system, num_cpus, cpu_clock, cpu_voltage="1.0V"):
-cpu_config = [ CpuConfig.get("atomic"), None, None, None, None ]
+cpu_config = [ CpuConfig.get("AtomicSimpleCPU"), None, None, None,  
None ]

 super(AtomicCluster, self).__init__(system, num_cpus, cpu_clock,
 cpu_voltage, *cpu_config)
 def addL1(self):
@@ -174,7 +174,7 @@

 class KvmCluster(CpuCluster):
 def __init__(self, system, num_cpus, cpu_clock, cpu_voltage="1.0V"):
-cpu_config = [ CpuConfig.get("kvm"), None, None, None, None ]
+cpu_config = [ CpuConfig.get("ArmV8KvmCPU"), None, None, None,  
None ]

 super(KvmCluster, self).__init__(system, num_cpus, cpu_clock,
  cpu_voltage, *cpu_config)
 def addL1(self):

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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: If36c46207f39ca1897ecf77d9588f1c059819e63
Gerrit-Change-Number: 4360
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Gerrit-Owner: Andreas Sandberg 
Gerrit-Reviewer: Nikos Nikoleris 
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[gem5-dev] Change in public/gem5[master]: util, m5: Use consistent naming for m5op C symbols

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/4264 )


Change subject: util, m5: Use consistent naming for m5op C symbols
..

util, m5: Use consistent naming for m5op C symbols

Rename m5op C symbols to be prefixed all lower case, separated by
underscore, and prefixed by m5. This avoids potential name clashes for
short names such as arm.

Change-Id: Ic42f94d8a722661ef96c151d627e31eeb2e51490
Signed-off-by: Andreas Sandberg 
Reviewed-by: Jose Marinho 
Reviewed-on: https://gem5-review.googlesource.com/4264
Reviewed-by: Gabe Black 
Reviewed-by: Jason Lowe-Power 
---
M include/gem5/asm/generic/m5ops.h
M util/m5/m5.c
M util/m5/m5op.h
M util/m5/m5op_alpha.S
M util/m5/m5op_sparc.S
M util/m5/m5op_x86.S
6 files changed, 101 insertions(+), 100 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Gabe Black: Looks good to me, but someone else must approve
  Andreas Sandberg: Looks good to me, approved



diff --git a/include/gem5/asm/generic/m5ops.h  
b/include/gem5/asm/generic/m5ops.h

index b7999cb..e3df3f6 100644
--- a/include/gem5/asm/generic/m5ops.h
+++ b/include/gem5/asm/generic/m5ops.h
@@ -102,31 +102,31 @@
 #define M5OP_AN_GETID   0x11


-#define M5OP_FOREACH  \
-M5OP(arm, M5OP_ARM, 0);   \
-M5OP(quiesce, M5OP_QUIESCE, 0);   \
-M5OP(quiesceNs, M5OP_QUIESCE_NS, 0);  \
-M5OP(quiesceCycle, M5OP_QUIESCE_CYCLE, 0);\
-M5OP(quiesceTime, M5OP_QUIESCE_TIME, 0);  \
-M5OP(rpns, M5OP_RPNS, 0); \
-M5OP(wakeCPU, M5OP_WAKE_CPU, 0);  \
-M5OP(m5_exit, M5OP_EXIT, 0);  \
-M5OP(m5_fail, M5OP_FAIL, 0);  \
-M5OP(m5_initparam, M5OP_INIT_PARAM, 0);   \
-M5OP(m5_loadsymbol, M5OP_LOAD_SYMBOL, 0); \
-M5OP(m5_reset_stats, M5OP_RESET_STATS, 0);\
-M5OP(m5_dump_stats, M5OP_DUMP_STATS, 0);  \
-M5OP(m5_dumpreset_stats, M5OP_DUMP_RESET_STATS, 0);   \
-M5OP(m5_checkpoint, M5OP_CHECKPOINT, 0);  \
-M5OP(m5_readfile, M5OP_READ_FILE, 0); \
-M5OP(m5_writefile, M5OP_WRITE_FILE, 0);   \
-M5OP(m5_debugbreak, M5OP_DEBUG_BREAK, 0); \
-M5OP(m5_switchcpu, M5OP_SWITCH_CPU, 0);   \
-M5OP(m5_addsymbol, M5OP_ADD_SYMBOL, 0);   \
-M5OP(m5_panic, M5OP_PANIC, 0);\
-M5OP(m5_work_begin, M5OP_WORK_BEGIN, 0);  \
-M5OP(m5_work_end, M5OP_WORK_END, 0);  \
-M5OP(m5_togglesync, M5OP_DIST_TOGGLE_SYNC, 0);
+#define M5OP_FOREACH\
+M5OP(m5_arm, M5OP_ARM, 0);  \
+M5OP(m5_quiesce, M5OP_QUIESCE, 0);  \
+M5OP(m5_quiesce_ns, M5OP_QUIESCE_NS, 0);\
+M5OP(m5_quiesce_cycle, M5OP_QUIESCE_CYCLE, 0);  \
+M5OP(m5_quiesce_time, M5OP_QUIESCE_TIME, 0);\
+M5OP(m5_rpns, M5OP_RPNS, 0);\
+M5OP(m5_wake_cpu, M5OP_WAKE_CPU, 0);\
+M5OP(m5_exit, M5OP_EXIT, 0);\
+M5OP(m5_fail, M5OP_FAIL, 0);\
+M5OP(m5_init_param, M5OP_INIT_PARAM, 0);\
+M5OP(m5_load_symbol, M5OP_LOAD_SYMBOL, 0);  \
+M5OP(m5_reset_stats, M5OP_RESET_STATS, 0);  \
+M5OP(m5_dump_stats, M5OP_DUMP_STATS, 0);\
+M5OP(m5_dump_reset_stats, M5OP_DUMP_RESET_STATS, 0);\
+M5OP(m5_checkpoint, M5OP_CHECKPOINT, 0);\
+M5OP(m5_read_file, M5OP_READ_FILE, 0);  \
+M5OP(m5_write_file, M5OP_WRITE_FILE, 0);\
+M5OP(m5_debug_break, M5OP_DEBUG_BREAK, 0);  \
+M5OP(m5_switch_cpu, M5OP_SWITCH_CPU, 0);\
+M5OP(m5_add_symbol, M5OP_ADD_SYMBOL, 0);\
+M5OP(m5_panic, M5OP_PANIC, 0);  \
+M5OP(m5_work_begin, M5OP_WORK_BEGIN, 0);\
+M5OP(m5_work_end, M5OP_WORK_END, 0);\
+M5OP(m5_dist_togglesync, M5OP_DIST_TOGGLE_SYNC, 0);

 #define M5OP_FOREACH_ANNOTATION  \
 M5_ANNOTATION(m5a_bsm, M5OP_AN_BSM); \
diff --git a/util/m5/m5.c b/util/m5/m5.c
index bd39041..5b6c7a6 100644
--- a/util/m5/m5.c
+++ b/util/m5/m5.c
@@ -117,7 +117,7 @@
 // Linux does demand paging.
 memset(buf, 0, sizeof(buf));

-while 

[gem5-dev] Change in public/gem5[master]: util: Move m5op.h to the shared include directory

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/4265 )


Change subject: util: Move m5op.h to the shared include directory
..

util: Move m5op.h to the shared include directory

The header file with C declarations for m5ops is sometimes needed by
code outside of the util/m5 directory. Move this file to the shared
include directory and factor out flags to a generic asm header. Note
that applications that need to call m5ops still need to link with
libm5.a or implement their own trampolines.

Change-Id: I36a3f459ed71593e38b869dc2b1302c810f92276
Signed-off-by: Andreas Sandberg 
Reviewed-by: Jose Marinho 
Reviewed-on: https://gem5-review.googlesource.com/4265
Reviewed-by: Gabe Black 
Reviewed-by: Jason Lowe-Power 
---
A include/gem5/asm/generic/m5op_flags.h
M include/gem5/asm/generic/m5ops.h
R include/gem5/m5ops.h
M util/m5/m5.c
4 files changed, 62 insertions(+), 9 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve
  Gabe Black: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved



diff --git a/include/gem5/asm/generic/m5op_flags.h  
b/include/gem5/asm/generic/m5op_flags.h

new file mode 100644
index 000..de44e00
--- /dev/null
+++ b/include/gem5/asm/generic/m5op_flags.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2017 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Copyright (c) 2003-2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ *  Ali Saidi
+ *  Andreas Sandberg
+ */
+
+#ifndef __GEM5_ASM_GENERIC_M5OP_FLAGS_H__
+#define __GEM5_ASM_GENERIC_M5OP_FLAGS_H__
+
+/* Flags for annotation calls */
+#define M5_AN_FL_NONE   0x0
+#define M5_AN_FL_BAD0x2
+#define M5_AN_FL_LINK   0x10
+#define M5_AN_FL_RESET  0x20
+
+#endif //  __GEM5_ASM_GENERIC_M5OP_FLAGS_H__
diff --git a/include/gem5/asm/generic/m5ops.h  
b/include/gem5/asm/generic/m5ops.h

index e3df3f6..81569e0 100644
--- a/include/gem5/asm/generic/m5ops.h
+++ b/include/gem5/asm/generic/m5ops.h
@@ -45,6 +45,8 @@
 #ifndef __GEM5_ASM_GENERIC_M5OPS_H__
 #define __GEM5_ASM_GENERIC_M5OPS_H__

+#include 
+
 #define M5OP_ARM0x00
 #define M5OP_QUIESCE0x01
 #define M5OP_QUIESCE_NS 0x02
diff --git a/util/m5/m5op.h b/include/gem5/m5ops.h
similarity index 94%
rename from util/m5/m5op.h
rename to include/gem5/m5ops.h
index 3a507e1..5062ac2 100644
--- a/util/m5/m5op.h
+++ b/include/gem5/m5ops.h
@@ -29,8 +29,8 @@
  *  Ali Saidi
  */

-#ifndef __M5OP_H__
-#define __M5OP_H__
+#ifndef __GEM5_M5OP_H__
+#define __GEM5_M5OP_H__

 #ifdef __cplusplus
 extern "C" {
@@ -38,6 +38,8 @@

 #include 

+#include 
+
 void m5_arm(uint64_t address);
 void m5_quiesce(void);
 

[gem5-dev] Change in public/gem5[master]: style: Add shared gem5 headers to the style checker

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/4300 )


Change subject: style: Add shared gem5 headers to the style checker
..

style: Add shared gem5 headers to the style checker

Teach the style checker about common headers living in gem5/. These
should be included after any global library headers (e.g., C headers
or STL headers), but before the normal gem5 headers.

Change-Id: I322f841420e361c16314be8fa4cbd1e86d2bfa9f
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/4300
Reviewed-by: Jason Lowe-Power 
---
M util/style/sort_includes.py
1 file changed, 2 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved



diff --git a/util/style/sort_includes.py b/util/style/sort_includes.py
index cb88fec..39b3a13 100644
--- a/util/style/sort_includes.py
+++ b/util/style/sort_includes.py
@@ -160,6 +160,7 @@
 ('python', '<>', _include_matcher_fname("^Python\.h$")),
 ('pybind', '""', _include_matcher_fname("^pybind11/.*\.h$",
 delim='""')),
+('m5shared', '<>', _include_matcher_fname("^gem5/")),
 ('c', '<>', _include_matcher_fname("^.*\.h$")),
 ('stl', '<>', _include_matcher_fname("^\w+$")),
 ('cc', '<>', _include_matcher_fname("^.*\.(hh|hxx|hpp|H)$")),
@@ -177,6 +178,7 @@
 ('c', ),
 ('stl', ),
 ('cc', ),
+('m5shared', ),
 ('m5header', ),
 ('swig0', 'swig1', 'swig2', 'swig3', ),
 )

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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I322f841420e361c16314be8fa4cbd1e86d2bfa9f
Gerrit-Change-Number: 4300
Gerrit-PatchSet: 2
Gerrit-Owner: Andreas Sandberg 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Anthony Gutierrez 
Gerrit-Reviewer: Curtis Dunham 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Joe Gross 
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[gem5-dev] Change in public/gem5[master]: util: Move the m5ops.h file to a shared directory

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/4261 )


Change subject: util: Move the m5ops.h file to a shared directory
..

util: Move the m5ops.h file to a shared directory

The header file m5ops.h contains a list of constants that should be
shared between the simulator and utilities. Move this header file to a
new top-level directory for shared files and rename constants to make
them suitable for inclusion in the main simulator.

The structure of the shared include directory is as follows:

include/gem5: Files that can be included from C code.
include/gem5/asm: Files that can be included from assembly code.
  asm/generic/: Files that aren't guest ISA specific
  asm/${isa}/: Files that are guest ISA specific

Change-Id: I1aa511057bcaa80cc2d566109ff26581558c4a41
Signed-off-by: Andreas Sandberg 
Reviewed-by: Jose Marinho 
Reviewed-on: https://gem5-review.googlesource.com/4261
Reviewed-by: Jason Lowe-Power 
---
A include/gem5/asm/generic/m5ops.h
M util/m5/Makefile.aarch64
M util/m5/Makefile.alpha
M util/m5/Makefile.arm
M util/m5/Makefile.sparc
M util/m5/Makefile.thumb
M util/m5/Makefile.x86
M util/m5/m5op_alpha.S
M util/m5/m5op_arm.S
M util/m5/m5op_arm_A64.S
M util/m5/m5op_sparc.S
M util/m5/m5op_x86.S
D util/m5/m5ops.h
13 files changed, 231 insertions(+), 224 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved



diff --git a/include/gem5/asm/generic/m5ops.h  
b/include/gem5/asm/generic/m5ops.h

new file mode 100644
index 000..b7999cb
--- /dev/null
+++ b/include/gem5/asm/generic/m5ops.h
@@ -0,0 +1,149 @@
+/*
+ * Copyright (c) 2016 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Copyright (c) 2003-2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ *  Ali Saidi
+ *  Andreas Sandberg
+ */
+
+#ifndef __GEM5_ASM_GENERIC_M5OPS_H__
+#define __GEM5_ASM_GENERIC_M5OPS_H__
+
+#define M5OP_ARM0x00
+#define M5OP_QUIESCE0x01
+#define M5OP_QUIESCE_NS 0x02
+#define M5OP_QUIESCE_CYCLE  0x03
+#define M5OP_QUIESCE_TIME   0x04
+#define M5OP_RPNS   0x07
+#define M5OP_WAKE_CPU   0x09
+#define M5OP_DEPRECATED10x10 // obsolete ivlb
+#define M5OP_DEPRECATED20x11 // obsolete ivle
+#define M5OP_DEPRECATED30x20 // deprecated exit function
+#define M5OP_EXIT   0x21
+#define M5OP_FAIL   0x22
+#define M5OP_INIT_PARAM 0x30
+#define M5OP_LOAD_SYMBOL0x31
+#define M5OP_RESET_STATS0x40
+#define M5OP_DUMP_STATS 0x41
+#define M5OP_DUMP_RESET_STATS   0x42
+#define M5OP_CHECKPOINT 0x43
+#define M5OP_WRITE_FILE 0x4F
+#define 

[gem5-dev] Change in public/gem5[master]: arch-arm: Use named constants for m5op instructions

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/4263 )


Change subject: arch-arm: Use named constants for m5op instructions
..

arch-arm: Use named constants for m5op instructions

Change-Id: I544519c4f87e50cc02af29cbb3edc31ecf726e8e
Signed-off-by: Andreas Sandberg 
Reviewed-by: Nikos Nikoleris 
Reviewed-on: https://gem5-review.googlesource.com/4263
Reviewed-by: Gabe Black 
Reviewed-by: Jason Lowe-Power 
---
M src/arch/arm/isa/formats/aarch64.isa
M src/arch/arm/isa/formats/m5ops.isa
M src/arch/arm/isa/includes.isa
3 files changed, 55 insertions(+), 52 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve
  Gabe Black: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved



diff --git a/src/arch/arm/isa/formats/aarch64.isa  
b/src/arch/arm/isa/formats/aarch64.isa

index 1252cdf..38e5b15 100644
--- a/src/arch/arm/isa/formats/aarch64.isa
+++ b/src/arch/arm/isa/formats/aarch64.isa
@@ -2002,32 +2002,32 @@
 {
 const uint32_t m5func = bits(machInst, 23, 16);
 switch (m5func) {
-  case 0x00: return new Arm(machInst);
-  case 0x01: return new Quiesce(machInst);
-  case 0x02: return new QuiesceNs64(machInst);
-  case 0x03: return new QuiesceCycles64(machInst);
-  case 0x04: return new QuiesceTime64(machInst);
-  case 0x07: return new Rpns64(machInst);
-  case 0x09: return new WakeCPU64(machInst);
-  case 0x10: return new Deprecated_ivlb(machInst);
-  case 0x11: return new Deprecated_ivle(machInst);
-  case 0x20: return new Deprecated_exit (machInst);
-  case 0x21: return new M5exit64(machInst);
-  case 0x22: return new M5fail64(machInst);
-  case 0x31: return new Loadsymbol(machInst);
-  case 0x30: return new Initparam64(machInst);
-  case 0x40: return new Resetstats64(machInst);
-  case 0x41: return new Dumpstats64(machInst);
-  case 0x42: return new Dumpresetstats64(machInst);
-  case 0x43: return new M5checkpoint64(machInst);
-  case 0x4F: return new M5writefile64(machInst);
-  case 0x50: return new M5readfile64(machInst);
-  case 0x51: return new M5break(machInst);
-  case 0x52: return new M5switchcpu(machInst);
-  case 0x53: return new M5addsymbol64(machInst);
-  case 0x54: return new M5panic(machInst);
-  case 0x5a: return new M5workbegin64(machInst);
-  case 0x5b: return new M5workend64(machInst);
+  case M5OP_ARM: return new Arm(machInst);
+  case M5OP_QUIESCE: return new Quiesce(machInst);
+  case M5OP_QUIESCE_NS: return new QuiesceNs64(machInst);
+  case M5OP_QUIESCE_CYCLE: return new QuiesceCycles64(machInst);
+  case M5OP_QUIESCE_TIME: return new QuiesceTime64(machInst);
+  case M5OP_RPNS: return new Rpns64(machInst);
+  case M5OP_WAKE_CPU: return new WakeCPU64(machInst);
+  case M5OP_DEPRECATED1: return new Deprecated_ivlb(machInst);
+  case M5OP_DEPRECATED2: return new Deprecated_ivle(machInst);
+  case M5OP_DEPRECATED3: return new Deprecated_exit (machInst);
+  case M5OP_EXIT: return new M5exit64(machInst);
+  case M5OP_FAIL: return new M5fail64(machInst);
+  case M5OP_LOAD_SYMBOL: return new Loadsymbol(machInst);
+  case M5OP_INIT_PARAM: return new Initparam64(machInst);
+  case M5OP_RESET_STATS: return new Resetstats64(machInst);
+  case M5OP_DUMP_STATS: return new Dumpstats64(machInst);
+  case M5OP_DUMP_RESET_STATS: return new  
Dumpresetstats64(machInst);

+  case M5OP_CHECKPOINT: return new M5checkpoint64(machInst);
+  case M5OP_WRITE_FILE: return new M5writefile64(machInst);
+  case M5OP_READ_FILE: return new M5readfile64(machInst);
+  case M5OP_DEBUG_BREAK: return new M5break(machInst);
+  case M5OP_SWITCH_CPU: return new M5switchcpu(machInst);
+  case M5OP_ADD_SYMBOL: return new M5addsymbol64(machInst);
+  case M5OP_PANIC: return new M5panic(machInst);
+  case M5OP_WORK_BEGIN: return new M5workbegin64(machInst);
+  case M5OP_WORK_END: return new M5workend64(machInst);
   default: return new Unknown64(machInst);
 }
 }
diff --git a/src/arch/arm/isa/formats/m5ops.isa  
b/src/arch/arm/isa/formats/m5ops.isa

index 26210af..d3db813 100644
--- a/src/arch/arm/isa/formats/m5ops.isa
+++ b/src/arch/arm/isa/formats/m5ops.isa
@@ -42,32 +42,32 @@
 {
 const uint32_t m5func = bits(machInst, 23, 16);
 switch(m5func) {
-case 0x00: return new Arm(machInst);
-case 0x01: return new Quiesce(machInst);
-case 0x02: return new 

[gem5-dev] Change in public/gem5[master]: sim: Use named constants for pseudo ops

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/4262 )


Change subject: sim: Use named constants for pseudo ops
..

sim: Use named constants for pseudo ops

Use named constants from a shared header instead of magic values when
handling pseudo ops.

Change-Id: If157060bbcd772ce7e8556482b44ca714f4319b1
Signed-off-by: Andreas Sandberg 
Reviewed-by: Nikos Nikoleris 
Reviewed-on: https://gem5-review.googlesource.com/4262
Reviewed-by: Gabe Black 
Reviewed-by: Jason Lowe-Power 
---
M SConstruct
M src/sim/pseudo_inst.cc
2 files changed, 39 insertions(+), 34 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved



diff --git a/SConstruct b/SConstruct
index 146b156..e4880e1 100755
--- a/SConstruct
+++ b/SConstruct
@@ -554,6 +554,9 @@
 # the ext directory should be on the #includes path
 main.Append(CPPPATH=[Dir('ext')])

+# Add shared top-level headers
+main.Prepend(CPPPATH=Dir('include'))
+
 def strip_build_path(path, env):
 path = str(path)
 variant_base = env['BUILDROOT'] + os.path.sep
diff --git a/src/sim/pseudo_inst.cc b/src/sim/pseudo_inst.cc
index 778675f..dc37a8c 100644
--- a/src/sim/pseudo_inst.cc
+++ b/src/sim/pseudo_inst.cc
@@ -51,6 +51,8 @@
 #include 
 #include 

+#include 
+
 #include "arch/kernel_stats.hh"
 #include "arch/pseudo_inst.hh"
 #include "arch/utility.hh"
@@ -109,111 +111,111 @@
 }

 switch (func) {
-  case 0x00: // arm_func
+  case M5OP_ARM:
 arm(tc);
 break;

-  case 0x01: // quiesce_func
+  case M5OP_QUIESCE:
 quiesce(tc);
 break;

-  case 0x02: // quiescens_func
-quiesceSkip(tc);
-break;
-
-  case 0x03: // quiescecycle_func
+  case M5OP_QUIESCE_NS:
 quiesceNs(tc, args[0]);
 break;

-  case 0x04: // quiescetime_func
+  case M5OP_QUIESCE_CYCLE:
+quiesceCycles(tc, args[0]);
+break;
+
+  case M5OP_QUIESCE_TIME:
 return quiesceTime(tc);

-  case 0x07: // rpns_func
+  case M5OP_RPNS:
 return rpns(tc);

-  case 0x09: // wakecpu_func
+  case M5OP_WAKE_CPU:
 wakeCPU(tc, args[0]);
 break;

-  case 0x21: // exit_func
+  case M5OP_EXIT:
 m5exit(tc, args[0]);
 break;

-  case 0x22:
+  case M5OP_FAIL:
 m5fail(tc, args[0], args[1]);
 break;

-  case 0x30: // initparam_func
+  case M5OP_INIT_PARAM:
 return initParam(tc, args[0], args[1]);

-  case 0x31: // loadsymbol_func
+  case M5OP_LOAD_SYMBOL:
 loadsymbol(tc);
 break;

-  case 0x40: // resetstats_func
+  case M5OP_RESET_STATS:
 resetstats(tc, args[0], args[1]);
 break;

-  case 0x41: // dumpstats_func
+  case M5OP_DUMP_STATS:
 dumpstats(tc, args[0], args[1]);
 break;

-  case 0x42: // dumprststats_func
+  case M5OP_DUMP_RESET_STATS:
 dumpresetstats(tc, args[0], args[1]);
 break;

-  case 0x43: // ckpt_func
+  case M5OP_CHECKPOINT:
 m5checkpoint(tc, args[0], args[1]);
 break;

-  case 0x4f: // writefile_func
+  case M5OP_WRITE_FILE:
 return writefile(tc, args[0], args[1], args[2], args[3]);

-  case 0x50: // readfile_func
+  case M5OP_READ_FILE:
 return readfile(tc, args[0], args[1], args[2]);

-  case 0x51: // debugbreak_func
+  case M5OP_DEBUG_BREAK:
 debugbreak(tc);
 break;

-  case 0x52: // switchcpu_func
+  case M5OP_SWITCH_CPU:
 switchcpu(tc);
 break;

-  case 0x53: // addsymbol_func
+  case M5OP_ADD_SYMBOL:
 addsymbol(tc, args[0], args[1]);
 break;

-  case 0x54: // panic_func
+  case M5OP_PANIC:
 panic("M5 panic instruction called at %s\n", tc->pcState());

-  case 0x5a: // work_begin_func
+  case M5OP_WORK_BEGIN:
 workbegin(tc, args[0], args[1]);
 break;

-  case 0x5b: // work_end_func
+  case M5OP_WORK_END:
 workend(tc, args[0], args[1]);
 break;

-  case 0x55: // annotate_func
-  case 0x56: // reserved2_func
-  case 0x57: // reserved3_func
-  case 0x58: // reserved4_func
-  case 0x59: // reserved5_func
+  case M5OP_ANNOTATE:
+  case M5OP_RESERVED2:
+  case M5OP_RESERVED3:
+  case M5OP_RESERVED4:
+  case M5OP_RESERVED5:
 warn("Unimplemented m5 op (0x%x)\n", func);
 break;

   /* SE mode functions */
-  case 0x60: // syscall_func
+  case M5OP_SE_SYSCALL:
 m5Syscall(tc);
 break;

-  case 0x61: // pagefault_func
+  case M5OP_SE_PAGE_FAULT:
 m5PageFault(tc);
 break;

   /* dist-gem5 

[gem5-dev] Change in public/gem5[master]: style: Add shared gem5 headers to the style checker

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/4300



Change subject: style: Add shared gem5 headers to the style checker
..

style: Add shared gem5 headers to the style checker

Teach the style checker about common headers living in gem5/. These
should be included after any global library headers (e.g., C headers
or STL headers), but before the normal gem5 headers.

Change-Id: I322f841420e361c16314be8fa4cbd1e86d2bfa9f
Signed-off-by: Andreas Sandberg 
---
M util/style/sort_includes.py
1 file changed, 2 insertions(+), 0 deletions(-)



diff --git a/util/style/sort_includes.py b/util/style/sort_includes.py
index cb88fec..39b3a13 100644
--- a/util/style/sort_includes.py
+++ b/util/style/sort_includes.py
@@ -160,6 +160,7 @@
 ('python', '<>', _include_matcher_fname("^Python\.h$")),
 ('pybind', '""', _include_matcher_fname("^pybind11/.*\.h$",
 delim='""')),
+('m5shared', '<>', _include_matcher_fname("^gem5/")),
 ('c', '<>', _include_matcher_fname("^.*\.h$")),
 ('stl', '<>', _include_matcher_fname("^\w+$")),
 ('cc', '<>', _include_matcher_fname("^.*\.(hh|hxx|hpp|H)$")),
@@ -177,6 +178,7 @@
 ('c', ),
 ('stl', ),
 ('cc', ),
+('m5shared', ),
 ('m5header', ),
 ('swig0', 'swig1', 'swig2', 'swig3', ),
 )

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Gerrit-Project: public/gem5
Gerrit-Branch: master
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Gerrit-Change-Id: I322f841420e361c16314be8fa4cbd1e86d2bfa9f
Gerrit-Change-Number: 4300
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Gerrit-Owner: Andreas Sandberg 
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[gem5-dev] Change in public/gem5[master]: kvm, arm: Switch to the device EQ when accessing ISA devices

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/4288 )


Change subject: kvm, arm: Switch to the device EQ when accessing ISA devices
..

kvm, arm: Switch to the device EQ when accessing ISA devices

ISA devices typically run in the device event queue. Previously, we
assumed that devices would perform their own EQ migrations as
needed. This isn't ideal since it means we have different conventions
for IO devices and ISA devices. Switch to doing migrations in the KVM
CPU instead to make the behavior consistent.

Change-Id: I33b74480fb2126b0786dbdbfdcfa86083384250c
Signed-off-by: Andreas Sandberg 
Reviewed-by: Nikos Nikoleris 
Reviewed-on: https://gem5-review.googlesource.com/4288
Reviewed-by: Jason Lowe-Power 
---
M src/arch/arm/kvm/armv8_cpu.cc
M src/dev/arm/generic_timer.cc
2 files changed, 18 insertions(+), 13 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved



diff --git a/src/arch/arm/kvm/armv8_cpu.cc b/src/arch/arm/kvm/armv8_cpu.cc
index db2b9c0..209f49e 100644
--- a/src/arch/arm/kvm/armv8_cpu.cc
+++ b/src/arch/arm/kvm/armv8_cpu.cc
@@ -260,7 +260,17 @@
 }

 for (const auto  : getSysRegMap()) {
-const uint64_t value(tc->readMiscReg(ri.idx));
+uint64_t value;
+if (ri.is_device) {
+// This system register is backed by a device. This means
+// we need to lock the device event queue.
+EventQueue::ScopedMigration migrate(deviceEventQueue());
+
+value = tc->readMiscReg(ri.idx);
+} else {
+value = tc->readMiscReg(ri.idx);
+}
+
 DPRINTF(KvmContext, "  %s := 0x%x\n", ri.name, value);
 setOneReg(ri.kvm, value);
 }
@@ -323,10 +333,15 @@
 for (const auto  : getSysRegMap()) {
 const auto value(getOneRegU64(ri.kvm));
 DPRINTF(KvmContext, "  %s := 0x%x\n", ri.name, value);
-if (ri.is_device)
+if (ri.is_device) {
+// This system register is backed by a device. This means
+// we need to lock the device event queue.
+EventQueue::ScopedMigration migrate(deviceEventQueue());
+
 tc->setMiscReg(ri.idx, value);
-else
+} else {
 tc->setMiscRegNoEffect(ri.idx, value);
+}
 }

 PCState pc(getOneRegU64(INT_REG(regs.pc)));
diff --git a/src/dev/arm/generic_timer.cc b/src/dev/arm/generic_timer.cc
index 6332b8f..3508674 100644
--- a/src/dev/arm/generic_timer.cc
+++ b/src/dev/arm/generic_timer.cc
@@ -318,11 +318,6 @@
 void
 GenericTimer::setMiscReg(int reg, unsigned cpu, MiscReg val)
 {
-// This method might have been called from another context if we
-// are running in multi-core KVM. Migrate to the SimObject's event
-// queue to prevent surprising race conditions.
-EventQueue::ScopedMigration migrate(eventQueue());
-
 CoreTimers (getTimers(cpu));

 switch (reg) {
@@ -415,11 +410,6 @@
 MiscReg
 GenericTimer::readMiscReg(int reg, unsigned cpu)
 {
-// This method might have been called from another context if we
-// are running in multi-core KVM. Migrate to the SimObject's event
-// queue to prevent surprising race conditions.
-EventQueue::ScopedMigration migrate(eventQueue());
-
 CoreTimers (getTimers(cpu));

 switch (reg) {

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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I33b74480fb2126b0786dbdbfdcfa86083384250c
Gerrit-Change-Number: 4288
Gerrit-PatchSet: 2
Gerrit-Owner: Andreas Sandberg 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nikos Nikoleris 
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[gem5-dev] Change in public/gem5[master]: cpu, kvm: Fix deadlock issue when resuming a drained system

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/4286 )


Change subject: cpu, kvm: Fix deadlock issue when resuming a drained system
..

cpu, kvm: Fix deadlock issue when resuming a drained system

The KVM CPU sometimes needs to access devices when drain() is
called. This typically happens on ARM when synchronizing devices that
use the system register interface. When called from drain(), the event
queue isn't locked since drain is called from the outside when the
simulator isn't servicing any events. In such cases, performing a
migration to the device's queue will unlock a mutex that isn't
locked. This typically results in a deadlock when resuming the system
since the lock will be in an undefined state.

Change-Id: Ibdcc2e034e916a929124f297e72aae306cf66728
Signed-off-by: Andreas Sandberg 
Reviewed-by: Nikos Nikoleris 
Reviewed-by: Curtis Dunham 
Reviewed-on: https://gem5-review.googlesource.com/4286
Reviewed-by: Jason Lowe-Power 
---
M src/cpu/kvm/base.cc
1 file changed, 7 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved



diff --git a/src/cpu/kvm/base.cc b/src/cpu/kvm/base.cc
index 250c6a2..6ea99ce 100644
--- a/src/cpu/kvm/base.cc
+++ b/src/cpu/kvm/base.cc
@@ -358,6 +358,13 @@
 return DrainState::Drained;

 DPRINTF(Drain, "BaseKvmCPU::drain\n");
+
+// The event queue won't be locked when calling drain since that's
+// not done from an event. Lock the event queue here to make sure
+// that scoped migrations continue to work if we need to
+// synchronize the thread context.
+std::lock_guard lock(*this->eventQueue());
+
 switch (_status) {
   case Running:
 // The base KVM code is normally ready when it is in the

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Gerrit-Change-Id: Ibdcc2e034e916a929124f297e72aae306cf66728
Gerrit-Change-Number: 4286
Gerrit-PatchSet: 2
Gerrit-Owner: Andreas Sandberg 
Gerrit-Reviewer: Andreas Sandberg 
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[gem5-dev] Change in public/gem5[master]: kvm: Add a helper method to access device event queues

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/4287 )


Change subject: kvm: Add a helper method to access device event queues
..

kvm: Add a helper method to access device event queues

The VM's event queue is normally used for devices in multi-core KVM
mode. Add a helper method, BaseKvmCPU::deviceEventQueue(), to access
this queue. This makes the intention of code migrating to device event
queues clearer.

Change-Id: Ifb10f553a6d7445c8d562f658cf9d0b1f4c577ff
Signed-off-by: Andreas Sandberg 
Reviewed-by: Nikos Nikoleris 
Reviewed-on: https://gem5-review.googlesource.com/4287
Reviewed-by: Jason Lowe-Power 
---
M src/cpu/kvm/base.cc
M src/cpu/kvm/base.hh
M src/cpu/kvm/x86_cpu.cc
3 files changed, 16 insertions(+), 8 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved



diff --git a/src/cpu/kvm/base.cc b/src/cpu/kvm/base.cc
index 6ea99ce..d0f7515 100644
--- a/src/cpu/kvm/base.cc
+++ b/src/cpu/kvm/base.cc
@@ -1147,10 +1147,9 @@
 delete pkt;
 return clockPeriod() * ipr_delay;
 } else {
-// Temporarily lock and migrate to the event queue of the
-// VM. This queue is assumed to "own" all devices we need to
-// access if running in multi-core mode.
-EventQueue::ScopedMigration migrate(vm.eventQueue());
+// Temporarily lock and migrate to the device event queue to
+// prevent races in multi-core mode.
+EventQueue::ScopedMigration migrate(deviceEventQueue());

 return dataPort.submitIO(pkt);
 }
diff --git a/src/cpu/kvm/base.hh b/src/cpu/kvm/base.hh
index 29872e7..a22637f 100644
--- a/src/cpu/kvm/base.hh
+++ b/src/cpu/kvm/base.hh
@@ -419,6 +419,16 @@
 void syncThreadContext();

 /**
+ * Get a pointer to the event queue owning devices.
+ *
+ * Devices always live in a separate device event queue when
+ * running in multi-core mode. We need to temporarily migrate to
+ * this queue when accessing devices. By convention, devices and
+ * the VM use the same event queue.
+ */
+EventQueue *deviceEventQueue() { return vm.eventQueue(); }
+
+/**
  * Update the KVM if the thread context is dirty.
  */
 void syncKvmState();
diff --git a/src/cpu/kvm/x86_cpu.cc b/src/cpu/kvm/x86_cpu.cc
index bdbdadf..467e1ba 100644
--- a/src/cpu/kvm/x86_cpu.cc
+++ b/src/cpu/kvm/x86_cpu.cc
@@ -1346,10 +1346,9 @@
 }

 const MemCmd cmd(isWrite ? MemCmd::WriteReq : MemCmd::ReadReq);
-// Temporarily lock and migrate to the event queue of the
-// VM. This queue is assumed to "own" all devices we need to
-// access if running in multi-core mode.
-EventQueue::ScopedMigration migrate(vm.eventQueue());
+// Temporarily lock and migrate to the device event queue to
+// prevent races in multi-core mode.
+EventQueue::ScopedMigration migrate(deviceEventQueue());
 for (int i = 0; i < count; ++i) {
 RequestPtr io_req = new Request(pAddr, kvm_run.io.size,
 Request::UNCACHEABLE,  
dataMasterId());


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Gerrit-Change-Id: Ifb10f553a6d7445c8d562f658cf9d0b1f4c577ff
Gerrit-Change-Number: 4287
Gerrit-PatchSet: 2
Gerrit-Owner: Andreas Sandberg 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nikos Nikoleris 
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[gem5-dev] Change in public/gem5[master]: arch-arm: Switch to DTOnly as the default machine type

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/4260 )


Change subject: arch-arm: Switch to DTOnly as the default machine type
..

arch-arm: Switch to DTOnly as the default machine type

Old ARM systems used to pass the machine type in the ATAGS list passed
to the kernel. This has been largely deprecated by the introduction of
device trees. Switch to the DTOnly machine type by default in gem5
since all new platforms and kernel will require this behavior.

Change-Id: Icfd085e4862863b4ef495566bfddbd11591866c3
Signed-off-by: Andreas Sandberg 
Reviewed-by: Nikos Nikoleris 
Reviewed-on: https://gem5-review.googlesource.com/4260
Reviewed-by: Jason Lowe-Power 
---
M configs/example/arm/fs_bigLITTLE.py
M configs/example/arm/starter_fs.py
M src/arch/arm/ArmSystem.py
3 files changed, 3 insertions(+), 5 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved



diff --git a/configs/example/arm/fs_bigLITTLE.py  
b/configs/example/arm/fs_bigLITTLE.py

index 2965f47..a6110b5 100644
--- a/configs/example/arm/fs_bigLITTLE.py
+++ b/configs/example/arm/fs_bigLITTLE.py
@@ -115,8 +115,7 @@
 def createSystem(caches, kernel, bootscript, disks=[]):
 sys = devices.SimpleSystem(caches, default_mem_size,
kernel=SysPaths.binary(kernel),
-   readfile=bootscript,
-   machine_type="DTOnly")
+   readfile=bootscript)

 sys.mem_ctrls = SimpleMemory(range=sys._mem_range)
 sys.mem_ctrls.port = sys.membus.master
diff --git a/configs/example/arm/starter_fs.py  
b/configs/example/arm/starter_fs.py

index 9b6f68f..2ca1cb8 100644
--- a/configs/example/arm/starter_fs.py
+++ b/configs/example/arm/starter_fs.py
@@ -110,8 +110,7 @@
   mem_mode=mem_mode,
   dtb_filename=dtb_file,
   kernel=SysPaths.binary(args.kernel),
-  readfile=args.script,
-  machine_type="DTOnly")
+  readfile=args.script)

 MemConfig.config_mem(args, system)

diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index c21b9c6..4fa9fd8 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -84,7 +84,7 @@
 type = 'GenericArmSystem'
 cxx_header = "arch/arm/system.hh"
 load_addr_mask = 0x0fff
-machine_type = Param.ArmMachineType('VExpress_EMM',
+machine_type = Param.ArmMachineType('DTOnly',
 "Machine id from http://www.arm.linux.org.uk/developer/machines/;)
 atags_addr = Param.Addr("Address where default atags structure  
should " \

 "be written")

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Gerrit-Change-Id: Icfd085e4862863b4ef495566bfddbd11591866c3
Gerrit-Change-Number: 4260
Gerrit-PatchSet: 2
Gerrit-Owner: Andreas Sandberg 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nikos Nikoleris 
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[gem5-dev] Change in public/gem5[master]: dev: Add a dummy serial device

[Andreas Sandberg (Gerrit)]

Hello Curtis Dunham,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/4290

to review the following change.


Change subject: dev: Add a dummy serial device
..

dev: Add a dummy serial device

Add a dummy serial device that discards any output and doesn't provide
any input. This device can be used to terminate UARTs that don't have
a default device (e.g., a terminal) attached.

Change-Id: I4a6b0b5037ce360f59bfb5c566e1698d113a1d26
Signed-off-by: Andreas Sandberg 
Reviewed-by: Curtis Dunham 
---
M src/dev/Serial.py
M src/dev/serial.cc
M src/dev/serial.hh
3 files changed, 57 insertions(+), 0 deletions(-)



diff --git a/src/dev/Serial.py b/src/dev/Serial.py
index b0bdc2c..0e653ad 100644
--- a/src/dev/Serial.py
+++ b/src/dev/Serial.py
@@ -43,3 +43,7 @@
 type = 'SerialDevice'
 abstract = True
 cxx_header = "dev/serial.hh"
+
+class SerialNullDevice(SerialDevice):
+type = 'SerialNullDevice'
+cxx_header = "dev/serial.hh"
diff --git a/src/dev/serial.cc b/src/dev/serial.cc
index c75cdf9..3318cc8 100644
--- a/src/dev/serial.cc
+++ b/src/dev/serial.cc
@@ -41,6 +41,7 @@

 #include "base/misc.hh"
 #include "params/SerialDevice.hh"
+#include "params/SerialNullDevice.hh"

 SerialDevice::SerialDevice(const SerialDeviceParams *p)
 : SimObject(p), deviceDataAvail(nullptr)
@@ -70,3 +71,39 @@
 deviceDataAvail->process();
 }

+
+
+
+SerialNullDevice::SerialNullDevice(const SerialNullDeviceParams *p)
+: SerialDevice(p)
+{
+}
+
+SerialNullDevice::~SerialNullDevice()
+{
+}
+
+bool
+SerialNullDevice::dataAvailable() const
+{
+return false;
+}
+
+void
+SerialNullDevice::out(char c)
+{
+}
+
+uint8_t
+SerialNullDevice::in()
+{
+panic("SerialNullDevice does not have pending data.\n");
+}
+
+
+
+SerialNullDevice *
+SerialNullDeviceParams::create()
+{
+return new SerialNullDevice(this);
+}
diff --git a/src/dev/serial.hh b/src/dev/serial.hh
index d131c48..c902723 100644
--- a/src/dev/serial.hh
+++ b/src/dev/serial.hh
@@ -44,6 +44,7 @@
 #include "sim/sim_object.hh"

 struct SerialDeviceParams;
+struct SerialNullDeviceParams;

 /**
  * Base class for serial devices such as terminals.
@@ -97,4 +98,19 @@
 Callback *deviceDataAvail;
 };

+/**
+ * Dummy serial device that discards all data sent to it.
+ */
+class SerialNullDevice : public SerialDevice
+{
+  public:
+SerialNullDevice(const SerialNullDeviceParams *p);
+~SerialNullDevice();
+
+  public:
+bool dataAvailable() const override;
+void out(char c) override;
+uint8_t in() override;
+};
+
 #endif // __DEV_SERIAL_HH__

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[gem5-dev] Change in public/gem5[master]: dev: Refactor UART->Terminal interface

[Andreas Sandberg (Gerrit)]

Hello Curtis Dunham,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/4289

to review the following change.


Change subject: dev: Refactor UART->Terminal interface
..

dev: Refactor UART->Terminal interface

The UART models currently assume that they are always wired to a
terminal. While true at the moment, this isn't necessarily a valid
assumption. This change introduces the SerialDevice class that defines
the interface for serial devices. Currently, Terminal is the only
class that implements this interface.

Change-Id: I74fefafbbaf5ac1ec0d4ec0b5a0f4b246fdad305
Signed-off-by: Andreas Sandberg 
Reviewed-by: Curtis Dunham 
---
M src/dev/SConscript
A src/dev/Serial.py
M src/dev/Terminal.py
M src/dev/Uart.py
M src/dev/arm/pl011.cc
A src/dev/serial.cc
A src/dev/serial.hh
M src/dev/terminal.cc
M src/dev/terminal.hh
M src/dev/uart.cc
M src/dev/uart.hh
M src/dev/uart8250.cc
M src/dev/virtio/VirtIOConsole.py
M src/dev/virtio/console.cc
M src/dev/virtio/console.hh
15 files changed, 261 insertions(+), 72 deletions(-)



diff --git a/src/dev/SConscript b/src/dev/SConscript
index 9cfda05..b95d360 100644
--- a/src/dev/SConscript
+++ b/src/dev/SConscript
@@ -44,6 +44,7 @@

 SimObject('BadDevice.py')
 SimObject('Platform.py')
+SimObject('Serial.py')
 SimObject('Terminal.py')
 SimObject('Uart.py')

@@ -53,6 +54,7 @@
 Source('pixelpump.cc')
 Source('platform.cc')
 Source('ps2.cc')
+Source('serial.cc')
 Source('terminal.cc')
 Source('uart.cc')
 Source('uart8250.cc')
diff --git a/src/dev/Serial.py b/src/dev/Serial.py
new file mode 100644
index 000..b0bdc2c
--- /dev/null
+++ b/src/dev/Serial.py
@@ -0,0 +1,45 @@
+# Copyright (c) 2014, 2017 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Sandberg
+
+from m5.params import *
+from m5.proxy import *
+from m5.SimObject import SimObject
+
+class SerialDevice(SimObject):
+type = 'SerialDevice'
+abstract = True
+cxx_header = "dev/serial.hh"
diff --git a/src/dev/Terminal.py b/src/dev/Terminal.py
index 2b54f9d..9b50111 100644
--- a/src/dev/Terminal.py
+++ b/src/dev/Terminal.py
@@ -29,8 +29,9 @@
 from m5.SimObject import SimObject
 from m5.params import *
 from m5.proxy import *
+from Serial import SerialDevice

-class Terminal(SimObject):
+class Terminal(SerialDevice):
 type = 'Terminal'
 cxx_header = "dev/terminal.hh"
 intr_control = Param.IntrControl(Parent.any, "interrupt controller")
diff --git a/src/dev/Uart.py b/src/dev/Uart.py
index c3bc9dd..c3bfd1b 100644
--- a/src/dev/Uart.py
+++ b/src/dev/Uart.py
@@ -29,13 +29,14 @@
 from m5.params import *
 from m5.proxy import *
 from Device import BasicPioDevice
+from Serial import SerialDevice

 class Uart(BasicPioDevice):
 type = 'Uart'
 abstract = True
 cxx_header = "dev/uart.hh"
 platform = Param.Platform(Parent.any, 

[gem5-dev] Change in public/gem5[master]: dev: Move generic serial devices to src/dev/serial

[Andreas Sandberg (Gerrit)]

Hello Curtis Dunham,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/4291

to review the following change.


Change subject: dev: Move generic serial devices to src/dev/serial
..

dev: Move generic serial devices to src/dev/serial

Change-Id: I104227fc460f8b561e7375b329a541c1fce881b2
Signed-off-by: Andreas Sandberg 
Reviewed-by: Curtis Dunham 
---
M src/dev/SConscript
M src/dev/alpha/backdoor.cc
M src/dev/alpha/tsunami.cc
M src/dev/arm/gic_pl390.cc
M src/dev/arm/pl011.hh
M src/dev/arm/realview.cc
M src/dev/arm/vgic.cc
M src/dev/mips/malta.cc
C src/dev/serial/SConscript
R src/dev/serial/Serial.py
R src/dev/serial/Terminal.py
R src/dev/serial/Uart.py
R src/dev/serial/serial.cc
R src/dev/serial/serial.hh
R src/dev/serial/terminal.cc
R src/dev/serial/terminal.hh
R src/dev/serial/uart.cc
R src/dev/serial/uart.hh
R src/dev/serial/uart8250.cc
R src/dev/serial/uart8250.hh
M src/dev/sparc/t1000.cc
M src/dev/virtio/block.hh
M src/dev/virtio/console.hh
M src/dev/x86/pc.cc
24 files changed, 37 insertions(+), 49 deletions(-)



diff --git a/src/dev/SConscript b/src/dev/SConscript
index b95d360..6939e03 100644
--- a/src/dev/SConscript
+++ b/src/dev/SConscript
@@ -44,9 +44,6 @@

 SimObject('BadDevice.py')
 SimObject('Platform.py')
-SimObject('Serial.py')
-SimObject('Terminal.py')
-SimObject('Uart.py')

 Source('baddev.cc')
 Source('intel_8254_timer.cc')
@@ -54,13 +51,6 @@
 Source('pixelpump.cc')
 Source('platform.cc')
 Source('ps2.cc')
-Source('serial.cc')
-Source('terminal.cc')
-Source('uart.cc')
-Source('uart8250.cc')

 DebugFlag('Intel8254Timer')
 DebugFlag('MC146818')
-DebugFlag('Terminal')
-DebugFlag('TerminalVerbose')
-DebugFlag('Uart')
diff --git a/src/dev/alpha/backdoor.cc b/src/dev/alpha/backdoor.cc
index 5c627ca..bb65282 100644
--- a/src/dev/alpha/backdoor.cc
+++ b/src/dev/alpha/backdoor.cc
@@ -52,7 +52,7 @@
 #include "dev/alpha/tsunami_io.hh"
 #include "dev/platform.hh"
 #include "dev/storage/simple_disk.hh"
-#include "dev/terminal.hh"
+#include "dev/serial/terminal.hh"
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
 #include "mem/physical.hh"
diff --git a/src/dev/alpha/tsunami.cc b/src/dev/alpha/tsunami.cc
index 82a3812..30df89d 100644
--- a/src/dev/alpha/tsunami.cc
+++ b/src/dev/alpha/tsunami.cc
@@ -44,7 +44,6 @@
 #include "dev/alpha/tsunami_cchip.hh"
 #include "dev/alpha/tsunami_io.hh"
 #include "dev/alpha/tsunami_pchip.hh"
-#include "dev/terminal.hh"

 using namespace std;
 //Should this be AlphaISA?
diff --git a/src/dev/arm/gic_pl390.cc b/src/dev/arm/gic_pl390.cc
index d2ec1d7..4818be6 100644
--- a/src/dev/arm/gic_pl390.cc
+++ b/src/dev/arm/gic_pl390.cc
@@ -48,7 +48,6 @@
 #include "debug/GIC.hh"
 #include "debug/IPI.hh"
 #include "debug/Interrupt.hh"
-#include "dev/terminal.hh"
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"

diff --git a/src/dev/arm/pl011.hh b/src/dev/arm/pl011.hh
index d6c839c..2317b31 100644
--- a/src/dev/arm/pl011.hh
+++ b/src/dev/arm/pl011.hh
@@ -50,7 +50,7 @@
 #define __DEV_ARM_PL011_H__

 #include "dev/arm/amba_device.hh"
-#include "dev/uart.hh"
+#include "dev/serial/uart.hh"

 class BaseGic;
 struct Pl011Params;
diff --git a/src/dev/arm/realview.cc b/src/dev/arm/realview.cc
index e5e7afd..8524b23 100644
--- a/src/dev/arm/realview.cc
+++ b/src/dev/arm/realview.cc
@@ -53,7 +53,6 @@
 #include "config/the_isa.hh"
 #include "cpu/intr_control.hh"
 #include "dev/arm/base_gic.hh"
-#include "dev/terminal.hh"
 #include "sim/system.hh"

 using namespace std;
diff --git a/src/dev/arm/vgic.cc b/src/dev/arm/vgic.cc
index cc8ad77..5295204 100644
--- a/src/dev/arm/vgic.cc
+++ b/src/dev/arm/vgic.cc
@@ -43,7 +43,6 @@
 #include "debug/Checkpoint.hh"
 #include "debug/VGIC.hh"
 #include "dev/arm/base_gic.hh"
-#include "dev/terminal.hh"
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"

diff --git a/src/dev/mips/malta.cc b/src/dev/mips/malta.cc
index 8843d4b..a259047 100755
--- a/src/dev/mips/malta.cc
+++ b/src/dev/mips/malta.cc
@@ -44,7 +44,6 @@
 #include "debug/Malta.hh"
 #include "dev/mips/malta_cchip.hh"
 #include "dev/mips/malta_io.hh"
-#include "dev/terminal.hh"
 #include "params/Malta.hh"
 #include "sim/system.hh"

diff --git a/src/dev/Serial.py b/src/dev/serial/SConscript
similarity index 82%
copy from src/dev/Serial.py
copy to src/dev/serial/SConscript
index 0e653ad..b9f13f5 100644
--- a/src/dev/Serial.py
+++ b/src/dev/serial/SConscript
@@ -1,4 +1,6 @@
-# Copyright (c) 2014, 2017 ARM Limited
+# -*- mode:python -*-
+
+# Copyright (c) 2017 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -10,6 +12,9 @@
 # unmodified and in its entirety in all distributions of the software,
 # modified or unmodified, in source code or in binary form.
 #
+# Copyright (c) 2006 The Regents of The University of Michigan
+# All rights reserved.
+#
 # 

[gem5-dev] Change in public/gem5[master]: kvm, arm: Switch to the device EQ when accessing ISA devices

[Andreas Sandberg (Gerrit)]

Hello Nikos Nikoleris,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/4288

to review the following change.


Change subject: kvm, arm: Switch to the device EQ when accessing ISA devices
..

kvm, arm: Switch to the device EQ when accessing ISA devices

ISA devices typically run in the device event queue. Previously, we
assumed that devices would perform their own EQ migrations as
needed. This isn't ideal since it means we have different conventions
for IO devices and ISA devices. Switch to doing migrations in the KVM
CPU instead to make the behavior consistent.

Change-Id: I33b74480fb2126b0786dbdbfdcfa86083384250c
Signed-off-by: Andreas Sandberg 
Reviewed-by: Nikos Nikoleris 
---
M src/arch/arm/kvm/armv8_cpu.cc
M src/dev/arm/generic_timer.cc
2 files changed, 18 insertions(+), 13 deletions(-)



diff --git a/src/arch/arm/kvm/armv8_cpu.cc b/src/arch/arm/kvm/armv8_cpu.cc
index db2b9c0..209f49e 100644
--- a/src/arch/arm/kvm/armv8_cpu.cc
+++ b/src/arch/arm/kvm/armv8_cpu.cc
@@ -260,7 +260,17 @@
 }

 for (const auto  : getSysRegMap()) {
-const uint64_t value(tc->readMiscReg(ri.idx));
+uint64_t value;
+if (ri.is_device) {
+// This system register is backed by a device. This means
+// we need to lock the device event queue.
+EventQueue::ScopedMigration migrate(deviceEventQueue());
+
+value = tc->readMiscReg(ri.idx);
+} else {
+value = tc->readMiscReg(ri.idx);
+}
+
 DPRINTF(KvmContext, "  %s := 0x%x\n", ri.name, value);
 setOneReg(ri.kvm, value);
 }
@@ -323,10 +333,15 @@
 for (const auto  : getSysRegMap()) {
 const auto value(getOneRegU64(ri.kvm));
 DPRINTF(KvmContext, "  %s := 0x%x\n", ri.name, value);
-if (ri.is_device)
+if (ri.is_device) {
+// This system register is backed by a device. This means
+// we need to lock the device event queue.
+EventQueue::ScopedMigration migrate(deviceEventQueue());
+
 tc->setMiscReg(ri.idx, value);
-else
+} else {
 tc->setMiscRegNoEffect(ri.idx, value);
+}
 }

 PCState pc(getOneRegU64(INT_REG(regs.pc)));
diff --git a/src/dev/arm/generic_timer.cc b/src/dev/arm/generic_timer.cc
index 6332b8f..3508674 100644
--- a/src/dev/arm/generic_timer.cc
+++ b/src/dev/arm/generic_timer.cc
@@ -318,11 +318,6 @@
 void
 GenericTimer::setMiscReg(int reg, unsigned cpu, MiscReg val)
 {
-// This method might have been called from another context if we
-// are running in multi-core KVM. Migrate to the SimObject's event
-// queue to prevent surprising race conditions.
-EventQueue::ScopedMigration migrate(eventQueue());
-
 CoreTimers (getTimers(cpu));

 switch (reg) {
@@ -415,11 +410,6 @@
 MiscReg
 GenericTimer::readMiscReg(int reg, unsigned cpu)
 {
-// This method might have been called from another context if we
-// are running in multi-core KVM. Migrate to the SimObject's event
-// queue to prevent surprising race conditions.
-EventQueue::ScopedMigration migrate(eventQueue());
-
 CoreTimers (getTimers(cpu));

 switch (reg) {

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[gem5-dev] Change in public/gem5[master]: kvm: Add a helper method to access device event queues

[Andreas Sandberg (Gerrit)]

Hello Nikos Nikoleris,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/4287

to review the following change.


Change subject: kvm: Add a helper method to access device event queues
..

kvm: Add a helper method to access device event queues

The VM's event queue is normally used for devices in multi-core KVM
mode. Add a helper method, BaseKvmCPU::deviceEventQueue(), to access
this queue. This makes the intention of code migrating to device event
queues clearer.

Change-Id: Ifb10f553a6d7445c8d562f658cf9d0b1f4c577ff
Signed-off-by: Andreas Sandberg 
Reviewed-by: Nikos Nikoleris 
---
M src/cpu/kvm/base.cc
M src/cpu/kvm/base.hh
M src/cpu/kvm/x86_cpu.cc
3 files changed, 16 insertions(+), 8 deletions(-)



diff --git a/src/cpu/kvm/base.cc b/src/cpu/kvm/base.cc
index 6ea99ce..d0f7515 100644
--- a/src/cpu/kvm/base.cc
+++ b/src/cpu/kvm/base.cc
@@ -1147,10 +1147,9 @@
 delete pkt;
 return clockPeriod() * ipr_delay;
 } else {
-// Temporarily lock and migrate to the event queue of the
-// VM. This queue is assumed to "own" all devices we need to
-// access if running in multi-core mode.
-EventQueue::ScopedMigration migrate(vm.eventQueue());
+// Temporarily lock and migrate to the device event queue to
+// prevent races in multi-core mode.
+EventQueue::ScopedMigration migrate(deviceEventQueue());

 return dataPort.submitIO(pkt);
 }
diff --git a/src/cpu/kvm/base.hh b/src/cpu/kvm/base.hh
index 29872e7..a22637f 100644
--- a/src/cpu/kvm/base.hh
+++ b/src/cpu/kvm/base.hh
@@ -419,6 +419,16 @@
 void syncThreadContext();

 /**
+ * Get a pointer to the event queue owning devices.
+ *
+ * Devices always live in a separate device event queue when
+ * running in multi-core mode. We need to temporarily migrate to
+ * this queue when accessing devices. By convention, devices and
+ * the VM use the same event queue.
+ */
+EventQueue *deviceEventQueue() { return vm.eventQueue(); }
+
+/**
  * Update the KVM if the thread context is dirty.
  */
 void syncKvmState();
diff --git a/src/cpu/kvm/x86_cpu.cc b/src/cpu/kvm/x86_cpu.cc
index bdbdadf..467e1ba 100644
--- a/src/cpu/kvm/x86_cpu.cc
+++ b/src/cpu/kvm/x86_cpu.cc
@@ -1346,10 +1346,9 @@
 }

 const MemCmd cmd(isWrite ? MemCmd::WriteReq : MemCmd::ReadReq);
-// Temporarily lock and migrate to the event queue of the
-// VM. This queue is assumed to "own" all devices we need to
-// access if running in multi-core mode.
-EventQueue::ScopedMigration migrate(vm.eventQueue());
+// Temporarily lock and migrate to the device event queue to
+// prevent races in multi-core mode.
+EventQueue::ScopedMigration migrate(deviceEventQueue());
 for (int i = 0; i < count; ++i) {
 RequestPtr io_req = new Request(pAddr, kvm_run.io.size,
 Request::UNCACHEABLE,  
dataMasterId());


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[gem5-dev] Change in public/gem5[master]: cpu, kvm: Fix deadlock issue when resuming a drained system

[Andreas Sandberg (Gerrit)]

Hello Nikos Nikoleris, Curtis Dunham,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/4286

to review the following change.


Change subject: cpu, kvm: Fix deadlock issue when resuming a drained system
..

cpu, kvm: Fix deadlock issue when resuming a drained system

The KVM CPU sometimes needs to access devices when drain() is
called. This typically happens on ARM when synchronizing devices that
use the system register interface. When called from drain(), the event
queue isn't locked since drain is called from the outside when the
simulator isn't servicing any events. In such cases, performing a
migration to the device's queue will unlock a mutex that isn't
locked. This typically results in a deadlock when resuming the system
since the lock will be in an undefined state.

Change-Id: Ibdcc2e034e916a929124f297e72aae306cf66728
Signed-off-by: Andreas Sandberg 
Reviewed-by: Nikos Nikoleris 
Reviewed-by: Curtis Dunham 
---
M src/cpu/kvm/base.cc
1 file changed, 7 insertions(+), 0 deletions(-)



diff --git a/src/cpu/kvm/base.cc b/src/cpu/kvm/base.cc
index 250c6a2..6ea99ce 100644
--- a/src/cpu/kvm/base.cc
+++ b/src/cpu/kvm/base.cc
@@ -358,6 +358,13 @@
 return DrainState::Drained;

 DPRINTF(Drain, "BaseKvmCPU::drain\n");
+
+// The event queue won't be locked when calling drain since that's
+// not done from an event. Lock the event queue here to make sure
+// that scoped migrations continue to work if we need to
+// synchronize the thread context.
+std::lock_guard lock(*this->eventQueue());
+
 switch (_status) {
   case Running:
 // The base KVM code is normally ready when it is in the

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[gem5-dev] Change in public/gem5[master]: arch-arm: Only increment SW PMU counters on writes to PMSWINC

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/4285



Change subject: arch-arm: Only increment SW PMU counters on writes to  
PMSWINC

..

arch-arm: Only increment SW PMU counters on writes to PMSWINC

When writing a bitmask of counters to PMSWINC, the PMU currently
increments the corresponding counters regardless of what they are
configured to count. According to the ARM ARM (D5.10.4), counters
should only be updated if they have been configured to count
software events (event type 0).

Change-Id: I5b2bc1fae55faa342b863721c9838342442831a9
Reviewed-by: Andreas Sandberg 
---
M src/arch/arm/pmu.cc
1 file changed, 3 insertions(+), 1 deletion(-)



diff --git a/src/arch/arm/pmu.cc b/src/arch/arm/pmu.cc
index 14b1b50..f1ff6cb 100644
--- a/src/arch/arm/pmu.cc
+++ b/src/arch/arm/pmu.cc
@@ -147,8 +147,10 @@
   case MISCREG_PMSWINC:
 for (int i = 0; i < counters.size(); ++i) {
 CounterState (getCounter(i));
-if (ctr.enabled && (val & (1 << i)))
+if (ctr.enabled && (val & (1 << i))
+&& ctr.eventId == ARCH_EVENT_SW_INCR ) {
 ++ctr.value;
+}
 }
 break;


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[gem5-dev] Change in public/gem5[master]: arch-x86: Add missing override in the X86 TLB

[Andreas Sandberg (Gerrit)]

Hello Nikos Nikoleris,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/4283

to review the following change.


Change subject: arch-x86: Add missing override in the X86 TLB
..

arch-x86: Add missing override in the X86 TLB

Change-Id: Ie5ef1aaaef46cf8ef8fa4b0fc8f7efb8cde9b489
Signed-off-by: Andreas Sandberg 
Reviewed-by: Nikos Nikoleris 
---
M src/arch/x86/tlb.hh
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh
index 09cd6ed..d036b74 100644
--- a/src/arch/x86/tlb.hh
+++ b/src/arch/x86/tlb.hh
@@ -151,7 +151,7 @@
 /*
  * Function to register Stats
  */
-void regStats();
+void regStats() override;

 // Checkpointing
 void serialize(CheckpointOut ) const override;

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[gem5-dev] Change in public/gem5[master]: python: Make GlobalExitEvent.getCode() return an int

[Andreas Sandberg (Gerrit)]

Hello Curtis Dunham,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/4280

to review the following change.


Change subject: python: Make GlobalExitEvent.getCode() return an int
..

python: Make GlobalExitEvent.getCode() return an int

PyBind normally casts integers returned from the C to long in
Python. This is normally fine since long in most cases behaves just
like an int. However, when passing the return value from getcode() to
sys.exit, unexpected behavior ensues. Due to the way the function is
defined, any type other than int (with the exception of None) will be
treated as an error and be equivalent to sys.exit(1).

Since we frequently use the sys.exit(event.getCode()) pattern, we need
to ensure that the function returns an integer. This change adds an
explicit type conversion to a Python integer in the wrapper code.

Change-Id: I73d6b881025064afa2b2e6eb4512fa2a4b0a87da
Signed-off-by: Andreas Sandberg 
Reviewed-by: Jose Marinho 
Reviewed-by: Curtis Dunham 
---
M src/python/pybind11/event.cc
1 file changed, 4 insertions(+), 1 deletion(-)



diff --git a/src/python/pybind11/event.cc b/src/python/pybind11/event.cc
index f9e6568..88ee699 100644
--- a/src/python/pybind11/event.cc
+++ b/src/python/pybind11/event.cc
@@ -135,7 +135,10 @@
std::unique_ptr>(
m, "GlobalSimLoopExitEvent")
 .def("getCause", ::getCause)
-.def("getCode", ::getCode)
+.def("getCode", [](GlobalSimLoopExitEvent *e) {
+return py::reinterpret_steal(
+PyInt_FromLong(e->getCode()));
+})
 ;

 // Event base class. These should never be returned directly to

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[gem5-dev] Change in public/gem5[master]: arch-arm: Add missing override keywords in fault.hh

[Andreas Sandberg (Gerrit)]

Hello Nikos Nikoleris,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/4284

to review the following change.


Change subject: arch-arm: Add missing override keywords in fault.hh
..

arch-arm: Add missing override keywords in fault.hh

Change-Id: I94a4bf4a633aeed550f8c01ccae824add3b85eb0
Signed-off-by: Andreas Sandberg 
Reviewed-by: Nikos Nikoleris 
---
M src/arch/arm/faults.hh
1 file changed, 67 insertions(+), 63 deletions(-)



diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh
index 6e7c92c..8d72dee 100644
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -183,7 +183,7 @@
 MiscRegIndex getFaultAddrReg64() const;

 void invoke(ThreadContext *tc, const StaticInstPtr  =
-StaticInst::nullStaticInstPtr);
+StaticInst::nullStaticInstPtr) override;
 void invoke64(ThreadContext *tc, const StaticInstPtr  =
   StaticInst::nullStaticInstPtr);
 virtual void annotate(AnnotationIDs id, uint64_t val) {}
@@ -215,13 +215,11 @@
   public:
 ArmFaultVals(ExtMachInst _machInst = 0, uint32_t _iss = 0) :
 ArmFault(_machInst, _iss) {}
-FaultName name() const { return vals.name; }
-FaultStat & countStat() { return vals.count; }
-FaultOffset offset(ThreadContext *tc);
+FaultName name() const override { return vals.name; }
+FaultStat & countStat() override { return vals.count; }
+FaultOffset offset(ThreadContext *tc) override;

-FaultOffset
-offset64()
-{
+FaultOffset offset64() override {
 if (toEL == fromEL) {
 if (opModeIsT(fromMode))
 return vals.currELTOffset;
@@ -233,25 +231,31 @@
 }
 }

-OperatingMode nextMode() { return vals.nextMode; }
-virtual bool routeToMonitor(ThreadContext *tc) const { return false; }
-uint8_t armPcOffset(bool isHyp)   { return isHyp ? vals.armPcElrOffset
- : vals.armPcOffset; }
-uint8_t thumbPcOffset(bool isHyp) { return isHyp ?  
vals.thumbPcElrOffset
- : vals.thumbPcOffset;  
}

-uint8_t armPcElrOffset() { return vals.armPcElrOffset; }
-uint8_t thumbPcElrOffset() { return vals.thumbPcElrOffset; }
-virtual bool abortDisable(ThreadContext* tc) { return  
vals.abortDisable; }

-virtual bool fiqDisable(ThreadContext* tc) { return vals.fiqDisable; }
-virtual ExceptionClass ec(ThreadContext *tc) const { return vals.ec; }
-virtual uint32_t iss() const { return issRaw; }
+OperatingMode nextMode() override { return vals.nextMode; }
+virtual bool routeToMonitor(ThreadContext *tc) const override {
+return false;
+}
+uint8_t armPcOffset(bool isHyp) override {
+return isHyp ? vals.armPcElrOffset
+ : vals.armPcOffset;
+}
+uint8_t thumbPcOffset(bool isHyp) override {
+return isHyp ? vals.thumbPcElrOffset
+ : vals.thumbPcOffset;
+}
+uint8_t armPcElrOffset() override { return vals.armPcElrOffset; }
+uint8_t thumbPcElrOffset() override { return vals.thumbPcElrOffset; }
+bool abortDisable(ThreadContext* tc) override { return  
vals.abortDisable; }

+bool fiqDisable(ThreadContext* tc) override { return vals.fiqDisable; }
+ExceptionClass ec(ThreadContext *tc) const override { return vals.ec; }
+uint32_t iss() const override { return issRaw; }
 };

 class Reset : public ArmFaultVals
 {
   public:
 void invoke(ThreadContext *tc, const StaticInstPtr  =
-StaticInst::nullStaticInstPtr);
+StaticInst::nullStaticInstPtr) override;
 };

 class UndefinedInstruction : public ArmFaultVals
@@ -279,10 +283,10 @@
 {}

 void invoke(ThreadContext *tc, const StaticInstPtr  =
-StaticInst::nullStaticInstPtr);
-bool routeToHyp(ThreadContext *tc) const;
-ExceptionClass ec(ThreadContext *tc) const;
-uint32_t iss() const;
+StaticInst::nullStaticInstPtr) override;
+bool routeToHyp(ThreadContext *tc) const override;
+ExceptionClass ec(ThreadContext *tc) const override;
+uint32_t iss() const override;
 };

 class SupervisorCall : public ArmFaultVals
@@ -297,10 +301,10 @@
 {}

 void invoke(ThreadContext *tc, const StaticInstPtr  =
-StaticInst::nullStaticInstPtr);
-bool routeToHyp(ThreadContext *tc) const;
-ExceptionClass ec(ThreadContext *tc) const;
-uint32_t iss() const;
+StaticInst::nullStaticInstPtr) override;
+bool routeToHyp(ThreadContext *tc) const override;
+ExceptionClass ec(ThreadContext *tc) const override;
+uint32_t iss() const override;
 };

 class SecureMonitorCall : public ArmFaultVals
@@ -311,9 +315,9 @@
 {}

 void invoke(ThreadContext *tc, const StaticInstPtr  =
-  

[gem5-dev] Change in public/gem5[master]: arch-alpha: Add missing overrides

[Andreas Sandberg (Gerrit)]

Hello Nikos Nikoleris,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/4281

to review the following change.


Change subject: arch-alpha: Add missing overrides
..

arch-alpha: Add missing overrides

Change-Id: I3a52fcdb449c7df1612466270aa2c9b0a0f3afef
Reviewed-by: Nikos Nikoleris 
---
M src/arch/alpha/remote_gdb.hh
1 file changed, 3 insertions(+), 3 deletions(-)



diff --git a/src/arch/alpha/remote_gdb.hh b/src/arch/alpha/remote_gdb.hh
index 38ff919..c8ed709 100644
--- a/src/arch/alpha/remote_gdb.hh
+++ b/src/arch/alpha/remote_gdb.hh
@@ -50,8 +50,8 @@
 {
   protected:
 // Machine memory
-bool acc(Addr addr, size_t len);
-bool write(Addr addr, size_t size, const char *data);
+bool acc(Addr addr, size_t len) override;
+bool write(Addr addr, size_t size, const char *data) override;

 void insertHardBreak(Addr addr, size_t len) override;

@@ -75,7 +75,7 @@

   public:
 RemoteGDB(System *system, ThreadContext *context);
-BaseGdbRegCache *gdbRegs();
+BaseGdbRegCache *gdbRegs() override;
 };

 } // namespace AlphaISA

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[gem5-dev] Change in public/gem5[master]: arch-sparc: Add a FaultVals instantiation for VecDisabled

[Andreas Sandberg (Gerrit)]

Hello Nikos Nikoleris,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/4282

to review the following change.


Change subject: arch-sparc: Add a FaultVals instantiation for VecDisabled
..

arch-sparc: Add a FaultVals instantiation for VecDisabled

Recent gcc versions complain about a missing VecDisabled not having an
explicit FaultVals instantiation.

Change-Id: I439e7b3a7d5cad20590f52b3f374ead3f3f070a6
Signed-off-by: Andreas Sandberg 
Reviewed-by: Nikos Nikoleris 
---
M src/arch/sparc/faults.hh
1 file changed, 1 insertion(+), 0 deletions(-)



diff --git a/src/arch/sparc/faults.hh b/src/arch/sparc/faults.hh
index aa270fa..86f8c5b 100644
--- a/src/arch/sparc/faults.hh
+++ b/src/arch/sparc/faults.hh
@@ -294,6 +294,7 @@
 template<> SparcFaultBase::FaultVals SparcFault::vals;
 template<> SparcFaultBase::FaultVals SparcFault::vals;
 template<> SparcFaultBase::FaultVals SparcFault::vals;
+template<> SparcFaultBase::FaultVals SparcFault::vals;
 template<> SparcFaultBase::FaultVals SparcFault::vals;
 template<> SparcFaultBase::FaultVals SparcFault::vals;
 template<> SparcFaultBase::FaultVals SparcFault::vals;

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[gem5-dev] Change in public/gem5[master]: util: Move m5op.h to the shared include directory

[Andreas Sandberg (Gerrit)]

Hello Gabe Black, Jason Lowe-Power,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/4265

to look at the new patch set (#2).

Change subject: util: Move m5op.h to the shared include directory
..

util: Move m5op.h to the shared include directory

The header file with C declarations for m5ops is sometimes needed by
code outside of the util/m5 directory. Move this file to the shared
include directory and factor out flags to a generic asm header. Note
that applications that need to call m5ops still need to link with
libm5.a or implement their own trampolines.

Change-Id: I36a3f459ed71593e38b869dc2b1302c810f92276
Signed-off-by: Andreas Sandberg 
Reviewed-by: Jose Marinho 
---
A include/gem5/asm/generic/m5op_flags.h
M include/gem5/asm/generic/m5ops.h
R include/gem5/m5ops.h
M util/m5/m5.c
4 files changed, 62 insertions(+), 9 deletions(-)


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[gem5-dev] Change in public/gem5[master]: config: Discover CPU timing models based on target ISA

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/3947 )


Change subject: config: Discover CPU timing models based on target ISA
..

config: Discover CPU timing models based on target ISA

The CpuConfig helper currently assumes that all timing models live in
the cores.arm package. This ignores the potential mismatch between the
target ISA and the ISA assumptions made by the timing models.

Instead of unconditionally listing all CPU models in cores.arm, list
timing models from cores.generic and cores.${TARGET_ISA}. This ensures
that the listed timing models support the ISA that gem5 is targeting.

Change-Id: If6235af2118889638f56ac4151003f38edfe9485
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/3947
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M configs/common/CpuConfig.py
1 file changed, 13 insertions(+), 4 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved



diff --git a/configs/common/CpuConfig.py b/configs/common/CpuConfig.py
index 731ba4f..327c431 100644
--- a/configs/common/CpuConfig.py
+++ b/configs/common/CpuConfig.py
@@ -114,7 +114,16 @@
 for name, cls in inspect.getmembers(m5.objects, is_cpu_class):
 _cpu_classes[name] = cls

-import cores.arm
-for mod_name, module in inspect.getmembers(cores.arm, inspect.ismodule):
-for name, cls in inspect.getmembers(module, is_cpu_class):
-_cpu_classes[name] = cls
+
+from m5.defines import buildEnv
+from importlib import import_module
+for package in [ "generic", buildEnv['TARGET_ISA']]:
+try:
+package = import_module(".cores." + package, package=__package__)
+except ImportError:
+# No timing models for this ISA
+continue
+
+for mod_name, module in inspect.getmembers(package, inspect.ismodule):
+for name, cls in inspect.getmembers(module, is_cpu_class):
+_cpu_classes[name] = cls

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Gerrit-Change-Number: 3947
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[gem5-dev] Change in public/gem5[master]: util: Move m5op.h to the shared include directory

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/4265



Change subject: util: Move m5op.h to the shared include directory
..

util: Move m5op.h to the shared include directory

The header file with C declarations for m5ops is sometimes needed by
code outside of the util/m5 directory. Move this file to the shared
include directory. Note that code that needs to call m5ops still need
to link with libm5.a or implement their own trampolines.

Change-Id: I36a3f459ed71593e38b869dc2b1302c810f92276
Signed-off-by: Andreas Sandberg 
Reviewed-by: Jose Marinho 
---
R include/gem5/m5ops.h
M util/m5/m5.c
2 files changed, 4 insertions(+), 4 deletions(-)



diff --git a/util/m5/m5op.h b/include/gem5/m5ops.h
similarity index 97%
rename from util/m5/m5op.h
rename to include/gem5/m5ops.h
index 3a507e1..61dfa23 100644
--- a/util/m5/m5op.h
+++ b/include/gem5/m5ops.h
@@ -29,8 +29,8 @@
  *  Ali Saidi
  */

-#ifndef __M5OP_H__
-#define __M5OP_H__
+#ifndef __GEM5_M5OP_H__
+#define __GEM5_M5OP_H__

 #ifdef __cplusplus
 extern "C" {
@@ -90,4 +90,4 @@
 #ifdef __cplusplus
 }
 #endif
-#endif // __M5OP_H__
+#endif // __GEM5_M5OP_H__
diff --git a/util/m5/m5.c b/util/m5/m5.c
index 5b6c7a6..82ef73b 100644
--- a/util/m5/m5.c
+++ b/util/m5/m5.c
@@ -57,7 +57,7 @@
 #include 
 #include 

-#include "m5op.h"
+#include 

 void *m5_mem = NULL;


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[gem5-dev] Change in public/gem5[master]: arch-arm: Use named constants for m5op instructions

[Andreas Sandberg (Gerrit)]

Hello Nikos Nikoleris,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/4263

to review the following change.


Change subject: arch-arm: Use named constants for m5op instructions
..

arch-arm: Use named constants for m5op instructions

Change-Id: I544519c4f87e50cc02af29cbb3edc31ecf726e8e
Signed-off-by: Andreas Sandberg 
Reviewed-by: Nikos Nikoleris 
---
M src/arch/arm/isa/formats/aarch64.isa
M src/arch/arm/isa/formats/m5ops.isa
M src/arch/arm/isa/includes.isa
3 files changed, 55 insertions(+), 52 deletions(-)



diff --git a/src/arch/arm/isa/formats/aarch64.isa  
b/src/arch/arm/isa/formats/aarch64.isa

index 1252cdf..38e5b15 100644
--- a/src/arch/arm/isa/formats/aarch64.isa
+++ b/src/arch/arm/isa/formats/aarch64.isa
@@ -2002,32 +2002,32 @@
 {
 const uint32_t m5func = bits(machInst, 23, 16);
 switch (m5func) {
-  case 0x00: return new Arm(machInst);
-  case 0x01: return new Quiesce(machInst);
-  case 0x02: return new QuiesceNs64(machInst);
-  case 0x03: return new QuiesceCycles64(machInst);
-  case 0x04: return new QuiesceTime64(machInst);
-  case 0x07: return new Rpns64(machInst);
-  case 0x09: return new WakeCPU64(machInst);
-  case 0x10: return new Deprecated_ivlb(machInst);
-  case 0x11: return new Deprecated_ivle(machInst);
-  case 0x20: return new Deprecated_exit (machInst);
-  case 0x21: return new M5exit64(machInst);
-  case 0x22: return new M5fail64(machInst);
-  case 0x31: return new Loadsymbol(machInst);
-  case 0x30: return new Initparam64(machInst);
-  case 0x40: return new Resetstats64(machInst);
-  case 0x41: return new Dumpstats64(machInst);
-  case 0x42: return new Dumpresetstats64(machInst);
-  case 0x43: return new M5checkpoint64(machInst);
-  case 0x4F: return new M5writefile64(machInst);
-  case 0x50: return new M5readfile64(machInst);
-  case 0x51: return new M5break(machInst);
-  case 0x52: return new M5switchcpu(machInst);
-  case 0x53: return new M5addsymbol64(machInst);
-  case 0x54: return new M5panic(machInst);
-  case 0x5a: return new M5workbegin64(machInst);
-  case 0x5b: return new M5workend64(machInst);
+  case M5OP_ARM: return new Arm(machInst);
+  case M5OP_QUIESCE: return new Quiesce(machInst);
+  case M5OP_QUIESCE_NS: return new QuiesceNs64(machInst);
+  case M5OP_QUIESCE_CYCLE: return new QuiesceCycles64(machInst);
+  case M5OP_QUIESCE_TIME: return new QuiesceTime64(machInst);
+  case M5OP_RPNS: return new Rpns64(machInst);
+  case M5OP_WAKE_CPU: return new WakeCPU64(machInst);
+  case M5OP_DEPRECATED1: return new Deprecated_ivlb(machInst);
+  case M5OP_DEPRECATED2: return new Deprecated_ivle(machInst);
+  case M5OP_DEPRECATED3: return new Deprecated_exit (machInst);
+  case M5OP_EXIT: return new M5exit64(machInst);
+  case M5OP_FAIL: return new M5fail64(machInst);
+  case M5OP_LOAD_SYMBOL: return new Loadsymbol(machInst);
+  case M5OP_INIT_PARAM: return new Initparam64(machInst);
+  case M5OP_RESET_STATS: return new Resetstats64(machInst);
+  case M5OP_DUMP_STATS: return new Dumpstats64(machInst);
+  case M5OP_DUMP_RESET_STATS: return new  
Dumpresetstats64(machInst);

+  case M5OP_CHECKPOINT: return new M5checkpoint64(machInst);
+  case M5OP_WRITE_FILE: return new M5writefile64(machInst);
+  case M5OP_READ_FILE: return new M5readfile64(machInst);
+  case M5OP_DEBUG_BREAK: return new M5break(machInst);
+  case M5OP_SWITCH_CPU: return new M5switchcpu(machInst);
+  case M5OP_ADD_SYMBOL: return new M5addsymbol64(machInst);
+  case M5OP_PANIC: return new M5panic(machInst);
+  case M5OP_WORK_BEGIN: return new M5workbegin64(machInst);
+  case M5OP_WORK_END: return new M5workend64(machInst);
   default: return new Unknown64(machInst);
 }
 }
diff --git a/src/arch/arm/isa/formats/m5ops.isa  
b/src/arch/arm/isa/formats/m5ops.isa

index 26210af..d3db813 100644
--- a/src/arch/arm/isa/formats/m5ops.isa
+++ b/src/arch/arm/isa/formats/m5ops.isa
@@ -42,32 +42,32 @@
 {
 const uint32_t m5func = bits(machInst, 23, 16);
 switch(m5func) {
-case 0x00: return new Arm(machInst);
-case 0x01: return new Quiesce(machInst);
-case 0x02: return new QuiesceNs(machInst);
-case 0x03: return new QuiesceCycles(machInst);
-case 0x04: return new QuiesceTime(machInst);
-case 0x07: return new Rpns(machInst);
-case 0x09: return new WakeCPU(machInst);
-case 0x10: return new 

[gem5-dev] Change in public/gem5[master]: sim: Use named constants for pseudo ops

[Andreas Sandberg (Gerrit)]

Hello Nikos Nikoleris,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/4262

to review the following change.


Change subject: sim: Use named constants for pseudo ops
..

sim: Use named constants for pseudo ops

Use named constants from a shared header instead of magic values when
handling pseudo ops.

Change-Id: If157060bbcd772ce7e8556482b44ca714f4319b1
Signed-off-by: Andreas Sandberg 
Reviewed-by: Nikos Nikoleris 
---
M SConstruct
M src/sim/pseudo_inst.cc
2 files changed, 39 insertions(+), 34 deletions(-)



diff --git a/SConstruct b/SConstruct
index 146b156..e4880e1 100755
--- a/SConstruct
+++ b/SConstruct
@@ -554,6 +554,9 @@
 # the ext directory should be on the #includes path
 main.Append(CPPPATH=[Dir('ext')])

+# Add shared top-level headers
+main.Prepend(CPPPATH=Dir('include'))
+
 def strip_build_path(path, env):
 path = str(path)
 variant_base = env['BUILDROOT'] + os.path.sep
diff --git a/src/sim/pseudo_inst.cc b/src/sim/pseudo_inst.cc
index 778675f..dc37a8c 100644
--- a/src/sim/pseudo_inst.cc
+++ b/src/sim/pseudo_inst.cc
@@ -51,6 +51,8 @@
 #include 
 #include 

+#include 
+
 #include "arch/kernel_stats.hh"
 #include "arch/pseudo_inst.hh"
 #include "arch/utility.hh"
@@ -109,111 +111,111 @@
 }

 switch (func) {
-  case 0x00: // arm_func
+  case M5OP_ARM:
 arm(tc);
 break;

-  case 0x01: // quiesce_func
+  case M5OP_QUIESCE:
 quiesce(tc);
 break;

-  case 0x02: // quiescens_func
-quiesceSkip(tc);
-break;
-
-  case 0x03: // quiescecycle_func
+  case M5OP_QUIESCE_NS:
 quiesceNs(tc, args[0]);
 break;

-  case 0x04: // quiescetime_func
+  case M5OP_QUIESCE_CYCLE:
+quiesceCycles(tc, args[0]);
+break;
+
+  case M5OP_QUIESCE_TIME:
 return quiesceTime(tc);

-  case 0x07: // rpns_func
+  case M5OP_RPNS:
 return rpns(tc);

-  case 0x09: // wakecpu_func
+  case M5OP_WAKE_CPU:
 wakeCPU(tc, args[0]);
 break;

-  case 0x21: // exit_func
+  case M5OP_EXIT:
 m5exit(tc, args[0]);
 break;

-  case 0x22:
+  case M5OP_FAIL:
 m5fail(tc, args[0], args[1]);
 break;

-  case 0x30: // initparam_func
+  case M5OP_INIT_PARAM:
 return initParam(tc, args[0], args[1]);

-  case 0x31: // loadsymbol_func
+  case M5OP_LOAD_SYMBOL:
 loadsymbol(tc);
 break;

-  case 0x40: // resetstats_func
+  case M5OP_RESET_STATS:
 resetstats(tc, args[0], args[1]);
 break;

-  case 0x41: // dumpstats_func
+  case M5OP_DUMP_STATS:
 dumpstats(tc, args[0], args[1]);
 break;

-  case 0x42: // dumprststats_func
+  case M5OP_DUMP_RESET_STATS:
 dumpresetstats(tc, args[0], args[1]);
 break;

-  case 0x43: // ckpt_func
+  case M5OP_CHECKPOINT:
 m5checkpoint(tc, args[0], args[1]);
 break;

-  case 0x4f: // writefile_func
+  case M5OP_WRITE_FILE:
 return writefile(tc, args[0], args[1], args[2], args[3]);

-  case 0x50: // readfile_func
+  case M5OP_READ_FILE:
 return readfile(tc, args[0], args[1], args[2]);

-  case 0x51: // debugbreak_func
+  case M5OP_DEBUG_BREAK:
 debugbreak(tc);
 break;

-  case 0x52: // switchcpu_func
+  case M5OP_SWITCH_CPU:
 switchcpu(tc);
 break;

-  case 0x53: // addsymbol_func
+  case M5OP_ADD_SYMBOL:
 addsymbol(tc, args[0], args[1]);
 break;

-  case 0x54: // panic_func
+  case M5OP_PANIC:
 panic("M5 panic instruction called at %s\n", tc->pcState());

-  case 0x5a: // work_begin_func
+  case M5OP_WORK_BEGIN:
 workbegin(tc, args[0], args[1]);
 break;

-  case 0x5b: // work_end_func
+  case M5OP_WORK_END:
 workend(tc, args[0], args[1]);
 break;

-  case 0x55: // annotate_func
-  case 0x56: // reserved2_func
-  case 0x57: // reserved3_func
-  case 0x58: // reserved4_func
-  case 0x59: // reserved5_func
+  case M5OP_ANNOTATE:
+  case M5OP_RESERVED2:
+  case M5OP_RESERVED3:
+  case M5OP_RESERVED4:
+  case M5OP_RESERVED5:
 warn("Unimplemented m5 op (0x%x)\n", func);
 break;

   /* SE mode functions */
-  case 0x60: // syscall_func
+  case M5OP_SE_SYSCALL:
 m5Syscall(tc);
 break;

-  case 0x61: // pagefault_func
+  case M5OP_SE_PAGE_FAULT:
 m5PageFault(tc);
 break;

   /* dist-gem5 functions */
-  case 0x62: // distToggleSync_func
+  case M5OP_DIST_TOGGLE_SYNC:
 togglesync(tc);
 break;


--
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[gem5-dev] Change in public/gem5[master]: util, m5: Use consistent naming for m5op C symbols

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/4264



Change subject: util, m5: Use consistent naming for m5op C symbols
..

util, m5: Use consistent naming for m5op C symbols

Rename m5op C symbols to be prefixed all lower case, separated by
underscore, and prefixed by m5. This avoids potential name clashes for
short names such as arm.

Change-Id: Ic42f94d8a722661ef96c151d627e31eeb2e51490
Signed-off-by: Andreas Sandberg 
Reviewed-by: Jose Marinho 
---
M include/gem5/asm/generic/m5ops.h
M util/m5/m5.c
M util/m5/m5op.h
M util/m5/m5op_alpha.S
M util/m5/m5op_sparc.S
M util/m5/m5op_x86.S
6 files changed, 101 insertions(+), 100 deletions(-)



diff --git a/include/gem5/asm/generic/m5ops.h  
b/include/gem5/asm/generic/m5ops.h

index b7999cb..e3df3f6 100644
--- a/include/gem5/asm/generic/m5ops.h
+++ b/include/gem5/asm/generic/m5ops.h
@@ -102,31 +102,31 @@
 #define M5OP_AN_GETID   0x11


-#define M5OP_FOREACH  \
-M5OP(arm, M5OP_ARM, 0);   \
-M5OP(quiesce, M5OP_QUIESCE, 0);   \
-M5OP(quiesceNs, M5OP_QUIESCE_NS, 0);  \
-M5OP(quiesceCycle, M5OP_QUIESCE_CYCLE, 0);\
-M5OP(quiesceTime, M5OP_QUIESCE_TIME, 0);  \
-M5OP(rpns, M5OP_RPNS, 0); \
-M5OP(wakeCPU, M5OP_WAKE_CPU, 0);  \
-M5OP(m5_exit, M5OP_EXIT, 0);  \
-M5OP(m5_fail, M5OP_FAIL, 0);  \
-M5OP(m5_initparam, M5OP_INIT_PARAM, 0);   \
-M5OP(m5_loadsymbol, M5OP_LOAD_SYMBOL, 0); \
-M5OP(m5_reset_stats, M5OP_RESET_STATS, 0);\
-M5OP(m5_dump_stats, M5OP_DUMP_STATS, 0);  \
-M5OP(m5_dumpreset_stats, M5OP_DUMP_RESET_STATS, 0);   \
-M5OP(m5_checkpoint, M5OP_CHECKPOINT, 0);  \
-M5OP(m5_readfile, M5OP_READ_FILE, 0); \
-M5OP(m5_writefile, M5OP_WRITE_FILE, 0);   \
-M5OP(m5_debugbreak, M5OP_DEBUG_BREAK, 0); \
-M5OP(m5_switchcpu, M5OP_SWITCH_CPU, 0);   \
-M5OP(m5_addsymbol, M5OP_ADD_SYMBOL, 0);   \
-M5OP(m5_panic, M5OP_PANIC, 0);\
-M5OP(m5_work_begin, M5OP_WORK_BEGIN, 0);  \
-M5OP(m5_work_end, M5OP_WORK_END, 0);  \
-M5OP(m5_togglesync, M5OP_DIST_TOGGLE_SYNC, 0);
+#define M5OP_FOREACH\
+M5OP(m5_arm, M5OP_ARM, 0);  \
+M5OP(m5_quiesce, M5OP_QUIESCE, 0);  \
+M5OP(m5_quiesce_ns, M5OP_QUIESCE_NS, 0);\
+M5OP(m5_quiesce_cycle, M5OP_QUIESCE_CYCLE, 0);  \
+M5OP(m5_quiesce_time, M5OP_QUIESCE_TIME, 0);\
+M5OP(m5_rpns, M5OP_RPNS, 0);\
+M5OP(m5_wake_cpu, M5OP_WAKE_CPU, 0);\
+M5OP(m5_exit, M5OP_EXIT, 0);\
+M5OP(m5_fail, M5OP_FAIL, 0);\
+M5OP(m5_init_param, M5OP_INIT_PARAM, 0);\
+M5OP(m5_load_symbol, M5OP_LOAD_SYMBOL, 0);  \
+M5OP(m5_reset_stats, M5OP_RESET_STATS, 0);  \
+M5OP(m5_dump_stats, M5OP_DUMP_STATS, 0);\
+M5OP(m5_dump_reset_stats, M5OP_DUMP_RESET_STATS, 0);\
+M5OP(m5_checkpoint, M5OP_CHECKPOINT, 0);\
+M5OP(m5_read_file, M5OP_READ_FILE, 0);  \
+M5OP(m5_write_file, M5OP_WRITE_FILE, 0);\
+M5OP(m5_debug_break, M5OP_DEBUG_BREAK, 0);  \
+M5OP(m5_switch_cpu, M5OP_SWITCH_CPU, 0);\
+M5OP(m5_add_symbol, M5OP_ADD_SYMBOL, 0);\
+M5OP(m5_panic, M5OP_PANIC, 0);  \
+M5OP(m5_work_begin, M5OP_WORK_BEGIN, 0);\
+M5OP(m5_work_end, M5OP_WORK_END, 0);\
+M5OP(m5_dist_togglesync, M5OP_DIST_TOGGLE_SYNC, 0);

 #define M5OP_FOREACH_ANNOTATION  \
 M5_ANNOTATION(m5a_bsm, M5OP_AN_BSM); \
diff --git a/util/m5/m5.c b/util/m5/m5.c
index bd39041..5b6c7a6 100644
--- a/util/m5/m5.c
+++ b/util/m5/m5.c
@@ -117,7 +117,7 @@
 // Linux does demand paging.
 memset(buf, 0, sizeof(buf));

-while ((len = m5_readfile(buf, sizeof(buf), offset)) > 0) {
+while ((len = m5_read_file(buf, sizeof(buf), offset)) > 0) {
 uint8_t *base = buf;
 offset += len;
 do {
@@ -158,7 +158,7 @@
 memset(buf, 0, sizeof(buf));

 while ((len = read(src_fid, buf, sizeof(buf))) > 0) {
-bytes += 

[gem5-dev] Change in public/gem5[master]: util: Move the m5ops.h file to a shared directory

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/4261



Change subject: util: Move the m5ops.h file to a shared directory
..

util: Move the m5ops.h file to a shared directory

The header file m5ops.h contains a list of constants that should be
shared between the simulator and utilities. Move this header file to a
new top-level directory for shared files and rename constants to make
them suitable for inclusion in the main simulator.

The structure of the shared include directory is as follows:

include/gem5: Files that can be included from C code.
include/gem5/asm: Files that can be included from assembly code.
  asm/generic/: Files that aren't guest ISA specific
  asm/${isa}/: Files that are guest ISA specific

Change-Id: I1aa511057bcaa80cc2d566109ff26581558c4a41
Signed-off-by: Andreas Sandberg 
Reviewed-by: Jose Marinho 
---
A include/gem5/asm/generic/m5ops.h
M util/m5/Makefile.aarch64
M util/m5/Makefile.alpha
M util/m5/Makefile.arm
M util/m5/Makefile.sparc
M util/m5/Makefile.thumb
M util/m5/Makefile.x86
M util/m5/m5op_alpha.S
M util/m5/m5op_arm.S
M util/m5/m5op_arm_A64.S
M util/m5/m5op_sparc.S
M util/m5/m5op_x86.S
D util/m5/m5ops.h
13 files changed, 231 insertions(+), 224 deletions(-)



diff --git a/include/gem5/asm/generic/m5ops.h  
b/include/gem5/asm/generic/m5ops.h

new file mode 100644
index 000..b7999cb
--- /dev/null
+++ b/include/gem5/asm/generic/m5ops.h
@@ -0,0 +1,149 @@
+/*
+ * Copyright (c) 2016 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Copyright (c) 2003-2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ *  Ali Saidi
+ *  Andreas Sandberg
+ */
+
+#ifndef __GEM5_ASM_GENERIC_M5OPS_H__
+#define __GEM5_ASM_GENERIC_M5OPS_H__
+
+#define M5OP_ARM0x00
+#define M5OP_QUIESCE0x01
+#define M5OP_QUIESCE_NS 0x02
+#define M5OP_QUIESCE_CYCLE  0x03
+#define M5OP_QUIESCE_TIME   0x04
+#define M5OP_RPNS   0x07
+#define M5OP_WAKE_CPU   0x09
+#define M5OP_DEPRECATED10x10 // obsolete ivlb
+#define M5OP_DEPRECATED20x11 // obsolete ivle
+#define M5OP_DEPRECATED30x20 // deprecated exit function
+#define M5OP_EXIT   0x21
+#define M5OP_FAIL   0x22
+#define M5OP_INIT_PARAM 0x30
+#define M5OP_LOAD_SYMBOL0x31
+#define M5OP_RESET_STATS0x40
+#define M5OP_DUMP_STATS 0x41
+#define M5OP_DUMP_RESET_STATS   0x42
+#define M5OP_CHECKPOINT 0x43
+#define M5OP_WRITE_FILE 0x4F
+#define M5OP_READ_FILE  0x50
+#define M5OP_DEBUG_BREAK0x51
+#define M5OP_SWITCH_CPU 0x52
+#define M5OP_ADD_SYMBOL 0x53
+#define M5OP_PANIC  0x54
+
+#define M5OP_RESERVED2  0x56 // 

[gem5-dev] Change in public/gem5[master]: arch-arm: Switch to DTOnly as the default machine type

[Andreas Sandberg (Gerrit)]

Hello Nikos Nikoleris,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/4260

to review the following change.


Change subject: arch-arm: Switch to DTOnly as the default machine type
..

arch-arm: Switch to DTOnly as the default machine type

Old ARM systems used to pass the machine type in the ATAGS list passed
to the kernel. This has been largely deprecated by the introduction of
device trees. Switch to the DTOnly machine type by default in gem5
since all new platforms and kernel will require this behavior.

Change-Id: Icfd085e4862863b4ef495566bfddbd11591866c3
Signed-off-by: Andreas Sandberg 
Reviewed-by: Nikos Nikoleris 
---
M configs/example/arm/fs_bigLITTLE.py
M configs/example/arm/starter_fs.py
M src/arch/arm/ArmSystem.py
3 files changed, 3 insertions(+), 5 deletions(-)



diff --git a/configs/example/arm/fs_bigLITTLE.py  
b/configs/example/arm/fs_bigLITTLE.py

index 2965f47..a6110b5 100644
--- a/configs/example/arm/fs_bigLITTLE.py
+++ b/configs/example/arm/fs_bigLITTLE.py
@@ -115,8 +115,7 @@
 def createSystem(caches, kernel, bootscript, disks=[]):
 sys = devices.SimpleSystem(caches, default_mem_size,
kernel=SysPaths.binary(kernel),
-   readfile=bootscript,
-   machine_type="DTOnly")
+   readfile=bootscript)

 sys.mem_ctrls = SimpleMemory(range=sys._mem_range)
 sys.mem_ctrls.port = sys.membus.master
diff --git a/configs/example/arm/starter_fs.py  
b/configs/example/arm/starter_fs.py

index 9b6f68f..2ca1cb8 100644
--- a/configs/example/arm/starter_fs.py
+++ b/configs/example/arm/starter_fs.py
@@ -110,8 +110,7 @@
   mem_mode=mem_mode,
   dtb_filename=dtb_file,
   kernel=SysPaths.binary(args.kernel),
-  readfile=args.script,
-  machine_type="DTOnly")
+  readfile=args.script)

 MemConfig.config_mem(args, system)

diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index c21b9c6..4fa9fd8 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -84,7 +84,7 @@
 type = 'GenericArmSystem'
 cxx_header = "arch/arm/system.hh"
 load_addr_mask = 0x0fff
-machine_type = Param.ArmMachineType('VExpress_EMM',
+machine_type = Param.ArmMachineType('DTOnly',
 "Machine id from http://www.arm.linux.org.uk/developer/machines/;)
 atags_addr = Param.Addr("Address where default atags structure  
should " \

 "be written")

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Icfd085e4862863b4ef495566bfddbd11591866c3
Gerrit-Change-Number: 4260
Gerrit-PatchSet: 1
Gerrit-Owner: Andreas Sandberg 
Gerrit-Reviewer: Nikos Nikoleris 
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[gem5-dev] Change in public/gem5[master]: config, arm: FS configuration for the ARM starter kit

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/4202 )


Change subject: config, arm: FS configuration for the ARM starter kit
..

config, arm: FS configuration for the ARM starter kit

Add a full system example configuration for the ARM Research Starter
Kit on System Modeling. More information can be found at:
http://www.arm.com/ResearchEnablement/SystemModeling

Change-Id: Ifa40419d21923a32bb383d58466e421fe4260ddd
Signed-off-by: Gabor Dozsa 
[ Minor cleanups and more documentation ]
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/4202
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
A configs/example/arm/starter_fs.py
1 file changed, 242 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved



diff --git a/configs/example/arm/starter_fs.py  
b/configs/example/arm/starter_fs.py

new file mode 100644
index 000..9b6f68f
--- /dev/null
+++ b/configs/example/arm/starter_fs.py
@@ -0,0 +1,242 @@
+# Copyright (c) 2016-2017 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+#  Authors:  Andreas Sandberg
+#Chuan Zhu
+#Gabor Dozsa
+#
+
+"""This script is the full system example script from the ARM
+Research Starter Kit on System Modeling. More information can be found
+at: http://www.arm.com/ResearchEnablement/SystemModeling
+"""
+
+import os
+import m5
+from m5.util import addToPath
+from m5.objects import *
+import argparse
+
+m5.util.addToPath('../..')
+
+from common import SysPaths
+from common import MemConfig
+from common.cores.arm import HPI
+
+import devices
+
+
+default_dist_version = '20170616'
+default_kernel = 'vmlinux.vexpress_gem5_v1_64.' + default_dist_version
+default_disk = 'linaro-minimal-aarch64.img'
+
+
+# Pre-defined CPU configurations. Each tuple must be ordered as :  
(cpu_class,
+# l1_icache_class, l1_dcache_class, walk_cache_class, l2_Cache_class). Any  
of

+# the cache class may be 'None' if the particular cache is not present.
+cpu_types = {
+
+"atomic" : ( AtomicSimpleCPU, None, None, None, None),
+"minor" : (MinorCPU,
+   devices.L1I, devices.L1D,
+   devices.WalkCache,
+   devices.L2),
+"hpi" : ( HPI.HPI,
+  HPI.HPI_ICache, HPI.HPI_DCache,
+  HPI.HPI_WalkCache,
+  HPI.HPI_L2)
+}
+
+def create_cow_image(name):
+"""Helper function to create a Copy-on-Write disk image"""
+image = CowDiskImage()
+image.child.image_file = SysPaths.disk(name)
+
+return image;
+
+
+def create(args):
+''' Create and configure the system object. '''
+
+if not args.dtb:
+dtb_file = SysPaths.binary("armv8_gem5_v1_%icpu.%s.dtb" %
+

[gem5-dev] Change in public/gem5[master]: config, arm: SE configuration for the ARM starter kit

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/4203 )


Change subject: config, arm: SE configuration for the ARM starter kit
..

config, arm: SE configuration for the ARM starter kit

Add a full system example configuration for the ARM Research Starter
Kit on System Modeling. More information can be found at:
http://www.arm.com/ResearchEnablement/SystemModeling

Change-Id: Ia32a28eb713ba7050d790327ba6dbb73ec33b53a
Signed-off-by: Gabor Dozsa 
[ Minor cleanups and more documentation ]
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/4203
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
A configs/example/arm/starter_se.py
1 file changed, 233 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved



diff --git a/configs/example/arm/starter_se.py  
b/configs/example/arm/starter_se.py

new file mode 100644
index 000..902e6e4
--- /dev/null
+++ b/configs/example/arm/starter_se.py
@@ -0,0 +1,233 @@
+# Copyright (c) 2016-2017 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+#  Authors:  Andreas Sandberg
+#Chuan Zhu
+#Gabor Dozsa
+#
+
+"""This script is the syscall emulation example script from the ARM
+Research Starter Kit on System Modeling. More information can be found
+at: http://www.arm.com/ResearchEnablement/SystemModeling
+"""
+
+import os
+import m5
+from m5.util import addToPath
+from m5.objects import *
+import argparse
+import shlex
+
+m5.util.addToPath('../..')
+
+from common import MemConfig
+from common.cores.arm import HPI
+
+import devices
+
+
+
+# Pre-defined CPU configurations. Each tuple must be ordered as :  
(cpu_class,
+# l1_icache_class, l1_dcache_class, walk_cache_class, l2_Cache_class). Any  
of

+# the cache class may be 'None' if the particular cache is not present.
+cpu_types = {
+"atomic" : ( AtomicSimpleCPU, None, None, None, None),
+"minor" : (MinorCPU,
+   devices.L1I, devices.L1D,
+   devices.WalkCache,
+   devices.L2),
+"hpi" : ( HPI.HPI,
+  HPI.HPI_ICache, HPI.HPI_DCache,
+  HPI.HPI_WalkCache,
+  HPI.HPI_L2)
+}
+
+
+class SimpleSeSystem(System):
+'''
+Example system class for syscall emulation mode
+'''
+
+# Use a fixed cache line size of 64 bytes
+cache_line_size = 64
+
+def __init__(self, args, **kwargs):
+super(SimpleSeSystem, self).__init__(**kwargs)
+
+# Setup book keeping to be able to use CpuClusters from the
+# devices module.
+self._clusters = []
+self._num_cpus = 0
+
+# Create a voltage and clock domain for system components
+self.voltage_domain = 

[gem5-dev] Change in public/gem5[master]: config, arm: Add a high-performance in order timing model

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/4201 )


Change subject: config, arm: Add a high-performance in order timing model
..

config, arm: Add a high-performance in order timing model

The High-Performance In-order (HPI) CPU timing model is tuned to be
representative of a modern in-order ARMv8-A implementation. The HPI
core and its supporting simulation scripts, namely starter_se.py and
starter_fs.py (under /configs/example/arm/) are part of the ARM
Research Starter Kit on System Modeling. More information can be found
at: http://www.arm.com/ResearchEnablement/SystemModeling

Change-Id: I124bd06ba42d20abff09d447542b031d17eabe22
Signed-off-by: Ashkan Tousi 
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/4201
Reviewed-by: Jason Lowe-Power 
---
A configs/common/cores/arm/HPI.py
1 file changed, 1,454 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/configs/common/cores/arm/HPI.py  
b/configs/common/cores/arm/HPI.py

new file mode 100644
index 000..03bad24
--- /dev/null
+++ b/configs/common/cores/arm/HPI.py
@@ -0,0 +1,1454 @@
+# Copyright (c) 2014-2017 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andrew Bardsley
+#
+
+"""The High-Performance In-order (HPI) CPU timing model is tuned to be
+representative of a modern in-order ARMv8-A implementation. The HPI
+core and its supporting simulation scripts, namely starter_se.py and
+starter_fs.py (under /configs/example/arm/) are part of the ARM
+Research Starter Kit on System Modeling. More information can be found
+at: http://www.arm.com/ResearchEnablement/SystemModeling
+
+"""
+
+from m5.objects import *
+
+# Simple function to allow a string of [01x_] to be converted into a
+# mask and value for use with MinorFUTiming
+def make_implicant(implicant_string):
+ret_mask = 0
+ret_match = 0
+
+shift = False
+for char in implicant_string:
+char = char.lower()
+if shift:
+ret_mask <<= 1
+ret_match <<= 1
+
+shift = True
+if char == '_':
+shift = False
+elif char == '0':
+ret_mask |= 1
+elif char == '1':
+ret_mask |= 1
+ret_match |= 1
+elif char == 'x':
+pass
+else:
+print "Can't parse implicant character", char
+
+return (ret_mask, ret_match)
+
+#  ,- 36 thumb
+#  | ,--- 35 bigThumb
+#  | |,-- 34 aarch64
+a64_inst =  
make_implicant('0_01xx__________')
+a32_inst =  

[gem5-dev] Change in public/gem5[master]: config: Change mem_range attribute naming in ARM SimpleSystem

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/4200 )


Change subject: config: Change mem_range attribute naming in ARM  
SimpleSystem

..

config: Change mem_range attribute naming in ARM SimpleSystem

MemConfig.config() expects memory ranges to be defined in a particular
way. This patch changes the naming of the mem_range attribute in
SympleSystem to enable use of MemConfig for configuring the memory.

Change-Id: I4964c136e53a99c69ff5e086cacb929aa435168d
Signed-off-by: Gabor Dozsa 
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/4200
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M configs/example/arm/devices.py
1 file changed, 3 insertions(+), 3 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved



diff --git a/configs/example/arm/devices.py b/configs/example/arm/devices.py
index f7375cd..467d2b9 100644
--- a/configs/example/arm/devices.py
+++ b/configs/example/arm/devices.py
@@ -209,13 +209,13 @@
 mem_range = self.realview._mem_regions[0]
 mem_range_size = long(mem_range[1]) - long(mem_range[0])
 assert mem_range_size >= long(Addr(mem_size))
-self._mem_range = AddrRange(start=mem_range[0], size=mem_size)
+self.mem_ranges = [ AddrRange(start=mem_range[0], size=mem_size) ]
 self._caches = caches
 if self._caches:
-self.iocache = IOCache(addr_ranges=[self._mem_range])
+self.iocache = IOCache(addr_ranges=[self.mem_ranges[0]])
 else:
 self.dmabridge = Bridge(delay='50ns',
-ranges=[self._mem_range])
+ranges=[self.mem_ranges[0]])

 self._pci_devices = 0
 self._clusters = []

--
To view, visit https://gem5-review.googlesource.com/4200
To unsubscribe, visit https://gem5-review.googlesource.com/settings

Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I4964c136e53a99c69ff5e086cacb929aa435168d
Gerrit-Change-Number: 4200
Gerrit-PatchSet: 3
Gerrit-Owner: Andreas Sandberg 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabor Dozsa 
Gerrit-Reviewer: Jason Lowe-Power 
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[gem5-dev] Change in public/gem5[master]: config, arm: FS configuration for the ARM starter kit

[Andreas Sandberg (Gerrit)]

Hello Jason Lowe-Power, Gabor Dozsa,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/4202

to look at the new patch set (#3).

Change subject: config, arm: FS configuration for the ARM starter kit
..

config, arm: FS configuration for the ARM starter kit

Add a full system example configuration for the ARM Research Starter
Kit on System Modeling. More information can be found at:
http://www.arm.com/ResearchEnablement/SystemModeling

Change-Id: Ifa40419d21923a32bb383d58466e421fe4260ddd
Signed-off-by: Gabor Dozsa 
[ Minor cleanups and more documentation ]
Signed-off-by: Andreas Sandberg 
---
A configs/example/arm/starter_fs.py
1 file changed, 242 insertions(+), 0 deletions(-)


--
To view, visit https://gem5-review.googlesource.com/4202
To unsubscribe, visit https://gem5-review.googlesource.com/settings

Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: Ifa40419d21923a32bb383d58466e421fe4260ddd
Gerrit-Change-Number: 4202
Gerrit-PatchSet: 3
Gerrit-Owner: Andreas Sandberg 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabor Dozsa 
Gerrit-Reviewer: Jason Lowe-Power 
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[gem5-dev] Change in public/gem5[master]: config, arm: FS configuration for the ARM starter kit

[Andreas Sandberg (Gerrit)]

Hello Jason Lowe-Power, Gabor Dozsa,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/4202

to look at the new patch set (#2).

Change subject: config, arm: FS configuration for the ARM starter kit
..

config, arm: FS configuration for the ARM starter kit

Add a full system example configuration for the ARM Research Starter
Kit on System Modeling. More information can be found at:
http://www.arm.com/ResearchEnablement/SystemModeling

Change-Id: Ifa40419d21923a32bb383d58466e421fe4260ddd
Signed-off-by: Gabor Dozsa 
[ Minor cleanups and more documentation ]
Signed-off-by: Andreas Sandberg 
---
A configs/example/arm/starter_fs.py
1 file changed, 237 insertions(+), 0 deletions(-)


--
To view, visit https://gem5-review.googlesource.com/4202
To unsubscribe, visit https://gem5-review.googlesource.com/settings

Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: Ifa40419d21923a32bb383d58466e421fe4260ddd
Gerrit-Change-Number: 4202
Gerrit-PatchSet: 2
Gerrit-Owner: Andreas Sandberg 
Gerrit-Reviewer: Gabor Dozsa 
Gerrit-Reviewer: Jason Lowe-Power 
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[gem5-dev] Change in public/gem5[master]: config, arm: SE configuration for the ARM starter kit

[Andreas Sandberg (Gerrit)]

Hello Jason Lowe-Power, Gabor Dozsa,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/4203

to look at the new patch set (#2).

Change subject: config, arm: SE configuration for the ARM starter kit
..

config, arm: SE configuration for the ARM starter kit

Add a full system example configuration for the ARM Research Starter
Kit on System Modeling. More information can be found at:
http://www.arm.com/ResearchEnablement/SystemModeling

Change-Id: Ia32a28eb713ba7050d790327ba6dbb73ec33b53a
Signed-off-by: Gabor Dozsa 
[ Minor cleanups and more documentation ]
Signed-off-by: Andreas Sandberg 
---
A configs/example/arm/starter_se.py
1 file changed, 233 insertions(+), 0 deletions(-)


--
To view, visit https://gem5-review.googlesource.com/4203
To unsubscribe, visit https://gem5-review.googlesource.com/settings

Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: Ia32a28eb713ba7050d790327ba6dbb73ec33b53a
Gerrit-Change-Number: 4203
Gerrit-PatchSet: 2
Gerrit-Owner: Andreas Sandberg 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabor Dozsa 
Gerrit-Reviewer: Jason Lowe-Power 
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[gem5-dev] Change in public/gem5[master]: tests: Fix path for module imports in ARM system configs

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/4220 )


Change subject: tests: Fix path for module imports in ARM system configs
..

tests: Fix path for module imports in ARM system configs

Change-Id: I6fd660da3899de1f8c61bf012532ff0437467302
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/4220
Maintainer: Andreas Sandberg 
---
M tests/configs/realview-o3-checker.py
M tests/configs/realview-o3-dual.py
M tests/configs/realview64-o3-checker.py
M tests/configs/realview64-o3-dual.py
M tests/configs/realview64-o3.py
5 files changed, 10 insertions(+), 10 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/tests/configs/realview-o3-checker.py  
b/tests/configs/realview-o3-checker.py

index b2e61d2..5bb266f 100644
--- a/tests/configs/realview-o3-checker.py
+++ b/tests/configs/realview-o3-checker.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2012 ARM Limited
+# Copyright (c) 2012, 2017 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -37,7 +37,7 @@

 from m5.objects import *
 from arm_generic import *
-from common.O3_ARM_v7a import O3_ARM_v7a_3
+from common.cores.arm.O3_ARM_v7a import O3_ARM_v7a_3

 root = LinuxArmFSSystemUniprocessor(mem_mode='timing',
 mem_class=DDR3_1600_8x8,
diff --git a/tests/configs/realview-o3-dual.py  
b/tests/configs/realview-o3-dual.py

index f2042cd..7b035ba 100644
--- a/tests/configs/realview-o3-dual.py
+++ b/tests/configs/realview-o3-dual.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2012 ARM Limited
+# Copyright (c) 2012, 2017 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -37,7 +37,7 @@

 from m5.objects import *
 from arm_generic import *
-from common.O3_ARM_v7a import O3_ARM_v7a_3
+from common.cores.arm.O3_ARM_v7a import O3_ARM_v7a_3

 root = LinuxArmFSSystem(mem_mode='timing',
 mem_class=DDR3_1600_8x8,
diff --git a/tests/configs/realview64-o3-checker.py  
b/tests/configs/realview64-o3-checker.py

index 0d52329..5fd50e6 100644
--- a/tests/configs/realview64-o3-checker.py
+++ b/tests/configs/realview64-o3-checker.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2012 ARM Limited
+# Copyright (c) 2012, 2017 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -37,7 +37,7 @@

 from m5.objects import *
 from arm_generic import *
-from common.O3_ARM_v7a import O3_ARM_v7a_3
+from common.cores.arm.O3_ARM_v7a import O3_ARM_v7a_3

 root = LinuxArmFSSystemUniprocessor(machine_type='VExpress_EMM64',
 mem_mode='timing',
diff --git a/tests/configs/realview64-o3-dual.py  
b/tests/configs/realview64-o3-dual.py

index 6675c6e..6c5dc0a 100644
--- a/tests/configs/realview64-o3-dual.py
+++ b/tests/configs/realview64-o3-dual.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2012 ARM Limited
+# Copyright (c) 2012, 2017 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -37,7 +37,7 @@

 from m5.objects import *
 from arm_generic import *
-from common.O3_ARM_v7a import O3_ARM_v7a_3
+from common.cores.arm.O3_ARM_v7a import O3_ARM_v7a_3

 root = LinuxArmFSSystem(machine_type='VExpress_EMM64',
 mem_mode='timing',
diff --git a/tests/configs/realview64-o3.py b/tests/configs/realview64-o3.py
index 090db1e..2558093 100644
--- a/tests/configs/realview64-o3.py
+++ b/tests/configs/realview64-o3.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2012 ARM Limited
+# Copyright (c) 2012, 2017 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -37,7 +37,7 @@

 from m5.objects import *
 from arm_generic import *
-from common.O3_ARM_v7a import O3_ARM_v7a_3
+from common.cores.arm.O3_ARM_v7a import O3_ARM_v7a_3

 root = LinuxArmFSSystemUniprocessor(machine_type='VExpress_EMM64',
 mem_mode='timing',

--
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Gerrit-MessageType: merged
Gerrit-Change-Id: I6fd660da3899de1f8c61bf012532ff0437467302
Gerrit-Change-Number: 4220
Gerrit-PatchSet: 2
Gerrit-Owner: Nikos Nikoleris 
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[gem5-dev] Change in public/gem5[master]: config, arm: Add a high-performance in order timing model

[Andreas Sandberg (Gerrit)]

Hello Ashkan Tousi,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/4201

to review the following change.


Change subject: config, arm: Add a high-performance in order timing model
..

config, arm: Add a high-performance in order timing model

The High-Performance In-order (HPI) CPU timing model is tuned to be
representative of a modern in-order ARMv8-A implementation. The HPI
core and its supporting simulation scripts, namely starter_se.py and
starter_fs.py (under /configs/example/arm/) are part of the ARM
Research Starter Kit on System Modeling. More information can be found
at: http://www.arm.com/ResearchEnablement/SystemModeling

Change-Id: I124bd06ba42d20abff09d447542b031d17eabe22
Signed-off-by: Ashkan Tousi 
Signed-off-by: Andreas Sandberg 
---
A configs/common/cores/arm/HPI.py
1 file changed, 1,454 insertions(+), 0 deletions(-)



diff --git a/configs/common/cores/arm/HPI.py  
b/configs/common/cores/arm/HPI.py

new file mode 100644
index 000..03bad24
--- /dev/null
+++ b/configs/common/cores/arm/HPI.py
@@ -0,0 +1,1454 @@
+# Copyright (c) 2014-2017 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andrew Bardsley
+#
+
+"""The High-Performance In-order (HPI) CPU timing model is tuned to be
+representative of a modern in-order ARMv8-A implementation. The HPI
+core and its supporting simulation scripts, namely starter_se.py and
+starter_fs.py (under /configs/example/arm/) are part of the ARM
+Research Starter Kit on System Modeling. More information can be found
+at: http://www.arm.com/ResearchEnablement/SystemModeling
+
+"""
+
+from m5.objects import *
+
+# Simple function to allow a string of [01x_] to be converted into a
+# mask and value for use with MinorFUTiming
+def make_implicant(implicant_string):
+ret_mask = 0
+ret_match = 0
+
+shift = False
+for char in implicant_string:
+char = char.lower()
+if shift:
+ret_mask <<= 1
+ret_match <<= 1
+
+shift = True
+if char == '_':
+shift = False
+elif char == '0':
+ret_mask |= 1
+elif char == '1':
+ret_mask |= 1
+ret_match |= 1
+elif char == 'x':
+pass
+else:
+print "Can't parse implicant character", char
+
+return (ret_mask, ret_match)
+
+#  ,- 36 thumb
+#  | ,--- 35 bigThumb
+#  | |,-- 34 aarch64
+a64_inst =  
make_implicant('0_01xx__________')
+a32_inst =  
make_implicant('0_00xx__________')
+t32_inst =  
make_implicant('1_10xx__________')
+t16_inst =  
make_implicant('1_00xx__________')
+any_inst =  

[gem5-dev] Change in public/gem5[master]: config, arm: SE configuration for the ARM starter kit

[Andreas Sandberg (Gerrit)]

Hello Gabor Dozsa,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/4203

to review the following change.


Change subject: config, arm: SE configuration for the ARM starter kit
..

config, arm: SE configuration for the ARM starter kit

Add a full system example configuration for the ARM Research Starter
Kit on System Modeling. More information can be found at:
http://www.arm.com/ResearchEnablement/SystemModeling

Change-Id: Ia32a28eb713ba7050d790327ba6dbb73ec33b53a
Signed-off-by: Gabor Dozsa 
Signed-off-by: Andreas Sandberg 
---
A configs/example/arm/starter_se.py
1 file changed, 201 insertions(+), 0 deletions(-)



diff --git a/configs/example/arm/starter_se.py  
b/configs/example/arm/starter_se.py

new file mode 100644
index 000..ff0c94c
--- /dev/null
+++ b/configs/example/arm/starter_se.py
@@ -0,0 +1,201 @@
+# Copyright (c) 2016-2017 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+#  Authors:  Andreas Sandberg
+#Chuan Zhu
+#Gabor Dozsa
+#
+
+import os
+import m5
+from m5.util import addToPath
+from m5.objects import *
+import argparse
+import shlex
+
+m5.util.addToPath('../..')
+
+from common import MemConfig
+from common.cores.arm import HPI
+
+import devices
+
+
+
+# Pre-defined CPU configurations. Each tuple must be ordered as :  
(cpu_class,
+# l1_icache_class, l1_dcache_class, walk_cache_class, l2_Cache_class). Any  
of

+# the cache class may be 'None' if the particular cache is not present.
+cpu_types = {
+"atomic" : ( AtomicSimpleCPU, None, None, None, None),
+"minor" : (MinorCPU,
+   devices.L1I, devices.L1D,
+   devices.WalkCache,
+   devices.L2),
+"hpi" : ( HPI.HPI,
+  HPI.HPI_ICache, HPI.HPI_DCache,
+  HPI.HPI_WalkCache,
+  HPI.HPI_L2)
+}
+
+
+def addOptions(parser):
+parser.add_argument("commands_to_run", metavar="command(s)", nargs='*',
+help="Command(s) to run")
+parser.add_argument("--cpu", type=str, choices=cpu_types.keys(),
+default="atomic",
+help="CPU model to use")
+parser.add_argument("--cpu-freq", type=str, default="4GHz")
+parser.add_argument("--num-cores", type=int, default=1,
+help="Number of CPU cores")
+parser.add_argument("--mem-type", default="DDR3_1600_8x8",
+choices=MemConfig.mem_names(),
+help = "type of memory to use")
+parser.add_argument("--mem-channels", type=int, default=2,
+help = "number of memory channels")
+parser.add_argument("--mem-ranks", type=int, default=None,
+help = "number of memory ranks per channel")
+parser.add_argument("--mem-size", action="store", type=str,
+ 

[gem5-dev] Change in public/gem5[master]: config: Change mem_range attribute naming in ARM SimpleSystem

[Andreas Sandberg (Gerrit)]

Hello Gabor Dozsa,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/4200

to review the following change.


Change subject: config: Change mem_range attribute naming in ARM  
SimpleSystem

..

config: Change mem_range attribute naming in ARM SimpleSystem

MemConfig.config() expects memory ranges to be defined in a particular
way. This patch changes the naming of the mem_range attribute in
SympleSystem to enable use of MemConfig for configuring the memory.

Change-Id: I4964c136e53a99c69ff5e086cacb929aa435168d
Signed-off-by: Gabor Dozsa 
Signed-off-by: Andreas Sandberg 
---
M configs/example/arm/devices.py
1 file changed, 3 insertions(+), 3 deletions(-)



diff --git a/configs/example/arm/devices.py b/configs/example/arm/devices.py
index f7375cd..467d2b9 100644
--- a/configs/example/arm/devices.py
+++ b/configs/example/arm/devices.py
@@ -209,13 +209,13 @@
 mem_range = self.realview._mem_regions[0]
 mem_range_size = long(mem_range[1]) - long(mem_range[0])
 assert mem_range_size >= long(Addr(mem_size))
-self._mem_range = AddrRange(start=mem_range[0], size=mem_size)
+self.mem_ranges = [ AddrRange(start=mem_range[0], size=mem_size) ]
 self._caches = caches
 if self._caches:
-self.iocache = IOCache(addr_ranges=[self._mem_range])
+self.iocache = IOCache(addr_ranges=[self.mem_ranges[0]])
 else:
 self.dmabridge = Bridge(delay='50ns',
-ranges=[self._mem_range])
+ranges=[self.mem_ranges[0]])

 self._pci_devices = 0
 self._clusters = []

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I4964c136e53a99c69ff5e086cacb929aa435168d
Gerrit-Change-Number: 4200
Gerrit-PatchSet: 1
Gerrit-Owner: Andreas Sandberg 
Gerrit-Reviewer: Gabor Dozsa 
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[gem5-dev] Change in public/gem5[master]: config, arm: FS configuration for the ARM starter kit

[Andreas Sandberg (Gerrit)]

Hello Gabor Dozsa,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/4202

to review the following change.


Change subject: config, arm: FS configuration for the ARM starter kit
..

config, arm: FS configuration for the ARM starter kit

Add a full system example configuration for the ARM Research Starter
Kit on System Modeling. More information can be found at:
http://www.arm.com/ResearchEnablement/SystemModeling

Change-Id: Ifa40419d21923a32bb383d58466e421fe4260ddd
Signed-off-by: Gabor Dozsa 
Signed-off-by: Andreas Sandberg 
---
A configs/example/arm/starter_fs.py
1 file changed, 212 insertions(+), 0 deletions(-)



diff --git a/configs/example/arm/starter_fs.py  
b/configs/example/arm/starter_fs.py

new file mode 100644
index 000..f3dbbec
--- /dev/null
+++ b/configs/example/arm/starter_fs.py
@@ -0,0 +1,212 @@
+# Copyright (c) 2016-2017 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+#  Authors:  Andreas Sandberg
+#Chuan Zhu
+#Gabor Dozsa
+#
+
+import os
+import m5
+from m5.util import addToPath
+from m5.objects import *
+import argparse
+
+m5.util.addToPath('../..')
+
+from common import SysPaths
+from common import MemConfig
+from common.cores.arm import HPI
+
+import devices
+
+
+default_dist_version = '20170616'
+
+default_kernel = 'vmlinux.vexpress_gem5_v1_64.' + default_dist_version
+default_disk = 'linaro-minimal-aarch64.img'
+default_mem_size= "2GB"
+
+
+
+# Pre-defined CPU configurations. Each tuple must be ordered as :  
(cpu_class,
+# l1_icache_class, l1_dcache_class, walk_cache_class, l2_Cache_class). Any  
of

+# the cache class may be 'None' if the particular cache is not present.
+cpu_types = {
+
+"atomic" : ( AtomicSimpleCPU, None, None, None, None),
+"minor" : (MinorCPU,
+   devices.L1I, devices.L1D,
+   devices.WalkCache,
+   devices.L2),
+"hpi" : ( HPI.HPI,
+  HPI.HPI_ICache, HPI.HPI_DCache,
+  HPI.HPI_WalkCache,
+  HPI.HPI_L2)
+}
+
+
+def addOptions(parser):
+parser.add_argument("--dtb", type=str, default=None,
+help="DTB file to load")
+parser.add_argument("--kernel", type=str, default=default_kernel,
+help="Linux kernel")
+parser.add_argument("--disk-image", type=str,
+default=default_disk,
+help="Disk to instantiate")
+parser.add_argument("--script", type=str, default="",
+help = "Linux bootscript")
+parser.add_argument("--cpu", type=str, choices=cpu_types.keys(),
+default="atomic",
+help="CPU model to use")
+parser.add_argument("--cpu-freq", type=str, default="4GHz")
+parser.add_argument("--num-cores", type=int, default=1,
+

[gem5-dev] Change in public/gem5[master]: sim: Prevent segfault in the wakeCpu m5op if id is invalid

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/3965 )


Change subject: sim: Prevent segfault in the wakeCpu m5op if id is invalid
..

sim: Prevent segfault in the wakeCpu m5op if id is invalid

Change-Id: I86229cedb206e10326cdee3f09a5c871e49c8d48
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/3965
---
M src/sim/pseudo_inst.cc
1 file changed, 8 insertions(+), 1 deletion(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/sim/pseudo_inst.cc b/src/sim/pseudo_inst.cc
index 8c2d26b..778675f 100644
--- a/src/sim/pseudo_inst.cc
+++ b/src/sim/pseudo_inst.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2012, 2015 ARM Limited
+ * Copyright (c) 2010-2012, 2015, 2017 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -285,6 +285,13 @@
 {
 DPRINTF(PseudoInst, "PseudoInst::wakeCPU(%i)\n", cpuid);
 System *sys = tc->getSystemPtr();
+
+if (sys->numContexts() <= cpuid) {
+warn("PseudoInst::wakeCPU(%i), cpuid greater than number of  
contexts"

+ "(%i)\n",cpuid, sys->numContexts());
+return;
+}
+
 ThreadContext *other_tc = sys->threadContexts[cpuid];
 if (other_tc->status() == ThreadContext::Suspended)
 other_tc->activate();

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I86229cedb206e10326cdee3f09a5c871e49c8d48
Gerrit-Change-Number: 3965
Gerrit-PatchSet: 4
Gerrit-Owner: Andreas Sandberg 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Jason Lowe-Power 
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[gem5-dev] Change in public/gem5[master]: cpu: Add missing rename of vector registers in the O3 CPU

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/4140 )


Change subject: cpu: Add missing rename of vector registers in the O3 CPU
..

cpu: Add missing rename of vector registers in the O3 CPU

The introduction of a new vector register class broke rename in the O3
CPU due to an unhandled register class in
DefaultRename::renameSrcRegs(). This patch fixes adds the
necessary handling to avoid a panic when the vector register file is
used.

Change-Id: Ie380ab35ec4a151db15402f25b25b58931ee0581
Reviewed-by: Giacomo Gabrielli 
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/4140
Reviewed-by: Jason Lowe-Power 
Maintainer: Andreas Sandberg 
---
M src/cpu/o3/rename_impl.hh
1 file changed, 3 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved



diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh
index b9adcdf..bc024f6 100644
--- a/src/cpu/o3/rename_impl.hh
+++ b/src/cpu/o3/rename_impl.hh
@@ -1028,6 +1028,9 @@
   case FloatRegClass:
 fpRenameLookups++;
 break;
+  case VecRegClass:
+vecRenameLookups++;
+break;
   case CCRegClass:
   case MiscRegClass:
 break;

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: Ie380ab35ec4a151db15402f25b25b58931ee0581
Gerrit-Change-Number: 4140
Gerrit-PatchSet: 2
Gerrit-Owner: Andreas Sandberg 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Jason Lowe-Power 
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[gem5-dev] Change in public/gem5[master]: cpu: Add missing rename of vector registers in the O3 CPU

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/4140



Change subject: cpu: Add missing rename of vector registers in the O3 CPU
..

cpu: Add missing rename of vector registers in the O3 CPU

The introduction of a new vector register class broke rename in the O3
CPU due to an unhandled register class in
DefaultRename::renameSrcRegs(). This patch fixes adds the
necessary handling to avoid a panic when the vector register file is
used.

Change-Id: Ie380ab35ec4a151db15402f25b25b58931ee0581
Reviewed-by: Giacomo Gabrielli 
Reviewed-by: Andreas Sandberg 
---
M src/cpu/o3/rename_impl.hh
1 file changed, 3 insertions(+), 0 deletions(-)



diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh
index b9adcdf..bc024f6 100644
--- a/src/cpu/o3/rename_impl.hh
+++ b/src/cpu/o3/rename_impl.hh
@@ -1028,6 +1028,9 @@
   case FloatRegClass:
 fpRenameLookups++;
 break;
+  case VecRegClass:
+vecRenameLookups++;
+break;
   case CCRegClass:
   case MiscRegClass:
 break;

--
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Gerrit-Change-Number: 4140
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[gem5-dev] Change in public/gem5[master]: tests: Don't treat new stats as a cause for failures

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/3962 )


Change subject: tests: Don't treat new stats as a cause for failures
..

tests: Don't treat new stats as a cause for failures

We currently fail the stat diff stage of tests if there are new
stats. This is usually undesirable since this would require any change
that adds a stat to also update the regressions.

Change-Id: Ieadebac6fd17534e1b49b6b9a1d56f037a423325
Signed-off-by: Andreas Sandberg 
Reviewed-by: Nikos Nikoleris 
Reviewed-on: https://gem5-review.googlesource.com/3962
Reviewed-by: Anthony Gutierrez 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M tests/diff-out
M tests/testing/units.py
2 files changed, 12 insertions(+), 4 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Anthony Gutierrez: Looks good to me, approved



diff --git a/tests/diff-out b/tests/diff-out
index c00d4f3..1eeac81 100755
--- a/tests/diff-out
+++ b/tests/diff-out
@@ -361,8 +361,12 @@
 }

 cleanup();
-# Exit code is 0 if all stats are found (with no extras) & no stats error,  
1 otherwise
-$status = ($missing_stats == 0 && $added_stats == 0 && $max_err_mag ==  
0.0) ? 0 : 1;

+# Exit codes:
+# 0 if all stats are found (with no extras) & no stats error
+# 1 if there are additional stats, but no stat errors
+# 2 otherwise
+$no_hard_errors = $missing_stats == 0 && $max_err_mag == 0.0;
+$status = $no_hard_errors ? ($added_stats == 0 ? 0 : 1) : 2;
 exit $status;

 sub cleanup
diff --git a/tests/testing/units.py b/tests/testing/units.py
index e8b87a0..220cf61 100644
--- a/tests/testing/units.py
+++ b/tests/testing/units.py
@@ -270,6 +270,10 @@
 self.stat_diff = os.path.join(_test_base, "diff-out")

 def _run(self):
+STATUS_OK = 0
+STATUS_NEW_STATS = 1
+STATUS_FAILED = 2
+
 stats = "stats.txt"

 cmd = [
@@ -281,9 +285,9 @@
stderr=subprocess.PIPE) as p:
 status, stdout, stderr = p.call()

-if status == 0:
+if status in (STATUS_OK, STATUS_NEW_STATS):
 return self.ok(stdout=stdout, stderr=stderr)
-if status == 1:
+elif status == STATUS_FAILED:
 return self.failure("Statistics mismatch",
 stdout=stdout, stderr=stderr)
 else:

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: Ieadebac6fd17534e1b49b6b9a1d56f037a423325
Gerrit-Change-Number: 3962
Gerrit-PatchSet: 2
Gerrit-Owner: Andreas Sandberg 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Anthony Gutierrez 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nikos Nikoleris 
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[gem5-dev] Change in public/gem5[master]: sim: Prevent segfault in the wakeCpu m5op if id is invalid

[Andreas Sandberg (Gerrit)]

Hello Jason Lowe-Power,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/3965

to look at the new patch set (#3).

Change subject: sim: Prevent segfault in the wakeCpu m5op if id is invalid
..

sim: Prevent segfault in the wakeCpu m5op if id is invalid

Change-Id: I86229cedb206e10326cdee3f09a5c871e49c8d48
Signed-off-by: Andreas Sandberg 
---
M src/sim/pseudo_inst.cc
1 file changed, 8 insertions(+), 1 deletion(-)


--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I86229cedb206e10326cdee3f09a5c871e49c8d48
Gerrit-Change-Number: 3965
Gerrit-PatchSet: 3
Gerrit-Owner: Andreas Sandberg 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Jason Lowe-Power 
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[gem5-dev] Change in public/gem5[master]: cpu, sim: Add param to force CPUs to wait for GDB

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/3963 )


Change subject: cpu, sim: Add param to force CPUs to wait for GDB
..

cpu, sim: Add param to force CPUs to wait for GDB

By setting the BaseCPU parameter wait_for_dbg_connection, the GDB
server blocks during initialisation waiting for the remote debugger to
connect before starting the simulated CPU.

Change-Id: I4d62c68ce9adf69344bccbb44f66e30b33715a1c
[ Update info message to include remote GDB port, rename param. ]
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/3963
Reviewed-by: Gabe Black 
Reviewed-by: Anthony Gutierrez 
---
M src/base/remote_gdb.cc
M src/base/remote_gdb.hh
M src/cpu/BaseCPU.py
M src/cpu/base.cc
M src/cpu/base.hh
M src/sim/system.cc
6 files changed, 30 insertions(+), 9 deletions(-)

Approvals:
  Anthony Gutierrez: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved



diff --git a/src/base/remote_gdb.cc b/src/base/remote_gdb.cc
index f7b0253..3b436cc 100644
--- a/src/base/remote_gdb.cc
+++ b/src/base/remote_gdb.cc
@@ -250,6 +250,16 @@
 }
 }

+int
+GDBListener::getPort() const
+{
+panic_if(!listener.islistening(),
+ "Remote GDB port is unknown until GDBListener::listen() has "
+ "been called.\n");
+
+return port;
+}
+
 BaseRemoteGDB::InputEvent::InputEvent(BaseRemoteGDB *g, int fd, int e)
 : PollEvent(fd, e), gdb(g)
 {}
diff --git a/src/base/remote_gdb.hh b/src/base/remote_gdb.hh
index b860f5d..b7de0ae 100644
--- a/src/base/remote_gdb.hh
+++ b/src/base/remote_gdb.hh
@@ -364,6 +364,8 @@
 void accept();
 void listen();
 std::string name();
+
+int getPort() const;
 };

 #endif /* __REMOTE_GDB_H__ */
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 550ba62..fcae742 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -151,6 +151,9 @@
 profile = Param.Latency('0ns', "trace the kernel stack")
 do_quiesce = Param.Bool(True, "enable quiesce instructions")

+wait_for_remote_gdb = Param.Bool(False,
+"Wait for a remote GDB connection");
+
 workload = VectorParam.Process([], "processes to run")

 if buildEnv['TARGET_ISA'] == 'sparc':
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 6f460d3..78b25ca 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -783,3 +783,9 @@
 functionEntryTick = curTick();
 }
 }
+
+bool
+BaseCPU::waitForRemoteGDB() const
+{
+return params()->wait_for_remote_gdb;
+}
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 14dfc26..b49f302 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -589,6 +589,8 @@
 return [tid];
 }

+bool waitForRemoteGDB() const;
+
 Cycles syscallRetryLatency;
 };

diff --git a/src/sim/system.cc b/src/sim/system.cc
index e46c356..42cd5e7 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -58,6 +58,7 @@
 #include "cpu/kvm/base.hh"
 #include "cpu/kvm/vm.hh"
 #endif
+#include "cpu/base.hh"
 #include "cpu/thread_context.hh"
 #include "debug/Loader.hh"
 #include "debug/WorkItems.hh"
@@ -221,13 +222,6 @@
 return false;
 }

-/**
- * Setting rgdb_wait to a positive integer waits for a remote debugger to
- * connect to that context ID before continuing.  This should really
-   be a parameter on the CPU object or something...
- */
-int rgdb_wait = -1;
-
 ContextID
 System::registerThreadContext(ThreadContext *tc, ContextID assigned)
 {
@@ -259,9 +253,13 @@
 GDBListener *gdbl = new GDBListener(rgdb, port + id);
 gdbl->listen();

-if (rgdb_wait != -1 && rgdb_wait == id)
-gdbl->accept();
+BaseCPU *cpu = tc->getCpuPtr();
+if (cpu->waitForRemoteGDB()) {
+inform("%s: Waiting for a remote GDB connection on port %d.\n",
+   cpu->name(), gdbl->getPort());

+gdbl->accept();
+}
 if (remoteGDB.size() <= id) {
 remoteGDB.resize(id + 1);
 }

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I4d62c68ce9adf69344bccbb44f66e30b33715a1c
Gerrit-Change-Number: 3963
Gerrit-PatchSet: 4
Gerrit-Owner: Andreas Sandberg 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Anthony Gutierrez 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
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[gem5-dev] Change in public/gem5[master]: dev-arm: Add ID registers to the GIC model

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/3961 )


Change subject: dev-arm: Add ID registers to the GIC model
..

dev-arm: Add ID registers to the GIC model

Implement GICD_IIDR, GICC_IIDR, GICD_PIDR0, GICD_PIDR1, GICD_PIDR2,
and GICD_PIDR3.

Change-Id: I4f6b5a6303907226e7d8e2f677543b3868c02e7b
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/3961
---
M src/dev/arm/gic_pl390.cc
M src/dev/arm/gic_pl390.hh
2 files changed, 26 insertions(+), 1 deletion(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/dev/arm/gic_pl390.cc b/src/dev/arm/gic_pl390.cc
index 93aaf5c..126431f 100644
--- a/src/dev/arm/gic_pl390.cc
+++ b/src/dev/arm/gic_pl390.cc
@@ -258,6 +258,18 @@
 return (((sys->numRunningContexts() - 1) << 5) |
 (itLines/INT_BITS_MAX -1) |
 (haveGem5Extensions ? 0x100 : 0x0));
+  case GICD_PIDR0:
+//ARM defined DevID
+return (GICD_400_PIDR_VALUE & 0xFF);
+  case GICD_PIDR1:
+return ((GICD_400_PIDR_VALUE >> 8) & 0xFF);
+  case GICD_PIDR2:
+return ((GICD_400_PIDR_VALUE >> 16) & 0xFF);
+  case GICD_PIDR3:
+return ((GICD_400_PIDR_VALUE >> 24) & 0xFF);
+  case GICD_IIDR:
+ /* revision id is resorted to 1 and variant to 0*/
+return GICD_400_IIDR_VALUE;
   default:
 panic("Tried to read Gic distributor at offset %#x\n", daddr);
 break;
@@ -287,7 +299,7 @@
 {
 switch(daddr) {
   case GICC_IIDR:
-return 0;
+return GICC_400_IIDR_VALUE;
   case GICC_CTLR:
 return cpuEnabled[ctx];
   case GICC_PMR:
diff --git a/src/dev/arm/gic_pl390.hh b/src/dev/arm/gic_pl390.hh
index 3b35b59..60d9ae3 100644
--- a/src/dev/arm/gic_pl390.hh
+++ b/src/dev/arm/gic_pl390.hh
@@ -67,10 +67,23 @@
 GICD_TYPER = 0x004, // controller type
 GICD_IIDR  = 0x008, // implementer id
 GICD_SGIR  = 0xf00, // software generated interrupt
+GICD_PIDR0 = 0xfe0, // distributor peripheral ID0
+GICD_PIDR1 = 0xfe4, // distributor peripheral ID1
+GICD_PIDR2 = 0xfe8, // distributor peripheral ID2
+GICD_PIDR3 = 0xfec, // distributor peripheral ID3

 DIST_SIZE  = 0xfff
 };

+/**
+ * As defined in:
+ * "ARM Generic Interrupt Controller Architecture" version 2.0
+ * "CoreLink GIC-400 Generic Interrupt Controller" revision r0p1
+ */
+static constexpr uint32_t  GICD_400_PIDR_VALUE = 0x002bb490;
+static constexpr uint32_t  GICD_400_IIDR_VALUE = 0x200143B;
+static constexpr uint32_t  GICC_400_IIDR_VALUE = 0x202143B;
+
 static const AddrRange GICD_IGROUPR;// interrupt group  
(unimplemented)

 static const AddrRange GICD_ISENABLER;  // interrupt set enable
 static const AddrRange GICD_ICENABLER;  // interrupt clear enable

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I4f6b5a6303907226e7d8e2f677543b3868c02e7b
Gerrit-Change-Number: 3961
Gerrit-PatchSet: 3
Gerrit-Owner: Andreas Sandberg 
Gerrit-Reviewer: Andreas Sandberg 
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[gem5-dev] Change in public/gem5[master]: cpu, sim: Add param to force CPUs to wait for GDB

[Andreas Sandberg (Gerrit)]

Hello Gabe Black, Anthony Gutierrez, Jason Lowe-Power,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/3963

to look at the new patch set (#3).

Change subject: cpu, sim: Add param to force CPUs to wait for GDB
..

cpu, sim: Add param to force CPUs to wait for GDB

By setting the BaseCPU parameter wait_for_dbg_connection, the GDB
server blocks during initialisation waiting for the remote debugger to
connect before starting the simulated CPU.

Change-Id: I4d62c68ce9adf69344bccbb44f66e30b33715a1c
[ Update info message to include remote GDB port, rename param. ]
Signed-off-by: Andreas Sandberg 
---
M src/base/remote_gdb.cc
M src/base/remote_gdb.hh
M src/cpu/BaseCPU.py
M src/cpu/base.cc
M src/cpu/base.hh
M src/sim/system.cc
6 files changed, 30 insertions(+), 9 deletions(-)


--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I4d62c68ce9adf69344bccbb44f66e30b33715a1c
Gerrit-Change-Number: 3963
Gerrit-PatchSet: 3
Gerrit-Owner: Andreas Sandberg 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Anthony Gutierrez 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
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[gem5-dev] Change in public/gem5[master]: arch-arm: Support PMU evens in the 0x4000-0x4040 range

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/3960 )


Change subject: arch-arm: Support PMU evens in the 0x4000-0x4040 range
..

arch-arm: Support PMU evens in the 0x4000-0x4040 range

ARMv8.1 added a second architected event range, 0x4000-0x4040. Events
in this range are discovered using the high word of PMCEID{0,1}_EL0

Change-Id: I4cd01264230e5da4c841268a7cf3e6bd307c7180
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/3960
---
M src/arch/arm/ArmPMU.py
M src/arch/arm/pmu.cc
M src/arch/arm/pmu.hh
3 files changed, 57 insertions(+), 18 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/arm/ArmPMU.py b/src/arch/arm/ArmPMU.py
index 3802e49..4292fd5 100644
--- a/src/arch/arm/ArmPMU.py
+++ b/src/arch/arm/ArmPMU.py
@@ -1,5 +1,5 @@
 # -*- mode:python -*-
-# Copyright (c) 2009-2014 ARM Limited
+# Copyright (c) 2009-2014, 2017 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -97,7 +97,7 @@

 # 0x01: L1I_CACHE_REFILL
 self.addEventProbe(0x02, itb, "Refills")
-# 0x03: L2D_CACHE_REFILL
+# 0x03: L1D_CACHE_REFILL
 # 0x04: L1D_CACHE
 self.addEventProbe(0x05, dtb, "Refills")
 self.addEventProbe(0x06, cpu, "RetiredLoads")
@@ -127,6 +127,22 @@
 # 0x1E: CHAIN
 # 0x1F: L1D_CACHE_ALLOCATE
 # 0x20: L2D_CACHE_ALLOCATE
+# 0x21: BR_RETIRED
+# 0x22: BR_MIS_PRED_RETIRED
+# 0x23: STALL_FRONTEND
+# 0x24: STALL_BACKEND
+# 0x25: L1D_TLB
+# 0x26: L1I_TLB
+# 0x27: L2I_CACHE
+# 0x28: L2I_CACHE_REFILL
+# 0x29: L3D_CACHE_ALLOCATE
+# 0x2A: L3D_CACHE_REFILL
+# 0x2B: L3D_CACHE
+# 0x2C: L3D_CACHE_WB
+# 0x2D: L2D_TLB_REFILL
+# 0x2E: L2I_TLB_REFILL
+# 0x2F: L2D_TLB
+# 0x30: L2I_TLB

 platform = Param.Platform(Parent.any, "Platform this device is part  
of.")

 eventCounters = Param.Int(31, "Number of supported PMU counters")
diff --git a/src/arch/arm/pmu.cc b/src/arch/arm/pmu.cc
index ac2f475..14b1b50 100644
--- a/src/arch/arm/pmu.cc
+++ b/src/arch/arm/pmu.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2014 ARM Limited
+ * Copyright (c) 2011-2014, 2017 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -59,7 +59,7 @@
 : SimObject(p), BaseISADevice(),
   reg_pmcnten(0), reg_pmcr(0),
   reg_pmselr(0), reg_pminten(0), reg_pmovsr(0),
-  reg_pmceid(0),
+  reg_pmceid0(0),reg_pmceid1(0),
   clock_remainder(0),
   counters(p->eventCounters),
   reg_pmcr_conf(0),
@@ -94,10 +94,17 @@
 id, obj->name(), probe_name);
 pmuEventTypes.insert(std::make_pair(id, EventType(obj, probe_name)));

-// Flag the event as available in the PMCEID register if it is an
-// architected event.
-if (id < 0x40)
-reg_pmceid |= (ULL(1) << id);
+// Flag the event as available in the corresponding PMCEID register if  
it

+// is an architected event.
+if (id < 0x20) {
+reg_pmceid0 |= ((uint64_t)1) << id;
+} else if (id > 0x20 && id < 0x40) {
+reg_pmceid1 |= ((uint64_t)1) << (id - 0x20);
+} else if (id >= 0x4000 && id < 0x4020) {
+reg_pmceid0 |= ((uint64_t)1) << (id - 0x4000 + 32);
+} else if (id >= 0x4020 && id < 0x4040) {
+reg_pmceid1 |= ((uint64_t)1) << (id - 0x4020 + 32);
+}
 }

 void
@@ -154,7 +161,7 @@
   case MISCREG_PMSELR:
 reg_pmselr = val;
 return;
-
+  //TODO: implement MISCREF_PMCEID{2,3}
   case MISCREG_PMCEID0_EL0:
   case MISCREG_PMCEID0:
   case MISCREG_PMCEID1_EL0:
@@ -256,12 +263,17 @@
 return reg_pmselr;

   case MISCREG_PMCEID0_EL0:
-  case MISCREG_PMCEID0: // Common Event ID register
-return reg_pmceid & 0x;
+return reg_pmceid0;

   case MISCREG_PMCEID1_EL0:
+return reg_pmceid1;
+
+  //TODO: implement MISCREF_PMCEID{2,3}
+  case MISCREG_PMCEID0: // Common Event ID register
+return reg_pmceid0 & 0x;
+
   case MISCREG_PMCEID1: // Common Event ID register
-return (reg_pmceid >> 32) & 0x;
+return reg_pmceid1 & 0x;

   case MISCREG_PMCCNTR_EL0:
 return cycleCounter.value;
@@ -522,7 +534,8 @@
 SERIALIZE_SCALAR(reg_pmselr);
 SERIALIZE_SCALAR(reg_pminten);
 SERIALIZE_SCALAR(reg_pmovsr);
-SERIALIZE_SCALAR(reg_pmceid);
+SERIALIZE_SCALAR(reg_pmceid0);
+SERIALIZE_SCALAR(reg_pmceid1);
 SERIALIZE_SCALAR(clock_remainder);

 for (size_t i = 0; i < counters.size(); ++i)
@@ -541,7 +554,16 @@
 UNSERIALIZE_SCALAR(reg_pmselr);
 UNSERIALIZE_SCALAR(reg_pminten);
 

[gem5-dev] Change in public/gem5[master]: dev-arm: Don't unconditionally overwrite bootloader params

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/3967 )


Change subject: dev-arm: Don't unconditionally overwrite bootloader params
..

dev-arm: Don't unconditionally overwrite bootloader params

The bootloader arguments were previously defaulting to a predetermined
value even if initialized elsewhere in the platform config script.
This commit fixes this issue by not calling the default initialization
routine if the bootloader is already defined.

Change-Id: Id80af4762b52dc036da29430b2795bb30970a349
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/3967
---
M src/dev/arm/RealView.py
1 file changed, 6 insertions(+), 3 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index 323c14c..51aa1cf 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -739,7 +739,8 @@
 self.nvmem = SimpleMemory(range = AddrRange('64MB'),
   conf_table_reported = False)
 self.nvmem.port = mem_bus.master
-cur_sys.boot_loader = loc('boot_emm.arm')
+if not cur_sys.boot_loader:
+cur_sys.boot_loader = loc('boot_emm.arm')
 cur_sys.atags_addr = 0x800
 cur_sys.load_addr_mask = 0xfff
 cur_sys.load_offset = 0x8000
@@ -756,7 +757,8 @@
 self.nvmem = SimpleMemory(range=AddrRange(0, size='64MB'),
   conf_table_reported=False)
 self.nvmem.port = mem_bus.master
-cur_sys.boot_loader = loc('boot_emm.arm64')
+if not cur_sys.boot_loader:
+cur_sys.boot_loader = loc('boot_emm.arm64')
 cur_sys.atags_addr = 0x800
 cur_sys.load_addr_mask = 0xfff
 cur_sys.load_offset = 0x8000
@@ -927,7 +929,8 @@
 self.nvmem = SimpleMemory(range=AddrRange(0, size='64MB'),
   conf_table_reported=False)
 self.nvmem.port = mem_bus.master
-cur_sys.boot_loader = [ loc('boot_emm.arm64'), loc('boot_emm.arm')  
]

+if not cur_sys.boot_loader:
+cur_sys.boot_loader = [ loc('boot_emm.arm64'),  
loc('boot_emm.arm') ]

 cur_sys.atags_addr = 0x800
 # the old load_add_mask 0xfff works for 32-bit kernel
 # but not the 64-bit one. The new value 0x7ff works for both

--
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Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: Id80af4762b52dc036da29430b2795bb30970a349
Gerrit-Change-Number: 3967
Gerrit-PatchSet: 4
Gerrit-Owner: Andreas Sandberg 
Gerrit-Reviewer: Andreas Sandberg 
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[gem5-dev] Change in public/gem5[master]: dev: Fix OnIdle test in DmaReadFifo

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/3966 )


Change subject: dev: Fix OnIdle test in DmaReadFifo
..

dev: Fix OnIdle test in DmaReadFifo

OnIdle() is never called since DMA active check is completely
opposite to what it should be. old active status should be 'true'
and new active status should be false for OnIdle to be called

Change-Id: I94eca50edbe96113190837c7f6e50a0d061158a6
Reported-by: Rohit Kurup 
Signed-off-by: Rohit Kurup 
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/3966
Reviewed-by: Michael LeBeane 
---
M src/dev/dma_device.cc
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  Michael LeBeane: Looks good to me, approved



diff --git a/src/dev/dma_device.cc b/src/dev/dma_device.cc
index a78819a..f6f751c 100644
--- a/src/dev/dma_device.cc
+++ b/src/dev/dma_device.cc
@@ -438,7 +438,7 @@
 handlePending();
 resumeFill();

-if (!old_active && isActive())
+if (old_active && !isActive())
 onIdle();
 }


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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I94eca50edbe96113190837c7f6e50a0d061158a6
Gerrit-Change-Number: 3966
Gerrit-PatchSet: 4
Gerrit-Owner: Andreas Sandberg 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Michael LeBeane 
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[gem5-dev] Change in public/gem5[master]: dev: Fix address type promotion issues in VirtIO devices

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/3968 )


Change subject: dev: Fix address type promotion issues in VirtIO devices
..

dev: Fix address type promotion issues in VirtIO devices

With the change we explicitly update the types for the VirtIO bit
masks to be Addr (uint64_t). By changing this, we ensure type
promotion where it is needed. Therefore, this fixes issues where, in
certain situations, address calculations were performed in 32-bits,
resulting in overflows.

Change-Id: I5c5c3f9a3f94e806812282da01268e18ae0d2d39
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/3968
---
M src/dev/virtio/base.hh
1 file changed, 3 insertions(+), 3 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/dev/virtio/base.hh b/src/dev/virtio/base.hh
index 89c281f..ed3b1b4 100644
--- a/src/dev/virtio/base.hh
+++ b/src/dev/virtio/base.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014, 2016 ARM Limited
+ * Copyright (c) 2014, 2016-2017 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -433,8 +433,8 @@
  * Page size used by VirtIO.\ It's hard-coded to 4096 bytes in
  * the spec for historical reasons.
  */
-static const unsigned ALIGN_BITS = 12;
-static const unsigned ALIGN_SIZE = 1 << ALIGN_BITS;
+static const Addr ALIGN_BITS = 12;
+static const Addr ALIGN_SIZE = 1 << ALIGN_BITS;
 /** @} */

   protected:

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I5c5c3f9a3f94e806812282da01268e18ae0d2d39
Gerrit-Change-Number: 3968
Gerrit-PatchSet: 4
Gerrit-Owner: Andreas Sandberg 
Gerrit-Reviewer: Andreas Sandberg 
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[gem5-dev] Change in public/gem5[master]: sim: Fix clashing stat names in TickedObject and Ticked

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/3964 )


Change subject: sim: Fix clashing stat names in TickedObject and Ticked
..

sim: Fix clashing stat names in TickedObject and Ticked

Change tickCycles numCycles stat name to totalTickCycles os as not to
clash with the name of the tickCycles stat of the same class.
Declared the params passed to the TickedObject constructer as const.
Call ClockedObject::regStats() from the TickedObject::regStats to
ensure the correct initialization of the base class (ClockedObject)
stats

Change-Id: I6cf5bbe10fa27f2ad0e31d9f70ec3be47fe41455
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/3964
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M src/sim/ticked_object.cc
M src/sim/ticked_object.hh
2 files changed, 6 insertions(+), 5 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved



diff --git a/src/sim/ticked_object.cc b/src/sim/ticked_object.cc
index 4cd0dc1..a9f3ace 100644
--- a/src/sim/ticked_object.cc
+++ b/src/sim/ticked_object.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2014 ARM Limited
+ * Copyright (c) 2013-2014, 2017 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -60,7 +60,7 @@
 {
 if (numCyclesLocal) {
 numCycles
-.name(object.name() + ".tickCycles")
+.name(object.name() + ".totalTickCycles")
 .desc("Number of cycles that the object ticked or was  
stopped");

 }

@@ -98,7 +98,7 @@
 lastStopped = Cycles(lastStoppedUint);
 }

-TickedObject::TickedObject(TickedObjectParams *params,
+TickedObject::TickedObject(const TickedObjectParams *params,
 Event::Priority priority) :
 ClockedObject(params),
 /* Make numCycles in Ticked */
@@ -109,6 +109,7 @@
 TickedObject::regStats()
 {
 Ticked::regStats();
+ClockedObject::regStats();
 }

 void
diff --git a/src/sim/ticked_object.hh b/src/sim/ticked_object.hh
index d8b69a3..3ba0045 100644
--- a/src/sim/ticked_object.hh
+++ b/src/sim/ticked_object.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2014 ARM Limited
+ * Copyright (c) 2013-2014, 2017 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -190,7 +190,7 @@
 class TickedObject : public ClockedObject, public Ticked
 {
   public:
-TickedObject(TickedObjectParams *params,
+TickedObject(const TickedObjectParams *params,
 Event::Priority priority = Event::CPU_Tick_Pri);

 /** Disambiguate to make these functions overload correctly */

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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I6cf5bbe10fa27f2ad0e31d9f70ec3be47fe41455
Gerrit-Change-Number: 3964
Gerrit-PatchSet: 2
Gerrit-Owner: Andreas Sandberg 
Gerrit-Reviewer: Andreas Sandberg 
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[gem5-dev] Change in public/gem5[master]: kvm, arm: don't create interrupt events while saving GIC state

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/3661 )


Change subject: kvm, arm: don't create interrupt events while saving GIC  
state

..

kvm, arm: don't create interrupt events while saving GIC state

If an interrupt was pending according to Kvm state during a drain,
the Pl390 model would create an interrupt event that could not be
serviced, preventing the system from draining.  The proper behavior
is for the Pl390 not actively being used for simulation to just skip
the GIC state machine that delivers interrupts.

Change-Id: Icb37e7e992f1fb441a9b3a26daa1bb5a6fe19228
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/3661
Maintainer: Andreas Sandberg 
---
M src/arch/arm/kvm/gic.cc
M src/arch/arm/kvm/gic.hh
M src/dev/arm/gic_pl390.cc
M src/dev/arm/gic_pl390.hh
4 files changed, 24 insertions(+), 1 deletion(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/arm/kvm/gic.cc b/src/arch/arm/kvm/gic.cc
index ce3baa5..d490265 100644
--- a/src/arch/arm/kvm/gic.cc
+++ b/src/arch/arm/kvm/gic.cc
@@ -292,6 +292,17 @@
 }

 void
+MuxingKvmGic::updateIntState(int hint)
+{
+// During Kvm->Pl390 state transfer, writes to the Pl390 will call
+// updateIntState() which can post an interrupt.  Since we're only
+// using the Pl390 model for holding state in this circumstance, we
+// short-circuit this behavior, as the Pl390 is not actually active.
+if (!usingKvm)
+return Pl390::updateIntState(hint);
+}
+
+void
 MuxingKvmGic::copyDistRegister(BaseGicRegisters* from, BaseGicRegisters*  
to,

ContextID ctx, Addr daddr)
 {
diff --git a/src/arch/arm/kvm/gic.hh b/src/arch/arm/kvm/gic.hh
index ee04088..5447e6a 100644
--- a/src/arch/arm/kvm/gic.hh
+++ b/src/arch/arm/kvm/gic.hh
@@ -194,6 +194,9 @@
 void sendPPInt(uint32_t num, uint32_t cpu) override;
 void clearPPInt(uint32_t num, uint32_t cpu) override;

+  protected: // Pl390
+void updateIntState(int hint) override;
+
   protected:
 /** System this interrupt controller belongs to */
 System 
diff --git a/src/dev/arm/gic_pl390.cc b/src/dev/arm/gic_pl390.cc
index 7b63306..93aaf5c 100644
--- a/src/dev/arm/gic_pl390.cc
+++ b/src/dev/arm/gic_pl390.cc
@@ -871,6 +871,14 @@
 }
 }

+
+void
+Pl390::drainResume()
+{
+// There may be pending interrupts if checkpointed from Kvm; post them.
+updateIntState(-1);
+}
+
 void
 Pl390::serialize(CheckpointOut ) const
 {
diff --git a/src/dev/arm/gic_pl390.hh b/src/dev/arm/gic_pl390.hh
index 5c8a712..3b35b59 100644
--- a/src/dev/arm/gic_pl390.hh
+++ b/src/dev/arm/gic_pl390.hh
@@ -318,7 +318,7 @@
 /** See if some processor interrupt flags need to be enabled/disabled
  * @param hint which set of interrupts needs to be checked
  */
-void updateIntState(int hint);
+virtual void updateIntState(int hint);

 /** Update the register that records priority of the highest priority
  *  active interrupt*/
@@ -368,6 +368,7 @@
 ~Pl390();

 DrainState drain() override;
+void drainResume() override;

 void serialize(CheckpointOut ) const override;
 void unserialize(CheckpointIn ) override;

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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: Icb37e7e992f1fb441a9b3a26daa1bb5a6fe19228
Gerrit-Change-Number: 3661
Gerrit-PatchSet: 3
Gerrit-Owner: Curtis Dunham 
Gerrit-Reviewer: Andreas Sandberg 
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[gem5-dev] Change in public/gem5[master]: kvm, arm: don't create interrupt events while saving GIC state

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has uploaded a new patch set (#2) to the change originally  
created by Curtis Dunham. ( https://gem5-review.googlesource.com/3661 )


Change subject: kvm, arm: don't create interrupt events while saving GIC  
state

..

kvm, arm: don't create interrupt events while saving GIC state

If an interrupt was pending according to Kvm state during a drain,
the Pl390 model would create an interrupt event that could not be
serviced, preventing the system from draining.  The proper behavior
is for the Pl390 not actively being used for simulation to just skip
the GIC state machine that delivers interrupts.

Change-Id: Icb37e7e992f1fb441a9b3a26daa1bb5a6fe19228
Reviewed-by: Andreas Sandberg 
---
M src/arch/arm/kvm/gic.cc
M src/arch/arm/kvm/gic.hh
M src/dev/arm/gic_pl390.cc
M src/dev/arm/gic_pl390.hh
4 files changed, 24 insertions(+), 1 deletion(-)


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Gerrit-Change-Id: Icb37e7e992f1fb441a9b3a26daa1bb5a6fe19228
Gerrit-Change-Number: 3661
Gerrit-PatchSet: 2
Gerrit-Owner: Curtis Dunham 
Gerrit-Reviewer: Andreas Sandberg 
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[gem5-dev] Change in public/gem5[master]: cpu, sim: Add param to force CPUs to wait for GDB

[Andreas Sandberg (Gerrit)]

Hello Gabe Black, Anthony Gutierrez, Jason Lowe-Power,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/3963

to look at the new patch set (#2).

Change subject: cpu, sim: Add param to force CPUs to wait for GDB
..

cpu, sim: Add param to force CPUs to wait for GDB

By setting the BaseCPU parameter wait_for_dbg_connection, the GDB
server blocks during initialisation waiting for the remote debugger to
connect before starting the simulated CPU.

Change-Id: I4d62c68ce9adf69344bccbb44f66e30b33715a1c
[ Update info message to include remote GDB port, rename param. ]
Signed-off-by: Andreas Sandberg 
---
M src/base/remote_gdb.cc
M src/base/remote_gdb.hh
M src/cpu/BaseCPU.py
M src/cpu/base.cc
M src/cpu/base.hh
M src/sim/system.cc
6 files changed, 30 insertions(+), 9 deletions(-)


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Gerrit-Change-Id: I4d62c68ce9adf69344bccbb44f66e30b33715a1c
Gerrit-Change-Number: 3963
Gerrit-PatchSet: 2
Gerrit-Owner: Andreas Sandberg 
Gerrit-Reviewer: Anthony Gutierrez 
Gerrit-Reviewer: Gabe Black 
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[gem5-dev] Change in public/gem5[master]: kvm, arm: Don't forward IRQ/FIQ when using the kernel's GIC

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/3660 )


Change subject: kvm, arm: Don't forward IRQ/FIQ when using the kernel's GIC
..

kvm, arm: Don't forward IRQ/FIQ when using the kernel's GIC

The BaseArmKvmCPU is responsible for forwarding the IRQ and FIQ
signals from gem5's simulated GIC to KVM. However, these signals
shouldn't be used when the in-kernel GIC emulator is used.

Instead of delivering the interrupts to the guest, we should just
ignore them since any such pending interrupts are likely to be an
artifact of CPU switching or incorrect draining.

Change-Id: I083b72639384272157f92f44a6606bdf0be7413c
Signed-off-by: Andreas Sandberg 
Reviewed-by: Sudhanshu Jha 
Reviewed-by: Curtis Dunham 
Reviewed-on: https://gem5-review.googlesource.com/3660
---
M src/arch/arm/kvm/base_cpu.cc
M src/arch/arm/kvm/gic.cc
M src/cpu/kvm/vm.hh
3 files changed, 36 insertions(+), 12 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/arm/kvm/base_cpu.cc b/src/arch/arm/kvm/base_cpu.cc
index e25112c..7659650 100644
--- a/src/arch/arm/kvm/base_cpu.cc
+++ b/src/arch/arm/kvm/base_cpu.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012, 2015 ARM Limited
+ * Copyright (c) 2012, 2015, 2017 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -88,19 +88,30 @@
 Tick
 BaseArmKvmCPU::kvmRun(Tick ticks)
 {
-bool simFIQ(interrupts[0]->checkRaw(INT_FIQ));
-bool simIRQ(interrupts[0]->checkRaw(INT_IRQ));
+const bool simFIQ(interrupts[0]->checkRaw(INT_FIQ));
+const bool simIRQ(interrupts[0]->checkRaw(INT_IRQ));

-if (fiqAsserted != simFIQ) {
-fiqAsserted = simFIQ;
-DPRINTF(KvmInt, "KVM: Update FIQ state: %i\n", simFIQ);
-vm.setIRQLine(INTERRUPT_VCPU_FIQ(vcpuID), simFIQ);
+if (!vm.hasKernelIRQChip()) {
+if (fiqAsserted != simFIQ) {
+DPRINTF(KvmInt, "KVM: Update FIQ state: %i\n", simFIQ);
+vm.setIRQLine(INTERRUPT_VCPU_FIQ(vcpuID), simFIQ);
+}
+if (irqAsserted != simIRQ) {
+DPRINTF(KvmInt, "KVM: Update IRQ state: %i\n", simIRQ);
+vm.setIRQLine(INTERRUPT_VCPU_IRQ(vcpuID), simIRQ);
+}
+} else {
+warn_if(simFIQ && !fiqAsserted,
+"FIQ raised by the simulated interrupt controller " \
+"despite in-kernel GIC emulation. This is probably a  
bug.");

+
+warn_if(simIRQ && !irqAsserted,
+"IRQ raised by the simulated interrupt controller " \
+"despite in-kernel GIC emulation. This is probably a  
bug.");

 }
-if (irqAsserted != simIRQ) {
-irqAsserted = simIRQ;
-DPRINTF(KvmInt, "KVM: Update IRQ state: %i\n", simIRQ);
-vm.setIRQLine(INTERRUPT_VCPU_IRQ(vcpuID), simIRQ);
-}
+
+irqAsserted = simIRQ;
+fiqAsserted = simFIQ;

 return BaseKvmCPU::kvmRun(ticks);
 }
diff --git a/src/arch/arm/kvm/gic.cc b/src/arch/arm/kvm/gic.cc
index 498b79f..ce3baa5 100644
--- a/src/arch/arm/kvm/gic.cc
+++ b/src/arch/arm/kvm/gic.cc
@@ -54,6 +54,10 @@
   vm(_vm),
   kdev(vm.createDevice(KVM_DEV_TYPE_ARM_VGIC_V2))
 {
+// Tell the VM that we will emulate the GIC in the kernel. This
+// disables IRQ and FIQ handling in the KVM CPU model.
+vm.enableKernelIRQChip();
+
 kdev.setAttr(
 KVM_DEV_ARM_VGIC_GRP_ADDR, KVM_VGIC_V2_ADDR_TYPE_DIST, dist_addr);
 kdev.setAttr(
diff --git a/src/cpu/kvm/vm.hh b/src/cpu/kvm/vm.hh
index df2e411..e122bbf 100644
--- a/src/cpu/kvm/vm.hh
+++ b/src/cpu/kvm/vm.hh
@@ -351,6 +351,15 @@
  * Is in-kernel IRQ chip emulation enabled?
  */
 bool hasKernelIRQChip() const { return _hasKernelIRQChip; }
+
+/**
+ * Tell the VM and VCPUs to use an in-kernel IRQ chip for
+ * interrupt delivery.
+ *
+ * @note This is set automatically if the IRQ chip is created
+ * using the KvmVM::createIRQChip() API.
+ */
+void enableKernelIRQChip() { _hasKernelIRQChip = true; }
 /** @} */

 struct MemSlot

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Gerrit-MessageType: merged
Gerrit-Change-Id: I083b72639384272157f92f44a6606bdf0be7413c
Gerrit-Change-Number: 3660
Gerrit-PatchSet: 3
Gerrit-Owner: Curtis Dunham 
Gerrit-Reviewer: Andreas Sandberg 
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[gem5-dev] Change in public/gem5[master]: dev: Fix address type promotion issues in VirtIO devices

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has uploaded a new patch set (#2). (  
https://gem5-review.googlesource.com/3968 )


Change subject: dev: Fix address type promotion issues in VirtIO devices
..

dev: Fix address type promotion issues in VirtIO devices

With the change we explicitly update the types for the VirtIO bit
masks to be Addr (uint64_t). By changing this, we ensure type
promotion where it is needed. Therefore, this fixes issues where, in
certain situations, address calculations were performed in 32-bits,
resulting in overflows.

Change-Id: I5c5c3f9a3f94e806812282da01268e18ae0d2d39
Signed-off-by: Andreas Sandberg 
---
M src/dev/virtio/base.hh
1 file changed, 3 insertions(+), 3 deletions(-)


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Gerrit-Change-Id: I5c5c3f9a3f94e806812282da01268e18ae0d2d39
Gerrit-Change-Number: 3968
Gerrit-PatchSet: 2
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Gerrit-Reviewer: Andreas Sandberg 
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[gem5-dev] Change in public/gem5[master]: dev: Fix OnIdle test in DmaReadFifo

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has uploaded a new patch set (#2). (  
https://gem5-review.googlesource.com/3966 )


Change subject: dev: Fix OnIdle test in DmaReadFifo
..

dev: Fix OnIdle test in DmaReadFifo

OnIdle() is never called since DMA active check is completely
opposite to what it should be. old active status should be 'true'
and new active status should be false for OnIdle to be called

Change-Id: I94eca50edbe96113190837c7f6e50a0d061158a6
Reported-by: Rohit Kurup 
Signed-off-by: Rohit Kurup 
Signed-off-by: Andreas Sandberg 
---
M src/dev/dma_device.cc
1 file changed, 1 insertion(+), 1 deletion(-)


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Gerrit-Change-Id: I94eca50edbe96113190837c7f6e50a0d061158a6
Gerrit-Change-Number: 3966
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[gem5-dev] Change in public/gem5[master]: dev-arm: Don't unconditionally overwrite bootloader params

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has uploaded a new patch set (#2). (  
https://gem5-review.googlesource.com/3967 )


Change subject: dev-arm: Don't unconditionally overwrite bootloader params
..

dev-arm: Don't unconditionally overwrite bootloader params

The bootloader arguments were previously defaulting to a predetermined
value even if initialized elsewhere in the platform config script.
This commit fixes this issue by not calling the default initialization
routine if the bootloader is already defined.

Change-Id: Id80af4762b52dc036da29430b2795bb30970a349
Signed-off-by: Andreas Sandberg 
---
M src/dev/arm/RealView.py
1 file changed, 6 insertions(+), 3 deletions(-)


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[gem5-dev] Change in public/gem5[master]: sim: Prevent seqfault in the wakeCpu m5op if id is invalid

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/3965



Change subject: sim: Prevent seqfault in the wakeCpu m5op if id is invalid
..

sim: Prevent seqfault in the wakeCpu m5op if id is invalid

Change-Id: I86229cedb206e10326cdee3f09a5c871e49c8d48
Signed-off-by: Andreas Sandberg 
---
M src/sim/pseudo_inst.cc
1 file changed, 8 insertions(+), 1 deletion(-)



diff --git a/src/sim/pseudo_inst.cc b/src/sim/pseudo_inst.cc
index 8c2d26b..778675f 100644
--- a/src/sim/pseudo_inst.cc
+++ b/src/sim/pseudo_inst.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2012, 2015 ARM Limited
+ * Copyright (c) 2010-2012, 2015, 2017 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -285,6 +285,13 @@
 {
 DPRINTF(PseudoInst, "PseudoInst::wakeCPU(%i)\n", cpuid);
 System *sys = tc->getSystemPtr();
+
+if (sys->numContexts() <= cpuid) {
+warn("PseudoInst::wakeCPU(%i), cpuid greater than number of  
contexts"

+ "(%i)\n",cpuid, sys->numContexts());
+return;
+}
+
 ThreadContext *other_tc = sys->threadContexts[cpuid];
 if (other_tc->status() == ThreadContext::Suspended)
 other_tc->activate();

--
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[gem5-dev] Change in public/gem5[master]: sim: Fix clashing stat names in TickedObject and Ticked

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/3964



Change subject: sim: Fix clashing stat names in TickedObject and Ticked
..

sim: Fix clashing stat names in TickedObject and Ticked

Change tickCycles numCycles stat name to totalTickCycles os as not to
clash with the name of the tickCycles stat of the same class.
Declared the params passed to the TickedObject constructer as const.
Call ClockedObject::regStats() from the TickedObject::regStats to
ensure the correct initialization of the base class (ClockedObject)
stats

Change-Id: I6cf5bbe10fa27f2ad0e31d9f70ec3be47fe41455
Signed-off-by: Andreas Sandberg 
---
M src/sim/ticked_object.cc
M src/sim/ticked_object.hh
2 files changed, 6 insertions(+), 5 deletions(-)



diff --git a/src/sim/ticked_object.cc b/src/sim/ticked_object.cc
index 4cd0dc1..a9f3ace 100644
--- a/src/sim/ticked_object.cc
+++ b/src/sim/ticked_object.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2014 ARM Limited
+ * Copyright (c) 2013-2014, 2017 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -60,7 +60,7 @@
 {
 if (numCyclesLocal) {
 numCycles
-.name(object.name() + ".tickCycles")
+.name(object.name() + ".totalTickCycles")
 .desc("Number of cycles that the object ticked or was  
stopped");

 }

@@ -98,7 +98,7 @@
 lastStopped = Cycles(lastStoppedUint);
 }

-TickedObject::TickedObject(TickedObjectParams *params,
+TickedObject::TickedObject(const TickedObjectParams *params,
 Event::Priority priority) :
 ClockedObject(params),
 /* Make numCycles in Ticked */
@@ -109,6 +109,7 @@
 TickedObject::regStats()
 {
 Ticked::regStats();
+ClockedObject::regStats();
 }

 void
diff --git a/src/sim/ticked_object.hh b/src/sim/ticked_object.hh
index d8b69a3..3ba0045 100644
--- a/src/sim/ticked_object.hh
+++ b/src/sim/ticked_object.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2014 ARM Limited
+ * Copyright (c) 2013-2014, 2017 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -190,7 +190,7 @@
 class TickedObject : public ClockedObject, public Ticked
 {
   public:
-TickedObject(TickedObjectParams *params,
+TickedObject(const TickedObjectParams *params,
 Event::Priority priority = Event::CPU_Tick_Pri);

 /** Disambiguate to make these functions overload correctly */

--
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[gem5-dev] Change in public/gem5[master]: dev-arm: Don't unconditionally overwrite bootloader params

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/3967



Change subject: dev-arm: Don't unconditionally overwrite bootloader params
..

dev-arm: Don't unconditionally overwrite bootloader params

The bootloader arguments were previously defaulting to a predetermined
value even if initialized elsewhere in the platform config script.
This commit fixes this issue by not calling the default initialization
routine if the bootloader is already defined.

Change-Id: Id80af4762b52dc036da29430b2795bb30970a349
Signed-off-by: Andreas Sandberg 
---
M src/dev/arm/RealView.py
1 file changed, 6 insertions(+), 3 deletions(-)



diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index 323c14c..51aa1cf 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -739,7 +739,8 @@
 self.nvmem = SimpleMemory(range = AddrRange('64MB'),
   conf_table_reported = False)
 self.nvmem.port = mem_bus.master
-cur_sys.boot_loader = loc('boot_emm.arm')
+if not cur_sys.boot_loader:
+cur_sys.boot_loader = loc('boot_emm.arm')
 cur_sys.atags_addr = 0x800
 cur_sys.load_addr_mask = 0xfff
 cur_sys.load_offset = 0x8000
@@ -756,7 +757,8 @@
 self.nvmem = SimpleMemory(range=AddrRange(0, size='64MB'),
   conf_table_reported=False)
 self.nvmem.port = mem_bus.master
-cur_sys.boot_loader = loc('boot_emm.arm64')
+if not cur_sys.boot_loader:
+cur_sys.boot_loader = loc('boot_emm.arm64')
 cur_sys.atags_addr = 0x800
 cur_sys.load_addr_mask = 0xfff
 cur_sys.load_offset = 0x8000
@@ -927,7 +929,8 @@
 self.nvmem = SimpleMemory(range=AddrRange(0, size='64MB'),
   conf_table_reported=False)
 self.nvmem.port = mem_bus.master
-cur_sys.boot_loader = [ loc('boot_emm.arm64'), loc('boot_emm.arm')  
]

+if not cur_sys.boot_loader:
+cur_sys.boot_loader = [ loc('boot_emm.arm64'),  
loc('boot_emm.arm') ]

 cur_sys.atags_addr = 0x800
 # the old load_add_mask 0xfff works for 32-bit kernel
 # but not the 64-bit one. The new value 0x7ff works for both

--
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[gem5-dev] Change in public/gem5[master]: dev: Fix OnIdle test in DmaReadFifo

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/3966



Change subject: dev: Fix OnIdle test in DmaReadFifo
..

dev: Fix OnIdle test in DmaReadFifo

OnIdle() is never called since DMA active check is completely
opposite to what it should be. old active status should be 'true'
and new active status should be false for OnIdle to be called

Signed-off-by:Rohit Kurup 
Reported-by:Rohit Kurup 

Change-Id: I94eca50edbe96113190837c7f6e50a0d061158a6
Signed-off-by: Andreas Sandberg 
---
M src/dev/dma_device.cc
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/dev/dma_device.cc b/src/dev/dma_device.cc
index a78819a..f6f751c 100644
--- a/src/dev/dma_device.cc
+++ b/src/dev/dma_device.cc
@@ -438,7 +438,7 @@
 handlePending();
 resumeFill();

-if (!old_active && isActive())
+if (old_active && !isActive())
 onIdle();
 }


--
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[gem5-dev] Change in public/gem5[master]: dev: Fix address type promotion issues in VirtIO devices

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/3968



Change subject: dev: Fix address type promotion issues in VirtIO devices
..

dev: Fix address type promotion issues in VirtIO devices

With the change we explicitly update the types for the VirtIO bit
masks to be Addr (uint64_t). By changing this, we ensure type
promotion where it is needed. Therefore, this fixes issues where, in
certain situations, address calculations were performed in 32-bits,
resulting in overflows.

Change-Id: I5c5c3f9a3f94e806812282da01268e18ae0d2d39
Signed-off-by: Andreas Sandberg 
---
M src/dev/virtio/base.hh
1 file changed, 3 insertions(+), 3 deletions(-)



diff --git a/src/dev/virtio/base.hh b/src/dev/virtio/base.hh
index 89c281f..ed3b1b4 100644
--- a/src/dev/virtio/base.hh
+++ b/src/dev/virtio/base.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014, 2016 ARM Limited
+ * Copyright (c) 2014, 2016-2017 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -433,8 +433,8 @@
  * Page size used by VirtIO.\ It's hard-coded to 4096 bytes in
  * the spec for historical reasons.
  */
-static const unsigned ALIGN_BITS = 12;
-static const unsigned ALIGN_SIZE = 1 << ALIGN_BITS;
+static const Addr ALIGN_BITS = 12;
+static const Addr ALIGN_SIZE = 1 << ALIGN_BITS;
 /** @} */

   protected:

--
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[gem5-dev] Change in public/gem5[master]: cpu, sim: Add param to force CPUs to wait for GDB

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/3963



Change subject: cpu, sim: Add param to force CPUs to wait for GDB
..

cpu, sim: Add param to force CPUs to wait for GDB

By setting the BaseCPU parameter wait_for_dbg_connection, the GDB
server blocks during initialisation waiting for the remote debugger to
connect before starting the simulated CPU.

Change-Id: I4d62c68ce9adf69344bccbb44f66e30b33715a1c
Signed-off-by: Andreas Sandberg 
---
M src/cpu/BaseCPU.py
M src/cpu/base.cc
M src/cpu/base.hh
M src/sim/system.cc
4 files changed, 18 insertions(+), 9 deletions(-)



diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 550ba62..da5bd66 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -151,6 +151,9 @@
 profile = Param.Latency('0ns', "trace the kernel stack")
 do_quiesce = Param.Bool(True, "enable quiesce instructions")

+wait_for_dbg_connection = Param.Bool(False,
+"Wait for a remote debugger connection");
+
 workload = VectorParam.Process([], "processes to run")

 if buildEnv['TARGET_ISA'] == 'sparc':
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 6f460d3..020ba88 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -783,3 +783,9 @@
 functionEntryTick = curTick();
 }
 }
+
+bool
+BaseCPU::waitForRemoteDebugger() const
+{
+return params()->wait_for_dbg_connection;
+}
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 14dfc26..b583e18 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -589,6 +589,8 @@
 return [tid];
 }

+bool waitForRemoteDebugger() const;
+
 Cycles syscallRetryLatency;
 };

diff --git a/src/sim/system.cc b/src/sim/system.cc
index e46c356..f3f0271 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -58,6 +58,7 @@
 #include "cpu/kvm/base.hh"
 #include "cpu/kvm/vm.hh"
 #endif
+#include "cpu/base.hh"
 #include "cpu/thread_context.hh"
 #include "debug/Loader.hh"
 #include "debug/WorkItems.hh"
@@ -221,13 +222,6 @@
 return false;
 }

-/**
- * Setting rgdb_wait to a positive integer waits for a remote debugger to
- * connect to that context ID before continuing.  This should really
-   be a parameter on the CPU object or something...
- */
-int rgdb_wait = -1;
-
 ContextID
 System::registerThreadContext(ThreadContext *tc, ContextID assigned)
 {
@@ -259,9 +253,13 @@
 GDBListener *gdbl = new GDBListener(rgdb, port + id);
 gdbl->listen();

-if (rgdb_wait != -1 && rgdb_wait == id)
-gdbl->accept();
+BaseCPU *cpu = tc->getCpuPtr();
+if (cpu->waitForRemoteDebugger()) {
+inform("Waiting for a remote GDB connection to CPU with  
id %d\n",

+   tc->cpuId());

+gdbl->accept();
+}
 if (remoteGDB.size() <= id) {
 remoteGDB.resize(id + 1);
 }

--
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[gem5-dev] Change in public/gem5[master]: tests: Don't treat new stats as a cause for failures

[Andreas Sandberg (Gerrit)]

Hello Nikos Nikoleris,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/3962

to review the following change.


Change subject: tests: Don't treat new stats as a cause for failures
..

tests: Don't treat new stats as a cause for failures

We currently fail the stat diff stage of tests if there are new
stats. This is usually undesirable since this would require any change
that adds a stat to also update the regressions.

Change-Id: Ieadebac6fd17534e1b49b6b9a1d56f037a423325
Signed-off-by: Andreas Sandberg 
Reviewed-by: Nikos Nikoleris 
---
M tests/diff-out
M tests/testing/units.py
2 files changed, 12 insertions(+), 4 deletions(-)



diff --git a/tests/diff-out b/tests/diff-out
index c00d4f3..1eeac81 100755
--- a/tests/diff-out
+++ b/tests/diff-out
@@ -361,8 +361,12 @@
 }

 cleanup();
-# Exit code is 0 if all stats are found (with no extras) & no stats error,  
1 otherwise
-$status = ($missing_stats == 0 && $added_stats == 0 && $max_err_mag ==  
0.0) ? 0 : 1;

+# Exit codes:
+# 0 if all stats are found (with no extras) & no stats error
+# 1 if there are additional stats, but no stat errors
+# 2 otherwise
+$no_hard_errors = $missing_stats == 0 && $max_err_mag == 0.0;
+$status = $no_hard_errors ? ($added_stats == 0 ? 0 : 1) : 2;
 exit $status;

 sub cleanup
diff --git a/tests/testing/units.py b/tests/testing/units.py
index e8b87a0..220cf61 100644
--- a/tests/testing/units.py
+++ b/tests/testing/units.py
@@ -270,6 +270,10 @@
 self.stat_diff = os.path.join(_test_base, "diff-out")

 def _run(self):
+STATUS_OK = 0
+STATUS_NEW_STATS = 1
+STATUS_FAILED = 2
+
 stats = "stats.txt"

 cmd = [
@@ -281,9 +285,9 @@
stderr=subprocess.PIPE) as p:
 status, stdout, stderr = p.call()

-if status == 0:
+if status in (STATUS_OK, STATUS_NEW_STATS):
 return self.ok(stdout=stdout, stderr=stderr)
-if status == 1:
+elif status == STATUS_FAILED:
 return self.failure("Statistics mismatch",
 stdout=stdout, stderr=stderr)
 else:

--
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[gem5-dev] Change in public/gem5[master]: dev-arm: Add ID registers to the GIC model

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/3961



Change subject: dev-arm: Add ID registers to the GIC model
..

dev-arm: Add ID registers to the GIC model

Implement GICD_IIDR, GICC_IIDR, GICD_PIDR0, GICD_PIDR1, GICD_PIDR2,
and GICD_PIDR3.

Change-Id: I4f6b5a6303907226e7d8e2f677543b3868c02e7b
Signed-off-by: Andreas Sandberg 
---
M src/dev/arm/gic_pl390.cc
M src/dev/arm/gic_pl390.hh
2 files changed, 26 insertions(+), 1 deletion(-)



diff --git a/src/dev/arm/gic_pl390.cc b/src/dev/arm/gic_pl390.cc
index 7b63306..9131689 100644
--- a/src/dev/arm/gic_pl390.cc
+++ b/src/dev/arm/gic_pl390.cc
@@ -258,6 +258,18 @@
 return (((sys->numRunningContexts() - 1) << 5) |
 (itLines/INT_BITS_MAX -1) |
 (haveGem5Extensions ? 0x100 : 0x0));
+  case GICD_PIDR0:
+//ARM defined DevID
+return (GICD_400_PIDR_VALUE & 0xFF);
+  case GICD_PIDR1:
+return ((GICD_400_PIDR_VALUE >> 8) & 0xFF);
+  case GICD_PIDR2:
+return ((GICD_400_PIDR_VALUE >> 16) & 0xFF);
+  case GICD_PIDR3:
+return ((GICD_400_PIDR_VALUE >> 24) & 0xFF);
+  case GICD_IIDR:
+ /* revision id is resorted to 1 and variant to 0*/
+return GICD_400_IIDR_VALUE;
   default:
 panic("Tried to read Gic distributor at offset %#x\n", daddr);
 break;
@@ -287,7 +299,7 @@
 {
 switch(daddr) {
   case GICC_IIDR:
-return 0;
+return GICC_400_IIDR_VALUE;
   case GICC_CTLR:
 return cpuEnabled[ctx];
   case GICC_PMR:
diff --git a/src/dev/arm/gic_pl390.hh b/src/dev/arm/gic_pl390.hh
index 5c8a712..33cfc9a 100644
--- a/src/dev/arm/gic_pl390.hh
+++ b/src/dev/arm/gic_pl390.hh
@@ -67,10 +67,23 @@
 GICD_TYPER = 0x004, // controller type
 GICD_IIDR  = 0x008, // implementer id
 GICD_SGIR  = 0xf00, // software generated interrupt
+GICD_PIDR0 = 0xfe0, // distributor peripheral ID0
+GICD_PIDR1 = 0xfe4, // distributor peripheral ID1
+GICD_PIDR2 = 0xfe8, // distributor peripheral ID2
+GICD_PIDR3 = 0xfec, // distributor peripheral ID3

 DIST_SIZE  = 0xfff
 };

+/**
+ * As defined in:
+ * "ARM Generic Interrupt Controller Architecture" version 2.0
+ * "CoreLink GIC-400 Generic Interrupt Controller" revision r0p1
+ */
+static constexpr uint32_t  GICD_400_PIDR_VALUE = 0x002bb490;
+static constexpr uint32_t  GICD_400_IIDR_VALUE = 0x200143B;
+static constexpr uint32_t  GICC_400_IIDR_VALUE = 0x202143B;
+
 static const AddrRange GICD_IGROUPR;// interrupt group  
(unimplemented)

 static const AddrRange GICD_ISENABLER;  // interrupt set enable
 static const AddrRange GICD_ICENABLER;  // interrupt clear enable

--
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[gem5-dev] Change in public/gem5[master]: arch-arm: Support PMU evens in the 0x4000-0x4040 range

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/3960



Change subject: arch-arm: Support PMU evens in the 0x4000-0x4040 range
..

arch-arm: Support PMU evens in the 0x4000-0x4040 range

ARMv8.1 added a second architected event range, 0x4000-0x4040. Events
in this range are discovered using the high word of PMCEID{0,1}_EL0

Change-Id: I4cd01264230e5da4c841268a7cf3e6bd307c7180
Signed-off-by: Andreas Sandberg 
---
M src/arch/arm/ArmPMU.py
M src/arch/arm/pmu.cc
M src/arch/arm/pmu.hh
3 files changed, 57 insertions(+), 18 deletions(-)



diff --git a/src/arch/arm/ArmPMU.py b/src/arch/arm/ArmPMU.py
index 3802e49..4292fd5 100644
--- a/src/arch/arm/ArmPMU.py
+++ b/src/arch/arm/ArmPMU.py
@@ -1,5 +1,5 @@
 # -*- mode:python -*-
-# Copyright (c) 2009-2014 ARM Limited
+# Copyright (c) 2009-2014, 2017 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -97,7 +97,7 @@

 # 0x01: L1I_CACHE_REFILL
 self.addEventProbe(0x02, itb, "Refills")
-# 0x03: L2D_CACHE_REFILL
+# 0x03: L1D_CACHE_REFILL
 # 0x04: L1D_CACHE
 self.addEventProbe(0x05, dtb, "Refills")
 self.addEventProbe(0x06, cpu, "RetiredLoads")
@@ -127,6 +127,22 @@
 # 0x1E: CHAIN
 # 0x1F: L1D_CACHE_ALLOCATE
 # 0x20: L2D_CACHE_ALLOCATE
+# 0x21: BR_RETIRED
+# 0x22: BR_MIS_PRED_RETIRED
+# 0x23: STALL_FRONTEND
+# 0x24: STALL_BACKEND
+# 0x25: L1D_TLB
+# 0x26: L1I_TLB
+# 0x27: L2I_CACHE
+# 0x28: L2I_CACHE_REFILL
+# 0x29: L3D_CACHE_ALLOCATE
+# 0x2A: L3D_CACHE_REFILL
+# 0x2B: L3D_CACHE
+# 0x2C: L3D_CACHE_WB
+# 0x2D: L2D_TLB_REFILL
+# 0x2E: L2I_TLB_REFILL
+# 0x2F: L2D_TLB
+# 0x30: L2I_TLB

 platform = Param.Platform(Parent.any, "Platform this device is part  
of.")

 eventCounters = Param.Int(31, "Number of supported PMU counters")
diff --git a/src/arch/arm/pmu.cc b/src/arch/arm/pmu.cc
index ac2f475..14b1b50 100644
--- a/src/arch/arm/pmu.cc
+++ b/src/arch/arm/pmu.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2014 ARM Limited
+ * Copyright (c) 2011-2014, 2017 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -59,7 +59,7 @@
 : SimObject(p), BaseISADevice(),
   reg_pmcnten(0), reg_pmcr(0),
   reg_pmselr(0), reg_pminten(0), reg_pmovsr(0),
-  reg_pmceid(0),
+  reg_pmceid0(0),reg_pmceid1(0),
   clock_remainder(0),
   counters(p->eventCounters),
   reg_pmcr_conf(0),
@@ -94,10 +94,17 @@
 id, obj->name(), probe_name);
 pmuEventTypes.insert(std::make_pair(id, EventType(obj, probe_name)));

-// Flag the event as available in the PMCEID register if it is an
-// architected event.
-if (id < 0x40)
-reg_pmceid |= (ULL(1) << id);
+// Flag the event as available in the corresponding PMCEID register if  
it

+// is an architected event.
+if (id < 0x20) {
+reg_pmceid0 |= ((uint64_t)1) << id;
+} else if (id > 0x20 && id < 0x40) {
+reg_pmceid1 |= ((uint64_t)1) << (id - 0x20);
+} else if (id >= 0x4000 && id < 0x4020) {
+reg_pmceid0 |= ((uint64_t)1) << (id - 0x4000 + 32);
+} else if (id >= 0x4020 && id < 0x4040) {
+reg_pmceid1 |= ((uint64_t)1) << (id - 0x4020 + 32);
+}
 }

 void
@@ -154,7 +161,7 @@
   case MISCREG_PMSELR:
 reg_pmselr = val;
 return;
-
+  //TODO: implement MISCREF_PMCEID{2,3}
   case MISCREG_PMCEID0_EL0:
   case MISCREG_PMCEID0:
   case MISCREG_PMCEID1_EL0:
@@ -256,12 +263,17 @@
 return reg_pmselr;

   case MISCREG_PMCEID0_EL0:
-  case MISCREG_PMCEID0: // Common Event ID register
-return reg_pmceid & 0x;
+return reg_pmceid0;

   case MISCREG_PMCEID1_EL0:
+return reg_pmceid1;
+
+  //TODO: implement MISCREF_PMCEID{2,3}
+  case MISCREG_PMCEID0: // Common Event ID register
+return reg_pmceid0 & 0x;
+
   case MISCREG_PMCEID1: // Common Event ID register
-return (reg_pmceid >> 32) & 0x;
+return reg_pmceid1 & 0x;

   case MISCREG_PMCCNTR_EL0:
 return cycleCounter.value;
@@ -522,7 +534,8 @@
 SERIALIZE_SCALAR(reg_pmselr);
 SERIALIZE_SCALAR(reg_pminten);
 SERIALIZE_SCALAR(reg_pmovsr);
-SERIALIZE_SCALAR(reg_pmceid);
+SERIALIZE_SCALAR(reg_pmceid0);
+SERIALIZE_SCALAR(reg_pmceid1);
 SERIALIZE_SCALAR(clock_remainder);

 for (size_t i = 0; i < counters.size(); ++i)
@@ -541,7 +554,16 @@
 UNSERIALIZE_SCALAR(reg_pmselr);
 UNSERIALIZE_SCALAR(reg_pminten);
 UNSERIALIZE_SCALAR(reg_pmovsr);
-UNSERIALIZE_SCALAR(reg_pmceid);
+
+// Old checkpoints used to store the entire PMCEID value in a
+// 

[gem5-dev] Change in public/gem5[master]: arch: added generic vector register

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/2704 )


Change subject: arch: added generic vector register
..

arch: added generic vector register

This commit adds a new generic vector register to have a cleaner
implementation of SIMD ISAs.

Nathanael's idea, Rekai's implementation.

Change-Id: I60b250bba6423153b7e04d2e6988d517a70a3e6b
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/2704
Reviewed-by: Anthony Gutierrez 
Reviewed-by: Tony Gutierrez 
Maintainer: Andreas Sandberg 
---
A src/arch/generic/vec_reg.hh
1 file changed, 648 insertions(+), 0 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  Tony Gutierrez: Looks good to me, approved
  Anthony Gutierrez: Looks good to me, approved



diff --git a/src/arch/generic/vec_reg.hh b/src/arch/generic/vec_reg.hh
new file mode 100644
index 000..7a993ea
--- /dev/null
+++ b/src/arch/generic/vec_reg.hh
@@ -0,0 +1,648 @@
+/*
+ * Copyright (c) 2015-2016 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Giacomo Gabrielli
+ *  Nathanael Premillieu
+ *  Rekai Gonzalez
+ */
+
+/** \file arch/generic/vec_reg.hh
+ * Vector Registers layout specification.
+ *
+ * This register type is to be used to model the SIMD registers.
+ * It takes into account the possibility that different architectural names
+ * may overlap (like for ARMv8 AArch32 for example).
+ *
+ * The design is having a basic vector register container that holds the
+ * bytes, unaware of anything else. This is implemented by VecRegContainer.
+ * As the (maximum) length of the physical vector register is a  
compile-time

+ * constant, it is defined as a template parameter.
+ *
+ * This file also describes two views of the container that have semantic
+ * information about the bytes. The first of this views is VecRegT.
+ *A VecRegT is a view of a VecRegContainer (by reference). The VecRegT  
has

+ *a type (VecElem) to which bytes are casted, and the amount of such
+ *elements that the vector contains (NumElems). The size of a view,
+ *calculated as sizeof(VecElem) * NumElems must match the size of the
+ *underlying container. As VecRegT has some degree of type information  
it

+ *has vector semantics, and defines the index operator ([]) to get
+ *references to particular bytes understood as a VecElem.
+ * The second view of a container implemented in this file is VecLaneT,  
which

+ * is a view of a subset of the container.
+ *A VecLaneT is a view of a lane of a vector register, where a lane is
+ *identified by a type (VecElem) and an index (although the view is
+ *unaware of its index). Operations 

[gem5-dev] Change in public/gem5[master]: cpu: Physical register structural + flat indexing

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/2701 )


Change subject: cpu: Physical register structural + flat indexing
..

cpu: Physical register structural + flat indexing

Mimic the changes done on the architectural register indexes on the
physical register indexes. This is specific to the O3 model. The
structure, called PhysRegId, contains a register class, a register
index and a flat register index. The flat register index is kept
because it is useful in some cases where the type of register is not
important (dependency graph and scoreboard for example). Instead
of directly using the structure, most of the code is working with
a const PhysRegId* (typedef to PhysRegIdPtr). The actual PhysRegId
objects are stored in the regFile.

Change-Id: Ic879a3cc608aa2f34e2168280faac1846de77667
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/2701
Reviewed-by: Anthony Gutierrez 
Maintainer: Andreas Sandberg 
---
M src/cpu/base_dyn_inst.hh
M src/cpu/o3/comm.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/cpu.hh
M src/cpu/o3/dyn_inst.hh
M src/cpu/o3/dyn_inst_impl.hh
M src/cpu/o3/free_list.hh
M src/cpu/o3/iew_impl.hh
M src/cpu/o3/inst_queue_impl.hh
M src/cpu/o3/probe/elastic_trace.cc
M src/cpu/o3/regfile.cc
M src/cpu/o3/regfile.hh
M src/cpu/o3/rename.hh
M src/cpu/o3/rename_impl.hh
M src/cpu/o3/rename_map.cc
M src/cpu/o3/rename_map.hh
M src/cpu/o3/scoreboard.cc
M src/cpu/o3/scoreboard.hh
18 files changed, 384 insertions(+), 377 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  Anthony Gutierrez: Looks good to me, approved



diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index 84a6540..369d7a0 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -267,17 +267,17 @@
 /** Physical register index of the destination registers of this
  *  instruction.
  */
-std::array _destRegIdx;
+std::array _destRegIdx;

 /** Physical register index of the source registers of this
  *  instruction.
  */
-std::array _srcRegIdx;
+std::array _srcRegIdx;

 /** Physical register index of the previous producers of the
  *  architected destinations.
  */
-std::array _prevDestRegIdx;
+std::array _prevDestRegIdx;


   public:
@@ -368,13 +368,13 @@
 /** Returns the physical register index of the i'th destination
  *  register.
  */
-PhysRegIndex renamedDestRegIdx(int idx) const
+PhysRegIdPtr renamedDestRegIdx(int idx) const
 {
 return _destRegIdx[idx];
 }

 /** Returns the physical register index of the i'th source register. */
-PhysRegIndex renamedSrcRegIdx(int idx) const
+PhysRegIdPtr renamedSrcRegIdx(int idx) const
 {
 assert(TheISA::MaxInstSrcRegs > idx);
 return _srcRegIdx[idx];
@@ -391,7 +391,7 @@
 /** Returns the physical register index of the previous physical  
register

  *  that remapped to the same logical register index.
  */
-PhysRegIndex prevDestRegIdx(int idx) const
+PhysRegIdPtr prevDestRegIdx(int idx) const
 {
 return _prevDestRegIdx[idx];
 }
@@ -400,8 +400,8 @@
  *  the previous physical register that the logical register mapped to.
  */
 void renameDestReg(int idx,
-   PhysRegIndex renamed_dest,
-   PhysRegIndex previous_rename)
+   PhysRegIdPtr renamed_dest,
+   PhysRegIdPtr previous_rename)
 {
 _destRegIdx[idx] = renamed_dest;
 _prevDestRegIdx[idx] = previous_rename;
@@ -411,7 +411,7 @@
  *  has/will produce that logical register's result.
  *  @todo: add in whether or not the source register is ready.
  */
-void renameSrcReg(int idx, PhysRegIndex renamed_src)
+void renameSrcReg(int idx, PhysRegIdPtr renamed_src)
 {
 _srcRegIdx[idx] = renamed_src;
 }
diff --git a/src/cpu/o3/comm.hh b/src/cpu/o3/comm.hh
index 4da2511..c5f1c01 100644
--- a/src/cpu/o3/comm.hh
+++ b/src/cpu/o3/comm.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011 ARM Limited
+ * Copyright (c) 2011, 2016 ARM Limited
  * Copyright (c) 2013 Advanced Micro Devices, Inc.
  * All rights reserved
  *
@@ -39,6 +39,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  * Authors: Kevin Lim
+ *  Nathanael Premillieu
  */

 #ifndef __CPU_O3_COMM_HH__
@@ -55,6 +56,57 @@
 // most likely location for this, there are a few classes that need this
 // typedef yet are not templated on the Impl. For now it 

[gem5-dev] Change in public/gem5[master]: arch: ISA parser additions of vector registers

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/2706 )


Change subject: arch: ISA parser additions of vector registers
..

arch: ISA parser additions of vector registers

Reiley's update :) of the isa parser definitions. My addition of the
vector element operand concept for the ISA parser. Nathanael's modification
creating a hierarchy between vector registers and its constituencies to the
isa parser.

Some fixes/updates on top to consider instructions as vectors instead of
floating when they use the VectorRF. Some counters added to all the
models to keep faithful counts.

Change-Id: Id8f162a525240dfd7ba884c5a4d9fa69f4050101
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/2706
Reviewed-by: Anthony Gutierrez 
Maintainer: Andreas Sandberg 
---
M src/arch/alpha/faults.cc
M src/arch/alpha/faults.hh
M src/arch/alpha/isa/fp.isa
M src/arch/arm/isa/insts/fp64.isa
M src/arch/arm/isa/insts/neon64.isa
M src/arch/arm/isa/operands.isa
M src/arch/arm/isa/templates/mem.isa
M src/arch/arm/isa/templates/pred.isa
M src/arch/isa_parser.py
M src/arch/sparc/faults.cc
M src/arch/sparc/faults.hh
M src/arch/sparc/isa/base.isa
M src/cpu/StaticInstFlags.py
M src/cpu/base_dyn_inst.hh
M src/cpu/o3/commit.hh
M src/cpu/o3/commit_impl.hh
M src/cpu/o3/inst_queue.hh
M src/cpu/o3/inst_queue_impl.hh
M src/cpu/simple/base.cc
M src/cpu/simple/exec_context.hh
M src/cpu/static_inst.hh
21 files changed, 614 insertions(+), 100 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  Anthony Gutierrez: Looks good to me, approved



diff --git a/src/arch/alpha/faults.cc b/src/arch/alpha/faults.cc
index 8a6e469..59d9500 100644
--- a/src/arch/alpha/faults.cc
+++ b/src/arch/alpha/faults.cc
@@ -98,6 +98,13 @@
 FaultVect FloatEnableFault::_vect = 0x0581;
 FaultStat FloatEnableFault::_count;

+/* We use the same fault vector, as for the guest system these should be  
the

+ * same, but for host purposes, having differentiation is helpful for
+ * debug/monitorization purposes. */
+FaultName VectorEnableFault::_name = "ven";
+FaultVect VectorEnableFault::_vect = 0x0581;
+FaultStat VectorEnableFault::_count;
+
 FaultName PalFault::_name = "pal";
 FaultVect PalFault::_vect = 0x2001;
 FaultStat PalFault::_count;
diff --git a/src/arch/alpha/faults.hh b/src/arch/alpha/faults.hh
index 80e3ae5..07789a2 100644
--- a/src/arch/alpha/faults.hh
+++ b/src/arch/alpha/faults.hh
@@ -299,6 +299,19 @@
 FaultStat & countStat() {return _count;}
 };

+class VectorEnableFault : public AlphaFault
+{
+  private:
+static FaultName _name;
+static FaultVect _vect;
+static FaultStat _count;
+
+  public:
+FaultName name() const {return _name;}
+FaultVect vect() {return _vect;}
+FaultStat & countStat() {return _count;}
+};
+
 class PalFault : public AlphaFault
 {
   private:
diff --git a/src/arch/alpha/isa/fp.isa b/src/arch/alpha/isa/fp.isa
index 6213c8e..ea692ae 100644
--- a/src/arch/alpha/isa/fp.isa
+++ b/src/arch/alpha/isa/fp.isa
@@ -50,6 +50,9 @@
 }
 return fault;
 }
+inline Fault checkVectorEnableFault(CPU_EXEC_CONTEXT *xc) {
+return std::make_shared();
+}
 }};

 output header {{
diff --git a/src/arch/arm/isa/insts/fp64.isa  
b/src/arch/arm/isa/insts/fp64.isa

index 706f77f..a5e1085 100644
--- a/src/arch/arm/isa/insts/fp64.isa
+++ b/src/arch/arm/isa/insts/fp64.isa
@@ -1,6 +1,6 @@
 // -*- mode:c++ -*-

-// Copyright (c) 2012-2013 ARM Limited
+// Copyright (c) 2012-2013, 2016 ARM Limited
 // All rights reserved
 //
 // The license below extends only to copyright in the software and shall
@@ -123,9 +123,11 @@
 exec_output+= BasicExecute.subst(fmovCoreRegXIop);

 fmovUCoreRegXCode = vfp64EnabledCheckCode + '''
+/* Explicitly merge with previous value */
+AA64FpDestP0_uw = AA64FpDestP0_uw;
+AA64FpDestP1_uw = AA64FpDestP1_uw;
 AA64FpDestP2_uw = XOp1_ud;
-AA64FpDestP3_uw = XOp1_ud >> 32;
-'''
+AA64FpDestP3_uw = XOp1_ud >> 32;'''
 fmovUCoreRegXIop = InstObjParams("fmov", "FmovUCoreRegX", "FpRegRegOp",
 { "code": fmovUCoreRegXCode,
   "op_class": "FloatMiscOp" }, [])
diff --git a/src/arch/arm/isa/insts/neon64.isa  
b/src/arch/arm/isa/insts/neon64.isa

index 7c9040b..4897e7c 100644
--- a/src/arch/arm/isa/insts/neon64.isa
+++ b/src/arch/arm/isa/insts/neon64.isa
@@ -1,6 +1,6 @@
 // -*- mode: c++ -*-

-// Copyright (c) 2012-2013, 2015 ARM Limited
+// Copyright (c) 2012-2013, 2015-2016 ARM Limited
 // All rights reserved
 //
 // The license below extends only to copyright in the software and shall
@@ -225,11 +225,16 @@
 AA64FpDestP%(destReg)d_uw = gtoh(destReg.regs[%(reg)d]);
 ''' % { "reg" : reg, 

[gem5-dev] Change in public/gem5[master]: cpu: Result refactoring

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/2703 )


Change subject: cpu: Result refactoring
..

cpu: Result refactoring

The Result union used to collect the result of an instruction is now a
class of its own, with its constructor, and explicit casting methods for
cleanliness.

This is also a stepping stone to have vector registers, and instructions
that produce a vector register as output.

Change-Id: I6f40c11cb5e835d8b11f7804a4e967aff18025b9
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/2703
Reviewed-by: Anthony Gutierrez 
Reviewed-by: Jason Lowe-Power 
Maintainer: Andreas Sandberg 
---
M src/cpu/base_dyn_inst.hh
M src/cpu/checker/cpu.hh
M src/cpu/checker/cpu_impl.hh
A src/cpu/inst_res.hh
4 files changed, 205 insertions(+), 78 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  Anthony Gutierrez: Looks good to me, approved



diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index 9c69523..a8e619c 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011,2013 ARM Limited
+ * Copyright (c) 2011,2013,2016 ARM Limited
  * Copyright (c) 2013 Advanced Micro Devices, Inc.
  * All rights reserved.
  *
@@ -49,18 +49,19 @@
 #include 
 #include 
 #include 
-#include 
 #include 
+#include 

 #include "arch/generic/tlb.hh"
 #include "arch/utility.hh"
 #include "base/trace.hh"
 #include "config/the_isa.hh"
 #include "cpu/checker/cpu.hh"
-#include "cpu/o3/comm.hh"
 #include "cpu/exec_context.hh"
 #include "cpu/exetrace.hh"
+#include "cpu/inst_res.hh"
 #include "cpu/inst_seq.hh"
+#include "cpu/o3/comm.hh"
 #include "cpu/op_class.hh"
 #include "cpu/static_inst.hh"
 #include "cpu/translation.hh"
@@ -94,15 +95,6 @@
 MaxInstDestRegs = TheISA::MaxInstDestRegs   /// Max dest regs
 };

-union Result {
-uint64_t integer;
-double dbl;
-void set(uint64_t i) { integer = i; }
-void set(double d) { dbl = d; }
-void get(uint64_t& i) { i = integer; }
-void get(double& d) { d = dbl; }
-};
-
   protected:
 enum Status {
 IqEntry, /// Instruction is in the IQ
@@ -174,7 +166,7 @@
 /** The result of the instruction; assumes an instruction can have many
  *  destination registers.
  */
-std::queue instResult;
+std::queue instResult;

 /** PC state for this instruction. */
 TheISA::PCState pc;
@@ -606,56 +598,55 @@
 /** Returns the logical register index of the i'th source register. */
 const RegId& srcRegIdx(int i) const { return staticInst->srcRegIdx(i);  
}


-/** Pops a result off the instResult queue */
-template 
-void popResult(T& t)
+/** Return the size of the instResult queue. */
+uint8_t resultSize() { return instResult.size(); }
+
+/** Pops a result off the instResult queue.
+ * If the result stack is empty, return the default value.
+ * */
+InstResult popResult(InstResult dflt = InstResult())
 {
 if (!instResult.empty()) {
-instResult.front().get(t);
+InstResult t = instResult.front();
 instResult.pop();
+return t;
 }
+return dflt;
 }

-/** Read the most recent result stored by this instruction */
-template 
-void readResult(T& t)
-{
-instResult.back().get(t);
-}
-
-/** Pushes a result onto the instResult queue */
-template 
-void setResult(T t)
+/** Pushes a result onto the instResult queue. */
+template
+void setScalarResult(T&& t)
 {
 if (instFlags[RecordResult]) {
-Result instRes;
-instRes.set(t);
-instResult.push(instRes);
+instResult.push(InstResult(std::forward(t),
+InstResult::ResultType::Scalar));
 }
 }

 /** Records an integer register being set to a value. */
 void setIntRegOperand(const StaticInst *si, int idx, IntReg val)
 {
-setResult(val);
+setScalarResult(val);
 }

 /** Records a CC register being set to a value. */
 void setCCRegOperand(const StaticInst *si, int idx, CCReg val)
 {
-setResult(val);
+setScalarResult(val);
 }

 /** Records an fp register being set to a value. */
 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
 {
-setResult(val);
+setScalarResult(val);
 }

 /** Records an fp register being set to an integer value. */
-void setFloatRegOperandBits(const StaticInst *si, int idx,  
FloatRegBits val)

+void
+setFloatRegOperandBits(const StaticInst *si, int 

[gem5-dev] Change in public/gem5[master]: cpu: Added interface for vector reg file

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has uploaded a new patch set (#4) to the change originally  
created by Curtis Dunham. ( https://gem5-review.googlesource.com/2705 )


Change subject: cpu: Added interface for vector reg file
..

cpu: Added interface for vector reg file

This patch adds some more functionality to the cpu model and the arch to
interface with the vector register file.

This change consists mainly of augmenting ThreadContexts and ExecContexts
with calls to get/set full vectors, underlying microarchitectural elements
or lanes. Those are meant to interface with the vector register file. All
classes that implement this interface also get an appropriate  
implementation.


This requires implementing the vector register file for the different
models using the VecRegContainer class.

This change set also updates the Result abstraction to contemplate the
possibility of having a vector as result.

The changes also affect how the remote_gdb connection works.

There are some (nasty) side effects, such as the need to define dummy
numPhysVecRegs parameter values for architectures that do not implement
vector extensions.

Nathanael Premillieu's work with an increasing number of fixes and
improvements of mine.

Change-Id: Iee65f4e8b03abfe1e94e6940a51b68d0977fd5bb
Reviewed-by: Andreas Sandberg 
[ Fix RISCV build issues and CC reg free list initialisation ]
Signed-off-by: Andreas Sandberg 
---
M configs/common/cores/arm/O3_ARM_v7a.py
M src/arch/SConscript
M src/arch/alpha/isa.hh
M src/arch/alpha/registers.hh
M src/arch/arm/ArmISA.py
M src/arch/arm/insts/static_inst.cc
M src/arch/arm/insts/static_inst.hh
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
M src/arch/arm/nativetrace.cc
M src/arch/arm/registers.hh
M src/arch/arm/remote_gdb.cc
M src/arch/arm/remote_gdb.hh
M src/arch/arm/utility.cc
A src/arch/generic/ISACommon.py
M src/arch/generic/SConscript
A src/arch/generic/traits.hh
M src/arch/generic/types.hh
M src/arch/isa_parser.py
M src/arch/mips/isa.hh
M src/arch/mips/registers.hh
M src/arch/null/registers.hh
M src/arch/power/isa.hh
M src/arch/power/registers.hh
M src/arch/riscv/isa.hh
M src/arch/riscv/registers.hh
M src/arch/sparc/isa.hh
M src/arch/sparc/registers.hh
M src/arch/x86/isa.hh
M src/arch/x86/registers.hh
M src/cpu/base_dyn_inst.hh
M src/cpu/checker/cpu.hh
M src/cpu/checker/cpu_impl.hh
M src/cpu/checker/thread_context.hh
M src/cpu/exec_context.hh
M src/cpu/inst_res.hh
M src/cpu/minor/dyn_inst.cc
M src/cpu/minor/exec_context.hh
M src/cpu/minor/scoreboard.cc
M src/cpu/minor/scoreboard.hh
M src/cpu/o3/O3CPU.py
M src/cpu/o3/comm.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/cpu.hh
M src/cpu/o3/dyn_inst.hh
M src/cpu/o3/free_list.hh
M src/cpu/o3/inst_queue_impl.hh
M src/cpu/o3/regfile.cc
M src/cpu/o3/regfile.hh
M src/cpu/o3/rename.hh
M src/cpu/o3/rename_impl.hh
M src/cpu/o3/rename_map.cc
M src/cpu/o3/rename_map.hh
M src/cpu/o3/thread_context.hh
M src/cpu/o3/thread_context_impl.hh
M src/cpu/reg_class.cc
M src/cpu/reg_class.hh
M src/cpu/reg_class_impl.hh
M src/cpu/simple/base.cc
M src/cpu/simple/exec_context.hh
M src/cpu/simple_thread.hh
M src/cpu/static_inst.hh
M src/cpu/thread_context.cc
M src/cpu/thread_context.hh
M src/sim/serialize.cc
65 files changed, 2,525 insertions(+), 75 deletions(-)


--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: Iee65f4e8b03abfe1e94e6940a51b68d0977fd5bb
Gerrit-Change-Number: 2705
Gerrit-PatchSet: 4
Gerrit-Owner: Curtis Dunham 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Anthony Gutierrez 
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[gem5-dev] Change in public/gem5[master]: arm, kvm: update CP15 timer model when exiting Kvm

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/3543 )


Change subject: arm,kvm: update CP15 timer model when exiting Kvm
..

arm,kvm: update CP15 timer model when exiting Kvm

The ARM MiscRegs implementation has two interfaces: 'normal'
and 'no effect'.  The latter acts as a way to access the
backing store without architectural 'effects'.  For instance,
a normal write to a timer compare value would call into the
timer model to emulate the device.  The 'no effect' interface,
however, would just write the value into the register backing
store and do nothing else.

For Kvm execution, a delicate balance must be struck for the
timer device specifically.  We need the code in the model
to be run, because it contains state other than the register
backing store that must stay in sync.  On the other hand, we
don't necessarily want the timer model to schedule gem5
events when this happens.

In this commit, we ensure that we use the 'effectful'
MiscReg interface when copying the CP15 timer registers
from Kvm back into gem5.  The prior commit makes sure
that this doesn't generate unnecessary timer events
or interrupts.

Change-Id: Id414c2965bd07fc21ac95e3d581ccc9f55cef9f9
Reviewed-on: https://gem5-review.googlesource.com/3543
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
---
M src/arch/arm/kvm/armv8_cpu.cc
M src/arch/arm/kvm/armv8_cpu.hh
2 files changed, 22 insertions(+), 6 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/arm/kvm/armv8_cpu.cc b/src/arch/arm/kvm/armv8_cpu.cc
index 352fb2c..db2b9c0 100644
--- a/src/arch/arm/kvm/armv8_cpu.cc
+++ b/src/arch/arm/kvm/armv8_cpu.cc
@@ -114,6 +114,12 @@
 MiscRegInfo(INT_REG(fp_regs.fpcr), MISCREG_FPCR, "FPCR"),
 };

+const std::set ArmV8KvmCPU::deviceRegSet = {
+MISCREG_CNTV_CTL_EL0,
+MISCREG_CNTV_CVAL_EL0,
+MISCREG_CNTKCTL_EL1,
+};
+
 const std::vector ArmV8KvmCPU::miscRegIdMap = {
 MiscRegInfo(SYS_MPIDR_EL1, MISCREG_MPIDR_EL1, "MPIDR(EL1)"),
 };
@@ -317,7 +323,10 @@
 for (const auto  : getSysRegMap()) {
 const auto value(getOneRegU64(ri.kvm));
 DPRINTF(KvmContext, "  %s := 0x%x\n", ri.name, value);
-tc->setMiscRegNoEffect(ri.idx, value);
+if (ri.is_device)
+tc->setMiscReg(ri.idx, value);
+else
+tc->setMiscRegNoEffect(ri.idx, value);
 }

 PCState pc(getOneRegU64(INT_REG(regs.pc)));
@@ -366,7 +375,8 @@
 // Only add implemented registers that we are going to be able
 // to write.
 if (implemented && writeable)
-sysRegMap.emplace_back(reg, idx, miscRegName[idx]);
+sysRegMap.emplace_back(reg, idx, miscRegName[idx],
+deviceRegSet.find(idx) != deviceRegSet.end());
 }

 return sysRegMap;
diff --git a/src/arch/arm/kvm/armv8_cpu.hh b/src/arch/arm/kvm/armv8_cpu.hh
index 63e0390..101ccc2 100644
--- a/src/arch/arm/kvm/armv8_cpu.hh
+++ b/src/arch/arm/kvm/armv8_cpu.hh
@@ -40,6 +40,7 @@
 #ifndef __ARCH_ARM_KVM_ARMV8_CPU_HH__
 #define __ARCH_ARM_KVM_ARMV8_CPU_HH__

+#include 
 #include 

 #include "arch/arm/intregs.hh"
@@ -107,8 +108,9 @@

 /** Mapping between misc registers in gem5 and registers in KVM */
 struct MiscRegInfo {
-MiscRegInfo(uint64_t _kvm, MiscRegIndex _idx, const char *_name)
-: kvm(_kvm), idx(_idx), name(_name) {}
+MiscRegInfo(uint64_t _kvm, MiscRegIndex _idx, const char *_name,
+bool _is_device = false)
+: kvm(_kvm), idx(_idx), name(_name), is_device(_is_device) {}

 /** Register index in KVM */
 uint64_t kvm;
@@ -116,6 +118,8 @@
 MiscRegIndex idx;
 /** Name to use in debug dumps */
 const char *name;
+/** is device register? (needs 'effectful' state update) */
+bool is_device;
 };

 /**
@@ -132,9 +136,11 @@

 /** Mapping between gem5 integer registers and integer registers in  
kvm */

 static const std::vector intRegMap;
-/** Mapping between gem5 misc registers registers and registers in kvm  
*/

+/** Mapping between gem5 misc registers and registers in kvm */
 static const std::vector miscRegMap;
-/** Mapping between gem5 ID misc registers registers and registers in  
kvm */

+/** Device registers (needing "effectful" MiscReg writes) */
+static const std::set deviceRegSet;
+/** Mapping between gem5 ID misc registers and registers in kvm */
 static const std::vector miscRegIdMap;

 /** Cached mapping between system registers in kvm and misc regs in  
gem5 */


--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged

[gem5-dev] Change in public/gem5[master]: dev, arm: add Kvm mode of operation for CP15 timer

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/3542 )


Change subject: dev,arm: add Kvm mode of operation for CP15 timer
..

dev,arm: add Kvm mode of operation for CP15 timer

The timer device exposed via the ARM ISA, also known as the
"CP15 timer" due to its legacy coprocessor encodings, is
implemented by the GenericTimerISA class.  During Kvm
execution, however, this functionality is directly emulated
by the hardware.

This commit subclasses the GenericTimer, which is (solely)
used by GenericTimerISA, to facilitate Kvm in much the same
way as the prior GIC changes: the gem5 model is used as the
backing store for state, so checkpointing and CPU switching
work correctly, but isn't used during Kvm execution.

The added indirection prevents the timer device from creating
events when we're just updating its state, but not actually
using it for simulation.

Change-Id: I427540d11ccf049c334afe318f575146aa888672
Reviewed-on: https://gem5-review.googlesource.com/3542
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
---
M src/dev/arm/generic_timer.cc
M src/dev/arm/generic_timer.hh
2 files changed, 47 insertions(+), 12 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/dev/arm/generic_timer.cc b/src/dev/arm/generic_timer.cc
index 48f70e1..6332b8f 100644
--- a/src/dev/arm/generic_timer.cc
+++ b/src/dev/arm/generic_timer.cc
@@ -109,8 +109,12 @@

 DPRINTF(Timer, "Counter limit reached\n");
 if (!_control.imask) {
-DPRINTF(Timer, "Causing interrupt\n");
-_interrupt.send();
+if (scheduleEvents()) {
+DPRINTF(Timer, "Causing interrupt\n");
+_interrupt.send();
+} else {
+DPRINTF(Timer, "Kvm mode; skipping simulated interrupt\n");
+}
 }
 }

@@ -122,10 +126,12 @@
 if (value() >= _counterLimit) {
 counterLimitReached();
 } else {
-const auto period(_systemCounter.period());
 _control.istatus = 0;
-_parent.schedule(_counterLimitReachedEvent,
- curTick() + (_counterLimit - value()) * period);
+if (scheduleEvents()) {
+const auto period(_systemCounter.period());
+_parent.schedule(_counterLimitReachedEvent,
+ curTick() + (_counterLimit - value()) * period);
+}
 }
 }

@@ -234,12 +240,13 @@

 GenericTimer::GenericTimer(GenericTimerParams *p)
 : SimObject(p),
+  system(*p->system),
   gic(p->gic),
   irqPhys(p->int_phys),
   irqVirt(p->int_virt)
 {
 fatal_if(!p->system, "No system specified, can't instantiate  
timer.\n");

-p->system->setGenericTimer(this);
+system.setGenericTimer(this);
 }

 void
@@ -303,7 +310,7 @@
 timers.resize(cpus);
 for (unsigned i = old_cpu_count; i < cpus; ++i) {
 timers[i].reset(
-new CoreTimers(*this, i, irqPhys, irqVirt));
+new CoreTimers(*this, system, i, irqPhys, irqVirt));
 }
 }

diff --git a/src/dev/arm/generic_timer.hh b/src/dev/arm/generic_timer.hh
index 3eec1d4..ccfb127 100644
--- a/src/dev/arm/generic_timer.hh
+++ b/src/dev/arm/generic_timer.hh
@@ -42,6 +42,7 @@
 #define __DEV_ARM_GENERIC_TIMER_HH__

 #include "arch/arm/isa_device.hh"
+#include "arch/arm/system.hh"
 #include "base/bitunion.hh"
 #include "dev/arm/base_gic.hh"
 #include "sim/core.hh"
@@ -159,6 +160,8 @@
 void counterLimitReached();
 EventFunctionWrapper _counterLimitReachedEvent;

+virtual bool scheduleEvents() { return true; }
+
   public:
 ArchTimer(const std::string ,
   SimObject ,
@@ -201,6 +204,28 @@
 ArchTimer(const ArchTimer );
 };

+class ArchTimerKvm : public ArchTimer
+{
+  private:
+ArmSystem 
+
+  public:
+ArchTimerKvm(const std::string ,
+ ArmSystem ,
+ SimObject ,
+ SystemCounter ,
+ const Interrupt )
+  : ArchTimer(name, parent, sysctr, interrupt), system(system) {}
+
+  protected:
+// For ArchTimer's in a GenericTimerISA with Kvm execution about
+// to begin, skip rescheduling the event.
+// Otherwise, we should reschedule the event (if necessary).
+bool scheduleEvents() override {
+return !system.validKvmEnvironment();
+}
+};
+
 class GenericTimer : public SimObject
 {
   public:
@@ -215,25 +240,25 @@

   protected:
 struct CoreTimers {
-CoreTimers(GenericTimer , unsigned cpu,
+CoreTimers(GenericTimer , ArmSystem , unsigned cpu,
unsigned _irqPhys, unsigned _irqVirt)
 : irqPhys(*parent.gic, _irqPhys, cpu),
   irqVirt(*parent.gic, _irqVirt, cpu),
   // This should really be phys_timerN, but we are stuck with
   // arch_timer for backwards compatibility.
   

[gem5-dev] Change in public/gem5[master]: kvm: move Kvm check from ARM Kvm GIC to System

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/3540 )


Change subject: kvm: move Kvm check from ARM Kvm GIC to System
..

kvm: move Kvm check from ARM Kvm GIC to System

The check was nearly completely generic anyway,
with the exception of the Kvm CPU type.

This will make it easier for other parts of the
codebase to do similar checks.

Change-Id: Ibfdd3d65e9e6cc3041b53b73adfabee1999283da
Reviewed-on: https://gem5-review.googlesource.com/3540
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
---
M src/arch/arm/kvm/gic.cc
M src/arch/arm/kvm/gic.hh
M src/sim/system.cc
M src/sim/system.hh
4 files changed, 24 insertions(+), 19 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/arm/kvm/gic.cc b/src/arch/arm/kvm/gic.cc
index 7cf4d07..498b79f 100644
--- a/src/arch/arm/kvm/gic.cc
+++ b/src/arch/arm/kvm/gic.cc
@@ -189,7 +189,7 @@
 MuxingKvmGic::startup()
 {
 Pl390::startup();
-usingKvm = (kernelGic != nullptr) && validKvmEnvironment();
+usingKvm = (kernelGic != nullptr) && system.validKvmEnvironment();
 if (usingKvm)
 fromPl390ToKvm();
 }
@@ -206,7 +206,7 @@
 MuxingKvmGic::drainResume()
 {
 Pl390::drainResume();
-bool use_kvm = (kernelGic != nullptr) && validKvmEnvironment();
+bool use_kvm = (kernelGic != nullptr) && system.validKvmEnvironment();
 if (use_kvm != usingKvm) {
 // Should only occur due to CPU switches
 if (use_kvm) // from simulation to KVM emulation
@@ -287,20 +287,6 @@
 kernelGic->clearPPI(cpu, num);
 }

-bool
-MuxingKvmGic::validKvmEnvironment() const
-{
-if (system.threadContexts.empty())
-return false;
-
-for (auto tc : system.threadContexts) {
-if (dynamic_cast(tc->getCpuPtr()) == nullptr) {
-return false;
-}
-}
-return true;
-}
-
 void
 MuxingKvmGic::copyDistRegister(BaseGicRegisters* from, BaseGicRegisters*  
to,

ContextID ctx, Addr daddr)
diff --git a/src/arch/arm/kvm/gic.hh b/src/arch/arm/kvm/gic.hh
index b554448..ee04088 100644
--- a/src/arch/arm/kvm/gic.hh
+++ b/src/arch/arm/kvm/gic.hh
@@ -195,9 +195,6 @@
 void clearPPInt(uint32_t num, uint32_t cpu) override;

   protected:
-/** Verify gem5 configuration will support KVM emulation */
-bool validKvmEnvironment() const;
-
 /** System this interrupt controller belongs to */
 System 

diff --git a/src/sim/system.cc b/src/sim/system.cc
index 9315882..e46c356 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -55,6 +55,7 @@
 #include "base/trace.hh"
 #include "config/use_kvm.hh"
 #if USE_KVM
+#include "cpu/kvm/base.hh"
 #include "cpu/kvm/vm.hh"
 #endif
 #include "cpu/thread_context.hh"
@@ -335,6 +336,24 @@
 remoteGDB[context_id]->replaceThreadContext(tc);
 }

+bool
+System::validKvmEnvironment() const
+{
+#if USE_KVM
+if (threadContexts.empty())
+return false;
+
+for (auto tc : threadContexts) {
+if (dynamic_cast(tc->getCpuPtr()) == nullptr) {
+return false;
+}
+}
+return true;
+#else
+return false;
+#endif
+}
+
 Addr
 System::allocPhysPages(int npages)
 {
diff --git a/src/sim/system.hh b/src/sim/system.hh
index c3c178d..a656ab3 100644
--- a/src/sim/system.hh
+++ b/src/sim/system.hh
@@ -262,6 +262,9 @@
 return kvmVM;
 }

+/** Verify gem5 configuration will support KVM emulation */
+bool validKvmEnvironment() const;
+
 /** Get a pointer to access the physical memory of the system */
 PhysicalMemory& getPhysMem() { return physmem; }


--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: Ibfdd3d65e9e6cc3041b53b73adfabee1999283da
Gerrit-Change-Number: 3540
Gerrit-PatchSet: 3
Gerrit-Owner: Curtis Dunham 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Curtis Dunham 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Weiping Liao 
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[gem5-dev] Change in public/gem5[master]: dev, arm: remove and recreate timer events around drains

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/3541 )


Change subject: dev,arm: remove and recreate timer events around drains
..

dev,arm: remove and recreate timer events around drains

Having timer events stored in checkpoints complicates Kvm
execution.  We change the timer behavior so that it always
deschedules any pending events on a drain() and recreates
them on a drainResume(), thus they will never appear in
checkpoints henceforth.  This pattern of behavior makes
it simpler to handle Kvm execution, where the hardware
performs the timer function directly.

Change-Id: Ia218868c69350d96e923c640634d492b5c19cd3f
Reviewed-on: https://gem5-review.googlesource.com/3541
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
---
M src/dev/arm/generic_timer.cc
M src/dev/arm/generic_timer.hh
2 files changed, 25 insertions(+), 16 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/dev/arm/generic_timer.cc b/src/dev/arm/generic_timer.cc
index efaebb1..48f70e1 100644
--- a/src/dev/arm/generic_timer.cc
+++ b/src/dev/arm/generic_timer.cc
@@ -179,13 +179,6 @@
 paramOut(cp, "control_serial", _control);
 SERIALIZE_SCALAR(_counterLimit);
 SERIALIZE_SCALAR(_offset);
-
-const bool event_scheduled(_counterLimitReachedEvent.scheduled());
-SERIALIZE_SCALAR(event_scheduled);
-if (event_scheduled) {
-const Tick event_time(_counterLimitReachedEvent.when());
-SERIALIZE_SCALAR(event_time);
-}
 }

 void
@@ -197,13 +190,24 @@
 // compatibility.
 if (!UNSERIALIZE_OPT_SCALAR(_offset))
 _offset = 0;
-bool event_scheduled;
-UNSERIALIZE_SCALAR(event_scheduled);
-if (event_scheduled) {
-Tick event_time;
-UNSERIALIZE_SCALAR(event_time);
-_parent.schedule(_counterLimitReachedEvent, event_time);
-}
+
+// We no longer schedule an event here because we may enter KVM
+// emulation.  The event creation is delayed until drainResume().
+}
+
+DrainState
+ArchTimer::drain()
+{
+if (_counterLimitReachedEvent.scheduled())
+_parent.deschedule(_counterLimitReachedEvent);
+
+return DrainState::Drained;
+}
+
+void
+ArchTimer::drainResume()
+{
+updateCounter();
 }

 void
diff --git a/src/dev/arm/generic_timer.hh b/src/dev/arm/generic_timer.hh
index 3a38954..3eec1d4 100644
--- a/src/dev/arm/generic_timer.hh
+++ b/src/dev/arm/generic_timer.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013, 2015 ARM Limited
+ * Copyright (c) 2013, 2015, 2017 ARM Limited
  * All rights reserved.
  *
  * The license below extends only to copyright in the software and shall
@@ -102,7 +102,7 @@
 };

 /// Per-CPU architected timer.
-class ArchTimer : public Serializable
+class ArchTimer : public Serializable, public Drainable
 {
   public:
 class Interrupt
@@ -188,9 +188,14 @@
 /// Returns the value of the counter which this timer relies on.
 uint64_t value() const;

+// Serializable
 void serialize(CheckpointOut ) const override;
 void unserialize(CheckpointIn ) override;

+// Drainable
+DrainState drain() override;
+void drainResume() override;
+
   private:
 // Disable copying
 ArchTimer(const ArchTimer );

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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: Ia218868c69350d96e923c640634d492b5c19cd3f
Gerrit-Change-Number: 3541
Gerrit-PatchSet: 3
Gerrit-Owner: Curtis Dunham 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Curtis Dunham 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Weiping Liao 
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