from:"Mahyar Samani \(Gerrit\) via gem5\-dev"

[gem5-dev] [XS] Change in gem5/gem5[develop]: tests: Reducing json stat dump size.

2023-06-15 Thread Mahyar Samani (Gerrit) via gem5-dev

Mahyar Samani has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/71438?usp=email )


Change subject: tests: Reducing json stat dump size.
..

tests: Reducing json stat dump size.

This change reduces the number of stats dumped as json in
traffic_gen tests.

Change-Id: I94becb2e6d5da6096271cf7893ff2b380314da06
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71402
Maintainer: Bobby Bruce 
Reviewed-by: Bobby Bruce 
Tested-by: kokoro 
(cherry picked from commit f78471fb81db40c836b89a015a61b8311b4b98fd)
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71438
---
M tests/gem5/traffic_gen/simple_traffic_run.py
1 file changed, 3 insertions(+), 1 deletion(-)

Approvals:
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/tests/gem5/traffic_gen/simple_traffic_run.py  
b/tests/gem5/traffic_gen/simple_traffic_run.py

index 7c0f188..3766d73 100644
--- a/tests/gem5/traffic_gen/simple_traffic_run.py
+++ b/tests/gem5/traffic_gen/simple_traffic_run.py
@@ -209,7 +209,9 @@
 exit_event = m5.simulate()
 print(f"Exiting @ tick {m5.curTick()} because {exit_event.getCause()}.")

-simstats = get_simstat(root, prepare_stats=True)
+simstats = get_simstat(
+[core.generator for core in generator.get_cores()], prepare_stats=True
+)
 json_output = Path(m5.options.outdir) / "output.json"
 with open(json_output, "w") as stats_file:
 simstats.dump(stats_file, indent=2)

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/71438?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I94becb2e6d5da6096271cf7893ff2b380314da06
Gerrit-Change-Number: 71438
Gerrit-PatchSet: 3
Gerrit-Owner: Bobby Bruce 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Mahyar Samani 
Gerrit-Reviewer: kokoro 
Gerrit-CC: kokoro 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [XS] Change in gem5/gem5[release-staging-v23-0]: tests: Reducing json stat dump size.

2023-06-08 Thread Mahyar Samani (Gerrit) via gem5-dev

Mahyar Samani has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/71402?usp=email )


Change subject: tests: Reducing json stat dump size.
..

tests: Reducing json stat dump size.

This change reduces the number of stats dumped as json in
traffic_gen tests.

Change-Id: I94becb2e6d5da6096271cf7893ff2b380314da06
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71402
Maintainer: Bobby Bruce 
Reviewed-by: Bobby Bruce 
Tested-by: kokoro 
---
M tests/gem5/traffic_gen/simple_traffic_run.py
1 file changed, 3 insertions(+), 1 deletion(-)

Approvals:
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/tests/gem5/traffic_gen/simple_traffic_run.py  
b/tests/gem5/traffic_gen/simple_traffic_run.py

index 7c0f188..3766d73 100644
--- a/tests/gem5/traffic_gen/simple_traffic_run.py
+++ b/tests/gem5/traffic_gen/simple_traffic_run.py
@@ -209,7 +209,9 @@
 exit_event = m5.simulate()
 print(f"Exiting @ tick {m5.curTick()} because {exit_event.getCause()}.")

-simstats = get_simstat(root, prepare_stats=True)
+simstats = get_simstat(
+[core.generator for core in generator.get_cores()], prepare_stats=True
+)
 json_output = Path(m5.options.outdir) / "output.json"
 with open(json_output, "w") as stats_file:
 simstats.dump(stats_file, indent=2)

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/71402?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: release-staging-v23-0
Gerrit-Change-Id: I94becb2e6d5da6096271cf7893ff2b380314da06
Gerrit-Change-Number: 71402
Gerrit-PatchSet: 3
Gerrit-Owner: Mahyar Samani 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Mahyar Samani 
Gerrit-Reviewer: kokoro 
Gerrit-CC: kokoro 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [XS] Change in gem5/gem5[release-staging-v23-0]: tests: Reducing json stat dump size.

2023-06-08 Thread Mahyar Samani (Gerrit) via gem5-dev

Mahyar Samani has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/71402?usp=email )



Change subject: tests: Reducing json stat dump size.
..

tests: Reducing json stat dump size.

This change reduces the number of stats dumped as json in
traffic_gen tests.

Change-Id: I94becb2e6d5da6096271cf7893ff2b380314da06
---
M tests/gem5/traffic_gen/simple_traffic_run.py
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/tests/gem5/traffic_gen/simple_traffic_run.py  
b/tests/gem5/traffic_gen/simple_traffic_run.py

index 7c0f188..bbb517e 100644
--- a/tests/gem5/traffic_gen/simple_traffic_run.py
+++ b/tests/gem5/traffic_gen/simple_traffic_run.py
@@ -209,7 +209,7 @@
 exit_event = m5.simulate()
 print(f"Exiting @ tick {m5.curTick()} because {exit_event.getCause()}.")

-simstats = get_simstat(root, prepare_stats=True)
+simstats = get_simstat([core.generator for core in generator.get_cores()],  
prepare_stats=True)

 json_output = Path(m5.options.outdir) / "output.json"
 with open(json_output, "w") as stats_file:
 simstats.dump(stats_file, indent=2)

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/71402?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: release-staging-v23-0
Gerrit-Change-Id: I94becb2e6d5da6096271cf7893ff2b380314da06
Gerrit-Change-Number: 71402
Gerrit-PatchSet: 1
Gerrit-Owner: Mahyar Samani 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] Change in gem5/gem5[develop]: stats: Adding tests for gem5stats.

2022-01-21 Thread Mahyar Samani (Gerrit) via gem5-dev

Mahyar Samani has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/55743 )



Change subject: stats: Adding tests for gem5stats.
..

stats: Adding tests for gem5stats.

This change adds the first of many tests for the gem5stats.
The current test only considers a setup consisiting of
traffic generator, cache and memory.

Change-Id: I3ebe16131aed5bf6dad68de673f9491f1bea1c78
---
A  
tests/gem5/gem5stats/trusted_results/RandomGenerator-2-PrivateL1PrivateL2/config.dot
A  
tests/gem5/gem5stats/trusted_results/RandomGenerator-8-MESITwoLevel/config.system.cache_hierarchy.ruby_system.dot

A tests/gem5/gem5stats/trusted_results/LinearGenerator-4-MESITwoLevel/simerr
A  
tests/gem5/gem5stats/trusted_results/LinearGenerator-1-PrivateL1PrivateL2/simout
A  
tests/gem5/gem5stats/trusted_results/LinearGenerator-2-MESITwoLevel/config.system.cache_hierarchy.ruby_system.dot
A  
tests/gem5/gem5stats/trusted_results/LinearGenerator-2-PrivateL1PrivateL2/config.dot.svg
A  
tests/gem5/gem5stats/trusted_results/RandomGenerator-8-PrivateL1PrivateL2/config.dot.svg
A  
tests/gem5/gem5stats/trusted_results/LinearGenerator-8-PrivateL1PrivateL2/simout
A  
tests/gem5/gem5stats/trusted_results/LinearGenerator-1-MESITwoLevel/config.json
A  
tests/gem5/gem5stats/trusted_results/RandomGenerator-2-PrivateL1PrivateL2/config.json
A  
tests/gem5/gem5stats/trusted_results/RandomGenerator-4-MESITwoLevel/generator_stats.json

A tests/gem5/gem5stats/trusted_results/RandomGenerator-4-MESITwoLevel/simerr
A  
tests/gem5/gem5stats/trusted_results/LinearGenerator-1-PrivateL1PrivateL2/config.dot.svg
A  
tests/gem5/gem5stats/trusted_results/LinearGenerator-8-MESITwoLevel/generator_stats.json
A  
tests/gem5/gem5stats/trusted_results/RandomGenerator-1-MESITwoLevel/config.system.cache_hierarchy.ruby_system.dot.pdf
A  
tests/gem5/gem5stats/trusted_results/RandomGenerator-4-PrivateL1PrivateL2/config.dot.pdf
A  
tests/gem5/gem5stats/trusted_results/RandomGenerator-1-MESITwoLevel/config.json
A  
tests/gem5/gem5stats/trusted_results/LinearGenerator-8-PrivateL1PrivateL2/config.dot.pdf

A tests/gem5/gem5stats/trusted_results/RandomGenerator-2-MESITwoLevel/simout
A  
tests/gem5/gem5stats/trusted_results/RandomGenerator-2-MESITwoLevel/generator_stats.json
A  
tests/gem5/gem5stats/trusted_results/RandomGenerator-4-MESITwoLevel/config.dot

A tests/gem5/gem5stats/trusted_results/RandomGenerator-1-MESITwoLevel/simout
A  
tests/gem5/gem5stats/trusted_results/LinearGenerator-8-PrivateL1PrivateL2/simerr
A  
tests/gem5/gem5stats/trusted_results/LinearGenerator-8-PrivateL1PrivateL2/config.json
A  
tests/gem5/gem5stats/trusted_results/LinearGenerator-1-PrivateL1PrivateL2/stats.txt
A  
tests/gem5/gem5stats/trusted_results/RandomGenerator-4-MESITwoLevel/config.json
A  
tests/gem5/gem5stats/trusted_results/LinearGenerator-1-MESITwoLevel/config.ini
A  
tests/gem5/gem5stats/trusted_results/LinearGenerator-1-PrivateL1PrivateL2/config.json
A  
tests/gem5/gem5stats/trusted_results/LinearGenerator-8-PrivateL1PrivateL2/generator_stats.json
A  
tests/gem5/gem5stats/trusted_results/RandomGenerator-2-MESITwoLevel/config.system.cache_hierarchy.ruby_system.dot
A  
tests/gem5/gem5stats/trusted_results/RandomGenerator-8-MESITwoLevel/config.json
A  
tests/gem5/gem5stats/trusted_results/RandomGenerator-4-MESITwoLevel/l2_cache_stats.json
A  
tests/gem5/gem5stats/trusted_results/LinearGenerator-1-PrivateL1PrivateL2/simerr
A  
tests/gem5/gem5stats/trusted_results/LinearGenerator-4-MESITwoLevel/config.dot
A  
tests/gem5/gem5stats/trusted_results/RandomGenerator-2-PrivateL1PrivateL2/simerr
A  
tests/gem5/gem5stats/trusted_results/RandomGenerator-2-MESITwoLevel/l2_cache_stats.json
A  
tests/gem5/gem5stats/trusted_results/RandomGenerator-8-MESITwoLevel/l2_cache_stats.json
A  
tests/gem5/gem5stats/trusted_results/LinearGenerator-2-MESITwoLevel/config.dot.pdf
A  
tests/gem5/gem5stats/trusted_results/RandomGenerator-8-PrivateL1PrivateL2/config.json
A  
tests/gem5/gem5stats/trusted_results/RandomGenerator-8-PrivateL1PrivateL2/stats.txt

A tests/gem5/gem5stats/trusted_results/LinearGenerator-4-MESITwoLevel/simout
A  
tests/gem5/gem5stats/trusted_results/LinearGenerator-1-MESITwoLevel/config.system.cache_hierarchy.ruby_system.dot.svg
A  
tests/gem5/gem5stats/trusted_results/RandomGenerator-1-MESITwoLevel/config.dot.pdf
A  
tests/gem5/gem5stats/trusted_results/RandomGenerator-8-MESITwoLevel/config.ini
A  
tests/gem5/gem5stats/trusted_results/LinearGenerator-2-MESITwoLevel/config.system.cache_hierarchy.ruby_system.dot.svg
A  
tests/gem5/gem5stats/trusted_results/RandomGenerator-1-MESITwoLevel/stats.txt
A  
tests/gem5/gem5stats/trusted_results/LinearGenerator-2-MESITwoLevel/l1_cache_stats.json
A  
tests/gem5/gem5stats/trusted_results/LinearGenerator-8-MESITwoLevel/config.system.cache_hierarchy.ruby_system.dot.pdf
A

[gem5-dev] Change in gem5/gem5[develop]: stdlib: Removing SingleChannelMemory

2021-12-07 Thread Mahyar Samani (Gerrit) via gem5-dev

Mahyar Samani has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53304 )


Change subject: stdlib: Removing SingleChannelMemory
..

stdlib: Removing SingleChannelMemory

This change removes the code base for SingleChannelMemory and
replaces it with MultiChannelMemory. muli_channel defines all
the classes that were defined by single_channel. Basically any
SingleChannelMemory could be thought of as a MultiChannelMemory
with 1 channel.

Change-Id: If96079d5f77be5a3ba26d2c2ddb98f5c60375cd8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53304
Reviewed-by: Bobby Bruce 
Maintainer: Bobby Bruce 
Tested-by: kokoro 
---
M configs/example/gem5_library/riscv-fs.py
A src/python/gem5/components/memory/memory.py
M configs/example/gem5_library/arm-hello.py
M tests/gem5/configs/boot_kvm_fork_run.py
M tests/gem5/configs/parsec_disk_run.py
M tests/gem5/configs/boot_kvm_switch_exit.py
M src/python/gem5/components/memory/multi_channel.py
M src/python/SConscript
M src/python/gem5/components/memory/__init__.py
M configs/example/gem5_library/x86-ubuntu-run.py
M tests/gem5/configs/riscv_boot_exit_run.py
M tests/gem5/configs/simple_binary_run.py
M src/python/gem5/components/memory/single_channel.py
M tests/gem5/traffic_gen/test_memory_traffic_gen.py
M tests/gem5/configs/x86_boot_exit_run.py
15 files changed, 321 insertions(+), 345 deletions(-)

Approvals:
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/configs/example/gem5_library/arm-hello.py  
b/configs/example/gem5_library/arm-hello.py

index 540a96b..5a2f46c 100644
--- a/configs/example/gem5_library/arm-hello.py
+++ b/configs/example/gem5_library/arm-hello.py
@@ -47,11 +47,11 @@
 from gem5.isas import ISA
 from gem5.utils.requires import requires
 from gem5.resources.resource import Resource
+from gem5.components.memory import SingleChannelDDR3_1600
+from gem5.components.processors.cpu_types import CPUTypes
 from gem5.components.boards.simple_board import SimpleBoard
 from gem5.components.cachehierarchies.classic.no_cache import NoCache
-from gem5.components.memory.single_channel import SingleChannelDDR3_1600
 from gem5.components.processors.simple_processor import SimpleProcessor
-from gem5.components.processors.cpu_types import CPUTypes

 # This check ensures the gem5 binary is compiled to the ARM ISA target. If  
not,

 # an exception will be thrown.
diff --git a/configs/example/gem5_library/riscv-fs.py  
b/configs/example/gem5_library/riscv-fs.py

index f46a345..4d0a2c8 100644
--- a/configs/example/gem5_library/riscv-fs.py
+++ b/configs/example/gem5_library/riscv-fs.py
@@ -43,7 +43,7 @@
 from m5.objects import Root

 from gem5.components.boards.riscv_board import RiscvBoard
-from gem5.components.memory.single_channel import SingleChannelDDR3_1600
+from gem5.components.memory import SingleChannelDDR3_1600
 from gem5.components.processors.simple_processor import SimpleProcessor
 from gem5.components.cachehierarchies.classic.\
 private_l1_private_l2_cache_hierarchy import (
diff --git a/configs/example/gem5_library/x86-ubuntu-run.py  
b/configs/example/gem5_library/x86-ubuntu-run.py

index 9979c14..622f4f3 100644
--- a/configs/example/gem5_library/x86-ubuntu-run.py
+++ b/configs/example/gem5_library/x86-ubuntu-run.py
@@ -47,8 +47,8 @@
 import m5
 from m5.objects import Root

-from gem5.prebuilt.demo.x86_demo_board import X86DemoBoard
 from gem5.resources.resource import Resource
+from gem5.prebuilt.demo.x86_demo_board import X86DemoBoard

 # Here we setup the board. The prebuilt X86DemoBoard allows for  
Full-System X86

 # simulation.
@@ -64,4 +64,4 @@

 root = Root(full_system=True, system=board)
 m5.instantiate()
-m5.simulate()
\ No newline at end of file
+m5.simulate()
diff --git a/src/python/SConscript b/src/python/SConscript
index 4487bdd..3d91ccb 100644
--- a/src/python/SConscript
+++ b/src/python/SConscript
@@ -133,8 +133,9 @@
 PySource('gem5.components.memory', 'gem5/components/memory/__init__.py')
  
PySource('gem5.components.memory', 'gem5/components/memory/abstract_memory_system.py')

 PySource('gem5.components.memory', 'gem5/components/memory/dramsim_3.py')
-PySource('gem5.components.memory', 'gem5/components/memory/single_channel.py')
 PySource('gem5.components.memory', 'gem5/components/memory/simple.py')
+PySource('gem5.components.memory', 'gem5/components/memory/memory.py')
+PySource('gem5.components.memory', 'gem5/components/memory/single_channel.py')
  
PySource('gem5.components.memory', 'gem5/components/memory/multi_channel.py')

 PySource('gem5.components.memory.dram_interfaces',
 'gem5/components/memory/dram_interfaces/__init__.py')
diff --git a/src/python/gem5/components/memory/__init__.py  
b/src/python/gem5/components/memory/__init__.py

index e69de29..5e16865 100644
--- a/src/python/gem5/components/memory/__init__.py
+++

[gem5-dev] Change in gem5/gem5[develop]: tests: Adding MultiChannelMemory to riscv-boot

2021-12-07 Thread Mahyar Samani (Gerrit) via gem5-dev

Mahyar Samani has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53303 )


 (

5 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: tests: Adding MultiChannelMemory to riscv-boot
..

tests: Adding MultiChannelMemory to riscv-boot

This change adds MultiChannelMemory to the tests for full system
risc-v.

Change-Id: I3e9b6f7ac539c24ca9694c1c49afa09d0cecca2f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53303
Maintainer: Bobby Bruce 
Reviewed-by: Bobby Bruce 
Tested-by: kokoro 
---
M tests/gem5/riscv-boot-tests/test_linux_boot.py
M tests/gem5/configs/riscv_boot_exit_run.py
2 files changed, 79 insertions(+), 37 deletions(-)

Approvals:
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/tests/gem5/configs/riscv_boot_exit_run.py  
b/tests/gem5/configs/riscv_boot_exit_run.py

index 8add619..45ce62c 100644
--- a/tests/gem5/configs/riscv_boot_exit_run.py
+++ b/tests/gem5/configs/riscv_boot_exit_run.py
@@ -36,15 +36,15 @@
 import m5
 from m5.objects import Root

-from gem5.components.boards.riscv_board import RiscvBoard
-from gem5.components.memory.single_channel import SingleChannelDDR3_1600
-from gem5.components.processors.simple_processor import SimpleProcessor
-from gem5.components.processors.cpu_types import CPUTypes
 from gem5.isas import ISA
 from gem5.utils.requires import requires
 from gem5.resources.resource import Resource
+from gem5.components.processors.cpu_types import CPUTypes
+from gem5.components.boards.riscv_board import RiscvBoard
+from gem5.components.processors.simple_processor import SimpleProcessor

 import argparse
+import importlib

 parser = argparse.ArgumentParser(
 description="A script to run the RISCV boot exit tests."
@@ -77,6 +77,14 @@
 )

 parser.add_argument(
+"-d",
+"--dram-class",
+type=str,
+required=True,
+help="The python class for the memory interface to use"
+)
+
+parser.add_argument(
 "-t",
 "--tick-exit",
 type=int,
@@ -117,7 +125,11 @@
 )

 # Setup the system memory.
-memory = SingleChannelDDR3_1600()
+python_module = "gem5.components.memory.multi_channel"
+memory_class = getattr(
+importlib.import_module(python_module), args.dram_class
+)
+memory = memory_class(size="4GiB")

 # Setup a processor.
 if args.cpu == "kvm":
diff --git a/tests/gem5/riscv-boot-tests/test_linux_boot.py  
b/tests/gem5/riscv-boot-tests/test_linux_boot.py

index 9eb9ae3..6d4e9f1 100644
--- a/tests/gem5/riscv-boot-tests/test_linux_boot.py
+++ b/tests/gem5/riscv-boot-tests/test_linux_boot.py
@@ -40,12 +40,13 @@
 cpu: str,
 num_cpus: int,
 cache_type: str,
+memory_class: str,
 length: str,
 to_tick: Optional[int] = None,
 ):

-name = "{}-cpu_{}-{}-cores_riscv-boot-test".format(
-cpu, str(num_cpus), cache_type)
+name = "{}-cpu_{}-cores_{}_{}_riscv-boot-test".format(
+cpu, str(num_cpus), cache_type, memory_class)

 verifiers = []
 exit_regex = re.compile(
@@ -62,6 +63,8 @@
 str(num_cpus),
 "--mem-system",
 cache_type,
+"--dram-class",
+memory_class,
 "--resource-directory",
 resource_path,
 ]
@@ -94,6 +97,7 @@
 cpu="atomic",
 num_cpus=1,
 cache_type="classic",
+memory_class="SingleChannelDDR3_1600",
 length=constants.quick_tag,
 to_tick=100,  # Simulates 1/100th of a second.
 )
@@ -102,6 +106,7 @@
 cpu="timing",
 num_cpus=1,
 cache_type="classic",
+memory_class="SingleChannelDDR3_2133",
 length=constants.quick_tag,
 to_tick=100,
 )
@@ -110,6 +115,7 @@
 cpu="timing",
 num_cpus=1,
 cache_type="mi_example",
+memory_class="SingleChannelDDR4_2400",
 length=constants.quick_tag,
 to_tick=100,
 )
@@ -118,6 +124,7 @@
 cpu="o3",
 num_cpus=1,
 cache_type="classic",
+memory_class="DualChannelDDR3_1600",
 length=constants.quick_tag,
 to_tick=100,
 )
@@ -126,6 +133,7 @@
 cpu="timing",
 num_cpus=4,
 cache_type="classic",
+memory_class="DualChannelDDR3_2133",
 length=constants.quick_tag,
 to_tick=100,
 )
@@ -134,6 +142,7 @@
 cpu="timing",
 num_cpus=4,
 cache_type="mi_example",
+memory_class="DualChannelDDR4_2400",
 length=constants.quick_tag,
 to_tick=100,
 )
@@ -144,37 +153,42 @@
 # https://gem5.atlassian.net/browse/GEM5-1120, these tests have been  
disabled
 # until the exact error causing the Nightly tests to timeout is  
established.


-#test_boot(
-#cpu="atomic",
-#num_cpus=1,
-#cache_type="classic",
-#length=constants.long_tag,
-#)
+# test_boot(
+# cpu="atomic",
+# num_cpus=1,
+# cache_type="classic",
+# memory_class="HBM2Stack",
+# length=constants.long_tag,
+# )

[gem5-dev] Change in gem5/gem5[develop]: tests: Adding MultiChannelMemory to x86-boot-tests

2021-12-07 Thread Mahyar Samani (Gerrit) via gem5-dev

Mahyar Samani has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53243 )


 (

6 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: tests: Adding MultiChannelMemory to x86-boot-tests
..

tests: Adding MultiChannelMemory to x86-boot-tests

This change adds modules from multi_channel.py to full system
tests for x86.

Change-Id: I585a381fa23c6595051ea917c080228e25e0a1a9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53243
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Bobby Bruce 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M tests/gem5/x86-boot-tests/test_linux_boot.py
M tests/gem5/configs/x86_boot_exit_run.py
2 files changed, 60 insertions(+), 11 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve; Looks  
good to me, approved

  Bobby Bruce: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/tests/gem5/configs/x86_boot_exit_run.py  
b/tests/gem5/configs/x86_boot_exit_run.py

index 238136b..58e7713 100644
--- a/tests/gem5/configs/x86_boot_exit_run.py
+++ b/tests/gem5/configs/x86_boot_exit_run.py
@@ -35,16 +35,16 @@
 get_runtime_coherence_protocol,
 get_runtime_isa,
 )
-from gem5.utils.requires import requires
-from gem5.components.boards.x86_board import X86Board
-from gem5.components.memory.single_channel import SingleChannelDDR3_1600
-from gem5.components.processors.simple_processor import SimpleProcessor
-from gem5.components.processors.cpu_types import CPUTypes
 from gem5.isas import ISA
-from gem5.coherence_protocol import CoherenceProtocol
+from gem5.utils.requires import requires
 from gem5.resources.resource import Resource
+from gem5.coherence_protocol import CoherenceProtocol
+from gem5.components.boards.x86_board import X86Board
+from gem5.components.processors.cpu_types import CPUTypes
+from gem5.components.processors.simple_processor import SimpleProcessor

 import argparse
+import importlib

 parser = argparse.ArgumentParser(
 description="A script to run the gem5 boot test. This test boots the "
@@ -75,6 +75,13 @@
 help="The CPU type.",
 )
 parser.add_argument(
+"-d",
+"--dram-class",
+type=str,
+required=True,
+help="The python class for the memory interface to use"
+)
+parser.add_argument(
 "-b",
 "--boot-type",
 type=str,
@@ -154,7 +161,11 @@
 # Setup the system memory.
 # Warning: This must be kept at 3GB for now. X86Motherboard does not  
support

 # anything else right now!
-memory = SingleChannelDDR3_1600(size="3GB")
+python_module = "gem5.components.memory.multi_channel"
+memory_class = getattr(
+importlib.import_module(python_module), args.dram_class
+)
+memory = memory_class(size="3GiB")

 # Setup a Processor.

diff --git a/tests/gem5/x86-boot-tests/test_linux_boot.py  
b/tests/gem5/x86-boot-tests/test_linux_boot.py

index d90f53b..77d1c0d 100644
--- a/tests/gem5/x86-boot-tests/test_linux_boot.py
+++ b/tests/gem5/x86-boot-tests/test_linux_boot.py
@@ -39,13 +39,14 @@
 cpu: str,
 num_cpus: int,
 mem_system: str,
+memory_class: str,
 length: str,
 boot_type: str = "init",
 to_tick: Optional[int] = None,
 ):

-name = "{}-cpu_{}-cores_{}_{}_x86-boot-test".format(
-cpu, str(num_cpus), mem_system, boot_type
+name = "{}-cpu_{}-cores_{}_{}_{}_x86-boot-test".format(
+cpu, str(num_cpus), mem_system, memory_class, boot_type
 )
 verifiers = []
 additional_config_args = []
@@ -89,6 +90,8 @@
 str(num_cpus),
 "--mem-system",
 mem_system,
+"--dram-class",
+memory_class,
 "--boot-type",
 boot_type,
 "--resource-directory",
@@ -108,6 +111,7 @@
 cpu="atomic",
 num_cpus=1,
 mem_system="classic",
+memory_class="SingleChannelDDR3_1600",
 to_tick=100, #Simulates 1/100th of a second.
 length=constants.quick_tag,
 )
@@ -116,6 +120,7 @@
 cpu="timing",
 num_cpus=1,
 mem_system="classic",
+memory_class="SingleChannelDDR3_2133",
 to_tick=100,
 length=constants.quick_tag,
 )
@@ -124,6 +129,7 @@
 cpu="atomic",
 num_cpus=4,
 mem_system="classic",
+memory_class="SingleChannelDDR4_2400",
 to_tick=100,
 length=constants.quick_tag,
 )
@@ -132,6 +138,7 @@
 cpu="o3",
 num_cpus=1,
 mem_system="classic",
+memory_class="SingleChannelLPDDR3_1600",
 to_tick=100,
 length=constants.quick_tag,
 )
@@ -142,6 +149,7 @@
 cpu="atomic",
 num_cpus=1,
 mem_system="classic",
+memory_class="SingleChannelHBM",
 boot_type="init",
 length=constants.long_tag,
 )
@@ -150,6 +158,7 @@
 cpu="timing",
 num_cpus=1,
 mem_system="mesi_two_level",
+memory_class="DualChannelDDR3_1600",
 boot_type="init",

[gem5-dev] Change in gem5/gem5[develop]: test: Updating simple_traffic_run and adding tests

2021-12-07 Thread Mahyar Samani (Gerrit) via gem5-dev

Mahyar Samani has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53164 )


 (

8 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: test: Updating simple_traffic_run and adding tests
..

test: Updating simple_traffic_run and adding tests

This change updates simple_traffic_run.py with adding clock_domain
for GUPSGen based generators. Also the tests that resulted in
error before are now fixed and added.

Change-Id: I992898a3aef509afd9dec1f9b5d14c5fd67cff37
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53164
Reviewed-by: Bobby Bruce 
Maintainer: Bobby Bruce 
Tested-by: kokoro 
---
M tests/gem5/traffic_gen/simple_traffic_run.py
M tests/gem5/traffic_gen/test_memory_traffic_gen.py
2 files changed, 24 insertions(+), 7 deletions(-)

Approvals:
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/tests/gem5/traffic_gen/simple_traffic_run.py  
b/tests/gem5/traffic_gen/simple_traffic_run.py

index 5230045..ede4993 100644
--- a/tests/gem5/traffic_gen/simple_traffic_run.py
+++ b/tests/gem5/traffic_gen/simple_traffic_run.py
@@ -35,7 +35,6 @@
 import argparse
 import importlib

-from os.path import join
 from m5.objects import Root, MemorySize
 from gem5.components.boards.test_board import TestBoard

@@ -71,15 +70,18 @@
 from gem5.components.processors.gups_generator import GUPSGenerator

 table_size = f"{int(mem_size / 2)}B"
-return GUPSGenerator(0, table_size, update_limit=1000)
+return GUPSGenerator(
+0, table_size, update_limit=1000, clk_freq="2GHz"
+)
 elif generator_class == "GUPSGeneratorEP":
 from gem5.components.processors.gups_generator_ep import (
 GUPSGeneratorEP,
 )

 table_size = f"{int(mem_size / 2)}B"
+
 return GUPSGeneratorEP(
-generator_cores, 0, table_size, update_limit=1000
+generator_cores, 0, table_size, update_limit=1000,  
clk_freq="2GHz"

 )
 elif generator_class == "GUPSGeneratorPAR":
 from gem5.components.processors.gups_generator_par import (
@@ -88,7 +90,7 @@

 table_size = f"{int(mem_size / 2)}B"
 return GUPSGeneratorPAR(
-generator_cores, 0, table_size, update_limit=1000
+generator_cores, 0, table_size, update_limit=1000,  
clk_freq="2GHz"

 )
 else:
 raise ValueError(f"Unknown generator class {generator_class}")
diff --git a/tests/gem5/traffic_gen/test_memory_traffic_gen.py  
b/tests/gem5/traffic_gen/test_memory_traffic_gen.py

index e5126ba..13b4638 100644
--- a/tests/gem5/traffic_gen/test_memory_traffic_gen.py
+++ b/tests/gem5/traffic_gen/test_memory_traffic_gen.py
@@ -106,9 +106,7 @@


 def create_single_core_tests(module, memory_classes):
-# TODO: Add GUPSGenerator to these tests after adding ClockDomain as
-# an input parameter.
-generator_classes = ["LinearGenerator", "RandomGenerator"]
+generator_classes =  
["LinearGenerator", "RandomGenerator", "GUPSGenerator"]

 for generator_class in generator_classes:
 for cache_class in cache_classes:
 for memory_class in memory_classes:

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/53164
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I992898a3aef509afd9dec1f9b5d14c5fd67cff37
Gerrit-Change-Number: 53164
Gerrit-PatchSet: 10
Gerrit-Owner: Mahyar Samani 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Mahyar Samani 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: stdlib: Adding clock_domain to GUPSGenerators

2021-12-07 Thread Mahyar Samani (Gerrit) via gem5-dev

Mahyar Samani has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53163 )


 (

8 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: stdlib: Adding clock_domain to GUPSGenerators
..

stdlib: Adding clock_domain to GUPSGenerators

This change adds clock domain as a parameter to the GUPSGen
classes. This way the generator and other components can
work on different clock frequencies.

Change-Id: If916877a57b3c3a61073dad075e35f3f93af8459
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53163
Tested-by: kokoro 
Reviewed-by: Bobby Bruce 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M src/python/gem5/components/processors/gups_generator_core.py
M src/python/gem5/components/processors/gups_generator_par.py
M src/python/gem5/components/processors/gups_generator.py
M src/python/gem5/components/processors/gups_generator_ep.py
4 files changed, 53 insertions(+), 21 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve; Looks  
good to me, approved

  Bobby Bruce: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/python/gem5/components/processors/gups_generator.py  
b/src/python/gem5/components/processors/gups_generator.py

index 191be6b..41d1812 100644
--- a/src/python/gem5/components/processors/gups_generator.py
+++ b/src/python/gem5/components/processors/gups_generator.py
@@ -25,15 +25,14 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.


-from ...utils.override import overrides
+from typing import Optional
 from m5.objects import Addr
+from ...utils.override import overrides

 from ..boards.mem_mode import MemMode
-
-from .gups_generator_core import GUPSGeneratorCore
-
 from .abstract_processor import AbstractProcessor
 from ..boards.abstract_board import AbstractBoard
+from .gups_generator_core import GUPSGeneratorCore


 class GUPSGenerator(AbstractProcessor):
@@ -42,6 +41,7 @@
 start_addr: Addr,
 mem_size: str,
 update_limit: int = 0,
+clk_freq: Optional[str] = None,
 ):
 """The GUPSGenerator class
 This class defines the interface for a single core GUPSGenerator,  
this

@@ -63,6 +63,7 @@
 start_addr=start_addr,
 mem_size=mem_size,
 update_limit=update_limit,
+clk_freq=clk_freq,
 )
 ]
 )
diff --git a/src/python/gem5/components/processors/gups_generator_core.py  
b/src/python/gem5/components/processors/gups_generator_core.py

index 8ce921e..f315b8b 100644
--- a/src/python/gem5/components/processors/gups_generator_core.py
+++ b/src/python/gem5/components/processors/gups_generator_core.py
@@ -24,10 +24,11 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from m5.objects import Port, GUPSGen, Addr

+from typing import Optional
 from ...utils.override import overrides
 from .abstract_generator_core import AbstractGeneratorCore
+from m5.objects import Port, GUPSGen, Addr, SrcClockDomain, VoltageDomain


 class GUPSGeneratorCore(AbstractGeneratorCore):
@@ -36,14 +37,24 @@
 start_addr: Addr,
 mem_size: str,
 update_limit: int,
+clk_freq: Optional[str],
 ):
 """
 Create a GUPSGeneratorCore as the main generator.
 """
 super().__init__()
 self.generator = GUPSGen(
-start_addr=start_addr, mem_size=mem_size,  
update_limit=update_limit

-)
+start_addr=start_addr,
+mem_size=mem_size,
+update_limit=update_limit,
+)
+if clk_freq:
+clock_domain = SrcClockDomain(
+clock=clk_freq, voltage_domain=VoltageDomain()
+)
+self.generator.clk_domain = clock_domain
+
+

 @overrides(AbstractGeneratorCore)
 def connect_dcache(self, port: Port) -> None:
diff --git a/src/python/gem5/components/processors/gups_generator_ep.py  
b/src/python/gem5/components/processors/gups_generator_ep.py

index 203a88c..da27494 100644
--- a/src/python/gem5/components/processors/gups_generator_ep.py
+++ b/src/python/gem5/components/processors/gups_generator_ep.py
@@ -25,17 +25,14 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.


-from ...utils.override import overrides
+from typing import Optional
 from m5.objects import Addr
-from m5.util.convert import toMemorySize
-
 from ..boards.mem_mode import MemMode
-
-from .gups_generator_core import GUPSGeneratorCore
-
+from ...utils.override import overrides
+from m5.util.convert import toMemorySize
 from .abstract_processor import AbstractProcessor
 from ..boards.abstract_board import AbstractBoard

[gem5-dev] Change in gem5/gem5[develop]: tests: Adding new test for traffic_gen

2021-12-07 Thread Mahyar Samani (Gerrit) via gem5-dev

Mahyar Samani has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/52905 )


 (

13 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: tests: Adding new test for traffic_gen
..

tests: Adding new test for traffic_gen

This change adds new tests for MultiChannelMemory,
PrivateL1CacheHierarchy, PrivateL1PrivateL2CacheHierachy,
GUPSGenerator, GUPSGeneratorEP, GUPSGeneratorPAR.

Change-Id: I1db1281cdd4ade65d9abf2d979ef45342b63496a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52905
Maintainer: Bobby Bruce 
Tested-by: kokoro 
Reviewed-by: Bobby Bruce 
---
A tests/gem5/traffic_gen/simple_traffic_run.py
M tests/gem5/traffic_gen/test_memory_traffic_gen.py
D tests/gem5/configs/simple_traffic_run.py
3 files changed, 309 insertions(+), 288 deletions(-)

Approvals:
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/tests/gem5/configs/simple_traffic_run.py  
b/tests/gem5/configs/simple_traffic_run.py

deleted file mode 100644
index 33e4419..000
--- a/tests/gem5/configs/simple_traffic_run.py
+++ /dev/null
@@ -1,148 +0,0 @@
-# Copyright (c) 2021 The Regents of the University of California
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-"""
-This scripts is used for checking the correctness of statistics reported
-by the gem5 simulator. It can excercise certain components in the memory
-subsystem. The reported values could be used to compare against a validated
-set of statistics.
-"""
-
-import m5
-import argparse
-import importlib
-
-from os.path import join
-from m5.objects import Root
-from m5.stats import gem5stats
-from gem5.components.boards.test_board import TestBoard
-from gem5.components.processors.linear_generator import LinearGenerator
-from gem5.components.processors.random_generator import RandomGenerator
-
-
-generator_class_map = {
-"LinearGenerator": LinearGenerator,
-"RandomGenerator": RandomGenerator,
-}
-
-generator_initializers = dict(rate="20GB/s")
-
-
-def cache_factory(cache_class):
-if cache_class == "NoCache":
-from gem5.components.cachehierarchies.classic.no_cache import  
NoCache

-
-return NoCache()
-elif cache_class == "MESITwoLevel":
-from gem5.components.cachehierarchies.ruby\
-.mesi_two_level_cache_hierarchy import (
-MESITwoLevelCacheHierarchy,
-)
-
-return MESITwoLevelCacheHierarchy(
-l1i_size="32KiB",
-l1i_assoc="8",
-l1d_size="32KiB",
-l1d_assoc="8",
-l2_size="256KiB",
-l2_assoc="4",
-num_l2_banks=1,
-)
-else:
-raise ValueError(f"The cache class {cache_class} is not  
supported.")

-
-
-parser = argparse.ArgumentParser(
-description="A traffic generator that can be used to test a gem5 "
-"memory component."
-)
-
-parser.add_argument(
-"generator_class",
-type=str,
-help="The class of generator to use.",
-choices=["LinearGenerator", "RandomGenerator"],
-)
-
-parser.add_argument(
-"cache_class",
-type=str,
-help="The cache class to import and instantiate.",
-choices=["NoCache", "MESITwoLevel"],
-)
-
-parser.add_argument(
-"mem_module",
-type=str,
-help="The python module to import for memory.",
-)
-
-parser.add_argument(
-"mem_class", type=str,

[gem5-dev] Change in gem5/gem5[develop]: stdlib: Updated MuliChannelMemory constructor

2021-12-07 Thread Mahyar Samani (Gerrit) via gem5-dev

Mahyar Samani has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/52904 )


Change subject: stdlib: Updated MuliChannelMemory constructor
..

stdlib: Updated MuliChannelMemory constructor

This change updates the constructor for MultiChannelMemory. The
constructor now assumes every input parameter is of type string
and casts them to proper types inside the function. This way
the MultiChannelMemory could be tested easier. Considering that
tests might not want to pass in all the arguments and might use
argparser to read the inputs.

Change-Id: I80786066ccbb9cb1b7111831d9bc9d95e5204f40
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52904
Maintainer: Bobby Bruce 
Tested-by: kokoro 
Reviewed-by: Bobby Bruce 
---
M src/python/gem5/components/memory/multi_channel.py
1 file changed, 176 insertions(+), 15 deletions(-)

Approvals:
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/python/gem5/components/memory/multi_channel.py  
b/src/python/gem5/components/memory/multi_channel.py

index 7d4baf1..8736f02 100644
--- a/src/python/gem5/components/memory/multi_channel.py
+++ b/src/python/gem5/components/memory/multi_channel.py
@@ -27,16 +27,21 @@
 """Multi channel "generic" DDR memory controllers
 """

-import enum
 from math import log
 from ...utils.override import overrides
 from m5.util.convert import toMemorySize
 from ..boards.abstract_board import AbstractBoard
 from .abstract_memory_system import AbstractMemorySystem
-from typing import Type, Sequence, Tuple, List, Optional
 from m5.objects import AddrRange, DRAMInterface, MemCtrl, Port
+from typing import Type, Sequence, Tuple, List, Optional, Union


+def _try_convert(val, cls):
+try:
+return cls(val)
+except:
+raise Exception(f"Could not convert {val} to {cls}")
+
 def _isPow2(num):
 log_num = int(log(num, 2))
 if 2 ** log_num != num:
@@ -53,8 +58,8 @@
 def __init__(
 self,
 dram_interface_class: Type[DRAMInterface],
-num_channels: int,
-interleaving_size: int,
+num_channels: Union[int, str],
+interleaving_size: Union[int, str],
 size: Optional[str] = None,
 addr_mapping: Optional[str] = None,
 ) -> None:
@@ -66,12 +71,21 @@
 :param size: Optionally specify the size of the DRAM controller's
 address space. By default, it starts at 0 and ends at the size  
of

 the DRAM device specified
-:param add_mapping: Defines the address mapping scheme to be used.
-By default, it is RoRaBaChCo
+:param addr_mapping: Defines the address mapping scheme to be used.
+If None, it is defaulted to addr_mapping from  
dram_interface_class.
 :param interleaving_size: Defines the interleaving size of the  
multi-

 channel memory system. By default, it is equivalent to the atom
 size, i.e., 64.
 """
+num_channels = _try_convert(num_channels, int)
+interleaving_size = _try_convert(interleaving_size, int)
+
+if size:
+size = _try_convert(size, str)
+
+if addr_mapping:
+addr_mapping = _try_convert(addr_mapping, str)
+
 super().__init__()
 self._dram_class = dram_interface_class
 self._num_channels = num_channels
@@ -98,7 +112,6 @@
 MemCtrl(dram=self._dram[i]) for i in range(num_channels)
 ]

-
 def _get_dram_size(self, num_channels: int, dram: DRAMInterface) ->  
int:

 return num_channels * (
 dram.device_size.value
@@ -107,8 +120,6 @@
 )

 def _interleave_addresses(self):
-print(f"Memory is interleaving the address range {self._mem_range}"
-f" using {self._intlv_size} as interleaving size.")
 if self._addr_mapping == "RoRaBaChCo":
 rowbuffer_size = (
 self._dram_class.device_rowbuffer_size.value
@@ -127,8 +138,8 @@
 for i, ctrl in enumerate(self.mem_ctrl):
 ctrl.dram.range = AddrRange(
 start=self._mem_range.start,
-end=self._mem_range.size(),
-intlvHighBit = intlv_low_bit + intlv_bits - 1,
+size=self._mem_range.size(),
+intlvHighBit=intlv_low_bit + intlv_bits - 1,
 xorHighBit=0,
 intlvBits=intlv_bits,
 intlvMatch=i,
@@ -137,10 +148,12 @@
 @overrides(AbstractMemorySystem)
 def incorporate_memory(self, board: AbstractBoard) -> None:
 if self._intlv_size < int(board.get_cache_line_size()):
-raise ValueError("Memory interleaving size can not be smaller  
than"

-" board's cache line size.\nBoard's cache line size: "
-f"{board.get_cache_line_size()}\n, This memory's interleaving "
-f"size:

[gem5-dev] Change in gem5/gem5[develop]: stdlib: Removing SingleChannelMemory

2021-11-28 Thread Mahyar Samani (Gerrit) via gem5-dev

Mahyar Samani has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53304 )



Change subject: stdlib: Removing SingleChannelMemory
..

stdlib: Removing SingleChannelMemory

This change removes the code base for SingleChannelMemory and
replaces it with MultiChannelMemory. muli_channel defines all
the classes that were defined by single_channel. Basically any
SingleChannelMemory could be thought of as a MultiChannelMemory
with 1 channel.

Change-Id: If96079d5f77be5a3ba26d2c2ddb98f5c60375cd8
---
M configs/example/gem5_library/riscv-fs.py
M configs/example/gem5_library/arm-hello.py
M tests/gem5/configs/boot_kvm_fork_run.py
M tests/gem5/configs/parsec_disk_run.py
M tests/gem5/configs/boot_kvm_switch_exit.py
M src/python/SConscript
M configs/example/gem5_library/x86-ubuntu-run.py
M tests/gem5/configs/simple_binary_run.py
D src/python/gem5/components/memory/single_channel.py
M tests/gem5/traffic_gen/test_memory_traffic_gen.py
10 files changed, 22 insertions(+), 153 deletions(-)



diff --git a/configs/example/gem5_library/arm-hello.py  
b/configs/example/gem5_library/arm-hello.py

index 540a96b..8be714d 100644
--- a/configs/example/gem5_library/arm-hello.py
+++ b/configs/example/gem5_library/arm-hello.py
@@ -49,7 +49,7 @@
 from gem5.resources.resource import Resource
 from gem5.components.boards.simple_board import SimpleBoard
 from gem5.components.cachehierarchies.classic.no_cache import NoCache
-from gem5.components.memory.single_channel import SingleChannelDDR3_1600
+from gem5.components.memory.multi_channel import SingleChannelDDR3_1600
 from gem5.components.processors.simple_processor import SimpleProcessor
 from gem5.components.processors.cpu_types import CPUTypes

diff --git a/configs/example/gem5_library/riscv-fs.py  
b/configs/example/gem5_library/riscv-fs.py

index f46a345..d79e3bf 100644
--- a/configs/example/gem5_library/riscv-fs.py
+++ b/configs/example/gem5_library/riscv-fs.py
@@ -43,7 +43,7 @@
 from m5.objects import Root

 from gem5.components.boards.riscv_board import RiscvBoard
-from gem5.components.memory.single_channel import SingleChannelDDR3_1600
+from gem5.components.memory.multi_channel import SingleChannelDDR3_1600
 from gem5.components.processors.simple_processor import SimpleProcessor
 from gem5.components.cachehierarchies.classic.\
 private_l1_private_l2_cache_hierarchy import (
diff --git a/configs/example/gem5_library/x86-ubuntu-run.py  
b/configs/example/gem5_library/x86-ubuntu-run.py

index 1ab9f3a..95b1acd 100644
--- a/configs/example/gem5_library/x86-ubuntu-run.py
+++ b/configs/example/gem5_library/x86-ubuntu-run.py
@@ -46,7 +46,7 @@

 from gem5.utils.requires import requires
 from gem5.components.boards.x86_board import X86Board
-from gem5.components.memory.single_channel import SingleChannelDDR3_1600
+from gem5.components.memory.multi_channel import SingleChannelDDR3_1600
 from gem5.components.processors.simple_switchable_processor import (
 SimpleSwitchableProcessor,
 )
diff --git a/src/python/SConscript b/src/python/SConscript
index d210960..d457cf4 100644
--- a/src/python/SConscript
+++ b/src/python/SConscript
@@ -117,7 +117,6 @@
 PySource('gem5.components.memory', 'gem5/components/memory/__init__.py')
  
PySource('gem5.components.memory', 'gem5/components/memory/abstract_memory_system.py')

 PySource('gem5.components.memory', 'gem5/components/memory/dramsim_3.py')
-PySource('gem5.components.memory', 'gem5/components/memory/single_channel.py')
 PySource('gem5.components.memory', 'gem5/components/memory/simple.py')
  
PySource('gem5.components.memory', 'gem5/components/memory/multi_channel.py')

 PySource('gem5.components.memory.dram_interfaces',
diff --git a/src/python/gem5/components/memory/single_channel.py  
b/src/python/gem5/components/memory/single_channel.py

deleted file mode 100644
index 11a0b15..000
--- a/src/python/gem5/components/memory/single_channel.py
+++ /dev/null
@@ -1,136 +0,0 @@
-# Copyright (c) 2021 The Regents of the University of California
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF

[gem5-dev] Change in gem5/gem5[develop]: tests: Adding MultiChannelMemory to x86-boot-tests

2021-11-24 Thread Mahyar Samani (Gerrit) via gem5-dev

Mahyar Samani has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53243 )



Change subject: tests: Adding MultiChannelMemory to x86-boot-tests
..

tests: Adding MultiChannelMemory to x86-boot-tests

This change adds modules from multi_channel.py to full system
tests for x86.

Change-Id: I585a381fa23c6595051ea917c080228e25e0a1a9
---
M tests/gem5/x86-boot-tests/test_linux_boot.py
M tests/gem5/configs/x86_boot_exit_run.py
2 files changed, 105 insertions(+), 20 deletions(-)



diff --git a/tests/gem5/configs/x86_boot_exit_run.py  
b/tests/gem5/configs/x86_boot_exit_run.py

index 238136b..90f99af 100644
--- a/tests/gem5/configs/x86_boot_exit_run.py
+++ b/tests/gem5/configs/x86_boot_exit_run.py
@@ -35,16 +35,16 @@
 get_runtime_coherence_protocol,
 get_runtime_isa,
 )
-from gem5.utils.requires import requires
-from gem5.components.boards.x86_board import X86Board
-from gem5.components.memory.single_channel import SingleChannelDDR3_1600
-from gem5.components.processors.simple_processor import SimpleProcessor
-from gem5.components.processors.cpu_types import CPUTypes
 from gem5.isas import ISA
-from gem5.coherence_protocol import CoherenceProtocol
+from gem5.utils.requires import requires
 from gem5.resources.resource import Resource
+from gem5.coherence_protocol import CoherenceProtocol
+from gem5.components.boards.x86_board import X86Board
+from gem5.components.processors.cpu_types import CPUTypes
+from gem5.components.processors.simple_processor import SimpleProcessor

 import argparse
+import importlib

 parser = argparse.ArgumentParser(
 description="A script to run the gem5 boot test. This test boots the "
@@ -75,6 +75,20 @@
 help="The CPU type.",
 )
 parser.add_argument(
+"-p",
+"--python-mem-module",
+type=str,
+required=True,
+help="The python module that includes definition for the memory to  
test"

+)
+parser.add_argument(
+"-d",
+"--python-mem-dram",
+type=str,
+required=True,
+help="The python class for the memory interface to use"
+)
+parser.add_argument(
 "-b",
 "--boot-type",
 type=str,
@@ -154,7 +168,10 @@
 # Setup the system memory.
 # Warning: This must be kept at 3GB for now. X86Motherboard does not  
support

 # anything else right now!
-memory = SingleChannelDDR3_1600(size="3GB")
+memory_class = getattr(
+importlib.import_module(args.python_mem_module),  
args.python_mem_interface

+)
+memory = memory_class(size="3GiB")

 # Setup a Processor.

diff --git a/tests/gem5/x86-boot-tests/test_linux_boot.py  
b/tests/gem5/x86-boot-tests/test_linux_boot.py

index 600d04b..de2f499 100644
--- a/tests/gem5/x86-boot-tests/test_linux_boot.py
+++ b/tests/gem5/x86-boot-tests/test_linux_boot.py
@@ -39,13 +39,15 @@
 cpu: str,
 num_cpus: int,
 mem_system: str,
+memory_module: str,
+memory_class: str,
 length: str,
 boot_type: str = "init",
 to_tick: Optional[int] = None,
 ):

-name = "{}-cpu_{}-cores_{}_{}_x86-boot-test".format(
-cpu, str(num_cpus), mem_system, boot_type
+name = "{}-cpu_{}-cores_{}_{}_{}_{}_x86-boot-test".format(
+cpu, str(num_cpus), mem_system, memory_module, memory_class,  
boot_type

 )
 verifiers = []
 additional_config_args = []
@@ -89,6 +91,10 @@
 str(num_cpus),
 "--mem-system",
 mem_system,
+"--python-mem-module",
+memory_module,
+"--python-mem-dram",
+memory_class,
 "--boot-type",
 boot_type,
 "--resource-directory",
@@ -108,6 +114,8 @@
 cpu="atomic",
 num_cpus=1,
 mem_system="classic",
+memory_module="gem5.componenets.memory.multi_channel",
+memory_class="SingleChannelDDR3_1600",
 to_tick=100, #Simulates 1/100th of a second.
 length=constants.quick_tag,
 )
@@ -116,6 +124,8 @@
 cpu="timing",
 num_cpus=1,
 mem_system="classic",
+memory_module="gem5.componenets.memory.multi_channel",
+memory_class="SingleChannelDDR3_1600",
 to_tick=100,
 length=constants.quick_tag,
 )
@@ -124,6 +134,8 @@
 cpu="atomic",
 num_cpus=4,
 mem_system="classic",
+memory_module="gem5.componenets.memory.multi_channel",
+memory_class="SingleChannelDDR3_1600",
 to_tick=100,
 length=constants.quick_tag,
 )
@@ -132,6 +144,8 @@
 cpu="o3",
 num_cpus=1,
 mem_system="classic",
+memory_module="gem5.componenets.memory.multi_channel",
+memory_class="SingleChannelDDR3_1600",
 to_tick=100,
 length=constants.quick_tag,
 )
@@ -142,6 +156,8 @@
 cpu="atomic",
 num_cpus=1,
 mem_system="classic",
+memory_module="gem5.componenets.memory.multi_channel",
+memory_class="SingleChannelDDR3_1600",
 boot_type="init",
 length=constants.long_tag,
 )
@@ -150,6 +166,8 @@
 cpu="timing",
 num_cpus=1,

[gem5-dev] Change in gem5/gem5[develop]: stdlib: Adding clock_domain to GUPSGenerators

2021-11-23 Thread Mahyar Samani (Gerrit) via gem5-dev

Mahyar Samani has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53163 )



Change subject: stdlib: Adding clock_domain to GUPSGenerators
..

stdlib: Adding clock_domain to GUPSGenerators

This change adds clock domain as a parameter to the GUPSGen
classes. This way the generator and other components can
work on different clock frequencies.

Change-Id: If916877a57b3c3a61073dad075e35f3f93af8459
---
M src/python/gem5/components/processors/gups_generator_core.py
M src/python/gem5/components/processors/gups_generator_par.py
M src/python/gem5/components/processors/gups_generator.py
M src/python/gem5/components/processors/gups_generator_ep.py
4 files changed, 43 insertions(+), 9 deletions(-)



diff --git a/src/python/gem5/components/processors/gups_generator.py  
b/src/python/gem5/components/processors/gups_generator.py

index 191be6b..626f5ac 100644
--- a/src/python/gem5/components/processors/gups_generator.py
+++ b/src/python/gem5/components/processors/gups_generator.py
@@ -26,7 +26,7 @@


 from ...utils.override import overrides
-from m5.objects import Addr
+from m5.objects import Addr, ClockDomain

 from ..boards.mem_mode import MemMode

@@ -42,6 +42,7 @@
 start_addr: Addr,
 mem_size: str,
 update_limit: int = 0,
+clock_domain: ClockDomain = None,
 ):
 """The GUPSGenerator class
 This class defines the interface for a single core GUPSGenerator,  
this

@@ -63,6 +64,7 @@
 start_addr=start_addr,
 mem_size=mem_size,
 update_limit=update_limit,
+clock_domain=clock_domain,
 )
 ]
 )
diff --git a/src/python/gem5/components/processors/gups_generator_core.py  
b/src/python/gem5/components/processors/gups_generator_core.py

index 8ce921e..4bcd8b9 100644
--- a/src/python/gem5/components/processors/gups_generator_core.py
+++ b/src/python/gem5/components/processors/gups_generator_core.py
@@ -24,7 +24,7 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from m5.objects import Port, GUPSGen, Addr
+from m5.objects import Port, GUPSGen, Addr, ClockDomain

 from ...utils.override import overrides
 from .abstract_generator_core import AbstractGeneratorCore
@@ -36,14 +36,25 @@
 start_addr: Addr,
 mem_size: str,
 update_limit: int,
+clock_domain: ClockDomain,
 ):
 """
 Create a GUPSGeneratorCore as the main generator.
 """
 super().__init__()
-self.generator = GUPSGen(
-start_addr=start_addr, mem_size=mem_size,  
update_limit=update_limit

-)
+if clock_domain:
+self.generator = GUPSGen(
+start_addr=start_addr,
+mem_size=mem_size,
+update_limit=update_limit,
+clk_domain=clock_domain
+)
+else:
+self.generator = GUPSGen(
+start_addr=start_addr,
+mem_size=mem_size,
+update_limit=update_limit,
+)

 @overrides(AbstractGeneratorCore)
 def connect_dcache(self, port: Port) -> None:
diff --git a/src/python/gem5/components/processors/gups_generator_ep.py  
b/src/python/gem5/components/processors/gups_generator_ep.py

index 203a88c..8779e38 100644
--- a/src/python/gem5/components/processors/gups_generator_ep.py
+++ b/src/python/gem5/components/processors/gups_generator_ep.py
@@ -26,7 +26,7 @@


 from ...utils.override import overrides
-from m5.objects import Addr
+from m5.objects import Addr, ClockDomain
 from m5.util.convert import toMemorySize

 from ..boards.mem_mode import MemMode
@@ -44,6 +44,7 @@
 start_addr: Addr,
 mem_size: str,
 update_limit: int = 0,
+clock_domain: ClockDomain = None,
 ):
 """The GUPSGeneratorEP class
 This class defines the interface for multi core GUPSGenerator, this
@@ -64,6 +65,7 @@
 start_addr=start_addr,
 mem_size=mem_size,
 update_limit=update_limit,
+clock_domain=clock_domain,
 )
 )

@@ -73,6 +75,7 @@
 start_addr: Addr,
 mem_size: str,
 update_limit: int,
+clock_domain: ClockDomain = None,
 ):
 """
 Helper function to create cores.
@@ -85,6 +88,7 @@
 start_addr=start_addr + i * chunk_size,
 mem_size=table_size,
 update_limit=update_limit,
+clock_domain=clock_domain
 )
 for i in range(num_cores)
 ]
diff --git a/src/python/gem5/components/processors/gups_generator_par.py  
b/src/python/gem5/components/processors/gups_generator_par.py

index aad360a..7a2e0de 100644
---

[gem5-dev] Change in gem5/gem5[develop]: test: Updating simple_traffic_run and adding tests

2021-11-23 Thread Mahyar Samani (Gerrit) via gem5-dev

Mahyar Samani has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53164 )



Change subject: test: Updating simple_traffic_run and adding tests
..

test: Updating simple_traffic_run and adding tests

This change updates simple_traffic_run.py with adding clock_domain
for GUPSGen based generators. Also the tests that resulted in
error before are now fixed and added.

Change-Id: I992898a3aef509afd9dec1f9b5d14c5fd67cff37
---
M tests/gem5/traffic_gen/test_memory_traffic_gen.py
M tests/gem5/configs/simple_traffic_run.py
2 files changed, 28 insertions(+), 5 deletions(-)



diff --git a/tests/gem5/configs/simple_traffic_run.py  
b/tests/gem5/configs/simple_traffic_run.py

index 0836580..5b86ae6 100644
--- a/tests/gem5/configs/simple_traffic_run.py
+++ b/tests/gem5/configs/simple_traffic_run.py
@@ -36,9 +36,9 @@
 import importlib

 from os.path import join
-from m5.objects import Root
 from m5.stats import gem5stats
 from gem5.components.boards.test_board import TestBoard
+from m5.objects import Root, SrcClockDomain, VoltageDomain


 def generator_factory(generator_class, generator_cores, mem_size):
@@ -70,13 +70,21 @@
 from gem5.components.processors.gups_generator import GUPSGenerator

 table_size = f"{int(mem_size / 2)}B"
-return GUPSGenerator(0, table_size, update_limit=1000)
+clk_domain = SrcClockDomain(
+clock="2GHz", voltage_domain=VoltageDomain()
+)
+return GUPSGenerator(
+0, table_size, update_limit=1000, clock_domain=clk_domain
+)
 elif generator_class == "GUPSGeneratorEP":
 from gem5.components.processors.gups_generator_ep import (
 GUPSGeneratorEP,
 )

 table_size = f"{int(mem_size / 2)}B"
+clk_domain = SrcClockDomain(
+clock="2GHz", voltage_domain=VoltageDomain()
+)
 return GUPSGeneratorEP(
 generator_cores, 0, table_size, update_limit=1000
 )
@@ -86,12 +94,16 @@
 )

 table_size = f"{int(mem_size / 2)}B"
+clk_domain = SrcClockDomain(
+clock="2GHz", voltage_domain=VoltageDomain()
+)
 return GUPSGeneratorPAR(
 generator_cores, 0, table_size, update_limit=1000
 )
 else:
 raise ValueError(f"Unknown generator class {generator_class}")

+
 def cache_factory(cache_class):
 if cache_class == "NoCache":
 from gem5.components.cachehierarchies\
diff --git a/tests/gem5/traffic_gen/test_memory_traffic_gen.py  
b/tests/gem5/traffic_gen/test_memory_traffic_gen.py

index f6824c8..0ff24d2 100644
--- a/tests/gem5/traffic_gen/test_memory_traffic_gen.py
+++ b/tests/gem5/traffic_gen/test_memory_traffic_gen.py
@@ -106,9 +106,7 @@


 def create_single_core_tests(module, memory_classes):
-# TODO: Add GUPSGenerator to these tests after adding ClockDomain as
-# an input parameter.
-generator_classes = ["LinearGenerator", "RandomGenerator"]
+generator_classes =  
["LinearGenerator", "RandomGenerator", "GUPSGenerator"]

 for generator_class in generator_classes:
 for cache_class in cache_classes:
 for memory_class in memory_classes:

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/53164
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I992898a3aef509afd9dec1f9b5d14c5fd67cff37
Gerrit-Change-Number: 53164
Gerrit-PatchSet: 1
Gerrit-Owner: Mahyar Samani 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: cpu: Change GUPSGen::memSize to uint64_t

2021-11-17 Thread Mahyar Samani (Gerrit) via gem5-dev

Mahyar Samani has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/52903 )


Change subject: cpu: Change GUPSGen::memSize to uint64_t
..

cpu: Change GUPSGen::memSize to uint64_t

This change changes the type for GUPSGen::memSize to uint64_t.
Previously uint32_t was used that would overflow for memories
bigger than 4GB.

Change-Id: I45d992b166a0dee2322c03e40beef1eee73e1855
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52903
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Gabe Black 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/cpu/testers/traffic_gen/gups_gen.hh
1 file changed, 19 insertions(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Gabe Black: Looks good to me, but someone else must approve
  kokoro: Regressions pass




diff --git a/src/cpu/testers/traffic_gen/gups_gen.hh  
b/src/cpu/testers/traffic_gen/gups_gen.hh

index fa7b336..f33f7da 100644
--- a/src/cpu/testers/traffic_gen/gups_gen.hh
+++ b/src/cpu/testers/traffic_gen/gups_gen.hh
@@ -256,7 +256,7 @@
 /**
  * @brief Size of the memory in bytes that will be allocated for the  
array.

  */
-const uint32_t memSize;
+const uint64_t memSize;

 /**
  * @brief The number of updates to do before creating an exit event.

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/52903
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I45d992b166a0dee2322c03e40beef1eee73e1855
Gerrit-Change-Number: 52903
Gerrit-PatchSet: 2
Gerrit-Owner: Mahyar Samani 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Mahyar Samani 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: stdlib: Updated MuliChannelMemory constructor

2021-11-16 Thread Mahyar Samani (Gerrit) via gem5-dev

Mahyar Samani has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/52904 )



Change subject: stdlib: Updated MuliChannelMemory constructor
..

stdlib: Updated MuliChannelMemory constructor

This change updates the constructor for MultiChannelMemory. The
constructor now assumes every input parameter is of type string
and casts them to proper types inside the function. This way
the MultiChannelMemory could be tested easier. Considering that
tests might not want to pass in all the arguments and might use
argparser to read the inputs.

Change-Id: I80786066ccbb9cb1b7111831d9bc9d95e5204f40
---
M src/python/gem5/components/memory/multi_channel.py
1 file changed, 156 insertions(+), 11 deletions(-)



diff --git a/src/python/gem5/components/memory/multi_channel.py  
b/src/python/gem5/components/memory/multi_channel.py

index 7d4baf1..26e856f 100644
--- a/src/python/gem5/components/memory/multi_channel.py
+++ b/src/python/gem5/components/memory/multi_channel.py
@@ -27,8 +27,8 @@
 """Multi channel "generic" DDR memory controllers
 """

-import enum
 from math import log
+from warnings import warn
 from ...utils.override import overrides
 from m5.util.convert import toMemorySize
 from ..boards.abstract_board import AbstractBoard
@@ -53,8 +53,8 @@
 def __init__(
 self,
 dram_interface_class: Type[DRAMInterface],
-num_channels: int,
-interleaving_size: int,
+num_channels: str,
+interleaving_size: str,
 size: Optional[str] = None,
 addr_mapping: Optional[str] = None,
 ) -> None:
@@ -72,6 +72,42 @@
 channel memory system. By default, it is equivalent to the atom
 size, i.e., 64.
 """
+# Make sure the input parameters are of the correct type
+# Then cast them to the proper type they will be used
+if not isinstance(num_channels, str):
+warn(f"num_channels should be passed as a string. This could "
+"cause an exception. num_channels will be cast to int.")
+try:
+num_channels = int(num_channels)
+except:
+raise Exception("Could not cast num_channels to int.")
+
+if not isinstance(interleaving_size, str):
+warn(f"interleaving_size should be passed as a string. This  
could "

+"cause an exception. interleaving_size will be cast to int.")
+try:
+interleaving_size = int(interleaving_size)
+except:
+raise Exception("Could not cast interleaving_size to int.")
+
+if size:
+if not isinstance(size, str):
+warn(f"size should be passed as a string. This could  
cause "

+"an exception. size will be cast to string.")
+try:
+size = str(size)
+except:
+raise Exception("Could not cast size to str.")
+
+if addr_mapping:
+if not isinstance(addr_mapping, str):
+warn(f"addr_mapping should be passed as a string. This  
could "
+"cause and exception. addr_mapping will be cast to  
string.")

+try:
+addr_mapping = str(addr_mapping)
+except:
+raise Exception("Could not cast addr_mapping to str.")
+
 super().__init__()
 self._dram_class = dram_interface_class
 self._num_channels = num_channels
@@ -98,7 +134,6 @@
 MemCtrl(dram=self._dram[i]) for i in range(num_channels)
 ]

-
 def _get_dram_size(self, num_channels: int, dram: DRAMInterface) ->  
int:

 return num_channels * (
 dram.device_size.value
@@ -107,8 +142,10 @@
 )

 def _interleave_addresses(self):
-print(f"Memory is interleaving the address range {self._mem_range}"
-f" using {self._intlv_size} as interleaving size.")
+print(
+f"Memory is interleaving the address range {self._mem_range}"
+f" using {self._intlv_size} as interleaving size."
+)
 if self._addr_mapping == "RoRaBaChCo":
 rowbuffer_size = (
 self._dram_class.device_rowbuffer_size.value
@@ -128,7 +165,7 @@
 ctrl.dram.range = AddrRange(
 start=self._mem_range.start,
 end=self._mem_range.size(),
-intlvHighBit = intlv_low_bit + intlv_bits - 1,
+intlvHighBit=intlv_low_bit + intlv_bits - 1,
 xorHighBit=0,
 intlvBits=intlv_bits,
 intlvMatch=i,
@@ -137,10 +174,12 @@
 @overrides(AbstractMemorySystem)
 def incorporate_memory(self, board: AbstractBoard) -> None:
 if self._intlv_size < int(board.get_cache_line_size()):
-raise ValueError("Memory interleaving size can not be smaller  
than"

-" board's cache line size.\nBoard's

[gem5-dev] Change in gem5/gem5[develop]: cpu: Change GUPSGen::memSize to uint64_t

2021-11-16 Thread Mahyar Samani (Gerrit) via gem5-dev

Mahyar Samani has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/52903 )



Change subject: cpu: Change GUPSGen::memSize to uint64_t
..

cpu: Change GUPSGen::memSize to uint64_t

This change changes the type for GUPSGen::memSize to uint64_t.
Previously uint32_t was used that would overflow for memories
bigger than 4GB.

Change-Id: I45d992b166a0dee2322c03e40beef1eee73e1855
---
M src/cpu/testers/traffic_gen/gups_gen.hh
1 file changed, 14 insertions(+), 1 deletion(-)



diff --git a/src/cpu/testers/traffic_gen/gups_gen.hh  
b/src/cpu/testers/traffic_gen/gups_gen.hh

index fa7b336..f33f7da 100644
--- a/src/cpu/testers/traffic_gen/gups_gen.hh
+++ b/src/cpu/testers/traffic_gen/gups_gen.hh
@@ -256,7 +256,7 @@
 /**
  * @brief Size of the memory in bytes that will be allocated for the  
array.

  */
-const uint32_t memSize;
+const uint64_t memSize;

 /**
  * @brief The number of updates to do before creating an exit event.

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/52903
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I45d992b166a0dee2322c03e40beef1eee73e1855
Gerrit-Change-Number: 52903
Gerrit-PatchSet: 1
Gerrit-Owner: Mahyar Samani 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: misc: Adding multi-channel memory to components library

2021-10-29 Thread Mahyar Samani (Gerrit) via gem5-dev

Mahyar Samani has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/51287 )


Change subject: misc: Adding multi-channel memory to components library
..

misc: Adding multi-channel memory to components library

This change adds source code for multi-channel memory in the
components library.

Change-Id: I52b5462939d4d2d1657c85394bd83afdb509a0b0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51287
Reviewed-by: Bobby R. Bruce 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M src/python/gem5/components/boards/simple_board.py
M src/python/gem5/components/boards/test_board.py
A src/python/gem5/components/memory/multi_channel.py
M src/python/SConscript
M src/python/gem5/components/boards/x86_board.py
M src/python/gem5/components/boards/abstract_board.py
6 files changed, 194 insertions(+), 14 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/python/SConscript b/src/python/SConscript
index 41c91e7..e750829 100644
--- a/src/python/SConscript
+++ b/src/python/SConscript
@@ -115,6 +115,7 @@
 PySource('gem5.components.memory', 'gem5/components/memory/dramsim_3.py')
  
PySource('gem5.components.memory', 'gem5/components/memory/single_channel.py')

 PySource('gem5.components.memory', 'gem5/components/memory/simple.py')
+PySource('gem5.components.memory', 'gem5/components/memory/multi_channel.py')
 PySource('gem5.components.memory.dram_interfaces',
 'gem5/components/memory/dram_interfaces/__init__.py')
 PySource('gem5.components.memory.dram_interfaces',
diff --git a/src/python/gem5/components/boards/abstract_board.py  
b/src/python/gem5/components/boards/abstract_board.py

index c83668b..165b0d9 100644
--- a/src/python/gem5/components/boards/abstract_board.py
+++ b/src/python/gem5/components/boards/abstract_board.py
@@ -71,6 +71,8 @@
 self.memory = memory
 self.cache_hierarchy = cache_hierarchy

+self.setup_memory_ranges()
+
 def get_processor(self) -> "AbstractProcessor":
 """Get the processor connected to the board.

@@ -188,9 +190,9 @@
 """
 Set the memory ranges for this board.

-This is called by `connect_things`. It can query the board's memory
-to determine the size and the set the memory ranges on the memory  
if

-it needs to move the memory devices.
+This is called by at the end of the constructor. It can query the
+board's memory to determine the size and the set the memory ranges  
on

+the memory if it needs to move the memory devices.

 The simplest implementation just sets the board's memory range to  
be

 the size of memory and memory's memory range to be the same as the
diff --git a/src/python/gem5/components/boards/simple_board.py  
b/src/python/gem5/components/boards/simple_board.py

index b52bc7c..62c2d33 100644
--- a/src/python/gem5/components/boards/simple_board.py
+++ b/src/python/gem5/components/boards/simple_board.py
@@ -92,9 +92,6 @@

 @overrides(AbstractBoard)
 def connect_things(self) -> None:
-# Before incorporating the memory, set up the memory ranges
-self.setup_memory_ranges()
-
 # Incorporate the cache hierarchy for the motherboard.
 self.get_cache_hierarchy().incorporate_cache(self)

diff --git a/src/python/gem5/components/boards/test_board.py  
b/src/python/gem5/components/boards/test_board.py

index 2b80f9d..ea8efa8 100644
--- a/src/python/gem5/components/boards/test_board.py
+++ b/src/python/gem5/components/boards/test_board.py
@@ -72,14 +72,12 @@
 self.system_port = port

 def connect_things(self) -> None:
-self.setup_memory_ranges()
-
-self.get_cache_hierarchy().incorporate_cache(self)
-
 self.get_processor().incorporate_processor(self)

 self.get_memory().incorporate_memory(self)

+self.get_cache_hierarchy().incorporate_cache(self)
+
 def get_clock_domain(self) -> ClockDomain:
 return self.clk_domain

diff --git a/src/python/gem5/components/boards/x86_board.py  
b/src/python/gem5/components/boards/x86_board.py

index e766c3e..49bf789 100644
--- a/src/python/gem5/components/boards/x86_board.py
+++ b/src/python/gem5/components/boards/x86_board.py
@@ -253,10 +253,6 @@
 # This board is a bit particular about the order that things are
 # connected together.

-# Before incorporating the memory or creating the I/O devices  
figure

-# out the memory ranges.
-self.setup_memory_ranges()
-
 # Set up all of the I/O before we incorporate anything else.
 self._setup_io_devices()

diff --git a/src/python/gem5/components/memory/multi_channel.py  
b/src/python/gem5/components/memory/multi_channel.py

new file mode 100644
index 000..7d4baf1
--- /dev/null
+++

[gem5-dev] Change in gem5/gem5[develop]: misc: Updating AbstractGeneratorCore

2021-10-28 Thread Mahyar Samani (Gerrit) via gem5-dev

Mahyar Samani has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/51610 )


Change subject: misc: Updating AbstractGeneratorCore
..

misc: Updating AbstractGeneratorCore

This change updates AbstractGeneratorCore so that it uses a
PortTerminator instead of a dummy PyTrafficGen. This PortTerminator
will be used to connect to icache, and walker ports.

Change-Id: Ic744003c3e633592449ec7d209e4fbb5242f11fa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51610
Reviewed-by: Bobby R. Bruce 
Reviewed-by: Jason Lowe-Power 
Maintainer: Bobby R. Bruce 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/python/gem5/components/processors/abstract_generator_core.py
1 file changed, 27 insertions(+), 7 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve; Looks  
good to me, approved

  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git  
a/src/python/gem5/components/processors/abstract_generator_core.py  
b/src/python/gem5/components/processors/abstract_generator_core.py

index 48049d8..8bde5a5 100644
--- a/src/python/gem5/components/processors/abstract_generator_core.py
+++ b/src/python/gem5/components/processors/abstract_generator_core.py
@@ -25,7 +25,7 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.


-from m5.objects import Port, PyTrafficGen
+from m5.objects import Port, PortTerminator
 from ...utils.override import overrides

 from .cpu_types import CPUTypes
@@ -52,24 +52,25 @@
 # TODO: Remove the CPU Type parameter. This not needed.
 # Jira issue here: https://gem5.atlassian.net/browse/GEM5-1031
 super(AbstractGeneratorCore, self).__init__(CPUTypes.TIMING)
-self.dummy_generator = PyTrafficGen()
+self.port_end = PortTerminator()

 @overrides(AbstractCore)
 def connect_icache(self, port: Port) -> None:
 """
 Generator cores only have one request port which we will connect to
-the data cache not the icache. Just connect the icache to the dummy
-generator here.
+the data cache not the icache. Just connect the icache to the
+PortTerminator here.
 """
-self.dummy_generator.port = port
+self.port_end.req_ports = port

 @overrides(AbstractCore)
 def connect_walker_ports(self, port1: Port, port2: Port) -> None:
 """
 Since generator cores are not used in full system mode, no need to
-connect them to walker ports. Just pass here.
+connect them to walker ports. connect them to PortTerminator here.
 """
-pass
+self.port_end.req_ports = port1
+self.port_end.req_ports = port2

 @overrides(AbstractCore)
 def set_workload(self, process: "Process") -> None:

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/51610
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic744003c3e633592449ec7d209e4fbb5242f11fa
Gerrit-Change-Number: 51610
Gerrit-PatchSet: 6
Gerrit-Owner: Mahyar Samani 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Mahyar Samani 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: misc: Adding GUPSGen to components library.

2021-10-28 Thread Mahyar Samani (Gerrit) via gem5-dev

Mahyar Samani has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/51613 )


Change subject: misc: Adding GUPSGen to components library.
..

misc: Adding GUPSGen to components library.

This change adds GUPSGenCore, GUPSGen, GUPSGenEP, and GUPSGenPAR.
GUPSGenCore inherits from AbstractGeneratorCore. It is used for
implementing GUPSGen, GUPSGenEP, and GUPSGenPAR which inherit from
AbstractProcessor. GUPSGen does not implement a multi-core
generator as there are two ways to implement GUPS in parallel.
GUPSGenEP implement GUPS in it Embarrassingly Parallel variant
where multiple instances of GUPS update separate partitions of the
memory. GUPSGenPAR impelements GUPS in its Parallel variant where
multiple generators acccess the same partition of the memory in
parallel.

Change-Id: I57fb327a1ddefb6735ee59a0d7b4609e50af3517
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51613
Reviewed-by: Bobby R. Bruce 
Reviewed-by: Jason Lowe-Power 
Tested-by: kokoro 
Maintainer: Jason Lowe-Power 
---
A src/python/gem5/components/processors/gups_generator_core.py
A src/python/gem5/components/processors/gups_generator_par.py
M src/python/SConscript
A src/python/gem5/components/processors/gups_generator.py
A src/python/gem5/components/processors/gups_generator_ep.py
5 files changed, 357 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve; Looks  
good to me, approved

  Bobby R. Bruce: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/python/SConscript b/src/python/SConscript
index b4aaae0..41c91e7 100644
--- a/src/python/SConscript
+++ b/src/python/SConscript
@@ -150,6 +150,14 @@
 PySource('gem5.components.processors',
 'gem5/components/processors/cpu_types.py')
 PySource('gem5.components.processors',
+'gem5/components/processors/gups_generator_core.py')
+PySource('gem5.components.processors',
+'gem5/components/processors/gups_generator.py')
+PySource('gem5.components.processors',
+'gem5/components/processors/gups_generator_ep.py')
+PySource('gem5.components.processors',
+'gem5/components/processors/gups_generator_par.py')
+PySource('gem5.components.processors',
 'gem5/components/processors/linear_generator_core.py')
 PySource('gem5.components.processors',
 'gem5/components/processors/linear_generator.py')
diff --git a/src/python/gem5/components/processors/gups_generator.py  
b/src/python/gem5/components/processors/gups_generator.py

new file mode 100644
index 000..11b2e71
--- /dev/null
+++ b/src/python/gem5/components/processors/gups_generator.py
@@ -0,0 +1,78 @@
+# Copyright (c) 2021 The Regents of the University of California
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+
+from ...utils.override import overrides
+from m5.objects import Addr
+
+from ..boards.mem_mode import MemMode
+
+from .gups_generator_core import GUPSGeneratorCore
+
+from .abstract_processor import AbstractProcessor
+from ..boards.abstract_board import AbstractBoard
+
+
+class GUPSGenerator(AbstractProcessor):
+def __init__(
+self,
+start_addr: Addr,
+mem_size: str,
+update_limit: int = 0,
+):
+"""The GUPSGenerator class
+This class defines the interface for a single core GUPSGenerator,  
this
+generator could be used in place of a processor. For multicore  
versions
+of this generator look at GUPSGeneraorEP (EP stands

[gem5-dev] Change in gem5/gem5[develop]: mem: Adding PortTerminator

2021-10-28 Thread Mahyar Samani (Gerrit) via gem5-dev

Mahyar Samani has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/51609 )


 (

4 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: mem: Adding PortTerminator
..

mem: Adding PortTerminator

This change adds the source code for the PortTerminator SimObject.
It could be used to connect request/response ports in the system
that can not be connected to any other ports. This will prevent
errors caused by orphan ports in the system. As an example if
you have set up a cache hierarchy and do not want to test its
performance in full system mode and want to use PyTrafficGen
instead, your system will end up with an icache or walker ports
that are not connected to anything. In this case, you can use a
PortTerminator to connect the orphan ports in your system.

Change-Id: I5e19cdd3ce064638ffabf29d29225eda77ffc146
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51609
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
A src/mem/PortTerminator.py
A src/mem/port_terminator.cc
A src/mem/port_terminator.hh
M src/mem/SConscript
4 files changed, 239 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/mem/PortTerminator.py b/src/mem/PortTerminator.py
new file mode 100644
index 000..761f5ed
--- /dev/null
+++ b/src/mem/PortTerminator.py
@@ -0,0 +1,39 @@
+# Copyright (c) 2021 The Regents of the University of California.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+from m5.params import *
+from m5.SimObject import SimObject
+
+class PortTerminator(SimObject):
+type = 'PortTerminator'
+cxx_header = "mem/port_terminator.hh"
+cxx_class = 'gem5::PortTerminator'
+
+req_ports = VectorRequestPort("Vector port for connecting terminating "
+"response ports.")
+resp_ports = VectorResponsePort("Vector port for terminating "
+"request ports.")
\ No newline at end of file
diff --git a/src/mem/SConscript b/src/mem/SConscript
index 5338b79..ddf6fee 100644
--- a/src/mem/SConscript
+++ b/src/mem/SConscript
@@ -58,6 +58,7 @@
 SimObject('HMCController.py')
 SimObject('SerialLink.py')
 SimObject('MemDelay.py')
+SimObject('PortTerminator.py')

 Source('abstract_mem.cc')
 Source('addr_mapper.cc')
@@ -85,6 +86,7 @@
 Source('htm.cc')
 Source('serial_link.cc')
 Source('mem_delay.cc')
+Source('port_terminator.cc')

 GTest('translation_gen.test', 'translation_gen.test.cc')

diff --git a/src/mem/port_terminator.cc b/src/mem/port_terminator.cc
new file mode 100644
index 000..57263b4
--- /dev/null
+++ b/src/mem/port_terminator.cc
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2021 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the

[gem5-dev] Change in gem5/gem5[develop]: misc: Adding SingleChannelSimpleMemory.

2021-10-28 Thread Mahyar Samani (Gerrit) via gem5-dev

Mahyar Samani has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/51611 )


Change subject: misc: Adding SingleChannelSimpleMemory.
..

misc: Adding SingleChannelSimpleMemory.

This change adds SimpleSingleChannelMemory to the components
library.

Change-Id: Id633d207842106a7da8532d3ac64adf022d30d7c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51611
Reviewed-by: Jason Lowe-Power 
Tested-by: kokoro 
Maintainer: Bobby R. Bruce 
---
M src/python/SConscript
A src/python/gem5/components/memory/simple.py
2 files changed, 101 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Bobby R. Bruce: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/python/SConscript b/src/python/SConscript
index f8a9136..b4aaae0 100644
--- a/src/python/SConscript
+++ b/src/python/SConscript
@@ -114,6 +114,7 @@
  
PySource('gem5.components.memory', 'gem5/components/memory/abstract_memory_system.py')

 PySource('gem5.components.memory', 'gem5/components/memory/dramsim_3.py')
  
PySource('gem5.components.memory', 'gem5/components/memory/single_channel.py')

+PySource('gem5.components.memory', 'gem5/components/memory/simple.py')
 PySource('gem5.components.memory.dram_interfaces',
 'gem5/components/memory/dram_interfaces/__init__.py')
 PySource('gem5.components.memory.dram_interfaces',
diff --git a/src/python/gem5/components/memory/simple.py  
b/src/python/gem5/components/memory/simple.py

new file mode 100644
index 000..80b1238
--- /dev/null
+++ b/src/python/gem5/components/memory/simple.py
@@ -0,0 +1,84 @@
+# Copyright (c) 2021 The Regents of the University of California
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+"""Simple memory controllers
+"""
+
+from ...utils.override import overrides
+from m5.util.convert import toMemorySize
+from typing import List, Sequence, Tuple
+from ..boards.abstract_board import AbstractBoard
+from .abstract_memory_system import AbstractMemorySystem
+from m5.objects import AddrRange, MemCtrl, Port, SimpleMemory
+
+class SingleChannelSimpleMemory(AbstractMemorySystem):
+"""A class to implement single channel memory system using SimpleMemory
+
+This class takes latency, latency variation, and bandwidth and  
configures
+a memory with those values. It could be used for studies that do not  
target

+memory subsystem design.
+"""
+
+def __init__(
+self, latency: str, latency_var: str, bandwidth: str, size: str
+):
+"""
+:param latency: The average of request to response latency.
+:param latency_var: The variance of request to response latency.
+:param bandwidth: Combined read and write bandwidth.
+:param size: Size of the memory.
+"""
+super().__init__()
+
+self.module = SimpleMemory(
+latency=latency, latency_var=latency_var, bandwidth=bandwidth
+)
+self._size = toMemorySize(size)
+
+@overrides(AbstractMemorySystem)
+def incorporate_memory(self, board: AbstractBoard) -> None:
+pass
+
+@overrides(AbstractMemorySystem)
+def get_mem_ports(self) -> Sequence[Tuple[AddrRange, Port]]:
+return [(self.module.range, self.module.port)]
+
+@overrides(AbstractMemorySystem)
+def get_memory_controllers(self) -> List[MemCtrl]:
+return [self.module]
+
+@overrides(AbstractMemorySystem)
+def get_size(self) -> int:
+

[gem5-dev] Change in gem5/gem5[develop]: cpu: Updating stats for GUPSGen

2021-10-14 Thread Mahyar Samani (Gerrit) via gem5-dev

Mahyar Samani has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/51608 )


Change subject: cpu: Updating stats for GUPSGen
..

cpu: Updating stats for GUPSGen

This changes deletes the deprecated stat types for GUPSGen and
replaces them with the namespaces.

Change-Id: I3a6f1bd65c0b5ebad613b8769553942d9b0d8e0c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51608
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/cpu/testers/traffic_gen/gups_gen.cc
1 file changed, 31 insertions(+), 12 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/cpu/testers/traffic_gen/gups_gen.cc  
b/src/cpu/testers/traffic_gen/gups_gen.cc

index 837b234..615d4b0 100644
--- a/src/cpu/testers/traffic_gen/gups_gen.cc
+++ b/src/cpu/testers/traffic_gen/gups_gen.cc
@@ -326,29 +326,32 @@

 GUPSGen::GUPSGenStat::GUPSGenStat(GUPSGen* parent):
 Stats::Group(parent),
-ADD_STAT(totalUpdates, UNIT_COUNT,
+ADD_STAT(totalUpdates, statistics::units::Count::get(),
 "Total number of updates the generator made in the memory"),
-ADD_STAT(GUPS, UNIT_RATE(Stats::Units::Count, Stats::Units::Second),
+ADD_STAT(GUPS, statistics::units::Rate::get(),
 "Rate of billion updates per second"),
-ADD_STAT(totalReads, UNIT_COUNT,
+ADD_STAT(totalReads, statistics::units::Count::get(),
 "Total number of read requests"),
-ADD_STAT(totalBytesRead, UNIT_BYTE,
+ADD_STAT(totalBytesRead, statistics::units::Byte::get(),
 "Total number of bytes read"),
-ADD_STAT(avgReadBW, UNIT_RATE(Stats::Units::Byte,  
Stats::Units::Second),

+ADD_STAT(avgReadBW, statistics::units::Rate::get(),
 "Average read bandwidth received from memory"),
-ADD_STAT(totalReadLat, UNIT_TICK,
+ADD_STAT(totalReadLat, statistics::units::Tick::get(),
 "Total latency of read requests."),
-ADD_STAT(avgReadLat, UNIT_TICK,
+ADD_STAT(avgReadLat, statistics::units::Tick::get(),
 "Average latency for read requests"),
-ADD_STAT(totalWrites, UNIT_COUNT,
+ADD_STAT(totalWrites, statistics::units::Count::get(),
 "Total number of write requests"),
-ADD_STAT(totalBytesWritten, UNIT_BYTE,
+ADD_STAT(totalBytesWritten, statistics::units::Byte::get(),
 "Total number of bytes written"),
-ADD_STAT(avgWriteBW, UNIT_RATE(Stats::Units::Byte,  
Stats::Units::Second),

+ADD_STAT(avgWriteBW, statistics::units::Rate::get(),
 "Average write bandwidth received from memory"),
-ADD_STAT(totalWriteLat, UNIT_TICK,
+ADD_STAT(totalWriteLat, statistics::units::Tick::get(),
 "Total latency of write requests."),
-ADD_STAT(avgWriteLat, UNIT_TICK,
+ADD_STAT(avgWriteLat, statistics::units::Tick::get(),
 "Average latency for write requests")
 {}


--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/51608
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3a6f1bd65c0b5ebad613b8769553942d9b0d8e0c
Gerrit-Change-Number: 51608
Gerrit-PatchSet: 2
Gerrit-Owner: Mahyar Samani 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Mahyar Samani 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: misc: Adding documentation on how to setup KVM.

2021-10-13 Thread Mahyar Samani (Gerrit) via gem5-dev

Mahyar Samani has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/51615 )



Change subject: misc: Adding documentation on how to setup KVM.
..

misc: Adding documentation on how to setup KVM.

This change adds doumentation on how to setup KVM.

Change-Id: Ie3bb47b0f9c00e040ba9425018b5659a421fb1a0
---
A INSTALLING-KVM.md
1 file changed, 66 insertions(+), 0 deletions(-)



diff --git a/INSTALLING-KVM.md b/INSTALLING-KVM.md
new file mode 100644
index 000..3520e19
--- /dev/null
+++ b/INSTALLING-KVM.md
@@ -0,0 +1,55 @@
+## Installing KVM
+
+In order to be able to use gem5's KVMCPU or use packer, you need to have  
KVM

+and QEMU installed on your host system. First, you need a processor that
+supports hardware virtualization. In order to see if your processor  
supports

+hardware virtualization, run the command below:
+
+```console
+$ egrep -c '(vmx|svm)' /proc/cpuinfo
+```
+
+If it returns 0, it means that your processor does not support hardware
+virtualization.
+
+If it returns 1 or more, it does. Note: You still have to make sure it is
+enabled in your bios.
+
+I tried this with my GigaByte Aorus X570 Elite motherboard (AMD AM4  
socket) and

+this is how I enabled hardware virtualization for my motherboard.
+
+```console
+Tweaker->Advanced CPU Settings->SVM Mode->Enabled
+```
+
+Note: It is also recommended that you use a 64-bit kernel on your host  
machine.
+The limitations of using a 32-bit kernel on your host machine are as  
follows:

+
+* You can only allocate 2GB of memory for your VMs
+* You can only create 32-bit VMs.
+
+After, in order to install kvm run the following command on terminal  
(tested

+with Ubuntu 20.04 but should work for 18.10 or later):
+
+```console
+$ sudo apt-get install qemu-kvm libvirt-daemon-system libvirt-clients  
bridge-utils

+```
+
+Note: You might also want to install virt-viewer, for viewing instances.
+
+Now add your user to the kvm and libvirt (libvirtd depending on the  
version of

+your Ubuntu). Run the two commands below to do this (it's been tested with
+Ubuntu 20.04 but should work for 18.04 or higher).
+
+```console
+$ sudo adduser `id -un` libvirt
+$ sudo adduser `id -un` kvm
+```
+
+After this, you need to relogin to your account. If you are using SSH,
+disconnect all your session and relogin again. Now if you run the command  
below

+you should see kvm and libvirt (libvirtd).
+
+```console
+$ groups
+```
\ No newline at end of file

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/51615
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie3bb47b0f9c00e040ba9425018b5659a421fb1a0
Gerrit-Change-Number: 51615
Gerrit-PatchSet: 1
Gerrit-Owner: Mahyar Samani 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: misc: Adding GUPSGen to components library.

2021-10-13 Thread Mahyar Samani (Gerrit) via gem5-dev

Mahyar Samani has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/51613 )



Change subject: misc: Adding GUPSGen to components library.
..

misc: Adding GUPSGen to components library.

This change adds GUPSGenCore, GUPSGen, GUPSGenEP, and GUPSGenPAR.
GUPSGenCore inherits from AbstractGeneratorCore. It is used for
implementing GUPSGen, GUPSGenEP, and GUPSGenPAR which inherit from
AbstractProcessor. GUPSGen does not implement a multi-core
generator as there are two ways to implement GUPS in parallel.
GUPSGenEP implement GUPS in it Embarrassingly Parallel variant
where multiple instances of GUPS update separate partitions of the
memory. GUPSGenPAR impelements GUPS in its Parallel variant where
multiple generators acccess the same partition of the memory in
parallel.

Change-Id: I57fb327a1ddefb6735ee59a0d7b4609e50af3517
---
A src/python/gem5/components/processors/gups_generator_core.py
A src/python/gem5/components/processors/gups_generator_par.py
M src/python/SConscript
A src/python/gem5/components/processors/gups_generator.py
A src/python/gem5/components/processors/gups_generator_ep.py
5 files changed, 343 insertions(+), 0 deletions(-)



diff --git a/src/python/SConscript b/src/python/SConscript
index f8a9136..2a51142 100644
--- a/src/python/SConscript
+++ b/src/python/SConscript
@@ -149,6 +149,14 @@
 PySource('gem5.components.processors',
 'gem5/components/processors/cpu_types.py')
 PySource('gem5.components.processors',
+'gem5/components/processors/gups_generator_core.py')
+PySource('gem5.components.processors',
+'gem5/components/processors/gups_generator.py')
+PySource('gem5.components.processors',
+'gem5/components/processors/gups_generator_ep.py')
+PySource('gem5.components.processors',
+'gem5/components/processors/gups_generator_par.py')
+PySource('gem5.components.processors',
 'gem5/components/processors/linear_generator_core.py')
 PySource('gem5.components.processors',
 'gem5/components/processors/linear_generator.py')
diff --git a/src/python/gem5/components/processors/gups_generator.py  
b/src/python/gem5/components/processors/gups_generator.py

new file mode 100644
index 000..08ff3fe
--- /dev/null
+++ b/src/python/gem5/components/processors/gups_generator.py
@@ -0,0 +1,75 @@
+# Copyright (c) 2021 The Regents of the University of California
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+
+from ...utils.override import overrides
+from m5.objects import Addr
+
+from ..boards.mem_mode import MemMode
+
+from .gups_generator_core import GUPSGeneratorCore
+
+from .abstract_processor import AbstractProcessor
+from ..boards.abstract_board import AbstractBoard
+
+
+class GUPSGenerator(AbstractProcessor):
+def __init__(
+self,
+start_addr: Addr = 0,
+mem_size: str = "32MB",
+update_limit: int = 0,
+):
+"""The GUPSGenerator class
+This class defines the interface for a single core GUPSGenerator,  
this
+generator could be used in place of a processor. For multicore  
versions
+of this generator look at GUPSGeneraorEP (EP stands for  
embarrassingly

+parallel) and GUPSGeneratorPAR (PAR stands for parallel). The two
+variants are specified by the HPCC benchmark.
+
+:param start_addr: The start address for allocating the update  
table.
+:param mem_size: The size of memory to allocate for the update  
table.

+Should be a

[gem5-dev] Change in gem5/gem5[develop]: misc: Adding SimpleSingleChannelMemory

2021-10-13 Thread Mahyar Samani (Gerrit) via gem5-dev

Mahyar Samani has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/51611 )



Change subject: misc: Adding SimpleSingleChannelMemory
..

misc: Adding SimpleSingleChannelMemory

This change adds SimpleSingleChannelMemory to the components
library.

Change-Id: Id633d207842106a7da8532d3ac64adf022d30d7c
---
M src/python/gem5/components/memory/single_channel.py
1 file changed, 54 insertions(+), 1 deletion(-)



diff --git a/src/python/gem5/components/memory/single_channel.py  
b/src/python/gem5/components/memory/single_channel.py

index 11a0b15..1ecdeda 100644
--- a/src/python/gem5/components/memory/single_channel.py
+++ b/src/python/gem5/components/memory/single_channel.py
@@ -31,7 +31,7 @@
 from .abstract_memory_system import AbstractMemorySystem
 from ...utils.override import overrides

-from m5.objects import AddrRange, DRAMInterface, MemCtrl, Port
+from m5.objects import AddrRange, DRAMInterface, MemCtrl, Port,  
SimpleMemory

 from m5.util.convert import toMemorySize

 from typing import List, Sequence, Tuple, Type, Optional
@@ -99,6 +99,47 @@
 self.mem_ctrl.dram.range = ranges[0]


+class SimpleSingleChannelMemory(AbstractMemorySystem):
+def __init__(
+self,
+latency: str,
+latency_var: str,
+bandwidth: str,
+size: Optional[str] = "1GB",
+):
+super().__init__()
+
+self.module = SimpleMemory(
+latency=latency, latency_var=latency_var, bandwidth=bandwidth
+)
+self._size = toMemorySize(size)
+
+@overrides(AbstractMemorySystem)
+def incorporate_memory(self, board: AbstractBoard) -> None:
+pass
+
+@overrides(AbstractMemorySystem)
+def get_mem_ports(self) -> Sequence[Tuple[AddrRange, Port]]:
+return [(self.module.range, self.module.port)]
+
+@overrides(AbstractMemorySystem)
+def get_memory_controllers(self) -> List[MemCtrl]:
+return [self.module]
+
+@overrides(AbstractMemorySystem)
+def get_size(self) -> int:
+return self._size
+
+@overrides(AbstractMemorySystem)
+def set_memory_range(self, ranges: List[AddrRange]) -> None:
+if len(ranges) != 1 or ranges[0].size() != self._size:
+print(ranges[0].size())
+raise Exception(
+"Simple single channel memory controller requires a  
single "

+"range which m atches the memory's size."
+)
+self.module.range = ranges[0]
+
 from .dram_interfaces.ddr3 import DDR3_1600_8x8, DDR3_2133_8x8
 from .dram_interfaces.ddr4 import DDR4_2400_8x8
 from .dram_interfaces.lpddr3 import LPDDR3_1600_1x32

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/51611
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id633d207842106a7da8532d3ac64adf022d30d7c
Gerrit-Change-Number: 51611
Gerrit-PatchSet: 1
Gerrit-Owner: Mahyar Samani 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: mem: Adding PortTerminator

2021-10-13 Thread Mahyar Samani (Gerrit) via gem5-dev

Mahyar Samani has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/51609 )



Change subject: mem: Adding PortTerminator
..

mem: Adding PortTerminator

This change adds the source code for the PortTerminator SimObject.
It could be used to connect request/response ports in the system
that can not be connected to any other ports. This will prevent
errors caused by orphan ports in the system.

Change-Id: I5e19cdd3ce064638ffabf29d29225eda77ffc146
---
A src/mem/PortTerminator.py
A src/mem/port_terminator.cc
A src/mem/port_terminator.hh
M src/mem/SConscript
4 files changed, 240 insertions(+), 0 deletions(-)



diff --git a/src/mem/PortTerminator.py b/src/mem/PortTerminator.py
new file mode 100644
index 000..d0b7169
--- /dev/null
+++ b/src/mem/PortTerminator.py
@@ -0,0 +1,53 @@
+# Copyright (c) 2012-2021 Arm Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Copyright (c) 2013 Amin Farmahini-Farahani
+# Copyright (c) 2015 University of Kaiserslautern
+# Copyright (c) 2015 The University of Bologna
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from m5.params import *
+from m5.SimObject import SimObject
+
+class PortTerminator(SimObject):
+type = 'PortTerminator'
+abstract = False
+cxx_header = "mem/port_terminator.hh"
+cxx_class = 'gem5::PortTerminator'
+
+req_ports = VectorRequestPort("Vector port for connecting terminating "
+"response ports.")
+resp_ports = VectorResponsePort("Vector port for terminating "
+"request ports.")
\ No newline at end of file
diff --git a/src/mem/SConscript b/src/mem/SConscript
index 5d3c5e6..e200982 100644
--- a/src/mem/SConscript
+++ b/src/mem/SConscript
@@ -58,6 +58,7 @@
 SimObject('HMCController.py')
 SimObject('SerialLink.py')
 SimObject('MemDelay.py')
+SimObject('PortTerminator.py')

 Source('abstract_mem.cc')
 Source('addr_mapper.cc')
@@ -85,6 +86,7 @@
 Source('htm.cc')
 Source('serial_link.cc')
 Source('mem_delay.cc')
+Source('port_terminator.cc')

 if env['TARGET_ISA'] != 'null':
 Source('translating_port_proxy.cc')
diff --git a/src/mem/port_terminator.cc b/src/mem/port_terminator.cc
new file mode 100644
index 000..cd56c53
--- /dev/null
+++ b/src/mem/port_terminator.cc
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2011-2015, 2018-2020 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+

[gem5-dev] Change in gem5/gem5[develop]: misc: Updating AbstractGeneratorCore

2021-10-13 Thread Mahyar Samani (Gerrit) via gem5-dev

Mahyar Samani has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/51610 )



Change subject: misc: Updating AbstractGeneratorCore
..

misc: Updating AbstractGeneratorCore

This change updates AbstractGeneratorCore so that it uses a
PortTerminator instead of a dummy PyTrafficGen. This PortTerminator
will be used to connect to icache, and walker ports.

Change-Id: Ic744003c3e633592449ec7d209e4fbb5242f11fa
---
M src/python/gem5/components/processors/abstract_generator_core.py
1 file changed, 21 insertions(+), 7 deletions(-)



diff --git  
a/src/python/gem5/components/processors/abstract_generator_core.py  
b/src/python/gem5/components/processors/abstract_generator_core.py

index 48049d8..8bde5a5 100644
--- a/src/python/gem5/components/processors/abstract_generator_core.py
+++ b/src/python/gem5/components/processors/abstract_generator_core.py
@@ -25,7 +25,7 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.


-from m5.objects import Port, PyTrafficGen
+from m5.objects import Port, PortTerminator
 from ...utils.override import overrides

 from .cpu_types import CPUTypes
@@ -52,24 +52,25 @@
 # TODO: Remove the CPU Type parameter. This not needed.
 # Jira issue here: https://gem5.atlassian.net/browse/GEM5-1031
 super(AbstractGeneratorCore, self).__init__(CPUTypes.TIMING)
-self.dummy_generator = PyTrafficGen()
+self.port_end = PortTerminator()

 @overrides(AbstractCore)
 def connect_icache(self, port: Port) -> None:
 """
 Generator cores only have one request port which we will connect to
-the data cache not the icache. Just connect the icache to the dummy
-generator here.
+the data cache not the icache. Just connect the icache to the
+PortTerminator here.
 """
-self.dummy_generator.port = port
+self.port_end.req_ports = port

 @overrides(AbstractCore)
 def connect_walker_ports(self, port1: Port, port2: Port) -> None:
 """
 Since generator cores are not used in full system mode, no need to
-connect them to walker ports. Just pass here.
+connect them to walker ports. connect them to PortTerminator here.
 """
-pass
+self.port_end.req_ports = port1
+self.port_end.req_ports = port2

 @overrides(AbstractCore)
 def set_workload(self, process: "Process") -> None:

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/51610
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic744003c3e633592449ec7d209e4fbb5242f11fa
Gerrit-Change-Number: 51610
Gerrit-PatchSet: 1
Gerrit-Owner: Mahyar Samani 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: cpu: Updating stats for GUPSGen

2021-10-13 Thread Mahyar Samani (Gerrit) via gem5-dev

Mahyar Samani has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/51608 )



Change subject: cpu: Updating stats for GUPSGen
..

cpu: Updating stats for GUPSGen

This changes deletes the deprecated stat types for GUPSGen and
replaces them with the namespaces.

Change-Id: I3a6f1bd65c0b5ebad613b8769553942d9b0d8e0c
---
M src/cpu/testers/traffic_gen/gups_gen.cc
1 file changed, 27 insertions(+), 12 deletions(-)



diff --git a/src/cpu/testers/traffic_gen/gups_gen.cc  
b/src/cpu/testers/traffic_gen/gups_gen.cc

index 837b234..615d4b0 100644
--- a/src/cpu/testers/traffic_gen/gups_gen.cc
+++ b/src/cpu/testers/traffic_gen/gups_gen.cc
@@ -326,29 +326,32 @@

 GUPSGen::GUPSGenStat::GUPSGenStat(GUPSGen* parent):
 Stats::Group(parent),
-ADD_STAT(totalUpdates, UNIT_COUNT,
+ADD_STAT(totalUpdates, statistics::units::Count::get(),
 "Total number of updates the generator made in the memory"),
-ADD_STAT(GUPS, UNIT_RATE(Stats::Units::Count, Stats::Units::Second),
+ADD_STAT(GUPS, statistics::units::Rate::get(),
 "Rate of billion updates per second"),
-ADD_STAT(totalReads, UNIT_COUNT,
+ADD_STAT(totalReads, statistics::units::Count::get(),
 "Total number of read requests"),
-ADD_STAT(totalBytesRead, UNIT_BYTE,
+ADD_STAT(totalBytesRead, statistics::units::Byte::get(),
 "Total number of bytes read"),
-ADD_STAT(avgReadBW, UNIT_RATE(Stats::Units::Byte,  
Stats::Units::Second),

+ADD_STAT(avgReadBW, statistics::units::Rate::get(),
 "Average read bandwidth received from memory"),
-ADD_STAT(totalReadLat, UNIT_TICK,
+ADD_STAT(totalReadLat, statistics::units::Tick::get(),
 "Total latency of read requests."),
-ADD_STAT(avgReadLat, UNIT_TICK,
+ADD_STAT(avgReadLat, statistics::units::Tick::get(),
 "Average latency for read requests"),
-ADD_STAT(totalWrites, UNIT_COUNT,
+ADD_STAT(totalWrites, statistics::units::Count::get(),
 "Total number of write requests"),
-ADD_STAT(totalBytesWritten, UNIT_BYTE,
+ADD_STAT(totalBytesWritten, statistics::units::Byte::get(),
 "Total number of bytes written"),
-ADD_STAT(avgWriteBW, UNIT_RATE(Stats::Units::Byte,  
Stats::Units::Second),

+ADD_STAT(avgWriteBW, statistics::units::Rate::get(),
 "Average write bandwidth received from memory"),
-ADD_STAT(totalWriteLat, UNIT_TICK,
+ADD_STAT(totalWriteLat, statistics::units::Tick::get(),
 "Total latency of write requests."),
-ADD_STAT(avgWriteLat, UNIT_TICK,
+ADD_STAT(avgWriteLat, statistics::units::Tick::get(),
 "Average latency for write requests")
 {}


--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/51608
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3a6f1bd65c0b5ebad613b8769553942d9b0d8e0c
Gerrit-Change-Number: 51608
Gerrit-PatchSet: 1
Gerrit-Owner: Mahyar Samani 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: cpu: Adding GUPSGen ClockedObject.

2021-10-13 Thread Mahyar Samani (Gerrit) via gem5-dev

Mahyar Samani has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/47439 )


Change subject: cpu: Adding GUPSGen ClockedObject.
..

cpu: Adding GUPSGen ClockedObject.

This patch adds the code base to implement GUPSGen which is a
ClockedObject that creates read/write requests to the memory
to update elements in an array. The choosing of elements in
the array follow a random distribution. Each element is read
from and return as GUPSGen implements a key-value store program.
Specifications are found in HPCC website from RandomAccess
benchmark. link below.
https://icl.cs.utk.edu/projectsfiles/hpcc/RandomAccess/

Change-Id: I5c07f230bee317fff2cceec04d15d0218e8ede9a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47439
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Bobby R. Bruce 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
A src/cpu/testers/traffic_gen/GUPSGen.py
A src/cpu/testers/traffic_gen/gups_gen.cc
A src/cpu/testers/traffic_gen/gups_gen.hh
M src/cpu/testers/traffic_gen/SConscript
4 files changed, 795 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve; Looks  
good to me, approved

  Bobby R. Bruce: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/cpu/testers/traffic_gen/GUPSGen.py  
b/src/cpu/testers/traffic_gen/GUPSGen.py

new file mode 100644
index 000..dafc86d
--- /dev/null
+++ b/src/cpu/testers/traffic_gen/GUPSGen.py
@@ -0,0 +1,60 @@
+# Copyright (c) 2021 The Regents of the University of California.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+from m5.params import *
+from m5.proxy import *
+from m5.objects.ClockedObject import ClockedObject
+
+class GUPSGen(ClockedObject):
+"""
+This ClockedObject implements the RandomAccess benchmark specified by  
HPCC

+benchmarks in https://icl.utk.edu/projectsfiles/hpcc/RandomAccess.
+"""
+type = 'GUPSGen'
+cxx_header = "cpu/testers/traffic_gen/gups_gen.hh"
+cxx_class = "gem5::GUPSGen"
+
+system = Param.System(Parent.any, 'System this generator is a part of')
+
+port = RequestPort('Port that should be connected to other components')
+
+start_addr = Param.Addr(0, 'Start address for allocating update table,'
+' should be a multiple of block_size')
+
+mem_size = Param.MemorySize('Size for allocating update table, based  
on'

+' randomAccess benchmark specification, this'
+' should be equal to half of total system  
memory'

+' ,also should be a power of 2')
+
+update_limit = Param.Int(0, 'The number of updates to issue before the'
+' simulation is over')
+
+request_queue_size = Param.Int(1024, 'Maximum number of parallel'
+' outstanding requests')
+
+init_memory = Param.Bool(False, 'Whether or not to initialize the  
memory,'

+' it does not effect the performance')
diff --git a/src/cpu/testers/traffic_gen/SConscript  
b/src/cpu/testers/traffic_gen/SConscript

index 640d81a..a2670e7 100644
--- a/src/cpu/testers/traffic_gen/SConscript
+++ b/src/cpu/testers/traffic_gen/SConscript
@@ -43,6 +43,7 @@
 Source('dram_gen.cc')
 Source('dram_rot_gen.cc')
 Source('exit_gen.cc')
+Source('gups_gen.cc')
 Source('hybrid_gen.cc')
 Source('idle_gen.cc')
 Source('linear_gen.cc')
@@

[gem5-dev] Change in gem5/gem5[develop]: misc: Adding multi-channel memory to components library

2021-10-05 Thread Mahyar Samani (Gerrit) via gem5-dev

Mahyar Samani has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/51287 )



Change subject: misc: Adding multi-channel memory to components library
..

misc: Adding multi-channel memory to components library

This change adds source code for multi-channel memory in the
components library.

Change-Id: I52b5462939d4d2d1657c85394bd83afdb509a0b0
---
A src/python/gem5/components/memory/multi_channel.py
1 file changed, 115 insertions(+), 0 deletions(-)



diff --git a/src/python/gem5/components/memory/multi_channel.py  
b/src/python/gem5/components/memory/multi_channel.py

new file mode 100644
index 000..f5e3db5
--- /dev/null
+++ b/src/python/gem5/components/memory/multi_channel.py
@@ -0,0 +1,103 @@
+# Copyright (c) 2021 The Regents of the University of California
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from math import log
+from typing import Type
+from m5.util.convert import toMemorySize
+from abstract_memory_system import AbstractMemorySystem
+from m5.objects import AddrRange, DRAMInterface, MemCtrl
+
+class MultiChannelMemory(AbstractMemorySystem):
+def __init__(
+self,
+dram_interface_class: Type[DRAMInterface],
+num_channels: int,
+size: Optional[str] = None,
+addr_mapping: Optional[str] = None,
+interleaving_size: Optional[int] = None,
+) -> None:
+super().__init__()
+self._dram_class = dram_interface_class
+self._num_channels = num_channels
+
+if interleaving_size:
+self._intlv_size = interleaving_size
+else:
+self._intlv_size = 64
+
+if addr_mapping:
+self._addr_mapping = addr_mapping
+else:
+self._addr_mapping = self._dram_class.addr_mapping
+
+if size:
+self._size = toMemorySize(size)
+else:
+self._size = _get_dram_size(num_channels, self._dram_class)
+
+self.mem_range = AddrRange(size)
+
+self._dram = [
+self._dram_class(addr_mapping=self._addr_mapping)
+for _ in range(num_channels)
+]
+self.mem_ctrl = [
+MemCtrl(dram=self._dram[i]) for i in range(num_channels)
+]
+
+def _get_dram_size(num_channels: int, dram: DRAMInterface) -> int:
+return num_channels * (
+dram.device_size.value
+* dram.devices_per_rank.value
+* dram.ranks_per_channel.value
+)
+
+def _interleave_addresses(self):
+if self._addr_mapping == "RoRaBaChCo":
+rowbuffer_size = (
+self._dram_class.device_rowbuffer_size.value
+* self._dram_class.devices_per_rank.value
+)
+intlv_low_bit = log(rowbuffer_size, 2)
+elif self._addr_mapping in ["RoRaBaCoCh", "RoCoRaBaCh"]:
+intlv_low_bit = 0
+else:
+raise ValueError(
+"Only these address mappings are supported: "
+"RoRaBaChCo, RoRaBaCoCh, RoCoRaBaCh"
+)
+
+intlv_bits = log(self._intlv_size)
+
+for i in range(self._num_channels):
+self._dram[i].range = AddrRange(
+self.mem_range.start,
+size=self.mem_range.size(),
+intlvHighBit=intlv_low_bit + intlv_bits - 1,
+xorHighBit=20,
+intlvBits=intlv_bits,
+intlvMatch=i,
+)

--
To

[gem5-dev] Change in gem5/gem5[develop]: tests: Adding tests to evaluate memory modules.

2021-10-01 Thread Mahyar Samani (Gerrit) via gem5-dev

Mahyar Samani has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/50752 )


Change subject: tests: Adding tests to evaluate memory modules.
..

tests: Adding tests to evaluate memory modules.

This change adds a script to validate the statistics reported
by gem5. It also overrides has_dma_ports for TestBoard to allow
other cache hierarchies such as MESITwoLevel connect to this board.

Change-Id: Iae0e61c1763c099cf10924a08b3e4989dc31e220
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50752
Reviewed-by: Bobby R. Bruce 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M src/python/gem5/components/boards/test_board.py
M tests/gem5/traffic_gen/test_memory_traffic_gen.py
M tests/gem5/configs/simple_traffic_run.py
3 files changed, 231 insertions(+), 34 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/python/gem5/components/boards/test_board.py  
b/src/python/gem5/components/boards/test_board.py

index 4bcefb1..2b80f9d 100644
--- a/src/python/gem5/components/boards/test_board.py
+++ b/src/python/gem5/components/boards/test_board.py
@@ -128,3 +128,7 @@
 # memory.
 self.mem_ranges = [AddrRange(memory.get_size())]
 memory.set_memory_range(self.mem_ranges)
+
+@overrides(AbstractBoard)
+def has_dma_ports(self) -> bool:
+return False
diff --git a/tests/gem5/configs/simple_traffic_run.py  
b/tests/gem5/configs/simple_traffic_run.py

index 2541d90..f519335 100644
--- a/tests/gem5/configs/simple_traffic_run.py
+++ b/tests/gem5/configs/simple_traffic_run.py
@@ -25,22 +25,55 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 """
-This script creates a simple traffic generator. The simulator starts with a
-linear traffic generator, and ends with a random traffic generator. It is  
used

-for testing purposes.
+This scripts is used for checking the correctness of statistics reported
+by the gem5 simulator. It can excercise certain components in the memory
+subsystem. The reported values could be used to compare against a validated
+set of statistics.
 """

 import m5
-
-from m5.objects import Root
-
 import argparse
 import importlib

+from os.path import join
+from m5.objects import Root
+from m5.stats import gem5stats
 from gem5.components.boards.test_board import TestBoard
-from gem5.components.cachehierarchies.classic.no_cache import NoCache
-from gem5.components.memory.single_channel import *
-from gem5.components.processors.complex_generator import ComplexGenerator
+from gem5.components.processors.linear_generator import LinearGenerator
+from gem5.components.processors.random_generator import RandomGenerator
+
+
+generator_class_map = {
+"LinearGenerator": LinearGenerator,
+"RandomGenerator": RandomGenerator,
+}
+
+generator_initializers = dict(rate="20GB/s")
+
+
+def cache_factory(cache_class):
+if cache_class == "NoCache":
+from gem5.components.cachehierarchies.classic.no_cache import  
NoCache

+
+return NoCache()
+elif cache_class == "MESITwoLevel":
+from gem5.components.cachehierarchies.ruby\
+.mesi_two_level_cache_hierarchy import (
+MESITwoLevelCacheHierarchy,
+)
+
+return MESITwoLevelCacheHierarchy(
+l1i_size="32KiB",
+l1i_assoc="8",
+l1d_size="32KiB",
+l1d_assoc="8",
+l2_size="256KiB",
+l2_assoc="4",
+num_l2_banks=1,
+)
+else:
+raise ValueError(f"The cache class {cache_class} is not  
supported.")

+

 parser = argparse.ArgumentParser(
 description="A traffic generator that can be used to test a gem5 "
@@ -48,41 +81,52 @@
 )

 parser.add_argument(
-"module",
+"generator_class",
 type=str,
-help="The python module to import.",
+help="The class of generator to use.",
+choices=["LinearGenerator", "RandomGenerator"],
 )

 parser.add_argument(
-"mem_class",
+"cache_class",
 type=str,
-help="The memory class to import and instantiate.",
+help="The cache class to import and instantiate.",
+choices=["NoCache", "MESITwoLevel"],
 )

 parser.add_argument(
-"arguments",
+"mem_module",
+type=str,
+help="The python module to import for memory.",
+)
+
+parser.add_argument(
+"mem_class", type=str, help="The memory class to import and  
instantiate."

+)
+
+parser.add_argument(
+"mem_args",
 nargs="*",
 help="The arguments needed to instantiate the memory class.",
 )

 args = parser.parse_args()

-# This setup does not require a cache heirarchy. We therefore use the  
`NoCache`

-# setup.
-cache_hierarchy = NoCache()
+generator_class = generator_class_map[args.generator_class]
+generator = generator_class(**generator_initializers)

-memory_class =

[gem5-dev] Change in gem5/gem5[develop]: tests: Adding tests to evaluate memory modules.

2021-09-21 Thread Mahyar Samani (Gerrit) via gem5-dev

Mahyar Samani has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/50752 )



Change subject: tests: Adding tests to evaluate memory modules.
..

tests: Adding tests to evaluate memory modules.

This change adds a script to validate the statistics reported
by gem5.

Change-Id: Iae0e61c1763c099cf10924a08b3e4989dc31e220
---
A tests/gem5/configs/eval_memory_modules.py
1 file changed, 116 insertions(+), 0 deletions(-)



diff --git a/tests/gem5/configs/eval_memory_modules.py  
b/tests/gem5/configs/eval_memory_modules.py

new file mode 100644
index 000..a92ac55
--- /dev/null
+++ b/tests/gem5/configs/eval_memory_modules.py
@@ -0,0 +1,116 @@
+# Copyright (c) 2021 The Regents of the University of California
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+"""
+This script creates a simple traffic generator. The simulator starts with a
+linear traffic generator, and ends with a random traffic generator. It is  
used

+for testing purposes.
+"""
+
+import m5
+import argparse
+
+from m5.objects import Root
+from gem5.components.memory.single_channel import *
+from gem5.components.boards.test_board import TestBoard
+from gem5.components.cachehierarchies.classic.no_cache import NoCache
+from gem5.components.processors.linear_generator import LinearGenerator
+from gem5.components.processors.random_generator import RandomGenerator
+from gem5.components.memory.single_channel import (
+SingleChannelDDR3_1600,
+SingleChannelDDR4_2400,
+SingleChannelHBM,
+)
+
+mem_class_map = {
+"ddr3": SingleChannelDDR3_1600,
+"ddr4": SingleChannelDDR4_2400,
+"hbm": SingleChannelHBM,
+}
+
+generator_class_map = {"linear": LinearGenerator, "random":  
RandomGenerator}

+
+parser = argparse.ArgumentParser(
+description="A traffic generator that can be used to test a gem5 "
+"memory component."
+)
+
+parser.add_argument(
+"traffic_mode",
+type=str,
+help="Type of traffic to simulate, could be linear or random.",
+)
+
+parser.add_argument(
+"traffic_rate",
+type=str,
+help="Rate at which requests to the memory are created. "
+"Remember to include the unit. example: 100GB/s",
+)
+
+parser.add_argument(
+"mem_class", type=str, help="Class of memory to be simulated."
+)
+
+parser.add_argument(
+"rd_perc",
+type=int,
+help="Percentage of read requests among all the created requests.",
+)
+
+args = parser.parse_args()
+
+# This setup does not require a cache heirarchy. We therefore use the  
`NoCache`

+# setup.
+cache_hierarchy = NoCache()
+
+memory_class = mem_class_map[args.mem_class]
+memory = memory_class()
+
+generator_class = generator_class_map[args.traffic_mode]
+generator = generator_class(rate=args.traffic_rate)
+
+# We use the Test Board. This is a special board to run traffic generation
+# tasks
+motherboard = TestBoard(
+clk_freq="4GHz",
+processor=generator,  # We pass the traffic generator as the processor.
+memory=memory,
+cache_hierarchy=cache_hierarchy,
+)
+
+motherboard.connect_things()
+
+root = Root(full_system=False, system=motherboard)
+
+m5.instantiate()
+
+generator.start_traffic()
+print("Beginning simulation!")
+exit_event = m5.simulate()
+print(
+"Exiting @ tick {} because {}.".format(m5.curTick(),  
exit_event.getCause())

+)

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/50752
To unsubscribe, or for help writing mail filters, visit

[gem5-dev] Change in gem5/gem5[develop]: cpu: Adding GUPSGen ClockedObject.

2021-06-30 Thread Mahyar Samani (Gerrit) via gem5-dev

Mahyar Samani has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/47439 )



Change subject: cpu: Adding GUPSGen ClockedObject.
..

cpu: Adding GUPSGen ClockedObject.

This patch adds the code base to implement GUPSGen which is a
ClockedObject that creates read/write requests to the memory
to update elements in an array. The choosing of elements in
the array follow a random distribution. Each element is read
from and return as GUPSGen implements a key-value store program.
Specifications are found in HPCC website from RandomAccess
benchmark. link below.
https://icl.cs.utk.edu/projectsfiles/hpcc/RandomAccess/

Change-Id: I5c07f230bee317fff2cceec04d15d0218e8ede9a
---
A src/cpu/testers/traffic_gen/GUPSGen.py
M src/cpu/testers/traffic_gen/SConscript
A src/cpu/testers/traffic_gen/gups_gen.cc
A src/cpu/testers/traffic_gen/gups_gen.hh
4 files changed, 761 insertions(+), 0 deletions(-)



diff --git a/src/cpu/testers/traffic_gen/GUPSGen.py  
b/src/cpu/testers/traffic_gen/GUPSGen.py

new file mode 100644
index 000..9a1b7c3
--- /dev/null
+++ b/src/cpu/testers/traffic_gen/GUPSGen.py
@@ -0,0 +1,59 @@
+# Copyright (c) 2021 The Regents of the University of California.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+from m5.params import *
+from m5.proxy import *
+from m5.objects.ClockedObject import ClockedObject
+
+class GUPSGen(ClockedObject):
+"""
+This ClockedObject implements the RandomAccess benchmark specified by  
HPCC

+benchmarks in https://icl.utk.edu/projectsfiles/hpcc/RandomAccess.
+"""
+type = 'GUPSGen'
+cxx_header = "cpu/testers/traffic_gen/gups_gen.hh"
+
+system = Param.System(Parent.any, 'System this generator is a part of')
+
+port = RequestPort('Port that should be connected to other components')
+
+start_addr = Param.Addr(0, 'Start address for allocating update table,'
+' should be a multiple of block_size')
+
+mem_size = Param.MemorySize('Size for allocating update table, based  
on'

+' randomAccess benchmark specification, this'
+' should be equal to half of total system  
memory'

+' ,also should be a power of 2')
+
+update_limit = Param.Int(0, 'The number of updates to issue before the'
+' simulation is over')
+
+request_queue_size = Param.Int(1024, 'Maximum number of parallel'
+' outstanding requests')
+
+init_memory = Param.Bool(False, 'Whether or not to initialize the  
memory,'

+' it does not effect the performance')
diff --git a/src/cpu/testers/traffic_gen/SConscript  
b/src/cpu/testers/traffic_gen/SConscript

index 640d81a..a2670e7 100644
--- a/src/cpu/testers/traffic_gen/SConscript
+++ b/src/cpu/testers/traffic_gen/SConscript
@@ -43,6 +43,7 @@
 Source('dram_gen.cc')
 Source('dram_rot_gen.cc')
 Source('exit_gen.cc')
+Source('gups_gen.cc')
 Source('hybrid_gen.cc')
 Source('idle_gen.cc')
 Source('linear_gen.cc')
@@ -54,6 +55,9 @@
 DebugFlag('TrafficGen')
 SimObject('BaseTrafficGen.py')

+DebugFlag('GUPSGen')
+SimObject('GUPSGen.py')
+
 if env['USE_PYTHON']:
 Source('pygen.cc', add_tags='python')
 SimObject('PyTrafficGen.py')
diff --git a/src/cpu/testers/traffic_gen/gups_gen.cc  
b/src/cpu/testers/traffic_gen/gups_gen.cc

new file mode 100644
index 000..4a47cf2
--- /dev/null
+++

[gem5-dev] Change in gem5/gem5[develop]: cpu: Adding stridedGen

2021-03-01 Thread Mahyar Samani (Gerrit) via gem5-dev

Mahyar Samani has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40515 )


Change subject: cpu: Adding stridedGen
..

cpu: Adding stridedGen

This patch adds the source code for a mode of traffic generator to
generate strided access pattern to the memory. The main difference
between a stridedGen and linearGen are in the way startAddr and
nextAddr are set. In stridedGen instead of increasing the current
address by blocksize to generate nextAddr, it is increased by
strideSize. Also, the offset param is used to indicate the order
of any instances of traffic generator in an array (similar to
threadId.x in CUDA)

Change-Id: I80df414faf1c73f68e87400654675a553de0caa5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40515
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
---
M src/cpu/testers/traffic_gen/PyTrafficGen.py
M src/cpu/testers/traffic_gen/SConscript
M src/cpu/testers/traffic_gen/base.cc
M src/cpu/testers/traffic_gen/base.hh
A src/cpu/testers/traffic_gen/strided_gen.cc
A src/cpu/testers/traffic_gen/strided_gen.hh
6 files changed, 269 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/cpu/testers/traffic_gen/PyTrafficGen.py  
b/src/cpu/testers/traffic_gen/PyTrafficGen.py

index 962f8e0..baf4ef5 100644
--- a/src/cpu/testers/traffic_gen/PyTrafficGen.py
+++ b/src/cpu/testers/traffic_gen/PyTrafficGen.py
@@ -60,6 +60,7 @@
 PyBindMethod("createDramRot"),
 PyBindMethod("createHybrid"),
 PyBindMethod("createNvm"),
+PyBindMethod("createStrided")
 ]

 @cxxMethod(override=True)
diff --git a/src/cpu/testers/traffic_gen/SConscript  
b/src/cpu/testers/traffic_gen/SConscript

index 987ed67..640d81a 100644
--- a/src/cpu/testers/traffic_gen/SConscript
+++ b/src/cpu/testers/traffic_gen/SConscript
@@ -49,6 +49,7 @@
 Source('nvm_gen.cc')
 Source('random_gen.cc')
 Source('stream_gen.cc')
+Source('strided_gen.cc')

 DebugFlag('TrafficGen')
 SimObject('BaseTrafficGen.py')
diff --git a/src/cpu/testers/traffic_gen/base.cc  
b/src/cpu/testers/traffic_gen/base.cc

index 320de92..3c28d00 100644
--- a/src/cpu/testers/traffic_gen/base.cc
+++ b/src/cpu/testers/traffic_gen/base.cc
@@ -51,6 +51,7 @@
 #include "cpu/testers/traffic_gen/nvm_gen.hh"
 #include "cpu/testers/traffic_gen/random_gen.hh"
 #include "cpu/testers/traffic_gen/stream_gen.hh"
+#include "cpu/testers/traffic_gen/strided_gen.hh"
 #include "debug/Checkpoint.hh"
 #include "debug/TrafficGen.hh"
 #include "enums/AddrMap.hh"
@@ -520,6 +521,22 @@
 }

 std::shared_ptr
+BaseTrafficGen::createStrided(Tick duration,
+ Addr start_addr, Addr end_addr, Addr  
blocksize,

+ Addr stride_size, int gen_id,
+ Tick min_period, Tick max_period,
+ uint8_t read_percent, Addr data_limit)
+{
+return std::shared_ptr(new StridedGen(*this, requestorId,
+  duration, start_addr,
+  end_addr, blocksize,
+  system->cacheLineSize(),
+  stride_size, gen_id,
+  min_period, max_period,
+  read_percent,  
data_limit));

+}
+
+std::shared_ptr
 BaseTrafficGen::createTrace(Tick duration,
 const std::string& trace_file, Addr  
addr_offset)

 {
diff --git a/src/cpu/testers/traffic_gen/base.hh  
b/src/cpu/testers/traffic_gen/base.hh

index 018028b..a1a1efc 100644
--- a/src/cpu/testers/traffic_gen/base.hh
+++ b/src/cpu/testers/traffic_gen/base.hh
@@ -314,6 +314,13 @@
 Enums::AddrMap addr_mapping,
 unsigned int nbr_of_ranks);

+std::shared_ptr createStrided(
+Tick duration,
+Addr start_addr, Addr end_addr, Addr blocksize,
+Addr stride_size, int gen_id,
+Tick min_period, Tick max_period,
+uint8_t read_percent, Addr data_limit);
+
 std::shared_ptr createTrace(
 Tick duration,
 const std::string& trace_file, Addr addr_offset);
diff --git a/src/cpu/testers/traffic_gen/strided_gen.cc  
b/src/cpu/testers/traffic_gen/strided_gen.cc

new file mode 100644
index 000..0b77872
--- /dev/null
+++ b/src/cpu/testers/traffic_gen/strided_gen.cc
@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2012-2013, 2016-2017 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ *

[gem5-dev] Change in gem5/gem5[develop]: cpu,stats: Update stats for tage_sc_l to new style stats

2020-10-19 Thread Mahyar Samani (Gerrit) via gem5-dev

Mahyar Samani has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/36336 )



Change subject: cpu,stats: Update stats for tage_sc_l to new style stats
..

cpu,stats: Update stats for tage_sc_l to new style stats

Updated tage_sc_l.hh and tage_sc_l.cc to use new style stats.

Change-Id: If172c95bb728c7c3748269469781212ef1da6f32
---
M src/cpu/pred/tage_sc_l.cc
M src/cpu/pred/tage_sc_l.hh
2 files changed, 0 insertions(+), 8 deletions(-)



diff --git a/src/cpu/pred/tage_sc_l.cc b/src/cpu/pred/tage_sc_l.cc
index 18fe983..f69a2da 100644
--- a/src/cpu/pred/tage_sc_l.cc
+++ b/src/cpu/pred/tage_sc_l.cc
@@ -464,9 +464,3 @@

 delete bi;
 }
-
-void
-TAGE_SC_L::regStats()
-{
-LTAGE::regStats();
-}
diff --git a/src/cpu/pred/tage_sc_l.hh b/src/cpu/pred/tage_sc_l.hh
index b8714ad..d4986e2 100644
--- a/src/cpu/pred/tage_sc_l.hh
+++ b/src/cpu/pred/tage_sc_l.hh
@@ -154,8 +154,6 @@
 bool predict(
 ThreadID tid, Addr branch_pc, bool cond_branch, void* ) override;

-void regStats() override;
-
 void update(ThreadID tid, Addr branch_addr, bool taken, void  
*bp_history,

 bool squashed, const StaticInstPtr & inst,
 Addr corrTarget) override;

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/36336
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If172c95bb728c7c3748269469781212ef1da6f32
Gerrit-Change-Number: 36336
Gerrit-PatchSet: 1
Gerrit-Owner: Mahyar Samani 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: cpu,stats: Update stats for LTAGE bpred

2020-10-19 Thread Mahyar Samani (Gerrit) via gem5-dev

Mahyar Samani has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/36335 )



Change subject: cpu,stats: Update stats for LTAGE bpred
..

cpu,stats: Update stats for LTAGE bpred

Updated stats in ltage.hh and ltage.cc to use new style stats.

Change-Id: I5f676381fce6f3a0b6abc6044577540e561dcd7b
---
M src/cpu/pred/ltage.cc
M src/cpu/pred/ltage.hh
2 files changed, 0 insertions(+), 7 deletions(-)



diff --git a/src/cpu/pred/ltage.cc b/src/cpu/pred/ltage.cc
index e770336..8138cd2 100644
--- a/src/cpu/pred/ltage.cc
+++ b/src/cpu/pred/ltage.cc
@@ -141,12 +141,6 @@
 TAGE::squash(tid, bp_history);
 }

-void
-LTAGE::regStats()
-{
-TAGE::regStats();
-}
-
 LTAGE*
 LTAGEParams::create() const
 {
diff --git a/src/cpu/pred/ltage.hh b/src/cpu/pred/ltage.hh
index 9ed1e48..f8c4369 100644
--- a/src/cpu/pred/ltage.hh
+++ b/src/cpu/pred/ltage.hh
@@ -69,7 +69,6 @@
 Addr corrTarget) override;

 void init() override;
-virtual void regStats() override;

   protected:
 /** The loop predictor object */

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/36335
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I5f676381fce6f3a0b6abc6044577540e561dcd7b
Gerrit-Change-Number: 36335
Gerrit-PatchSet: 1
Gerrit-Owner: Mahyar Samani 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: mem,ext: Integrating DRAMSim3 with gem5

2020-09-02 Thread Mahyar Samani (Gerrit) via gem5-dev

Mahyar Samani has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/31757 )


Change subject: mem,ext: Integrating DRAMSim3 with gem5
..

mem,ext: Integrating DRAMSim3 with gem5

Adding DRAMSim3 source code to the gem5 source code, the original
code was taken from umd-memsys github at https://github.com/umd-memsys/

Change-Id: I32c982206f33b0acf2121f322d15baa064c412c4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31757
Reviewed-by: Ayaz Akram 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
A ext/dramsim3/README
A ext/dramsim3/SConscript
A src/mem/DRAMsim3.py
M src/mem/SConscript
A src/mem/dramsim3.cc
A src/mem/dramsim3.hh
A src/mem/dramsim3_wrapper.cc
A src/mem/dramsim3_wrapper.hh
8 files changed, 1,069 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Ayaz Akram: Looks good to me, but someone else must approve
  kokoro: Regressions pass



diff --git a/ext/dramsim3/README b/ext/dramsim3/README
new file mode 100644
index 000..f3ee0a4
--- /dev/null
+++ b/ext/dramsim3/README
@@ -0,0 +1,14 @@
+Follow these steps to get DRAMSim3 as part of gem5
+
+1. Download DRAMSim3
+1.1 Go to ext/dramsim3 (this directory)
+1.2 Clone DRAMSim3: git clone g...@github.com:umd-memsys/DRAMSim3.git  
DRAMsim3

+1.3 cd DRAMSim3 && mkdir build
+1.4 cd build
+1.5 cmake ..
+1.6 make
+
+2. Compile gem5
+2.1 cd gem5
+2.2 Business as usual
+
diff --git a/ext/dramsim3/SConscript b/ext/dramsim3/SConscript
new file mode 100644
index 000..9e5a3a1
--- /dev/null
+++ b/ext/dramsim3/SConscript
@@ -0,0 +1,69 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2013 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+import os
+
+Import('main')
+
+thermal = False
+
+# See if we got a cloned DRAMSim3 repo as a subdirectory and set the
+# HAVE_DRAMSIM flag accordingly
+if not os.path.exists(Dir('.').srcnode().abspath + '/DRAMsim3'):
+main['HAVE_DRAMSIM3'] = False
+Return()
+
+# We have got the folder, so add the library and build the wrappers
+main['HAVE_DRAMSIM3'] = True
+
+
+dramsim_path = os.path.join(Dir('#').abspath, 'ext/dramsim3/DRAMsim3/')
+
+if thermal:
+superlu_path = os.path.join(dramsim_path, 'ext/SuperLU_MT_3.1/lib')
+main.Prepend(CPPPATH=Dir('.'))
+main.Append(LIBS=['dramsim3', 'superlu_mt_OPENMP', 'm', 'f77blas',
+  'atlas', 'gomp'],
+LIBPATH=[dramsim_path, superlu_path])
+else:
+main.Prepend(CPPPATH=Dir('.'))
+# a littel hacky but can get a shared library working
+main.Append(LIBS=['dramsim3', 'gomp'],
+LIBPATH=[dramsim_path],  # compile-time lookup
+RPATH=[dramsim_path],  # runtime lookup
+CPPPATH=[dramsim_path+'/src/'])
diff --git a/src/mem/DRAMsim3.py

[gem5-dev] Change in gem5/gem5[develop]: mem,ext: Fixed DRAMSim2 Integration

2020-09-02 Thread Mahyar Samani (Gerrit) via gem5-dev

Mahyar Samani has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33938 )


Change subject: mem,ext: Fixed DRAMSim2 Integration
..

mem,ext: Fixed DRAMSim2 Integration

Fixed the way callbacks were used due to changes in
src/sim/callback.hh. Removed author line in SConsript.

Change-Id: I2c2b8dbe13e4f58680806126cd9cf209748e788a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33938
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M ext/dramsim2/SConscript
M src/mem/dramsim2.cc
2 files changed, 1 insertion(+), 2 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/ext/dramsim2/SConscript b/ext/dramsim2/SConscript
index 869d220..b4355fa 100644
--- a/ext/dramsim2/SConscript
+++ b/ext/dramsim2/SConscript
@@ -35,7 +35,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #
-# Authors: Andreas Hansson

 import os

diff --git a/src/mem/dramsim2.cc b/src/mem/dramsim2.cc
index aeafad0..2307df0 100644
--- a/src/mem/dramsim2.cc
+++ b/src/mem/dramsim2.cc
@@ -68,7 +68,7 @@

 // Register a callback to compensate for the destructor not
 // being called. The callback prints the DRAMSim2 stats.
-registerExitCallback([]() { wrapper->printStats(); });
+registerExitCallback([this]() { wrapper.printStats(); });
 }

 void

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/33938
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I2c2b8dbe13e4f58680806126cd9cf209748e788a
Gerrit-Change-Number: 33938
Gerrit-PatchSet: 3
Gerrit-Owner: Mahyar Samani 
Gerrit-Reviewer: Ayaz Akram 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Mahyar Samani 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: mem,ext: Fixed DRAMSim2 Integration

2020-09-01 Thread Mahyar Samani (Gerrit) via gem5-dev

Mahyar Samani has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33938 )



Change subject: mem,ext: Fixed DRAMSim2 Integration
..

mem,ext: Fixed DRAMSim2 Integration

Fixed the way callbacks were used due to changes in
src/sim/callback.hh. Removed author line in SConsript.

Change-Id: I2c2b8dbe13e4f58680806126cd9cf209748e788a
---
M ext/dramsim2/SConscript
M src/mem/dramsim2.cc
2 files changed, 1 insertion(+), 2 deletions(-)



diff --git a/ext/dramsim2/SConscript b/ext/dramsim2/SConscript
index 869d220..b4355fa 100644
--- a/ext/dramsim2/SConscript
+++ b/ext/dramsim2/SConscript
@@ -35,7 +35,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #
-# Authors: Andreas Hansson

 import os

diff --git a/src/mem/dramsim2.cc b/src/mem/dramsim2.cc
index aeafad0..553d2cc 100644
--- a/src/mem/dramsim2.cc
+++ b/src/mem/dramsim2.cc
@@ -68,7 +68,7 @@

 // Register a callback to compensate for the destructor not
 // being called. The callback prints the DRAMSim2 stats.
-registerExitCallback([]() { wrapper->printStats(); });
+registerExitCallback([this]() { wrapper->printStats(); });
 }

 void

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/33938
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I2c2b8dbe13e4f58680806126cd9cf209748e788a
Gerrit-Change-Number: 33938
Gerrit-PatchSet: 1
Gerrit-Owner: Mahyar Samani 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: sim: Updated function calls due in DRAMsim3.

2020-07-27 Thread Mahyar Samani (Gerrit) via gem5-dev

Mahyar Samani has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/31870 )



Change subject: sim: Updated function calls due in DRAMsim3.
..

sim: Updated function calls due in DRAMsim3.

Change-Id: Icf4d13996ceb767f622b8ac9951b3cc2488d5050
---
M src/mem/dramsim3.cc
M src/mem/dramsim3.hh
2 files changed, 4 insertions(+), 4 deletions(-)



diff --git a/src/mem/dramsim3.cc b/src/mem/dramsim3.cc
index d29ce4a..0f4933e 100644
--- a/src/mem/dramsim3.cc
+++ b/src/mem/dramsim3.cc
@@ -335,10 +335,10 @@
 }

 Port&
-DRAMsim3::getSlavePort(const std::string _name, PortID idx)
+DRAMsim3::getPort(const std::string _name, PortID idx)
 {
 if (if_name != "port") {
-return MemObject::getSlavePort(if_name, idx);
+return ClockedObject::getPort(if_name, idx);
 } else {
 return port;
 }
diff --git a/src/mem/dramsim3.hh b/src/mem/dramsim3.hh
index ce5b443..98142d5 100644
--- a/src/mem/dramsim3.hh
+++ b/src/mem/dramsim3.hh
@@ -199,8 +199,8 @@

 DrainState drain() override;

-virtual Port& getSlavePort(const std::string& if_name,
-  PortID idx = InvalidPortID) override;
+virtual Port& getPort(const std::string& if_name,
+  PortID idx = InvalidPortID) override;

 void init() override;
 void startup() override;

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31870
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Icf4d13996ceb767f622b8ac9951b3cc2488d5050
Gerrit-Change-Number: 31870
Gerrit-PatchSet: 1
Gerrit-Owner: Mahyar Samani 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: misc: Rename source code inclusion of DRAMSim3

2020-07-27 Thread Mahyar Samani (Gerrit) via gem5-dev

Mahyar Samani has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/31867 )



Change subject: misc: Rename source code inclusion of DRAMSim3
..

misc: Rename source code inclusion of DRAMSim3

Change-Id: I99f5e665cb06dc180632f176e069503c381446aa
---
M .gitignore
M configs/common/MemConfig.py
M ext/dramsim3/SConscript
R src/mem/DRAMsim3.py
M src/mem/SConscript
M src/mem/dramsim3.cc
M src/mem/dramsim3.hh
M src/mem/dramsim3_wrapper.cc
M src/mem/dramsim3_wrapper.hh
9 files changed, 101 insertions(+), 101 deletions(-)



diff --git a/.gitignore b/.gitignore
index 679c9f7..00a8756 100644
--- a/.gitignore
+++ b/.gitignore
@@ -10,7 +10,7 @@
 m5out
 /src/doxygen/html
 /ext/dramsim2/DRAMSim2
-/ext/dramsim3/DRAMSim3
+/ext/dramsim3/DRAMsim3
 /ext/mcpat/regression/*/*.out
 /util/m5/*.o
 /util/m5/*.a
diff --git a/configs/common/MemConfig.py b/configs/common/MemConfig.py
index ae04607..4831c86 100644
--- a/configs/common/MemConfig.py
+++ b/configs/common/MemConfig.py
@@ -89,7 +89,7 @@
 return _mem_classes.keys()

 def dramsim3_size_mb(ini_file):
-"""Parsing ini file for DRAMSim3 so that the system knows mem size"""
+"""Parsing ini file for DRAMsim3 so that the system knows mem size"""
 assert(os.path.exists(ini_file))
 import ConfigParser
 config = ConfigParser.ConfigParser()
@@ -179,12 +179,12 @@
 opt_xor_low_bit = getattr(options, "xor_low_bit", 0)
 opt_dramsim3_ini = getattr(options, 'dramsim3_ini', None)

-if opt_mem_type == "DRAMSim3":
+if opt_mem_type == "DRAMsim3":
 ini_file = ''
 if opt_dramsim3_ini:
 ini_file = opt_dramsim3_ini
 else:
-ini_file = m5.objects.DRAMSim3.config_file
+ini_file = m5.objects.DRAMsim3.config_file
 mem_size = dramsim3_size_mb(ini_file)
 mem_size_str =  str(mem_size) + "MB"
 options.mem_size = mem_size_str
@@ -241,9 +241,9 @@
 # address mapping in the case of a DRAM
 for r in system.mem_ranges:
 for i in xrange(nbr_mem_ctrls):
-# We need to do a couple of things differently for DRAMSim3
+# We need to do a couple of things differently for DRAMsim3
 # use same outdir as gem5, and use its own address mapping
-if opt_mem_type == 'DRAMSim3':
+if opt_mem_type == 'DRAMsim3':
 mem_ctrl = cls()
 if opt_dramsim3_ini:
 mem_ctrl.config_file = opt_dramsim3_ini
diff --git a/ext/dramsim3/SConscript b/ext/dramsim3/SConscript
index 13b13fb..3fcff46 100644
--- a/ext/dramsim3/SConscript
+++ b/ext/dramsim3/SConscript
@@ -45,7 +45,7 @@

 # See if we got a cloned DRAMSim3 repo as a subdirectory and set the
 # HAVE_DRAMSIM flag accordingly
-if not os.path.exists(Dir('.').srcnode().abspath + '/DRAMSim3'):
+if not os.path.exists(Dir('.').srcnode().abspath + '/DRAMsim3'):
 main['HAVE_DRAMSIM3'] = False
 Return()

@@ -53,7 +53,7 @@
 main['HAVE_DRAMSIM3'] = True


-dramsim_path = os.path.join(Dir('#').abspath, 'ext/dramsim3/DRAMSim3/')
+dramsim_path = os.path.join(Dir('#').abspath, 'ext/dramsim3/DRAMsim3/')

 if thermal:
 superlu_path = os.path.join(dramsim_path, 'ext/SuperLU_MT_3.1/lib')
diff --git a/src/mem/DRAMSim3.py b/src/mem/DRAMsim3.py
similarity index 93%
rename from src/mem/DRAMSim3.py
rename to src/mem/DRAMsim3.py
index c8f3efe..3b00192 100644
--- a/src/mem/DRAMSim3.py
+++ b/src/mem/DRAMsim3.py
@@ -39,15 +39,15 @@
 from AbstractMemory import *

 # A wrapper for DRAMSim2 multi-channel memory controller
-class DRAMSim3(AbstractMemory):
-type = 'DRAMSim3'
+class DRAMsim3(AbstractMemory):
+type = 'DRAMsim3'
 cxx_header = "mem/dramsim3.hh"

 # A single port for now
 port = SlavePort("Slave port")

-config_file = Param.String("ext/dramsim3/DRAMSim3/configs/"
+config_file = Param.String("ext/dramsim3/DRAMsim3/configs/"
   "DDR4_8Gb_x8_2400.ini",
   "One configuration file")
-file_path = Param.String("ext/dramsim3/DRAMSim3/",
+file_path = Param.String("ext/dramsim3/DRAMsim3/",
 "Directory to prepend to file names")
diff --git a/src/mem/SConscript b/src/mem/SConscript
index 467b188..8dcb63a 100644
--- a/src/mem/SConscript
+++ b/src/mem/SConscript
@@ -91,7 +91,7 @@
 Source('dramsim2.cc')

 if env['HAVE_DRAMSIM3']:
-SimObject('DRAMSim3.py')
+SimObject('DRAMsim3.py')
 Source('dramsim3_wrapper.cc')
 Source('dramsim3.cc')

@@ -119,7 +119,7 @@
 DebugFlag('PacketQueue')
 DebugFlag('StackDist')
 DebugFlag("DRAMSim2")
-DebugFlag("DRAMSim3")
+DebugFlag("DRAMsim3")
 DebugFlag('HMCController')
 DebugFlag('SerialLink')
 DebugFlag('TokenPort')
diff --git a/src/mem/dramsim3.cc b/src/mem/dramsim3.cc
index ef275b0..c739609 100644
--- a/src/mem/dramsim3.cc
+++ b/src/mem/dramsim3.cc
@@ -41,16 +41,16 @@

 #include

[gem5-dev] Change in gem5/gem5[develop]: sim: Fixed issue with importing AbstractMemory in DRAMsim3.py.

2020-07-27 Thread Mahyar Samani (Gerrit) via gem5-dev

Mahyar Samani has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/31868 )



Change subject: sim: Fixed issue with importing AbstractMemory in  
DRAMsim3.py.

..

sim: Fixed issue with importing AbstractMemory in DRAMsim3.py.

Change-Id: I3c81e643d31fe5d13a7ed22d5b93574ac16506a6
---
M src/mem/DRAMsim3.py
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/mem/DRAMsim3.py b/src/mem/DRAMsim3.py
index 3b00192..13a7032 100644
--- a/src/mem/DRAMsim3.py
+++ b/src/mem/DRAMsim3.py
@@ -36,7 +36,7 @@
 # Authors: Andreas Hansson

 from m5.params import *
-from AbstractMemory import *
+from m5.objects.AbstractMemory import *

 # A wrapper for DRAMSim2 multi-channel memory controller
 class DRAMsim3(AbstractMemory):

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31868
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3c81e643d31fe5d13a7ed22d5b93574ac16506a6
Gerrit-Change-Number: 31868
Gerrit-PatchSet: 1
Gerrit-Owner: Mahyar Samani 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: sim: Fixed port terminology in old DRAMsim3 sources.

2020-07-27 Thread Mahyar Samani (Gerrit) via gem5-dev

Mahyar Samani has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/31869 )



Change subject: sim: Fixed port terminology in old DRAMsim3 sources.
..

sim: Fixed port terminology in old DRAMsim3 sources.

Change-Id: Ifecd5343ab04bd200264d1678a316d26cb750d52
---
M src/mem/dramsim3.cc
M src/mem/dramsim3.hh
2 files changed, 4 insertions(+), 4 deletions(-)



diff --git a/src/mem/dramsim3.cc b/src/mem/dramsim3.cc
index c739609..d29ce4a 100644
--- a/src/mem/dramsim3.cc
+++ b/src/mem/dramsim3.cc
@@ -171,7 +171,7 @@

 // potentially update the packets in our response queue as well
 for (auto i = responseQueue.begin(); i != responseQueue.end(); ++i)
-pkt->checkFunctional(*i);
+pkt->trySatisfyFunctional(*i);

 pkt->popLabel();
 }
@@ -334,7 +334,7 @@
 signalDrainDone();
 }

-BaseSlavePort&
+Port&
 DRAMsim3::getSlavePort(const std::string _name, PortID idx)
 {
 if (if_name != "port") {
diff --git a/src/mem/dramsim3.hh b/src/mem/dramsim3.hh
index e75fff4..ce5b443 100644
--- a/src/mem/dramsim3.hh
+++ b/src/mem/dramsim3.hh
@@ -199,8 +199,8 @@

 DrainState drain() override;

-virtual BaseSlavePort& getSlavePort(const std::string& if_name,
-PortID idx = InvalidPortID)  
override;

+virtual Port& getSlavePort(const std::string& if_name,
+  PortID idx = InvalidPortID) override;

 void init() override;
 void startup() override;

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31869
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ifecd5343ab04bd200264d1678a316d26cb750d52
Gerrit-Change-Number: 31869
Gerrit-PatchSet: 1
Gerrit-Owner: Mahyar Samani 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: mem: Update DRAMSim3 functionlity to tick only in timing mode

2020-07-27 Thread Mahyar Samani (Gerrit) via gem5-dev

Mahyar Samani has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/31866 )



Change subject: mem: Update DRAMSim3 functionlity to tick only in timing  
mode

..

mem: Update DRAMSim3 functionlity to tick only in timing mode

Change-Id: I8d2e55a7e9ed7b68862491e6694a96936a2acb18
---
M src/mem/dramsim3.cc
1 file changed, 9 insertions(+), 6 deletions(-)



diff --git a/src/mem/dramsim3.cc b/src/mem/dramsim3.cc
index fdab85b..ef275b0 100644
--- a/src/mem/dramsim3.cc
+++ b/src/mem/dramsim3.cc
@@ -138,13 +138,16 @@
 void
 DRAMSim3::tick()
 {
-wrapper.tick();
+// Only tick when it's timing mode
+if (system()->isTimingMode()) {
+wrapper.tick();

-// is the connected port waiting for a retry, if so check the
-// state and send a retry if conditions have changed
-if (retryReq && nbrOutstanding() < wrapper.queueSize()) {
-retryReq = false;
-port.sendRetryReq();
+// is the connected port waiting for a retry, if so check the
+// state and send a retry if conditions have changed
+if (retryReq && nbrOutstanding() < wrapper.queueSize()) {
+retryReq = false;
+port.sendRetryReq();
+}
 }

 schedule(tickEvent, curTick() + wrapper.clockPeriod() *  
SimClock::Int::ns);


--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31866
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8d2e55a7e9ed7b68862491e6694a96936a2acb18
Gerrit-Change-Number: 31866
Gerrit-PatchSet: 1
Gerrit-Owner: Mahyar Samani 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: scons: Add omp lib for DRAMSim3 compilation

2020-07-27 Thread Mahyar Samani (Gerrit) via gem5-dev

Mahyar Samani has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/31865 )



Change subject: scons: Add omp lib for DRAMSim3 compilation
..

scons: Add omp lib for DRAMSim3 compilation

Change-Id: Ib532e89d6951d7f0d310e411ceae2b578f7629f7
---
M ext/dramsim3/SConscript
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/ext/dramsim3/SConscript b/ext/dramsim3/SConscript
index a568f11..13b13fb 100644
--- a/ext/dramsim3/SConscript
+++ b/ext/dramsim3/SConscript
@@ -64,7 +64,7 @@
 else:
 main.Prepend(CPPPATH=Dir('.'))
 # a littel hacky but can get a shared library working
-main.Append(LIBS=['dramsim3'],
+main.Append(LIBS=['dramsim3', 'gomp'],
 LIBPATH=[dramsim_path],  # compile-time lookup
 RPATH=[dramsim_path],  # runtime lookup
 CPPPATH=[dramsim_path+'/src/'])

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31865
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib532e89d6951d7f0d310e411ceae2b578f7629f7
Gerrit-Change-Number: 31865
Gerrit-PatchSet: 1
Gerrit-Owner: Mahyar Samani 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: mem: Add reset status interface for DRAMSim3

2020-07-27 Thread Mahyar Samani (Gerrit) via gem5-dev

Mahyar Samani has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/31864 )



Change subject: mem: Add reset status interface for DRAMSim3
..

mem: Add reset status interface for DRAMSim3

Change-Id: I5d253bac0f247015bb8422b56ea55e82f4c41d7c
---
M ext/dramsim3/README
M src/mem/dramsim3.cc
M src/mem/dramsim3.hh
M src/mem/dramsim3_wrapper.cc
M src/mem/dramsim3_wrapper.hh
5 files changed, 20 insertions(+), 2 deletions(-)



diff --git a/ext/dramsim3/README b/ext/dramsim3/README
index 8fd503c..d4a2db3 100644
--- a/ext/dramsim3/README
+++ b/ext/dramsim3/README
@@ -3,9 +3,9 @@
 1. Download DRAMSim3
 1.1 Go to ext/dramsim3 (this directory)
 1.2 Clone DRAMSim3: git clone g...@github.com:shavvn/DRAMSim3.git
-1.3 mkdir build
+1.3 cd DRAMSim3 && mkdir build
 1.4 cd build
-1.5 cmake ../
+1.5 cmake ..
 1.6 make

 2. Compile gem5
diff --git a/src/mem/dramsim3.cc b/src/mem/dramsim3.cc
index e2ac53b..fdab85b 100644
--- a/src/mem/dramsim3.cc
+++ b/src/mem/dramsim3.cc
@@ -95,6 +95,11 @@
 }

 void
+DRAMSim3::resetStats() {
+wrapper.resetStats();
+}
+
+void
 DRAMSim3::sendResponse()
 {
 assert(!retryResp);
diff --git a/src/mem/dramsim3.hh b/src/mem/dramsim3.hh
index 3717906..7a1a813 100644
--- a/src/mem/dramsim3.hh
+++ b/src/mem/dramsim3.hh
@@ -205,6 +205,8 @@
 void init() override;
 void startup() override;

+void resetStats() override;
+
   protected:

 Tick recvAtomic(PacketPtr pkt);
diff --git a/src/mem/dramsim3_wrapper.cc b/src/mem/dramsim3_wrapper.cc
index 0c59471..fd437c3 100644
--- a/src/mem/dramsim3_wrapper.cc
+++ b/src/mem/dramsim3_wrapper.cc
@@ -103,6 +103,12 @@
 }

 void
+DRAMSim3Wrapper::resetStats()
+{
+dramsim->ResetStats();
+}
+
+void
 DRAMSim3Wrapper::setCallbacks(std::function read_complete,
   std::function write_complete)
 {
diff --git a/src/mem/dramsim3_wrapper.hh b/src/mem/dramsim3_wrapper.hh
index f073327..8053101 100644
--- a/src/mem/dramsim3_wrapper.hh
+++ b/src/mem/dramsim3_wrapper.hh
@@ -103,6 +103,11 @@
 void printStats();

 /**
+ * Reset stats (useful for fastforwarding switch)
+ */
+void resetStats();
+
+/**
  * Set the callbacks to use for read and write completion.
  *
  * @param read_callback Callback used for read completions

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31864
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I5d253bac0f247015bb8422b56ea55e82f4c41d7c
Gerrit-Change-Number: 31864
Gerrit-PatchSet: 1
Gerrit-Owner: Mahyar Samani 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: configs: Adding DRAMSim3 models to configs

2020-07-27 Thread Mahyar Samani (Gerrit) via gem5-dev

Mahyar Samani has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/31857 )



Change subject: configs: Adding DRAMSim3 models to configs
..

configs: Adding DRAMSim3 models to configs

Change-Id: Ib243444b1dd0a7b643d765731a2753314e74baff
---
M configs/common/MemConfig.py
M configs/common/Options.py
M src/mem/DRAMSim3.py
M src/mem/dramsim3.cc
4 files changed, 102 insertions(+), 19 deletions(-)



diff --git a/configs/common/MemConfig.py b/configs/common/MemConfig.py
index b530145..ae04607 100644
--- a/configs/common/MemConfig.py
+++ b/configs/common/MemConfig.py
@@ -36,10 +36,73 @@
 from __future__ import print_function
 from __future__ import absolute_import

+import inspect
+import os
+import sys
+from textwrap import  TextWrapper
 import m5.objects
 from common import ObjectList
 from common import HMC

+# Dictionary of mapping names of real memory controller models to
+# classes.
+_mem_classes = {}
+
+def is_mem_class(cls):
+"""Determine if a class is a memory controller that can be  
instantiated"""

+
+# We can't use the normal inspect.isclass because the ParamFactory
+# and ProxyFactory classes have a tendency to confuse it.
+try:
+return issubclass(cls, m5.objects.AbstractMemory) and \
+not cls.abstract
+except TypeError:
+return False
+
+def get(name):
+"""Get a memory class from a user provided class name."""
+
+try:
+mem_class = _mem_classes[name]
+return mem_class
+except KeyError:
+print("%s is not a valid memory controller." % (name,))
+sys.exit(1)
+
+def print_mem_list():
+"""Print a list of available memory classes."""
+
+print("Available memory classes:")
+doc_wrapper = TextWrapper(initial_indent="\t\t",  
subsequent_indent="\t\t")

+for name, cls in _mem_classes.items():
+print("\t%s" % name)
+
+# Try to extract the class documentation from the class help
+# string.
+doc = inspect.getdoc(cls)
+if doc:
+for line in doc_wrapper.wrap(doc):
+print(line)
+
+def mem_names():
+"""Return a list of valid memory names."""
+return _mem_classes.keys()
+
+def dramsim3_size_mb(ini_file):
+"""Parsing ini file for DRAMSim3 so that the system knows mem size"""
+assert(os.path.exists(ini_file))
+import ConfigParser
+config = ConfigParser.ConfigParser()
+config.read(ini_file)
+channel_size = config.getint("system", "channel_size")
+num_channels = config.getint("system", "channels")
+size_mb = channel_size * num_channels
+return size_mb
+
+# Add all memory controllers in the object hierarchy.
+for name, cls in inspect.getmembers(m5.objects, is_mem_class):
+_mem_classes[name] = cls
+
 def create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits, intlv_size,\
 xor_low_bit):
 """
@@ -114,6 +177,18 @@
 opt_dram_powerdown = getattr(options, "enable_dram_powerdown", None)
 opt_mem_channels_intlv = getattr(options, "mem_channels_intlv", 128)
 opt_xor_low_bit = getattr(options, "xor_low_bit", 0)
+opt_dramsim3_ini = getattr(options, 'dramsim3_ini', None)
+
+if opt_mem_type == "DRAMSim3":
+ini_file = ''
+if opt_dramsim3_ini:
+ini_file = opt_dramsim3_ini
+else:
+ini_file = m5.objects.DRAMSim3.config_file
+mem_size = dramsim3_size_mb(ini_file)
+mem_size_str =  str(mem_size) + "MB"
+options.mem_size = mem_size_str
+system.mem_ranges = [m5.objects.AddrRange(mem_size_str)]

 if opt_mem_type == "HMC_2500_1x32":
 HMChost = HMC.config_hmc_host_ctrl(options, system)
@@ -165,22 +240,27 @@
 # array of controllers and set their parameters to match their
 # address mapping in the case of a DRAM
 for r in system.mem_ranges:
-for i in range(nbr_mem_ctrls):
-mem_ctrl = create_mem_ctrl(cls, r, i, nbr_mem_ctrls,  
intlv_bits,

-   intlv_size, opt_xor_low_bit)
-# Set the number of ranks based on the command-line
-# options if it was explicitly set
-if issubclass(cls, m5.objects.DRAMCtrl) and opt_mem_ranks:
-mem_ctrl.ranks_per_channel = opt_mem_ranks
+for i in xrange(nbr_mem_ctrls):
+# We need to do a couple of things differently for DRAMSim3
+# use same outdir as gem5, and use its own address mapping
+if opt_mem_type == 'DRAMSim3':
+mem_ctrl = cls()
+if opt_dramsim3_ini:
+mem_ctrl.config_file = opt_dramsim3_ini
+mem_ctrl.file_path = m5.options.outdir
+mem_ctrl.range = m5.objects.AddrRange(r.size())
+else:
+mem_ctrl = create_mem_ctrl(cls, r, i, nbr_mem_ctrls,
+intlv_bits,

[gem5-dev] Change in gem5/gem5[develop]: mem: Adding DRAMSim3 source code

2020-07-27 Thread Mahyar Samani (Gerrit) via gem5-dev

Mahyar Samani has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/31855 )



Change subject: mem: Adding DRAMSim3 source code
..

mem: Adding DRAMSim3 source code

Change-Id: I3e435732a495759a4001c620d89a97572041338a
---
M .gitignore
A ext/dramsim3/README
A ext/dramsim3/SConscript
A src/mem/DRAMSim3.py
A src/mem/dramsim3.cc
A src/mem/dramsim3.hh
A src/mem/dramsim3_wrapper.cc
A src/mem/dramsim3_wrapper.hh
8 files changed, 1,049 insertions(+), 0 deletions(-)



diff --git a/.gitignore b/.gitignore
index a195609..679c9f7 100644
--- a/.gitignore
+++ b/.gitignore
@@ -10,6 +10,7 @@
 m5out
 /src/doxygen/html
 /ext/dramsim2/DRAMSim2
+/ext/dramsim3/DRAMSim3
 /ext/mcpat/regression/*/*.out
 /util/m5/*.o
 /util/m5/*.a
diff --git a/ext/dramsim3/README b/ext/dramsim3/README
new file mode 100644
index 000..8fd503c
--- /dev/null
+++ b/ext/dramsim3/README
@@ -0,0 +1,15 @@
+Follow these steps to get DRAMSim3 as part of gem5
+
+1. Download DRAMSim3
+1.1 Go to ext/dramsim3 (this directory)
+1.2 Clone DRAMSim3: git clone g...@github.com:shavvn/DRAMSim3.git
+1.3 mkdir build
+1.4 cd build
+1.5 cmake ../
+1.6 make
+
+2. Compile gem5
+2.1 Business as usual
+
+3. Run gem5 with DRAMSim3
+3.1 Use --mem-type=dramsim3 and set the device and system configuration
diff --git a/ext/dramsim3/SConscript b/ext/dramsim3/SConscript
new file mode 100644
index 000..510cf4d
--- /dev/null
+++ b/ext/dramsim3/SConscript
@@ -0,0 +1,66 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2013 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Hansson
+
+import os
+
+Import('main')
+
+# See if we got a cloned DRAMSim3 repo as a subdirectory and set the
+# HAVE_DRAMSIM flag accordingly
+if not os.path.exists(Dir('.').srcnode().abspath + '/DRAMSim3'):
+main['HAVE_DRAMSIM3'] = False
+Return()
+
+# We have got the folder, so add the library and build the wrappers
+main['HAVE_DRAMSIM3'] = True
+
+# Add the appropriate files. We leave out the trace driven simulator
+dram_files = []
+
+dram_path = os.path.join(Dir('#').abspath, 'ext/dramsim3/DRAMSim3')
+
+dramsim_lib_path = os.path.join(dram_path, 'build')
+superlu_path = os.path.join(dram_path, 'ext/SuperLU_MT_3.1/lib')
+
+
+main.Prepend(CPPPATH=Dir('.'))
+main.Append(LIBS=['dramsim3', 'superlu_mt_OPENMP', 'm', 'f77blas',
+  'atlas', 'gomp'],
+LIBPATH=[dramsim_lib_path, superlu_path])
+
diff --git a/src/mem/DRAMSim3.py b/src/mem/DRAMSim3.py
new file mode 100644
index 000..45feab0
--- /dev/null
+++ b/src/mem/DRAMSim3.py
@@ -0,0 +1,52 @@
+# Copyright (c) 2013 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a

[gem5-dev] Change in gem5/gem5[develop]: scons: Update dramsim3 lib path

2020-07-27 Thread Mahyar Samani (Gerrit) via gem5-dev

Mahyar Samani has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/31858 )



Change subject: scons: Update dramsim3 lib path
..

scons: Update dramsim3 lib path

Change-Id: I6fef206882c679f5fffc6547dd7a0fdb9514d238
---
M ext/dramsim3/SConscript
1 file changed, 3 insertions(+), 4 deletions(-)



diff --git a/ext/dramsim3/SConscript b/ext/dramsim3/SConscript
index 510cf4d..0c6c971 100644
--- a/ext/dramsim3/SConscript
+++ b/ext/dramsim3/SConscript
@@ -53,14 +53,13 @@
 # Add the appropriate files. We leave out the trace driven simulator
 dram_files = []

-dram_path = os.path.join(Dir('#').abspath, 'ext/dramsim3/DRAMSim3')
+dramsim_path = os.path.join(Dir('#').abspath, 'ext/dramsim3/DRAMSim3')

-dramsim_lib_path = os.path.join(dram_path, 'build')
-superlu_path = os.path.join(dram_path, 'ext/SuperLU_MT_3.1/lib')
+superlu_path = os.path.join(dramsim_path, 'ext/SuperLU_MT_3.1/lib')


 main.Prepend(CPPPATH=Dir('.'))
 main.Append(LIBS=['dramsim3', 'superlu_mt_OPENMP', 'm', 'f77blas',
   'atlas', 'gomp'],
-LIBPATH=[dramsim_lib_path, superlu_path])
+LIBPATH=[dramsim_path, superlu_path])


--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31858
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I6fef206882c679f5fffc6547dd7a0fdb9514d238
Gerrit-Change-Number: 31858
Gerrit-PatchSet: 1
Gerrit-Owner: Mahyar Samani 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: mem: Adjust interface to new DRAMSim build

2020-07-27 Thread Mahyar Samani (Gerrit) via gem5-dev

Mahyar Samani has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/31859 )



Change subject: mem: Adjust interface to new DRAMSim build
..

mem: Adjust interface to new DRAMSim build

Change-Id: Iab1d626e18c5ea099ed994456c93eb13f3e0d46a
---
M src/mem/dramsim3.cc
M src/mem/dramsim3_wrapper.cc
M src/mem/dramsim3_wrapper.hh
3 files changed, 8 insertions(+), 8 deletions(-)



diff --git a/src/mem/dramsim3.cc b/src/mem/dramsim3.cc
index 6d37567..e9b239c 100644
--- a/src/mem/dramsim3.cc
+++ b/src/mem/dramsim3.cc
@@ -221,14 +221,14 @@
 if (can_accept) {
 // we should never have a situation when we think there is space,
 // and there isn't
-assert(wrapper.canAccept());
+assert(wrapper.canAccept(pkt->getAddr(), pkt->isWrite()));

 DPRINTF(DRAMSim3, "Enqueueing address %lld\n", pkt->getAddr());

 // @todo what about the granularity here, implicit assumption that
 // a transaction matches the burst size of the memory (which we
 // cannot determine without parsing the ini file ourselves)
-wrapper.enqueue(pkt->isWrite(), pkt->getAddr());
+wrapper.enqueue(pkt->getAddr(), pkt->isWrite());

 return true;
 } else {
diff --git a/src/mem/dramsim3_wrapper.cc b/src/mem/dramsim3_wrapper.cc
index 08f78aa..1b4aefc 100644
--- a/src/mem/dramsim3_wrapper.cc
+++ b/src/mem/dramsim3_wrapper.cc
@@ -110,15 +110,15 @@
 }

 bool
-DRAMSim3Wrapper::canAccept() const
+DRAMSim3Wrapper::canAccept(uint64_t addr, bool is_write) const
 {
-return dramsim->IsInsertable();
+return dramsim->WillAcceptTransaction(addr, is_write);
 }

 void
-DRAMSim3Wrapper::enqueue(bool is_write, uint64_t addr)
+DRAMSim3Wrapper::enqueue(uint64_t addr, bool is_write)
 {
-bool success M5_VAR_USED = dramsim->InsertRequest(is_write, addr);
+bool success M5_VAR_USED = dramsim->AddTransaction(addr, is_write);
 assert(success);
 }

diff --git a/src/mem/dramsim3_wrapper.hh b/src/mem/dramsim3_wrapper.hh
index 03e0ad5..f073327 100644
--- a/src/mem/dramsim3_wrapper.hh
+++ b/src/mem/dramsim3_wrapper.hh
@@ -116,14 +116,14 @@
  *
  * @return true if the controller can accept transactions
  */
-bool canAccept() const;
+bool canAccept(uint64_t addr, bool is_write) const;

 /**
  * Enqueue a packet. This assumes that canAccept has returned true.
  *
  * @param pkt Packet to turn into a DRAMSim3 transaction
  */
-void enqueue(bool is_write, uint64_t addr);
+void enqueue(uint64_t addr, bool is_write);

 /**
  * Get the internal clock period used by DRAMSim3, specified in

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31859
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iab1d626e18c5ea099ed994456c93eb13f3e0d46a
Gerrit-Change-Number: 31859
Gerrit-PatchSet: 1
Gerrit-Owner: Mahyar Samani 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: scons: Add support for shared dramsim lib

2020-07-27 Thread Mahyar Samani (Gerrit) via gem5-dev

Mahyar Samani has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/31862 )



Change subject: scons: Add support for shared dramsim lib
..

scons: Add support for shared dramsim lib

Change-Id: I72e42816d23efc6655ea6ae4f378944cc105ea11
---
M ext/dramsim3/SConscript
1 file changed, 5 insertions(+), 3 deletions(-)



diff --git a/ext/dramsim3/SConscript b/ext/dramsim3/SConscript
index bc2333d..a568f11 100644
--- a/ext/dramsim3/SConscript
+++ b/ext/dramsim3/SConscript
@@ -53,7 +53,7 @@
 main['HAVE_DRAMSIM3'] = True


-dramsim_path = os.path.join(Dir('#').abspath, 'ext/dramsim3/DRAMSim3')
+dramsim_path = os.path.join(Dir('#').abspath, 'ext/dramsim3/DRAMSim3/')

 if thermal:
 superlu_path = os.path.join(dramsim_path, 'ext/SuperLU_MT_3.1/lib')
@@ -63,6 +63,8 @@
 LIBPATH=[dramsim_path, superlu_path])
 else:
 main.Prepend(CPPPATH=Dir('.'))
+# a littel hacky but can get a shared library working
 main.Append(LIBS=['dramsim3'],
-LIBPATH=[dramsim_path])
-
+LIBPATH=[dramsim_path],  # compile-time lookup
+RPATH=[dramsim_path],  # runtime lookup
+CPPPATH=[dramsim_path+'/src/'])

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31862
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I72e42816d23efc6655ea6ae4f378944cc105ea11
Gerrit-Change-Number: 31862
Gerrit-PatchSet: 1
Gerrit-Owner: Mahyar Samani 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: sim: Adding DRAMSim3 compilatin flags

2020-07-27 Thread Mahyar Samani (Gerrit) via gem5-dev

Mahyar Samani has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/31854 )



Change subject: sim: Adding DRAMSim3 compilatin flags
..

sim: Adding DRAMSim3 compilatin flags

Change-Id: Id2edb4f9c0c942f3a8fd47b3df66e3beb394be28
---
M src/mem/SConscript
1 file changed, 6 insertions(+), 0 deletions(-)



diff --git a/src/mem/SConscript b/src/mem/SConscript
index b77dbb1..467b188 100644
--- a/src/mem/SConscript
+++ b/src/mem/SConscript
@@ -90,6 +90,11 @@
 Source('dramsim2_wrapper.cc')
 Source('dramsim2.cc')

+if env['HAVE_DRAMSIM3']:
+SimObject('DRAMSim3.py')
+Source('dramsim3_wrapper.cc')
+Source('dramsim3.cc')
+
 SimObject('MemChecker.py')
 Source('mem_checker.cc')
 Source('mem_checker_monitor.cc')
@@ -114,6 +119,7 @@
 DebugFlag('PacketQueue')
 DebugFlag('StackDist')
 DebugFlag("DRAMSim2")
+DebugFlag("DRAMSim3")
 DebugFlag('HMCController')
 DebugFlag('SerialLink')
 DebugFlag('TokenPort')

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31854
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id2edb4f9c0c942f3a8fd47b3df66e3beb394be28
Gerrit-Change-Number: 31854
Gerrit-PatchSet: 1
Gerrit-Owner: Mahyar Samani 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: sim: Fix callback crushing issue

2020-07-27 Thread Mahyar Samani (Gerrit) via gem5-dev

Mahyar Samani has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/31856 )



Change subject: sim: Fix callback crushing issue
..

sim: Fix callback crushing issue

Change-Id: I5943cf2ca3bba8495b4ff238898a823ba8562a81
---
M src/mem/DRAMSim3.py
M src/mem/dramsim3.cc
M src/mem/dramsim3.hh
3 files changed, 19 insertions(+), 13 deletions(-)



diff --git a/src/mem/DRAMSim3.py b/src/mem/DRAMSim3.py
index 45feab0..d33d001 100644
--- a/src/mem/DRAMSim3.py
+++ b/src/mem/DRAMSim3.py
@@ -46,7 +46,8 @@
 # A single port for now
 port = SlavePort("Slave port")

-deviceConfigFile = Param.String("configs/DDR4_8Gb_x8_2400.ini",
-"One configuration file")
+configFile = Param.String("ext/dramsim3/DRAMSim3/configs/"
+  "DDR4_8Gb_x8_2400.ini",
+  "One configuration file")
 filePath = Param.String("ext/dramsim3/DRAMSim3/",
 "Directory to prepend to file names")
diff --git a/src/mem/dramsim3.cc b/src/mem/dramsim3.cc
index 26212e3..a18e1f4 100644
--- a/src/mem/dramsim3.cc
+++ b/src/mem/dramsim3.cc
@@ -48,17 +48,21 @@
 DRAMSim3::DRAMSim3(const Params* p) :
 AbstractMemory(p),
 port(name() + ".port", *this),
-wrapper(p->deviceConfigFile, p->filePath, NULL, NULL),
+read_cb(std::bind(::readComplete,
+  this, 0, std::placeholders::_1)),
+write_cb(std::bind(::writeComplete,
+   this, 0, std::placeholders::_1)),
+wrapper(p->configFile, p->filePath, read_cb, write_cb),
 retryReq(false), retryResp(false), startTick(0),
 nbrOutstandingReads(0), nbrOutstandingWrites(0),
 sendResponseEvent([this]{ sendResponse(); }, name()),
 tickEvent([this]{ tick(); }, name())
 {
-read_cb =
-std::bind(::readComplete, this, 0, std::placeholders::_1);
-write_cb =
-std::bind(::writeComplete, this, 0,  
std::placeholders::_1);

-wrapper.setCallbacks(read_cb, write_cb);
+// read_cb =
+// std::bind(::readComplete, this, 0,  
std::placeholders::_1);

+// write_cb =
+// std::bind(::writeComplete, this, 0,  
std::placeholders::_1);

+// wrapper.setCallbacks(read_cb, write_cb);

 DPRINTF(DRAMSim3,
 "Instantiated DRAMSim3 with clock %d ns and queue size %d\n",
diff --git a/src/mem/dramsim3.hh b/src/mem/dramsim3.hh
index 48c28d6..3717906 100644
--- a/src/mem/dramsim3.hh
+++ b/src/mem/dramsim3.hh
@@ -90,6 +90,12 @@
 MemoryPort port;

 /**
+ * Callback functions
+ */
+std::function read_cb;
+std::function write_cb;
+
+/**
  * The actual DRAMSim3 wrapper
  */
 DRAMSim3Wrapper wrapper;
@@ -133,11 +139,6 @@
  */
 std::deque responseQueue;

-/**
- * Callback functions
- */
-std::function read_cb;
-std::function write_cb;

 unsigned int nbrOutstanding() const;


--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31856
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I5943cf2ca3bba8495b4ff238898a823ba8562a81
Gerrit-Change-Number: 31856
Gerrit-PatchSet: 1
Gerrit-Owner: Mahyar Samani 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: mem: Update dramsim header

2020-07-27 Thread Mahyar Samani (Gerrit) via gem5-dev

Mahyar Samani has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/31863 )



Change subject: mem: Update dramsim header
..

mem: Update dramsim header

Change-Id: I3d13d957f8941d070fd7a23932d1a50793bab854
---
M src/mem/dramsim3_wrapper.cc
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/mem/dramsim3_wrapper.cc b/src/mem/dramsim3_wrapper.cc
index 1b4aefc..0c59471 100644
--- a/src/mem/dramsim3_wrapper.cc
+++ b/src/mem/dramsim3_wrapper.cc
@@ -52,7 +52,7 @@

 #include 

-#include "DRAMSim3/src/memory_system.h"
+#include "DRAMSim3/src/dramsim3.h"
 #include "base/compiler.hh"
 #include "base/logging.hh"


--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31863
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3d13d957f8941d070fd7a23932d1a50793bab854
Gerrit-Change-Number: 31863
Gerrit-PatchSet: 1
Gerrit-Owner: Mahyar Samani 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: misc: Remove commented code

2020-07-27 Thread Mahyar Samani (Gerrit) via gem5-dev

Mahyar Samani has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/31860 )



Change subject: misc: Remove commented code
..

misc: Remove commented code

Change-Id: Iacb6be190efef03968e42c5221bf22d98388cd60
---
M src/mem/dramsim3.cc
1 file changed, 0 insertions(+), 10 deletions(-)



diff --git a/src/mem/dramsim3.cc b/src/mem/dramsim3.cc
index e9b239c..e2ac53b 100644
--- a/src/mem/dramsim3.cc
+++ b/src/mem/dramsim3.cc
@@ -58,12 +58,6 @@
 sendResponseEvent([this]{ sendResponse(); }, name()),
 tickEvent([this]{ tick(); }, name())
 {
-// read_cb =
-// std::bind(::readComplete, this, 0,  
std::placeholders::_1);

-// write_cb =
-// std::bind(::writeComplete, this, 0,  
std::placeholders::_1);

-// wrapper.setCallbacks(read_cb, write_cb);
-
 DPRINTF(DRAMSim3,
 "Instantiated DRAMSim3 with clock %d ns and queue size %d\n",
 wrapper.clockPeriod(), wrapper.queueSize());
@@ -286,8 +280,6 @@

 void DRAMSim3::readComplete(unsigned id, uint64_t addr)
 {
-// assert(cycle == divCeil(curTick() - startTick,
-// wrapper.clockPeriod() * SimClock::Int::ns));

 DPRINTF(DRAMSim3, "Read to address %lld complete\n", addr);

@@ -314,8 +306,6 @@

 void DRAMSim3::writeComplete(unsigned id, uint64_t addr)
 {
-// assert(cycle == divCeil(curTick() - startTick,
-// wrapper.clockPeriod() * SimClock::Int::ns));

 DPRINTF(DRAMSim3, "Write to address %lld complete\n", addr);


--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31860
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iacb6be190efef03968e42c5221bf22d98388cd60
Gerrit-Change-Number: 31860
Gerrit-PatchSet: 1
Gerrit-Owner: Mahyar Samani 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: scons: Separate thermal build flag

2020-07-27 Thread Mahyar Samani (Gerrit) via gem5-dev

Mahyar Samani has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/31861 )



Change subject: scons: Separate thermal build flag
..

scons: Separate thermal build flag

Change-Id: Iad502dbdbc8665fe9c744451b1b67cce25f6a65d
---
M ext/dramsim3/SConscript
1 file changed, 12 insertions(+), 9 deletions(-)



diff --git a/ext/dramsim3/SConscript b/ext/dramsim3/SConscript
index 0c6c971..bc2333d 100644
--- a/ext/dramsim3/SConscript
+++ b/ext/dramsim3/SConscript
@@ -41,6 +41,8 @@

 Import('main')

+thermal = False
+
 # See if we got a cloned DRAMSim3 repo as a subdirectory and set the
 # HAVE_DRAMSIM flag accordingly
 if not os.path.exists(Dir('.').srcnode().abspath + '/DRAMSim3'):
@@ -50,16 +52,17 @@
 # We have got the folder, so add the library and build the wrappers
 main['HAVE_DRAMSIM3'] = True

-# Add the appropriate files. We leave out the trace driven simulator
-dram_files = []

 dramsim_path = os.path.join(Dir('#').abspath, 'ext/dramsim3/DRAMSim3')

-superlu_path = os.path.join(dramsim_path, 'ext/SuperLU_MT_3.1/lib')
-
-
-main.Prepend(CPPPATH=Dir('.'))
-main.Append(LIBS=['dramsim3', 'superlu_mt_OPENMP', 'm', 'f77blas',
-  'atlas', 'gomp'],
-LIBPATH=[dramsim_path, superlu_path])
+if thermal:
+superlu_path = os.path.join(dramsim_path, 'ext/SuperLU_MT_3.1/lib')
+main.Prepend(CPPPATH=Dir('.'))
+main.Append(LIBS=['dramsim3', 'superlu_mt_OPENMP', 'm', 'f77blas',
+  'atlas', 'gomp'],
+LIBPATH=[dramsim_path, superlu_path])
+else:
+main.Prepend(CPPPATH=Dir('.'))
+main.Append(LIBS=['dramsim3'],
+LIBPATH=[dramsim_path])


--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31861
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iad502dbdbc8665fe9c744451b1b67cce25f6a65d
Gerrit-Change-Number: 31861
Gerrit-PatchSet: 1
Gerrit-Owner: Mahyar Samani 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: sim: Fixed error when compiling gem5 with dramsim2.

2020-07-17 Thread Mahyar Samani (Gerrit) via gem5-dev

Mahyar Samani has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/31434 )


Change subject: sim: Fixed error when compiling gem5 with dramsim2.
..

sim: Fixed error when compiling gem5 with dramsim2.

Compiling gem5 with dramsim2 included fails due to some inconsistencies in
including SimObjects. In this patch this issue is fixed along with
temporarily disabling -Werror=nonnull-compare in CCFLAGS. Also, the remote
for cloning dramsim2 has been changed.

Change-Id: Ia24095150d026d736352aaf0d735b7554ede10bb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31434
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M ext/dramsim2/README
M ext/dramsim2/SConscript
M src/mem/DRAMSim2.py
3 files changed, 3 insertions(+), 3 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/ext/dramsim2/README b/ext/dramsim2/README
index f83e3f0..7c5535d 100644
--- a/ext/dramsim2/README
+++ b/ext/dramsim2/README
@@ -2,7 +2,7 @@

 1. Download DRAMSim2
 1.1 Go to ext/dramsim2 (this directory)
-1.2 Clone DRAMSim2: git clone  
git://github.com/dramninjasUMD/DRAMSim2.git

+1.2 Clone DRAMSim2: git clone g...@github.com:umd-memsys/DRAMSim2.git

 2. Compile gem5
 2.1 Business as usual
diff --git a/ext/dramsim2/SConscript b/ext/dramsim2/SConscript
index bc4c047..869d220 100644
--- a/ext/dramsim2/SConscript
+++ b/ext/dramsim2/SConscript
@@ -73,7 +73,7 @@
 # DRAMSim2 violates some of the warning flags used by gem5, so
 # we explicitly disable them here
 dramenv = main.Clone()
-dramenv.Append(CCFLAGS=['-Wno-unused-value'])
+dramenv.Append(CCFLAGS=['-Wno-unused-value', '-Wno-error=nonnull-compare'])

 # If we are using clang, there are more flags to disable
 if main['CLANG']:
diff --git a/src/mem/DRAMSim2.py b/src/mem/DRAMSim2.py
index aa83729..bf5143f 100644
--- a/src/mem/DRAMSim2.py
+++ b/src/mem/DRAMSim2.py
@@ -34,7 +34,7 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 from m5.params import *
-from AbstractMemory import *
+from m5.objects.AbstractMemory import *

 # A wrapper for DRAMSim2 multi-channel memory controller
 class DRAMSim2(AbstractMemory):

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31434
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia24095150d026d736352aaf0d735b7554ede10bb
Gerrit-Change-Number: 31434
Gerrit-PatchSet: 3
Gerrit-Owner: Mahyar Samani 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Mahyar Samani 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Add hsub instructions to x86

2020-04-23 Thread Mahyar Samani (Gerrit) via gem5-dev

Mahyar Samani has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/26123 )


Change subject: arch-x86: Add hsub instructions to x86
..

arch-x86: Add hsub instructions to x86

Implemented hsubpd and hsubps instructions from x86.

Issue-on: https://gem5.atlassian.net/browse/GEM5-181
Change-Id: I62919017d3c00119123bda89b2f99cb3bf0b55a8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26123
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/x86/isa/decoder/two_byte_opcodes.isa
M  
src/arch/x86/isa/insts/simd128/floating_point/arithmetic/horizontal_subtraction.py

2 files changed, 49 insertions(+), 4 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa  
b/src/arch/x86/isa/decoder/two_byte_opcodes.isa

index c7c62c2..28affdb 100644
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -691,7 +691,7 @@
 // operand size (0x66)
 0x1: decode OPCODE_OP_BOTTOM3 {
 0x4: HADDPD(Vo,Wo);
-0x5: WarnUnimpl::hsubpd_Vo_Wo();
+0x5: HSUBPD(Vo, Wo);
 0x6: MOVD(Edp,Vd);
 0x7: MOVDQA(Wo,Vo);
 default: UD2();
@@ -699,7 +699,7 @@
 // repne (0xF2)
 0x8: decode OPCODE_OP_BOTTOM3 {
 0x4: HADDPS(Vo,Wo);
-0x5: WarnUnimpl::hsubps_Vo_Wo();
+0x5: HSUBPS(Vo, Wo);
 default: UD2();
 }
 default: UD2();
diff --git  
a/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/horizontal_subtraction.py  
b/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/horizontal_subtraction.py

index a629ecd..43523c1 100644
---  
a/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/horizontal_subtraction.py
+++  
b/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/horizontal_subtraction.py

@@ -34,6 +34,51 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 microcode = '''
-# HSUBPS
-# HSUBPD
+def macroop HSUBPS_XMM_XMM {
+shuffle ufp1, xmml, xmmh, ext=((0 << 0) | (2 << 2)), size=4
+shuffle ufp2, xmml, xmmh, ext=((1 << 0) | (3 << 2)), size=4
+shuffle ufp3, xmmlm, xmmhm, ext=((0 << 0) | (2 << 2)), size=4
+shuffle ufp4, xmmlm, xmmhm, ext=((1 << 0) | (3 << 2)), size=4
+msubf xmml, ufp1, ufp2, size=4
+msubf xmmh, ufp3, ufp4, size=4
+};
+def macroop HSUBPS_XMM_M {
+ldfp ufp1, seg, sib, disp, dataSize=8
+ldfp ufp2, seg, sib, "DISPLACEMENT+8", dataSize=8
+shuffle ufp3, xmml, xmmh, ext=((0 << 0) | (2 << 2)), size=4
+shuffle ufp4, xmml, xmmh, ext=((1 << 0) | (3 << 2)), size=4
+shuffle ufp5, ufp1, ufp2, ext=((0 << 0) | (2 << 2)), size=4
+shuffle ufp6, ufp1, ufp2, ext=((1 << 0) | (3 << 2)), size=4
+msubf xmml, ufp3, ufp4, size=4
+msubf xmmh, ufp5, ufp6, size=4
+};
+def macroop HSUBPS_XMM_P {
+rdip t7
+ldfp ufp1, seg, riprel, disp, dataSize=8
+ldfp ufp2, seg, riprel, "DISPLACEMENT+8", dataSize=8
+shuffle ufp3, xmml, xmmh, ext=((0 << 0) | (2 << 2)), size=4
+shuffle ufp4, xmml, xmmh, ext=((1 << 0) | (3 << 2)), size=4
+shuffle ufp5, ufp1, ufp2, ext=((0 << 0) | (2 << 2)), size=4
+shuffle ufp6, ufp1, ufp2, ext=((1 << 0) | (3 << 2)), size=4
+msubf xmml, ufp3, ufp4, size=4
+msubf xmmh, ufp5, ufp6, size=4
+};
+def macroop HSUBPD_XMM_XMM {
+msubf ufp1, xmmh , xmml, size=8, ext=Scalar
+msubf xmmh, xmmlm, xmmhm, size=8, ext=Scalar
+movfp xmml, ufp1
+};
+def macroop HSUBPD_XMM_M {
+ldfp ufp1, seg, sib, disp, dataSize=8
+ldfp ufp2, seg, sib, "DISPLACEMENT+8", dataSize=8
+msubf xmml, xmml, xmmh, size=8, ext=Scalar
+msubf xmmh, ufp1, ufp2, size=8, ext=Scalar
+};
+def macroop HSUBPD_XMM_P {
+rdip t7
+ldfp ufp1, seg, riprel, disp, dataSize=8
+ldfp ufp2, seg, riprel, "DISPLACEMENT+8", dataSize=8
+msubf xmml, xmml, xmmh, size=8, ext=Scalar
+msubf xmmh, ufp1, ufp2, size=8, ext=Scalar
+};
 '''

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/26123
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I62919017d3c00119123bda89b2f99cb3bf0b55a8
Gerrit-Change-Number: 26123
Gerrit-PatchSet: 8
Gerrit-Owner: Mahyar Samani 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Mahyar Samani 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

60 matches

Mail list logo