[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task has a new comment added: FS#337 - Checkpoint Tester Identifies Mismatches (Bugs) for X86_FS User who did this: - Brad Beckmann (beckmabd) -- Responses below: 1. Actually I don't believe the MOESI_hammer part of the binary is important at all. It just happened to be the particular binary I had built when observing the issue. Since the test uses X86_FS in atomic mode, any X86_FS binary should behave the same. 2. Yes, the script option doesn't matter either. I only specified it because I copied it from the example listed in checkpoint-tester.py. 3. I believe that since each user may have their kernel in different locations that it made sense that a default wasn't specified. I'll send you a separate mail with the specific kernel I used. So in summary, the following commands also lead to the exact same problem: % scons -j 4 default=X86_FS build/X86_FS/m5.debug USE_MYSQL=False NO_FAST_ALLOC=1 EXTRAS= % util/checkpoint-tester.py -i 2000 -- build/X86_FS/m5.debug configs/example/fs.py -- More information can be found at the following URL: http://www.m5sim.org/flyspray/task/337#comment164 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task has a new comment added: FS#337 - Checkpoint Tester Identifies Mismatches (Bugs) for X86_FS User who did this: - Gabe Black (gblack) -- Yeah, I was able to reproduce the problem so that wasn't an issue, I just wanted to point out the differences in case somebody else wanted to reproduce it too. I poked at it a bit and have some idea what's going on, but I need to dig into what I was seeing a little deeper so I don't go charging off in the wrong direction. -- More information can be found at the following URL: http://www.m5sim.org/flyspray/task/337#comment165 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task has a new comment added: FS#337 - Checkpoint Tester Identifies Mismatches (Bugs) for X86_FS User who did this: - Gabe Black (gblack) -- I looked at this, and there are still some problems with your command line. 1. X86_FS_MOESI_hammer doesn't exist in the public repository. I created it by merging ALPHA_SE_MOESI_hammer and X86_FS 2. The X86 FS files available publicly don't yet, to the best of my knowledge, support the --script option to fs.py. It's unnecessary anyway since the simulation is stopped long, long before it gets to user land. 3. The version of fs.py in the public repository doesn't seem to want to run without --kernel being specified. I don't remember for sure if I added a default, but apparently I didn't. I have some basic ideas about what actually makes the checker upset, but I need to look at it again more carefully. -- More information can be found at the following URL: http://www.m5sim.org/flyspray/task/337#comment163 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task has a new comment added: FS#337 - Checkpoint Tester Identifies Mismatches (Bugs) for X86_FS User who did this: - Brad Beckmann (beckmabd) -- Oops...it is the same command line, just a different binary: util/checkpoint-tester.py -i 2000 -- build/X86_FS_MOESI_hammer/m5.debug configs/example/fs.py --script test/halt.sh -- More information can be found at the following URL: http://www.m5sim.org/flyspray/task/337#comment162 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task has a new comment added: FS#337 - Checkpoint Tester Identifies Mismatches (Bugs) for X86_FS User who did this: - Gabe Black (gblack) -- The differences in state look like basically one more (or less) instruction/microop executed between the two instances. My very off the cuff hunch is that the macroop isn't being checkpointed, so when the CPU starts up again it has to fetch the instruction, decode it to a macroop, and then start executing the microops. When it's not from a checkpoint, the macroop is already there and ready to go. If that is what's happening, no trivial fix springs to mind, though here are some non-trivial possibilities. One would be to force the current macroop to finish executing and consider that part of draining (right term?), although there's no guaranteed bound to how long a macroop can take. They would practically tend to be short, but tend to isn't something to design around. Alternatively, when dropping a checkpoint we could just forcefully lose track of the macroop so it has to be fetched again in both cases. A third option would be to serialize the macroop itself by serializing it's ExtMachInst, although I suspect there would be complications and it isn't clear it would be worthwhile unless checkpointing was frequent enough to cause statistically meaningful differences in behavior without that sort of thing. -- More information can be found at the following URL: http://www.m5sim.org/flyspray/task/337#comment159 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task has a new comment added: FS#251 - valgrind detects two errors User who did this: - Gabe Black (gblack) -- These look like they might be that issue we fixed in the UART code a little while ago. Could you please check to see if they're still there? -- More information can be found at the following URL: http://www.m5sim.org/flyspray/task/251#comment160 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task is now closed: FS#335 - SPARC's call instruction makes R15 look like a source User who did this: - Gabe Black (gblack) Reason for closing: - Fixed More information can be found at the following URL: http://www.m5sim.org/flyspray/task/335 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task is now closed: FS#325 - clean up PC management in the simple CPU User who did this: - Gabe Black (gblack) Reason for closing: - Fixed More information can be found at the following URL: http://www.m5sim.org/flyspray/task/325 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task has been changed. The new details are below. For full information about what has changed, visit the URL and click the History tab. FS#333 - Create a generic ISA directory. User who did this: - Gabe Black (gblack) Attached to Project - M5 Bugs Summary - Create a generic ISA directory. Task Type - Minor Enhancement Category - ISA Support Status - New Assigned To - Gabe Black Operating System - All Severity - Low Priority - Normal Reported Version - 2.0beta5 Due in Version - Due Date - Undecided Percent Complete - 30% Details - A non-trivial amount of code is exactly the same between multiple ISAs or is the same but with minor modifications. A directory in arch called generic should be created for these common implementations which will be put in an namespace called GenericISA. The individual ISAs can wrap these versions of functions or pieces of functions, or import them directly into their own namespace with using. The directory has been created, and now more common code needs to be moved into it. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/333 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. A new Flyspray task has been opened. Details are below. User who did this: - Brad Beckmann (beckmabd) Attached to Project - M5 Bugs Summary - Checkpoint Tester Identifies Mismatches (Bugs) for X86_FS Task Type - Bug Category - ISA Support Status - Unconfirmed Assigned To - Operating System - Linux Severity - High Priority - Normal Reported Version - 2.0beta5 Due in Version - Due Date - Undecided Details - While using the checkpoint tester script, I noticed that X86_FS encounters differences in the checkpoint state. This problem exists for both atomic and timing mode, as well as classic and Ruby memory systems. A short test with the checkpoint tester script, will identify the problem: % util/checkpoint-tester.py -i 2000 -- build/ALPHA_FS_MOESI_hammer/m5.debug configs/example/fs.py --script test/halt.sh Identified differences in the checkpoint: --- checkpoint-test/m5out/cpt.1/m5.cpt Wed Jan 12 14:59:28 2011 +++ checkpoint-test/test.4/cpt.1/m5.cpt Wed Jan 12 15:00:42 2011 @@ -10,20 +10,20 @@ so_state=2 locked=false _status=1 -instCnt=10 +instCnt=9 [system.cpu.xc.0] _status=0 -funcExeInst=16 +funcExeInst=15 quiesceEndTick=0 iplLast=0 iplLastTick=0 floatRegs.i=0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -intRegs=549755813888 0 2097152 0 0 0 590336 0 0 0 0 0 0 0 0 0 0 2097208 380 0 0 0 0 2097189 0 0 0 0 0 0 0 0 133 0 0 0 0 0 0 +intRegs=549755813888 0 2097152 0 0 0 590336 0 0 0 0 0 0 0 0 0 +18446743523955834880 2097182 380 0 0 0 0 2097189 0 0 0 0 0 0 0 0 133 0 0 0 0 0 0 _pc=2097202 -_npc=2097208 -_upc=1 -_nupc=2 +_npc=2097210 +_upc=0 +_nupc=1 regVal=3758096401 0 0 458752 32 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4294905840 1024 2 243392 0 1288 0 0 0 260 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1974748653749254 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1280 0 0 0 0 0 0 0 0 0 0 0 0 0 0 132609 0 0 0 0 67108864 0 0 0 0 0 16 8 16 16 16 16 0 0 0 0 0 24 0 0 0 0 0 0 0 0 0 483328 0 0 0 0 0 0 0 0 0 0 0 0 483328 0 0 0 0 983295 983295 983295 983295 983295 983295 65535 65535 23 65535 65535 983295 655 35 45768 43728 45768 45768 45768 45768 45952 0 45952 45952 45952 43976 45952 0 0 0 0 0 0 0 0 0 0 0 4 276095232 0 [system.cpu.tickEvent] More information can be found at the following URL: http://www.m5sim.org/flyspray/task/337 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task is now closed: FS#336 - strange, possibly wrong return value in i8254xGBe descSize function User who did this: - Ali Saidi (saidi) Reason for closing: - Fixed More information can be found at the following URL: http://www.m5sim.org/flyspray/task/336 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. A new Flyspray task has been opened. Details are below. User who did this: - Gabe Black (gblack) Attached to Project - M5 Bugs Summary - strange, possibly wrong return value in i8254xGBe descSize function Task Type - Bug Category - Device Models Status - New Assigned To - Ali Saidi Operating System - All Severity - Low Priority - Normal Reported Version - 2.0beta5 Due in Version - Due Date - Undecided Details - The descSize function in i8254xGBe_defs.hh returns a -1 in a few places, even though it has an unsigned return type. It's possible this is to indicate an error, or a convenient way to return a very large size. In the former case, it doesn't look like the -1 is ever checked for, so any error being flagged would probably go unnoticed and cause strange downstream behavior. In both cases, the implicit conversion of -1 to an unsigned value causes certain versions of gcc to warn, and that causes compilation to fail. The warning would likely go away if the conversion was explicit, ie. (unsigned)(-1). More information can be found at the following URL: http://www.m5sim.org/flyspray/task/336 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. A new Flyspray task has been opened. Details are below. User who did this: - Ali Saidi (saidi) Attached to Project - M5 Bugs Summary - Cleanup RemoteGDB code Task Type - Minor Enhancement Category - Utilities Status - New Assigned To - Operating System - All Severity - Medium Priority - Normal Reported Version - 2.0beta5 Due in Version - Due Date - Undecided Details - The remote gdb code could use some better structuring and perhaps templating on the ISA. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/334 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. A new Flyspray task has been opened. Details are below. User who did this: - Steve Reinhardt (stever) Attached to Project - M5 Bugs Summary - minor FS checkpoint/restore discrepancies Task Type - Bug Category - CPU Status - New Assigned To - Operating System - All Severity - Medium Priority - Normal Reported Version - 2.0beta5 Due in Version - Due Date - Undecided Details - Running the following command: util/checkpoint-tester.py -i 2000 -- build/ALPHA_FS/m5.opt configs/example/fs.py --script tests/halt.sh reveals a few discrepancies. First, the files that restore from a checkpoint always seem to have 24 more instructions in instCnt and funcExeInst than the original run. Second, sometimes the first field of rtc.clock_data (the seconds field?) is a 1 in the checkpoints regenerated from earlier checkpoints, even though it's always a 0 in the original checkpoints. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/332 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task is now closed: FS#60 - Verify IPRs in ev5.cc User who did this: - Steve Reinhardt (stever) Reason for closing: - Not a bug Additional comments about closing: - This task is pretty vague, and we are moving away from depending on Alpha anyway. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/60 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task is now closed: FS#95 - Figure out possible EIO replacement User who did this: - Steve Reinhardt (stever) Reason for closing: - Won't implement Additional comments about closing: - Not seeing any demand for this. If someone does need something like this, they're free to do whatever solves their problem. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/95 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task is now closed: FS#246 - Odd pthread_mutex_test behavior User who did this: - Steve Reinhardt (stever) Reason for closing: - Not a bug Additional comments about closing: - From the description this sounds like an artifact of poor Linux thread scheduling decisions... outside of our scope. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/246 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task has had a dependency removed: FS#133 - Make ROB per-thread for SMT User who did this: - Korey Sewell (ksewell) More information can be found at the following URL: http://www.m5sim.org/flyspray/task/133 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task is now closed: FS#28 - checkpoint - InstCheckpoint User who did this: - Steve Reinhardt (stever) Reason for closing: - Not a bug Additional comments about closing: - There is no checkpoint in isa_parser.py. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/28 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task is now closed: FS#59 - Match names in code for convience/clarity User who did this: - Steve Reinhardt (stever) Reason for closing: - Works for me Additional comments about closing: - Don't see 'virt_addr' or 'virtAddr' in the code anymore, just 'vaddr'. There are some 'effAddr' cases but that seems OK to me. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/59 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task has had a dependency removed: FS#318 - SPLASH doesn't work on O3 SE mode User who did this: - Korey Sewell (ksewell) More information can be found at the following URL: http://www.m5sim.org/flyspray/task/318 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task is now closed: FS#318 - SPLASH doesn't work on O3 SE mode User who did this: - Korey Sewell (ksewell) Reason for closing: - Duplicate Additional comments about closing: - Handled by patch from stever in FS#317 (http://www.m5sim.org/flyspray/task/317) ... More information can be found at the following URL: http://www.m5sim.org/flyspray/task/318 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task is now closed: FS#307 - MIPS breaks in O3!... (branch pred.???) User who did this: - Korey Sewell (ksewell) Reason for closing: - Works for me Additional comments about closing: - Hello regression for MIPS-O3 already committed in tree as well as other commits from m5users that address floating point double register allocation for MIPS-O3 runs. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/307 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task is now closed: FS#319 - No point in having thread contexts with no workload in SE mode User who did this: - Korey Sewell (ksewell) Reason for closing: - Not a bug Additional comments about closing: - Dynamic thread creation in InOrder as well as the future of that in O3 makes this irrelevant. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/319 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task is now closed: FS#197 - Fail outstanding SC on invalidation User who did this: - Steve Reinhardt (stever) Reason for closing: - Fixed Additional comments about closing: - Fixed in cset f97b62be544f. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/197 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task is now closed: FS#329 - SWIG warning in stats code User who did this: - Nathan Binkert (nate) Reason for closing: - Fixed Additional comments about closing: - Renamed print to display More information can be found at the following URL: http://www.m5sim.org/flyspray/task/329 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task is now closed: FS#70 - Dictionary-based coherence User who did this: - Steve Reinhardt (stever) Reason for closing: - Implemented Additional comments about closing: - Taken care of by Ruby integration. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/70 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task is now closed: FS#89 - Add an actual compressed main memory User who did this: - Steve Reinhardt (stever) Reason for closing: - Won't implement Additional comments about closing: - This is a research project, not a core feature. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/89 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task is now closed: FS#87 - Add more compression algs from the literature User who did this: - Steve Reinhardt (stever) Reason for closing: - Won't implement Additional comments about closing: - Compression support is gone from the cache now. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/87 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task is now closed: FS#86 - Add some MP interconnect models User who did this: - Steve Reinhardt (stever) Reason for closing: - Implemented Additional comments about closing: - Taken care of with Ruby/Garnet integration. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/86 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task is now closed: FS#81 - Add support for dynamic partitioning of the IIC User who did this: - Steve Reinhardt (stever) Reason for closing: - Won't implement Additional comments about closing: - IIC is deprecated. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/81 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task is now closed: FS#80 - Add support for static partioning of the IIC User who did this: - Steve Reinhardt (stever) Reason for closing: - Won't implement Additional comments about closing: - IIC is deprecated. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/80 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task is now closed: FS#79 - Rework current IIC to exact model, add a fast model User who did this: - Steve Reinhardt (stever) Reason for closing: - Won't implement Additional comments about closing: - IIC is deprecated. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/79 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task is now closed: FS#18 - support PowerPC ISA User who did this: - Steve Reinhardt (stever) Reason for closing: - Implemented Additional comments about closing: - Done, thanks to Timothy Jones. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/18 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task is now closed: FS#99 - MSHRs return wrong outstanding miss count User who did this: - Steve Reinhardt (stever) Reason for closing: - Not a bug Additional comments about closing: - I'm sure the code this is referring to is long gone. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/99 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. A new Flyspray task has been opened. Details are below. User who did this: - Steve Reinhardt (stever) Attached to Project - M5 Bugs Summary - Regressions no longer retry on user kill Task Type - Bug Category - Testing Status - New Assigned To - Operating System - All Severity - Medium Priority - Normal Reported Version - 2.0beta5 Due in Version - Due Date - Undecided Details - There's some code I added to tests/SConscript that intentionally avoids creating the 'status' output file if m5 terminates with one of a certain set of signals such as SIGINT. (Grep for retry_signals in that file to see where.) Without this code, premature termination of m5 counts as a test failure (as is often appropriate, e.g., if you hit an assertion failure or SIGSEGV). The intended effect here is that if you ^C a regression test for some reason then restart it, it will re-run the test automatically, rather than reporting a failed test and requiring you to go delete the output files to force scons to re-run it. This used to work (I know it did when I added this code in March 2009, see http://repo.m5sim.org/m5/rev/e0344c15e73b). It doesn't anymore; I just ^C'd a regression and got the old behavior. I suspect the interrupt return code is getting lost in the transition from C++ to Python, but a quick skim doesn't turn up any changes since then that would look suspicious, and I don't have time to dig into this right now. Anything come to mind, Nate? More information can be found at the following URL: http://www.m5sim.org/flyspray/task/330 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. A new Flyspray task has been opened. Details are below. User who did this: - Steve Reinhardt (stever) Attached to Project - M5 Bugs Summary - SWIG warning in ARM code Task Type - Bug Category - ISA Support Status - Assigned Assigned To - Nathan Binkert Operating System - All Severity - Low Priority - Normal Reported Version - 2.0beta5 Due in Version - Due Date - Undecided Details - With SWIG 1.3.36, compiling ARM_SE gives this warning: swig -c++ -python -modern -templatereduce -Ibuild/gzstream -Ibuild/libelf -Iext -I/usr/include/python2.6 -Ibuild/ARM_SE -I/home/stever/hg/m5sim.org/encumbered -outdir build/ARM_SE/python/swig -o build/ARM_SE/python/swig/stats_wrap.cc build/ARM_SE/python/swig/stats.i build/ARM_SE/base/stats/info.hh:47: Warning(314): 'print' is a python keyword, renaming to '_print' More information can be found at the following URL: http://www.m5sim.org/flyspray/task/329 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task has been changed. The new details are below. For full information about what has changed, visit the URL and click the History tab. FS#329 - SWIG warning in ARM code User who did this: - Steve Reinhardt (stever) Attached to Project - M5 Bugs Summary - SWIG warning in ARM code Task Type - Bug Category - ISA Support Status - Assigned Assigned To - Nathan Binkert Operating System - All Severity - Low Priority - Normal Reported Version - 2.0beta5 Due in Version - Due Date - Undecided Percent Complete - 0% Details - SWIG (versions 1.3.33 and 1.3.36, at least) gives this warning (on any build, ARM_SE shown here as exmaple): swig -c++ -python -modern -templatereduce -Ibuild/gzstream -Ibuild/libelf -Iext -I/usr/include/python2.6 -Ibuild/ARM_SE -I/home/stever/hg/m5sim.org/encumbered -outdir build/ARM_SE/python/swig -o build/ARM_SE/python/swig/stats_wrap.cc build/ARM_SE/python/swig/stats.i build/ARM_SE/base/stats/info.hh:47: Warning(314): 'print' is a python keyword, renaming to '_print' More information can be found at the following URL: http://www.m5sim.org/flyspray/task/329 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task has been changed. The new details are below. For full information about what has changed, visit the URL and click the History tab. FS#329 - SWIG warning in stats code User who did this: - Steve Reinhardt (stever) Attached to Project - M5 Bugs Summary - SWIG warning in stats code Task Type - Bug Category - ISA Support Status - Assigned Assigned To - Nathan Binkert Operating System - All Severity - Low Priority - Normal Reported Version - 2.0beta5 Due in Version - Due Date - Undecided Percent Complete - 0% Details - SWIG (versions 1.3.33 and 1.3.36, at least) gives this warning (on any build, ARM_SE shown here as exmaple): swig -c++ -python -modern -templatereduce -Ibuild/gzstream -Ibuild/libelf -Iext -I/usr/include/python2.6 -Ibuild/ARM_SE -I/home/stever/hg/m5sim.org/encumbered -outdir build/ARM_SE/python/swig -o build/ARM_SE/python/swig/stats_wrap.cc build/ARM_SE/python/swig/stats.i build/ARM_SE/base/stats/info.hh:47: Warning(314): 'print' is a python keyword, renaming to '_print' More information can be found at the following URL: http://www.m5sim.org/flyspray/task/329 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. A new Flyspray task has been opened. Details are below. User who did this: - Ali Saidi (saidi) Attached to Project - M5 Bugs Summary - Bitfield definitions in ARM ISA Task Type - Bug Category - ISA Support Status - New Assigned To - Gabe Black Operating System - All Severity - Medium Priority - Normal Reported Version - 2.0beta5 Due in Version - 2.1 Due Date - 2010-07-31 Details - Steve Reinhardt: I do see lots of repeated definitions of rn, rd, and rm. Also for other fields like lsb, msb, rotation, that are defined in multiple places (e.g., 2 out of 3 branches of an if/else if tree) I'd prefer to see them defined at the top in a common place; I don't think that avoiding extracting them in the one case where they're not needed is a real performance issue. If our decode cache isn't broken then actual from-scratch decode should not be a performance issue at all. I had a couple of other ideas: 1. Maybe we should define bits() as a method on ExtMachInst, so we can say machInst.bits(X,Y). That's not a huge win by itself, but if we couple it with getting rid of def bitfield and have bitfields in the ISA language be attributes on the ExtMachInst, then you could even say decode bits(5,3) right in the ISA language. 2. We could extend bits() to take multiple pairs of bit indices, concatenating the indicated ranges, so expressions like: timm = (bits(machInst, 19, 16) 12) | bits(machInst, 11, 0); could be rewritten as: timm = machInst.bits(19, 16, 11, 0); I think #2 would even be useful in converting some of your if/else if structures back to switches, which I find preferable because they make it clear(er) that you've covered all the possible cases. Gabe Black wrote: I've had thoughts similar to these. For instance, it would be nice to add a function to either the ExtMachInst (or the StaticInst) that would return an IntRegIndex from a set of bits. That would get rid of some of the stacks of casts that tend to happen around register indexes. It wouldn't be that bad (knock on wood) to add new types of bitfields to BitUnions that would do arbitrarily complex things when reading or writing bits. The problem is that they'd need to be set up first, and if they only show up once or twice the overhead makes them a lot more verbose than just calling bits directly. I'd be fine with moving the common definitions to the tops of the blocks they're used in. The thing to watch out for is bitfields that are -almost- the same but that are changed around sometimes. There are instances of that and they have caused some bugs. While these sorts of extensions are a good idea and would clean things up even outside of ARM in some places, they won't remove all instances of having to do things the hard way because there are plenty of places where the bits of interest shift for what seems like (or literaly is) every different instruction in a group, or where things are combined like bit a == bit b, or a == 1 and b != 010. It's sort of a mess. Steve Reinhardt: I'm still not very happy with all the redundant bitfield stuff, even if it is caused by IntRegIndex casting issues. (It looks like the big problem is that IntRegIndex is an enum rather than an integer type... is there a big benefit from that? Clearly the cost is pretty high, in my opinion. Why not replace it with a typedef to an integer type and a bunch of constants, maybe in their own Arm::IntReg namespace if that helps?) I'd also like to see the extended bits() notation (or something similar) that concatenates bitfields, e.g., replacing expressions like: (bits(data, 15) 2) | bits(data,11,10) with: bits(data, 15, 15, 11, 10) (or something similar... I'm open to ideas for better syntax). This makes it more obvious that the bitfields are being concatenated and avoids the magic '2' that really represents the width of bits(_, 11, 10) without being obvious about that. There are even cases where another shift gets folded in that are more confusing; for example, I think this: (bits(machInst, 9) 6) | (bits(machInst, 7, 3) 1) is much less clear than: bits(machInst, 9, 9, 7, 3) 1 More information can be found at the following URL: http://www.m5sim.org/flyspray/task/328 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. A new Flyspray task has been opened. Details are below. User who did this: - Gabe Black (gblack) Attached to Project - M5 Bugs Summary - Improve handling of the FSR in SPARC. Task Type - Minor Enhancement Category - ISA Support Status - Assigned Assigned To - Gabe Black Operating System - All Severity - Low Priority - Normal Reported Version - 2.0beta5 Due in Version - Due Date - Undecided Details - SPARC's FSR controls floating point operations and also tracks floating point condition codes. The register should probably be split into a control register and an integer register for the condition codes. That way the condition codes would be renameable like the integer ones, and instructions that set them won't be serializing. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/327 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task is now closed: FS#293 - Fix division corner case User who did this: - Gabe Black (gblack) Reason for closing: - Fixed More information can be found at the following URL: http://www.m5sim.org/flyspray/task/293 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task is now closed: FS#297 - Make the x86 page table walker run when there is a miss, not through a fault User who did this: - Gabe Black (gblack) Reason for closing: - Fixed More information can be found at the following URL: http://www.m5sim.org/flyspray/task/297 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task has been changed. The new details are below. For full information about what has changed, visit the URL and click the History tab. FS#294 - Clean up and refactor dprintfs for SPARC and x86 User who did this: - Gabe Black (gblack) Attached to Project - M5 Bugs Summary - Clean up and refactor dprintfs for SPARC and x86 Task Type - Minor Enhancement Category - CPU Status - New Assigned To - Gabe Black Operating System - All Severity - Low Priority - Normal Reported Version - 2.0beta3 Due in Version - Due Date - Undecided Percent Complete - 70% Details - The OS specific trace flags for SPARC and x86 are currently grouped into generic Sparc and X86 traceflags. They should be split into more specialized flags and be shared consistently between ISAs. This is mostly complete, but a few uses of both traceflags could still be generalized. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/294 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task is now closed: FS#314 - Make the x86 predecoder set the default segment to SS appropriately User who did this: - Gabe Black (gblack) Reason for closing: - Fixed More information can be found at the following URL: http://www.m5sim.org/flyspray/task/314 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task has been changed. The new details are below. For full information about what has changed, visit the URL and click the History tab. FS#306 - Mixie CPU Model - M5 In-Order CPU Model User who did this: - Korey Sewell (ksewell) Attached to Project - M5 Bugs Summary - Mixie CPU Model - M5 In-Order CPU Model Task Type - Major Feature Category - CPU Status - New Assigned To - Korey Sewell Operating System - All Severity - Low Priority - Normal Reported Version - 2.0beta3 Due in Version - Due Date - Undecided Percent Complete - 100% Details - Integrate mixie cpu model into base M5 code as a inorder cpu model... More information can be found at the following URL: http://www.m5sim.org/flyspray/task/306 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task is now closed: FS#306 - Mixie CPU Model - M5 In-Order CPU Model User who did this: - Korey Sewell (ksewell) Reason for closing: - Implemented More information can be found at the following URL: http://www.m5sim.org/flyspray/task/306 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task has been changed. The new details are below. For full information about what has changed, visit the URL and click the History tab. FS#223 - Get distributed scons to work with lsf User who did this: - Gabe Black (gblack) Attached to Project - M5 Bugs Summary - Get distributed scons to work with lsf Task Type - Minor Enhancement Category - CPU Status - New Assigned To - Nathan Binkert Operating System - All Severity - Low Priority - Normal Reported Version - 1.1 Due in Version - Due Date - Undecided Percent Complete - 0% Details - Get distributed scons to work with lsf so it can be used at HP. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/223 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task has been changed. The new details are below. For full information about what has changed, visit the URL and click the History tab. FS#224 - x86 support User who did this: - Gabe Black (gblack) Attached to Project - M5 Bugs Summary - x86 support Task Type - Major Feature Category - CPU Status - New Assigned To - Gabe Black Operating System - All Severity - Low Priority - Normal Reported Version - 1.1 Due in Version - Due Date - Undecided Percent Complete - 50% Details - x86 support More information can be found at the following URL: http://www.m5sim.org/flyspray/task/224 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task is now closed: FS#227 - Automate microcode generation in isa_parser.py User who did this: - Gabe Black (gblack) Reason for closing: - Implemented More information can be found at the following URL: http://www.m5sim.org/flyspray/task/227 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task is now closed: FS#230 - x86 segmentation support User who did this: - Gabe Black (gblack) Reason for closing: - Implemented More information can be found at the following URL: http://www.m5sim.org/flyspray/task/230 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task is now closed: FS#277 - Make a pair of formats for x86 which are legal only in or not in 64 bit mode User who did this: - Gabe Black (gblack) Reason for closing: - Won't implement Additional comments about closing: - This is now done in the decoder. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/277 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task is now closed: FS#320 - O3 ISA-specific code needs refactoring User who did this: - Gabe Black (gblack) Reason for closing: - Fixed More information can be found at the following URL: http://www.m5sim.org/flyspray/task/320 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task has a new comment added: FS#306 - Mixie CPU Model - M5 In-Order CPU Model User who did this: - Korey Sewell (ksewell) -- Added to M5 Development tree as Inorder model. Support ALPHA and MIPS currently. Added Alpha regressions for hello, twolf, and vortex Added MIPS regresion for hello. -- More information can be found at the following URL: http://www.m5sim.org/flyspray/task/306#comment158 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task has been changed. The new details are below. For full information about what has changed, visit the URL and click the History tab. FS#306 - Mixie CPU Model - M5 In-Order CPU Model User who did this: - Korey Sewell (ksewell) Attached to Project - M5 Bugs Summary - Mixie CPU Model - M5 In-Order CPU Model Task Type - Major Feature Category - CPU Status - New Assigned To - Korey Sewell Operating System - All Severity - Low Priority - Normal Reported Version - 2.0beta3 Due in Version - Due Date - Undecided Percent Complete - 100% Details - Integrate mixie cpu model into base M5 code as a inorder cpu model... More information can be found at the following URL: http://www.m5sim.org/flyspray/task/306 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task is now closed: FS#315 - Python doesn't panic when parameter with no default isn't set User who did this: - Ali Saidi (saidi) Reason for closing: - Fixed Additional comments about closing: - in rev 2831ae658bfc More information can be found at the following URL: http://www.m5sim.org/flyspray/task/315 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task has been changed. The new details are below. For full information about what has changed, visit the URL and click the History tab. FS#315 - Python doesn't panic when parameter with no default isn't set User who did this: - Nathan Binkert (nate) Attached to Project - M5 Bugs Summary - Python doesn't panic when parameter with no default isn't set Task Type - Bug Category - Configuration Status - Assigned Assigned To - Nathan Binkert Operating System - All Severity - Critical Priority - Normal Reported Version - 2.0beta5 Due in Version - 2.0 release Due Date - Undecided Percent Complete - 0% Details - A parameter that doesn't have a default value isn't caught in the configuration stage. The parameter isn't printed in the ini and the value is undefined in the C++ struct. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/315 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. A new Flyspray task has been opened. Details are below. User who did this: - Ali Saidi (saidi) Attached to Project - M5 Bugs Summary - glibc reads /proc/meminfo and that can effect simulation Task Type - Bug Category - Global/Other Status - New Assigned To - Operating System - All Severity - High Priority - Normal Reported Version - 2.0beta5 Due in Version - Due Date - Undecided Details - The 20.parser benchmark tends to fail because glibc reads /proc/meminfo to determine how much memory is available in the system. qsort() uses that information to choose an algorithm to use thus depending on the host system, the guest can make a different choice. Ultimately, we need to provide a fake /proc/meminfo on open() syscalls that either has some generic info or better yet has the correct information for the simulated system. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/326 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task is now closed: FS#168 - fix m5term in MacOS User who did this: - Ali Saidi (saidi) Reason for closing: - Implemented More information can be found at the following URL: http://www.m5sim.org/flyspray/task/168 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task is now closed: FS#291 - Include hg hash/version number if available in build and print it out when executing User who did this: - Ali Saidi (saidi) Reason for closing: - Implemented More information can be found at the following URL: http://www.m5sim.org/flyspray/task/291 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task is now closed: FS#110 - Tru64/Tsunami boot User who did this: - Nathan Binkert (nate) Reason for closing: - Won't implement Additional comments about closing: - This just isn't going to happen More information can be found at the following URL: http://www.m5sim.org/flyspray/task/110 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. A new Flyspray task has been opened. Details are below. User who did this: - Ali Saidi (saidi) Attached to Project - M5 Bugs Summary - Clean-up CPU statistics Task Type - Bug Category - CPU Status - New Assigned To - Operating System - All Severity - High Priority - High Reported Version - 2.0beta5 Due in Version - Due Date - Undecided Details - The CPU statistics are a big messy. In the O3 cpu it's not clear what is for what and in the SimpleCPU I think the idle time is still calculated incorrectly (when a switchover occurs). In both cases quiesce instructions aren't handled in a good way. It's difficult to figure out which statistics are idle because the CPU was blocked doing something and which are the CPU was idle because it was put to sleep. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/323 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY.
A new Flyspray task has been opened. Details are below.
User who did this: - Steve Reinhardt (stever)
Attached to Project - M5 Bugs
Summary - Dynamic thread creation in O3 is broken
Task Type - Bug
Category - CPU
Status - New
Assigned To - Korey Sewell
Operating System - All
Severity - Medium
Priority - Normal
Reported Version - 2.0beta5
Due in Version -
Due Date - Undecided
Details - Although there's code to allow new threads to be created on
the fly in O3, there are multiple bugs that prevent it from working.
The basic idea is that O3ThreadContextImpl::activate() in
src/cpu/o3/thread_context_impl.hh checks to make sure there are enough
resources to activate an additional thread if the thread's status is
Unallocated. (Threads that are in the Suspended state are assumed to
already be holding the needed resources and just need to be woken up.)
This check is done by calling FullO3CPUImpl::activateWhenReady() in
src/cpu/o3/cpu.cc, which returns a bool indicating whether the
resources are available. However this test is broken in at least two
ways:
1. All the comparisons in this function are backwards ('=' should be
'' in each if)
2. LSQImpl::numFreeEntries() is broken in that it calculates the
total free entries by summing up the free entries for each active
thread, which means that if there are no active threads it returns
0... so if there are no active threads, you cannot activate the first
thread since there never appear to be any free LSQ entries for it.
I think this second bug is symptomatic of some deeper thinking that
needs to take place... for example, most of the SMT resources have
multiple allocation policies (Dynamic, Partitioned, and Threshold),
and whether or not there are enough resources available for a new
thread would seem to depend on the policy, but the activateWhenReady()
and numFreeEntries() functions are independent of that policy setting.
More information can be found at the following URL:
http://www.m5sim.org/flyspray/task/317
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THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task has a new comment added: FS#317 - Dynamic thread creation in O3 is broken User who did this: - Steve Reinhardt (stever) -- Here's a patch; apply this and run configs/splash2/run.py -d -n 4 -b OceanContig to see the problem. --- a/src/cpu/o3/alpha/cpu_impl.hh Sat Jun 21 14:23:58 2008 -0400 +++ b/src/cpu/o3/alpha/cpu_impl.hh Wed Jun 25 07:48:46 2008 -0700 @@ -74,7 +74,7 @@ AlphaO3CPUImpl::AlphaO3CPU(Params *par i, this-thread[i]); this-thread[i] = new Thread(this, i, params-workload[i], i); -this-thread[i]-setStatus(ThreadContext::Suspended); +this-thread[i]-setStatus(ThreadContext::Unallocated); //usedTids[i] = true; //threadMap[i] = i; -- More information can be found at the following URL: http://www.m5sim.org/flyspray/task/317#comment157 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. A new Flyspray task has been opened. Details are below. User who did this: - Steve Reinhardt (stever) Attached to Project - M5 Bugs Summary - O3 ISA-specific code needs refactoring Task Type - Minor Enhancement Category - CPU Status - New Assigned To - Operating System - All Severity - Medium Priority - Normal Reported Version - 2.0beta5 Due in Version - Due Date - Undecided Details - If you look in src/cpu/o3/*/* there are 1200-1800 lines of code in each directory, and I'd guess at least 600-800 lines in each of those is the same (or should be the same, or is trivially different) in each one. We should push all the common code we can up into the ISA-independent src/cpu/o3 code. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/320 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task is now closed: FS#272 - Make the x86 predecoder calculate the correct address size User who did this: - Gabe Black (gblack) Reason for closing: - Fixed More information can be found at the following URL: http://www.m5sim.org/flyspray/task/272 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. A new Flyspray task has been opened. Details are below. User who did this: - Gabe Black (gblack) Attached to Project - M5 Bugs Summary - Make the x86 predecoder set the default segment to SS appropriately Task Type - Bug Category - ISA Support Status - New Assigned To - Gabe Black Operating System - All Severity - Low Priority - Normal Reported Version - 2.0beta5 Due in Version - 2.1 Due Date - Undecided Details - Currently, the predecoder sets the default segment to DS always. The manual says it should be SS if rSP or rBP are used as base registers or if values are pushed/popped from the stack. It's ambiguous what they mean when about rSP and rBP being used as bases. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/314 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. A new Flyspray task has been opened. Details are below. User who did this: - Ali Saidi (saidi) Attached to Project - M5 Bugs Summary - Python doesn't panic when parameter with no default isn't set Task Type - Bug Category - Configuration Status - New Assigned To - Operating System - All Severity - High Priority - Normal Reported Version - 2.0beta5 Due in Version - 2.0 release Due Date - Undecided Details - A parameter that doesn't have a default value isn't caught in the configuration stage. The parameter isn't printed in the ini and the value is undefined in the C++ struct. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/315 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task is now closed: FS#185 - get flyspray to send emails to m5-dev when new tasks are created User who did this: - Ali Saidi (saidi) Reason for closing: - Fixed Additional comments about closing: - Seems to be fixed More information can be found at the following URL: http://www.m5sim.org/flyspray/task/185 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Task Tracker
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task is now closed: FS#254 - packet is timing request is rejected by the recipient the bus still waits the entire transfer time User who did this: - Ali Saidi (saidi) Reason for closing: - Not a bug More information can be found at the following URL: http://www.m5sim.org/flyspray/task/254 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task has been changed. The new details are below. For full information about what has changed, visit the URL and click the History tab. FS#291 - Include hg hash/version number if available in build and print it out when executing User who did this: - Ali Saidi (saidi) Attached to Project - M5 Bugs Summary - Include hg hash/version number if available in build and print it out when executing Task Type - Minor Enhancement Category - Global/Other Status - New Assigned To - Operating System - All Severity - High Priority - Normal Reported Version - 2.0beta3 Due in Version - Due Date - Undecided Percent Complete - 0% Details - I think this is almost a must have when we release the source code to the world. If we get a random bit of output this is a good way to know what version it came from. Perhaps we want both current version and last upstream version although I don't exactly know how that could be found. Additionally, there have been a couple of times when I wanted to know what version this particular binary came from More information can be found at the following URL: http://www.m5sim.org/flyspray/task/291 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Task Tracker
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task is now closed: FS#309 - test... do we get an email? User who did this: - Ali Saidi (saidi) Reason for closing: - Not a bug More information can be found at the following URL: http://www.m5sim.org/flyspray/task/309 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task has a new comment added: FS#75 - Make WH64 work under coherence User who did this: - Ali Saidi (saidi) -- I don't know if this is a bug anymore? Steve? -- More information can be found at the following URL: http://www.m5sim.org/flyspray/task/75#comment149 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task has been changed. The new details are below. For full information about what has changed, visit the URL and click the History tab. FS#91 - Add DPRINTFs for trace addr and marked requests User who did this: - Ali Saidi (saidi) Attached to Project - M5 Bugs Summary - Add DPRINTFs for trace addr and marked requests Task Type - Minor Enhancement Category - Memory System Status - Unconfirmed Assigned To - Ron Dreslinski Operating System - All Severity - Medium Priority - Normal Reported Version - head Due in Version - 2.1 Due Date - Undecided Percent Complete - 10% Details - Add debugging support for a trace address for the hierarchy and marked requests. This should aid in tracking an address through the hierarchy (or a specific request) making debugging easier. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/91 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
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THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task has been changed. The new details are below. For full information about what has changed, visit the URL and click the History tab. FS#134 - jobs scripts fail if no groups aren't required for a checkpoint User who did this: - Ali Saidi (saidi) Attached to Project - M5 Bugs Summary - jobs scripts fail if no groups aren't required for a checkpoint Task Type - Bug Category - Utilities Status - Unconfirmed Assigned To - Nathan Binkert Operating System - All Severity - Medium Priority - Normal Reported Version - head Due in Version - Due Date - Undecided Percent Complete - 0% Details - The job scripts fail to pass the checkpoint parameter to a run if none of the specified groups are required for a checkpoint, or if no checkpoints are needed at all, or if there are no shared checkpoints. Workaround: add a null group that does nothing. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/134 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
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THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task has a new comment added: FS#208 - Implement Atomic Sparc Memory operations User who did this: - Ali Saidi (saidi) -- This has been implemented for the caches. I don't know if it's implemented for the o3 -- More information can be found at the following URL: http://www.m5sim.org/flyspray/task/208#comment152 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task has been changed. The new details are below. For full information about what has changed, visit the URL and click the History tab. FS#251 - valgrind detects two errors User who did this: - Ali Saidi (saidi) Attached to Project - M5 Bugs Summary - valgrind detects two errors Task Type - Bug Category - Testing Status - New Assigned To - Operating System - All Severity - Medium Priority - Normal Reported Version - 1.1 Due in Version - 2.0 Due Date - Undecided Percent Complete - 0% Details - Errors listed below... I can't see anything wrong with the code... ==24752== Conditional jump or move depends on uninitialised value(s) ==24752==at 0x4E9E21: AlphaISAInst::Addl::execute(TimingSimpleCPU*, Trace::InstRecord*) const (bitfield.hh:88) ==24752==by 0x736BFD: TimingSimpleCPU::completeIfetch(Packet*) (timing.cc:547) ==24752==by 0x9F2CD9: EventQueue::serviceOne() (eventq.cc:118) ==24752==by 0xA23491: simulate(long) (simulate.cc:72) ==24752==by 0xA3E532: _wrap_simulate (event_wrap.cc:3367) ==24752==by 0x4E63032: PyObject_Call (in /usr/lib/libpython2.5.so.1.0) ==24752==by 0x4EE1717: PyEval_EvalFrameEx (in /usr/lib/libpython2.5.so.1.0) ==24752==by 0x4EE4805: PyEval_EvalCodeEx (in /usr/lib/libpython2.5.so.1.0) ==24752==by 0x4EE2C1C: PyEval_EvalFrameEx (in /usr/lib/libpython2.5.so.1.0) ==24752==by 0x4EE3C43: PyEval_EvalFrameEx (in /usr/lib/libpython2.5.so.1.0) ==24752==by 0x4EE4805: PyEval_EvalCodeEx (in /usr/lib/libpython2.5.so.1.0) ==24752==by 0x4EE4841: PyEval_EvalCode (in /usr/lib/libpython2.5.so.1.0) ==24752== Conditional jump or move depends on uninitialised value(s) ==24752==at 0x873124: Uart8250::write(Packet*) (uart8250.cc:266) ==24752==by 0x8F28CB: SimpleTimingPort::recvTiming(Packet*) (tport.cc:64) ==24752==by 0x8C84B3: Bus::recvTiming(Packet*) (port.hh:189) ==24752==by 0x8CFAB8: Bus::BusPort::recvTiming(Packet*) (bus.hh:168) ==24752==by 0x8B4658: Bridge::BridgePort::trySend() (port.hh:189) ==24752==by 0x9F2CD9: EventQueue::serviceOne() (eventq.cc:118) ==24752==by 0xA23491: simulate(long) (simulate.cc:72) ==24752==by 0xA3E532: _wrap_simulate (event_wrap.cc:3367) ==24752==by 0x4E63032: PyObject_Call (in /usr/lib/libpython2.5.so.1.0) ==24752==by 0x4EE1717: PyEval_EvalFrameEx (in /usr/lib/libpython2.5.so.1.0) ==24752==by 0x4EE4805: PyEval_EvalCodeEx (in /usr/lib/libpython2.5.so.1.0) ==24752==by 0x4EE2C1C: PyEval_EvalFrameEx (in /usr/lib/libpython2.5.so.1.0) More information can be found at the following URL: http://www.m5sim.org/flyspray/task/251 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task has a new comment added: FS#262 - Make default parameters more reasonable User who did this: - Ali Saidi (saidi) -- Default latency is set to 1t still, however I did update regressions to use more reasonable values. -- More information can be found at the following URL: http://www.m5sim.org/flyspray/task/262#comment153 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task has been changed. The new details are below. For full information about what has changed, visit the URL and click the History tab. FS#268 - O3 LSQ needs coherence support User who did this: - Ali Saidi (saidi) Attached to Project - M5 Bugs Summary - O3 LSQ needs coherence support Task Type - Minor Enhancement Category - CPU Status - New Assigned To - Kevin Lim Operating System - All Severity - Medium Priority - Normal Reported Version - 2.0beta2 Due in Version - 2.1 Due Date - Undecided Percent Complete - 0% Details - For ISAs with stronger consistency models than Alpha, invalidates need to be processed by the O3 LSQ to detect forwarding situations that violate the consistency model and treat them as mispredicts. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/268 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task has been changed. The new details are below. For full information about what has changed, visit the URL and click the History tab. FS#270 - cache and bus reschedule on next tick instead of next clock User who did this: - Ali Saidi (saidi) Attached to Project - M5 Bugs Summary - cache and bus reschedule on next tick instead of next clock Task Type - Bug Category - Memory System Status - New Assigned To - Operating System - All Severity - Medium Priority - Normal Reported Version - 2.0beta2 Due in Version - 2.0 Due Date - Undecided Percent Complete - 0% Details - Lots of retry type events get scheduled at curTick+1 when they really should be scheduled for the next device clock edge (if not later). Requires adding the notion of a clock to the cache. Depends on new mechanism to be added for having per-object clocks. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/270 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
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THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task has been changed. The new details are below. For full information about what has changed, visit the URL and click the History tab. FS#290 - Make build_opts have target defined defines as well User who did this: - Ali Saidi (saidi) Attached to Project - M5 Bugs Summary - Make build_opts have target defined defines as well Task Type - Minor Enhancement Category - Global/Other Status - New Assigned To - Operating System - All Severity - Medium Priority - Normal Reported Version - 2.0beta3 Due in Version - 2.1 Due Date - Undecided Percent Complete - 0% Details - Currently the build_opts struct doesn't have the defines that come from the build name (e.g. m5.fast). This prevents us from sanity checking inputs like --trace= on a fast binary. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/290 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task has been changed. The new details are below. For full information about what has changed, visit the URL and click the History tab. FS#3 - error on running past end of EIO trace User who did this: - Ali Saidi (saidi) Attached to Project - M5 Bugs Summary - error on running past end of EIO trace Task Type - Bug Category - Global/Other Status - New Assigned To - Operating System - All Severity - Low Priority - Normal Reported Version - head Due in Version - Due Date - Undecided Percent Complete - 0% Details - M5 may silently do who knows what when running past eof on an EIO trace. From 12/11/03 mtg: Erik will try running off the end of an EIO trace again... now that we no longer ignore SIGPIPE we may get a signal instead of nothing. If not, need to figure out how to address this. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/3 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
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THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task has been changed. The new details are below. For full information about what has changed, visit the URL and click the History tab. FS#50 - Update statistics to use new models more efficiently User who did this: - Ali Saidi (saidi) Attached to Project - M5 Bugs Summary - Update statistics to use new models more efficiently Task Type - Minor Enhancement Category - Global/Other Status - Waiting on Customer Assigned To - Operating System - All Severity - Low Priority - Normal Reported Version - head Due in Version - Due Date - Undecided Percent Complete - 0% Details - Many average stats can be moved over to the new model more efficiently. Make better use of 2d vectors in the cache. Dependent on fixing Average stat. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/50 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
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THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task has been changed. The new details are below. For full information about what has changed, visit the URL and click the History tab. FS#73 - Snoop for hits in the write/victim buffer User who did this: - Ali Saidi (saidi) Attached to Project - M5 Bugs Summary - Snoop for hits in the write/victim buffer Task Type - Minor Enhancement Category - CPU Status - Unconfirmed Assigned To - Operating System - All Severity - Low Priority - Normal Reported Version - head Due in Version - Due Date - Undecided Percent Complete - 0% Details - Add support for satisfying/filling a block from the write/victim buffer for performance. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/73 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task has a new comment added: FS#73 - Snoop for hits in the write/victim buffer User who did this: - Ali Saidi (saidi) -- I imagine this is actually fixed at this point? I don't see how it couldn't be -- More information can be found at the following URL: http://www.m5sim.org/flyspray/task/73#comment155 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY.
The following task has been changed. The new details are below. For
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FS#151 - Make adding children an explicit operation in Python config
User who did this: - Ali Saidi (saidi)
Attached to Project - M5 Bugs
Summary - Make adding children an explicit operation in Python config
Task Type - Minor Enhancement
Category - Configuration
Status - New
Assigned To - Steve Reinhardt
Operating System - All
Severity - Low
Priority - Normal
Reported Version - 1.1
Due in Version -
Due Date - Undecided
Percent Complete - 0%
Details - I still find it dangerous that if we assign a SimObject to
an otherwise unknown attribute of another SimObject we assume we are
adding a child (as opposed to having mistyped the name of a
parameter). It doesn't seem like too big of a burden to say
foo.add_child('name', bar)
or something like that instead of the current foo.name = bar since
most children are added implicitly via parameter assignment anyway.
More information can be found at the following URL:
http://www.m5sim.org/flyspray/task/151
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[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. A new Flyspray task has been opened. Details are below. User who did this: - Ali Saidi (saidi) Attached to Project - M5 Bugs Summary - Integrated one of the many other DRAM models that have bene written for M5 Task Type - Minor Enhancement Category - Memory System Status - New Assigned To - Operating System - All Severity - Medium Priority - Normal Reported Version - 2.0beta5 Due in Version - Due Date - Undecided Details - There are a couple of people who have dram models that are better than the one we have in m5... we should do something about this. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/311 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task has been changed. The new details are below. For full information about what has changed, visit the URL and click the History tab. FS#180 - Fix byte swapping User who did this: - Ali Saidi (saidi) Attached to Project - M5 Bugs Summary - Fix byte swapping Task Type - Bug Category - Memory System Status - New Assigned To - Nathan Binkert Operating System - All Severity - Low Priority - Normal Reported Version - 1.1 Due in Version - 2.1 Due Date - Undecided Percent Complete - 0% Details - Currently, the memory system get()/set() accessor methods use the endianness of TheISA to determine what byte swapping should be done. This is incorrect since one, it can't possibly let heterogeneous systems work; two, the memory system really doesn't care what the endianness is; and three, will break for the cases where device drivers do the byte swapping, expecting the device to have a fixed endianness. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/180 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task has been changed. The new details are below. For full information about what has changed, visit the URL and click the History tab. FS#182 - refactor Fault object classes User who did this: - Ali Saidi (saidi) Attached to Project - M5 Bugs Summary - refactor Fault object classes Task Type - Minor Enhancement Category - ISA Support Status - New Assigned To - Gabe Black Operating System - All Severity - Low Priority - Normal Reported Version - 1.1 Due in Version - Due Date - Undecided Percent Complete - 0% Details - Too much redundancy in all the Fault class definitions in arch/*/faults.hh. Looks like it might be a job for the Curiously Recurring Template Pattern. If that doesn't pan out, even a #define would be better than what's there now. Also, all the derived classes should just be in the .cc files, with only declarations of the functions (e.g. genFooFault()) in the header. No need to include all those class definitions all over the place when the whole point is that they are hidden behind the generic fault base class. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/182 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task has been changed. The new details are below. For full information about what has changed, visit the URL and click the History tab. FS#196 - Make Checker handle multiple threads User who did this: - Ali Saidi (saidi) Attached to Project - M5 Bugs Summary - Make Checker handle multiple threads Task Type - Minor Enhancement Category - CPU Status - New Assigned To - Kevin Lim Operating System - All Severity - Low Priority - Normal Reported Version - 1.1 Due in Version - Due Date - Undecided Percent Complete - 0% Details - Checker right now is only single threaded, and gives no warnings about being used in an SMT context (in fact it just gives a hard to hunt down configuration error). It's probably not too hard to make it multithreaded. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/196 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task has been changed. The new details are below. For full information about what has changed, visit the URL and click the History tab. FS#217 - SPARC fault priorities User who did this: - Ali Saidi (saidi) Attached to Project - M5 Bugs Summary - SPARC fault priorities Task Type - Bug Category - CPU Status - New Assigned To - Lisa Hsu Operating System - All Severity - Low Priority - Normal Reported Version - 1.1 Due in Version - 2.1 Due Date - Undecided Percent Complete - 0% Details - I don't know how much we need to worry about this, but instruction tlb misses are higher priority than interrupts I put some code like if (curTick == X) return NoFault; in interrupts to make M5 line up with legion in this regard. The problem is we get the interrupt faults and the tlb faults in different places (interrupt first currently). Once we get the interrupt fault we can't undo that. (The interrupt controller thinks its been handled now). So we need to split this up into a getInterrutp() and then handleInterrupt() which actually marks that interrupt as taken or something. I don't know how the detailed cpu handles interrupts as well. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/217 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task has been changed. The new details are below. For full information about what has changed, visit the URL and click the History tab. FS#221 - Perlbmk o3 regression fails User who did this: - Ali Saidi (saidi) Attached to Project - M5 Bugs Summary - Perlbmk o3 regression fails Task Type - Bug Category - CPU Status - New Assigned To - Kevin Lim Operating System - All Severity - Low Priority - Normal Reported Version - 1.1 Due in Version - Due Date - Undecided Percent Complete - 0% Details - The o3 perlbmk regression fails when a longjmp syscall doesn't transfer control to where setjmp was called. The function continues to execute which causes it to enter error handling code, and that code uses an unimplemented syscall. The regression also fails with the smred input set which could let you get to the failure sooner. The syscall itself works in the simple cpus, so the problem most likely lies in o3. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/221 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task has been changed. The new details are below. For full information about what has changed, visit the URL and click the History tab. FS#224 - x86 support User who did this: - Ali Saidi (saidi) Attached to Project - M5 Bugs Summary - x86 support Task Type - Major Feature Category - ISA Support Status - New Assigned To - Gabe Black Operating System - All Severity - Low Priority - Normal Reported Version - 1.1 Due in Version - 2.1 Due Date - Undecided Percent Complete - 20% Details - x86 support More information can be found at the following URL: http://www.m5sim.org/flyspray/task/224 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task has been changed. The new details are below. For full information about what has changed, visit the URL and click the History tab. FS#231 - Flatten floating point registers to support x87 floating point User who did this: - Ali Saidi (saidi) Attached to Project - M5 Bugs Summary - Flatten floating point registers to support x87 floating point Task Type - Minor Enhancement Category - ISA Support Status - New Assigned To - Gabe Black Operating System - All Severity - Low Priority - Normal Reported Version - 1.1 Due in Version - 2.1 Due Date - Undecided Percent Complete - 50% Details - Floating point register indexes need to be flattened or otherwise contextualized to support the stack semantics of x87 floating point. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/231 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task has been changed. The new details are below. For full information about what has changed, visit the URL and click the History tab. FS#238 - x86 doesn't seem to have the concept of a link register. User who did this: - Ali Saidi (saidi) Attached to Project - M5 Bugs Summary - x86 doesn't seem to have the concept of a link register. Task Type - Bug Category - ISA Support Status - New Assigned To - Gabe Black Operating System - All Severity - Low Priority - Normal Reported Version - 1.1 Due in Version - 2.1 Due Date - Undecided Percent Complete - 0% Details - Since x86 relies heavily on the stack, it doesn't seem to use a link register. I'm not 100% sure about that. Code that relies on there being a link register will have to be fixed. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/238 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task has been changed. The new details are below. For full information about what has changed, visit the URL and click the History tab. FS#242 - Add 32 bit SPEC regressions for SPARC_SE User who did this: - Ali Saidi (saidi) Attached to Project - M5 Bugs Summary - Add 32 bit SPEC regressions for SPARC_SE Task Type - Minor Enhancement Category - Testing Status - New Assigned To - Gabe Black Operating System - All Severity - Low Priority - Normal Reported Version - 1.1 Due in Version - 2.1 Due Date - Undecided Percent Complete - 70% Details - Get the SPEC benchmarks working in the first place, and then create regressions for them. The test.pys for the various spec regressions need to be generalized away from Alpha using values from tests/run.py. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/242 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task has been changed. The new details are below. For full information about what has changed, visit the URL and click the History tab. FS#247 - branch predictor handles delay slots User who did this: - Ali Saidi (saidi) Attached to Project - M5 Bugs Summary - branch predictor handles delay slots Task Type - Minor Enhancement Category - CPU Status - New Assigned To - Gabe Black Operating System - All Severity - Low Priority - Normal Reported Version - 1.1 Due in Version - 2.1 Due Date - Undecided Percent Complete - 0% Details - Implement a branch predictor which can predict regular branches and delay branches in architectures which have delay slots. Right now, the predictor predicts a single target pc, and it's always interpreted as delayed by the fetch stage. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/247 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task has been changed. The new details are below. For full information about what has changed, visit the URL and click the History tab. FS#248 - expand microcode in the decode stage User who did this: - Ali Saidi (saidi) Attached to Project - M5 Bugs Summary - expand microcode in the decode stage Task Type - Minor Enhancement Category - CPU Status - New Assigned To - Gabe Black Operating System - All Severity - Low Priority - Normal Reported Version - 1.1 Due in Version - 2.1 Due Date - Undecided Percent Complete - 0% Details - Move the code which expands microcode from the fetch stage in o3 to the decode stage. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/248 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task has been changed. The new details are below. For full information about what has changed, visit the URL and click the History tab. FS#249 - Handle zero registers flexibly User who did this: - Ali Saidi (saidi) Attached to Project - M5 Bugs Summary - Handle zero registers flexibly Task Type - Minor Enhancement Category - CPU Status - New Assigned To - Gabe Black Operating System - All Severity - Low Priority - Normal Reported Version - 1.1 Due in Version - 2.1 Due Date - Undecided Percent Complete - 0% Details - Make TheISA::ZeroReg into a more generic concept. Kevin has suggested that there could be an index which specifically makes a register behave as a constant. In ISAs which have floating point or integer zero registers, the register remapping system could make the architected index map to the special constant index. Also, the cpus need to not constantly write zero into any register. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/249 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Notification from M5 Bugs
THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. The following task has been changed. The new details are below. For full information about what has changed, visit the URL and click the History tab. FS#250 - Revamp register handling mechanism User who did this: - Ali Saidi (saidi) Attached to Project - M5 Bugs Summary - Revamp register handling mechanism Task Type - Minor Enhancement Category - ISA Support Status - New Assigned To - Gabe Black Operating System - All Severity - Low Priority - Normal Reported Version - 1.1 Due in Version - 2.1 Due Date - Undecided Percent Complete - 0% Details - Currently, registers are either floating point, integer, or misc. This doesn't fit naturally in architectures like x86 which have multiple floating point register files, and any architecture which has microregisters could use a second integer register file. Also, some misc registers are more like integer registers and should be renamed. An idea would be to allow defining an arbitrary number and combination of register file interfaces. These interfaces would allow access to registers which were either integer, floating point, or control. The floating point registers would be basically the same as the integer, except that they would have floating point return values in the accessors. The control registers would actually perform control functions, unlike the msic regs which are a mixture. Each of these interfaces would map from a potentially aliased or sparse register space into a packed, unambiguous register space which would be handled by the cpu. The actual backing store would be implemented as part of the cpu and not as part of the ISA. The exec contexts of the cpu would allow an operation very similar to changing the register file context, but this would change parameters in the register file interfaces. That would allow a dynamic mapping from the architected register space to a logical one to implement concepts like register windows or pal shadow registers. It might also be a good idea for each of these interfaces to export a set of properties which would allow the cpu to handle them properly. For instance, all register files could specify that they have control registers and shouldn't be renamed rather than having a seperate control register file interface. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/250 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
