[m5-dev] [PATCH] SCons: Make --help reflect the arguments to scons
# HG changeset patch # User Gabe Black gbl...@eecs.umich.edu # Date 1262434350 18000 # Node ID 1b2fdc53c73cdd24dac772e38beed0d721200e3c # Parent 9e14a8c76257df063c65603e7a4001488f5e543f SCons: Make --help reflect the arguments to scons. The arguments were added to the global_sticky_vars Variables object after the basic help text was generated. As a result, the actual: value wouldn't reflect the arguments to scons and wouldn't really be the actual value used by the build. This change fixes that by updating global_sticky_vars slightly earlier. diff --git a/SConstruct b/SConstruct --- a/SConstruct +++ b/SConstruct @@ -324,11 +324,11 @@ Global sticky options: ''' -help_text += global_sticky_vars.GenerateHelpText(main) - # Update main environment with values from ARGUMENTS global_sticky_vars_file global_sticky_vars.Update(main) +help_text += global_sticky_vars.GenerateHelpText(main) + # Save sticky variable settings back to current variables file global_sticky_vars.Save(global_sticky_vars_file, main) ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] [PATCH 0 of 6] Get MIPS farther into double fp test programs.
These MIPS patches clean up two generic issues (rdhwr decoding, MIPS ISA object CPU pointer), improve the initial stack frame, and add support for thread local storage. The initial stack frame change was essentially moved over by Matt (originally from SPARC? Alpha?), and is currently credited just to Matt. Please let me know what you want the commit to say. I removed your comment about generalizing argsInit and generalized it like SPARC's version. Instead of putting the thread local storage pointer in the various contexts and routing it through all the CPUs and *Insts, contexts, etc., I added a new, artificial control register to MIPS. I used a register to associate it with a thread, but to the simulated code it should look like it's managed in software like it is in the Linux kernel. In SE mode the difference is basically irrelevant. Thes changes do -not- allow the fp-add-mips or add.d.mips64el test programs sent out by Matt and Vince to run, but do let them get farther before crashing. Right now it runs into the assert in fpNanOperands Matt identified earlier. To fix fpNanOperands, I think we're going to have to significantly change how that's set up. Right now, it goes through all the operands of the instruction and checks each one for nan assuming it's single precision. It also assumes it's floating point, I think, which seems a little dangerous. What will probably need to happen is to check each argument more explicitly, taking into account whether it's half of a double, etc. I'm not all that familiar with FP in MIPS or, off hand, how nan is encoded, so I could be wrong. After that we'll need the fpFilterDoubles function Matt moved over, and I think by that point double operands will be basically straightened out. As a nice side effect we should be able to run more modern binaries. Gabe ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] [PATCH 1 of 6] MIPS: Extract CPU pointer from the thread context in scheduleCP0 setMiscReg
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1262149471 18000
# Node ID 81e26ffe559669a2b5015b1ef7dc178ec7063d4f
# Parent aa9e72a7d8d3a57f60fdf717a49e0c0dba01c79f
MIPS: Extract CPU pointer from the thread context in scheduleCP0 setMiscReg.
The MIPS ISA object expects to be constructed with a CPU pointer it uses to
look at other thread contexts and allow them to be manipulated with control
registers. Unfortunately, that differs from all the other ISA classes and
would complicate their implementation.
This change makes the event constructor use a CPU pointer pulled out of the
thread context passed to setMiscReg instead.
diff --git a/src/arch/mips/isa.cc b/src/arch/mips/isa.cc
--- a/src/arch/mips/isa.cc
+++ b/src/arch/mips/isa.cc
@@ -91,12 +91,6 @@
init();
}
-ISA::ISA(BaseCPU *_cpu)
-{
-cpu = _cpu;
-init();
-}
-
void
ISA::init()
{
@@ -173,11 +167,10 @@
//@TODO: Use MIPS STYLE CONSTANTS (e.g. TCHALT_H instead of TCH_H)
void
ISA::reset(std::string core_name, ThreadID num_threads,
- unsigned num_vpes, BaseCPU *_cpu)
+ unsigned num_vpes, BaseCPU *cpu)
{
DPRINTF(MipsPRA, Resetting CP0 State with %i TCs and %i VPEs\n,
num_threads, num_vpes);
-cpu = _cpu;
MipsISA::CoreSpecific cp = cpu-coreParams;
@@ -499,7 +492,7 @@
miscRegFile[misc_reg][reg_sel] = cp0_val;
-scheduleCP0Update(1);
+scheduleCP0Update(tc-getCpuPtr(), 1);
}
/**
@@ -528,7 +521,7 @@
}
void
-ISA::scheduleCP0Update(int delay)
+ISA::scheduleCP0Update(BaseCPU *cpu, int delay)
{
if (!cp0Updated) {
cp0Updated = true;
@@ -540,7 +533,7 @@
}
void
-ISA::updateCPU()
+ISA::updateCPU(BaseCPU *cpu)
{
///
//
@@ -578,7 +571,7 @@
switch (cp0EventType)
{
case UpdateCP0:
-cp0-updateCPU();
+cp0-updateCPU(cpu);
break;
}
}
diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh
--- a/src/arch/mips/isa.hh
+++ b/src/arch/mips/isa.hh
@@ -64,18 +64,15 @@
std::vectorstd::vectorMiscReg miscRegFile_WriteMask;
std::vectorBankType bankType;
-BaseCPU *cpu;
-
public:
ISA();
-ISA(BaseCPU *_cpu);
void init();
void clear(unsigned tid_or_vpn = 0);
void reset(std::string core_name, ThreadID num_threads,
- unsigned num_vpes, BaseCPU *_cpu);
+ unsigned num_vpes, BaseCPU *cpu);
void expandForMultithreading(ThreadID num_threads, unsigned num_vpes);
@@ -147,11 +144,11 @@
};
// Schedule a CP0 Update Event
-void scheduleCP0Update(int delay = 0);
+void scheduleCP0Update(BaseCPU *cpu, int delay = 0);
// If any changes have been made, then check the state for changes
// and if necessary alert the CPU
-void updateCPU();
+void updateCPU(BaseCPU *cpu);
// Keep a List of CPU Events that need to be deallocated
std::queueCP0Event* cp0EventRemoveList;
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[m5-dev] [PATCH 2 of 6] MIPS: Create an artificial control register to hold the thread pointer
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1262149473 18000
# Node ID 1fb8f91df6587d350ab154a1116718a5cb0ebe19
# Parent 81e26ffe559669a2b5015b1ef7dc178ec7063d4f
MIPS: Create an artificial control register to hold the thread pointer.
In Linux, the set_thread_area system call stores the address of the thread
local storage area into a field of the current thread_info structure. Later,
to access that value, the program uses the rdhwr instruction to read a
hardware register with index 29. The 64 bit MIPS manual, volume II, says
that index 29 is reserved for a future ABI extension and should cause a
Reserved Instruction Exception. In Linux (and potentially other ISAs) that
exception is trapped and emulated to return the value stored by
set_thread_area as if that were actually stored by a physical register.
The tp_value address (as named in the Linux kernel) is ironically stored as a
control register so that it goes with a particular ThreadContext. Syscall
emulation will use that to emulate storing to the OS's thread info structure,
and rdhwr will emulate faulting and returning that value from software by
returning the value itself, as if it was in hardware. In other words, we fake
faking the register in SE mode. In an FS mode implementation it should
work as specified in the manual.
diff --git a/src/arch/mips/isa/operands.isa b/src/arch/mips/isa/operands.isa
--- a/src/arch/mips/isa/operands.isa
+++ b/src/arch/mips/isa/operands.isa
@@ -109,8 +109,11 @@
#LL Flag
'LLFlag': ('ControlReg', 'uw', 'MISCREG_LLFLAG', None, 1),
+#Thread pointer value for SE mode
+'TpValue': ('ControlReg', 'ud', 'MISCREG_TP_VALUE', None, 1),
+
# Index Register
-'Index':('ControlReg','uw','MISCREG_INDEX',None,1),
+'Index': ('ControlReg','uw','MISCREG_INDEX',None,1),
'CP0_RD_SEL': ('ControlReg', 'uw', '(RD 3 | SEL)', None, 1),
diff --git a/src/arch/mips/registers.hh b/src/arch/mips/registers.hh
--- a/src/arch/mips/registers.hh
+++ b/src/arch/mips/registers.hh
@@ -275,6 +275,7 @@
MISCREG_DESAVE = 248, //Bank 31: 248-256
MISCREG_LLFLAG = 257,
+MISCREG_TP_VALUE,
MISCREG_NUMREGS
};
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[m5-dev] [PATCH 4 of 6] MIPS: Fix decoding of the rdhwr instruction
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1262149473 18000
# Node ID a72cecae3e4bc51baa672d44e2682da47d0c1e6c
# Parent 7df34886ee2c03786587f858762a766468ef8d68
MIPS: Fix decoding of the rdhwr instruction.
diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa
--- a/src/arch/mips/isa/decoder.isa
+++ b/src/arch/mips/isa/decoder.isa
@@ -2476,10 +2476,8 @@
}
}
}
-0x3: decode OP_HI {
-0x2: decode OP_LO {
-0x3: FailUnimpl::rdhwr();
-}
+0x3: decode OP {
+0x0: FailUnimpl::rdhwr();
}
}
}
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[m5-dev] [PATCH 5 of 6] MIPS: Implement the SE mode version of rdhwr
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1262149473 18000
# Node ID e5980e0dc2dffa870b776341fddcbc2159571044
# Parent a72cecae3e4bc51baa672d44e2682da47d0c1e6c
MIPS: Implement the SE mode version of rdhwr.
diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa
--- a/src/arch/mips/isa/decoder.isa
+++ b/src/arch/mips/isa/decoder.isa
@@ -2477,7 +2477,13 @@
}
}
0x3: decode OP {
+#if FULL_SYSTEM
0x0: FailUnimpl::rdhwr();
+#else
+0x0: decode RD {
+29: BasicOp::rdhwr({{ Rt = TpValue; }});
+}
+#endif
}
}
}
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[m5-dev] [PATCH 00 of 31] Patches to clean up ARM and eliminate ISA register files
These patches first cleanup/restructure the ARM ISA description to make working on it easier, and to extend it slightly. Later patches eliminate ISA defined register files in favor of ISA defined register policies/semantics and CPU implemented register files. The MiscRegFile was subsumed by a new ISA object which will perform the same job. It will also allow stateful register index flattening, potentially parameterizing the ISA per CPU, and distinguishes regular old data registers from unrenamable, side effect carrying, ISA semantic implementing control registers. The idea behind the register file changes were detailed in a pdf sent to this list a while ago. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] [PATCH 01 of 31] ARM: Add operands for the load/store double instructions
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1247027877 25200
# Node ID 25e9fe47c844a1e59f9705fcd0844da1312ae0d0
# Parent b42cea5e16251b2f556271f17edb2f24a8998260
ARM: Add operands for the load/store double instructions.
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -47,22 +47,26 @@
'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3),
'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4),
-'Raddr': ('IntReg', 'uw', '17', 'IsInteger', 5),
-'Rhi': ('IntReg', 'uw', '18', 'IsInteger', 5),
-'Rlo': ('IntReg', 'uw', '19', 'IsInteger', 6),
-'LR': ('IntReg', 'uw', '14', 'IsInteger', 6),
+#Destination register for load/store double instructions
+'Rdo': ('IntReg', 'uw', '(RD ~1)', 'IsInteger', 4),
+'Rde': ('IntReg', 'uw', '(RD | 1)', 'IsInteger', 5),
+
+'Raddr': ('IntReg', 'uw', '17', 'IsInteger', 6),
+'Rhi': ('IntReg', 'uw', '18', 'IsInteger', 7),
+'Rlo': ('IntReg', 'uw', '19', 'IsInteger', 8),
+'LR': ('IntReg', 'uw', '14', 'IsInteger', 9),
#General Purpose Floating Point Reg Operands
-'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 1),
-'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 2),
-'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 3),
+'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 20),
+'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 21),
+'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 22),
#Memory Operand
-'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 8),
+'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 30),
-'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', 'IsInteger', 7),
-'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', 'IsInteger', 7),
-'NPC': ('NPC', 'uw', None, (None, None, 'IsControl'), 9),
-'NNPC': ('NNPC', 'uw', None, (None, None, 'IsControl'), 9),
+'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', 'IsInteger', 40),
+'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', 'IsInteger', 41),
+'NPC': ('NPC', 'uw', None, (None, None, 'IsControl'), 42),
+'NNPC': ('NNPC', 'uw', None, (None, None, 'IsControl'), 43),
}};
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[m5-dev] [PATCH 02 of 31] ARM: Add load/store double instructions
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1247028089 25200
# Node ID 6e5c26fe17ea449302c4e6357ee5ade8a0b2fc37
# Parent 25e9fe47c844a1e59f9705fcd0844da1312ae0d0
ARM: Add load/store double instructions.
diff --git a/src/arch/arm/isa/decoder.isa b/src/arch/arm/isa/decoder.isa
--- a/src/arch/arm/isa/decoder.isa
+++ b/src/arch/arm/isa/decoder.isa
@@ -184,35 +184,79 @@
}
format ArmLoadMemory {
0xd: decode PUBWL {
+0x0: ldrd_({{ Rde = bits(Mem.ud, 31, 0);
+ Rdo = bits(Mem.ud, 63, 32);
+ Rn = Rn - Rm; }},
+ {{ EA = Rn; }});
0x1: ldrsb_l({{ Rd = Mem.sb;
Rn = Rn - Rm; }},
{{ EA = Rn; }});
+0x4: ldrd_i({{ Rde = bits(Mem.ud, 31, 0);
+ Rdo = bits(Mem.ud, 63, 32);
+ Rn = Rn + hilo; }},
+{{ EA = Rn; }});
0x5: ldrsb_il({{ Rd = Mem.sb;
Rn = Rn + hilo; }},
{{ EA = Rn; }});
+0x8: ldrd_u({{ Rde = bits(Mem.ud, 31, 0);
+ Rdo = bits(Mem.ud, 63, 32);
+ Rn = Rn + Rm; }},
+{{ EA = Rn; }});
0x9: ldrsb_ul({{ Rd = Mem.sb;
Rn = Rn + Rm; }},
{{ EA = Rn; }});
+0xc: ldrd_ui({{ Rde = bits(Mem.ud, 31, 0);
+Rdo = bits(Mem.ud, 63, 32);
+Rn = Rn + hilo; }},
+ {{ EA = Rn; }});
0xd: ldrsb_uil({{ Rd = Mem.sb;
Rn = Rn + hilo; }},
{{ EA = Rn; }});
+0x10: ldrd_p({{ Rde = bits(Mem.ud, 31, 0);
+Rdo = bits(Mem.ud, 63, 32); }},
+ {{ EA = Rn - Rm; }});
0x11: ldrsb_pl({{ Rd = Mem.sb; }},
{{ EA = Rn - Rm; }});
+0x12: ldrd_pw({{ Rde = bits(Mem.ud, 31, 0);
+ Rdo = bits(Mem.ud, 63, 32);
+ Rn = Rn - Rm; }},
+ {{ EA = Rn - Rm; }});
0x13: ldrsb_pwl({{ Rd = Mem.sb;
Rn = Rn - Rm; }},
{{ EA = Rn - Rm; }});
+0x14: ldrd_pi({{ Rde = bits(Mem.ud, 31, 0);
+ Rdo = bits(Mem.ud, 63, 32); }},
+ {{ EA = Rn + hilo; }});
0x15: ldrsb_pil({{ Rd = Mem.sb; }},
{{ EA = Rn + hilo; }});
+0x16: ldrd_piw({{ Rde = bits(Mem.ud, 31, 0);
+ Rdo = bits(Mem.ud, 63, 32);
+ Rn = Rn + hilo; }},
+ {{ EA = Rn + hilo; }});
0x17: ldrsb_piwl({{ Rd = Mem.sb;
Rn = Rn + hilo; }},
{{ EA = Rn + hilo; }});
+0x18: ldrd_pu({{ Rde = bits(Mem.ud, 31, 0);
+ Rdo = bits(Mem.ud, 63, 32); }},
+ {{ EA = Rn + Rm; }});
0x19: ldrsb_pul({{ Rd = Mem.sb; }},
{{ EA = Rn + Rm; }});
+0x1a: ldrd_puw({{ Rde = bits(Mem.ud, 31, 0);
+ Rdo = bits(Mem.ud, 63, 32);
+ Rn = Rn + Rm; }},
+ {{ EA = Rn + Rm; }});
0x1b: ldrsb_puwl({{ Rd = Mem.sb;
Rn = Rn + Rm; }},
{{ EA = Rn + Rm; }});
+0x1c: ldrd_pui({{ Rde = bits(Mem.ud, 31, 0);
+ Rdo = bits(Mem.ud, 63, 32); }},
+ {{ EA = Rn + hilo; }});
0x1d: ldrsb_puil({{ Rd = Mem.sb; }},
{{ EA = Rn + hilo; }});
+0x1e: ldrd_puiw({{ Rde = bits(Mem.ud, 31, 0);
+ Rdo = bits(Mem.ud, 63, 32);
+ Rn = Rn + hilo; }},
+{{ EA = Rn + hilo; }});
0x1f: ldrsb_puiwl({{ Rd = Mem.sb;
Rn = Rn + hilo; }},
{{ EA = Rn + hilo; }});
@@
[m5-dev] [PATCH 04 of 31] ARM: Don't always update CPSR
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1247028751 25200
# Node ID e4e0a9c21038f603f01f8ae76c530bd85e9ea88c
# Parent f51525f758ad52dad2be9872bd7ae9c3ed04ab60
ARM: Don't always update CPSR.
diff --git a/src/arch/arm/isa/formats/mem.isa b/src/arch/arm/isa/formats/mem.isa
--- a/src/arch/arm/isa/formats/mem.isa
+++ b/src/arch/arm/isa/formats/mem.isa
@@ -354,7 +354,8 @@
{
Fault fault = NoFault;
-%(op_dest_decl)s;
+%(op_decl)s;
+%(op_rd)s;
if (%(predicate_test)s)
{
diff --git a/src/arch/arm/isa/formats/util.isa
b/src/arch/arm/isa/formats/util.isa
--- a/src/arch/arm/isa/formats/util.isa
+++ b/src/arch/arm/isa/formats/util.isa
@@ -35,7 +35,6 @@
# Substitute in the shifted portion of operations
new_code = re.sub(r'Rm_Imm', 'shift_rm_imm(Rm, shift_size, shift,
Cpsr29:)', code)
new_code = re.sub(r'Rm_Rs', 'shift_rm_rs(Rm, Rs, shift, Cpsr29:)',
new_code)
-new_code = re.sub(r'^', 'Cpsr = Cpsr;', new_code)
return new_code
def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
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[m5-dev] [PATCH 05 of 31] ARM: Add an AddrMode2 format for memory instructions that use address mode 2
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1247029036 25200
# Node ID 16c1879694a187e9124819e196c8ce0181ee83f2
# Parent e4e0a9c21038f603f01f8ae76c530bd85e9ea88c
ARM: Add an AddrMode2 format for memory instructions that use address mode 2.
diff --git a/src/arch/arm/insts/mem.hh b/src/arch/arm/insts/mem.hh
--- a/src/arch/arm/insts/mem.hh
+++ b/src/arch/arm/insts/mem.hh
@@ -68,12 +68,6 @@
hilo((machInst.immedHi11_8 4) | machInst.immedLo3_0),
shift_size(machInst.shiftSize), shift(machInst.shift)
{
-// When Up is not set, then we must subtract by the displacement
-if (!up)
-{
-disp = -disp;
-disp8 = -disp8;
-}
}
std::string
diff --git a/src/arch/arm/isa/decoder.isa b/src/arch/arm/isa/decoder.isa
--- a/src/arch/arm/isa/decoder.isa
+++ b/src/arch/arm/isa/decoder.isa
@@ -46,10 +46,10 @@
0x1: PredImmOp::subi_uop({{ Raddr = Rn - rotated_imm; }},
'IsMicroop');
0x2: ArmLoadMemory::ldr_uop({{ Rd = Mem; }},
-{{ EA = Raddr + disp; }},
+{{ EA = Raddr + (up ? disp : -disp);
}},
inst_flags = [IsMicroop]);
0x3: ArmStoreMemory::str_uop({{ Mem = Rd; }},
- {{ EA = Raddr + disp; }},
+ {{ EA = Raddr + (up ? disp : -disp);
}},
inst_flags = [IsMicroop]);
0x4: PredImmOp::addi_rd_uop({{ Rd = Rn + rotated_imm; }},
'IsMicroop');
@@ -63,16 +63,16 @@
Rlo = Fd.ud 0x; }},
'IsMicroop');
0x2: ArmLoadMemory::ldhi_uop({{ Rhi = Mem; }},
- {{ EA = Rn + disp; }},
+ {{ EA = Rn + (up ? disp : -disp); }},
inst_flags = [IsMicroop]);
0x3: ArmLoadMemory::ldlo_uop({{ Rlo = Mem; }},
- {{ EA = Rn + disp; }},
+ {{ EA = Rn + (up ? disp : -disp); }},
inst_flags = [IsMicroop]);
0x4: ArmStoreMemory::sthi_uop({{ Mem = Rhi; }},
- {{ EA = Rn + disp; }},
+ {{ EA = Rn + (up ? disp : -disp); }},
inst_flags = [IsMicroop]);
0x5: ArmStoreMemory::stlo_uop({{ Mem = Rlo; }},
- {{ EA = Rn + disp; }},
+ {{ EA = Rn + (up ? disp : -disp); }},
inst_flags = [IsMicroop]);
}
default: Unknown::unknown(); // TODO: Ignore other NV space for now
@@ -225,107 +225,9 @@
0xb: WarnUnimpl::mrs_i_spsr();
}
}
-0x2: decode PUBWL {
-// CAREFUL:
-// Can always do EA + disp, since we negate disp using the UP flag
-// Post-indexed variants
-0x00,0x08: ArmStoreMemory::str_({{ Mem = Rd;
- Rn = Rn + disp; }},
-{{ EA = Rn; }});
-0x01,0x09: ArmLoadMemory::ldr_l({{ Rn = Rn + disp;
- Rd = Mem; }},
-{{ EA = Rn; }});
-0x04,0x0c: ArmStoreMemory::strb_b({{ Mem.ub = Rd.ub;
- Rn = Rn + disp; }},
- {{ EA = Rn; }});
-0x05,0x0d: ArmLoadMemory::ldrb_bl({{ Rn = Rn + disp;
- Rd.ub = Mem.ub; }},
- {{ EA = Rn; }});
-// Pre-indexed variants
-0x10,0x18: ArmStoreMemory::str_p({{ Mem = Rd; }});
-0x11,0x19: ArmLoadMemory::ldr_pl({{ Rd = Mem; }});
-0x12,0x1a: ArmStoreMemory::str_pw({{ Mem = Rd;
- Rn = Rn + disp; }});
-0x13,0x1b: ArmLoadMemory::ldr_pwl({{ Rn = Rn + disp;
- Rd = Mem; }});
-0x14,0x1c: ArmStoreMemory::strb_pb({{ Mem.ub = Rd.ub; }});
-0x15,0x1d: ArmLoadMemory::ldrb_pbl({{ Rd.ub = Mem.ub; }});
-0x16,0x1e: ArmStoreMemory::strb_pbw({{ Mem.ub = Rd.ub;
- Rn = Rn + disp; }});
-0x17,0x1f: ArmLoadMemory::ldrb_pbwl({{ Rn = Rn + disp;
- Rd.ub = Mem.ub; }});
-}
+0x2: AddrMode2::addrMode2(Disp, disp);
0x3: decode OPCODE_4 {
-0: decode PUBWL {
-format
[m5-dev] [PATCH 06 of 31] ARM: Get rid of end_addr in the ArmMacroStore constructor
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1247029159 25200
# Node ID ba161dcdbde4ce9fc6f5e7424095a1121897e18b
# Parent 16c1879694a187e9124819e196c8ce0181ee83f2
ARM: Get rid of end_addr in the ArmMacroStore constructor.
diff --git a/src/arch/arm/isa/formats/macromem.isa
b/src/arch/arm/isa/formats/macromem.isa
--- a/src/arch/arm/isa/formats/macromem.isa
+++ b/src/arch/arm/isa/formats/macromem.isa
@@ -52,9 +52,7 @@
{
%(constructor)s;
uint32_t regs_to_handle = reglist;
-uint32_t j = 0,
- start_addr = 0,
- end_addr = 0;
+uint32_t start_addr = 0;
switch (puswl)
{
@@ -63,28 +61,24 @@
case 0x02: //W stmda_w
case 0x03: //WL ldmda_wl
start_addr = (ones 2) - 4;
-end_addr = 0;
break;
case 0x08: // Ustmia_u
case 0x09: // U L ldmia_ul
case 0x0a: // U W stmia
case 0x0b: // U WL ldmia
start_addr = 0;
-end_addr = (ones 2) - 4;
break;
case 0x10: // P stmdb
case 0x11: // P L ldmdb
case 0x12: // P W stmdb
case 0x13: // P WL ldmdb
start_addr = (ones 2); // U-bit is already 0 for subtract
-end_addr = 4; // negative 4
break;
case 0x18: // PUstmib
case 0x19: // PU L ldmib
case 0x1a: // PU W stmib
case 0x1b: // PU WL ldmib
start_addr = 4;
-end_addr = (ones 2) + 4;
break;
default:
panic(Unhandled Load/Store Multiple Instruction,
@@ -92,12 +86,11 @@
break;
}
-//TODO - Add addi_uop/subi_uop here to create starting addresses
-//Just using addi with 0 offset makes a copy of Rn for our use
uint32_t newMachInst = 0;
newMachInst = machInst 0x;
microOps[0] = new Addi_uop(newMachInst);
+unsigned j = 0;
for (int i = 1; i ones+1; i++)
{
// Get next available bit for transfer
@@ -112,15 +105,6 @@
else
start_addr -= 4;
}
-
-/* TODO: Take a look at how these 2 values should meet together
-if (start_addr != (end_addr - 4))
-{
-fprintf(stderr, start_addr: %d\n, start_addr);
-fprintf(stderr, end_addr: %d\n, end_addr);
-panic(start_addr does not meet end_addr);
-}
-*/
if (writeback)
{
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[m5-dev] [PATCH 08 of 31] ARM: Tune up predicated instruction decoding
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1247030011 25200
# Node ID f7fff997a90c73c0039a4df21765af1e7472d009
# Parent 390b00170a5874e09107d0b16f33ce59e1e7111d
ARM: Tune up predicated instruction decoding.
diff --git a/src/arch/arm/insts/pred_inst.cc b/src/arch/arm/insts/pred_inst.cc
--- a/src/arch/arm/insts/pred_inst.cc
+++ b/src/arch/arm/insts/pred_inst.cc
@@ -32,10 +32,18 @@
namespace ArmISA
{
std::string
-PredOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+PredIntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
-printDataInst(ss);
+printDataInst(ss, false);
+return ss.str();
+}
+
+std::string
+PredImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+std::stringstream ss;
+printDataInst(ss, true);
return ss.str();
}
diff --git a/src/arch/arm/insts/pred_inst.hh b/src/arch/arm/insts/pred_inst.hh
--- a/src/arch/arm/insts/pred_inst.hh
+++ b/src/arch/arm/insts/pred_inst.hh
@@ -56,8 +56,6 @@
condCode((ConditionCode)(unsigned)machInst.condCode)
{
}
-
-std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
/**
@@ -65,23 +63,25 @@
*/
class PredImmOp : public PredOp
{
-protected:
+protected:
-uint32_t imm;
-uint32_t rotate;
-uint32_t rotated_imm;
-uint32_t rotated_carry;
+uint32_t imm;
+uint32_t rotate;
+uint32_t rotated_imm;
+uint32_t rotated_carry;
-/// Constructor
-PredImmOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
- PredOp(mnem, _machInst, __opClass),
- imm(machInst.imm), rotate(machInst.rotate 1),
- rotated_imm(0), rotated_carry(0)
-{
-rotated_imm = rotate_imm(imm, rotate);
-if (rotate != 0)
-rotated_carry = (rotated_imm 31) 1;
-}
+/// Constructor
+PredImmOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
+ PredOp(mnem, _machInst, __opClass),
+ imm(machInst.imm), rotate(machInst.rotate 1),
+ rotated_imm(0), rotated_carry(0)
+{
+rotated_imm = rotate_imm(imm, rotate);
+if (rotate != 0)
+rotated_carry = (rotated_imm 31) 1;
+}
+
+std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
/**
@@ -89,17 +89,19 @@
*/
class PredIntOp : public PredOp
{
-protected:
+protected:
-uint32_t shift_size;
-uint32_t shift;
+uint32_t shift_size;
+uint32_t shift;
-/// Constructor
-PredIntOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
- PredOp(mnem, _machInst, __opClass),
- shift_size(machInst.shiftSize), shift(machInst.shift)
-{
-}
+/// Constructor
+PredIntOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
+ PredOp(mnem, _machInst, __opClass),
+ shift_size(machInst.shiftSize), shift(machInst.shift)
+{
+}
+
+std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
/**
@@ -107,36 +109,36 @@
*/
class PredMacroOp : public PredOp
{
-protected:
+protected:
-uint32_t numMicroops;
-StaticInstPtr * microOps;
+uint32_t numMicroops;
+StaticInstPtr * microOps;
-/// Constructor
-PredMacroOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
-PredOp(mnem, _machInst, __opClass),
-numMicroops(0)
-{
-// We rely on the subclasses of this object to handle the
-// initialization of the micro-operations, since they are
-// all of variable length
-flags[IsMacroop] = true;
-}
+/// Constructor
+PredMacroOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
+PredOp(mnem, _machInst, __opClass),
+numMicroops(0)
+{
+// We rely on the subclasses of this object to handle the
+// initialization of the micro-operations, since they are
+// all of variable length
+flags[IsMacroop] = true;
+}
-~PredMacroOp()
-{
-if (numMicroops)
-delete [] microOps;
-}
+~PredMacroOp()
+{
+if (numMicroops)
+delete [] microOps;
+}
-StaticInstPtr
-fetchMicroop(MicroPC microPC)
-{
-assert(microPC numMicroops);
-return microOps[microPC];
-}
+StaticInstPtr
+fetchMicroop(MicroPC microPC)
+{
+assert(microPC numMicroops);
+return microOps[microPC];
+}
-std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
const;
+std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
/**
@@
[m5-dev] [PATCH 09 of 31] ARM: Improve memory instruction disassembly
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1247030039 25200
# Node ID e654a7b1863b13b020abe6716eb71a4348177271
# Parent f7fff997a90c73c0039a4df21765af1e7472d009
ARM: Improve memory instruction disassembly.
diff --git a/src/arch/arm/insts/mem.cc b/src/arch/arm/insts/mem.cc
--- a/src/arch/arm/insts/mem.cc
+++ b/src/arch/arm/insts/mem.cc
@@ -37,14 +37,17 @@
{
std::stringstream ss;
printMnemonic(ss);
+printReg(ss, machInst.rd);
+ss , [;
+printReg(ss, machInst.rn);
+ss , ;
+if (machInst.puswl.prepost == 1)
+printOffset(ss);
+ss ];
+if (machInst.puswl.prepost == 0)
+printOffset(ss);
+else if (machInst.puswl.writeback)
+ss !;
return ss.str();
}
-
-std::string
-MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
-{
-std::stringstream ss;
-printMnemonic(ss);
-return ss.str();
}
-}
diff --git a/src/arch/arm/insts/mem.hh b/src/arch/arm/insts/mem.hh
--- a/src/arch/arm/insts/mem.hh
+++ b/src/arch/arm/insts/mem.hh
@@ -65,23 +65,75 @@
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+
+virtual void
+printOffset(std::ostream os) const
+{}
};
- /**
- * Base class for a few miscellaneous memory-format insts
- * that don't interpret the disp field
- */
-class MemoryNoDisp : public Memory
+class MemoryDisp : public Memory
{
protected:
/// Constructor
-MemoryNoDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
+MemoryDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
: Memory(mnem, _machInst, __opClass)
{
}
-std::string
-generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+void
+printOffset(std::ostream os) const
+{
+ccprintf(os, #%#x, (machInst.puswl.up ? disp : -disp));
+}
+};
+
+class MemoryHilo : public Memory
+{
+ protected:
+/// Constructor
+MemoryHilo(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
+: Memory(mnem, _machInst, __opClass)
+{
+}
+
+void
+printOffset(std::ostream os) const
+{
+ccprintf(os, #%#x, (machInst.puswl.up ? hilo : -hilo));
+}
+};
+
+class MemoryShift : public Memory
+{
+ protected:
+/// Constructor
+MemoryShift(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
+: Memory(mnem, _machInst, __opClass)
+{
+}
+
+void
+printOffset(std::ostream os) const
+{
+printShiftOperand(os);
+}
+};
+
+class MemoryReg : public Memory
+{
+ protected:
+/// Constructor
+MemoryReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
+: Memory(mnem, _machInst, __opClass)
+{
+}
+
+void
+printOffset(std::ostream os) const
+{
+os (machInst.puswl.up ? + : - );
+printReg(os, machInst.rm);
+}
};
}
diff --git a/src/arch/arm/isa/formats/mem.isa b/src/arch/arm/isa/formats/mem.isa
--- a/src/arch/arm/isa/formats/mem.isa
+++ b/src/arch/arm/isa/formats/mem.isa
@@ -276,11 +276,12 @@
# Here's where we'll tack on a flag to make this a usermode access.
mnem += t
type = (Store, Load)[l]
-suffix = _%s_P%dU%dB%dW%d % (suffix, p, u, b, w)
+newSuffix = _%s_P%dU%dB%dW%d % (suffix, p, u, b, w)
if b == 1:
mnem += b
-return LoadStoreBase(mnem, mnem.capitalize() + suffix,
+return LoadStoreBase(mnem, mnem.capitalize() + newSuffix,
ea_code, code, mem_flags = [], inst_flags = [],
+base_class = 'Memory' + suffix,
exec_template_base = type.capitalize())
def buildMode3Inst(p, u, i, w, type, code, mnem):
@@ -289,9 +290,11 @@
ea_code = EA = Rn %s; % (, offset)[p]
if p == 0 or w == 1:
code += Rn = Rn %s; % offset
-suffix = _P%dU%dI%dW%d % (p, u, i, w)
-return LoadStoreBase(mnem, mnem.capitalize() + suffix,
+newSuffix = _P%dU%dI%dW%d % (p, u, i, w)
+suffix = (Reg, Hilo)[i]
+return LoadStoreBase(mnem, mnem.capitalize() + newSuffix,
ea_code, code, mem_flags = [], inst_flags = [],
+base_class = 'Memory' + suffix,
exec_template_base = type.capitalize())
}};
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[m5-dev] [PATCH 11 of 31] ARM: Move the memory microops out of the decoder and into the ISA desc
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1247030415 25200
# Node ID 35afb9c03f93765def29418dda102a4fe0783796
# Parent d243b53a4a035947d7519c72b1f6cb6dc9c11c71
ARM: Move the memory microops out of the decoder and into the ISA desc.
diff --git a/src/arch/arm/insts/macromem.hh b/src/arch/arm/insts/macromem.hh
--- a/src/arch/arm/insts/macromem.hh
+++ b/src/arch/arm/insts/macromem.hh
@@ -59,6 +59,22 @@
RegIndex _ura, RegIndex _urb, uint8_t _imm)
: PredOp(mnem, machInst, __opClass),
ura(_ura), urb(_urb), imm(_imm)
+{
+}
+};
+
+/**
+ * Memory microops which use IntReg + Imm addressing
+ */
+class MicroMemOp : public MicroIntOp
+{
+ protected:
+unsigned memAccessFlags;
+
+MicroMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
+ RegIndex _ura, RegIndex _urb, uint8_t _imm)
+: MicroIntOp(mnem, machInst, __opClass, _ura, _urb, _imm),
+ memAccessFlags(0)
{
}
};
diff --git a/src/arch/arm/isa/decoder.isa b/src/arch/arm/isa/decoder.isa
--- a/src/arch/arm/isa/decoder.isa
+++ b/src/arch/arm/isa/decoder.isa
@@ -39,33 +39,13 @@
//
decode COND_CODE default Unknown::unknown() {
0xf: decode COND_CODE {
-0x0: decode OPCODE {
+0x1: decode OPCODE {
// Just a simple trick to allow us to specify our new uops here
-0x2: ArmLoadMemory::ldr_uop({{ Rd = Mem; }},
-{{ EA = Raddr + (up ? disp : -disp);
}},
- inst_flags = [IsMicroop]);
-0x3: ArmStoreMemory::str_uop({{ Mem = Rd; }},
- {{ EA = Raddr + (up ? disp : -disp);
}},
-inst_flags = [IsMicroop]);
-}
-0x1: decode OPCODE {
0x0: PredIntOp::mvtd_uop({{ Fd.ud = ((uint64_t) Rhi 32)|Rlo; }},
'IsMicroop');
0x1: PredIntOp::mvfd_uop({{ Rhi = (Fd.ud 32) 0x;
Rlo = Fd.ud 0x; }},
'IsMicroop');
-0x2: ArmLoadMemory::ldhi_uop({{ Rhi = Mem; }},
- {{ EA = Rn + (up ? disp : -disp); }},
-inst_flags = [IsMicroop]);
-0x3: ArmLoadMemory::ldlo_uop({{ Rlo = Mem; }},
- {{ EA = Rn + (up ? disp : -disp); }},
-inst_flags = [IsMicroop]);
-0x4: ArmStoreMemory::sthi_uop({{ Mem = Rhi; }},
- {{ EA = Rn + (up ? disp : -disp); }},
- inst_flags = [IsMicroop]);
-0x5: ArmStoreMemory::stlo_uop({{ Mem = Rlo; }},
- {{ EA = Rn + (up ? disp : -disp); }},
- inst_flags = [IsMicroop]);
}
default: Unknown::unknown(); // TODO: Ignore other NV space for now
}
diff --git a/src/arch/arm/isa/formats/macromem.isa
b/src/arch/arm/isa/formats/macromem.isa
--- a/src/arch/arm/isa/formats/macromem.isa
+++ b/src/arch/arm/isa/formats/macromem.isa
@@ -29,6 +29,67 @@
// Authors: Stephen Hines
// Gabe Black
+
+//
+// Common microop templates
+//
+
+def template MicroConstructor {{
+inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ RegIndex _ura,
+ RegIndex _urb,
+ uint8_t _imm)
+: %(base_class)s(%(mnemonic)s, machInst, %(op_class)s,
+ _ura, _urb, _imm)
+{
+%(constructor)s;
+}
+}};
+
+
+//
+// Load/store microops
+//
+
+def template MicroMemDeclare {{
+class %(class_name)s : public %(base_class)s
+{
+ public:
+%(class_name)s(ExtMachInst machInst,
+ RegIndex _ura, RegIndex _urb,
+ uint8_t _imm);
+%(BasicExecDeclare)s
+%(InitiateAccDeclare)s
+%(CompleteAccDeclare)s
+};
+}};
+
+let {{
+microLdrUopIop = InstObjParams('ldr_uop', 'MicroLdrUop',
+ 'MicroMemOp',
+ {'memacc_code': 'Ra = Mem;',
+'ea_code': 'EA = Rb + (UP ? imm : -imm);',
+'predicate_test': predicateTest},
+ ['IsMicroop'])
+
+microStrUopIop = InstObjParams('str_uop', 'MicroStrUop',
+ 'MicroMemOp',
+ {'memacc_code': 'Mem = Ra;',
+
[m5-dev] [PATCH 10 of 31] ARM: Move the integer microops out of the decoder and into the ISA desc
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1247030259 25200
# Node ID d243b53a4a035947d7519c72b1f6cb6dc9c11c71
# Parent e654a7b1863b13b020abe6716eb71a4348177271
ARM: Move the integer microops out of the decoder and into the ISA desc.
diff --git a/src/arch/arm/insts/macromem.hh b/src/arch/arm/insts/macromem.hh
--- a/src/arch/arm/insts/macromem.hh
+++ b/src/arch/arm/insts/macromem.hh
@@ -45,6 +45,23 @@
}
return ones;
}
+
+/**
+ * Microops of the form IntRegA = IntRegB op Imm
+ */
+class MicroIntOp : public PredOp
+{
+ protected:
+RegIndex ura, urb;
+uint8_t imm;
+
+MicroIntOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
+ RegIndex _ura, RegIndex _urb, uint8_t _imm)
+: PredOp(mnem, machInst, __opClass),
+ ura(_ura), urb(_urb), imm(_imm)
+{
+}
+};
/**
* Arm Macro Memory operations like LDM/STM
diff --git a/src/arch/arm/isa/decoder.isa b/src/arch/arm/isa/decoder.isa
--- a/src/arch/arm/isa/decoder.isa
+++ b/src/arch/arm/isa/decoder.isa
@@ -41,20 +41,12 @@
0xf: decode COND_CODE {
0x0: decode OPCODE {
// Just a simple trick to allow us to specify our new uops here
-0x0: PredImmOp::addi_uop({{ Raddr = Rn + rotated_imm; }},
-'IsMicroop');
-0x1: PredImmOp::subi_uop({{ Raddr = Rn - rotated_imm; }},
-'IsMicroop');
0x2: ArmLoadMemory::ldr_uop({{ Rd = Mem; }},
{{ EA = Raddr + (up ? disp : -disp);
}},
inst_flags = [IsMicroop]);
0x3: ArmStoreMemory::str_uop({{ Mem = Rd; }},
{{ EA = Raddr + (up ? disp : -disp);
}},
inst_flags = [IsMicroop]);
-0x4: PredImmOp::addi_rd_uop({{ Rd = Rn + rotated_imm; }},
- 'IsMicroop');
-0x5: PredImmOp::subi_rd_uop({{ Rd = Rn - rotated_imm; }},
- 'IsMicroop');
}
0x1: decode OPCODE {
0x0: PredIntOp::mvtd_uop({{ Fd.ud = ((uint64_t) Rhi 32)|Rlo; }},
diff --git a/src/arch/arm/isa/formats/macromem.isa
b/src/arch/arm/isa/formats/macromem.isa
--- a/src/arch/arm/isa/formats/macromem.isa
+++ b/src/arch/arm/isa/formats/macromem.isa
@@ -27,6 +27,57 @@
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Stephen Hines
+// Gabe Black
+
+
+
+//
+// Integer = Integer op Immediate microops
+//
+
+def template MicroIntDeclare {{
+class %(class_name)s : public %(base_class)s
+{
+ public:
+%(class_name)s(ExtMachInst machInst,
+ RegIndex _ura, RegIndex _urb,
+ uint8_t _imm);
+%(BasicExecDeclare)s
+};
+}};
+
+def template MicroIntConstructor {{
+inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ RegIndex _ura,
+ RegIndex _urb,
+ uint8_t _imm)
+: %(base_class)s(%(mnemonic)s, machInst, %(op_class)s,
+ _ura, _urb, _imm)
+{
+%(constructor)s;
+}
+}};
+
+let {{
+microAddiUopIop = InstObjParams('addi_uop', 'MicroAddiUop',
+'MicroIntOp',
+{'code': 'Ra = Rb + imm;',
+ 'predicate_test': predicateTest},
+['IsMicroop'])
+
+microSubiUopIop = InstObjParams('subi_uop', 'MicroSubiUop',
+'MicroIntOp',
+{'code': 'Ra = Rb - imm;',
+ 'predicate_test': predicateTest},
+['IsMicroop'])
+
+header_output = MicroIntDeclare.subst(microAddiUopIop) + \
+MicroIntDeclare.subst(microSubiUopIop)
+decoder_output = MicroIntConstructor.subst(microAddiUopIop) + \
+ MicroIntConstructor.subst(microSubiUopIop)
+exec_output = PredOpExecute.subst(microAddiUopIop) + \
+ PredOpExecute.subst(microSubiUopIop)
+}};
//
@@ -86,13 +137,12 @@
break;
}
-uint32_t newMachInst = 0;
-newMachInst = machInst 0x;
-microOps[0] = new Addi_uop(newMachInst);
+// Add 0 to Rn and stick it in Raddr (register 17).
+// This is equivalent to a move.
+microOps[0] = new MicroAddiUop(machInst, 17, RN, 0);
unsigned j = 0;
-for (int i = 1; i ones+1; i++)
-{
+for (int i = 1; i ones+1; i++) {
// Get next available bit for transfer
[m5-dev] [PATCH 12 of 31] ARM: Move the remaining microops out of the decoder and into the ISA desc
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1247030577 25200
# Node ID fb76c90f067563a312f12d012f77787d2093a79b
# Parent 35afb9c03f93765def29418dda102a4fe0783796
ARM: Move the remaining microops out of the decoder and into the ISA desc.
diff --git a/src/arch/arm/isa/decoder.isa b/src/arch/arm/isa/decoder.isa
--- a/src/arch/arm/isa/decoder.isa
+++ b/src/arch/arm/isa/decoder.isa
@@ -37,19 +37,8 @@
// in the ARM ISA specification document starting with Table B.1 or 3-1
//
//
-decode COND_CODE default Unknown::unknown() {
-0xf: decode COND_CODE {
-0x1: decode OPCODE {
-// Just a simple trick to allow us to specify our new uops here
-0x0: PredIntOp::mvtd_uop({{ Fd.ud = ((uint64_t) Rhi 32)|Rlo; }},
-'IsMicroop');
-0x1: PredIntOp::mvfd_uop({{ Rhi = (Fd.ud 32) 0x;
-Rlo = Fd.ud 0x; }},
-'IsMicroop');
-}
-default: Unknown::unknown(); // TODO: Ignore other NV space for now
-}
-default: decode ENCODING {
+
+decode ENCODING default Unknown::unknown() {
format DataOp {
0x0: decode SEVEN_AND_FOUR {
1: decode MISC_OPCODE {
@@ -440,5 +429,4 @@
}
}
}
-}
diff --git a/src/arch/arm/isa/formats/macromem.isa
b/src/arch/arm/isa/formats/macromem.isa
--- a/src/arch/arm/isa/formats/macromem.isa
+++ b/src/arch/arm/isa/formats/macromem.isa
@@ -126,6 +126,33 @@
MicroConstructor.subst(microSubiUopIop)
exec_output = PredOpExecute.subst(microAddiUopIop) + \
PredOpExecute.subst(microSubiUopIop)
+}};
+
+
+//
+// Moving to/from double floating point registers
+//
+
+let {{
+microMvtdUopIop = InstObjParams('mvtd_uop', 'MicroMvtdUop',
+'PredOp',
+{'code': 'Fd.ud = (Rhi.ud 32) | Rlo;',
+ 'predicate_test': predicateTest},
+['IsMicroop'])
+
+microMvfdUopIop = InstObjParams('mvfd_uop', 'MicroMvfdUop',
+'PredOp',
+{'code': '''Rhi = bits(Fd.ud, 63, 32);
+Rlo = bits(Fd.ud, 31, 0);''',
+ 'predicate_test': predicateTest},
+['IsMicroop'])
+
+header_output = BasicDeclare.subst(microMvtdUopIop) + \
+BasicDeclare.subst(microMvfdUopIop)
+decoder_output = BasicConstructor.subst(microMvtdUopIop) + \
+ BasicConstructor.subst(microMvfdUopIop)
+exec_output = PredOpExecute.subst(microMvtdUopIop) + \
+ PredOpExecute.subst(microMvfdUopIop)
}};
diff --git a/src/arch/arm/isa/formats/util.isa
b/src/arch/arm/isa/formats/util.isa
--- a/src/arch/arm/isa/formats/util.isa
+++ b/src/arch/arm/isa/formats/util.isa
@@ -106,18 +106,16 @@
emit_ldfstf_uops(StaticInstPtr* microOps, int index, ExtMachInst machInst,
bool loadop, bool up, int32_t disp)
{
-MachInst newMachInst = machInst 0xf000f000;
-
if (loadop)
{
microOps[index++] = new MicroLdrUop(machInst, 19, RN, disp);
microOps[index++] =
new MicroLdrUop(machInst, 18, RN, disp + (up ? 4 : -4));
-microOps[index++] = new Mvtd_uop(newMachInst);
+microOps[index++] = new MicroMvtdUop(machInst);
}
else
{
-microOps[index++] = new Mvfd_uop(newMachInst);
+microOps[index++] = new MicroMvfdUop(machInst);
microOps[index++] = new MicroStrUop(machInst, 19, RN, disp);
microOps[index++] =
new MicroStrUop(machInst, 18, RN, disp + (up ? 4 : -4));
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[m5-dev] [PATCH 13 of 31] ISA parser: Allow alternative read/write code for operands
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1247030684 25200
# Node ID b754546a7d335695138e0cb5fb422e6273861fb9
# Parent fb76c90f067563a312f12d012f77787d2093a79b
ISA parser: Allow alternative read/write code for operands.
diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py
--- a/src/arch/isa_parser.py
+++ b/src/arch/isa_parser.py
@@ -344,7 +344,7 @@
error(t.lexer.lineno,
'error: operand types must be defined before operands')
try:
-userDict = eval('{' + t[3] + '}')
+userDict = eval('{' + t[3] + '}', exportContext)
except Exception, exc:
error(t.lexer.lineno,
'error: %s in def operands block %s.' % (exc, t[3]))
@@ -1173,6 +1173,41 @@
# (e.g., 32-bit integer register).
#
class Operand(object):
+def buildReadCode(self, func = None, width = None):
+code = self.read_code % {name: self.base_name,
+ func: func,
+ width: width,
+ op_idx: self.src_reg_idx,
+ reg_idx: self.reg_spec,
+ size: self.size,
+ ctype: self.ctype}
+if self.size != self.dflt_size:
+return '%s = bits(%s, %d, 0);\n' % \
+ (self.base_name, code, self.size-1)
+else:
+return '%s = %s;\n' % \
+ (self.base_name, code)
+
+def buildWriteCode(self, func = None, width = None):
+if (self.size != self.dflt_size and self.is_signed):
+final_val = 'sext%d(%s)' % (self.size, self.base_name)
+else:
+final_val = self.base_name
+code = self.write_code % {name: self.base_name,
+ func: func,
+ width: width,
+ op_idx: self.dest_reg_idx,
+ reg_idx: self.reg_spec,
+ size: self.size,
+ ctype: self.ctype,
+ final_val: final_val}
+return '''
+{
+%s final_val = %s;
+%s;
+if (traceData) { traceData-setData(final_val); }
+}''' % (self.dflt_ctype, final_val, code)
+
def __init__(self, full_name, ext, is_src, is_dest):
self.full_name = full_name
self.ext = ext
@@ -1272,6 +1307,8 @@
def makeRead(self):
if (self.ctype == 'float' or self.ctype == 'double'):
error(0, 'Attempt to read integer register as FP')
+if self.read_code != None:
+return self.buildReadCode('readIntRegOperand')
if (self.size == self.dflt_size):
return '%s = xc-readIntRegOperand(this, %d);\n' % \
(self.base_name, self.src_reg_idx)
@@ -1288,6 +1325,8 @@
def makeWrite(self):
if (self.ctype == 'float' or self.ctype == 'double'):
error(0, 'Attempt to write integer register as FP')
+if self.write_code != None:
+return self.buildWriteCode('setIntRegOperand')
if (self.size != self.dflt_size and self.is_signed):
final_val = 'sext%d(%s)' % (self.size, self.base_name)
else:
@@ -1340,6 +1379,8 @@
else:
base = 'xc-%s(this, %d)' % \
(func, self.src_reg_idx)
+if self.read_code != None:
+return self.buildReadCode(func, width)
if bit_select:
return '%s = bits(%s, %d, 0);\n' % \
(self.base_name, base, self.size-1)
@@ -1368,6 +1409,8 @@
final_ctype = 'uint%d_t' % self.dflt_size
if (self.size != self.dflt_size and self.is_signed):
final_val = 'sext%d(%s)' % (self.size, self.base_name)
+if self.write_code != None:
+return self.buildWriteCode(func, width)
if width:
widthSpecifier = ', %d' % width
wb = '''
@@ -1400,6 +1443,8 @@
bit_select = 0
if (self.ctype == 'float' or self.ctype == 'double'):
error(0, 'Attempt to read control register as FP')
+if self.read_code != None:
+return self.buildReadCode('readMiscRegOperand')
base = 'xc-readMiscRegOperand(this, %s)' % self.src_reg_idx
if self.size == self.dflt_size:
return '%s = %s;\n' % (self.base_name, base)
@@ -1410,6 +1455,8 @@
def makeWrite(self):
if (self.ctype == 'float' or self.ctype == 'double'):
error(0, 'Attempt to write control register as FP')
+if self.write_code != None:
+return self.buildWriteCode('setMiscRegOperand')
wb = 'xc-setMiscRegOperand(this, %s, %s);\n' % \
(self.dest_reg_idx, self.base_name)
wb += 'if (traceData) { traceData-setData(%s); }' % \
@@ -1437,6 +1484,8 @@
bit_select = 0
[m5-dev] [PATCH 14 of 31] ARM: Use custom read/write code to alias R15 with the PC
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1247030974 25200
# Node ID 558ae700b4c884985894057001b428581cad8a87
# Parent b754546a7d335695138e0cb5fb422e6273861fb9
ARM: Use custom read/write code to alias R15 with the PC.
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -40,16 +40,27 @@
'df' : ('float', 64)
}};
+let {{
+maybePCRead = '''
+((%(reg_idx)s == PCReg) ? (xc-readPC() + 8) :
+ xc-%(func)s(this, %(op_idx)s))
+'''
+maybePCWrite = '''
+((%(reg_idx)s == PCReg) ? xc-setNextPC(%(final_val)s) :
+ xc-%(func)s(this, %(op_idx)s, %(final_val)s))
+'''
+}};
+
def operands {{
#General Purpose Integer Reg Operands
-'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1),
-'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2),
-'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3),
-'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4),
+'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1, maybePCRead, maybePCWrite),
+'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite),
+'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3, maybePCRead, maybePCWrite),
+'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4, maybePCRead, maybePCWrite),
#Destination register for load/store double instructions
-'Rdo': ('IntReg', 'uw', '(RD ~1)', 'IsInteger', 4),
-'Rde': ('IntReg', 'uw', '(RD | 1)', 'IsInteger', 5),
+'Rdo': ('IntReg', 'uw', '(RD ~1)', 'IsInteger', 4, maybePCRead,
maybePCWrite),
+'Rde': ('IntReg', 'uw', '(RD | 1)', 'IsInteger', 5, maybePCRead,
maybePCWrite),
'Raddr': ('IntReg', 'uw', '17', 'IsInteger', 6),
'Rhi': ('IntReg', 'uw', '18', 'IsInteger', 7),
@@ -57,8 +68,8 @@
'LR': ('IntReg', 'uw', '14', 'IsInteger', 9),
#Register fields for microops
-'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 11),
-'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 12),
+'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 11, maybePCRead, maybePCWrite),
+'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 12, maybePCRead, maybePCWrite),
#General Purpose Floating Point Reg Operands
'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 20),
diff --git a/src/arch/arm/regfile/regfile.hh b/src/arch/arm/regfile/regfile.hh
--- a/src/arch/arm/regfile/regfile.hh
+++ b/src/arch/arm/regfile/regfile.hh
@@ -122,22 +122,12 @@
IntReg readIntReg(int intReg)
{
-// In the Arm, reading from the PC for a generic instruction yields
-// the current PC + 8, due to previous pipeline implementations
-if (intReg == PCReg)
-return intRegFile.readReg(intReg) + 8;
-//return pc + 8;
-else
-return intRegFile.readReg(intReg);
+return intRegFile.readReg(intReg);
}
void setIntReg(int intReg, const IntReg val)
{
-// Have to trap writes to PC so that they update NPC instead
-if (intReg == PCReg)
-setNextPC(val);
-else
-intRegFile.setReg(intReg, val);
+intRegFile.setReg(intReg, val);
}
protected:
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[m5-dev] [PATCH 17 of 31] Registers: Eliminate the ISA defined floating point register file
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1247031835 25200
# Node ID 95d483300be325e2f201ce2cd111a6f6a53c0b3c
# Parent 2a32835617508ef7ffb24324446a6091f0874b5f
Registers: Eliminate the ISA defined floating point register file.
diff --git a/src/arch/alpha/SConscript b/src/arch/alpha/SConscript
--- a/src/arch/alpha/SConscript
+++ b/src/arch/alpha/SConscript
@@ -34,7 +34,6 @@
if env['TARGET_ISA'] == 'alpha':
Source('ev5.cc')
Source('faults.cc')
-Source('floatregfile.cc')
Source('intregfile.cc')
Source('ipr.cc')
Source('isa.cc')
diff --git a/src/arch/alpha/floatregfile.cc b/src/arch/alpha/floatregfile.cc
deleted file mode 100644
--- a/src/arch/alpha/floatregfile.cc
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * AS IS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Steve Reinhardt
- * Gabe Black
- * Kevin Lim
- */
-
-#include cstring
-
-#include arch/alpha/floatregfile.hh
-#include sim/serialize.hh
-
-namespace AlphaISA {
-void
-FloatRegFile::clear()
-{
-std::memset(d, 0, sizeof(d));
-}
-
-void
-FloatRegFile::serialize(std::ostream os)
-{
-SERIALIZE_ARRAY(q, NumFloatRegs);
-}
-
-void
-FloatRegFile::unserialize(Checkpoint *cp, const std::string section)
-{
-UNSERIALIZE_ARRAY(q, NumFloatRegs);
-}
-
-} // namespace AlphaISA
diff --git a/src/arch/alpha/floatregfile.hh b/src/arch/alpha/floatregfile.hh
deleted file mode 100644
--- a/src/arch/alpha/floatregfile.hh
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * AS IS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Steve Reinhardt
- * Gabe Black
- */
-
-#ifndef __ARCH_ALPHA_FLOATREGFILE_HH__
-#define __ARCH_ALPHA_FLOATREGFILE_HH__
-
-#include iosfwd
-#include string
-
-#include arch/alpha/isa_traits.hh
-#include arch/alpha/types.hh
-
-class Checkpoint;
-
-namespace AlphaISA {
-
-class FloatRegFile
-{
- public:
-union {
-
[m5-dev] [PATCH 18 of 31] Registers: Eliminate the ISA defined integer register file
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1247031915 25200
# Node ID 1e69e4af6b8326bc39832eb283932765ca6028e8
# Parent 95d483300be325e2f201ce2cd111a6f6a53c0b3c
Registers: Eliminate the ISA defined integer register file.
diff --git a/src/arch/alpha/intregfile.cc b/src/arch/alpha/intregfile.cc
--- a/src/arch/alpha/intregfile.cc
+++ b/src/arch/alpha/intregfile.cc
@@ -30,11 +30,7 @@
* Kevin Lim
*/
-#include cstring
-
-#include arch/alpha/isa_traits.hh
#include arch/alpha/intregfile.hh
-#include sim/serialize.hh
namespace AlphaISA {
@@ -52,23 +48,5 @@
/* 24 */ 24, 25, 26, 27, 28, 29, 30, 31 };
#endif
-void
-IntRegFile::clear()
-{
-std::memset(regs, 0, sizeof(regs));
-}
-
-void
-IntRegFile::serialize(std::ostream os)
-{
-SERIALIZE_ARRAY(regs, NumIntRegs);
-}
-
-void
-IntRegFile::unserialize(Checkpoint *cp, const std::string section)
-{
-UNSERIALIZE_ARRAY(regs, NumIntRegs);
-}
-
} // namespace AlphaISA
diff --git a/src/arch/alpha/intregfile.hh b/src/arch/alpha/intregfile.hh
--- a/src/arch/alpha/intregfile.hh
+++ b/src/arch/alpha/intregfile.hh
@@ -32,42 +32,13 @@
#ifndef __ARCH_ALPHA_INTREGFILE_HH__
#define __ARCH_ALPHA_INTREGFILE_HH__
-#include iosfwd
-#include string
-
-#include arch/alpha/types.hh
-
-class Checkpoint;
+#include arch/alpha/isa_traits.hh
namespace AlphaISA {
// redirected register map, really only used for the full system case.
extern const int reg_redir[NumIntRegs];
-class IntRegFile
-{
- protected:
-IntReg regs[NumIntRegs];
-
- public:
-IntReg
-readReg(int intReg)
-{
-return regs[intReg];
-}
-
-void
-setReg(int intReg, const IntReg val)
-{
-regs[intReg] = val;
-}
-
-void clear();
-
-void serialize(std::ostream os);
-void unserialize(Checkpoint *cp, const std::string section);
-};
-
} // namespace AlphaISA
#endif // __ARCH_ALPHA_INTREGFILE_HH__
diff --git a/src/arch/alpha/regfile.cc b/src/arch/alpha/regfile.cc
--- a/src/arch/alpha/regfile.cc
+++ b/src/arch/alpha/regfile.cc
@@ -41,7 +41,6 @@
void
RegFile::serialize(EventManager *em, ostream os)
{
-intRegFile.serialize(os);
SERIALIZE_SCALAR(pc);
SERIALIZE_SCALAR(npc);
#if FULL_SYSTEM
@@ -52,7 +51,6 @@
void
RegFile::unserialize(EventManager *em, Checkpoint *cp, const string section)
{
-intRegFile.unserialize(cp, section);
UNSERIALIZE_SCALAR(pc);
UNSERIALIZE_SCALAR(npc);
#if FULL_SYSTEM
diff --git a/src/arch/alpha/regfile.hh b/src/arch/alpha/regfile.hh
--- a/src/arch/alpha/regfile.hh
+++ b/src/arch/alpha/regfile.hh
@@ -89,9 +89,6 @@
setNextNPC(Addr val)
{ }
- protected:
-IntRegFile intRegFile; // (signed) integer register file
-
public:
#if FULL_SYSTEM
int intrflag; // interrupt flag
@@ -100,19 +97,6 @@
void
clear()
{
-intRegFile.clear();
-}
-
-IntReg
-readIntReg(int intReg)
-{
-return intRegFile.readReg(intReg);
-}
-
-void
-setIntReg(int intReg, const IntReg val)
-{
-intRegFile.setReg(intReg, val);
}
void serialize(EventManager *em, std::ostream os);
diff --git a/src/arch/arm/regfile/int_regfile.hh
b/src/arch/arm/regfile/int_regfile.hh
--- a/src/arch/arm/regfile/int_regfile.hh
+++ b/src/arch/arm/regfile/int_regfile.hh
@@ -43,11 +43,6 @@
namespace ArmISA
{
-static inline std::string getIntRegName(RegIndex)
-{
-return ;
-}
-
enum MiscIntRegNums {
zero_reg = NumIntArchRegs,
addr_reg,
@@ -77,42 +72,6 @@
r14_abt
};
-class IntRegFile
-{
- protected:
-IntReg regs[NumIntRegs];
-
- public:
-IntReg readReg(int intReg)
-{
-DPRINTF(IntRegs, Reading int reg %d as %#x.\n,
-intReg, regs[intReg]);
-return regs[intReg];
-}
-
-void clear()
-{
-bzero(regs, sizeof(regs));
-}
-
-Fault setReg(int intReg, const IntReg val)
-{
-DPRINTF(IntRegs, Setting int reg %d to %#x.\n, intReg, val);
-regs[intReg] = val;
-return NoFault;
-}
-
-void serialize(std::ostream os)
-{
-SERIALIZE_ARRAY(regs, NumIntRegs);
-}
-
-void unserialize(Checkpoint *cp, const std::string section)
-{
-UNSERIALIZE_ARRAY(regs, NumIntRegs);
-}
-};
-
} // namespace ArmISA
#endif
diff --git a/src/arch/arm/regfile/regfile.cc b/src/arch/arm/regfile/regfile.cc
--- a/src/arch/arm/regfile/regfile.cc
+++ b/src/arch/arm/regfile/regfile.cc
@@ -57,7 +57,6 @@
void
RegFile::serialize(EventManager *em, ostream os)
{
-intRegFile.serialize(os);
SERIALIZE_SCALAR(npc);
SERIALIZE_SCALAR(nnpc);
}
@@ -65,7 +64,6 @@
void
RegFile::unserialize(EventManager *em, Checkpoint *cp, const string section)
{
-intRegFile.unserialize(cp, section);
[m5-dev] [PATCH 19 of 31] ARM: Flush out the ARM's int_regfile.hh
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1247032287 25200
# Node ID 6f4db071b6a035d228e232e30bdec6fe53c294ef
# Parent 1e69e4af6b8326bc39832eb283932765ca6028e8
ARM: Flush out the ARM's int_regfile.hh.
diff --git a/src/arch/arm/regfile/int_regfile.hh
b/src/arch/arm/regfile/int_regfile.hh
deleted file mode 100644
--- a/src/arch/arm/regfile/int_regfile.hh
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * Copyright (c) 2007-2008 The Florida State University
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * AS IS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Stephen Hines
- */
-
-#ifndef __ARCH_ARM_REGFILE_INT_REGFILE_HH__
-#define __ARCH_ARM_REGFILE_INT_REGFILE_HH__
-
-#include arch/arm/isa_traits.hh
-#include arch/arm/types.hh
-#include base/misc.hh
-#include base/trace.hh
-#include sim/faults.hh
-#include sim/serialize.hh
-
-class Checkpoint;
-class ThreadContext;
-
-namespace ArmISA
-{
-enum MiscIntRegNums {
-zero_reg = NumIntArchRegs,
-addr_reg,
-
-rhi,
-rlo,
-
-r8_fiq,/* FIQ mode register bank */
-r9_fiq,
-r10_fiq,
-r11_fiq,
-r12_fiq,
-
-r13_fiq, /* FIQ mode SP and LR */
-r14_fiq,
-
-r13_irq, /* IRQ mode SP and LR */
-r14_irq,
-
-r13_svc, /* SVC mode SP and LR */
-r14_svc,
-
-r13_undef, /* UNDEF mode SP and LR */
-r14_undef,
-
-r13_abt, /* ABT mode SP and LR */
-r14_abt
-};
-
-} // namespace ArmISA
-
-#endif
diff --git a/src/arch/arm/regfile/regfile.cc b/src/arch/arm/regfile/regfile.cc
--- a/src/arch/arm/regfile/regfile.cc
+++ b/src/arch/arm/regfile/regfile.cc
@@ -29,6 +29,7 @@
*/
#include arch/arm/regfile/regfile.hh
+#include base/misc.hh
#include sim/serialize.hh
using namespace std;
diff --git a/src/arch/arm/regfile/regfile.hh b/src/arch/arm/regfile/regfile.hh
--- a/src/arch/arm/regfile/regfile.hh
+++ b/src/arch/arm/regfile/regfile.hh
@@ -32,7 +32,6 @@
#define __ARCH_ARM_REGFILE_REGFILE_HH__
#include arch/arm/types.hh
-#include arch/arm/regfile/int_regfile.hh
#include arch/arm/regfile/misc_regfile.hh
#include sim/faults.hh
@@ -63,6 +62,35 @@
Flag_Field = 1,
Enable_Field = 6,
Cause_Field = 11
+};
+
+enum MiscIntRegNums {
+zero_reg = NumIntArchRegs,
+addr_reg,
+
+rhi,
+rlo,
+
+r8_fiq,/* FIQ mode register bank */
+r9_fiq,
+r10_fiq,
+r11_fiq,
+r12_fiq,
+
+r13_fiq, /* FIQ mode SP and LR */
+r14_fiq,
+
+r13_irq, /* IRQ mode SP and LR */
+r14_irq,
+
+r13_svc, /* SVC mode SP and LR */
+r14_svc,
+
+r13_undef, /* UNDEF mode SP and LR */
+r14_undef,
+
+r13_abt, /* ABT mode SP and LR */
+r14_abt
};
class RegFile
___
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[m5-dev] [PATCH 20 of 31] MIPS: Phase out MIPS's int_regfile.hh
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1247032307 25200
# Node ID 3258ed877cdf1c2d5652459a4e47bb07fe940096
# Parent 6f4db071b6a035d228e232e30bdec6fe53c294ef
MIPS: Phase out MIPS's int_regfile.hh.
diff --git a/src/arch/mips/regfile.cc b/src/arch/mips/regfile.cc
--- a/src/arch/mips/regfile.cc
+++ b/src/arch/mips/regfile.cc
@@ -37,7 +37,6 @@
#include arch/mips/types.hh
#include arch/mips/isa_traits.hh
#include arch/mips/mt.hh
-#include arch/mips/regfile/int_regfile.hh
#include arch/mips/regfile/misc_regfile.hh
#include sim/faults.hh
diff --git a/src/arch/mips/regfile/int_regfile.hh
b/src/arch/mips/regfile/int_regfile.hh
deleted file mode 100644
--- a/src/arch/mips/regfile/int_regfile.hh
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * Copyright (c) 2006 The Regents of The University of Michigan
- * Copyright (c) 2007 MIPS Technologies, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * AS IS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Korey Sewell
- */
-
-#ifndef __ARCH_MIPS_REGFILE_INT_REGFILE_HH__
-#define __ARCH_MIPS_REGFILE_INT_REGFILE_HH__
-
-#include arch/mips/types.hh
-#include arch/mips/isa_traits.hh
-#include base/misc.hh
-#include base/trace.hh
-#include sim/faults.hh
-
-class Checkpoint;
-
-namespace MipsISA
-{
-enum MiscIntRegNums {
- LO = NumIntArchRegs,
- HI,
- DSPACX0,
- DSPLo1,
- DSPHi1,
- DSPACX1,
- DSPLo2,
- DSPHi2,
- DSPACX2,
- DSPLo3,
- DSPHi3,
- DSPACX3,
- DSPControl,
- DSPLo0 = LO,
- DSPHi0 = HI
-};
-
-//@TODO: Implementing ShadowSets needs to
-//edit this value such that:
-//TotalArchRegs = NumIntArchRegs * ShadowSets
-const int TotalArchRegs = NumIntArchRegs;
-
-} // namespace MipsISA
-
-#endif
diff --git a/src/arch/mips/regfile/regfile.hh b/src/arch/mips/regfile/regfile.hh
--- a/src/arch/mips/regfile/regfile.hh
+++ b/src/arch/mips/regfile/regfile.hh
@@ -35,7 +35,6 @@
#include arch/mips/types.hh
#include arch/mips/isa_traits.hh
//#include arch/mips/mt.hh
-#include arch/mips/regfile/int_regfile.hh
//#include cpu/base.hh
#include sim/faults.hh
@@ -71,6 +70,30 @@
Cause_Field = 11
};
+enum MiscIntRegNums {
+ LO = NumIntArchRegs,
+ HI,
+ DSPACX0,
+ DSPLo1,
+ DSPHi1,
+ DSPACX1,
+ DSPLo2,
+ DSPHi2,
+ DSPACX2,
+ DSPLo3,
+ DSPHi3,
+ DSPACX3,
+ DSPControl,
+ DSPLo0 = LO,
+ DSPHi0 = HI
+};
+
+//@TODO: Implementing ShadowSets needs to
+//edit this value such that:
+//TotalArchRegs = NumIntArchRegs * ShadowSets
+const int TotalArchRegs = NumIntArchRegs;
+
+
class RegFile {
protected:
Addr pc;// program counter
___
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[m5-dev] [PATCH 21 of 31] X86: Phase out x86's intregfile.hh
# HG changeset patch # User Gabe Black gbl...@eecs.umich.edu # Date 1247032325 25200 # Node ID aae0868864317ce2a75fcc983824d70bca57c389 # Parent 3258ed877cdf1c2d5652459a4e47bb07fe940096 X86: Phase out x86's intregfile.hh. diff --git a/src/arch/x86/intregfile.hh b/src/arch/x86/intregfile.hh deleted file mode 100644 --- a/src/arch/x86/intregfile.hh +++ /dev/null @@ -1,102 +0,0 @@ -/* - * Copyright (c) 2003-2007 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * AS IS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - */ - -/* - * Copyright (c) 2007 The Hewlett-Packard Development Company - * All rights reserved. - * - * Redistribution and use of this software in source and binary forms, - * with or without modification, are permitted provided that the - * following conditions are met: - * - * The software must be used only for Non-Commercial Use which means any - * use which is NOT directed to receiving any direct monetary - * compensation for, or commercial advantage from such use. Illustrative - * examples of non-commercial use are academic research, personal study, - * teaching, education and corporate research development. - * Illustrative examples of commercial use are distributing products for - * commercial advantage and providing services using the software for - * commercial advantage. - * - * If you wish to use this software or functionality therein that may be - * covered by patents for commercial use, please contact: - * Director of Intellectual Property Licensing - * Office of Strategy and Technology - * Hewlett-Packard Company - * 1501 Page Mill Road - * Palo Alto, California 94304 - * - * Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. Redistributions - * in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. Neither the name of - * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. No right of - * sublicense is granted herewith. Derivatives of the software and - * output created using the software may be prepared, but only for - * Non-Commercial Uses. Derivatives of the software may be shared with - * others provided: (i) the others agree to abide by the list of - * conditions herein which includes the Non-Commercial Use restrictions; - * and (ii) such Derivatives of the software include the above copyright - * notice to acknowledge the contribution from this software where - * applicable, this list of conditions and the disclaimer below. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * AS IS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
[m5-dev] [PATCH 22 of 31] SPARC: Phase out SPARC's intregfile.hh
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1247032343 25200
# Node ID 6ef0fe52b0f8c1c6515f87557733c37123cca123
# Parent aae0868864317ce2a75fcc983824d70bca57c389
SPARC: Phase out SPARC's intregfile.hh.
diff --git a/src/arch/sparc/interrupts.hh b/src/arch/sparc/interrupts.hh
--- a/src/arch/sparc/interrupts.hh
+++ b/src/arch/sparc/interrupts.hh
@@ -34,6 +34,7 @@
#include arch/sparc/faults.hh
#include arch/sparc/isa_traits.hh
+#include arch/sparc/miscregfile.hh
#include cpu/thread_context.hh
#include params/SparcInterrupts.hh
#include sim/sim_object.hh
diff --git a/src/arch/sparc/intregfile.hh b/src/arch/sparc/intregfile.hh
deleted file mode 100644
--- a/src/arch/sparc/intregfile.hh
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * AS IS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
- * Ali Saidi
- */
-
-#ifndef __ARCH_SPARC_INTREGFILE_HH__
-#define __ARCH_SPARC_INTREGFILE_HH__
-
-#include arch/sparc/sparc_traits.hh
-
-namespace SparcISA
-{
-const int NumIntArchRegs = 32;
-const int NumIntRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroIntRegs;
-}
-
-#endif
diff --git a/src/arch/sparc/predecoder.hh b/src/arch/sparc/predecoder.hh
--- a/src/arch/sparc/predecoder.hh
+++ b/src/arch/sparc/predecoder.hh
@@ -31,6 +31,7 @@
#ifndef __ARCH_SPARC_PREDECODER_HH__
#define __ARCH_SPARC_PREDECODER_HH__
+#include arch/sparc/miscregfile.hh
#include arch/sparc/types.hh
#include base/bitfield.hh
#include base/misc.hh
diff --git a/src/arch/sparc/process.cc b/src/arch/sparc/process.cc
--- a/src/arch/sparc/process.cc
+++ b/src/arch/sparc/process.cc
@@ -32,6 +32,7 @@
#include arch/sparc/asi.hh
#include arch/sparc/handlers.hh
#include arch/sparc/isa_traits.hh
+#include arch/sparc/miscregfile.hh
#include arch/sparc/process.hh
#include arch/sparc/types.hh
#include base/loader/object_file.hh
diff --git a/src/arch/sparc/regfile.cc b/src/arch/sparc/regfile.cc
--- a/src/arch/sparc/regfile.cc
+++ b/src/arch/sparc/regfile.cc
@@ -30,6 +30,7 @@
*/
#include arch/sparc/regfile.hh
+#include arch/sparc/miscregfile.hh
#include cpu/thread_context.hh
class Checkpoint;
diff --git a/src/arch/sparc/regfile.hh b/src/arch/sparc/regfile.hh
--- a/src/arch/sparc/regfile.hh
+++ b/src/arch/sparc/regfile.hh
@@ -34,16 +34,20 @@
#include string
-#include arch/sparc/intregfile.hh
-#include arch/sparc/isa_traits.hh
#include arch/sparc/miscregfile.hh
-#include arch/sparc/types.hh
+#include arch/sparc/sparc_traits.hh
#include base/types.hh
+#include sim/serialize.hh
class Checkpoint;
+class EventManager;
+class ThreadContext;
namespace SparcISA
{
+const int NumIntArchRegs = 32;
+const int NumIntRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroIntRegs;
+
class RegFile
{
protected:
diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh
--- a/src/arch/sparc/utility.hh
+++ b/src/arch/sparc/utility.hh
@@ -33,6 +33,7 @@
#include arch/sparc/faults.hh
#include arch/sparc/isa_traits.hh
+#include arch/sparc/miscregfile.hh
#include arch/sparc/tlb.hh
#include base/misc.hh
#include base/bitfield.hh
___
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[m5-dev] [PATCH 23 of 31] Alpha: Phase out Alpha's intregfile.hh and intregfile.cc
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1247032355 25200
# Node ID d8a15ef0b98a97ffc001da822a1e181c15f4e51d
# Parent 6ef0fe52b0f8c1c6515f87557733c37123cca123
Alpha: Phase out Alpha's intregfile.hh and intregfile.cc.
diff --git a/src/arch/alpha/SConscript b/src/arch/alpha/SConscript
--- a/src/arch/alpha/SConscript
+++ b/src/arch/alpha/SConscript
@@ -34,7 +34,6 @@
if env['TARGET_ISA'] == 'alpha':
Source('ev5.cc')
Source('faults.cc')
-Source('intregfile.cc')
Source('ipr.cc')
Source('isa.cc')
Source('miscregfile.cc')
diff --git a/src/arch/alpha/intregfile.cc b/src/arch/alpha/intregfile.cc
deleted file mode 100644
--- a/src/arch/alpha/intregfile.cc
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * AS IS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Steve Reinhardt
- * Gabe Black
- * Kevin Lim
- */
-
-#include arch/alpha/intregfile.hh
-
-namespace AlphaISA {
-
-#if FULL_SYSTEM
-const int reg_redir[NumIntRegs] = {
-/* 0 */ 0, 1, 2, 3, 4, 5, 6, 7,
-/* 8 */ 32, 33, 34, 35, 36, 37, 38, 15,
-/* 16 */ 16, 17, 18, 19, 20, 21, 22, 23,
-/* 24 */ 24, 39, 26, 27, 28, 29, 30, 31 };
-#else
-const int reg_redir[NumIntRegs] = {
-/* 0 */ 0, 1, 2, 3, 4, 5, 6, 7,
-/* 8 */ 8, 9, 10, 11, 12, 13, 14, 15,
-/* 16 */ 16, 17, 18, 19, 20, 21, 22, 23,
-/* 24 */ 24, 25, 26, 27, 28, 29, 30, 31 };
-#endif
-
-} // namespace AlphaISA
-
diff --git a/src/arch/alpha/intregfile.hh b/src/arch/alpha/intregfile.hh
deleted file mode 100644
--- a/src/arch/alpha/intregfile.hh
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * AS IS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Steve Reinhardt
- * Gabe Black
- */
-
-#ifndef __ARCH_ALPHA_INTREGFILE_HH__
-#define __ARCH_ALPHA_INTREGFILE_HH__
-
-#include arch/alpha/isa_traits.hh
-
-namespace AlphaISA {
-
-// redirected register map, really only
[m5-dev] [PATCH 24 of 31] MIPS: Get rid of an orphaned MIPS .cc file
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1247032533 25200
# Node ID 84d1f065dc0ada2b1999d1db2dd21ce063853bc2
# Parent d8a15ef0b98a97ffc001da822a1e181c15f4e51d
MIPS: Get rid of an orphaned MIPS .cc file.
diff --git a/src/arch/mips/regfile.cc b/src/arch/mips/regfile.cc
deleted file mode 100644
--- a/src/arch/mips/regfile.cc
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * Copyright (c) 2007 MIPS Technologies, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * AS IS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
- * Ali Saidi
- * Korey Sewell
- */
-
-#ifndef __ARCH_MIPS_REGFILE_REGFILE_HH__
-#define __ARCH_MIPS_REGFILE_REGFILE_HH__
-
-#include arch/mips/types.hh
-#include arch/mips/isa_traits.hh
-#include arch/mips/mt.hh
-#include arch/mips/regfile/misc_regfile.hh
-#include sim/faults.hh
-
-class Checkpoint;
-class ThreadContext;
-
-using namespace MipsISA;
-
-void RegFile::clear()
-{
-miscRegFile.clear();
-}
-
-void
-RegFile::reset(std::string core_name, ThreadID num_threads,
- unsigned num_vpes)
-{
-miscRegFile.reset(core_name, num_threads, num_vpes);
-}
-
-MiscReg
-RegFile::readMiscRegNoEffect(int miscReg, ThreadID tid = 0)
-{
-return miscRegFile.readRegNoEffect(miscReg, tid);
-}
-
-MiscReg
-RegFile::readMiscReg(int miscReg, ThreadContext *tc, ThreadID tid = 0)
-{
-return miscRegFile.readReg(miscReg, tc, tid);
-}
-
-void
-RegFile::setMiscRegNoEffect(int miscReg, const MiscReg val, ThreadID tid = 0)
-{
-miscRegFile.setRegNoEffect(miscReg, val, tid);
-}
-
-void
-RegFile::setMiscReg(int miscReg, const MiscReg val,
-ThreadContext *tc, ThreadID tid = 0)
-{
-miscRegFile.setReg(miscReg, val, tc, tid);
-}
-
-Addr RegFile::readPC()
-{
-return pc;
-}
-
-void RegFile::setPC(Addr val)
-{
-pc = val;
-}
-
-Addr RegFile::readNextPC()
-{
-return npc;
-}
-
-void RegFile::setNextPC(Addr val)
-{
-npc = val;
-}
-
-Addr RegFile::readNextNPC()
-{
-return nnpc;
-}
-
-void RegFile::setNextNPC(Addr val)
-{
-nnpc = val;
-}
-
-void
-RegFile::serialize(std::ostream os)
-{
-miscRegFile.serialize(os);
-
-SERIALIZE_SCALAR(pc);
-SERIALIZE_SCALAR(npc);
-SERIALIZE_SCALAR(nnpc);
-}
-
-
-void
-RegFile::unserialize(Checkpoint *cp, const std::string section)
-{
-miscRegFile.unserialize(cp, section);
-UNSERIALIZE_SCALAR(pc);
-UNSERIALIZE_SCALAR(npc);
-UNSERIALIZE_SCALAR(nnpc);
-
-}
-
-void
-MipsISA::copyRegs(ThreadContext *src, ThreadContext *dest)
-{
-panic(Copy Regs Not Implemented Yet\n);
-}
-
-void
-MipsISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest)
-{
-panic(Copy Misc. Regs Not Implemented Yet\n);
-}
___
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[m5-dev] [PATCH 25 of 31] ARM, Simple CPU: Fix an index and add assert checks
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1247032618 25200
# Node ID 69fc4de727cc87f848066ec5adc4575dfd138c49
# Parent 84d1f065dc0ada2b1999d1db2dd21ce063853bc2
ARM, Simple CPU: Fix an index and add assert checks.
diff --git a/src/arch/arm/isa_traits.hh b/src/arch/arm/isa_traits.hh
--- a/src/arch/arm/isa_traits.hh
+++ b/src/arch/arm/isa_traits.hh
@@ -33,6 +33,7 @@
#ifndef __ARCH_ARM_ISA_TRAITS_HH__
#define __ARCH_ARM_ISA_TRAITS_HH__
+#include arch/arm/max_inst_regs.hh
#include arch/arm/types.hh
#include base/types.hh
@@ -45,6 +46,8 @@
namespace ArmISA
{
using namespace LittleEndianGuest;
+using ArmISAInst::MaxInstSrcRegs;
+using ArmISAInst::MaxInstDestRegs;
StaticInstPtr decodeInst(ExtMachInst);
@@ -100,20 +103,10 @@
const int NumIntSpecialRegs = 19;
const int NumFloatArchRegs = 16;
const int NumFloatSpecialRegs = 5;
-const int NumControlRegs = 7;
const int NumInternalProcRegs = 0;
const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs;
const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;
-const int NumMiscRegs = NumControlRegs;
-
-const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
-
-const int TotalDataRegs = NumIntRegs + NumFloatRegs;
-
-// Static instruction parameters
-const int MaxInstSrcRegs = 5;
-const int MaxInstDestRegs = 3;
// semantically meaningful register indices
const int ReturnValueReg = 0;
diff --git a/src/arch/arm/regfile/misc_regfile.hh
b/src/arch/arm/regfile/misc_regfile.hh
--- a/src/arch/arm/regfile/misc_regfile.hh
+++ b/src/arch/arm/regfile/misc_regfile.hh
@@ -32,6 +32,7 @@
#define __ARCH_ARM_REGFILE_MISC_REGFILE_HH__
#include arch/arm/isa_traits.hh
+#include arch/arm/miscregs.hh
#include arch/arm/types.hh
#include sim/faults.hh
@@ -39,6 +40,8 @@
namespace ArmISA
{
+const int NumMiscRegs = NUM_MISCREGS;
+
static inline std::string getMiscRegName(RegIndex)
{
return ;
@@ -59,22 +62,26 @@
MiscReg readRegNoEffect(int misc_reg)
{
+assert(misc_reg NumMiscRegs);
return miscRegFile[misc_reg];
}
MiscReg readReg(int misc_reg, ThreadContext *tc)
{
+assert(misc_reg NumMiscRegs);
return miscRegFile[misc_reg];
}
void setRegNoEffect(int misc_reg, const MiscReg val)
{
+assert(misc_reg NumMiscRegs);
miscRegFile[misc_reg] = val;
}
void setReg(int misc_reg, const MiscReg val,
ThreadContext *tc)
{
+assert(misc_reg NumMiscRegs);
miscRegFile[misc_reg] = val;
}
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -243,36 +243,42 @@
uint64_t readIntReg(int reg_idx)
{
int flatIndex = isa.flattenIntIndex(reg_idx);
+assert(flatIndex TheISA::NumIntRegs);
return intRegs[flatIndex];
}
FloatReg readFloatReg(int reg_idx)
{
int flatIndex = isa.flattenFloatIndex(reg_idx);
+assert(flatIndex TheISA::NumFloatRegs);
return floatRegs.f[flatIndex];
}
FloatRegBits readFloatRegBits(int reg_idx)
{
int flatIndex = isa.flattenFloatIndex(reg_idx);
+assert(flatIndex TheISA::NumFloatRegs);
return floatRegs.i[flatIndex];
}
void setIntReg(int reg_idx, uint64_t val)
{
int flatIndex = isa.flattenIntIndex(reg_idx);
+assert(flatIndex TheISA::NumIntRegs);
intRegs[flatIndex] = val;
}
void setFloatReg(int reg_idx, FloatReg val)
{
int flatIndex = isa.flattenFloatIndex(reg_idx);
+assert(flatIndex TheISA::NumFloatRegs);
floatRegs.f[flatIndex] = val;
}
void setFloatRegBits(int reg_idx, FloatRegBits val)
{
int flatIndex = isa.flattenFloatIndex(reg_idx);
+assert(flatIndex TheISA::NumFloatRegs);
floatRegs.i[flatIndex] = val;
}
___
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[m5-dev] [PATCH 27 of 31] Alpha: Get rid of function prototypes with no implementations
# HG changeset patch # User Gabe Black gbl...@eecs.umich.edu # Date 1247032718 25200 # Node ID 0c71cf640a766877f362fd8fd7606d0c778079ad # Parent 2ae12bc9cb4e6c170e8c2cd363667063b406ac2a Alpha: Get rid of function prototypes with no implementations. diff --git a/src/arch/alpha/utility.hh b/src/arch/alpha/utility.hh --- a/src/arch/alpha/utility.hh +++ b/src/arch/alpha/utility.hh @@ -111,10 +111,6 @@ return 0; } -// Machine operations -void saveMachineReg(AnyReg savereg, const RegFile reg_file, int regnum); -void restoreMachineReg(RegFile regs, const AnyReg reg, int regnum); - /** * Function to insure ISA semantics about 0 registers. * @param tc The thread context. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] [PATCH 26 of 31] Registers: Move the PCs out of the ISAs and into the CPUs
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1247032696 25200
# Node ID 2ae12bc9cb4e6c170e8c2cd363667063b406ac2a
# Parent 69fc4de727cc87f848066ec5adc4575dfd138c49
Registers: Move the PCs out of the ISAs and into the CPUs.
diff --git a/src/arch/alpha/regfile.cc b/src/arch/alpha/regfile.cc
--- a/src/arch/alpha/regfile.cc
+++ b/src/arch/alpha/regfile.cc
@@ -55,8 +55,6 @@
void
RegFile::serialize(EventManager *em, ostream os)
{
-SERIALIZE_SCALAR(pc);
-SERIALIZE_SCALAR(npc);
#if FULL_SYSTEM
SERIALIZE_SCALAR(intrflag);
#endif
@@ -65,8 +63,6 @@
void
RegFile::unserialize(EventManager *em, Checkpoint *cp, const string section)
{
-UNSERIALIZE_SCALAR(pc);
-UNSERIALIZE_SCALAR(npc);
#if FULL_SYSTEM
UNSERIALIZE_SCALAR(intrflag);
#endif
diff --git a/src/arch/alpha/regfile.hh b/src/arch/alpha/regfile.hh
--- a/src/arch/alpha/regfile.hh
+++ b/src/arch/alpha/regfile.hh
@@ -32,10 +32,6 @@
#define __ARCH_ALPHA_REGFILE_HH__
#include arch/alpha/isa_traits.hh
-#include arch/alpha/miscregfile.hh
-#include arch/alpha/types.hh
-#include arch/alpha/mt.hh
-#include sim/faults.hh
#include string
@@ -51,46 +47,6 @@
extern const int reg_redir[NumIntRegs];
class RegFile {
- protected:
-Addr pc; // program counter
-Addr npc; // next-cycle program counter
-Addr nnpc; // next next-cycle program counter
-
- public:
-Addr
-readPC()
-{
-return pc;
-}
-
-void
-setPC(Addr val)
-{
-pc = val;
-}
-
-Addr
-readNextPC()
-{
-return npc;
-}
-
-void
-setNextPC(Addr val)
-{
-npc = val;
-}
-
-Addr
-readNextNPC()
-{
-return npc + sizeof(MachInst);
-}
-
-void
-setNextNPC(Addr val)
-{ }
-
public:
#if FULL_SYSTEM
int intrflag; // interrupt flag
diff --git a/src/arch/arm/regfile/regfile.cc b/src/arch/arm/regfile/regfile.cc
--- a/src/arch/arm/regfile/regfile.cc
+++ b/src/arch/arm/regfile/regfile.cc
@@ -55,18 +55,4 @@
panic(Copy Misc. Regs Not Implemented Yet\n);
}
-void
-RegFile::serialize(EventManager *em, ostream os)
-{
-SERIALIZE_SCALAR(npc);
-SERIALIZE_SCALAR(nnpc);
-}
-
-void
-RegFile::unserialize(EventManager *em, Checkpoint *cp, const string section)
-{
-UNSERIALIZE_SCALAR(npc);
-UNSERIALIZE_SCALAR(nnpc);
-}
-
} // namespace ArmISA
diff --git a/src/arch/arm/regfile/regfile.hh b/src/arch/arm/regfile/regfile.hh
--- a/src/arch/arm/regfile/regfile.hh
+++ b/src/arch/arm/regfile/regfile.hh
@@ -99,46 +99,12 @@
void clear()
{}
- protected:
-Addr pc; // program counter
-Addr npc; // next-cycle program counter
-Addr nnpc; // next-next-cycle program counter
-
- public:
-Addr readPC()
-{
-return pc;
-}
-
-void setPC(Addr val)
-{
-pc = val;
-}
-
-Addr readNextPC()
-{
-return npc;
-}
-
-void setNextPC(Addr val)
-{
-npc = val;
-}
-
-Addr readNextNPC()
-{
-return npc + sizeof(MachInst);
-}
-
-void setNextNPC(Addr val)
-{
-//nnpc = val;
-}
-
-void serialize(EventManager *em, std::ostream os);
+void serialize(EventManager *em, std::ostream os)
+{}
void unserialize(EventManager *em, Checkpoint *cp,
- const std::string section);
+ const std::string section)
+{}
};
void copyRegs(ThreadContext *src, ThreadContext *dest);
diff --git a/src/arch/mips/SConscript b/src/arch/mips/SConscript
--- a/src/arch/mips/SConscript
+++ b/src/arch/mips/SConscript
@@ -36,7 +36,6 @@
Source('faults.cc')
Source('isa.cc')
Source('regfile/misc_regfile.cc')
-Source('regfile/regfile.cc')
Source('tlb.cc')
Source('pagetable.cc')
Source('utility.cc')
diff --git a/src/arch/mips/regfile/regfile.cc b/src/arch/mips/regfile/regfile.cc
deleted file mode 100644
--- a/src/arch/mips/regfile/regfile.cc
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software
[m5-dev] [PATCH 28 of 31] Registers: Eliminate the ISA defined RegFile class
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1247032814 25200
# Node ID 1914f4971a5c8c5dc043b41ec0956392b31c0bd2
# Parent 0c71cf640a766877f362fd8fd7606d0c778079ad
Registers: Eliminate the ISA defined RegFile class.
diff --git a/src/arch/alpha/miscregfile.hh b/src/arch/alpha/miscregfile.hh
--- a/src/arch/alpha/miscregfile.hh
+++ b/src/arch/alpha/miscregfile.hh
@@ -57,7 +57,6 @@
class MiscRegFile
{
public:
-friend class RegFile;
typedef uint64_t InternalProcReg;
protected:
diff --git a/src/arch/alpha/regfile.cc b/src/arch/alpha/regfile.cc
--- a/src/arch/alpha/regfile.cc
+++ b/src/arch/alpha/regfile.cc
@@ -53,22 +53,6 @@
#endif
void
-RegFile::serialize(EventManager *em, ostream os)
-{
-#if FULL_SYSTEM
-SERIALIZE_SCALAR(intrflag);
-#endif
-}
-
-void
-RegFile::unserialize(EventManager *em, Checkpoint *cp, const string section)
-{
-#if FULL_SYSTEM
-UNSERIALIZE_SCALAR(intrflag);
-#endif
-}
-
-void
copyRegs(ThreadContext *src, ThreadContext *dest)
{
// First loop through the integer registers.
diff --git a/src/arch/alpha/regfile.hh b/src/arch/alpha/regfile.hh
--- a/src/arch/alpha/regfile.hh
+++ b/src/arch/alpha/regfile.hh
@@ -46,22 +46,6 @@
// redirected register map, really only used for the full system case.
extern const int reg_redir[NumIntRegs];
-class RegFile {
- public:
-#if FULL_SYSTEM
-int intrflag; // interrupt flag
-#endif // FULL_SYSTEM
-
-void
-clear()
-{
-}
-
-void serialize(EventManager *em, std::ostream os);
-void unserialize(EventManager *em, Checkpoint *cp,
-const std::string section);
-};
-
void copyRegs(ThreadContext *src, ThreadContext *dest);
void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -433,7 +433,6 @@
{
#if FULL_SYSTEM
DPRINTF(Arm,%s encountered.\n, name());
- //RegFile *Reg = tc-getRegFilePtr(); // Get pointer to the register fil
setExceptionState(tc,0x0A);
Addr HandlerBase;
@@ -469,7 +468,6 @@
{
#if FULL_SYSTEM
DPRINTF(Arm,%s encountered.\n, name());
- //RegFile *Reg = tc-getRegFilePtr(); // Get pointer to the register fil
setExceptionState(tc,0x0A);
Addr HandlerBase;
HandlerBase= vect() + tc-readMiscRegNoEffect(ArmISA::EBase); // Offset
0x180 - General Exception Vector
diff --git a/src/arch/arm/regfile/misc_regfile.hh
b/src/arch/arm/regfile/misc_regfile.hh
--- a/src/arch/arm/regfile/misc_regfile.hh
+++ b/src/arch/arm/regfile/misc_regfile.hh
@@ -84,8 +84,6 @@
assert(misc_reg NumMiscRegs);
miscRegFile[misc_reg] = val;
}
-
-friend class RegFile;
};
} // namespace ArmISA
diff --git a/src/arch/arm/regfile/regfile.hh b/src/arch/arm/regfile/regfile.hh
--- a/src/arch/arm/regfile/regfile.hh
+++ b/src/arch/arm/regfile/regfile.hh
@@ -93,20 +93,6 @@
r14_abt
};
-class RegFile
-{
- public:
-
-void clear()
-{}
-
-void serialize(EventManager *em, std::ostream os)
-{}
-void unserialize(EventManager *em, Checkpoint *cp,
- const std::string section)
-{}
-};
-
void copyRegs(ThreadContext *src, ThreadContext *dest);
void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
diff --git a/src/arch/mips/faults.cc b/src/arch/mips/faults.cc
--- a/src/arch/mips/faults.cc
+++ b/src/arch/mips/faults.cc
@@ -435,7 +435,6 @@
{
#if FULL_SYSTEM
DPRINTF(MipsPRA,%s encountered.\n, name());
- //RegFile *Reg = tc-getRegFilePtr(); // Get pointer to the register fil
setExceptionState(tc,0x0A);
Addr HandlerBase;
@@ -471,7 +470,6 @@
{
#if FULL_SYSTEM
DPRINTF(MipsPRA,%s encountered.\n, name());
- //RegFile *Reg = tc-getRegFilePtr(); // Get pointer to the register fil
setExceptionState(tc,0x0A);
Addr HandlerBase;
HandlerBase= vect() + tc-readMiscRegNoEffect(MipsISA::EBase); // Offset
0x180 - General Exception Vector
diff --git a/src/arch/mips/regfile/misc_regfile.hh
b/src/arch/mips/regfile/misc_regfile.hh
--- a/src/arch/mips/regfile/misc_regfile.hh
+++ b/src/arch/mips/regfile/misc_regfile.hh
@@ -48,9 +48,6 @@
{
class MiscRegFile {
public:
-// Give RegFile object, private access
-friend class RegFile;
-
// The MIPS name for this file is CP0 or Coprocessor 0
typedef MiscRegFile CP0;
diff --git a/src/arch/mips/regfile/regfile.hh b/src/arch/mips/regfile/regfile.hh
--- a/src/arch/mips/regfile/regfile.hh
+++ b/src/arch/mips/regfile/regfile.hh
@@ -92,27 +92,6 @@
//TotalArchRegs = NumIntArchRegs * ShadowSets
const int TotalArchRegs = NumIntArchRegs;
-
-class RegFile {
- public:
-void clear()
-{}
-void reset(std::string core_name, ThreadID num_threads,
- unsigned num_vpes, BaseCPU *_cpu)
-{}
-
-void setShadowSet(int css)
-
[m5-dev] [PATCH 29 of 31] Alpha: Move reg_redir into its own files, and move some constants into regfile.hh
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1247033042 25200
# Node ID 963e51dbd618daf84e1e95a2861891b38311bb35
# Parent 1914f4971a5c8c5dc043b41ec0956392b31c0bd2
Alpha: Move reg_redir into its own files, and move some constants into
regfile.hh.
diff --git a/src/arch/alpha/SConscript b/src/arch/alpha/SConscript
--- a/src/arch/alpha/SConscript
+++ b/src/arch/alpha/SConscript
@@ -39,6 +39,7 @@
Source('miscregfile.cc')
Source('pagetable.cc')
Source('regfile.cc')
+Source('regredir.cc')
Source('remote_gdb.cc')
Source('tlb.cc')
Source('utility.cc')
diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa
--- a/src/arch/alpha/isa/main.isa
+++ b/src/arch/alpha/isa/main.isa
@@ -56,6 +56,7 @@
#include cmath
#include arch/alpha/miscregfile.hh
+#include arch/alpha/regredir.hh
#include base/cprintf.hh
#include base/fenv.hh
#include base/loader/symtab.hh
@@ -69,6 +70,7 @@
output exec {{
#include math.h
+#include arch/alpha/regredir.hh
#include base/cp_annotate.hh
#include sim/pseudo_inst.hh
#include arch/alpha/ipr.hh
diff --git a/src/arch/alpha/isa_traits.hh b/src/arch/alpha/isa_traits.hh
--- a/src/arch/alpha/isa_traits.hh
+++ b/src/arch/alpha/isa_traits.hh
@@ -128,21 +128,6 @@
// Constants Related to the number of registers
enum {
-NumIntArchRegs = 32,
-NumPALShadowRegs = 8,
-NumFloatArchRegs = 32,
-// @todo: Figure out what this number really should be.
-NumMiscArchRegs = 77,
-
-NumIntRegs = NumIntArchRegs + NumPALShadowRegs,
-NumFloatRegs = NumFloatArchRegs,
-NumMiscRegs = NumMiscArchRegs,
-
-TotalNumRegs =
-NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs,
-
-TotalDataRegs = NumIntRegs + NumFloatRegs,
-
// semantically meaningful register indices
ZeroReg = 31, // architecturally meaningful
// the rest of these depend on the ABI
diff --git a/src/arch/alpha/regfile.cc b/src/arch/alpha/regfile.cc
--- a/src/arch/alpha/regfile.cc
+++ b/src/arch/alpha/regfile.cc
@@ -30,6 +30,7 @@
* Kevin Lim
*/
+#include arch/alpha/isa_traits.hh
#include arch/alpha/regfile.hh
#include arch/alpha/miscregfile.hh
#include cpu/thread_context.hh
@@ -37,20 +38,6 @@
using namespace std;
namespace AlphaISA {
-
-#if FULL_SYSTEM
-const int reg_redir[NumIntRegs] = {
-/* 0 */ 0, 1, 2, 3, 4, 5, 6, 7,
-/* 8 */ 32, 33, 34, 35, 36, 37, 38, 15,
-/* 16 */ 16, 17, 18, 19, 20, 21, 22, 23,
-/* 24 */ 24, 39, 26, 27, 28, 29, 30, 31 };
-#else
-const int reg_redir[NumIntRegs] = {
-/* 0 */ 0, 1, 2, 3, 4, 5, 6, 7,
-/* 8 */ 8, 9, 10, 11, 12, 13, 14, 15,
-/* 16 */ 16, 17, 18, 19, 20, 21, 22, 23,
-/* 24 */ 24, 25, 26, 27, 28, 29, 30, 31 };
-#endif
void
copyRegs(ThreadContext *src, ThreadContext *dest)
diff --git a/src/arch/alpha/regfile.hh b/src/arch/alpha/regfile.hh
--- a/src/arch/alpha/regfile.hh
+++ b/src/arch/alpha/regfile.hh
@@ -31,20 +31,27 @@
#ifndef __ARCH_ALPHA_REGFILE_HH__
#define __ARCH_ALPHA_REGFILE_HH__
-#include arch/alpha/isa_traits.hh
+#include arch/alpha/ipr.hh
-#include string
-
-//XXX These should be implemented by someone who knows the alpha stuff better
-
-class Checkpoint;
-class EventManager;
class ThreadContext;
namespace AlphaISA {
-// redirected register map, really only used for the full system case.
-extern const int reg_redir[NumIntRegs];
+const int NumIntArchRegs = 32;
+const int NumPALShadowRegs = 8;
+const int NumFloatArchRegs = 32;
+// @todo: Figure out what this number really should be.
+const int NumMiscArchRegs = 77;
+
+const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs;
+const int NumFloatRegs = NumFloatArchRegs;
+const int NumMiscRegs = NumMiscArchRegs;
+
+const int TotalNumRegs =
+NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs;
+
+const int TotalDataRegs = NumIntRegs + NumFloatRegs;
+
void copyRegs(ThreadContext *src, ThreadContext *dest);
diff --git a/src/arch/alpha/regredir.hh b/src/arch/alpha/regredir.hh
new file mode 100644
--- /dev/null
+++ b/src/arch/alpha/regredir.hh
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2003-2009 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY
[m5-dev] [PATCH 30 of 31] Registers: Collapse ARM and MIPS regfile directories
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1247033125 25200
# Node ID 9edc4e717d8933b93fa9a8c04c663e46df6f6594
# Parent 963e51dbd618daf84e1e95a2861891b38311bb35
Registers: Collapse ARM and MIPS regfile directories.
diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript
--- a/src/arch/arm/SConscript
+++ b/src/arch/arm/SConscript
@@ -41,7 +41,7 @@
Source('insts/static_inst.cc')
Source('isa.cc')
Source('pagetable.cc')
-Source('regfile/regfile.cc')
+Source('regfile.cc')
Source('tlb.cc')
Source('vtophys.cc')
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -31,7 +31,7 @@
#ifndef __ARCH_ARM_ISA_HH__
#define __ARCH_MRM_ISA_HH__
-#include arch/arm/regfile/misc_regfile.hh
+#include arch/arm/misc_regfile.hh
#include arch/arm/types.hh
class Checkpoint;
diff --git a/src/arch/arm/regfile/misc_regfile.hh b/src/arch/arm/misc_regfile.hh
rename from src/arch/arm/regfile/misc_regfile.hh
rename to src/arch/arm/misc_regfile.hh
diff --git a/src/arch/arm/regfile/regfile.cc b/src/arch/arm/regfile.cc
rename from src/arch/arm/regfile/regfile.cc
rename to src/arch/arm/regfile.cc
--- a/src/arch/arm/regfile/regfile.cc
+++ b/src/arch/arm/regfile.cc
@@ -28,7 +28,7 @@
* Authors: Stephen Hines
*/
-#include arch/arm/regfile/regfile.hh
+#include arch/arm/regfile.hh
#include base/misc.hh
#include sim/serialize.hh
diff --git a/src/arch/arm/regfile.hh b/src/arch/arm/regfile.hh
--- a/src/arch/arm/regfile.hh
+++ b/src/arch/arm/regfile.hh
@@ -28,9 +28,75 @@
* Authors: Stephen Hines
*/
-#ifndef __ARCH_ARM_REGFILE_HH__
-#define __ARCH_ARM_REGFILE_HH__
+#ifndef __ARCH_ARM_REGFILE_REGFILE_HH__
+#define __ARCH_ARM_REGFILE_REGFILE_HH__
-#include arch/arm/regfile/regfile.hh
+#include arch/arm/types.hh
+#include arch/arm/misc_regfile.hh
+#include sim/faults.hh
+
+class Checkpoint;
+class EventManager;
+class ThreadContext;
+
+namespace ArmISA
+{
+enum FPControlRegNums {
+ FIR = NumFloatArchRegs,
+ FCCR,
+ FEXR,
+ FENR,
+ FCSR
+};
+
+enum FCSRBits {
+Inexact = 1,
+Underflow,
+Overflow,
+DivideByZero,
+Invalid,
+Unimplemented
+};
+
+enum FCSRFields {
+Flag_Field = 1,
+Enable_Field = 6,
+Cause_Field = 11
+};
+
+enum MiscIntRegNums {
+zero_reg = NumIntArchRegs,
+addr_reg,
+
+rhi,
+rlo,
+
+r8_fiq,/* FIQ mode register bank */
+r9_fiq,
+r10_fiq,
+r11_fiq,
+r12_fiq,
+
+r13_fiq, /* FIQ mode SP and LR */
+r14_fiq,
+
+r13_irq, /* IRQ mode SP and LR */
+r14_irq,
+
+r13_svc, /* SVC mode SP and LR */
+r14_svc,
+
+r13_undef, /* UNDEF mode SP and LR */
+r14_undef,
+
+r13_abt, /* ABT mode SP and LR */
+r14_abt
+};
+
+void copyRegs(ThreadContext *src, ThreadContext *dest);
+
+void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
+
+} // namespace ArmISA
#endif
diff --git a/src/arch/arm/regfile/regfile.hh b/src/arch/arm/regfile/regfile.hh
deleted file mode 100644
--- a/src/arch/arm/regfile/regfile.hh
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * Copyright (c) 2007-2008 The Florida State University
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * AS IS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Stephen Hines
- */
-
-#ifndef __ARCH_ARM_REGFILE_REGFILE_HH__
-#define
[m5-dev] [PATCH 0 of 6] First ARM regression
These patches touch up our ARM implementation and add in support for some new features including TLS, a page for the kernel to install user level helper functions, a few of those functions, and hooking in mmap2. With these patches, I can run a new hello world I compiled which will become ARM's first regression test. I wanted to send these out for review mainly because of the user level helper page/functions. I'm mostly guessing how this page (pages?) is (are) supposed to work, and I'm even guessing at what the right name is. The name I'm using, comm page, came from a post about valgrind and may be totally inaccurate. Also, the functions I implemented are paraphrased from the Linux kernel. Please let me know if there are any copyright concerns. They're generally very short, but the one for cmpxchg is a little longer. My version is dumbed down because some of the needed instructions aren't supported, so that specific one isn't copied verbatim. Steve Hines (and anyone else), could you please review these patches and let me know if I screwed anything up? ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] [PATCH 1 of 6] ARM: Update the kernel version M5 reports to 2.6.16.19
# HG changeset patch # User Gabe Black gbl...@eecs.umich.edu # Date 1244530437 25200 # Node ID 13b9bbc8d150839506c6676e7bb447ceefcbeb61 # Parent 240a5a39e56f411a1df95e4ce5f259fbbcddec75 ARM: Update the kernel version M5 reports to 2.6.16.19 diff --git a/src/arch/arm/linux/process.cc b/src/arch/arm/linux/process.cc --- a/src/arch/arm/linux/process.cc +++ b/src/arch/arm/linux/process.cc @@ -53,7 +53,7 @@ strcpy(name-sysname, Linux); strcpy(name-nodename, m5.eecs.umich.edu); -strcpy(name-release, 2.4.20); +strcpy(name-release, 2.6.16.19); strcpy(name-version, #1 Mon Aug 18 11:32:15 EDT 2003); strcpy(name-machine, arm); ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] [PATCH 4 of 6] ARM: Add a cmpxchg implementation to the comm page
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1244530437 25200
# Node ID 8eb27d634b6af3e1643ab8ca5d6e5c8d3f876ff1
# Parent d855cf72ad22de64ffefb2db0ca3ee061a37fd98
ARM: Add a cmpxchg implementation to the comm page.
This implementation does what it's supposed to (I think), but it's not atomic
and doesn't have memory barriers like the kernel's version.
diff --git a/src/arch/arm/linux/process.cc b/src/arch/arm/linux/process.cc
--- a/src/arch/arm/linux/process.cc
+++ b/src/arch/arm/linux/process.cc
@@ -482,6 +482,18 @@
swiNeg1, sizeof(swiNeg1));
}
+// This -should- be atomic, but I don't think all the support that we'd
+// need is implemented. There should also be memory barriers around it.
+uint8_t cmpxchg[] =
+{
+0x00, 0x30, 0x92, 0xe5, //ldr r3, [r2]
+0x00, 0x30, 0x53, 0xe0, //subs r3, r3, r0
+0x00, 0x10, 0x92, 0x05, //streq r1, [r2]
+0x03, 0x00, 0xa0, 0xe1, //mov r0, r3
+0x0e, 0xf0, 0xa0, 0xe1 //usr_ret lr
+};
+tc-getMemPort()-writeBlob(commPage + 0x0fc0, cmpxchg, sizeof(cmpxchg));
+
uint8_t get_tls[] =
{
0x08, 0x00, 0x9f, 0xe5, //ldr r0, [pc, #(16 - 8)]
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[m5-dev] [PATCH 5 of 6] ARM: Add a memory_barrier function to the comm page
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1244530437 25200
# Node ID 1ac3b66da1bab6e4c8321d670d56bfd53af7eab5
# Parent 8eb27d634b6af3e1643ab8ca5d6e5c8d3f876ff1
ARM: Add a memory_barrier function to the comm page.
This function doesn't actually provide a memory barrier (I don't think they're
implemented) and instead just returns.
diff --git a/src/arch/arm/linux/process.cc b/src/arch/arm/linux/process.cc
--- a/src/arch/arm/linux/process.cc
+++ b/src/arch/arm/linux/process.cc
@@ -482,6 +482,14 @@
swiNeg1, sizeof(swiNeg1));
}
+// We don't have barriers, so just return.
+uint8_t memory_barrier[] =
+{
+0x0e, 0xf0, 0xa0, 0xe1 //usr_ret lr
+};
+tc-getMemPort()-writeBlob(commPage + 0x0fa0, memory_barrier,
+sizeof(memory_barrier));
+
// This -should- be atomic, but I don't think all the support that we'd
// need is implemented. There should also be memory barriers around it.
uint8_t cmpxchg[] =
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[m5-dev] [PATCH 6 of 6] ARM: Hook in the mmap2 system call. Make ArmLinuxProcess handle 5, 6 syscall params
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1244530437 25200
# Node ID 8379905a430091750495fab821f428fca4f951b2
# Parent 1ac3b66da1bab6e4c8321d670d56bfd53af7eab5
ARM: Hook in the mmap2 system call. Make ArmLinuxProcess handle 5,6 syscall
params.
diff --git a/src/arch/arm/linux/process.cc b/src/arch/arm/linux/process.cc
--- a/src/arch/arm/linux/process.cc
+++ b/src/arch/arm/linux/process.cc
@@ -255,7 +255,7 @@
/* 189 */ SyscallDesc(putpmsg, unimplementedFunc),
/* 190 */ SyscallDesc(vfork, unimplementedFunc),
/* 191 */ SyscallDesc(getrlimit, unimplementedFunc),
-/* 192 */ SyscallDesc(mmap2, unimplementedFunc),
+/* 192 */ SyscallDesc(mmap2, mmapFuncArmLinux),
/* 193 */ SyscallDesc(truncate64, unimplementedFunc),
/* 194 */ SyscallDesc(ftruncate64, unimplementedFunc),
/* 195 */ SyscallDesc(stat64, unimplementedFunc),
@@ -509,3 +509,21 @@
};
tc-getMemPort()-writeBlob(commPage + 0x0fe0, get_tls, sizeof(get_tls));
}
+
+ArmISA::IntReg
+ArmLinuxProcess::getSyscallArg(ThreadContext *tc, int i)
+{
+// Linux apparently allows more parameter than the ABI says it should.
+// This limit may need to be increased even further.
+assert(i 6);
+return tc-readIntReg(ArgumentReg0 + i);
+}
+
+void
+ArmLinuxProcess::setSyscallArg(ThreadContext *tc, int i, ArmISA::IntReg val)
+{
+// Linux apparently allows more parameter than the ABI says it should.
+// This limit may need to be increased even further.
+assert(i 6);
+tc-setIntReg(ArgumentReg0 + i, val);
+}
diff --git a/src/arch/arm/linux/process.hh b/src/arch/arm/linux/process.hh
--- a/src/arch/arm/linux/process.hh
+++ b/src/arch/arm/linux/process.hh
@@ -44,6 +44,9 @@
void startup();
+ArmISA::IntReg getSyscallArg(ThreadContext *tc, int i);
+void setSyscallArg(ThreadContext *tc, int i, ArmISA::IntReg val);
+
/// The target system's hostname.
static const char *hostname;
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[m5-dev] [PATCH 2 of 6] ARM: Make ArmLinuxProcess understand ARM private system calls
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1244530437 25200
# Node ID 444aabc655c792ba6767192799c45a0c85862f07
# Parent 13b9bbc8d150839506c6676e7bb447ceefcbeb61
ARM: Make ArmLinuxProcess understand ARM private system calls.
diff --git a/src/arch/arm/linux/process.cc b/src/arch/arm/linux/process.cc
--- a/src/arch/arm/linux/process.cc
+++ b/src/arch/arm/linux/process.cc
@@ -411,20 +411,36 @@
/* 346 */ SyscallDesc(epoll_pwait, unimplementedFunc),
};
+SyscallDesc ArmLinuxProcess::privSyscallDescs[] = {
+/* 1 */ SyscallDesc(breakpoint, unimplementedFunc),
+/* 2 */ SyscallDesc(cacheflush, unimplementedFunc),
+/* 3 */ SyscallDesc(usr26, unimplementedFunc),
+/* 4 */ SyscallDesc(usr32, unimplementedFunc),
+/* 5 */ SyscallDesc(set_tls, unimplementedFunc)
+};
+
ArmLinuxProcess::ArmLinuxProcess(LiveProcessParams * params,
ObjectFile *objFile)
: ArmLiveProcess(params, objFile),
- Num_Syscall_Descs(sizeof(syscallDescs) / sizeof(SyscallDesc))
+ Num_Syscall_Descs(sizeof(syscallDescs) / sizeof(SyscallDesc)),
+ Num_Priv_Syscall_Descs(sizeof(privSyscallDescs) / sizeof(SyscallDesc))
{ }
SyscallDesc*
ArmLinuxProcess::getDesc(int callnum)
{
// Angel SWI syscalls are unsupported in this release
-if (callnum == 0x123456)
+if (callnum == 0x123456) {
panic(Attempt to execute an ANGEL_SWI system call (newlib-related));
-else if ((callnum 0x00f0) == 0x0090)
+} else if ((callnum 0x00f0) == 0x0090) {
callnum = 0x000f;
+if ((callnum 0x0f) == 0xf) {
+callnum -= 0x0f0001;
+if (callnum 0 || callnum Num_Priv_Syscall_Descs)
+return NULL;
+return privSyscallDescs[callnum];
+}
+}
// Linux syscalls have to strip off the 0x0090
if (callnum 0 || callnum Num_Syscall_Descs)
diff --git a/src/arch/arm/linux/process.hh b/src/arch/arm/linux/process.hh
--- a/src/arch/arm/linux/process.hh
+++ b/src/arch/arm/linux/process.hh
@@ -45,10 +45,15 @@
/// The target system's hostname.
static const char *hostname;
- /// Array of syscall descriptors, indexed by call number.
+/// Array of syscall descriptors, indexed by call number.
static SyscallDesc syscallDescs[];
+/// Array of arm private syscall descriptors.
+static SyscallDesc privSyscallDescs[];
+
const int Num_Syscall_Descs;
+
+const int Num_Priv_Syscall_Descs;
};
#endif // __ARM_LINUX_PROCESS_HH__
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[m5-dev] [PATCH] CPU: Defer completing an access until we're no longer running out of initiateAcc
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1241318863 25200
# Node ID 8876c73dde1b40863d98fadb1524536eb333a658
# Parent af13ed3bea4884454325d5e05d7e9d2ff54e7301
CPU: Defer completing an access until we're no longer running out of
initiateAcc.
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -105,7 +105,7 @@
TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p)
: BaseSimpleCPU(p), fetchTranslation(this), icachePort(this, p-clock),
-dcachePort(this, p-clock), fetchEvent(this)
+dcachePort(this, p-clock), completeAccessEvent(this), fetchEvent(this)
{
_status = Idle;
@@ -275,7 +275,7 @@
delete data;
delete req;
-translationFault(fault);
+delayAccessCompletion(fault);
return;
}
PacketPtr pkt;
@@ -284,7 +284,7 @@
if (req-getFlags().isSet(Request::NO_ACCESS)) {
assert(!dcache_pkt);
pkt-makeResponse();
-completeDataAccess(pkt);
+delayAccessCompletion(pkt);
} else if (read) {
handleReadPacket(pkt);
} else {
@@ -302,7 +302,7 @@
handleWritePacket();
} else {
_status = DcacheWaitResponse;
-completeDataAccess(pkt);
+delayAccessCompletion(pkt);
}
}
}
@@ -318,9 +318,9 @@
delete req1;
delete req2;
if (fault1 != NoFault)
-translationFault(fault1);
+delayAccessCompletion(fault1);
else if (fault2 != NoFault)
-translationFault(fault2);
+delayAccessCompletion(fault2);
return;
}
PacketPtr pkt1, pkt2;
@@ -328,7 +328,7 @@
if (req-getFlags().isSet(Request::NO_ACCESS)) {
assert(!dcache_pkt);
pkt1-makeResponse();
-completeDataAccess(pkt1);
+delayAccessCompletion(pkt1);
} else if (read) {
if (handleReadPacket(pkt1)) {
SplitFragmentSenderState * send_state =
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -309,8 +309,51 @@
};
+struct CompleteAccessEvent : public Event
+{
+PacketPtr pkt;
+Fault fault;
+TimingSimpleCPU *cpu;
+
+CompleteAccessEvent(TimingSimpleCPU *_cpu)
+: cpu(_cpu) {}
+
+void
+process()
+{
+if (fault != NoFault) {
+cpu-translationFault(fault);
+} else {
+cpu-completeDataAccess(pkt);
+}
+}
+const char
+*description() const
+{
+return Delayed data access completion;
+}
+};
+
IcachePort icachePort;
DcachePort dcachePort;
+
+CompleteAccessEvent completeAccessEvent;
+
+void
+delayAccessCompletion(PacketPtr pkt)
+{
+completeAccessEvent.pkt = pkt;
+completeAccessEvent.fault = NoFault;
+schedule(completeAccessEvent, curTick);
+}
+
+void
+delayAccessCompletion(Fault fault)
+{
+completeAccessEvent.pkt = NULL;
+completeAccessEvent.fault = fault;
+schedule(completeAccessEvent, curTick);
+}
PacketPtr ifetch_pkt;
PacketPtr dcache_pkt;
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[m5-dev] [PATCH] CPU: Make the CPU wait until initiateAcc finishes before calling completeAcc
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1240729422 25200
# Node ID 284ff3c27bbddacf5763e7b5a54e99e4dcd1912a
# Parent 8652636856b3d24fb0088fb1af5f5dca5008d9c8
CPU: Make the CPU wait until initiateAcc finishes before calling completeAcc.
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -115,6 +115,8 @@
ifetch_pkt = dcache_pkt = NULL;
drainEvent = NULL;
previousTick = 0;
+inInitiateAcc = false;
+completionPkt = NULL;
changeState(SimObject::Running);
}
@@ -758,7 +760,13 @@
if (curStaticInst
curStaticInst-isMemRef() !curStaticInst-isDataPrefetch()) {
// load or store: just send to dcache
+inInitiateAcc = true;
Fault fault = curStaticInst-initiateAcc(this, traceData);
+inInitiateAcc = false;
+if (completionPkt) {
+completeDataAccess(completionPkt);
+completionPkt = NULL;
+}
if (_status != Running) {
// instruction will complete in dcache response callback
assert(_status == DcacheWaitResponse ||
@@ -856,6 +864,10 @@
void
TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
{
+if (inInitiateAcc) {
+completionPkt = pkt;
+return;
+}
// received a response from the dcache: complete the load or store
// instruction
assert(!pkt-isError());
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -317,6 +317,9 @@
Tick previousTick;
+bool inInitiateAcc;
+PacketPtr completionPkt;
+
public:
virtual Port *getPort(const std::string if_name, int idx = -1);
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[m5-dev] [PATCH] SPARC: Tighten up the clone system call and SPARCs copyRegs
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1240469552 25200
# Node ID 5a407ba6230735ed175c5b7a33fc4b5f083d1c2c
# Parent babe6d1f91f78fd1d1be9b7dc2ae3395f74befbe
SPARC: Tighten up the clone system call and SPARCs copyRegs.
diff --git a/src/arch/sparc/regfile.cc b/src/arch/sparc/regfile.cc
--- a/src/arch/sparc/regfile.cc
+++ b/src/arch/sparc/regfile.cc
@@ -359,19 +359,20 @@
for (int x = 0; x MaxGL; ++x) {
src-setMiscRegNoEffect(MISCREG_GL, x);
dest-setMiscRegNoEffect(MISCREG_GL, x);
-for (int y = 0; y 8; y++)
+// Skip %g0 which is always zero.
+for (int y = 1; y 8; y++)
dest-setIntReg(y, src-readIntReg(y));
}
-//Locals/Ins/Outs
+//Locals and ins. Outs are all also ins.
for (int x = 0; x NWindows; ++x) {
src-setMiscRegNoEffect(MISCREG_CWP, x);
dest-setMiscRegNoEffect(MISCREG_CWP, x);
- for (int y = 8; y 32; y++)
+ for (int y = 16; y 32; y++)
dest-setIntReg(y, src-readIntReg(y));
}
-//MicroIntRegs
-for (int y = 0; y NumMicroIntRegs; ++y)
-dest-setIntReg(y+32, src-readIntReg(y+32));
+//Microcode reg and pseudo int regs (misc regs in the integer regfile).
+for (int y = NumIntArchRegs; y NumIntArchRegs + NumMicroIntRegs; ++y)
+dest-setIntReg(y, src-readIntReg(y));
//Restore src's GL, CWP
src-setMiscRegNoEffect(MISCREG_GL, old_gl);
@@ -379,7 +380,7 @@
// Then loop through the floating point registers.
-for (int i = 0; i SparcISA::NumFloatRegs; ++i) {
+for (int i = 0; i SparcISA::NumFloatArchRegs; ++i) {
dest-setFloatRegBits(i, src-readFloatRegBits(i));
}
diff --git a/src/sim/syscall_emul.cc b/src/sim/syscall_emul.cc
--- a/src/sim/syscall_emul.cc
+++ b/src/sim/syscall_emul.cc
@@ -723,11 +723,7 @@
ctc-setPC(tc-readNextPC());
ctc-setNextPC(tc-readNextPC() + sizeof(TheISA::MachInst));
-
-// In SPARC, need NNPC too...
-#if THE_ISA == SPARC_ISA
-ctc-setNextNPC(tc-readNextNPC() + sizeof(TheISA::MachInst));
-#endif
+ctc-setNextNPC(tc-readNextNPC() + sizeof(TheISA::MachInst));
ctc-activate();
___
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[m5-dev] [PATCH] imported patch unifytlb.patch
Patch subject is complete summary.
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1236576344 25200
# Node ID 1c069851445b283974b8c1ed4102659ef86b96e4
# Parent 74bc713c71ce4e2a2e29958ff2f4c6f5c6ab6aa0
imported patch unifytlb.patch
diff --git a/src/arch/alpha/AlphaTLB.py b/src/arch/alpha/AlphaTLB.py
--- a/src/arch/alpha/AlphaTLB.py
+++ b/src/arch/alpha/AlphaTLB.py
@@ -33,15 +33,5 @@
class AlphaTLB(BaseTLB):
type = 'AlphaTLB'
-abstract = True
-size = Param.Int(TLB size)
-
-class AlphaDTB(AlphaTLB):
-type = 'AlphaDTB'
-cxx_class = 'AlphaISA::DTB'
-size = 64
-
-class AlphaITB(AlphaTLB):
-type = 'AlphaITB'
-cxx_class = 'AlphaISA::ITB'
-size = 48
+cxx_class = 'AlphaISA::TLB'
+size = Param.Int(64, TLB size)
diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc
--- a/src/arch/alpha/tlb.cc
+++ b/src/arch/alpha/tlb.cc
@@ -70,6 +70,90 @@
{
if (table)
delete [] table;
+}
+
+void
+TLB::regStats()
+{
+fetch_hits
+.name(name() + .fetch_hits)
+.desc(ITB hits);
+fetch_misses
+.name(name() + .fetch_misses)
+.desc(ITB misses);
+fetch_acv
+.name(name() + .fetch_acv)
+.desc(ITB acv);
+fetch_accesses
+.name(name() + .fetch_accesses)
+.desc(ITB accesses);
+
+fetch_accesses = fetch_hits + fetch_misses;
+
+read_hits
+.name(name() + .read_hits)
+.desc(DTB read hits)
+;
+
+read_misses
+.name(name() + .read_misses)
+.desc(DTB read misses)
+;
+
+read_acv
+.name(name() + .read_acv)
+.desc(DTB read access violations)
+;
+
+read_accesses
+.name(name() + .read_accesses)
+.desc(DTB read accesses)
+;
+
+write_hits
+.name(name() + .write_hits)
+.desc(DTB write hits)
+;
+
+write_misses
+.name(name() + .write_misses)
+.desc(DTB write misses)
+;
+
+write_acv
+.name(name() + .write_acv)
+.desc(DTB write access violations)
+;
+
+write_accesses
+.name(name() + .write_accesses)
+.desc(DTB write accesses)
+;
+
+data_hits
+.name(name() + .data_hits)
+.desc(DTB hits)
+;
+
+data_misses
+.name(name() + .data_misses)
+.desc(DTB misses)
+;
+
+data_acv
+.name(name() + .data_acv)
+.desc(DTB access violations)
+;
+
+data_accesses
+.name(name() + .data_accesses)
+.desc(DTB accesses)
+;
+
+data_hits = read_hits + write_hits;
+data_misses = read_misses + write_misses;
+data_acv = read_acv + write_acv;
+data_accesses = read_accesses + write_accesses;
}
// look up an entry in the TLB
@@ -288,36 +372,8 @@
}
}
-///
-//
-// Alpha ITB
-//
-ITB::ITB(const Params *p)
-: TLB(p)
-{}
-
-
-void
-ITB::regStats()
-{
-hits
-.name(name() + .hits)
-.desc(ITB hits);
-misses
-.name(name() + .misses)
-.desc(ITB misses);
-acv
-.name(name() + .acv)
-.desc(ITB acv);
-accesses
-.name(name() + .accesses)
-.desc(ITB accesses);
-
-accesses = hits + misses;
-}
-
Fault
-ITB::translateAtomic(RequestPtr req, ThreadContext *tc)
+TLB::translateInst(RequestPtr req, ThreadContext *tc)
{
//If this is a pal pc, then set PHYSICAL
if (FULL_SYSTEM PcPAL(req-getPC()))
@@ -326,7 +382,7 @@
if (PcPAL(req-getPC())) {
// strip off PAL PC marker (lsb is 1)
req-setPaddr((req-getVaddr() ~3) PAddrImplMask);
-hits++;
+fetch_hits++;
return NoFault;
}
@@ -335,7 +391,7 @@
} else {
// verify that this is a good virtual address
if (!validVirtualAddress(req-getVaddr())) {
-acv++;
+fetch_acv++;
return new ItbAcvFault(req-getVaddr());
}
@@ -352,7 +408,7 @@
// only valid in kernel mode
if (ICM_CM(tc-readMiscRegNoEffect(IPR_ICM)) !=
mode_kernel) {
-acv++;
+fetch_acv++;
return new ItbAcvFault(req-getVaddr());
}
@@ -373,7 +429,7 @@
asn);
if (!entry) {
-misses++;
+fetch_misses++;
return new ItbPageFault(req-getVaddr());
}
@@ -385,11 +441,11 @@
if (!(entry-xre
(1 ICM_CM(tc-readMiscRegNoEffect(IPR_ICM) {
// instruction access fault
-acv++;
+fetch_acv++;
return new ItbAcvFault(req-getVaddr());
}
-hits++;
+fetch_hits++;
}
}
@@ -401,93 +457,8 @@
}
-void
-ITB::translateTiming(RequestPtr req, ThreadContext *tc,
-Translation
[m5-dev] [PATCH 1 of 5] CPU: Get rid of translate... functions from various interface classes
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1235378626 28800
# Node ID 6556d15760b4cd662c1ea819b1e24e27f8fe77c0
# Parent 73c0f1860203e886fa9106ffe9ec573947b5
CPU: Get rid of translate... functions from various interface classes.
diff --git a/src/arch/x86/isa/microops/ldstop.isa
b/src/arch/x86/isa/microops/ldstop.isa
--- a/src/arch/x86/isa/microops/ldstop.isa
+++ b/src/arch/x86/isa/microops/ldstop.isa
@@ -454,7 +454,7 @@
Mem = Data;
Base = merge(Base, EA - SegBase, addressSize);
''');
-
+defineMicroStoreOp('Cda', 'Mem = 0;', Request::NO_ACCESS)
iop = InstObjParams(lea, Lea, 'X86ISA::LdStOp',
{code: Data = merge(Data, EA, dataSize);,
@@ -493,17 +493,6 @@
microopClasses[tia] = TiaOp
-iop = InstObjParams(cda, Cda, 'X86ISA::LdStOp',
-{code: '''
-Addr paddr;
-fault = xc-translateDataWriteAddr(EA, paddr,
-dataSize, (1 segment));
-''',
-ea_code: calculateEA})
-header_output += MicroLeaDeclare.subst(iop)
-decoder_output += MicroLdStOpConstructor.subst(iop)
-exec_output += MicroLeaExecute.subst(iop)
-
class CdaOp(LdStOp):
def __init__(self, segment, addr, disp = 0,
dataSize=env.dataSize, addressSize=env.addressSize):
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -115,9 +115,6 @@
template class T
Fault read(Addr addr, T data, unsigned flags);
-Fault translateDataReadAddr(Addr vaddr, Addr paddr,
-int size, unsigned flags);
-
/**
* Does a write to a given address.
* @param data The data to be written.
@@ -129,9 +126,6 @@
template class T
Fault write(T data, Addr addr, unsigned flags,
uint64_t *res);
-
-Fault translateDataWriteAddr(Addr vaddr, Addr paddr,
-int size, unsigned flags);
void prefetch(Addr addr, unsigned flags);
void writeHint(Addr addr, int size, unsigned flags);
@@ -857,29 +851,6 @@
};
templateclass Impl
-Fault
-BaseDynInstImpl::translateDataReadAddr(Addr vaddr, Addr paddr,
-int size, unsigned flags)
-{
-if (traceData) {
-traceData-setAddr(vaddr);
-}
-
-reqMade = true;
-Request *req = new Request();
-req-setVirt(asid, vaddr, size, flags, PC);
-req-setThreadContext(thread-contextId(), threadNumber);
-
-fault = cpu-translateDataReadReq(req, thread);
-
-if (fault == NoFault)
-paddr = req-getPaddr();
-
-delete req;
-return fault;
-}
-
-templateclass Impl
templateclass T
inline Fault
BaseDynInstImpl::read(Addr addr, T data, unsigned flags)
@@ -889,7 +860,7 @@
req-setVirt(asid, addr, sizeof(T), flags, this-PC);
req-setThreadContext(thread-contextId(), threadNumber);
-fault = cpu-translateDataReadReq(req, thread);
+fault = cpu-dtb-translate(req, thread-getTC(), false);
if (req-isUncacheable())
isUncacheable = true;
@@ -931,29 +902,6 @@
}
templateclass Impl
-Fault
-BaseDynInstImpl::translateDataWriteAddr(Addr vaddr, Addr paddr,
-int size, unsigned flags)
-{
-if (traceData) {
-traceData-setAddr(vaddr);
-}
-
-reqMade = true;
-Request *req = new Request();
-req-setVirt(asid, vaddr, size, flags, PC);
-req-setThreadContext(thread-contextId(), threadNumber);
-
-fault = cpu-translateDataWriteReq(req, thread);
-
-if (fault == NoFault)
-paddr = req-getPaddr();
-
-delete req;
-return fault;
-}
-
-templateclass Impl
templateclass T
inline Fault
BaseDynInstImpl::write(T data, Addr addr, unsigned flags, uint64_t *res)
@@ -968,7 +916,7 @@
req-setVirt(asid, addr, sizeof(T), flags, this-PC);
req-setThreadContext(thread-contextId(), threadNumber);
-fault = cpu-translateDataWriteReq(req, thread);
+fault = cpu-dtb-translate(req, thread-getTC(), true);
if (req-isUncacheable())
isUncacheable = true;
diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc
--- a/src/cpu/checker/cpu.cc
+++ b/src/cpu/checker/cpu.cc
@@ -158,8 +158,9 @@
memReq-setVirt(0, addr, sizeof(T), flags, thread-readPC());
+
// translate to physical address
-translateDataReadReq(memReq);
+dtb-translate(memReq, tc, false);
PacketPtr pkt = new Packet(memReq, Packet::ReadReq, Packet::Broadcast);
@@ -229,7 +230,7 @@
memReq-setVirt(0, addr, sizeof(T), flags, thread-readPC());
// translate to physical address
-thread-translateDataWriteReq(memReq);
+dtb-translate(memReq, tc, true);
// Can compare the write data and result only if it's cacheable,
// not a store conditional, or is a store conditional that
@@ -325,57 +326,6 @@
#endif // FULL_SYSTEM
bool
-CheckerCPU::translateInstReq(Request *req)
-{
-#if FULL_SYSTEM
-return (thread-translateInstReq(req) == NoFault);
-#else
-
[m5-dev] [PATCH 2 of 5] ISA: Replace the translate functions in the TLBs with translateAtomic
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1235378627 28800
# Node ID 2432bfd936b1e15c6b5dc043ae2abac4037f120b
# Parent 6556d15760b4cd662c1ea819b1e24e27f8fe77c0
ISA: Replace the translate functions in the TLBs with translateAtomic.
diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc
--- a/src/arch/alpha/tlb.cc
+++ b/src/arch/alpha/tlb.cc
@@ -317,7 +317,7 @@
}
Fault
-ITB::translate(RequestPtr req, ThreadContext *tc)
+ITB::translateAtomic(RequestPtr req, ThreadContext *tc)
{
//If this is a pal pc, then set PHYSICAL
if (FULL_SYSTEM PcPAL(req-getPC()))
@@ -479,7 +479,7 @@
}
Fault
-DTB::translate(RequestPtr req, ThreadContext *tc, bool write)
+DTB::translateAtomic(RequestPtr req, ThreadContext *tc, bool write)
{
Addr pc = tc-readPC();
diff --git a/src/arch/alpha/tlb.hh b/src/arch/alpha/tlb.hh
--- a/src/arch/alpha/tlb.hh
+++ b/src/arch/alpha/tlb.hh
@@ -131,7 +131,7 @@
ITB(const Params *p);
virtual void regStats();
-Fault translate(RequestPtr req, ThreadContext *tc);
+Fault translateAtomic(RequestPtr req, ThreadContext *tc);
};
class DTB : public TLB
@@ -155,7 +155,7 @@
DTB(const Params *p);
virtual void regStats();
-Fault translate(RequestPtr req, ThreadContext *tc, bool write);
+Fault translateAtomic(RequestPtr req, ThreadContext *tc, bool write);
};
} // namespace AlphaISA
diff --git a/src/arch/mips/tlb.cc b/src/arch/mips/tlb.cc
--- a/src/arch/mips/tlb.cc
+++ b/src/arch/mips/tlb.cc
@@ -310,7 +310,7 @@
}
Fault
-ITB::translate(RequestPtr req, ThreadContext *tc)
+ITB::translateAtomic(RequestPtr req, ThreadContext *tc)
{
#if !FULL_SYSTEM
Process * p = tc-getProcessPtr();
@@ -427,7 +427,7 @@
}
Fault
-DTB::translate(RequestPtr req, ThreadContext *tc, bool write)
+DTB::translateAtomic(RequestPtr req, ThreadContext *tc, bool write)
{
#if !FULL_SYSTEM
Process * p = tc-getProcessPtr();
diff --git a/src/arch/mips/tlb.hh b/src/arch/mips/tlb.hh
--- a/src/arch/mips/tlb.hh
+++ b/src/arch/mips/tlb.hh
@@ -145,7 +145,7 @@
typedef MipsTLBParams Params;
ITB(const Params *p);
-Fault translate(RequestPtr req, ThreadContext *tc);
+Fault translateAtomic(RequestPtr req, ThreadContext *tc);
};
class DTB : public TLB {
@@ -153,7 +153,8 @@
typedef MipsTLBParams Params;
DTB(const Params *p);
-Fault translate(RequestPtr req, ThreadContext *tc, bool write = false);
+Fault translateAtomic(RequestPtr req, ThreadContext *tc,
+bool write = false);
};
class UTB : public ITB, public DTB {
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -436,7 +436,7 @@
}
Fault
-ITB::translate(RequestPtr req, ThreadContext *tc)
+ITB::translateAtomic(RequestPtr req, ThreadContext *tc)
{
uint64_t tlbdata = tc-readMiscRegNoEffect(MISCREG_TLB_DATA);
@@ -549,7 +549,7 @@
}
Fault
-DTB::translate(RequestPtr req, ThreadContext *tc, bool write)
+DTB::translateAtomic(RequestPtr req, ThreadContext *tc, bool write)
{
/*
* @todo this could really use some profiling and fixing to make
diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh
--- a/src/arch/sparc/tlb.hh
+++ b/src/arch/sparc/tlb.hh
@@ -177,7 +177,7 @@
cacheEntry = NULL;
}
-Fault translate(RequestPtr req, ThreadContext *tc);
+Fault translateAtomic(RequestPtr req, ThreadContext *tc);
private:
void writeSfsr(bool write, ContextType ct,
bool se, FaultTypes ft, int asi);
@@ -199,7 +199,7 @@
cacheEntry[1] = NULL;
}
-Fault translate(RequestPtr req, ThreadContext *tc, bool write);
+Fault translateAtomic(RequestPtr req, ThreadContext *tc, bool write);
#if FULL_SYSTEM
Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -190,7 +190,8 @@
templateclass TlbFault
Fault
-TLB::translate(RequestPtr req, ThreadContext *tc, bool write, bool execute)
+TLB::translateAtomic(RequestPtr req, ThreadContext *tc,
+bool write, bool execute)
{
Addr vaddr = req-getVaddr();
DPRINTF(TLB, Translating vaddr %#x.\n, vaddr);
@@ -662,15 +663,15 @@
};
Fault
-DTB::translate(RequestPtr req, ThreadContext *tc, bool write)
+DTB::translateAtomic(RequestPtr req, ThreadContext *tc, bool write)
{
-return TLB::translateFakeDTLBFault(req, tc, write, false);
+return TLB::translateAtomicFakeDTLBFault(req, tc, write, false);
}
Fault
-ITB::translate(RequestPtr req, ThreadContext *tc)
+ITB::translateAtomic(RequestPtr req, ThreadContext *tc)
{
-return TLB::translateFakeITLBFault(req, tc, false, true);
+return TLB::translateAtomicFakeITLBFault(req, tc, false, true);
}
#if FULL_SYSTEM
diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh
--- a/src/arch/x86/tlb.hh
+++ b/src/arch/x86/tlb.hh
@@
[m5-dev] [PATCH 3 of 5] X86: Make the stupd microop not update registers in initiateAcc
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1235378628 28800
# Node ID 6883fc9e770aa72afc3e35b892215a66023ef6b2
# Parent 2432bfd936b1e15c6b5dc043ae2abac4037f120b
X86: Make the stupd microop not update registers in initiateAcc.
diff --git a/src/arch/x86/isa/microops/ldstop.isa
b/src/arch/x86/isa/microops/ldstop.isa
--- a/src/arch/x86/isa/microops/ldstop.isa
+++ b/src/arch/x86/isa/microops/ldstop.isa
@@ -228,6 +228,7 @@
fault = write(xc, Mem, EA, (%(mem_flags)s) | segment);
if(fault == NoFault)
{
+%(post_code)s;
%(op_wb)s;
}
}
@@ -252,20 +253,20 @@
if(fault == NoFault)
{
-fault = write(xc, Mem, EA, (%(mem_flags)s) | segment);
-if(fault == NoFault)
-{
-%(op_wb)s;
-}
+write(xc, Mem, EA, (%(mem_flags)s) | segment);
}
return fault;
}
}};
def template MicroStoreCompleteAcc {{
-Fault %(class_name)s::completeAcc(PacketPtr, %(CPU_exec_context)s * xc,
-Trace::InstRecord * traceData) const
+Fault %(class_name)s::completeAcc(PacketPtr pkt,
+%(CPU_exec_context)s * xc, Trace::InstRecord * traceData) const
{
+%(op_decl)s;
+%(op_rd)s;
+%(complete_code)s;
+%(op_wb)s;
return NoFault;
}
}};
@@ -419,7 +420,8 @@
defineMicroLoadOp('Ldst', 'Data = merge(Data, Mem, dataSize);',
'StoreCheck')
defineMicroLoadOp('Ldfp', 'FpData.uqw = Mem;')
-def defineMicroStoreOp(mnemonic, code, mem_flags=0):
+def defineMicroStoreOp(mnemonic, code, \
+postCode=, completeCode=, mem_flags=0):
global header_output
global decoder_output
global exec_output
@@ -430,6 +432,8 @@
# Build up the all register version of this micro op
iop = InstObjParams(name, Name, 'X86ISA::LdStOp',
{code: code,
+ post_code: postCode,
+ complete_code: completeCode,
ea_code: calculateEA,
mem_flags: mem_flags})
header_output += MicroLdStOpDeclare.subst(iop)
@@ -450,11 +454,10 @@
defineMicroStoreOp('St', 'Mem = Data;')
defineMicroStoreOp('Stfp', 'Mem = FpData.uqw;')
-defineMicroStoreOp('Stupd', '''
-Mem = Data;
-Base = merge(Base, EA - SegBase, addressSize);
-''');
-defineMicroStoreOp('Cda', 'Mem = 0;', Request::NO_ACCESS)
+defineMicroStoreOp('Stupd', 'Mem = Data;',
+'Base = merge(Base, EA - SegBase, addressSize);',
+'Base = merge(Base, pkt-req-getVaddr() - SegBase,
addressSize);');
+defineMicroStoreOp('Cda', 'Mem = 0;', mem_flags=Request::NO_ACCESS)
iop = InstObjParams(lea, Lea, 'X86ISA::LdStOp',
{code: Data = merge(Data, EA, dataSize);,
___
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Re: [m5-dev] X86 project
Thank you for reminding me of that. Unfortunately, it tests basically the inverse of what we have support for at the moment which is long mode. It would be a good starting point though. Gabe Quoting Adler, Michael michael.ad...@intel.com: I asked around here whether there is a public test suite that would work for you. Some suggested that QEMU already has a test program to do what you want for the x86 ISA. You might look there before writing one yourself. -Michael Gabe Black wrote: I changed the subject of this to try to pretend to be a little dignified. It's a stretch I realize. Anyway, I've discovered part of why the output of init I sent out earlier is garbled. The relevant chunk of the trace is below if you're curious. Finding this made me realize that it would be very useful to have a large test program that did nothing but make sure that adds add, that flags are set correctly, that if you try to access sph you get it, etc. The example programs I've run have flushed out a lot of those problems, but I'm sure there are still a lot in there. As M5 gets to be more and more correct, those bugs will be harder and harder to diagnose or even run across accidentally like they have been. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] MWAHAHAHAHAHAHAHAHAHA
I haven't looked into that yet, but I think it's probably from the file names getting garbled somehow before a call to exec. I'm not expecting that to be too hard to figure out (knock on wood). Quoting Ali Saidi sa...@umich.edu: Congrats!! What is with the file or directory not found errors? You should probably remove /sbin/login and replace it with a symlink to /bin/bash. Ali On Feb 4, 2009, at 10:04 AM, Lisa Hsu wrote: wooot! you are l33t!! :) Nice job Gabe. On Wed, Feb 4, 2009 at 4:08 AM, Gabe Black gbl...@eecs.umich.edu wrote: A little over dramatic perhaps, and it's not quite right, but tada! Again! It even echoed when I typed! Freeing unused kernel memory: 232k freed INIT: version 2.86 booting /bin/bash: /sbin/rccùü¢+: No such file or directory /bin/baahh: /sbinnrr: No such file or directory INIT: Entering runlevel: 3 /bin/bash: /sbin/rccyðLý*: No such file or directory This is (none).unknown_domain (Linux x86_64 2.6.22.9) 00:00:05 (none) login: ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] MWAHAHAHAHAHAHAHAHAHA
Even if people wouldn't normally run init (the scripts, not /sbin/init I'm assuming), there's an error here that I'd like to fix. I'm expecting it's just that a string got mangled while being copied around so I shouldn't even have to dreg kernel innards to fix it. There are few things that are next. The first thing I'd like to do, after fixing the apparent issues with the output below, is to go back and fix up the two hacks I'm aware of that I have in my tree. The first is handling TLB misses more cleanly. The second is that my syscall tracer is still just stuck to the side of the exec tracer, but that should be mostly mechanical to correct. After that, I'd like to take care of the unimplemented instructions which are being skipped/warned about, support checkpointing, set up a golden model to compare execution against somehow, start working on 32 bit support in SE, and work on propagating my new message based interrupt scheme into the other ISAs. I'd also like to try other kernel versions/compiles with other config options to see what errors those expose. Beyond that, in no particular order, I'd like to work on some sort of BIOS/boot loader set up so I can boot all the way from power on to power off, add minimal ACPI support, fill out my SMBios table, add a simple graphics device of some sort, and try to tighten up performance. Performance might actually be something to work on earlier since it would make all the other work a little more palatable. There are stretch marks on the simple CPU specifically from the microcode stuff but also unaligned memory accesses which I'd like to address at some point. Gabe Quoting nathan binkert n...@binkert.org: Woo! Super awesome! We generally don't run init and do our own thing, so it should be even easier to move forward. What's next? Nate On Wed, Feb 4, 2009 at 1:08 AM, Gabe Black gbl...@eecs.umich.edu wrote: A little over dramatic perhaps, and it's not quite right, but tada! Again! It even echoed when I typed! Freeing unused kernel memory: 232k freed INIT: version 2.86 booting /bin/bash: /sbin/rccùü¢+: No such file or directory /bin/baahh: /sbinnrr: No such file or directory INIT: Entering runlevel: 3 /bin/bash: /sbin/rccyðLý*: No such file or directory This is (none).unknown_domain (Linux x86_64 2.6.22.9) 00:00:05 (none) login: ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] Idea for error messages
I'd probably lean towards Ali's proposal due to its simplicity, but I think we'd need to run ispell on all of the messages to make sure that they're ok and I think we also need to find out how many duplicates we have because the same message is in multiple places. Yes. I don't think we have many duplicates, at least not when the the messages are meaningful. panic(crap) isn't at all helpful. And conversely if panic(Useful error message) shows up in more than one place, it would ideally have the same explanation on the same wiki page. People would need to try to be consistent with each other as far as the exact text goes though. One thing we should consider is the fact that not everyone will be using the same version of the source. If a message changes and we move the page, the old message could still be out there but have no explanation. If old wiki pages live forever that may start to get crowded. Gabe ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] syscall tracer
Quoting Geoffrey Blake bla...@umich.edu: What exactly are you trying to do with making a syscall tracer Gabe? I thought your original problem was a happening with GLIBC doing some bizarre pointer encryption/decryption and it was getting it wrong leading to a segmentation fault? That is the base problem. What I was doing manually was that since the binary is dynamically linked, I was searching for system calls in the Exec trace to find where the dynamic linker had mmapped slabs of init and libc. That was/is the only way to know that something like 0x28faff0ac850 really goes with 0x850 in the linker (or init or libc? I forget). There are patterns, but they're hard to remember and they were actually changing when I tried the small TLB size. Address space randomization seems to be sensitive to small changes in execution, so unless I was just changing the trace flags I'd have to figure out the mappings all over again. Then it occurred to me there was an easy way to automate part of that process which is where this part came from. To help find that seg fault, I'd suggest going into the kernel and placing m5_exit() calls in arch/x86/mm/fault.c in the do_page_fault() where the kernel sends a SIGSEGV to user code and that'll help track down when it happens the first time, and reduce the cruft that happens after the program halts, like printing Segmentation Fault to the serial port. I'm not sure a syscall tracer will help with finding the segfault, I have a feeling its all in glibc and some weird corner case in the ISA of the M5 implementation that is causing the bug. This version of glibc causing the fault does work on real hardware correct? I'm assuming it works on real hardware. The image I'm using is the starter file system for Gentoo, so if it didn't work there'd be a lot of annoyed people. What I did was add a trace flag for all faults in x86. Since there are no tlb miss faults, or at least those work different, the only ones that should show up are the page faults. That let me home in on the exact instruction at fault, and then though a lot of painful pattern matching find the C that spawned it. I think there's some sort of address mapping issue because the thing that set the pointer that's being garbled appears to be constructing a linked list for the heap manager. Obviously those two things shouldn't land on top of each other. Fortunately, I found the code that manipulates that as well. Unfortunately I forgot where it was, so I'll have to dumpster dive again. What I'm going to do is to find the actual address used in both cases, fortunately a statically defined global address in the faulting case, and try to figure out which one is in the wrong for using it. It's possible they both are right and the kernel is mistakenly mapping the same physical page to both addresses. In that case it'll be a little more fun to figure out, but at least I'll be working with debug information and letting gdb do the heavy lifting. It's also possible that the kernel is mapping everything right and my page table walker or TLB code is tripping things up. Gabe ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] tlb misses in x86
Sure. Also the current process is not inaccurate, or at least mostly accurate if you want to be picky, for all the ISAs except x86. Currently, translation works like this as I'm sure you know: 1. Instruction generates request. 2. CPU asks TLB to translate request possibly generating a fault. 3. If there's a fault, the request is dropped and the fault is handled. 4. If not, the translated request is sent to the memory system. 5. Get coffee while request is handled. 6. The request comes back and the instruction can be finished. The problem is that with current ISAs if there's a TLB miss that generates an architected fault which gets handled in the normal way in step 3, and normal execution fixes things up. In x86, though, a TLB miss triggers a hardware mechanism which fixes things up, and the current instruction continues as if nothing happened. In the case of a TLB miss, x86 would realistically do something more like: 1. Instruction generates request. 2. CPU asks TLB to translate request possibly generating a fault. 2.5 Get coffee while page table walk happens. 3. If there's a fault, the request is dropped and the fault is handled. 4. If not, the translated request is sent to the memory system. 5. Get coffee while request is handled. 6. The request comes back and the instruction can be finished. What I've been doing to fake this is that the TLB miss itself fixes up the TLB when it's invoked. This sort of works, except if the walk itself turns up a not present page or encounters some other problem. Then you've already started handling one fault, so there's nothing to do with the new one. The two options I mentioned before were to either: 1. Invoke the new fault from the invoke method of the TLB miss. 2. Change the CPU models so that translation can put off finishing. Gabe Quoting Korey Sewell ksew...@umich.edu: Gabe, Can you step-by-step explain what's inaccurate about the current TLB process? On Wed, Jan 14, 2009 at 6:31 PM, gbl...@eecs.umich.edu wrote: Has anyone had a chance to give this some thought? Could Kevin/Korey comment on how hard they think it would be and/or how much overhead there would be to make translation be deferrable in O3? Gabe Quoting gbl...@eecs.umich.edu: I've been putting off starting a discussion about this since I know some people are otherwise occupied, but it would be useful for it to at least be in the back of someones mind. I haven't spent a huge amount of time thinking about this recently, but I see two possible ways to handle it. 1. Translation is reworked so that it can be delayed like memory transations. In atomic mode it could be blocking and immediate, and in timing mode the CPU would get a call back. This isn't ideal because it would require changes to the CPU models which would potentially cause performance overhead for the other ISAs, potentially break ARM (more?), and would be painful to add to O3 in the long term. It's the most realistic, though, in terms of mimicking actual CPUs. 2. Make the TLB miss fault invoke whichever other faults may come up inside it's own invoke method. This would be comparatively easy, but would be inaccurate as far as performance. It also goes behind the CPU's back as far as who is in control of faults/exceptions, etc., and could cause problems with generic statistics for instance. I don't know if such statistics exist. Gabe ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev -- -- Korey L Sewell Graduate Student - PhD Candidate Computer Science Engineering University of Michigan ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] tlb misses in x86
Has anyone had a chance to give this some thought? Could Kevin/Korey comment on how hard they think it would be and/or how much overhead there would be to make translation be deferrable in O3? Gabe Quoting gbl...@eecs.umich.edu: I've been putting off starting a discussion about this since I know some people are otherwise occupied, but it would be useful for it to at least be in the back of someones mind. I haven't spent a huge amount of time thinking about this recently, but I see two possible ways to handle it. 1. Translation is reworked so that it can be delayed like memory transations. In atomic mode it could be blocking and immediate, and in timing mode the CPU would get a call back. This isn't ideal because it would require changes to the CPU models which would potentially cause performance overhead for the other ISAs, potentially break ARM (more?), and would be painful to add to O3 in the long term. It's the most realistic, though, in terms of mimicking actual CPUs. 2. Make the TLB miss fault invoke whichever other faults may come up inside it's own invoke method. This would be comparatively easy, but would be inaccurate as far as performance. It also goes behind the CPU's back as far as who is in control of faults/exceptions, etc., and could cause problems with generic statistics for instance. I don't know if such statistics exist. Gabe ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] BIOS vs. EFI
I don't plan on doing any work on this in the near future, but what are people's opinions about implementing an EFI BIOS for m5 rather than a traditional BIOS? I think EFI would be easier to implement and work with and easier to get documentation and support tools for, but a traditional BIOS would potentially be compatible with more guests. EFI supports a compatibility layer, but at that point we'd be approximating implementing both, I think. That may be ok because I think most BIOS services are ignored by most modern guests, with the fairly minor exception of a boot loader. Gabe ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] Compiling Bug
I think your change is right, but just in case could you please try tracing with
different combinations of turning on and explicitly off Exec, ExecMicro, and
ExecMacro? I sent an email recently which talked about how the new options
work.
My compiler must not have that warning, but I have seen that at work a few
times. Do we want to and is there a way to disable it? It seems a little
excessive to call that an error.
Gabe
Quoting nathan binkert n...@binkert.org:
Gabe just committed this code, and your fix looks right to me.
Nate
On Thu, Jan 8, 2009 at 11:36 AM, Rick Strong rstr...@cs.ucsd.edu wrote:
Hi all,
It appears that there is a compiler error in src/cpu/exetrace.cc for gcc
version 4.3.2 for m5dev.
scons: Building targets ...
g++ -o /home/rstrong/build/m5dev/build/ALPHA_SE/cpu/exetrace.do -c
-Wno-deprecated -pipe -fno-strict-aliasing -Wall -Wno-sign-compare
-Werror -Wundef -ggdb3 -DTHE_ISA=ALPHA_ISA -DDEBUG -DTRACING_ON=1
-Iext/dnet -I/usr/include/python2.5
-I/home/rstrong/build/m5dev/build/libelf
-I/home/rstrong/build/m5dev/build/gzstream
-I/home/rstrong/build/m5dev/build/ALPHA_SE
/home/rstrong/build/m5dev/build/ALPHA_SE/cpu/exetrace.cc
cc1plus: warnings being treated as errors
/home/rstrong/build/m5dev/build/ALPHA_SE/cpu/exetrace.cc: In member
function 'virtual void Trace::ExeTracerRecord::dump()':
/home/rstrong/build/m5dev/build/ALPHA_SE/cpu/exetrace.cc:134: error:
suggest parentheses around within ||
/home/rstrong/build/m5dev/build/ALPHA_SE/arch/alpha/isa_traits.hh: At
global scope:
/home/rstrong/build/m5dev/build/ALPHA_SE/arch/alpha/isa_traits.hh:159:
error: 'AlphaISA::SyscallPseudoReturnReg' defined but not used
scons: *** [/home/rstrong/build/m5dev/build/ALPHA_SE/cpu/exetrace.do]
Error 1
scons: building terminated because of errors.
The fix I propose below fixes this with a simple addition of an extra
set of parenthesis. Does everyone agree? Has anyone else had this
problem from m5dev?
diff -r 9279812da5ee src/cpu/exetrace.cc
--- a/src/cpu/exetrace.cc Wed Jan 07 00:05:33 2009 -0800
+++ b/src/cpu/exetrace.cc Thu Jan 08 04:13:52 2009 -0800
@@ -128,10 +128,10 @@
* complete/print when they fault.
*/
if (IsOn(ExecMacro) staticInst-isMicroop()
-(IsOn(ExecMicro)
+((IsOn(ExecMicro)
macroStaticInst staticInst-isFirstMicroop()) ||
(!IsOn(ExecMicro)
- macroStaticInst staticInst-isLastMicroop())) {
+ macroStaticInst staticInst-isLastMicroop( {
traceInst(macroStaticInst, false);
}
if (IsOn(ExecMicro) || !staticInst-isMicroop()) {
Best,
-Rick
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Re: [m5-dev] SLOOOOOOOOOOW IDE controller
Yes. I'm having network issues so it might not make it into the tree quickly. Gabe Quoting nathan binkert n...@binkert.org: I recently put the mkblankimage.sh script in m5/util. My guess is that we should remove the one from the website (with maybe a pointer to the repository) and fix the one in the tree. Can you take care of it gabe? I have the M5 ops working, but the slow IDE controller turned out to be a bug in the rdtsc (read time stamp counter) instruction and a coincidence of timing. When making a blank image using the script on the website, there was a bug which was fairly easy to fix. There was one place where sudo was used directly instead of using the run_priv (right name?) function, so if you try to run as root without using sudo it won't work. I think it was on line 154, but I haven't looked at that for a day or two so that may be completely wrong. I still haven't actually ran anything off the image I made, but I've fixed a few problems and I'm getting closer. Happy holidays everybody! ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] [PATCH] imported patch breaks.patch
# HG changeset patch
# User Gabe Black gbl...@eecs.umich.edu
# Date 1229253215 28800
# Node ID 7e36f63964a665423d687262b20129f71ef847d7
# Parent 436cb149e7563491491e8202f99d80945232fccc
imported patch breaks.patch
diff --git a/src/dev/pcidev.cc b/src/dev/pcidev.cc
--- a/src/dev/pcidev.cc
+++ b/src/dev/pcidev.cc
@@ -216,8 +216,10 @@
switch (offset) {
case PCI0_INTERRUPT_LINE:
config.interruptLine = pkt-getuint8_t();
+break;
case PCI_CACHE_LINE_SIZE:
config.cacheLineSize = pkt-getuint8_t();
+break;
case PCI_LATENCY_TIMER:
config.latencyTimer = pkt-getuint8_t();
break;
@@ -240,8 +242,10 @@
switch (offset) {
case PCI_COMMAND:
config.command = pkt-getuint8_t();
+break;
case PCI_STATUS:
config.status = pkt-getuint8_t();
+break;
case PCI_CACHE_LINE_SIZE:
config.cacheLineSize = pkt-getuint8_t();
break;
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[m5-dev] [PATCH] IDE: Fix serialization for the IDE controller
# HG changeset patch
# User Richard Strong r.d.str...@gmail.com
# Date 1228847648 28800
# Node ID 436cb149e7563491491e8202f99d80945232fccc
# Parent a7ce656e32a0253b3f0578c7e9fd0a097e1b905b
IDE: Fix serialization for the IDE controller.
diff --git a/src/dev/ide_ctrl.cc b/src/dev/ide_ctrl.cc
--- a/src/dev/ide_ctrl.cc
+++ b/src/dev/ide_ctrl.cc
@@ -524,9 +524,11 @@
SERIALIZE_SCALAR(cmdSize);
SERIALIZE_SCALAR(ctrlAddr);
SERIALIZE_SCALAR(ctrlSize);
-SERIALIZE_SCALAR((uint8_t)bmiRegs.command);
+uint8_t command = bmiRegs.command;
+SERIALIZE_SCALAR(command);
SERIALIZE_SCALAR(bmiRegs.reserved0);
-SERIALIZE_SCALAR((uint8_t)bmiRegs.status);
+uint8_t status = bmiRegs.status;
+SERIALIZE_SCALAR(status);
SERIALIZE_SCALAR(bmiRegs.reserved1);
SERIALIZE_SCALAR(bmiRegs.bmidtp);
SERIALIZE_SCALAR(selectBit);
@@ -559,16 +561,17 @@
IdeController::Channel::unserialize(
Checkpoint *cp, const std::string section)
{
-uint8_t temp;
UNSERIALIZE_SCALAR(cmdAddr);
UNSERIALIZE_SCALAR(cmdSize);
UNSERIALIZE_SCALAR(ctrlAddr);
UNSERIALIZE_SCALAR(ctrlSize);
-UNSERIALIZE_SCALAR(temp);
-bmiRegs.command = temp;
+uint8_t command;
+UNSERIALIZE_SCALAR(command);
+bmiRegs.command = command;
UNSERIALIZE_SCALAR(bmiRegs.reserved0);
-UNSERIALIZE_SCALAR(temp);
-bmiRegs.status = temp;
+uint8_t status;
+UNSERIALIZE_SCALAR(status);
+bmiRegs.status = status;
UNSERIALIZE_SCALAR(bmiRegs.reserved1);
UNSERIALIZE_SCALAR(bmiRegs.bmidtp);
UNSERIALIZE_SCALAR(selectBit);
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Re: [m5-dev] Notification from M5 Bugs
It would be nice if that happened while I'm still alive to appreciate it :) Gabe Quoting nathan binkert [EMAIL PROTECTED]: I was thinking that sometime in Jan or (probably more realistically Feb), we should try to actually release m5 2.0. I know that this is largely symbolic, but it's something that we should do. That said, we should try to get all of the TODOs and bugs in the database up to date over the next few weeks and try to determine what exactly is required for 2.0. Any opinions? Does anyone agree? Nate On Mon, Dec 8, 2008 at 2:12 PM, Flyspray m5-dev@m5sim.org wrote: THIS IS AN AUTOMATED MESSAGE, DO NOT REPLY. A new Flyspray task has been opened. Details are below. User who did this: - Ali Saidi (saidi) Attached to Project - M5 Bugs Summary - glibc reads /proc/meminfo and that can effect simulation Task Type - Bug Category - Global/Other Status - New Assigned To - Operating System - All Severity - High Priority - Normal Reported Version - 2.0beta5 Due in Version - Due Date - Undecided Details - The 20.parser benchmark tends to fail because glibc reads /proc/meminfo to determine how much memory is available in the system. qsort() uses that information to choose an algorithm to use thus depending on the host system, the guest can make a different choice. Ultimately, we need to provide a fake /proc/meminfo on open() syscalls that either has some generic info or better yet has the correct information for the simulated system. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/326 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] PCI IO BARs
Ah, ok. I see where I was getting confused. There doesn't look like there's any way to disable a BAR or force it to a particular value, correct? In reality you wouldn't force a BAR to a particular value you'd just work without it, but that way the existing models won't have to be changed. Gabe Quoting Ali Saidi [EMAIL PROTECTED]: You should setup the BARs and the BAR sizes with the BARX and BARSizeX variables. If you set the BAR to 0x1 and the size to 1024, then you would get an 1024 byte I/O space when Linux reads the bar type, writes -1 to read the bar size, and then properly configures the device. Ali On Nov 24, 2008, at 9:50 PM, Gabe Black wrote: I dug around in the lspci source a bit, and [virtual] means that the OS has assigned a resource to a device but it doesn't appear in the BARs. It shows up as the memory type because bit 0 of an unimplemented BAR is 0, but the address it prints is what the OS reports which matches with the legacy addresses. [disabled] shows up because the command registers memory bit is 0, again because lspci is misinterpreting the virtual regions as memory instead of IO. The final region of IO I'm assuming is the BMI region in our controller model, and it -is- actually set up with its BAR. So the unresolved issue here is still how do I get M5 to do this? I need to be able to set up an IO BAR and to disable any particular BAR and force an address in its place. If there's already a way to do this then please let me know. If not, I'll go ahead and cook one up. Gabe Gabe Black wrote: I've been looking at the implementation of the PCI BAR registers, and I can't see how it's possible to set up an IO decoder. The lowest bit of the BAR is supposed to be a 1 for IO addresses, and the BARs are memset to 0 in the constructor. The only way to set them that I see is to write to the BARs, but that preserves what type it is so it can never change from memory to IO. Also, the thing that sets the range for the various devices just uses the address directly without masking that bit out. What it should do is mask it out, and if it was a 1 transform the rest to an IO address somehow. Also, there doesn't seem to be any way to disable BARs, or at least not that I see. I have the mindshare PCI book, and it says that for legacy IO decoders, like what I'm trying to get to work, the BAR is not implemented. I think that means reading it returns 0, but that part is a little fuzzy. The configuration software is supposed to then recognize that this is a legacy device and turn on it's IO decoders in the command register. There doesn't seem to be any way to set this sort of thing up in the IDE controller, although that's pretty understandable since Alpha probably doesn't expect devices to end up in fixed locations. On my system my IDE controller shows up under lspci as copied below. I'm not sure how to interpret all of it, but the Memory regions actually correspond to the IO locations the legacy controllers are supposed to be at. They're marked as [disabled] which matches the description of the legacy devices, but I don't know how it determined that. They're also marked as [virtual] and I have no idea what that means either, unless it has something to do with an IO MMU. 00:0d.0 IDE interface: nVidia Corporation MCP55 IDE (rev a1) (prog- if 8a [Master SecP PriP]) Subsystem: nVidia Corporation Device c55e Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast TAbort- TAbort- MAbort- SERR- PERR- INTx- Latency: 0 (750ns min, 250ns max) Region 0: [virtual] Memory at 01f0 (32-bit, non-prefetchable) [disabled] [size=8] Region 1: [virtual] Memory at 03f0 (type 3, non-prefetchable) [disabled] [size=1] Region 2: [virtual] Memory at 0170 (32-bit, non-prefetchable) [disabled] [size=8] Region 3: [virtual] Memory at 0370 (type 3, non-prefetchable) [disabled] [size=1] Region 4: I/O ports at ec00 [size=16] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: AMD_IDE ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org
Re: [m5-dev] [PATCH 1 of 2] [mq]: make_mixie_cmdline_runnable
There's one other thing I just realized. I'm assuming you're extending the trace
stuff by modifying exetrace.cc. The idea there was that you could make your own
class which replaces or inherits from the default tracer, and then set that up
to run in an arbitrary CPU. In the python, you could then override the default
tracer your CPU class uses to be the one that does whatever special thing you
want. The class that keeps track of the execution of a particular instruction
is extensible as well if you want to add new fields, etc.
Gabe
Quoting Korey Sewell [EMAIL PROTECTED]:
# HG changeset patch
# User Korey Sewell [EMAIL PROTECTED]
# Date 1227320916 18000
# Node ID b2b20a241e923c43a6978ea42fab9be4ead71220
# Parent 6f9923f77ced7b25a7a573549fd4ca1b0a49c466
[mq]: make_mixie_cmdline_runnable
diff -r 6f9923f77ced -r b2b20a241e92 configs/common/Options.py
--- a/configs/common/Options.py Tue Nov 18 16:03:31 2008 -0500
+++ b/configs/common/Options.py Fri Nov 21 21:28:36 2008 -0500
@@ -29,6 +29,7 @@
# system options
parser.add_option(-d, --detailed, action=store_true)
parser.add_option(-t, --timing, action=store_true)
+parser.add_option(--mixie, action=store_true)
parser.add_option(-n, --num-cpus, type=int, default=1)
parser.add_option(--caches, action=store_true)
parser.add_option(--l2cache, action=store_true)
diff -r 6f9923f77ced -r b2b20a241e92 configs/common/Simulation.py
--- a/configs/common/Simulation.pyTue Nov 18 16:03:31 2008 -0500
+++ b/configs/common/Simulation.pyFri Nov 21 21:28:36 2008 -0500
@@ -43,6 +43,11 @@ def setCPUClass(options):
print O3 CPU must be used with caches
sys.exit(1)
class TmpClass(DerivO3CPU): pass
+elif options.mixie:
+if not options.caches:
+print Mixie CPU must be used with caches
+sys.exit(1)
+class TmpClass(MixieCPU): pass
else:
class TmpClass(AtomicSimpleCPU): pass
atomic = True
diff -r 6f9923f77ced -r b2b20a241e92 src/arch/mips/faults.cc
--- a/src/arch/mips/faults.cc Tue Nov 18 16:03:31 2008 -0500
+++ b/src/arch/mips/faults.cc Fri Nov 21 21:28:36 2008 -0500
@@ -461,6 +461,9 @@ void ResetFault::invoke(ThreadContext *t
tc-setNextPC(vect()+sizeof(MachInst));
tc-setNextNPC(vect()+sizeof(MachInst)+sizeof(MachInst));
DPRINTF(MipsPRA,(%x) - ResetFault::invoke : PC set to
%x,(unsigned)tc,(unsigned)tc-readPC());
+#else
+ //MixieCPU *cpu_ptr = reinterpret_castMixieCPU*(tc-getCpuPtr());
+ //cpu_ptr-miscRegFile.reset();
#endif
// Set Coprocessor 1 (Floating Point) To Usable
diff -r 6f9923f77ced -r b2b20a241e92 src/arch/mips/mt.hh
--- a/src/arch/mips/mt.hh Tue Nov 18 16:03:31 2008 -0500
+++ b/src/arch/mips/mt.hh Fri Nov 21 21:28:36 2008 -0500
@@ -68,7 +68,7 @@ getTargetThread(TC *tc)
}
template class TC
-inline void
+void
haltThread(TC *tc)
{
if (tc-status() == TC::Active) {
@@ -77,6 +77,8 @@ haltThread(TC *tc)
// Save last known PC in TCRestart
// @TODO: Needs to check if this is a branch and if so, take
previous instruction
tc-setMiscReg(TCRestart, tc-readNextPC());
+
+ //assert(0);
warn(%i: Halting thread %i in %s @ PC %x, setting restart PC to
%x, curTick, tc-threadId(), tc-getCpuPtr()-name(),
tc-readPC(), tc-readNextPC());
diff -r 6f9923f77ced -r b2b20a241e92 src/arch/mips/regfile/misc_regfile.cc
--- a/src/arch/mips/regfile/misc_regfile.cc Tue Nov 18 16:03:31 2008 -0500
+++ b/src/arch/mips/regfile/misc_regfile.cc Fri Nov 21 21:28:36 2008 -0500
@@ -179,8 +179,10 @@ int MiscRegFile:: getDataAsid()
}
//@TODO: Use MIPS STYLE CONSTANTS (e.g. TCHALT_H instead of TCH_H)
void
-MiscRegFile::reset(std::string core_name, unsigned num_threads,
- unsigned num_vpes, BaseCPU *_cpu)
+MiscRegFile::reset(std::string core_name,
+unsigned num_threads,
+ unsigned num_vpes,
+BaseCPU *_cpu)
{
DPRINTF(MipsPRA, Resetting CP0 State with %i TCs and %i VPEs\n,
num_threads, num_vpes);
@@ -588,6 +590,8 @@ MiscRegFile::updateCPU()
//@todo: add vpe/mt check here thru mvpcontrol vpecontrol regs
if (bits(tc_halt, TCH_H) == 1 || bits(tc_status, TCS_A) == 0) {
+ cout TCHALT: bits(tc_halt, TCH_H)
+ TCStatus: bits(tc_status, TCS_A) endl;
haltThread(cpu-getContext(tid));
} else if (bits(tc_halt, TCH_H) == 0 bits(tc_status, TCS_A) == 1)
{
restoreThread(cpu-getContext(tid));
diff -r 6f9923f77ced -r b2b20a241e92 src/cpu/exetrace.cc
--- a/src/cpu/exetrace.cc Tue Nov 18 16:03:31 2008 -0500
+++ b/src/cpu/exetrace.cc Fri Nov 21 21:28:36 2008 -0500
@@ -50,8 +50,21 @@ Trace::ExeTracerRecord::dump()
{
ostream outs = Trace::output();
-if (IsOn(ExecTicks))
-ccprintf(outs, %7d: , when);
+if (IsOn(ExecTicks))
+ //
Re: [m5-dev] [PATCH 1 of 2] [mq]: make_mixie_cmdline_runnable
There are changes in this patch that you undo in the next one like your
modifications to exetrace.cc. It also looks like there's some debug code in
here, specifically the lines with cout and the commented out lines. Also,
please try not to leave small whitespace changes in there.
Gabe
Quoting Korey Sewell [EMAIL PROTECTED]:
# HG changeset patch
# User Korey Sewell [EMAIL PROTECTED]
# Date 1227320916 18000
# Node ID b2b20a241e923c43a6978ea42fab9be4ead71220
# Parent 6f9923f77ced7b25a7a573549fd4ca1b0a49c466
[mq]: make_mixie_cmdline_runnable
diff -r 6f9923f77ced -r b2b20a241e92 configs/common/Options.py
--- a/configs/common/Options.py Tue Nov 18 16:03:31 2008 -0500
+++ b/configs/common/Options.py Fri Nov 21 21:28:36 2008 -0500
@@ -29,6 +29,7 @@
# system options
parser.add_option(-d, --detailed, action=store_true)
parser.add_option(-t, --timing, action=store_true)
+parser.add_option(--mixie, action=store_true)
parser.add_option(-n, --num-cpus, type=int, default=1)
parser.add_option(--caches, action=store_true)
parser.add_option(--l2cache, action=store_true)
diff -r 6f9923f77ced -r b2b20a241e92 configs/common/Simulation.py
--- a/configs/common/Simulation.pyTue Nov 18 16:03:31 2008 -0500
+++ b/configs/common/Simulation.pyFri Nov 21 21:28:36 2008 -0500
@@ -43,6 +43,11 @@ def setCPUClass(options):
print O3 CPU must be used with caches
sys.exit(1)
class TmpClass(DerivO3CPU): pass
+elif options.mixie:
+if not options.caches:
+print Mixie CPU must be used with caches
+sys.exit(1)
+class TmpClass(MixieCPU): pass
else:
class TmpClass(AtomicSimpleCPU): pass
atomic = True
diff -r 6f9923f77ced -r b2b20a241e92 src/arch/mips/faults.cc
--- a/src/arch/mips/faults.cc Tue Nov 18 16:03:31 2008 -0500
+++ b/src/arch/mips/faults.cc Fri Nov 21 21:28:36 2008 -0500
@@ -461,6 +461,9 @@ void ResetFault::invoke(ThreadContext *t
tc-setNextPC(vect()+sizeof(MachInst));
tc-setNextNPC(vect()+sizeof(MachInst)+sizeof(MachInst));
DPRINTF(MipsPRA,(%x) - ResetFault::invoke : PC set to
%x,(unsigned)tc,(unsigned)tc-readPC());
+#else
+ //MixieCPU *cpu_ptr = reinterpret_castMixieCPU*(tc-getCpuPtr());
+ //cpu_ptr-miscRegFile.reset();
#endif
// Set Coprocessor 1 (Floating Point) To Usable
diff -r 6f9923f77ced -r b2b20a241e92 src/arch/mips/mt.hh
--- a/src/arch/mips/mt.hh Tue Nov 18 16:03:31 2008 -0500
+++ b/src/arch/mips/mt.hh Fri Nov 21 21:28:36 2008 -0500
@@ -68,7 +68,7 @@ getTargetThread(TC *tc)
}
template class TC
-inline void
+void
haltThread(TC *tc)
{
if (tc-status() == TC::Active) {
@@ -77,6 +77,8 @@ haltThread(TC *tc)
// Save last known PC in TCRestart
// @TODO: Needs to check if this is a branch and if so, take
previous instruction
tc-setMiscReg(TCRestart, tc-readNextPC());
+
+ //assert(0);
warn(%i: Halting thread %i in %s @ PC %x, setting restart PC to
%x, curTick, tc-threadId(), tc-getCpuPtr()-name(),
tc-readPC(), tc-readNextPC());
diff -r 6f9923f77ced -r b2b20a241e92 src/arch/mips/regfile/misc_regfile.cc
--- a/src/arch/mips/regfile/misc_regfile.cc Tue Nov 18 16:03:31 2008 -0500
+++ b/src/arch/mips/regfile/misc_regfile.cc Fri Nov 21 21:28:36 2008 -0500
@@ -179,8 +179,10 @@ int MiscRegFile:: getDataAsid()
}
//@TODO: Use MIPS STYLE CONSTANTS (e.g. TCHALT_H instead of TCH_H)
void
-MiscRegFile::reset(std::string core_name, unsigned num_threads,
- unsigned num_vpes, BaseCPU *_cpu)
+MiscRegFile::reset(std::string core_name,
+unsigned num_threads,
+ unsigned num_vpes,
+BaseCPU *_cpu)
{
DPRINTF(MipsPRA, Resetting CP0 State with %i TCs and %i VPEs\n,
num_threads, num_vpes);
@@ -588,6 +590,8 @@ MiscRegFile::updateCPU()
//@todo: add vpe/mt check here thru mvpcontrol vpecontrol regs
if (bits(tc_halt, TCH_H) == 1 || bits(tc_status, TCS_A) == 0) {
+ cout TCHALT: bits(tc_halt, TCH_H)
+ TCStatus: bits(tc_status, TCS_A) endl;
haltThread(cpu-getContext(tid));
} else if (bits(tc_halt, TCH_H) == 0 bits(tc_status, TCS_A) == 1)
{
restoreThread(cpu-getContext(tid));
diff -r 6f9923f77ced -r b2b20a241e92 src/cpu/exetrace.cc
--- a/src/cpu/exetrace.cc Tue Nov 18 16:03:31 2008 -0500
+++ b/src/cpu/exetrace.cc Fri Nov 21 21:28:36 2008 -0500
@@ -50,8 +50,21 @@ Trace::ExeTracerRecord::dump()
{
ostream outs = Trace::output();
-if (IsOn(ExecTicks))
-ccprintf(outs, %7d: , when);
+if (IsOn(ExecTicks))
+ // {
+ //if (!stageTrace) {
+ ccprintf(outs, %7d: , when);
+/*} else {
+ //outs dec \t;
+ ccprintf(outs, );
+ for (int i=0; i stageCycle.size(); i++) {
+ if (i stageCycle.size() - 1)
+ outs dec
Re: [m5-dev] [PATCH 1 of 2] [mq]: make_mixie_cmdline_runnable
Maybe we should set up a repository for your patch queue? I wouldn't mind
helping to clean up some of the rough edges.
Gabe
Quoting nathan binkert [EMAIL PROTECTED]:
How about when Korey's ready, he takes a break and lets us work on the
diffs a bit before they go in the tree? Let us know when you're ready
Korey.
On Mon, Nov 24, 2008 at 5:41 PM, [EMAIL PROTECTED] wrote:
There are changes in this patch that you undo in the next one like your
modifications to exetrace.cc. It also looks like there's some debug code in
here, specifically the lines with cout and the commented out lines. Also,
please try not to leave small whitespace changes in there.
Gabe
Quoting Korey Sewell [EMAIL PROTECTED]:
# HG changeset patch
# User Korey Sewell [EMAIL PROTECTED]
# Date 1227320916 18000
# Node ID b2b20a241e923c43a6978ea42fab9be4ead71220
# Parent 6f9923f77ced7b25a7a573549fd4ca1b0a49c466
[mq]: make_mixie_cmdline_runnable
diff -r 6f9923f77ced -r b2b20a241e92 configs/common/Options.py
--- a/configs/common/Options.py Tue Nov 18 16:03:31 2008 -0500
+++ b/configs/common/Options.py Fri Nov 21 21:28:36 2008 -0500
@@ -29,6 +29,7 @@
# system options
parser.add_option(-d, --detailed, action=store_true)
parser.add_option(-t, --timing, action=store_true)
+parser.add_option(--mixie, action=store_true)
parser.add_option(-n, --num-cpus, type=int, default=1)
parser.add_option(--caches, action=store_true)
parser.add_option(--l2cache, action=store_true)
diff -r 6f9923f77ced -r b2b20a241e92 configs/common/Simulation.py
--- a/configs/common/Simulation.pyTue Nov 18 16:03:31 2008 -0500
+++ b/configs/common/Simulation.pyFri Nov 21 21:28:36 2008 -0500
@@ -43,6 +43,11 @@ def setCPUClass(options):
print O3 CPU must be used with caches
sys.exit(1)
class TmpClass(DerivO3CPU): pass
+elif options.mixie:
+if not options.caches:
+print Mixie CPU must be used with caches
+sys.exit(1)
+class TmpClass(MixieCPU): pass
else:
class TmpClass(AtomicSimpleCPU): pass
atomic = True
diff -r 6f9923f77ced -r b2b20a241e92 src/arch/mips/faults.cc
--- a/src/arch/mips/faults.cc Tue Nov 18 16:03:31 2008 -0500
+++ b/src/arch/mips/faults.cc Fri Nov 21 21:28:36 2008 -0500
@@ -461,6 +461,9 @@ void ResetFault::invoke(ThreadContext *t
tc-setNextPC(vect()+sizeof(MachInst));
tc-setNextNPC(vect()+sizeof(MachInst)+sizeof(MachInst));
DPRINTF(MipsPRA,(%x) - ResetFault::invoke : PC set to
%x,(unsigned)tc,(unsigned)tc-readPC());
+#else
+ //MixieCPU *cpu_ptr = reinterpret_castMixieCPU*(tc-getCpuPtr());
+ //cpu_ptr-miscRegFile.reset();
#endif
// Set Coprocessor 1 (Floating Point) To Usable
diff -r 6f9923f77ced -r b2b20a241e92 src/arch/mips/mt.hh
--- a/src/arch/mips/mt.hh Tue Nov 18 16:03:31 2008 -0500
+++ b/src/arch/mips/mt.hh Fri Nov 21 21:28:36 2008 -0500
@@ -68,7 +68,7 @@ getTargetThread(TC *tc)
}
template class TC
-inline void
+void
haltThread(TC *tc)
{
if (tc-status() == TC::Active) {
@@ -77,6 +77,8 @@ haltThread(TC *tc)
// Save last known PC in TCRestart
// @TODO: Needs to check if this is a branch and if so, take
previous instruction
tc-setMiscReg(TCRestart, tc-readNextPC());
+
+ //assert(0);
warn(%i: Halting thread %i in %s @ PC %x, setting restart PC to
%x, curTick, tc-threadId(), tc-getCpuPtr()-name(),
tc-readPC(), tc-readNextPC());
diff -r 6f9923f77ced -r b2b20a241e92 src/arch/mips/regfile/misc_regfile.cc
--- a/src/arch/mips/regfile/misc_regfile.cc Tue Nov 18 16:03:31 2008
-0500
+++ b/src/arch/mips/regfile/misc_regfile.cc Fri Nov 21 21:28:36 2008
-0500
@@ -179,8 +179,10 @@ int MiscRegFile:: getDataAsid()
}
//@TODO: Use MIPS STYLE CONSTANTS (e.g. TCHALT_H instead of TCH_H)
void
-MiscRegFile::reset(std::string core_name, unsigned num_threads,
- unsigned num_vpes, BaseCPU *_cpu)
+MiscRegFile::reset(std::string core_name,
+unsigned num_threads,
+ unsigned num_vpes,
+BaseCPU *_cpu)
{
DPRINTF(MipsPRA, Resetting CP0 State with %i TCs and %i VPEs\n,
num_threads, num_vpes);
@@ -588,6 +590,8 @@ MiscRegFile::updateCPU()
//@todo: add vpe/mt check here thru mvpcontrol vpecontrol regs
if (bits(tc_halt, TCH_H) == 1 || bits(tc_status, TCS_A) == 0) {
+ cout TCHALT: bits(tc_halt, TCH_H)
+ TCStatus: bits(tc_status, TCS_A) endl;
haltThread(cpu-getContext(tid));
} else if (bits(tc_halt, TCH_H) == 0 bits(tc_status, TCS_A) ==
1)
{
restoreThread(cpu-getContext(tid));
diff -r 6f9923f77ced -r b2b20a241e92 src/cpu/exetrace.cc
--- a/src/cpu/exetrace.cc Tue Nov 18 16:03:31 2008 -0500
+++
Re: [m5-dev] parser error (was Re: changeset in m5: Update stats for brk fix (cset f28f020f3006).)
That makes a lot of sense. I had thought before about an SE chroot, especially when I was thinking about getting dynamic linking to work. I think it is sort of overkill, but it probably wouldn't be -that- bad to implement. It would also help protect against a crazy defunct simulation destroying everything on your machine with your privileges. Trapping /proc/ also sounds like a good idea since there's probably nothing in there the test should really be messing with. I do think we should keep parser as a regression, though. Gabe Quoting Steve Reinhardt [EMAIL PROTECTED]: Took me a lot longer than it should have in retrospect, but here's the problem (from --trace-flags=SyscallVerbose): 594199893000: global: opening file /proc/meminfo 594199893000: system.cpu: syscall open returns 4 594200152000: system.cpu: syscall fstat called w/arguments 4,140737488339680,140737488339680,0 594200152000: system.cpu: syscall fstat returns 0 [...] 594200272000: system.cpu: syscall read called w/arguments 4,46912559464448,8192,34 594200272000: system.cpu: syscall read returns 630 I don't know *why* parser opens, fstats, and reads /proc/meminfo, but that's clearly where the system dependence is coming from. As far as fixing the problem, the easiest thing would be to hack parser to not do that, or just not use parser in the regressions. If we wanted to get really fancy we could recognize /proc/meminfo as special and redirect it to some canned input. It might be worth checking in open() and warning anytime anything under /proc gets opened. Or maybe we should implement something like chroot inside of SE mode, so you could get rid of all the path-based issues by forcing everything to be relative to the working dir, and then use symlinks to set up the structure you want... powerful, but overkill for our uses IMO. Steve On Mon, Nov 17, 2008 at 7:37 PM, [EMAIL PROTECTED] wrote: Yes, I'm sure it's not a timing mode thing. The timing mode regressions didn't exist for x86 until very recently, and parser has been unstable for maybe as long as a year. Gabe Quoting Steve Reinhardt [EMAIL PROTECTED]: Interestingly, I just ran on my desktop here and on zizzer and both failed, but when I looked more closely, I see that my desktop is failing because it's running 5 fewer instructions than the reference output, while zizzer is failing because it's running 5 extra instructions. (And yes, I double-checked and they both have the same reference instruction count.) Both of these seem pretty consistent. I also checked the poolfs regression outputs and they get yet a third value, and amazingly the simple-atomic runs fail there too. All of the instruction counts vary only in the last couple of digits, so I'll just use those to summarize: ref zizzer poolfs home simple-atomic 702 702786 692 simple-timing697 702786 692 So it doesn't appear to be a timing-mode thing; that's just a side effect of us having inconsistent reference outputs for the two runs. Steve On Mon, Nov 17, 2008 at 2:53 PM, [EMAIL PROTECTED] wrote: Exactly. Or one machine will be in Ann Arbor and the other in California. Maybe it has something to do with the test checking the actual clock time/date on the host somehow? It could behave slightly differently depending on some little part of that like converting it to seconds changing the path the microcode takes for the division instruction or something. Speaking of which, I think it would be really handy to distinguish between the number of actual instructions that commit vs. the number of microops. If I have to change microcode for some reason I'd expect the later to change, but the former probably means I broke something. Gabe Quoting nathan binkert [EMAIL PROTECTED]: The biggest problem is that I've never been able to find two machines that behave differently. When things change, I can't find something that did it the old way. Nate If somebody can and wants to get a tracediff between two differently behaving versions of parser, that would go a long way to figuring out what the problem is. Gabe Quoting nathan binkert [EMAIL PROTECTED]: I more meant that it seems like an infrequently used syscall that uses an uninitilaized variable that affects the return value could easily be the result. The stats differences in both simulations are minimal and similar. Nate On Mon, Nov 17, 2008 at 12:07 PM, Steve Reinhardt [EMAIL PROTECTED] wrote: I sort of doubt it... parser has always been a bit nondeterministic, where this is just a subtle and unforeseen but deterministic side effect of a bug fix. Steve On Mon, Nov 17, 2008 at 11:57 AM, nathan binkert [EMAIL PROTECTED] wrote: Ah, so that was
Re: [m5-dev] parser error (was Re: changeset in m5: Update stats for brk fix (cset f28f020f3006).)
I'd vote for 2 since you may get unrealistic results otherwise. I don't think this is what that person on the mailing list is seeing since they're out of memory at tick 0. Gabe Quoting Ali Saidi [EMAIL PROTECTED]: I did some digging and I figured it out. There is a libc function (posix.1): int sysconf(int name). The various system parameters you can query vary from the maximum number of arguments to the number of free physical pages in the system. Parser doesn't call this function directly, however it does call qsort which checks to how much physical memory is available for use by calling sysconf(). The amount of physical memory is used to decide what algorithm is used and if enough memory can be allocated to have an additional copy of the items in memory. The glibc function falls back to returning -1 if it can't open /proc/meminfo and qsort handles this by assuming the correct amount of memory is available. So there are some options: 1) Just return -1 and warn any time an application attempts to read / proc/*; glibc will fall back or return an error however it can produce a non-optimal situation. 2) create a /proc/meminfo based on the number of free/allocated pages so that glibc makes the correct decision. I don't think anything else is really reasonable as it makes an non- optimal decision. As an aside, it seems that obreak() should error appropriately when the amount of memory requested exceeds the physical memory provided rather than fatal(). This would simply involve returning the old brk. As a second aside, it's possible that the person who is allocating 16GB of ram and still running into problems running some number of benchmarks could be running into an issue something like this. Ali On Nov 18, 2008, at 6:45 PM, Steve Reinhardt wrote: No rush... we've lived with this for quite a while, at least we know why now. On Tue, Nov 18, 2008 at 3:10 PM, nathan binkert [EMAIL PROTECTED] wrote: I added support for this kind of file mapping stuff for the m5 command so I could load multiple files into the simulator in full system mode. The python portion of this work could easily be ported to SE mode. Unless you want diffs now, I'll work on getting this stuff in the tree after ISCA. It basically allowed me to clean up all of the boot scripts and such. Nate On Tue, Nov 18, 2008 at 2:25 PM, Steve Reinhardt [EMAIL PROTECTED] wrote: Took me a lot longer than it should have in retrospect, but here's the problem (from --trace-flags=SyscallVerbose): 594199893000: global: opening file /proc/meminfo 594199893000: system.cpu: syscall open returns 4 594200152000: system.cpu: syscall fstat called w/arguments 4,140737488339680,140737488339680,0 594200152000: system.cpu: syscall fstat returns 0 [...] 594200272000: system.cpu: syscall read called w/arguments 4,46912559464448,8192,34 594200272000: system.cpu: syscall read returns 630 I don't know *why* parser opens, fstats, and reads /proc/meminfo, but that's clearly where the system dependence is coming from. As far as fixing the problem, the easiest thing would be to hack parser to not do that, or just not use parser in the regressions. If we wanted to get really fancy we could recognize /proc/meminfo as special and redirect it to some canned input. It might be worth checking in open() and warning anytime anything under /proc gets opened. Or maybe we should implement something like chroot inside of SE mode, so you could get rid of all the path-based issues by forcing everything to be relative to the working dir, and then use symlinks to set up the structure you want... powerful, but overkill for our uses IMO. Steve On Mon, Nov 17, 2008 at 7:37 PM, [EMAIL PROTECTED] wrote: Yes, I'm sure it's not a timing mode thing. The timing mode regressions didn't exist for x86 until very recently, and parser has been unstable for maybe as long as a year. Gabe Quoting Steve Reinhardt [EMAIL PROTECTED]: Interestingly, I just ran on my desktop here and on zizzer and both failed, but when I looked more closely, I see that my desktop is failing because it's running 5 fewer instructions than the reference output, while zizzer is failing because it's running 5 extra instructions. (And yes, I double-checked and they both have the same reference instruction count.) Both of these seem pretty consistent. I also checked the poolfs regression outputs and they get yet a third value, and amazingly the simple-atomic runs fail there too. All of the instruction counts vary only in the last couple of digits, so I'll just use those to summarize: ref zizzer poolfs home simple-atomic 702 702786 692 simple-timing697 702786 692 So it doesn't appear to be a timing-mode thing; that's just a side effect of us having inconsistent
Re: [m5-dev] changeset in m5: Update stats for brk fix (cset f28f020f3006).
Exactly. Or one machine will be in Ann Arbor and the other in California. Maybe it has something to do with the test checking the actual clock time/date on the host somehow? It could behave slightly differently depending on some little part of that like converting it to seconds changing the path the microcode takes for the division instruction or something. Speaking of which, I think it would be really handy to distinguish between the number of actual instructions that commit vs. the number of microops. If I have to change microcode for some reason I'd expect the later to change, but the former probably means I broke something. Gabe Quoting nathan binkert [EMAIL PROTECTED]: The biggest problem is that I've never been able to find two machines that behave differently. When things change, I can't find something that did it the old way. Nate If somebody can and wants to get a tracediff between two differently behaving versions of parser, that would go a long way to figuring out what the problem is. Gabe Quoting nathan binkert [EMAIL PROTECTED]: I more meant that it seems like an infrequently used syscall that uses an uninitilaized variable that affects the return value could easily be the result. The stats differences in both simulations are minimal and similar. Nate On Mon, Nov 17, 2008 at 12:07 PM, Steve Reinhardt [EMAIL PROTECTED] wrote: I sort of doubt it... parser has always been a bit nondeterministic, where this is just a subtle and unforeseen but deterministic side effect of a bug fix. Steve On Mon, Nov 17, 2008 at 11:57 AM, nathan binkert [EMAIL PROTECTED] wrote: Ah, so that was you. That makes sense. I seriously wonder if this or something like it is the problem with 20.parser. Nate On Mon, Nov 17, 2008 at 11:11 AM, Steve Reinhardt [EMAIL PROTECTED] wrote: changeset c5447915af50 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=c5447915af50 description: Update stats for brk fix (cset f28f020f3006). diffstat: 2 files changed, 3 insertions(+), 8 deletions(-) tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt |6 ++ tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout |5 + diffs (237 lines): diff -r 7015e400bd1d -r c5447915af50 tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt Sat Nov 15 23:42:11 2008 -0500 +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt Mon Nov 17 14:11:09 2008 -0500 @@ -1,13 +1,13 @@ -- Begin Simulation Statistics -- -host_inst_rate1243989 # Simulator instruction rate (inst/s) -host_mem_usage 207864 # Number of bytes of host memory used -host_seconds 155.50 # Real time elapsed on the host -host_tick_rate 1740014863 # Simulator tick rate (ticks/s) +host_inst_rate1229412 # Simulator instruction rate (inst/s) +host_mem_usage 207888 # Number of bytes of host memory used +host_seconds 157.35 # Real time elapsed on the host +host_tick_rate 1719613407 # Simulator tick rate (ticks/s) sim_freq 1 # Frequency of simulated ticks sim_insts 193444769 # Number of instructions simulated sim_seconds 0.270579 # Number of seconds simulated -sim_ticks270578958000 # Number of ticks simulated +sim_ticks270578573000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 57735069 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency56000 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency53000 # average ReadReq mshr miss latency @@ -31,16 +31,16 @@ system.cpu.dcache.WriteReq_accesses 18976439 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency56000 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 18975331 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 62048000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_hits 18975338 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 61656000 # number of WriteReq
Re: [m5-dev] changeset in m5: Update stats for brk fix (cset f28f020f3006).
Yes, I'm sure it's not a timing mode thing. The timing mode regressions didn't exist for x86 until very recently, and parser has been unstable for maybe as long as a year. Gabe Quoting Steve Reinhardt [EMAIL PROTECTED]: Interestingly, I just ran on my desktop here and on zizzer and both failed, but when I looked more closely, I see that my desktop is failing because it's running 5 fewer instructions than the reference output, while zizzer is failing because it's running 5 extra instructions. (And yes, I double-checked and they both have the same reference instruction count.) Both of these seem pretty consistent. I also checked the poolfs regression outputs and they get yet a third value, and amazingly the simple-atomic runs fail there too. All of the instruction counts vary only in the last couple of digits, so I'll just use those to summarize: ref zizzer poolfs home simple-atomic 702 702786 692 simple-timing697 702786 692 So it doesn't appear to be a timing-mode thing; that's just a side effect of us having inconsistent reference outputs for the two runs. Steve On Mon, Nov 17, 2008 at 2:53 PM, [EMAIL PROTECTED] wrote: Exactly. Or one machine will be in Ann Arbor and the other in California. Maybe it has something to do with the test checking the actual clock time/date on the host somehow? It could behave slightly differently depending on some little part of that like converting it to seconds changing the path the microcode takes for the division instruction or something. Speaking of which, I think it would be really handy to distinguish between the number of actual instructions that commit vs. the number of microops. If I have to change microcode for some reason I'd expect the later to change, but the former probably means I broke something. Gabe Quoting nathan binkert [EMAIL PROTECTED]: The biggest problem is that I've never been able to find two machines that behave differently. When things change, I can't find something that did it the old way. Nate If somebody can and wants to get a tracediff between two differently behaving versions of parser, that would go a long way to figuring out what the problem is. Gabe Quoting nathan binkert [EMAIL PROTECTED]: I more meant that it seems like an infrequently used syscall that uses an uninitilaized variable that affects the return value could easily be the result. The stats differences in both simulations are minimal and similar. Nate On Mon, Nov 17, 2008 at 12:07 PM, Steve Reinhardt [EMAIL PROTECTED] wrote: I sort of doubt it... parser has always been a bit nondeterministic, where this is just a subtle and unforeseen but deterministic side effect of a bug fix. Steve On Mon, Nov 17, 2008 at 11:57 AM, nathan binkert [EMAIL PROTECTED] wrote: Ah, so that was you. That makes sense. I seriously wonder if this or something like it is the problem with 20.parser. Nate On Mon, Nov 17, 2008 at 11:11 AM, Steve Reinhardt [EMAIL PROTECTED] wrote: changeset c5447915af50 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=c5447915af50 description: Update stats for brk fix (cset f28f020f3006). diffstat: 2 files changed, 3 insertions(+), 8 deletions(-) tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt | 6 ++ tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout | 5 + diffs (237 lines): diff -r 7015e400bd1d -r c5447915af50 tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt Sat Nov 15 23:42:11 2008 -0500 +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt Mon Nov 17 14:11:09 2008 -0500 @@ -1,13 +1,13 @@ -- Begin Simulation Statistics -- -host_inst_rate1243989 # Simulator instruction rate (inst/s) -host_mem_usage 207864 # Number of bytes of host memory used -host_seconds 155.50 # Real time elapsed on the host -host_tick_rate 1740014863 # Simulator tick rate (ticks/s) +host_inst_rate1229412 # Simulator instruction rate (inst/s) +host_mem_usage 207888 # Number of bytes of host memory used +host_seconds 157.35 # Real time elapsed on the host +host_tick_rate 1719613407 # Simulator tick rate (ticks/s) sim_freq 1 # Frequency of simulated ticks sim_insts 193444769 #
[m5-dev] [PATCH] refactor read/write in the simple timing CPU
# HG changeset patch
# User Gabe Black [EMAIL PROTECTED]
# Date 1226304386 28800
# Node ID cc6fe515daecdcf4a1a25660bd66c48a8d4a72d4
# Parent f186533c0dc2d948be0523b452356918124d7f57
CPU: Refactor read/write in the simple timing CPU.
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -262,6 +262,70 @@
return dcache_pkt == NULL;
}
+Fault
+TimingSimpleCPU::buildSplitPacket(PacketPtr pkt1, PacketPtr pkt2,
+RequestPtr req, Addr split_addr, uint8_t *data, bool read)
+{
+Fault fault;
+RequestPtr req1, req2;
+assert(!req-isLocked() !req-isSwap());
+req-splitOnVaddr(split_addr, req1, req2);
+
+pkt1 = pkt2 = NULL;
+if ((fault = buildPacket(pkt1, req1, read)) != NoFault ||
+(fault = buildPacket(pkt2, req2, read)) != NoFault) {
+delete req;
+delete pkt1;
+req = NULL;
+pkt1 = NULL;
+return fault;
+}
+
+req-setPhys(req1-getPaddr(), req-getSize(), req1-getFlags());
+PacketPtr pkt = new Packet(req, pkt1-cmd.responseCommand(),
+ Packet::Broadcast);
+
+pkt-dataDynamicuint8_t(data);
+pkt1-dataStaticuint8_t(data);
+pkt2-dataStaticuint8_t(data + req1-getSize());
+
+SplitMainSenderState * main_send_state = new SplitMainSenderState;
+pkt-senderState = main_send_state;
+main_send_state-fragments[0] = pkt1;
+main_send_state-fragments[1] = pkt2;
+main_send_state-outstanding = 2;
+pkt1-senderState = new SplitFragmentSenderState(pkt, 0);
+pkt2-senderState = new SplitFragmentSenderState(pkt, 1);
+return fault;
+}
+
+Fault
+TimingSimpleCPU::buildPacket(PacketPtr pkt, RequestPtr req, bool read)
+{
+Fault fault = read ? thread-translateDataReadReq(req) :
+ thread-translateDataWriteReq(req);
+MemCmd cmd;
+if (fault != NoFault) {
+delete req;
+req = NULL;
+pkt = NULL;
+return fault;
+} else if (read) {
+cmd = MemCmd::ReadReq;
+if (req-isLocked())
+cmd = MemCmd::LoadLockedReq;
+} else {
+cmd = MemCmd::WriteReq;
+if (req-isLocked()) {
+cmd = MemCmd::StoreCondReq;
+} else if (req-isSwap()) {
+cmd = MemCmd::SwapReq;
+}
+}
+pkt = new Packet(req, cmd, Packet::Broadcast);
+return NoFault;
+}
+
template class T
Fault
TimingSimpleCPU::read(Addr addr, T data, unsigned flags)
@@ -270,91 +334,35 @@
const int asid = 0;
const int thread_id = 0;
const Addr pc = thread-readPC();
-
-PacketPtr pkt;
-RequestPtr req;
-
int block_size = dcachePort.peerBlockSize();
int data_size = sizeof(T);
-Addr second_addr = roundDown(addr + data_size - 1, block_size);
+PacketPtr pkt;
+RequestPtr req = new Request(asid, addr, data_size,
+ flags, pc, _cpuId, thread_id);
-if (second_addr addr) {
-Addr first_size = second_addr - addr;
-Addr second_size = data_size - first_size;
-// Make sure we'll only need two accesses.
-assert(roundDown(second_addr + second_size - 1, block_size) ==
-second_addr);
+Addr split_addr = roundDown(addr + data_size - 1, block_size);
+assert(split_addr = addr || split_addr - addr block_size);
-/*
- * Do the translations. If something isn't going to work, find out
- * before we waste time setting up anything else.
- */
-req = new Request(asid, addr, first_size,
- flags, pc, _cpuId, thread_id);
-fault = thread-translateDataReadReq(req);
+if (split_addr addr) {
+PacketPtr pkt1, pkt2;
+this-buildSplitPacket(pkt1, pkt2, req,
+split_addr, (uint8_t *)(new T), true);
+if (handleReadPacket(pkt1)) {
+SplitFragmentSenderState * send_state =
+dynamic_castSplitFragmentSenderState *(pkt1-senderState);
+send_state-clearFromParent();
+if (handleReadPacket(pkt2)) {
+send_state =
+dynamic_castSplitFragmentSenderState
*(pkt1-senderState);
+send_state-clearFromParent();
+}
+}
+} else {
+Fault fault = buildPacket(pkt, req, true);
if (fault != NoFault) {
-delete req;
return fault;
}
-Request *second_req =
-new Request(asid, second_addr, second_size,
-flags, pc, _cpuId, thread_id);
-fault = thread-translateDataReadReq(second_req);
-if (fault != NoFault) {
-delete req;
-delete second_req;
-return fault;
-}
-
-T * data_ptr = new T;
-
-/*
- * This is the big packet that will hold the data we've gotten so far,
- * if any, and also act as the response we actually give to the
-
[m5-dev] [PATCH] updated unaligned patch
# HG changeset patch
# User Gabe Black [EMAIL PROTECTED]
# Date 1226207167 28800
# Node ID dc856beee70a0af5562dc3d83a94fb177bcd292e
# Parent d449af5378971cd0eb6bbafb84900a8f7ed50251
CPU: Make unaligned accesses work in the timing simple CPU.
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -241,57 +241,130 @@
_status = Idle;
}
+void
+TimingSimpleCPU::handleReadPacket(PacketPtr pkt)
+{
+RequestPtr req = pkt-req;
+if (req-isMmapedIpr()) {
+Tick delay;
+delay = TheISA::handleIprRead(thread-getTC(), pkt);
+new IprEvent(pkt, this, nextCycle(curTick + delay));
+_status = DcacheWaitResponse;
+dcache_pkt = NULL;
+} else if (!dcachePort.sendTiming(pkt)) {
+_status = DcacheRetry;
+dcache_pkt = pkt;
+} else {
+_status = DcacheWaitResponse;
+// memory system takes ownership of packet
+dcache_pkt = NULL;
+}
+}
template class T
Fault
TimingSimpleCPU::read(Addr addr, T data, unsigned flags)
{
-Request *req =
-new Request(/* asid */ 0, addr, sizeof(T), flags, thread-readPC(),
-_cpuId, /* thread ID */ 0);
+Fault fault;
+const int asid = 0;
+const int threadId = 0;
+const Addr pc = thread-readPC();
-if (traceData) {
-traceData-setAddr(req-getVaddr());
+PacketPtr pkt;
+RequestPtr req;
+
+int blockSize = dcachePort.peerBlockSize();
+int dataSize = sizeof(T);
+
+Addr secondAddr = roundDown(addr + dataSize - 1, blockSize);
+
+if (secondAddr addr) {
+Addr firstSize = secondAddr - addr;
+Addr secondSize = dataSize - firstSize;
+// Make sure we'll only need two accesses.
+assert(roundDown(secondAddr + secondSize - 1, blockSize) ==
+secondAddr);
+
+/*
+ * Do the translations. If something isn't going to work, find out
+ * before we waste time setting up anything else.
+ */
+req = new Request(asid, addr, firstSize, flags, pc, _cpuId, threadId);
+fault = thread-translateDataReadReq(req);
+if (fault != NoFault) {
+delete req;
+return fault;
+}
+Request *secondReq =
+new Request(asid, secondAddr, secondSize,
+flags, pc, _cpuId, threadId);
+fault = thread-translateDataReadReq(secondReq);
+if (fault != NoFault) {
+delete req;
+delete secondReq;
+return fault;
+}
+
+// This is the packet we'll process now.
+pkt = new Packet(req,
+ (req-isLocked() ?
+ MemCmd::LoadLockedReq : MemCmd::ReadReq),
+ Packet::Broadcast);
+pkt-dataDynamicuint8_t(new uint8_t[firstSize]);
+SplitSenderState *sendState = new SplitSenderState;
+pkt-senderState = sendState;
+
+// This is the second half of the access we'll deal with later.
+PacketPtr secondPkt =
+new Packet(secondReq,
+ (secondReq-isLocked() ?
+MemCmd::LoadLockedReq : MemCmd::ReadReq),
+ Packet::Broadcast);
+secondPkt-dataDynamicuint8_t(new uint8_t[secondSize]);
+sendState-secondPkt = secondPkt;
+
+/*
+ * This is the big packet that will hold the data we've gotten so far,
+ * if any, and also act as the response we actually give to the
+ * instruction.
+ */
+Request *origReq =
+new Request(asid, addr, dataSize, flags, pc, _cpuId, threadId);
+origReq-setPhys(req-getPaddr(), dataSize, flags);
+PacketPtr bigPkt =
+new Packet(origReq, MemCmd::ReadResp, Packet::Broadcast);
+bigPkt-dataDynamicT(new T);
+sendState-bigPkt = bigPkt;
+} else {
+req = new Request(asid, addr, dataSize, flags, pc, _cpuId, threadId);
+
+// translate to physical address
+Fault fault = thread-translateDataReadReq(req);
+
+if (fault != NoFault) {
+delete req;
+return fault;
+}
+
+pkt = new Packet(req,
+ (req-isLocked() ?
+ MemCmd::LoadLockedReq : MemCmd::ReadReq),
+ Packet::Broadcast);
+pkt-dataDynamicT(new T);
}
- // translate to physical address
-Fault fault = thread-translateDataReadReq(req);
-
-// Now do the access.
-if (fault == NoFault) {
-PacketPtr pkt =
-new Packet(req,
- (req-isLocked() ?
-MemCmd::LoadLockedReq : MemCmd::ReadReq),
- Packet::Broadcast);
-pkt-dataDynamicT(new T);
-
-if (req-isMmapedIpr()) {
-Tick delay;
-delay = TheISA::handleIprRead(thread-getTC(), pkt);
-new
[m5-dev] [PATCH 1 of 3] X86: Make the timing simple CPU handle variable length instructions
# HG changeset patch
# User Gabe Black [EMAIL PROTECTED]
# Date 1226041356 28800
# Node ID 94ef4905a939b782105ce0ebb3c063451744fb3d
# Parent 61c838ecc2259cd0d60dc7d7b9bf0e92cb1a89da
X86: Make the timing simple CPU handle variable length instructions.
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -561,7 +561,8 @@
void
TimingSimpleCPU::advanceInst(Fault fault)
{
-advancePC(fault);
+if (fault != NoFault || !stayAtPC)
+advancePC(fault);
if (_status == Running) {
// kick off fetch of next instruction... callback from icache
@@ -599,7 +600,8 @@
}
preExecute();
-if (curStaticInst-isMemRef() !curStaticInst-isDataPrefetch()) {
+if (curStaticInst
+curStaticInst-isMemRef() !curStaticInst-isDataPrefetch()) {
// load or store: just send to dcache
Fault fault = curStaticInst-initiateAcc(this, traceData);
if (_status != Running) {
@@ -638,7 +640,7 @@
instCnt++;
advanceInst(fault);
}
-} else {
+} else if (curStaticInst) {
// non-memory instruction: execute completely now
Fault fault = curStaticInst-execute(this, traceData);
@@ -657,6 +659,8 @@
curStaticInst-isFirstMicroop()))
instCnt++;
advanceInst(fault);
+} else {
+advanceInst(NoFault);
}
if (pkt) {
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Re: [m5-dev] encumbered: appease gabe, fatal out if EioProcess attempts to st...
I am officially appeased. :)
Gabe
Quoting [EMAIL PROTECTED]:
changeset 324547c99895 in /z/repo/encumbered
details: http://repo.m5sim.org/encumbered?cmd=changeset;node=324547c99895
summary: appease gabe, fatal out if EioProcess attempts to start up in a
non-ALPHA ISA
diffstat:
1 file changed, 2 insertions(+)
eio/eio.cc |2 ++
diffs (14 lines):
diff -r 2c7b9d01d542 -r 324547c99895 eio/eio.cc
--- a/eio/eio.cc Tue Nov 04 21:55:49 2008 -0500
+++ b/eio/eio.cc Wed Nov 05 16:21:42 2008 -0500
@@ -631,6 +631,10 @@
void
EioProcess::startup()
{
+#if THE_ISA != ALPHA_ISA
+fatal(EIO Processes only work with Alpha)
+#endif
+
Process::startup();
/* load initial state checkpoint */
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Re: [m5-dev] cpu vs thread vs contexts
I mostly agree with this, except that it might be tricky to use the context ID t index into a vector of thread contexts when the numbering doesn't start over for each CPU. Other than that it looks like we're strictly getting closer to the right answer at least. Gabe Quoting Lisa Hsu [EMAIL PROTECTED]: yes, that's what i mean. believe it or not, right now if you run se.py -n4, all four cpus get cpuId = 0 (regardless of which cpu type you use). talk about broken. and from now on, getCpuId() should pretty much only be used for things like stats, or as a secondary identifier, the primary thing to care about is the HW context ID. On Fri, Oct 24, 2008 at 4:51 PM, Korey Sewell [EMAIL PROTECTED] wrote: Are you saying make a distinction between the cpu ID and the actual hardware context ID? This is something definitely needed. I think this is what you describe below... I'm seeing something where there is a: getCpuId() and a getContext() function. On a 2-way SMT system with 1 CPU... process0-getCpuId() = 0 process0-getContext() = 0 process1-getCpuId() = 0 process1-getContext() = 1 but with a 2-CPU system , No-SMT... process0-getCpuId() = 0 process0-getContext() = 0 process1-getCpuId() = 1 process1-getContext() = 1 and finally, a 2-way SMT, 2-cpu system... process0-getCpuId() = 0 process0-getContext() = 0 process1-getCpuId() = 0 process1-getContext() = 1 process2-getCpuId() = 1 process2-getContext() = 2 process3-getCpuId() = 1 process3-getContext() = 3 Is this what you describe, by all means all systems go! 2008/10/24 Lisa Hsu [EMAIL PROTECTED]: Hi All, In case you haven't guessed it, I'm hacking on M5 once again. I've noticed recently that there is a big hot mess when it comes to identification mechanisms for CPUs, threads, and contexts. Alternately all contexts are assumed to be separate CPUs (which is wrong when there is SMT), vs times when CPUs are CPUs and threads are subsets of certain CPUs such that a system can have names like CPU0,T0; CPU,T1; CPU1,T0; CPU1,T1, etc. I talked about it with Steve today and here's what I propose, let me know if you object. All CPUs with have an ID, but this will not be a primary context identification mechanism. In other words, in many places where tc-getCpuId() is used in order to index into a threadContexts vector, it will be changed so that tc-getIdentifier() will give back something unique across the system. The primary context identification mechanism will be a system-wide context id-value. That means in a 2 CPU 2 thread SMT system, you will have system-wide context IDs of 0-3. So the tc-getCpuId() mentioned above will be changed to something like tc-getContextId(). Each context will still have a pointer to the CPU it belongs to, which in turn will have an ID value so you can always know which CPU you belong to if you want. I'm going to start working on this now, so speak now or forever hold your peace. :) Lisa ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev -- -- Korey L Sewell Graduate Student - PhD Candidate Computer Science Engineering University of Michigan ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] changeset in m5: Create a message port for sending messages as a...
That sounds reasonable. I had originally envisioned this code having a use outside of the interrupt messages, or at least in objects that wouldn't inherit from IntDev to avoid multiple inheritance, etc, but if not then it doesn't need to be in its own class. Gabe Quoting Steve Reinhardt [EMAIL PROTECTED]: Hi Gabe, I haven't looked at all the code surrounding this in detail, but I think this is unnecessary... packets really are messages (though up to now they've all been coherence messages), and the idea behind Port objects is that in the common case a MemObject should have a dedicated Port subclass that maps virtual functions like recvAtomic() to non-virtual member functions of that MemObject so that there's only one virtual function call on the path between two objects. I suggest having IntDev::IntPort derive directly from SimpleTimingPort, move MessagePort::recvAtomic() directly into IntDev::IntPort, and then get rid of the MessagePort class entirely. Also I think that IntReq and IntResp (as you have in the comments in packet.cc) are much more descriptive names than MessageReq and MessageResp. Steve On Sun, Oct 12, 2008 at 1:15 PM, Gabe Black [EMAIL PROTECTED] wrote: changeset d2782c951841 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=d2782c951841 description: Create a message port for sending messages as apposed to reading/writing a memory range. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] unhalting CPU
No, but they're shortly after them in my queue and can't be easily moved. I'll send you more information about them when I get home and can get at everything. Gabe Quoting nathan binkert [EMAIL PROTECTED]: Is it necessary to solve those to get your o3 diffs in? If so, what diffs can I look at again to try to figure it out? Nate On Wed, Oct 8, 2008 at 11:41 AM, [EMAIL PROTECTED] wrote: Ok. I'll work on rebasing this evening, and then around midnight I'll update stable and start pumping changes into the head. There are still a handful of changes to, for example, the params stuff that we need to agree on, plus the warn with character array vs. warn with character pointer issue from a while ago. Gabe Quoting nathan binkert [EMAIL PROTECTED]: I actually have some outstanding diffs to this area of the code that centralize the wakeup code. It would probably be best for us to coordinate some of this. It probably makes sense for you to get all of your o3 generalization diffs committed first though. Nate On Wed, Oct 8, 2008 at 12:52 AM, Gabe Black [EMAIL PROTECTED] wrote: I'm at the point where a timer interrupt needs to wake the CPU out of its idle thread. The idle thread uses a hlt instruction to suspend itself, and that ends up as a call to halt() on the exec context. I'm not sending interrupts through the older post, clear, etc., so I don't know if the CPU realizes it has some work to do and should stop being halted. I added a call to activate() in the interrupt object invoke method, but I don't think that'll help because the CPU's not checking its interrupts. What I probably need to do is to make the interrupts object call that function, but for that I'd need a way to get at the CPU it's part of, and know what thread to wake up. What's the right way to go about this? Gabe ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] another warn bug
It was in a set of microops I made which just panic/warn/etc with a string you pass as the argument. It lets you use that sort of functionality at the microcode level of abstraction which is fairly handy. Anyway, the string was just a regular English sentence with a ., a ( and a ) if I remember correctly. I can't dig into the code at the moment so this might not be quite right, but if you go into arch/x86/isa/insts/general_purpose/logical.py, go to the microcode for XOR_R_R which is the first macroop executed in SE in the regressions, and add warn This is an example warning to the beginning of that block, you should be able to very quickly reproduce the problem with any of the regressions. Gabe Quoting nathan binkert [EMAIL PROTECTED]: You mean a std::string? I guess I could disallow std::string as the format string and only allow const char *. This probably isn't overly burdensome. Though the question is, what was in the string that caused it to break? In theory, it should work, unless there are a lot of %s in it. And I could probably fail those a bit more gracefully. Nate On Thu, Oct 2, 2008 at 12:49 AM, Gabe Black [EMAIL PROTECTED] wrote: I just fixed a nasty memory bug where I was unwittingly passing a string as the format argument of warn. I believe what happened was that it was treating the string as a character pointer directly, and that somehow broke the stack (or not? I'm not sure) and forced __warn to recurse until the stack ran out and everything exploded. The segfault could also have just been from the stack running out. It was hard to tell what happened. In any case, it's something people should avoid doing. Is there some way to handle this correctly, or at least complain about a type mismatch or something and not self destruct? Gabe ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] microcode plan of record
Quoting Steve Reinhardt [EMAIL PROTECTED]: Great, glad you guys were able to do that. There will be a new flag on static insts which will indicate whether or not they leave the context of the current macroop on faults. Is this flag for microops or macroops or both? Both, since they're both static insts. We might want to subclass them at some point, but that may or may not be useful complexity. Is this feature required only for the optimization cases you mentioned before? If so, was it spelled out explicitly in the patent you read? It seems to me that almost any optimization that requires handling a fault and restarting within the macroop could also be handled by restarting the entire macroop using the more conservative microcode (given that you can treat each REP iteration as an independent macroop), as I described earlier. Basically this feature sounds complicated and I want to be really sure we need it before we put it in... I'll happily get into more detail in a little while. This isn't something that will be important for a while and there's quite a few patches ahead of anything that would make this change in my queue, so there's plenty of time to change our minds. Nate, if you'd like to clarify right now that would be fine too. Gabe ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] ISA specific decoder state
Unfortunately there's still one missing component here. If you switch to the ROM and change the micropc, you may just be starting up the part of the macroop stored in the ROM, or you may be, for instance, trying to enter an interrupt handler. In the former case you want a macroop and in the later you don't, but it isn't clear how to differentiate between the two. Most of the time the problem isn't that big of a deal because you can just ignore the macroop, but in cases where the macroop doesn't work at all, like on a page fault in instruction memory, that can effectively block an interrupt from happening. One possible solution is to keep the macroop around effectively until you know for sure you finished a macroop, or if the thread context tells you to artificially kick it out with some sort of function. A possible name is endMacroop. Gabe Quoting Gabe Black [EMAIL PROTECTED]: I've considered it, and I think this is a good solution. I'm going to pass the current macroop into the rom when getting microops, and then when this gets to o3 at some point, keep the current macroop in the DynamicInst. Gabe [EMAIL PROTECTED] wrote: I'll have to think about it more, but at first pass that sounds pretty good. It might also help generate better/more descriptive disassembly which is something I've wanted to do for a while. Gabe Quoting Steve Reinhardt [EMAIL PROTECTED]: How about having a current macroop pointer in the execution context (so there would be a single pointer for SimpleCPU, and it would live in the DynamicInst object in O3)? On Sun, Sep 21, 2008 at 11:25 PM, Gabe Black [EMAIL PROTECTED] wrote: To break this into more digestible chunks, I need a way to get important information from the most recent macroop to the ROM so it can tune it's microops accordingly. I'd like to have two different types of regions in the ROM, those that are extensions of combinational macroops and need the specifics of the original macroop to do their job, and those that use a predefined set of parameters so they always work in predictable ways (and don't require a macroop). When the ROM was just an abstraction internal to the macroops, really just a special range of micropcs, the macroop itself could ferry that information along when it got microops from the ROM to give to the decoder. Now that the decoder gets the microops directly from the ROM, the information needs a new way to get to there. Two possibilities are that the decoder could expose the last macroop to the ROM so the ROM can pull out what it needs itself. The other is that the macroop sets up state maintained in the decoder which is exposed to the ROM for the same purpose. Exposing the macroop would probably be easier, but then it's easier to do something bad if there's no macroop but the ROM expects one. Liberal application of assert(ptr != NULL) would probably help mitigate that. One additional complication is if you mispredict or otherwise need to reset to a particular microop in the ROM. It could be hard to figure out if you need to get a macroop so the ROM can get the state it needs, or if the PC is nonsense and the ROM doesn't need the macroop. In this case, if the macroop is needed, fetch/decode should generate it, and if it causes a fault the fault should be handled. If the macroop isn't needed, fetch/decode shouldn't try to get it, and if they do and a fault happens, the fault should be ignored. I'm not sure what the best way to differentiate these is. One option would be to add more state which says whether or not the microops are stand alone and not intended to be part of a macroop. I feel like the decoder might be trying to keep track of too many things already, so some way to work that in there without just layering it on top would be best. Gabe Gabe Black wrote: I'm getting pretty close to starting with the interrupt entering microcode, but one annoying issue I'm not sure how to deal with is passing an environment to the microops in the ROM. For the interrupt code it's not as important because for a particular mode, the code should always behave the same way, generally outside the scope of any instruction. In the case of macroops being partially stored in the ROM, it becomes more important since the registers used, the various widths involved, etc. become more important. The ROM itself as it stands spits out instructions which correspond to a particular micropc but aren't otherwise specialized. If this was just x86, the obvious/easy solution would be to pass the emulation environment and extended machine instruction being used with the current macroop through to the ROM as the instructions are generated. Since it isn't, I need some way to get that information, whose existence is unknown to the decoder, out of the macroop, and then pass it into the ROM when a microop is requested. Any ideas
Re: [m5-dev] changeset in m5: inifile: Whack preprocessor access.
This is a fairly minor complaint, but could we tag these messages with [m5-cvs]
like we used to? It's handy to be able to filter mercurial messages to their
own folder.
Gabe
Quoting Nathan Binkert [EMAIL PROTECTED]:
changeset 65b27e939646 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=65b27e939646
description:
inifile: Whack preprocessor access.
We haven't used the preprocessor feature of the inifile stuff in a
very long time, so let's get rid of it since it would otherwise take
effort to maintain.
diffstat:
2 files changed, 12 deletions(-)
src/base/inifile.cc |8
src/base/inifile.hh |4
diffs (148 lines):
diff -r 3af77710f397 -r 65b27e939646 src/base/inifile.cc
--- a/src/base/inifile.cc Wed Sep 10 14:26:15 2008 -0400
+++ b/src/base/inifile.cc Fri Sep 19 09:11:40 2008 -0700
@@ -29,22 +29,8 @@
* Steve Reinhardt
*/
-#define USE_CPP
-
-#ifdef USE_CPP
-#include sys/signal.h
-#include sys/types.h
-#include sys/wait.h
-
-#include libgen.h
-#include stdio.h
-#include stdlib.h
-#include unistd.h
-#endif
-
#include fstream
#include iostream
-
#include vector
#include string
@@ -66,103 +52,6 @@
++i;
}
}
-
-
-#ifdef USE_CPP
-bool
-IniFile::loadCPP(const string file, vectorchar * cppArgs)
-{
-// Open the file just to verify that we can. Otherwise if the
-// file doesn't exist or has bad permissions the user will get
-// confusing errors from cpp/g++.
-ifstream tmpf(file.c_str());
-
-if (!tmpf.is_open())
-return false;
-
-tmpf.close();
-
-char *cfile = strncpy(new char[file.size() + 1], file.c_str(),
- file.size());
-char *dir = dirname(cfile);
-char *dir_arg = NULL;
-if (*dir != '.') {
-string arg = -I;
-arg += dir;
-
-dir_arg = new char[arg.size() + 1];
-strncpy(dir_arg, arg.c_str(), arg.size());
-}
-
-delete [] cfile;
-
-char tempfile[] = /tmp/configXX;
-int tmp_fd = mkstemp(tempfile);
-
-int pid = fork();
-
-if (pid == -1)
-return false;
-
-if (pid == 0) {
-char filename[FILENAME_MAX];
-string::size_type i = file.copy(filename, sizeof(filename) - 1);
-filename[i] = '\0';
-
-int arg_count = cppArgs.size();
-
-const char **args = new const char *[arg_count + 20];
-
-int nextArg = 0;
-args[nextArg++] = g++;
-args[nextArg++] = -E;
-args[nextArg++] = -P;
-args[nextArg++] = -nostdinc;
-args[nextArg++] = -nostdinc++;
-args[nextArg++] = -x;
-args[nextArg++] = c++;
-args[nextArg++] = -undef;
-
-for (int i = 0; i arg_count; i++)
-args[nextArg++] = cppArgs[i];
-
-if (dir_arg)
-args[nextArg++] = dir_arg;
-
-args[nextArg++] = filename;
-args[nextArg++] = NULL;
-
-close(STDOUT_FILENO);
-if (dup2(tmp_fd, STDOUT_FILENO) == -1)
-exit(1);
-
-// execvp signature is intentionally broken wrt const-ness for
-// backwards compatibility... see man page
-execvp(g++, const_castchar * const *(args));
-
-exit(0);
-}
-
-int retval;
-waitpid(pid, retval, 0);
-
-delete [] dir_arg;
-
-// check for normal completion of CPP
-if (!WIFEXITED(retval) || WEXITSTATUS(retval) != 0)
-return false;
-
-close(tmp_fd);
-
-bool status = false;
-
-status = load(tempfile);
-
-unlink(tempfile);
-
-return status;
-}
-#endif
bool
IniFile::load(const string file)
diff -r 3af77710f397 -r 65b27e939646 src/base/inifile.hh
--- a/src/base/inifile.hh Wed Sep 10 14:26:15 2008 -0400
+++ b/src/base/inifile.hh Fri Sep 19 09:11:40 2008 -0700
@@ -167,14 +167,6 @@
/// @retval True if successful, false if errors were encountered.
bool load(std::istream f);
-/// Load the specified file, passing it through the C preprocessor.
-/// Parameter settings found in the file will be merged with any
-/// already defined in this object.
-/// @param file The path of the file to load.
-/// @param cppFlags Vector of extra flags to pass to cpp.
-/// @retval True if successful, false if errors were encountered.
-bool loadCPP(const std::string file, std::vectorchar * cppFlags);
-
/// Load the specified file.
/// Parameter settings found in the file will be merged with any
/// already defined in this object.
___
m5-dev mailing list
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http://m5sim.org/mailman/listinfo/m5-dev
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] changeset in m5: inifile: Whack preprocessor access.
Could we create m5-cvs and then just subscribe m5-dev to it?
Gabe
Quoting nathan binkert [EMAIL PROTECTED]:
We'd have to create a separate m5-cvs mailing list do do that. We
could maybe make m5-cvs an alias for m5-dev so that everyone gets
both. If you can figure out how to make mailman do this, I don't
think anyone would object.
Nate
This is a fairly minor complaint, but could we tag these messages with
[m5-cvs]
like we used to? It's handy to be able to filter mercurial messages to
their
own folder.
Gabe
Quoting Nathan Binkert [EMAIL PROTECTED]:
changeset 65b27e939646 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=65b27e939646
description:
inifile: Whack preprocessor access.
We haven't used the preprocessor feature of the inifile stuff in a
very long time, so let's get rid of it since it would otherwise take
effort to maintain.
diffstat:
2 files changed, 12 deletions(-)
src/base/inifile.cc |8
src/base/inifile.hh |4
diffs (148 lines):
diff -r 3af77710f397 -r 65b27e939646 src/base/inifile.cc
--- a/src/base/inifile.cc Wed Sep 10 14:26:15 2008 -0400
+++ b/src/base/inifile.cc Fri Sep 19 09:11:40 2008 -0700
@@ -29,22 +29,8 @@
* Steve Reinhardt
*/
-#define USE_CPP
-
-#ifdef USE_CPP
-#include sys/signal.h
-#include sys/types.h
-#include sys/wait.h
-
-#include libgen.h
-#include stdio.h
-#include stdlib.h
-#include unistd.h
-#endif
-
#include fstream
#include iostream
-
#include vector
#include string
@@ -66,103 +52,6 @@
++i;
}
}
-
-
-#ifdef USE_CPP
-bool
-IniFile::loadCPP(const string file, vectorchar * cppArgs)
-{
-// Open the file just to verify that we can. Otherwise if the
-// file doesn't exist or has bad permissions the user will get
-// confusing errors from cpp/g++.
-ifstream tmpf(file.c_str());
-
-if (!tmpf.is_open())
-return false;
-
-tmpf.close();
-
-char *cfile = strncpy(new char[file.size() + 1], file.c_str(),
- file.size());
-char *dir = dirname(cfile);
-char *dir_arg = NULL;
-if (*dir != '.') {
-string arg = -I;
-arg += dir;
-
-dir_arg = new char[arg.size() + 1];
-strncpy(dir_arg, arg.c_str(), arg.size());
-}
-
-delete [] cfile;
-
-char tempfile[] = /tmp/configXX;
-int tmp_fd = mkstemp(tempfile);
-
-int pid = fork();
-
-if (pid == -1)
-return false;
-
-if (pid == 0) {
-char filename[FILENAME_MAX];
-string::size_type i = file.copy(filename, sizeof(filename) - 1);
-filename[i] = '\0';
-
-int arg_count = cppArgs.size();
-
-const char **args = new const char *[arg_count + 20];
-
-int nextArg = 0;
-args[nextArg++] = g++;
-args[nextArg++] = -E;
-args[nextArg++] = -P;
-args[nextArg++] = -nostdinc;
-args[nextArg++] = -nostdinc++;
-args[nextArg++] = -x;
-args[nextArg++] = c++;
-args[nextArg++] = -undef;
-
-for (int i = 0; i arg_count; i++)
-args[nextArg++] = cppArgs[i];
-
-if (dir_arg)
-args[nextArg++] = dir_arg;
-
-args[nextArg++] = filename;
-args[nextArg++] = NULL;
-
-close(STDOUT_FILENO);
-if (dup2(tmp_fd, STDOUT_FILENO) == -1)
-exit(1);
-
-// execvp signature is intentionally broken wrt const-ness for
-// backwards compatibility... see man page
-execvp(g++, const_castchar * const *(args));
-
-exit(0);
-}
-
-int retval;
-waitpid(pid, retval, 0);
-
-delete [] dir_arg;
-
-// check for normal completion of CPP
-if (!WIFEXITED(retval) || WEXITSTATUS(retval) != 0)
-return false;
-
-close(tmp_fd);
-
-bool status = false;
-
-status = load(tempfile);
-
-unlink(tempfile);
-
-return status;
-}
-#endif
bool
IniFile::load(const string file)
diff -r 3af77710f397 -r 65b27e939646 src/base/inifile.hh
--- a/src/base/inifile.hh Wed Sep 10 14:26:15 2008 -0400
+++ b/src/base/inifile.hh Fri Sep 19 09:11:40 2008 -0700
@@ -167,14 +167,6 @@
/// @retval True if successful, false if errors were encountered.
bool load(std::istream f);
-/// Load the specified file, passing it through the C preprocessor.
-/// Parameter settings found in the file will be merged with any
-/// already defined in this object.
-/// @param file The path of the file to load.
-/// @param cppFlags Vector of extra flags to pass to cpp.
-/// @retval True if successful, false if errors were encountered.
-bool loadCPP(const std::string file,
Re: [m5-dev] another microcode design decision
There is conceptually no upper bound, but really it's because you simply can't branch withing the number of microops generated by the combinational decoder. It's generating what amounts to an atomic VLIW vector of operations where control happens between entire vectors. Only one comes out of the combinational decoder, so it's like you get one instruction at that point. Either that one instruction does the trick, or you need to go to the ROM where a micropc conceptually exists. Gabe Quoting Steve Reinhardt [EMAIL PROTECTED]: I see...the only reason I saw to switch to relative branches is that it avoids the need to distinguish between ROM and non-ROM targets. I guess the argument for their approach is that if your microcode flow is complex enough to require a branch then it's probably complex enough to need to come out of ROM anyway. I'm guessing the difference with what you're doing is that there's no hard upper bound on the number of microops you can generate via the combinational decoder; is that true? Steve On Thu, Sep 18, 2008 at 12:52 AM, Gabe Black [EMAIL PROTECTED] wrote: This email is a minor informational update on the microcode/micropc/branching/ROM stuff. I started working on making the microbranches relative, but I had a hard time getting it to work because of how the microcode listing is processed and needing to know the current micropc in order to compute the argument for the branch microop. I went to check the patent to just to make sure I was thinking about things the right way, and it turns out I was wrong about two things. First, the branches are absolute and not relative. This makes a lot of sense because you eliminate the need for an adder to computer your target, and also one big win of relative branches, relocatable code, is moot in a ROM like this. Second, branches are not register operations. They come in one or two parts and are centered around generating quads of operations from the ROM on each read. On the end of a quad, there's a field called OpSeq which directs you to the next quad to fetch and is similar to what I'd call a branch. It has a 12 bit field which encodes it's target, and since it deals with a quad of microops, I'd say it's 14 effective bits. If you want a conditional branch, one of the operations in the quad says what the condition is and what the fall through address is, and there are 17 bits for that. Since that's all tied to having quads and that's a little to specific to a particular implementation for M5, I think, it seems more appropriate to have a conditional branch microop that just does everything at once. What I did before was make the branch instruction a register operation which only supports 8 bits of immediate because that made it easy to make it conditional. What I should really do is move the branch instruction to the right category and extend the immediate field to 16 bits, a handy number which approximates what's in the patent. Also, as far as different address spaces for the ROM and the macroop, the patent handles that by making -all- branches go to the ROM, and by making the unit of execution a quad. That way, if you're not finished when you execute the one and only combinational quad associated with an instruction (which effectively has no micropc), you always go to someplace in the ROM with a branch. This again doesn't work for M5 because we're not architected around quads and all microops have a micropc. Gabe ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] changeset in m5: style: Remove non-leading tabs everywhere they ...
I really hope this isn't going to make applying all my patches significantly harder... Gabe Quoting Ali Saidi [EMAIL PROTECTED]: changeset 3af77710f397 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=3af77710f397 description: style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs diffstat: 69 files changed, 427 insertions(+), 682 deletions(-) configs/common/Benchmarks.py | 17 src/arch/alpha/aout_machdep.h | 21 src/arch/alpha/floatregfile.hh |1 src/arch/alpha/ipr.cc | 53 -- src/arch/alpha/ipr.hh | 54 +- src/arch/alpha/isa_traits.hh |4 src/arch/alpha/linux/linux.cc | 16 src/arch/alpha/linux/linux.hh | 14 src/arch/alpha/miscregfile.hh |4 src/arch/alpha/osfpal.cc | 193 ++- src/arch/alpha/pagetable.hh|8 src/arch/alpha/regfile.hh |1 src/arch/alpha/system.cc |2 src/arch/alpha/tru64/tru64.cc | 16 src/arch/alpha/tru64/tru64.hh | 14 src/arch/mips/isa_traits.hh|4 src/arch/mips/linux/linux.cc | 16 src/arch/mips/linux/linux.hh | 14 src/arch/mips/regfile/regfile.hh |6 src/arch/mips/system.cc|2 src/arch/mips/tlb.hh |2 src/arch/sparc/linux/linux.cc | 16 src/arch/sparc/linux/linux.hh | 14 src/arch/sparc/miscregfile.hh | 22 src/arch/sparc/regfile.hh |1 src/arch/sparc/solaris/solaris.cc | 18 src/arch/sparc/solaris/solaris.hh | 10 src/arch/sparc/sparc_traits.hh |1 src/arch/x86/isa/insts/general_purpose/cache_and_memory_management.py |4 src/arch/x86/isa/insts/general_purpose/data_conversion/ascii_adjust.py |2 src/arch/x86/isa/insts/general_purpose/load_segment_registers.py |4 src/arch/x86/isa/insts/general_purpose/system_calls.py |2 src/arch/x86/linux/linux.hh| 14 src/base/crc.cc|1 src/base/inifile.hh|1 src/base/loader/coff_symconst.h| 12 src/base/stats/flags.hh|9 src/cpu/base_dyn_inst.hh |1 src/cpu/checker/cpu_impl.hh|2 src/cpu/memtest/memtest.hh |2 src/cpu/o3/alpha/dyn_inst.hh |1 src/cpu/o3/mips/dyn_inst.hh|1 src/cpu/simple_thread.cc |1 src/cpu/static_inst.hh | 16 src/dev/alpha/access.h | 14 src/dev/etherdump.cc |8 src/dev/mips/access.h | 16 src/dev/ns_gige.hh |3 src/dev/pcireg.h | 11 src/kern/linux/linux.hh| 28 - src/kern/operatingsystem.hh|1 src/kern/solaris/solaris.hh| 22 src/kern/tru64/mbuf.hh | 33 - src/kern/tru64/tru64_syscalls.cc | 243 -- src/mem/cache/blk.hh |1 src/mem/cache/builder.cc | 26 - src/mem/cache/prefetch/stride.cc |2
Re: [m5-dev] g++ 4.3
I'm in favor of ignoring the parenthesis warning. Gabe Quoting nathan binkert [EMAIL PROTECTED]: As usual the gnu guys are out to make our life easier. I've more or less got things working with 4.3, but there are a couple of issues we need to sort out. I'll also need people to compile M5 on as many systems as possible to make sure that my changes don't break things. (I'll commit the patches in a day or so) 1) G++ now complains about lack of parenthesis in expressions with combinations of operators that are commonly screwed up. We can disable the warning with -Wno-parentheses and ignore the issue. I generally feel that people should know their order of operations, but with so many people hacking, maybe it's worth it to fix them and enable the warning. Examples a b || c d===(a b) || (c d) a b - c ===a (b - c) 2) hash_map is now deprecated and people are supposed to use unordered_map which will be in the next C++ standard. Unfortunately, it's not too easy to provide an adapter between the two without using #define. We can ignore the error for now with -Wno-deprecated, but we're going to have to bite the bullet at some point when hash_map is really moved. To top things off, if you use unordered_map, you have to set --std=c++0x or --std=gnu++0x. I'm inclined to disable the warning, and just do whatever magic is necessary when things finally break, but the downside of that is when they do break, it might be harder to keep older versions of compilers working if we don't have some sort of adapter. Anyone have any opinions? Nate ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] interrupts interface
I'll buy that. Gabe Quoting Ali Saidi [EMAIL PROTECTED]: I don't think this optimization will work. The reason that the get and update parts were separated was because getInterupt() is supposed to be callable without changing the interrupt/system state. If memory serves the reason for this is because there are cases where you might call get a fault multiple places interrupt + itb fault + something else and the fault priority the ISA specifies is not the order which we would generate things. The two step process allows us to fix that up. Ali On Sep 8, 2008, at 2:01 AM, Gabe Black wrote: Since I've been poking around the Interrupts object, I've noticed we've got a lot of functions on there, and we can probably trim that down a bit. There are functions related to setting and clearing interrupts which go away when those are delivered through the memory system, although that transition will take a while and I'm not planning on it any time soon. Also, there are three functions related to getting an interrupt to process. There's check_interrupts which returns a bool of whether or not there's an interrupt waiting, getInterrupt which actually retrieves the interrupt, and updateIntrInfo which records the fact that the interrupt is about to happen in the ThreadContext. What I think will work and be a bit more streamline is to combine getInterrupt and updateIntrInfo into one function called, for instance, acceptInterrupt. This way you can check whether an interrupt is ready whenever you want without going through the overhead of actually generating it, and when you're ready to actually invoke it, you can do that all in one shot. I haven't actually tried doing this so I'm not sure there isn't some corner case it can't handle, so if Kevin or Korey could comment that would be helpful. Also, check_interrupts probably should be renamed checkInterrupts to match the style of the other function names. Gabe ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] interrupt messages
The accesses are supposed to be atomic, I'm pretty sure. I think they're basically just special messages passed around on the bus which I'm approximating with reads and writes. I set aside a page for those accesses because it was a convenient size and I already needed a second page for access to the local APICs configuration space, but I don't expect anywhere near that much data to actually go into these messages. It should just be a handful of bytes. What might be best would be to create some new type/command for packets that represent interrupt messages, but I initially shied away from that because it might be hard to implement properly, could make all the devices more complex since they have to handle or at least ignore those messages, and adds clutter and complexity to the way the memory system works. I'm pretty open to suggestions if there's some way to implement things that seems obviously best. Gabe Quoting Steve Reinhardt [EMAIL PROTECTED]: The memory system doesn't do any segmentation. It will choke if you try and do a single access that spans cache blocks in cached memory. For uncached physical accesses, I don't know if there are any hard limits or not, but performance would get unrealistic if you tie up a bus while a full page of data traverses it. There are ports that provide readBlob/writeBlob calls, though they're really only intended for functional accesses (like program loading, syscall emulation, etc.). I don't know enough detail about the APIC accesses to comment on the atomicity issues. I'd expect that it's designed so that you just do atomic accesses. Steve On Thu, Sep 4, 2008 at 9:23 AM, Gabe Black [EMAIL PROTECTED] wrote: I'm close to the point of sending messages between APICs, and I was thinking about the semantics of how I actually want to send the message. I need to know the specifics of a few properties of the memory system in order to be sure it will work. First, if I send a bigger message, is it possible it'll be split up before getting to it's destination? Second, if it is split up, is there any guarantee of ordering? Third, is there any easy socket style mechanism to send a bunch of bytes to one location (a bunch of small, sequential writes seems fairly clunky), or would I want to write into a buffer and then somehow signal it was all in there? I've allocated a page of memory space for each APIC so they have a space to send each other messages. I suppose a fourth concern if the buffer approach is used is that multiple APICs could compete to write into the same portion of the APICs page unless it was further divided into regions for each sender. Gabe ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] bug in x86
Quoting Gabe Black [EMAIL PROTECTED]: Specifying the right bus in the MP tables partially fixed the kernel's handling of interrupts, but there was also a semi-corner case bug in how one of the instructions was microcoded which was also partially breaking things. I have a patch and I've verified it fixes the problem, and I'm running the X86_SE regressions on zizzer to see if those changed and to update them if appropriate. My question is, should I push this into the stable repo? I'm thinking yes but I figured I'd check before needlessly causing headaches. Gabe ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev Somebody? Anybody? ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] Configuring the 8254 timer from the platform
I don't think there's anything wrong with the southbridge as a conceptual object, but I thought having it in the SimObject hierarchy was a bad idea since, for instance in ancient PCs, all the little bits and pieces we're dealing with were their own entities. It's conceivable that in the future these things will even be on die. What I thought would be best was to make all these components first class objects that are directly attached to the bus, etc, but provide a SouthBridge python class that didn't exist beyond the configuration phase and provided a handy conceptual handle on all the bits and pieces and helped set them up properly. Since I don't want the SouthBridge to be between the legacy components and what refers to them (so that that sort of relationship isn't mandantory), I need to find a way to get from the PC object to the timer directly without the timer having to cooperate. What would be best, I think, is if there was some way for a pointer to the timer to persist into C++ without it having to be a Param people could muck with, but I don't think that's currently possible. Gabe Quoting nathan binkert [EMAIL PROTECTED]: What was wrong with the southbridge object? Was it because of the subdevice thing? I don't think you need to necessarily get rid of the southbridge, you can still have it to do the initialization that you want, I just think you want to make all of the things that were subdevices proper SimObjects. Nate On Thu, Aug 21, 2008 at 9:58 AM, [EMAIL PROTECTED] wrote: The problem here isn't the memory locations things are attached at, it's doing some initial configuration on the 8254 which I believe the BIOS would normally do. If you look in the PC init function you can see where this is happening currently. The southBridge pointer (I think) is near the top and it's used to set the value for the timer pointer to point at the 8254. Since the southbridge object no longer exists, that code won't work as is. In order to avoid a loop in SimObject references, I had the SouthBridge set a pointer back to itself in the platform object. I don't want to push that down into the 8254 model because I want to keep that a relatively generic device you could stick anywhere, if you so desired, that doesn't know it's part of the PC platform. Gabe Quoting nathan binkert [EMAIL PROTECTED]: I'm not exactly clear what you're saying here. You had a SouthBridge object, and in south_bridge.cc, it looks like you manually set the memory locations of the various objects in the south bridge. Now, you want to make the individual objects normal SimObjects, but you're having trouble figuring out how to stick them at the right memory locations? What about a simple attachSouthBridge() function in python that take a platform object as a parameter and attaches the various objects at the right memory locations. Alternatively, you could just derive from the PC platform object and stick the south bridge stuff at the right memory locations in there as defaults. Do I understand the problem correctly? Nate On Wed, Aug 20, 2008 at 11:58 PM, Gabe Black [EMAIL PROTECTED] wrote: Now that I'm flattening out the SouthBridge object, I'm ending up breaking the solution I had before to allow the PC platform to program the initial state of the 8254 PIT. What would happen before was that the SouthBridge would tell the PC platform about itself, and then later the platform would get at the timer through the SouthBridge and configure it properly. Now there's no SouthBridge, and I don't want to push the artificial initial configuration code down into the device itself. One possible solution I was thinking of would be to actually just do functional accesses to the right locations to program the PIT like software would. I'm not sure that would work, though, since I don't know if all the devices have been constructed or hooked up to the memory system yet. Another option would be to record in the PC simobject where the timer is since the timer is created and hooked up by the python version. I don't necessarily want to make it a Param though, because I don't want anyone to be able to modify what it's pointing at. All the other connections, to the 8259 PIC, the speaker, etc, will all be to the original object, so it won't do any good for the C++ PC object to initialize something else. Any ideas? Gabe ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list
Re: [m5-dev] Implementing multi CPU x86 sistem call emulation in M5 (running multithreaded programs)
This sort of question should be sent to [EMAIL PROTECTED] Please resend it to
there.
Gabe
Quoting SrÄan StipiÄ [EMAIL PROTECTED]:
Hi.
I am trying to implement multi CPU x86 sistem call emulation in M5.
Idea that every thread that is created in the program runs on it's own CPU,
so that we don't need any thread scheduling.
The following program runs without the problems with my implementation:
int k = 0;
void f(long a){ k+= a; }
void g(long a){ k+= a; }
int main(){
long t1 = create_thread(f, 5);
long t2 = create_thread(g, 6);
join_thread(t1);
join_thread(t2);
printf(%d, k);
}
The implementation that I have wright now is:
I have implemented 3 new system calls:
create_thread
join_thread
stop_thread.
create_thread(f, a):
- alocates a stack space for new thread
- and adds the code that will call the stop_thread system call when
function 'f' returns.
- sets program counter of the unactive cpu to point to address of 'f'
- activates inactive cpu
join_thread(t1):
- waits thread 't1' to be suspended or suspends parent thread
stop_thread():
- suspends itself.
When I run more complex examples that execute 'printf' or 'malloc' in
child thread,
the simulator stop executing program with the following error message:
Running clients... panic: Tried to access unmapped address 0.
@ cycle 132099500
[invoke:build/X86_SE/arch/x86/faults.cc, line 160]
Program aborted at cycle 132099500
Aborted
Can you give me any directions what can be the problem?
(I have the feeling that current sistem call emulation doesn't support
I/0 that execute from two different thread_conetexts)
Tnx,
Srdjan
P.S.
Longer log for the example were child thread calls malloc:
127311000: system.cpu2 T0 : @main+280 : CALL_NEAR_I : stupd
t7, SS:[rsp + 0xfff8] : MemWrite : D=0x7fffeaa8
A=0x7fffeaa8
127311500: system.cpu2 T0 : @main+280 : CALL_NEAR_I : wrip ,
t7, t1 : IntAlu :
127312000: system.cpu2 T0 : @create_thread :PUSH_R : stupd rbp,
SS:[rsp + 0xfff8] : MemWrite : D=0x7fffeaa0
A=0x7fffeaa0
127312500: system.cpu2 T0 : @create_thread+1 : MOV_R_R : mov rbp,
rbp, rsp : IntAlu : D=0x7fffeaa0
127313000: system.cpu2 T0 : @create_thread+4 : SUB_R_I : limm t1,
0x20 : IntAlu : D=0x0020
127313500: system.cpu2 T0 : @create_thread+4 : SUB_R_I : sub rsp,
rsp, t1 : IntAlu : D=0x002c
127314000: system.cpu2 T0 : @create_thread+8 : MOV_M_R : st rdi,
SS:[rbp + 0xffe8] : MemWrite : D=0x004005ea
A=0x7fffea88
127314500: system.cpu2 T0 : @create_thread+12 : MOV_M_R : st
rsi, SS:[rbp + 0xffe0] : MemWrite : D=0x00d91c28
A=0x7fffea80
127315500: system.cpu2 T0 : @create_thread+16 : MOV_R_I : limm
eax, 0x111 : IntAlu : D=0x0111
127316000: system.cpu2 T0 : @create_thread+21 : MOV_R_M : ld
rdi, SS:[rbp + 0xffe8] : MemRead : D=0x004005ea
A=0x7fffea88
127317000: system.cpu2 T0 : @create_thread+25 : MOV_R_M : ld
rsi, SS:[rbp + 0xffe0] : MemRead : D=0x00d91c28
A=0x7fffea80
127317500: system.cpu2 T0 : @create_thread+29 : syscalleax
: IntAlu :
127318000: system.cpu2 T0 : @create_thread+31 : MOV_M_R : st
rax, SS:[rbp + 0xfff8] : MemWrite : D=0x00cbb0d0
A=0x7fffea98
127318500: system.cpu0 T0 : @client_run : PUSH_R : stupd rbp,
SS:[rsp + 0xfff8] : MemWrite : D=0x2abacfe9
A=0x2abacfe9
127319000: system.cpu2 T0 : @create_thread+35 : MOV_R_M : ld
rax, SS:[rbp + 0xfff8] : MemRead : D=0x00cbb0d0
A=0x7fffea98
127319000: system.cpu0 T0 : @client_run+1 : MOV_R_R : mov rbp,
rbp, rsp : IntAlu : D=0x2abacfe9
127339500: system.cpu2 T0 : @main+355 : CMP_R_M : sub t0,
rax, t1 : IntAlu : D=0x00b9
12734: system.cpu2 T0 : @main+359 : JL_I : rdip t1,
%ctrl153, : IntAlu : D=0x0040367e
12734: system.cpu0 T0 : @malloc+22 :MOV_R_P : ld rax,
DS:[t7 + 0x16fcab] : MemRead : D=0x A=0x58a848
127340500: system.cpu0 T0 : @malloc+29 :TEST_R_R : and t0,
rax, rax : IntAlu : D=0x0050
127340500: system.cpu2 T0 : @main+359 : JL_I : limm t2,
0xffda : IntAlu : D=0xffda
127341000: system.cpu2 T0 : @main+359 : JL_I : wrip , t1, t2
: IntAlu :
127341000: system.cpu0 T0 : @malloc+32 :JZ_I : rdip t1,
%ctrl153, : IntAlu : D=0x0041aba2
127341500: system.cpu0 T0 : @malloc+32 :JZ_I : limm t2, 0x1e
: IntAlu : D=0x001e
127341500: system.cpu2 T0 : @main+323 : MOV_R_M : ld eax,
SS:[rbp + 0xffe4] : MemRead : D=0x
A=0x7fffeb34
127342000: system.cpu2 T0 : @main+326 :
Re: [m5-dev] llvm
Quoting Steve Reinhardt [EMAIL PROTECTED]: On Wed, Jul 23, 2008 at 8:12 AM, nathan binkert [EMAIL PROTECTED] wrote: I was thinking the other day that instead of having all the templating we have to try to allow the compiler to optomize things it otherwise wouldn't, maybe we should look into some sort of run-time optimization system like llvm? I think several downsides include extra complexity, it not necessarily working with all our fancy widgets and doodads, and it not necessarily being as effective as we'd like anyway. I figured the idea might have some merit, though, so it was worth at least mentioning. I think it is possible to just change CC and CXX to point to llvm. If you were able to make it work, and you could show test cases that demonstrate a substantial benefit, then we might think about it. I personally would consider the idea of getting rid of all of the template junk a benefit, but it would take forever to convert the code. Maybe I'm just working on different parts of the code base (e.g., not O3?), but getting rid of templating, while not something I'd object to, is way way down on my list of things to do. Plus if we're going to have to change code I'd rather do it to make our code work with more compilers (e.g., MSVC) and not fewer/different ones. Your mention of llvm reminded me though: Derek Chiou's group at UT is using llvm to generate microcode for their FPGA-based simulated x86 core from C descriptions: http://ramp.eecs.berkeley.edu/Publications/Functional-Timing%20Split%20in%20UT%20FAST%20(Slides,%201-17-2008).ppt Not that I want you to spend time on that either, but I thought it was interesting that they took that approach. I would *MUCH* rather see you spend the effort on getting linux to boot on x86. This would be a far, far bigger deal and I'd hate to see you get derailed from that path. Agreed... Steve I agree with you both that it's not a productive use of time, at least for me. It sounded at least a little interesting so I thought I'd throw it out there in case somebody thought it was useful. Gabe ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] Cron [EMAIL PROTECTED] /z/m5/regression/do-regression --scratch all
Sure. We can still look at the old version later if we really need to. Gabe Quoting nathan binkert [EMAIL PROTECTED]: Since we don't know, can I just commit what zizzer says is correct and we'll look for failures on other systems? Nate On Tue, Jul 22, 2008 at 9:24 AM, Gabriel Michael Black [EMAIL PROTECTED] wrote: I have changed the microcode somewhat recently so that could be it. parser just seems to not always behave very well for some reason so I wouldn't be too surprised if it was some minor nondeterminism someplace either in the benchmark, like there was in twolf, or in m5. The tricky part is getting one copy that behaves and one that doesn't to compare since it seems to change all of a sudden and then stay that way for a while. Gabe On Tue, 22 Jul 2008, nathan binkert wrote: So, x86/20.parser has failed for quite some time. There appear to be some slight stat differences because 5 more instructions are being simulated now. Do we want to keep this test failing Gabe? Does it pass somewhere else? I'm just wondering if the difference is simply because of your microcode having changed slightly. Nate On Sun, Jul 20, 2008 at 3:01 AM, Cron Daemon [EMAIL PROTECTED] wrote: * build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing passed. * build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing passed. * build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing passed. * build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic passed. * build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic passed. * build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing passed. * build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing passed. * build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic passed. * build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual passed. * build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest passed. * build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing passed. * build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual passed. * build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic passed. * build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic passed. * build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing passed. * build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic passed. * build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic passed. * build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing passed. * build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing passed. * build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic passed. * build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing passed. * build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic passed. * build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing passed. * build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic passed. * build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic passed. * build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing passed. * build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic passed. * build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing passed. * build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing passed. * build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic passed. * build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing passed. * build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing passed. * build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic passed. * build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic passed. * build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic passed. * build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic passed. * build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing passed. * build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic passed. *
Re: [m5-dev] hwrei
I looked into this just now, and it should be pretty much trivially easy to do things like I described below. Gabe Quoting Gabriel Michael Black [EMAIL PROTECTED]: Actually, the stat is pretty ISA specific as well. I'll have to remember to look at how things are structured, but it might make sense to stick the kernel stat object onto the system or cpu objects and get at it through some path in the thread context. If those stats are per system then I think there's a function that'll get you most of the way there. If it's per cpu I'm not sure if you can get at the cpu you're on rather than just cpu 2 for instance. Either way it shouldn't take too much to let the ISA specific functions outside of the cpu modify the kernel stats through an ISA agnostic interface like a thread context or something. Gabe On Mon, 21 Jul 2008, Steve Reinhardt wrote: On Mon, Jul 21, 2008 at 2:31 PM, nathan binkert [EMAIL PROTECTED] wrote: \ I'm not sure about simPalCheck, but I suspect the reasons were similar. It was hard to get around having to do things in the CPU if the kernelStats needed to be incremented. I never really used the kernelStats much, but I think Nate was fairly interested in it. I created kernelStats to generalize things a little bit. That said, if one of these stats causes a call that's annoying, move it into the ISA, or if really necessary, get rid of it. Few stats are really necessary, though many are helpful for debugging. Another option would be to create a method on the CPU just to increment the stat (which is ISA independent), and then call that from the Alpha-specific hwrei and simPalCheck methods which you can then move into the Alpha-specific part of the code. Steve ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
