[gem5-users] Re: Simulation of Hybrid Memory in Gem5

[Ayaz Akram via gem5-users]

Hi Sadhana,

In the screenshot you shared, the address ranges assigned to two memory
devices are overlapping (0:1073741824 and 0:2147483648). You should modify
the second range such that it does not start from 0 but starts from
1073741824 or some other address (such that the two ranges do not overlap).

-Ayaz

On Wed, Sep 20, 2023 at 10:16 PM Sadhana . via gem5-users <
gem5-users@gem5.org> wrote:

> I am using gem5 version 22.0. I want to simulate hybrid memory
> comprising DRAM and NVM. I have written the code to simulate hybrid memory
> using heterogeneous memory controller as:
> system.mem_ctrl=HeteroMemCtrl()
> system.mem_ctrl.dram = DDR3_1600_8x8()
> system.mem_ctrl.dram.range = system.mem_ranges[0]
> system.mem_ctrl.nvm=NVM_2400_1x64()
> system.mem_ctrl.nvm.range =system.mem_ranges[1]
> print(system.mem_ranges[0])
> print(system.mem_ranges[1])
> But I am getting the error as the memory address range for nvm memory
> is overlapping, how can I assign continuous addressing to both memories?
>
>
> [image: image.png]
> Thanks and Regards,
> Sadhana,
> Research Scholar-NITK,
> Dept. of Computer Science and Engineering
> .
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[gem5-users] Re: How se mode implements system calls for riscv

[Ayaz Akram via gem5-users]

Hi Srikanta,

You can find the implementation of system calls in src/sim/syscall_emul.cc
(and related files in the same directory). You can use the "strace" tool to
find out the syscalls used by a binary.

As far as multithreading is concerned, I think SE mode is not suitable for
that purpose and you might want to use FS mode of gem5.

-Ayaz

On Sun, Jul 16, 2023 at 9:59 PM Srikanta Chaitanya via gem5-users <
gem5-users@gem5.org> wrote:

> Hi ,
> I am simulating muticore riscv but when i fork threads it count is less
> than my spawn count ,
>
> I just want to read code of system calls , how they are implemented in
> gem5
>
> Please share me file names
>
> Let me know how to identify the system call from elf
>
> Please
> Thanks srikanta
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[gem5-users] Re: Analyzing instruction cycle count

[Ayaz Akram via gem5-users]

Hi Nick,

I wonder which optimization flag you are using while compiling your
program? My guess is the the behavior you are observing is because the
compiler is able to figure out that the x is a constant number that can be
determined statically and the binary it is generating in both cases
probably does not do anything (as there is nothing else in the loop as
well). As a result, you don't see any difference in cycle count.

As far as your blog post is concerned, please note that the format block
defines how your instruction will be executed in the simulation. Basically,
the value of `i' will not have any impact on the latency of the
instruction. To change the latency you will have to separately change the
latency of that opClass of the instruction you have added. For example, for
O3CPU you can have a look at the latencies of different instructions:

https://gem5.googlesource.com/public/gem5/+/refs/heads/develop/src/cpu/o3/FuncUnitConfig.py

-Ayaz

On Tue, Jul 11, 2023 at 6:16 PM Nick F via gem5-users 
wrote:

> Good afternoon,
>
> I have been trying to use Gem5 to research and study the performance of
> several different computer architectures. However, I have been noticing
> that I may be unable to accurately model the differences in cycle length
> for computer programs.
>
> Take for example these two programs:
>
> #include 
>
> int main(void)
> {
> for (uint32_t i = 0; i < 1000; i++) {
> uint32_t x = 5 * 6;
> if (x != 30) {
> return 1;
> }
> }
> return 0;
> }
>
> #include 
>
> int main(void)
> {
> for (uint32_t i = 0; i < 1000; i++) {
> uint32_t x = 5 + 6;
> if (x != 11) {
> return 1;
> }
> }
> return 0;
> }
>
> Compiling and running both individually on a basic RISC-V CPU config, they
> both exit at exactly 1,297,721,000. However, in a real system, each
> multiply operation would take longer and I'd suspect doing 1000
> multiplications would have even a tiny difference in performance. My own
> research would also have difficulties analyzing relative performance unless
> I'm missing something.
>
> Even custom instructions seem to execute in a single CPU cycle regardless
> of how the hardware would be implemented.
>
> Is there a good way to define cycle delays in my Gem5 environment? I can
> implement a "multiply" function inserts a bunch of no-ops, but that would
> make it more complicated when the program complexity grows.
>
> I've written a small blog post
> 
> exploring some of what I've tried in the past week. If anyone here has any
> suggestions I'd be interested to hear them.
>
> Thanks,
>
> Nick
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[gem5-users] Re: recvAtomicLogic() in mem_ctrl.cc

[Ayaz Akram via gem5-users]

Hi Eliot,

Based on my understanding, when pkt->makeResponse() is called it updates
the "cmd" of the pkt with the appropriate responseCommand (this line of
code: cmd = cmd.responseCommand();) . If you look at
"MemCmd::commandInfo[]"  in packet.cc, the response command for a
"WriteReq" command is "WriteResp". And the attributes of a "WriteResp"
command don't have "HasData", which is why the response pkt will return
false on a "hasData()" check.

You might also want to look at the struct CommandInfo in packet.hh.

-Ayaz

On Tue, Jul 11, 2023 at 2:15 PM Eliot Moss via gem5-users <
gem5-users@gem5.org> wrote:

> On 7/11/2023 3:03 PM, John Smith wrote:
> > Thanks for responding, Elliot. I somewhat understand that after the
> write is accomplished, the
> > returning packet won't have the data. But still, why is the returned
> value 0 in that case? Shouldn't
> > it still be equal to the memory access latency.
>
> In the Atomic case this code is assuming the write can
> be absorbed into a write buffer, so there is no additional
> latency visible to the user.  Of course it is *possible* to
> saturate the buffers, and if you want a more accurate
> accounting you can use a Timing model instead.
>
> EM
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[gem5-users] Re: recvAtomicLogic() in mem_ctrl.cc

[Ayaz Akram via gem5-users]

Hi John,

If you are checking if the pkt is write when pkt->hasData() condition is
true in recvAtomicLogic() function, the check (pkt_is_write) will always be
false. The reason is that a write pkt would have already written its data
to the memory (abstract memory) in the previous line of code
"mem_intr->access(pkt);" That access to the memory interface converts a
request pkt into a response pkt and adds or removes data from the pkt
(depending on if the request was a read or a write). Also, in this
implementation, the accessLatency will only be returned if the request was
a read request i.e., the write requests would not see any latency.

-Ayaz

On Tue, Jul 11, 2023 at 12:06 PM John Smith via gem5-users <
gem5-users@gem5.org> wrote:

> Thanks for responding, Elliot. I somewhat understand that after the write
> is accomplished, the returning packet won't have the data. But still, why
> is the returned value 0 in that case? Shouldn't it still be equal to the
> memory access latency.
>
> On Tue, Jul 11, 2023 at 2:34 PM Eliot Moss  wrote:
>
>> On 7/11/2023 1:28 PM, John Smith via gem5-users wrote:
>> > So, I used the function pkt->isWrite() to check if the packet is a
>> write request. And I observed
>> > that inside the pkt->hasData() if condition, pkt->isWrite() returned
>> false. Hence only the read
>> > packets were entering the if(pkt->hasData()) condition
>>
>> So you're saying that inside the if condition, pkt->isWrite is *always*
>> false?
>>
>> I see.  I couldn't find a place in the code (in the version I have
>> downloaded
>> anyway) where the data is dropped, but I can imagine it happening after
>> the
>> write is accomplished (though I don't see why), so that the "returning"
>> packet no longer has data.  What are the exact types of the components
>> involved?  And maybe someone else is more competent to answer this since
>> it
>> is somewhat stumping me from my reading of the code.
>>
>> Cheers - Eliot
>>
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[gem5-users] Re: Regarding the recvAtomic() function in mem_ctrl.cc

[Ayaz Akram via gem5-users]

Hi John,

What's the exact stat you are looking at for AMAT? My guess is that it is
not getting updated for Atomic mode memory accesses.

interface. If I change the code to:
> return mem_intr->accessLatency() + 100;
> Does this mean that it will take 100 more ticks for the memory controller
> to access the memory? If yes, then how can I visualize this change?


Yes, this means that the response from the controller will be delayed by
100 ticks. In case you are looking for a more detailed timing model, and
need to use Timing memory accesses, you can do something similar (adding
delay) by tweaking memory controllers' frontEnd and backEnd latency
parameters.

-Ayaz

On Thu, Jul 6, 2023 at 4:46 PM John Smith via gem5-users <
gem5-users@gem5.org> wrote:

> Hi everyone,
> I have a doubt regarding the operation of the recvAtomic() function in the
> memory controller. I can see that recvAtomic() calls recvAtomicLogic(),
> which returns the access latency from the memory interface. If I change the
> code to:
> return mem_intr->accessLatency() + 100;
>
> Does this mean that it will take 100 more ticks for the memory controller
> to access the memory? If yes, then how can I visualize this change? The
> AMAT stats in stats.txt are giving me 'nan' and even with the debug flags
> on, I cant exactly measure this change. Any help would be appreciated!
>
>
> --
> Regards,
> John Smith
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[gem5-users] Re: Browsing the gem5 codebase

[Ayaz Akram via gem5-users]

Hi John,

You can open gem5 code base in Microsoft VS Code to use different code
navigation options that work for any C/C++ project.

-Ayaz

On Wed, Jul 5, 2023 at 9:29 AM John Smith via gem5-users <
gem5-users@gem5.org> wrote:

> Is there a way to make browsing the gem5 codebase and performing
> functionalities like 'Go to Definition' easier?
>
> Thanks,
> John
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[gem5-users] Re: How to port designs simulated on gem5 to real time FPGAs

[Ayaz Akram via gem5-users]

Hi Saras,

I don't think there is a way to convert your gem5 model to an FPGA board as
gem5 models are cycle-level models and not not cycle-accurate/cycle-exact.
The paper you have referred to, shows how to use gem5 performance numbers
and pass them to McPAT, ArchFP, and HotSpot to get power,area, and heat
estimations.

I think there has been work done to convert Chisel based cycle-accurate
models to gem5 models (for example using Verilator), but not the other way
around. If your configuration/model looks similar to Rocket/Boom I think
the best option would be to make same changes in Chisel models and deploy
them on an FPGA.

-Ayaz

On Thu, Jun 29, 2023 at 12:12 PM saras nanda via gem5-users <
gem5-users@gem5.org> wrote:

> Hi all ,
>
> I am curious to know how to port a design made on gem5 on to a FPGA board ,
> there is a bit of gap in my mind on the steps that i would want to
> follow,i found a paper in this line which shows the following steps
> [image: Screenshot from 2023-06-29 15-03-31.png]
>
> paper: https://carrv.github.io/2017/papers/roelke-risc5-carrv2017.pdf
>
> so if i use Archfp then i would be able to port my design to rocketchip or
> BOOM projects ,then i can port it to FPGA board?please let me know if these
> steps are right
>
> Regards
> saras
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[gem5-users] Re: Creating Checkpoint with KVM cpu and restore with Timing cpu

[Ayaz Akram via gem5-users]

Hi Hansika,


>1. Is there anything I'm doing wrong or missing or does checkpointing
>usually take hours like this?
>
> I don't think there is anything wrong with how you are trying to create
the checkpoint. If the cpt.tick_value directory is created and has contents
in it, that means the checkpoint is created. Depending on the size of the
checkpoint and your filesystem, taking the checkpoint can be slow but it
should not take hours. I actually tried your command with the same
kernel/disk versions and used the gem5  "release-staging-v23-0" branch and
things seem to work fine for me i.e., the checkpoint is taken and the
simulation terminates after that.


>1. Is there a better way to do fast forwarding without using
>checkpoints? (I cannot use new gem5 standard library because it does
>not support garnet, therefore I need to use fs.py)
>
>
The alternative is to just switch CPUs at runtime (once you are about to
start your benchmark of interest). Example of how to do that (assuming that
you cannot use standard library) can be found in older versions of
gem5-resources (for example:
https://gem5.googlesource.com/public/gem5-resources/+/refs/tags/v21.0.1.0/src/npb/configs/run_npb.py).
However, please note that those scripts might not work with the latest gem5
version and require small changes.

-Ayaz



On Fri, Jun 30, 2023 at 3:32 PM Hansika Weerasena via gem5-users <
gem5-users@gem5.org> wrote:

> Hi,
>
> I want to boot up Linux with *X86KvmCPU *and switch to TimingCpu to run
> some benchmarks, and I needed to run them with garnet interconnection
> network. I’m planning to do switching via checkpoint (loading checkpoint
> with TimingCPU).
>
> Following is the command I used to run gem5 in full system mode and create
> the checkpoint. The details on versions can be found at the end.
>
> *./build/X86/gem5.opt configs/example/fs.py
> --disk-image=dist/x86-ubuntu.img --kernel=dist/vmlinux-4.4.186 --num-cpus=4
> --num-dirs=4 --cpu-type=X86KvmCPU --cpu-clock=2GHz --caches --l1d_size=16kB
> --l1i_size=16kB --l2cache --num-l2cache=4 --mem-type=SimpleMemory
> --mem-size=2GB --ruby --network=garnet --topology=Mesh_XY --mesh-rows=2
> --script=config/boot/hack_back_ckpt.rcS*
>
>
> system.pc.com_1.device shows the last message as "*Checkpointing
> simulation..." *and I can see a folder *cpt.* created at
> m5out directory. But the simulation is hanging there for more than two
> hours. I would like to know :
>
>1. Is there anything I'm doing wrong or missing or does checkpointing
>usually take hours like this?
>2. Does checkpointing works with KvmCPU ?
>3. Is there a better way to do fast forwarding without using
>checkpoints? (I cannot use new gem5 standard library because it does not
>support garnet, therefore I need to use fs.py)
>
>
> *gem5 version : 22.0.0.1*
>
> disk image : x86-ubuntu-18.04-img from the gem5 resources :
> https://resources.gem5.org/resources/x86-ubuntu-18.04-img?database=gem5-resources=1.0.0
>
> kernel : x86-linux-kernel-4.4.186 from gem5 resources :
> https://resources.gem5.org/resources/x86-linux-kernel-4.4.186?version=1.0.0
>
> Regards,
> Hansika Weerasena
>
> Hansika Weerasena
>
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[gem5-users] Re: Simple Switchable Processor with checkpoint restoration

[Ayaz Akram via gem5-users]

Hi Abdal,

Assuming that you run into this problem when using different start and
switch core types for SimpleSwitchable processor in your script, I think
the main problem is that on restore the start core type is not the same as
the core with which you took the checkpoint (which I am assuming was the
switch core type, let me know if that is not the case). I think you can
restore your checkpoint using SimpleProcessor as well. However, in that
case if you want to switch again after restoring you would not be able to
do so. Another solution/option is to create a new class that inherits from
SimpleSwitchableProcessor in which you just swap the start and switch keys,
for example some thing like following:

self._start_key = "switch"
self._switch_key = "start"


And then use this new processor type in your restore script. This way
you will restore with the correct CPU type and if you want to switch
to a different CPU type you can do that as well.

-Ayaz


On Mon, Jun 19, 2023 at 11:45 AM AbdelQader AlKilany via gem5-users <
gem5-users@gem5.org> wrote:

> Hello gem5 users,
>
>
>
>
>
> I was having some trouble trying to restore a simulation from a checkpoint
> when using a stdlib switchable processor (SimpleSwitchableProcessor).
>
>
>
> When I would attempt to run a simulation like this the simulation would
> freeze up and not restore the checkpoint at all.
>
>
>
> I was wondering whether this functionality had been implemented yet or
> whether there was another way to achieve this using by adding to one of the
> processor or configuration scripts.
>
>
>
> The only difference I could find between SwitchableProcessor and
> SimpleProcessor (which restored checkpoints fine) was that the former
> inherits directly from AbstractProcessor and the latter inherits from
> BaseCPUProcessor so I thought some functionality may have been added to
> BaseCPUProcessor which wasn’t available in AbstractProcessor alone.
>
>
>
> Thank you for any help! 
>
>
>
> Kind Regards,
>
> Abdal
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[gem5-users] Re: Fatal error for when clflush is included in workload for O3 system simulation

[Ayaz Akram via gem5-users]

Hi Shaikhul,

I think clflush is not supported in Ruby caches at the moment. For
reference, here is the original patch that added support for clflush
instruction in gem5:

arch-x86: Adding clflush, clflushopt, clwb instructions (7401) · Gerrit
Code Review (googlesource.com)


-Ayaz

On Fri, Jun 16, 2023 at 2:49 PM Khan Shaikhul Hadi via gem5-users <
gem5-users@gem5.org> wrote:

> Hi,
> When I include "clflush" instruction for out-of-order execution simulation
> in MESITwoLevelCacheHeirarchy, it givis following error:
>
> build/X86/mem/ruby/system/RubyPort.cc:433: fatal: Ruby functional read
>> failed for address 0x1f2b80
>
>
> Commenting out clflush operations seems to solve the problem. Any idea why
> it could happen? does CLFLUSH properly implemented in Two Level MESI
> protocol ?
>
> I'm not proficient in gem5 debugging, but what I've observed is that this
> fatal error is caused by some read request packet, surprisingly not any
> flush request.  Also, If I commented out the fatal error message, system
> gives warning as follows:
>
> build/X86/mem/ruby/system/RubyPort.cc:267: warn: Cache maintenance
>> operations are not supported in Ruby.
>
>
> and completes execution, no crash or other type of error message. I don't
> know what "Cache maintenance operations" means here and is it related to
> the previous error.
>
> I'm pretty confused and can't figure out how to approach. Anyone have any
> suggestions ? I want to understand how clflush operation is simulated in
> gem5 so that I could modify it for my research needs. I have attached my
> configuration script and workload C++ file here.
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[gem5-users] Re: Question about checkpoints

[Ayaz Akram via gem5-users]

Hi,

I've realised though I'm not sure this may work as intended. Do the
> checkpoints gem5 generates include a memory dump of instructions loaded
> from a binary as well as stack/heap working data too? I'm intending for all
> instructions to be loaded out of the binary I pass on checkpoint restore,
> rather than out of the checkpoint. Is anybody able to confirm for me
> whether or not this is actually the case?


I doubt that restoring will work the way you intend to. Based on my
understanding, the checkpoint contains a dump of the physical memory and
the architectural state and the simulation will restore from exactly the
same state/memory image.  That means the simulation will resume with the
old program loaded into the memory.

-Ayaz

On Wed, Jun 14, 2023 at 4:09 AM muke101 via gem5-users 
wrote:

> I'm generating checkpoints from spec for a research project. I have a use
> case where I'm introducing novel instructions but they only have OoO core
> semantics rather than program semantics, and any binary I modify to include
> them has the exact same addresses for functions, basic blocks etc as an
> unmodified binary.
>
> My method to generate checkpoints has been to run a binary without novel
> instructions natively to generate simpoints, generate the checkpoints with
> gem5 passing the unmodified binaries, then restore the checkpoints passing
> the modified binaries that have the novel instructions.
>
> I've realised though I'm not sure this may work as intended. Do the
> checkpoints gem5 generates include a memory dump of instructions loaded
> from a binary as well as stack/heap working data too? I'm intending for all
> instructions to be loaded out of the binary I pass on checkpoint restore,
> rather than out of the checkpoint. Is anybody able to confirm for me
> whether or not this is actually the case?
>
> Thanks.
>
>
> Sent from Proton Mail mobile
>
>
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[gem5-users] Re: Writing a script to run multiple simulations at once

[Ayaz Akram via gem5-users]

Hi Derek,

I am not sure if I have understood your question correctly, but the gem5
interface is basically a Python run script in which you can add parameters
as well (that can be set from the command line or in shell scripts). For
example, you can look at the following link to see how `argparse` is used
for this purpose:

https://www.gem5.org/documentation/learning_gem5/part1/cache_config/

-Ayaz

On Tue, Jun 13, 2023 at 11:32 PM Derek Christ via gem5-users <
gem5-users@gem5.org> wrote:

> Hello,
>
> maybe I have missed something in the official docs, but I'm not sure how
> to run multiple simulations with different parameters concurrently to
> speed up the process.
>
> What I have done is I created a Python script that sets environment
> variables and then kicks-off gem5 which in turn runs another Python
> script that reads those environment variables to configure the simulation.
> But I'm sure there has to be a better way?
>
> I think it might be easier if it would be possible to run gem5 purely
> with Python (without the gem5 executable) because then it would be easy
> to pass custom parameters to the gem5 configuration.
>
> Is there something that I missed?
>
> Thanks
>
> Best
> Derek
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[gem5-users] Re: Integrate mcpat to gem5 simulation

[Ayaz Akram via gem5-users]

Hi Qian,

Based on my understanding, people use scripts to convert gem5
statistics/configs to McPAT understandable statistics/configs and there are
multiple scripts around to do that. You might find some help from the
following resource:

https://github.com/saideeptiku/Gem5McPatParser
http://users.ece.utexas.edu/~ljohn/teaching/382m-15/assignments/assignment4.pdf

-Ayaz

On Sat, Jun 10, 2023 at 12:02 AM 李强 via gem5-users 
wrote:

> Hi, everyone:
>
> How can I integrate McPAT power estimation tool to gem5, to try DVFS
> control on simulated MultiCore system? I konw it's a big question to
> answer, but can anyone provide me some tips or basic flow to do this?
>
> Thanks
>
>
> Qiang
>
>
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[gem5-users] Re: Modeling DRAM memory latencies

[Ayaz Akram via gem5-users]

Hi Vincent,

I think the simplest way to add additional latency is to change the
frontend/backend latency parameters of the memory controller (for
reference: src/mem/MemCtrl.py). Though you can also try to change the DRAM
timing parameters, but that can be much more complicated due to the
relation between different timing parameters.

-Ayaz

On Sat, Jun 10, 2023 at 11:36 AM Vincent Abraham via gem5-users <
gem5-users@gem5.org> wrote:

> I'm extremely sorry if I worded my question incorrectly. I'm actually
> trying to introduce a delay whenever a read/write request happens in the
> main memory. For example, in a memory write, the data would only be flagged
> as dirty after a 10ns delay.
>
> Regardless, thanks a lot for the response!
>
> On Sat, Jun 10, 2023 at 12:28 PM Eliot Moss  wrote:
>
>> On 6/10/2023 11:12 AM, Vincent Abraham via gem5-users wrote:
>> > Hi everyone,
>> > I'm trying to model additional latencies in the main memory while
>> performing write/read operations.
>> > Could anyone tell me how I could go about doing it?
>>
>> Of course the dram module has a gazillion timing and energy parameters
>> that
>> you can simply look up in your config.ini file, if that's what you mean.
>>
>> But I suspect you want to know something like the distribution of access
>> times.  You can see comm_monitor for statistics examples (and the memory
>> controller already has a lot as well), but it might go roughly like this.
>>
>> First, set up a map in the controller module along these lines:
>>
>> hash_map arrivalTime;
>>
>> When a packet arrives at the controller, put it into the map like this:
>>
>> arrivalTime.emplace(pkt, curTick());
>>
>> Later, when the packet has finished processing, you can find out how long
>> it
>> took by code like this:
>>
>> auto it = arrivalTime.find(pkt);
>> assert(it != arrivalTime.end);  // it really should be there
>> Tick arrival = it->second;
>> Tick latency = curTick() - arrival;
>> arrivalTime.erase(it);
>>
>> The other part is recording statistics.  To get a histogram over all
>> packets,
>> declare a stat like this as a member of the memory controller's class:
>>
>> Stats::Histogram pktLatencies;
>>
>> In the controller module's regStats function, add this:
>>
>> pktLatencies
>>  .init(20) // or whatever number of buckets you want
>>  .name(name() + ".pkt_latencies")
>>  .desc("Histogram of packet latencies")
>>  .flags(cdf | dist | nozero);  // I like cdf, but pdf can be good too
>>
>> Of course you don't have to use a histogram, and you don't have to use
>> just
>> one.  For example, you could have one for reads and one for writes, and
>> enter
>> packets conditionalized on isRead() and isWrite().
>>
>> The one piece I did not mention yet is adding a sample to the histogram.
>> When
>> a packet finishes and you know its latency, just do:
>>
>> arrivalTimes.sample(latency);
>>
>> The magic of stats will do the rest.
>>
>> Cheers - Eliot Moss
>>
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[gem5-users] Re: Possible bug between X86 processors?

[Ayaz Akram via gem5-users]

Hi,

The question is: Do I build the AMD system differently?


gem5 does not need to be built differently on different host platforms.

build/X86/base/loader/image_file_data.cc:54: panic: panic condition sz != 2
> occurred: Couldn't read magic bytes from object file


This error usually shows up if there is something wrong with the elf of the
binary that is being simulated (for example different ISA than the ISA gem5
binary expects). I wonder if you see the same error for other
binaries/programs on the AMD system?

-Ayaz

On Sat, Jun 3, 2023 at 11:12 AM Beser, Nicholas D. via gem5-users <
gem5-users@gem5.org> wrote:

> I am working my way through the bootcamp 2022 tutorial, and I noticed
> something odd. It suggests that if I have different types of X86
> processors, I may have issues in execution.
>
>
>
> I was working with two different systems. A slower (6 core) VM system
> (genuine intel), and a AMD Ryzen 9 16 core processor. I tried to run the
> hello-world-with-cache-complete.py code on both systems. The VM system
> succeeded. The AMD system failed. In addition to the terminal output, I am
> including the output of lscpu. The question is: Do I build the AMD system
> differently? I recompiled the matrix-multiply routine thinking that it
> might have a problem with the executable, but I got the same error:
>
>
>
> Here is the VM terminal dump:
>
>
>
> $ build/X86/gem5.opt
> ../materials/using-gem5/02-stdlib/complete/hello-world-with-cache-complete.py
>
>
> gem5 Simulator System.  https://www.gem5.org
>
> gem5 is copyrighted software; use the --copyright option for details.
>
>
>
> gem5 version 22.0.0.0
>
> gem5 compiled Jun  3 2023 10:44:14
>
> gem5 started Jun  3 2023 13:50:32
>
> gem5 executing on besernd1-vm5, pid 980747
>
> command line: build/X86/gem5.opt
> ../materials/using-gem5/02-stdlib/complete/hello-world-with-cache-complete.py
>
>
>
> warn: The `get_runtime_isa` function is deprecated. Please migrate away
> from using this function.
>
> warn: The simulate package is still in a beta state. The gem5 project does
> not guarantee the APIs within this package will remain consistent across
> upcoming releases.
>
> Global frequency set at 1 ticks per second
>
> warn: failed to generate dot output from m5out/config.dot
>
> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
> Mbytes) does not match the address range assigned (1024 Mbytes)
>
> 0: board.remote_gdb: listening for remote gdb on port 7000
>
> build/X86/sim/simulate.cc:194: info: Entering event queue @ 0.  Starting
> simulation...
>
> build/X86/sim/mem_state.cc:443: info: Increasing stack size by one page.
>
> build/X86/sim/syscall_emul.cc:74: warn: ignoring syscall mprotect(...)
>
> build/X86/sim/syscall_emul.cc:74: warn: ignoring syscall mprotect(...)
>
> build/X86/sim/syscall_emul.cc:74: warn: ignoring syscall mprotect(...)
>
> build/X86/sim/mem_state.cc:443: info: Increasing stack size by one page.
>
> build/X86/sim/mem_state.cc:443: info: Increasing stack size by one page.
>
> build/X86/sim/mem_state.cc:443: info: Increasing stack size by one page.
>
> build/X86/sim/mem_state.cc:443: info: Increasing stack size by one page.
>
> build/X86/sim/mem_state.cc:443: info: Increasing stack size by one page.
>
> build/X86/sim/mem_state.cc:443: info: Increasing stack size by one page.
>
> build/X86/sim/mem_state.cc:443: info: Increasing stack size by one page.
>
> build/X86/sim/mem_state.cc:443: info: Increasing stack size by one page.
>
> build/X86/sim/mem_state.cc:443: info: Increasing stack size by one page.
>
> build/X86/sim/mem_state.cc:443: info: Increasing stack size by one page.
>
> build/X86/sim/mem_state.cc:443: info: Increasing stack size by one page.
>
> build/X86/sim/mem_state.cc:443: info: Increasing stack size by one page.
>
> build/X86/sim/mem_state.cc:443: info: Increasing stack size by one page.
>
> build/X86/sim/mem_state.cc:443: info: Increasing stack size by one page.
>
> build/X86/sim/mem_state.cc:443: info: Increasing stack size by one page.
>
> build/X86/sim/mem_state.cc:443: info: Increasing stack size by one page.
>
> build/X86/sim/mem_state.cc:443: info: Increasing stack size by one page.
>
> build/X86/sim/mem_state.cc:443: info: Increasing stack size by one page.
>
> build/X86/sim/mem_state.cc:443: info: Increasing stack size by one page.
>
> build/X86/sim/mem_state.cc:443: info: Increasing stack size by one page.
>
> build/X86/sim/mem_state.cc:443: info: Increasing stack size by one page.
>
> build/X86/sim/mem_state.cc:443: info: Increasing stack size by one page.
>
> build/X86/sim/mem_state.cc:443: info: Increasing stack size by one page.
>
> build/X86/sim/mem_state.cc:443: info: Increasing stack size by one page.
>
> build/X86/sim/mem_state.cc:443: info: Increasing stack size by one page.
>
> build/X86/sim/mem_state.cc:443: info: Increasing stack size by one page.
>
> build/X86/sim/mem_state.cc:443: info: Increasing stack size by one page.
>
> build/X86/sim/mem_state.cc:443: info: 

[gem5-users] Re: Running gem5 with custom instructions

[Ayaz Akram via gem5-users]

Hi Nick,

One of the common reasons you might see the error you are noticing is if
you somehow end up using the host compiler instead of the RISC-V compiler.
I will recommend that you verify that riscv toolchain directory is added to
your $PATH. See this for reference:
https://github.com/riscv-software-src/riscv-tools/issues/292

-Ayaz

On Sat, Jun 3, 2023 at 9:36 AM Nick F via gem5-users 
wrote:

> Good afternoon folks,
>
> As part of a research project I have been trying to setup a Gem5
> simulation with a RISC-V ISA while adding in a custom operation. I found a
> handful of old articles
>  [2
> ]
> and videos  on how to accomplish this but
> appear to be out of date. I noticed there is a gem5 doc on ISA Parsing
> 
> that has a few unfinished sections.
>
> I tried following the tutorial but have run into some issues getting the
> RISC-V tools to compile.
>
> After spending a lot of time trying to build things, I've found myself
> stuck on this error when trying to build the riscv-pk project:
>
>
> gcc: error: unrecognized argument in option '-mcmodel=medany'
>
> gcc: note: valid arguments to '-mcmodel=' are: 32 kernel large medium small
> make: *** [Makefile:319: file.o] Error 1
>
> Does anyone know if I'm going down the wrong path here? Is there a good
> tutorial that you recommend?
>
> Thanks all,
>
> Nick Felker
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[gem5-users] Re: [EXT] Re: Question about running the hpca-2023 tutorial

[Ayaz Akram via gem5-users]

Hi everyone,

The examples from the tutorial repo (
https://github.com/gem5-hpca-2023/gem5-tutorial-codespace) seem to work for
me with the gem5/gem5-resources versions checked out in that repo. I
basically cloned the entire repo using the --recursive flag. If you are
using a different version of gem5, my guess is that your scripts might need
to be updated because of changes in the standard library.

-Ayaz


On Fri, Jun 2, 2023 at 12:28 PM Beser, Nicholas D. via gem5-users <
gem5-users@gem5.org> wrote:

> Thiago,
>
>
>
> I have had better luck working through the gem5 bootcamp 2022. I have run
> into some odd issues that I would love to compare notes with someone who
> knows the gem5 system. Some of the errors have to do with the directory
> organization of the gem5-bootcamp-env code from the github. I am running
> into python errors that suggest that the code is not able to find the
> python files. As an example when I run:
>
>
>
> build/X86/gem5.opt
> /home/besernd1/gem5-bootcamp-env/materials/using-gem5/02-stdlib/complete/hello-world-with-unique-cache.py
>
>
>
> I had to make some changes in the unique_cache_hierarchy_complete.py file
> because the python code could not see liCache.py. When I tried to run the
> hello-world example, it still does not see the python file. I also have to
> explicitly define the path to the customResource file, because it does not
> understand the abbreviated directory path provided.
>
>
>
> I also ran into a problem with some of the earlier examples. I had to add
> a line in front of the m5.instantiate():
>
>
>
> board._pre_instantiate()
>
> m5.instantiate()
>
>
>
> This was not necessary in later examples fro 02-stdlib.
>
>
>
> Part of the problem has to do with the tutorial and bootcamp using the
> codespaces. I think we need clear instructions on how to do those examples
> with the basic gem5 installation.
>
>
>
> Nick
>
> *From:* Thiago Rodrigues via gem5-users 
> *Sent:* Thursday, June 1, 2023 11:13 AM
> *To:* The gem5 Users mailing list 
> *Cc:* Thiago Rodrigues 
> *Subject:* [EXT] [gem5-users] Re: Question about running the hpca-2023
> tutorial
>
>
>
> *APL external email warning: *Verify sender
> gem5-users-bounces+nick.beser=jhuapl@gem5.org before clicking links
> or attachments
>
>
>
> Hello, same problem here.
>
>
>
> I am using the Ubuntu 22.04 LTS and the latest gem5 stable version. I
> followed the HPCA(23) video tutorial and even used the available git
> codespace.
>
>
>
> I removed the "resource" related code lines and used a variable
> -> binary = "path_to_the_benchmark" <- to set the benchmark, and another
> error occurred: "Attribute_Error: 'str' object has no attribute
> 'get_local_path' in the" -> '(86) set_se_binary_workload.py' -< file
>
>
>
> After that I used the get_started scripts (part 1) and the benchmark
> worked just fine.
>
>
>
> The new Python API is very friendly but I could not use it.
>
>
>
> Em qua., 31 de mai. de 2023 às 10:31, Beser, Nicholas D. via gem5-users <
> gem5-users@gem5.org> escreveu:
>
> I was reviewing the tutorial with the hope that I could setup something
> similar for a class that I am teaching at Johns Hopkins Whiting School of
> Engineering. Is there a way of running this locally on my linux system. I
> have gem5 installed, and it runs the basic routines described in the
> getting started documentation. When I try to run the tutorial I get the
> following error:
>
>
>
> ~/gem5$ build/X86/gem5.opt
> ../gem5-tutorial-codespace/materials/hello-world.py
>
> gem5 Simulator System.  https://www.gem5.org
>
> gem5 is copyrighted software; use the --copyright option for details.
>
>
>
> gem5 version 22.1.0.0
>
> gem5 compiled May 30 2023 13:05:58
>
> gem5 started May 31 2023 09:12:10
>
> gem5 executing on besernd1-vm5, pid 862230
>
> command line: build/X86/gem5.opt
> ../gem5-tutorial-codespace/materials/hello-world.py
>
>
>
> ImportError: cannot import name 'obtain_resource' from
> 'gem5.resources.resource' (unknown location)
>
>
>
> At:
>
>   ../gem5-tutorial-codespace/materials/hello-world.py(6): 
>
>   build/X86/python/m5/main.py(597): main
>
>
>
> The github link: https://github.com/gem5-hpca-2023/gem5-tutorial-codespace
> does not give precise instructions on integrating any changes required back
> into gem5. I was wondering if there was a clearer procedure.
>
>
>
> Thank-you,
>
>
>
> Nick Beser
>
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>
>
>
>
> --
>
> Me. Thiago R. B. S Soares
>
> Professor do Instituto Federal do Piauí - IFPI
>
> Campus São Raimundo Nonato
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[gem5-users] Re: Run multiple instances of gem5 in FS mode on a single host operating system

[Ayaz Akram via gem5-users]

Hi Lucas,

You should be able to launch multiple instances of gem5 at the same time. 
What’s the issue that you are facing? 

-Ayaz

> On May 31, 2023, at 9:33 AM, Lucas Zhang via gem5-users  
> wrote:
> 
> 
> I am a college student using gem5 for research.The performance of gem5's FS 
> mode is bad, and I don't know whether it can make use of multiple CPU cores 
> to improve the performance(I guess no). Anyway, running multiple instances of 
> gem5 in FS mode on a single host operating system can also help, but I've 
> tried to do this and didn't make it. So I'd like to is it feasible and how 
> can I run multiple instances? 
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[gem5-users] Re: How to create riscv mesi 3 level or ruby

[Ayaz Akram via gem5-users]

Hi Srikanta,

gem5 stdlib supports MESI_Three_Level (
https://gem5.googlesource.com/public/gem5/+/refs/heads/develop/src/python/gem5/components/cachehierarchies/ruby/mesi_three_level_cache_hierarchy.py)
which you should be able to use with RISC-V. You might want to look at the
examples in
https://gem5.googlesource.com/public/gem5/+/refs/heads/develop/configs/example/gem5_library/
to see how you can use any cache hierarchy component.

-Ayaz

On Mon, May 22, 2023 at 4:38 AM Srikanta Chaitanya via gem5-users <
gem5-users@gem5.org> wrote:

> Hi I am new to gem5, help in how to create riscv ruby mem model please
> help me ..
>
> Thanks in advance ..
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[gem5-users] Re: Fail to bootup with KVM on X86 arch

[Ayaz Akram via gem5-users]

Hi,

It does not seem like there is anything wrong with your simulation from the
terminal output you shared. Please, note that this example script will boot
a system with KVM CPU, switch to Timing CPU and then exit the simulation
(comment in the file might be useful:
https://gem5.googlesource.com/public/gem5/+/refs/heads/develop/configs/example/gem5_library/x86-ubuntu-run-with-kvm.py
).

-Ayaz

On Tue, May 23, 2023 at 2:16 AM jtzhangxpgz via gem5-users <
gem5-users@gem5.org> wrote:

> hello,everyone!
> I follow the steps in
> https://www.gem5.org/documentation/general_docs/using_kvm/
> then  I start the simulation using ./build/X86/gem5.opt
> configs/example/gem5_library/x86-ubuntu-run-with-kvm.py
>
> but  something wrong happen,here is the message :
>
> --
> zjt@Ubuntu20:~/gem5_bak/gem5$ ./build/X86/gem5.opt
> configs/example/gem5_library/x86-ubuntu-run-with-kvm.py
> gem5 Simulator System.  https://www.gem5.org
> gem5 is copyrighted software; use the --copyright option for details.
>
> gem5 version 22.1.0.0
> gem5 compiled May 23 2023 15:52:30
> gem5 started May 23 2023 17:07:15
> gem5 executing on Ubuntu20, pid 34005
> command line: ./build/X86/gem5.opt
> configs/example/gem5_library/x86-ubuntu-run-with-kvm.py
>
> warn: The simulate package is still in a beta state. The gem5 project does
> not guarantee the APIs within this package will remain consistent across
> upcoming releases.
> Global frequency set at 1 ticks per second
> build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
> Mbytes) does not match the address range assigned (4096 Mbytes)
> build/X86/sim/kernel_workload.cc:46: info: kernel located at:
> /home/zjt/.cache/gem5/x86-linux-kernel-5.4.49
> build/X86/base/statistics.hh:280: warn: One of the stats is a legacy stat.
> Legacy stat is a stat that does not belong to any statistics::Group. Legacy
> stat is deprecated.
>   0: board.pc.south_bridge.cmos.rtc: Real-time clock set to Sun Jan  1
> 00:00:00 2012
> board.pc.com_1.device: Listening for connections on port 3456
> build/X86/dev/intel_8254_timer.cc:128: warn: Reading current count from
> inactive timer.
> 0: board.remote_gdb: listening for remote gdb on port 7000
> build/X86/cpu/kvm/base.cc:150: info: KVM: Coalesced MMIO disabled by
> config.
> build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x:
> unimplemented function 2
> build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x:
> unimplemented function 3
> build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x:
> unimplemented function 4
> build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x:
> unimplemented function 5
> build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x:
> unimplemented function 6
> build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x:
> unimplemented function 8
> build/X86/cpu/kvm/base.cc:150: info: KVM: Coalesced MMIO disabled by
> config.
> build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x:
> unimplemented function 2
> build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x:
> unimplemented function 3
> build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x:
> unimplemented function 4
> build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x:
> unimplemented function 5
> build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x:
> unimplemented function 6
> build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x:
> unimplemented function 8
> build/X86/sim/simulate.cc:192: info: Entering event queue @ 0.  Starting
> simulation...
> build/X86/arch/x86/kvm/x86_cpu.cc:1562: warn: kvm-x86: MSR (0x3a)
> unsupported by gem5. Skipping.
> build/X86/arch/x86/kvm/x86_cpu.cc:1562: warn: kvm-x86: MSR (0x48)
> unsupported by gem5. Skipping.
> build/X86/arch/x86/kvm/x86_cpu.cc:1562: warn: kvm-x86: MSR (0xe1)
> unsupported by gem5. Skipping.
> build/X86/arch/x86/kvm/x86_cpu.cc:1562: warn: kvm-x86: MSR (0x309)
> unsupported by gem5. Skipping.
> build/X86/arch/x86/kvm/x86_cpu.cc:1562: warn: kvm-x86: MSR (0x30a)
> unsupported by gem5. Skipping.
> build/X86/arch/x86/kvm/x86_cpu.cc:1562: warn: kvm-x86: MSR (0x30b)
> unsupported by gem5. Skipping.
> build/X86/arch/x86/kvm/x86_cpu.cc:1562: warn: kvm-x86: MSR (0x38d)
> unsupported by gem5. Skipping.
> build/X86/arch/x86/kvm/x86_cpu.cc:1562: warn: kvm-x86: MSR (0x38e)
> unsupported by gem5. Skipping.
> build/X86/arch/x86/kvm/x86_cpu.cc:1562: warn: kvm-x86: MSR (0x38f)
> unsupported by gem5. Skipping.
> build/X86/arch/x86/kvm/x86_cpu.cc:1562: warn: kvm-x86: MSR (0x390)
> unsupported by gem5. Skipping.
> build/X86/arch/x86/kvm/x86_cpu.cc:1562: warn: kvm-x86: MSR (0xc1)
> unsupported by gem5. Skipping.
> build/X86/arch/x86/kvm/x86_cpu.cc:1562: warn: kvm-x86: MSR (0xc2)
> unsupported by gem5. Skipping.
> build/X86/arch/x86/kvm/x86_cpu.cc:1562: warn: kvm-x86: MSR (0xc3)
> unsupported by gem5. Skipping.
> build/X86/arch/x86/kvm/x86_cpu.cc:1562: warn: kvm-x86: MSR (0xc4)
> 

[gem5-users] Re: Performance difference in full system (FS) and system emulation (SE) mode

[Ayaz Akram via gem5-users]

Hi Vipin,

In my opinion, 3% difference is probably not something to worry about.
However, there could be many reasons for the difference. As SE mode will
use predefined memory address mapping, and thread schedule, that might
cause differences compared to the full-system mode.

Can the difference in the clock cycle of the memory controller and cache
> proxy port result in such differences? What can be the other possible
> reasons?


If you are using the same memory system configuration for both modes, the
memory controller clock should be the same and not impact the difference
you are observing (in my opinion).

-Ayaz

On Fri, May 26, 2023 at 7:16 AM VIPIN PATEL via gem5-users <
gem5-users@gem5.org> wrote:

> Hi All,
>
>
> I ran the attached microbenchmark (test1.c) with gem5 in FS and SE mode. I
> am interested in the stats only for the region marked with the ROI marker.
>
>
> I assume the FS mode is similar to or slower than the SE mode for the
> microbenchmark in the ROI, but the stats point otherwise. The FS mode is 3%
> faster than the SE mode.
>
>
>  I am using the gem5 V20 for SE mode, and the gem5 provided resources
> V20.0.3
>  
> for
> FS mode.
>
> Can the difference in the clock cycle of the memory controller and cache
> proxy port result in such differences? What can be the other possible
> reasons?
>
>
> Regards,
>
> Vipin
>
> Ph.D. Scholar IIT Kanpur
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[gem5-users] Re: SMT in full system mode

[Ayaz Akram via gem5-users]

Hi Ishita,

Regarding SMT in FS mode, you might find the discussion in the comments of
the following JIRA issue helpful:

[GEM5-332] SMT simulation in x86 is not supported - Jira (atlassian.net)


-Ayaz

On Thu, May 18, 2023 at 10:22 PM Ishita Chaturvedi via gem5-users <
gem5-users@gem5.org> wrote:

> Hi,
>
> I want to run SMT in FS mode, however, the support does not exist for it.
>
> Is there a reason for this support to not be available? Is it easy to
> implement SMT in FS mode?
>
> Thanks!
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[gem5-users] Re: How do I fix extraDataValid error while trying to run a test program on a gem5 simple ARM configuration with cache?

[Ayaz Akram via gem5-users]

Hi Pedro,

I tried this test and noticed the same problem. However, the test seems to
work if you use example/se.py script. For example, following command worked:

build/ARM/gem5.opt configs/example/se.py -c
tests/test-progs/hello/bin/arm/linux/hello --cpu-type=TimingSimpleCPU
--caches

I would suggest you to look at m5out/config.ini files from both runs and
see what's different between the two configurations. That might help you to
figure out how to modify your simulation script to make it work for ARM.

-Ayaz

On Wed, May 10, 2023 at 9:39 AM Pedro Corrêa Rigotto via gem5-users <
gem5-users@gem5.org> wrote:

> Good afternoon.
> I encountered this error while trying to run an ARM configuration with one
> of the scripts in the learning_gem5 folder. The following is my post on
> Stack Overflow, which received an answer directing me to this mailing list.
>
> I am learning how to use gem5. I followed the learning_gem5 book and
> successfully ran the suggested test programs on an ARM simple configuration
> without cache. For my research, I need to test caches on ARM systems, so I
> tried to adapt the simple_cache.py file to run on ARM, like what was done
> to simple.py to generate simple-arm.py. However, when trying to run the
> "hello" test program, or the other two that were suggested in the
> "Extending gem5 for ARM" page, I get the following error:
>
> gem5.opt: build/ARM/mem/request.hh:882: uint64_t 
> gem5::Request::getExtraData() const: Assertion `extraDataValid()' failed.
> Program aborted at tick 12162000
>
> The full terminal log is available at https://pastebin.com/VLJ1Szxy. The
> config file is available at https://pastebin.com/SeajkNPT.
>
> I tried changing the test file to the Bubblesort and FloatMM files. I
> checked the request source code to try to understand more about the error.
> I expected the simulation to run like it did with simple-arm.py. I followed
> the tutorial on this page:
> https://www.gem5.org/documentation/learning_gem5/part1/extending_configs
> Does anyone know what causes this error and how it may be fixed?
> Thank you for your attention,
> Pedro Corrêa Rigotto
> Computer Science undergraduate at PUC Minas
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[gem5-users] Re: (1 of 3) A start job is running for...twork interfaces (14s / 5min 1s)

[Ayaz Akram via gem5-users]

Hi Xiang,

>From the guest terminal output you shared, it seems like it is busy running
systemd services after the kernel boot. Simulating those can take a long
time. How long has it been running for?

-Ayaz

On Wed, May 10, 2023 at 5:07 PM Xiang Li via gem5-users 
wrote:

> Hi,
> I'm running a X86 full-system, which needs a about 30G memory. When I'm
> running the FS, it would say ' Welcome to Ubuntu 16.04.7 LTS!', and then
> somehing like these:
> '''
> systemd[1]: Reached target Encrypted Volumes.
> [  OK  ] Reached target Encrypted Volumes.
> systemd[1]: Listening on fsck to fsckd communication Socket.
> [  OK  ] Listening on fsck to fsckd communication Socket.
> systemd[1]: Listening on udev Kernel Socket.
> [  OK  ] Listening on udev Kernel Socket.
> systemd[1]: Started Trigger resolvconf update for networkd DNS.
> [  OK  ] Started Trigger resolvconf update for networkd DNS.
> systemd[1]: Created slice System Slice.
> [  OK  ] Created slice System Slice.
> systemd[1]: Listening on udev Control Socket.
> [  OK  ] Listening on udev Control Socket.
> ...
> [  OK  ] Started LSB: AppArmor initialization.
>  Starting Raise network interfaces...
> [  *** ] (1 of 3) A start job is running for...twork interfaces (14s /
> 5min 1s)
> '''
> Someone says that's because I don't have enough swap space, but I made a
> 30G swap space for my host, and I used --mem-size=3MB in the command.
> Maybe because my disk-img file only have a 8.5G space? Could please tell me
> why? It would run several hours. Thanks,
>
> Best wish,
> Xiang
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[gem5-users] Re: gem5 won't exit when running 'riscv-tests' in bare metal mode

[Ayaz Akram via gem5-users]

Hi Evangelos,

The problem with these tests (in gem5) is discussed here (
https://gem5.atlassian.net/browse/GEM5-938) in detail. Since they get stuck
in a loop after executing some instructions (and I think this happens when
the useful part of the benchmark is done), probably using max insts is a
reasonable solution, but you will have to figure out the (max) number of
insts. for each test separately.

-Ayaz

On Mon, May 8, 2023 at 10:26 AM Kioulos Evangelos via gem5-users <
gem5-users@gem5.org> wrote:

> Hey everyone,
>
> I'm running tests from the 'riscv-tests' suite in gem5 bare metal mode.
> The tests won't stop running and gem5 never exits.
> I've tried using m5_exit, but it doesn't seem to work. To fix the issue, I
> used a max instruction limit.
>
> Is there a better way to do this? Are m5ops supported in bare metal mode?
>
> Thank you in advance for your help!
> Evangelos
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[gem5-users] Re: RISCVMatchedBoard FS

[Ayaz Akram via gem5-users]

Hi Nikos,

I think the simulation might take that long if "-i" flag is not used as the
simulation will try to boot Ubuntu. If there is no progress even much later
than 2 hours, something else might be going on there.

-Ayaz

On Tue, May 2, 2023 at 4:40 AM Νικόλαος Ταμπουρατζής via gem5-users <
gem5-users@gem5.org> wrote:

> Dear gem5 community,
>
> I try to simulate RISCV FS using the RISCVMatchedBoard but after 2 hours
> it does not get output in the terminal. Specifically, I use the following
> command (with latest gem5 version): ./build/RISCV/gem5.opt
> configs/example/gem5_library/riscvmatched-fs.py
>
> To be noticed that it boots successfully FS with the generic RiscvBoard
> using:
> ./build/RISCV/gem5.opt configs/example/gem5_library/riscv-ubuntu-run.py
>
>
> Best regards,
> Nikos
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[gem5-users] Re: How to stop running scipt when starting fs

[Ayaz Akram via gem5-users]

Yes, in that case, you might want to remove the last "m5 exit" in your init
script.

-Ayaz

On Sun, Apr 30, 2023 at 2:29 PM Xiang Li via gem5-users 
wrote:

> Hi Ayaz,
>
> Thanks for your reply. I used qemu to build a Ubuntu16.04 image. My OS
> booted fully now but it exit automatically, I don't have chance to type
> command. I mean I want to boot the OS and type command just like a normal
> Ubuntu. I guess I can't have a "m5 exit" right?
>
> Best wish,
> Xiang
>  Replied Message 
> From Ayaz Akram via gem5-users 
> Date 05/01/2023 03:47
> To The gem5 Users mailing list 
> Cc Xiang Li ,
> Ayaz Akram 
> Subject [gem5-users] Re: How to stop running scipt when starting fs
> Hi Xiang Li,
>
> Based on your shared guest terminal output, OS has yet to boot fully. Your
> init script probably has not been executed yet. In case you don't care
> about systemd, you can also change the kernel arguments in the gem5 run
> script to directly run your init script once the kernel has booted. Also, I
> am not fully sure what disk image you are using, but please make sure that
> the init script you have modified executes "m5 exit" so that the simulation
> can be terminated.
>
> -Ayaz
>
> On Sun, Apr 30, 2023 at 8:32 AM Xiang Li via gem5-users <
> gem5-users@gem5.org> wrote:
>
>> Hi,
>> I'm trying to running a X86 full-system, it seems like it would run a
>> script and exit automatically. I have delated the second if-fi from
>> gem5init, but it doesn't work. Could you please tell how to do that?
>>
>>
>> ...
>>
>> VFS: Mounted root (ext4 filesystem) on device 3:1.
>>
>> devtmpfs: mounted
>>
>> Freeing unused kernel memory: 1200K
>>
>> Write protecting the kernel read-only data: 12288k
>>
>> Freeing unused kernel memory: 2020K
>>
>> Freeing unused kernel memory: 92K
>>
>> rodata_test: all tests were successful
>>
>> systemd[1]: System time before build time, advancing clock.
>>
>> random: systemd: uninitialized urandom read (16 bytes read)
>>
>> systemd[1]: systemd 229 running in system mode. (+PAM +AUDIT +SELINUX
>> +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL
>> +XZ -LZ4 +SECCOMP +BLKID +ELFUTILS +KMOD -IDN)
>>
>> systemd[1]: Detected architecture x86-64.
>>
>>
>>
>> Welcome to [1mUbuntu 16.04.7 LTS[0m!
>>
>>
>>
>> systemd[1]: Set hostname to .
>>
>> random: systemd: uninitialized urandom read (16 bytes read)
>>
>> random: systemd: uninitialized urandom read (16 bytes read)
>>
>> systemd[1]: Listening on LVM2 metadata daemon socket.
>>
>> [[0;32m  OK  [0m] Listening on LVM2 metadata daemon socket.
>>
>> systemd[1]: Listening on /dev/initctl Compatibility Named Pipe.
>>
>> [[0;32m  OK  [0m] Listening on /dev/initctl Compatibility Named Pipe.
>>
>> systemd[1]: Reached target User and Group Name Lookups.
>>
>> [[0;32m  OK  [0m] Reached target User and Group Name Lookups.
>>
>> systemd[1]: Listening on Journal Socket.
>>
>> [[0;32m  OK  [0m] Listening on Journal Socket.
>>
>> systemd[1]: Listening on fsck to fsckd communication Socket.
>>
>> [[0;32m  OK  [0m] Listening on fsck to fsckd communication Socket.
>>
>> systemd[1]: Listening on udev Kernel Socket.
>>
>> [[0;32m  OK  [0m] Listening on udev Kernel Socket.
>>
>> systemd[1]: Listening on Journal Audit Socket.
>>
>> [[0;32m  OK  [0m] Listening on Journal Audit Socket.
>>
>> [[0;32m  OK  [0m] Started Forward Password Requests to Wall Directory
>> Watch.
>>
>> [[0;32m  OK  [0m] Reached target Encrypted Volumes.
>>
>> [[0;32m  OK  [0m] Started Trigger resolvconf update for networkd DNS.
>>
>> [[0;32m  OK  [0m] Listening on LVM2 poll daemon socket.
>>
>> [[0;32m  OK  [0m] Listening on Journal Socket (/dev/log).
>>
>> [[0;32m  OK  [0m] Created slice System Slice.
>>
>> [[0;32m  OK  [0m] Started Read required files in advance.
>>
>>  Mounting Debug File System...
>>
>>  Starting Set console keymap...
>>
>>  Starting Load Kernel Modules...
>>
>>  Mounting POSIX Message Queue File System...
>>
>>  Starting Create Static Device Nodes in /dev...
>>
>> [[0;32m  OK  [0m] Created slice system-serial\x2dgetty.slice.
>>
>>  Starting Nameserver information manager...
>>
>>  Starting Remount Root and Kernel File Systems...
>>
>>  Mounting Huge

[gem5-users] Re: GEM5 dcache dual-porting

[Ayaz Akram via gem5-users]

Hi,

Based on my understanding, I think if you configure multiple load
functional units that would be equivalent to multiple dcache ports.
However, using multiple LQs might require changes in the source code.

-Ayaz

On Mon, Apr 24, 2023 at 11:42 PM G via gem5-users 
wrote:

> Hello,
>
> Seems default O3 CPU has single load queue and have single port to dcache,
> is there way we can configure dual port dcache and have 2 LQs working in
> parallel?
>
> Thanks
>
> G
> ginger...@163.com
>
> 
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[gem5-users] Re: RISC-V full system simulation: adding benchmarks to disk image

[Ayaz Akram via gem5-users]

You might find some useful things in these slides:  PowerPoint Presentation
(gem5.org)
<https://www.gem5.org/assets/files/isca2022-tutorial/gem5-stdlib-tutorial.pdf>.
But, mainly, you just need to change the following line in the fs script
(assuming you are using riscv full system example from gem5 source):

disk_image=Resource("riscv-disk-img")

-Ayaz

On Sun, Apr 30, 2023 at 1:02 PM Vladimir Milicevic <
vladimirmilice...@cmail.carleton.ca> wrote:

> Thank you Ayaz.
>
> Is there documentation for the CustomResource command, or an example?
> Also is there any recommendation for modifying the disk image
> successfully? I cannot see my benchmarks when the OS is loaded.
>
> Thank you in advance.
>
> Sent from my iPhone
>
> On Apr 30, 2023, at 3:53 PM, Ayaz Akram  wrote:
>
> 
> [External Email]
> Hi Vladimir,
>
> You can modify the riscv fs script and use CustomResource for the disk
> image resource by passing the path to your modified disk image. This will
> ensure that gem5 is using your disk image and not redownloading a clean
> resource.
>
> -Ayaz
>
> On Sun, Apr 30, 2023 at 9:13 AM Vladimir Milicevic via gem5-users <
> gem5-users@gem5.org> wrote:
>
>> I’m running UCanLinux full-system simulation on RISC-V using the
>> instructions found here: http://resources.gem5.org/resources/riscv-fs
>> With the intention to enable multi-threaded and multi-core simulations
>> with the host OS.
>>
>> Now that I have it up and running, I’m looking for how to modify the
>> riscv_disk disk image from above to include my benchmark programs.
>> Using the mount instructions in the guide and copying the files into the
>> image before booting in GEM5 does not appear to work.
>> When I try to do this, it appears either GEM5 redownloads a clean image -
>> OR - my copied benchmark suit is not visible on the UCanLinux filesystem.
>>
>>
>> Are there any guiding instructions to copy benchmark programs into the
>> bootable disk image for GEM5? Thank you in advance.
>> This email contains links to content or websites. Always be cautious when
>> opening external links or attachments.
>>
>> Please visit https://carleton.ca/its/help-centre/report-phishing/ for
>> information on reporting phishing messages.
>>
>> When in doubt, the ITS Service Desk can provide assistance.
>> https://carleton.ca/its/chat
>>
>> -End of Disclaimer-
>>
>>
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[gem5-users] Re: RISC-V full system simulation: adding benchmarks to disk image

[Ayaz Akram via gem5-users]

Hi Vladimir,

You can modify the riscv fs script and use CustomResource for the disk
image resource by passing the path to your modified disk image. This will
ensure that gem5 is using your disk image and not redownloading a clean
resource.

-Ayaz

On Sun, Apr 30, 2023 at 9:13 AM Vladimir Milicevic via gem5-users <
gem5-users@gem5.org> wrote:

> I’m running UCanLinux full-system simulation on RISC-V using the
> instructions found here: http://resources.gem5.org/resources/riscv-fs
> With the intention to enable multi-threaded and multi-core simulations
> with the host OS.
>
> Now that I have it up and running, I’m looking for how to modify the
> riscv_disk disk image from above to include my benchmark programs.
> Using the mount instructions in the guide and copying the files into the
> image before booting in GEM5 does not appear to work.
> When I try to do this, it appears either GEM5 redownloads a clean image -
> OR - my copied benchmark suit is not visible on the UCanLinux filesystem.
>
>
> Are there any guiding instructions to copy benchmark programs into the
> bootable disk image for GEM5? Thank you in advance.
> This email contains links to content or websites. Always be cautious when
> opening external links or attachments.
>
> Please visit https://carleton.ca/its/help-centre/report-phishing/ for
> information on reporting phishing messages.
>
> When in doubt, the ITS Service Desk can provide assistance.
> https://carleton.ca/its/chat
>
> -End of Disclaimer-
>
>
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[gem5-users] Re: How to stop running scipt when starting fs

[Ayaz Akram via gem5-users]

Hi Xiang Li,

Based on your shared guest terminal output, OS has yet to boot fully. Your
init script probably has not been executed yet. In case you don't care
about systemd, you can also change the kernel arguments in the gem5 run
script to directly run your init script once the kernel has booted. Also, I
am not fully sure what disk image you are using, but please make sure that
the init script you have modified executes "m5 exit" so that the simulation
can be terminated.

-Ayaz

On Sun, Apr 30, 2023 at 8:32 AM Xiang Li via gem5-users 
wrote:

> Hi,
> I'm trying to running a X86 full-system, it seems like it would run a
> script and exit automatically. I have delated the second if-fi from
> gem5init, but it doesn't work. Could you please tell how to do that?
>
>
> ...
>
> VFS: Mounted root (ext4 filesystem) on device 3:1.
>
> devtmpfs: mounted
>
> Freeing unused kernel memory: 1200K
>
> Write protecting the kernel read-only data: 12288k
>
> Freeing unused kernel memory: 2020K
>
> Freeing unused kernel memory: 92K
>
> rodata_test: all tests were successful
>
> systemd[1]: System time before build time, advancing clock.
>
> random: systemd: uninitialized urandom read (16 bytes read)
>
> systemd[1]: systemd 229 running in system mode. (+PAM +AUDIT +SELINUX +IMA
> +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ
> -LZ4 +SECCOMP +BLKID +ELFUTILS +KMOD -IDN)
>
> systemd[1]: Detected architecture x86-64.
>
>
>
> Welcome to [1mUbuntu 16.04.7 LTS[0m!
>
>
>
> systemd[1]: Set hostname to .
>
> random: systemd: uninitialized urandom read (16 bytes read)
>
> random: systemd: uninitialized urandom read (16 bytes read)
>
> systemd[1]: Listening on LVM2 metadata daemon socket.
>
> [[0;32m  OK  [0m] Listening on LVM2 metadata daemon socket.
>
> systemd[1]: Listening on /dev/initctl Compatibility Named Pipe.
>
> [[0;32m  OK  [0m] Listening on /dev/initctl Compatibility Named Pipe.
>
> systemd[1]: Reached target User and Group Name Lookups.
>
> [[0;32m  OK  [0m] Reached target User and Group Name Lookups.
>
> systemd[1]: Listening on Journal Socket.
>
> [[0;32m  OK  [0m] Listening on Journal Socket.
>
> systemd[1]: Listening on fsck to fsckd communication Socket.
>
> [[0;32m  OK  [0m] Listening on fsck to fsckd communication Socket.
>
> systemd[1]: Listening on udev Kernel Socket.
>
> [[0;32m  OK  [0m] Listening on udev Kernel Socket.
>
> systemd[1]: Listening on Journal Audit Socket.
>
> [[0;32m  OK  [0m] Listening on Journal Audit Socket.
>
> [[0;32m  OK  [0m] Started Forward Password Requests to Wall Directory
> Watch.
>
> [[0;32m  OK  [0m] Reached target Encrypted Volumes.
>
> [[0;32m  OK  [0m] Started Trigger resolvconf update for networkd DNS.
>
> [[0;32m  OK  [0m] Listening on LVM2 poll daemon socket.
>
> [[0;32m  OK  [0m] Listening on Journal Socket (/dev/log).
>
> [[0;32m  OK  [0m] Created slice System Slice.
>
> [[0;32m  OK  [0m] Started Read required files in advance.
>
>  Mounting Debug File System...
>
>  Starting Set console keymap...
>
>  Starting Load Kernel Modules...
>
>  Mounting POSIX Message Queue File System...
>
>  Starting Create Static Device Nodes in /dev...
>
> [[0;32m  OK  [0m] Created slice system-serial\x2dgetty.slice.
>
>  Starting Nameserver information manager...
>
>  Starting Remount Root and Kernel File Systems...
>
>  Mounting Huge Pages File System...
>
> [[0;32m  OK  [0m] Listening on Syslog Socket.
>
>  Starting Journal Service...
>
>  Starting Uncomplicated firewall...
>
> [[0;32m  OK  [0m] Listening on udev Control Socket.
>
> [[0;32m  OK  [0m] Created slice User and Session Slice.
>
> [[0;32m  OK  [0m] Reached target Slices.
>
> [[0;32m  OK  [0m] Listening on Device-mapper event daemon FIFOs.
>
>  Starting Monitoring of LVM2 mirrors... dmeventd or progress
> polling...
>
> [[0;32m  OK  [0m] Started Uncomplicated firewall.
>
> [[0;32m  OK  [0m] Mounted POSIX Message Queue File System.
>
> [[0;32m  OK  [0m] Mounted Debug File System.
>
> [[0;32m  OK  [0m] Mounted Huge Pages File System.
>
> [[0;32m  OK  [0m] Started Nameserver information manager.
>
> [[0;32m  OK  [0m] Reached target Network (Pre).
>
> [[0;1;31mFAILED[0m] Failed to start Load Kernel Modules.
>
> See 'systemctl status systemd-modules-load.service' for details.
>
>  Mounting FUSE Control File System...
>
>  Starting Apply Kernel Variables...
>
>  Mounting Configuration File System...
>
> [[0;32m  OK  [0m] Mounted Configuration File System.
>
> [[0;32m  OK  [0m] Started Apply Kernel Variables.
>
> [[0;32m  OK  [0m] Mounted FUSE Control File System.
>
> [[0;32m  OK  [0m] Started Create Static Device Nodes in /dev.
>
>  Starting udev Kernel Device Manager...
>
> [[0;32m  OK  [0m] Started Remount Root and Kernel File Systems.
>
>  Starting udev Coldplug all Devices...
>
>  Starting Load/Save Random Seed...
>
> [[0;32m  OK  [0m] Started LVM2 metadata daemon.
>
> 

[gem5-users] Re: Question about gem5 tutorial

[Ayaz Akram via gem5-users]

Hi Dr. Nick Beser,

I am working my way through the tutorial and I have some questions. I
> noticed that the tutorial at:
> https://www.gem5.org/documentation/learning_gem5/part1/cache_config/ has
> a section called Adding parameters to your script. It describes the parser
> arguments that seem to be built in to the current caches.py. The segment of
> code is not in the example full scripts caches.py and two_level.py. Are
> these examples that should be added to new runs to make sure we can modify
> the parameters?


I think that is right. If you want to modify the parameters, you can add
argparse related code block in your script.

I found the statistics file for gem5 in the m5out directory. Is that the
> limit of the output statistics? I can see that to generate a performance
> versus size of cache experiment, I will have the students run through
> multiple parameters and then parse the stats.txt file.


Given a particular configuration, all the available statistics will be in
the stats.txt file. Please, note that the available statistics depend on
the system you are simulating. For example, an O3 CPU-based simulation will
have more/different statistics than an Atomic CPU-based simulation.

Also based on my reading, gem5 has several CPU designs built in to the
> system (X86, RISCV, MIPS, SPARC, and ARM). Are there block diagrams of the
> internal CPU simulations available? The diagram would assist the user in
> defining memory and control interfaces.


gem5 tries to separate ISA from the CPU as much as possible. So, all the
supported ISAs can be used with all the available CPU models (Atomic,
Timing, O3) except KVM. gem5 documentation has a page on CPU models that
provide a summary of the available models with some diagrams (gem5: gem5's
CPU models ).

If you have not already looked at it, I think gem5 BootCamp (from last
year) is a good reference to get more information on different aspects of
gem5 (gem5 Bootcamp 2022 | Learning gem5 Bootcamp 2022
).

-Ayaz

On Sun, Apr 30, 2023 at 8:21 AM Beser, Nicholas D. via gem5-users <
gem5-users@gem5.org> wrote:

> I am working my way through the tutorial and I have some questions. I
> noticed that the tutorial at:
> https://www.gem5.org/documentation/learning_gem5/part1/cache_config/ has
> a section called Adding parameters to your script. It describes the parser
> arguments that seem to be built in to the current caches.py. The segment of
> code is not in the example full scripts caches.py and two_level.py. Are
> these examples that should be added to new runs to make sure we can modify
> the parameters?
>
>
>
> I found the statistics file for gem5 in the m5out directory. Is that the
> limit of the output statistics? I can see that to generate a performance
> versus size of cache experiment, I will have the students run through
> multiple parameters and then parse the stats.txt file.
>
>
>
> Also based on my reading, gem5 has several CPU designs built in to the
> system (X86, RISCV, MIPS, SPARC, and ARM). Are there block diagrams of the
> internal CPU simulations available? The diagram would assist the user in
> defining memory and control interfaces.
>
>
>
> I am working up a set of lecture for an advanced computer architecture
> class which will include a tutorial, and a class project. I am trying to
> find existing art that might help me tailor the lecture notes.
>
>
>
> Dr. Nick Beser
>
> Johns Hopkins University
>
> Whiting School of Engineering
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[gem5-users] Re: Running a machine learning model on gem5

[Ayaz Akram via gem5-users]

Hi Saras,

If you have a disk image with a machine learning model and relevant
libraries installed, you should be able to use it with gem5. I would
suggest looking at the examples of full-system simulation with gem5.
Secondly, you might want to look at how to modify disk images with QEMU and
test your workload on QEMU. If the model works on QEMU, I think
theoretically it should work on gem5 as well.

-Ayaz

On Thu, Apr 20, 2023 at 2:53 PM saras nanda via gem5-users <
gem5-users@gem5.org> wrote:

> Hi ,
>
>
> I am new to gem5. I would like to know if I can run a machine-learning
> model on gem5. Would gem5 accept external libraries like TensorFlow,
> PyTorch..etc. please provide me with some first steps to approach this
> problem of running a machine learning model on gem5.
>
> regards
> saras
>
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[gem5-users] Re: SPEC2017 - Most of the metrics in m5.out/stats.txt are 0 or undefined

[Ayaz Akram via gem5-users]

Hi Farbin,

I think that change/fix is already merged.

-Ayaz

On Wed, Apr 12, 2023 at 1:47 PM Farbin Fayza  wrote:

> Hi everyone, thank you very much for co-operating. The stat file errors
> were resolved by the change that Humza mentioned. The stat file now
> contains non-zero metrics. Should I make changes and push them to the repo?
> Should it be in the "develop" branch of
> https://gem5.googlesource.com/public/gem5?
>
> Thanks,
> Farbin.
>
>
> On Fri, Apr 7, 2023 at 10:12 PM Eliot Moss  wrote:
>
>> On 4/7/2023 10:05 PM, Farbin Fayza via gem5-users wrote:
>> > Could you kindly tell me if there's any way to run the gem5 simulation
>> faster using multiple cores?
>> > Is it possible while we run SPEC?
>>
>> The only way is to run multiple distinct simulations in parallel.
>> This can be done by directing their outputs (both the gem5 output
>> and the simulated program's output) to different files.  When I
>> do this I also have some temporary mounts that I need to be
>> careful about so I copy the (fortunately small) different
>> mounted drive files.
>>
>> Anyway, I do this all the time.
>>
>> HTH -- Eliot Moss
>>
>
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[gem5-users] Re: Does Gem5 support arm64 SVE2?

[Ayaz Akram via gem5-users]

Hi Shuo,

If I am not mistaken, I think gem5 only supports SVE instructions.

-Ayaz

On Sun, Apr 9, 2023 at 7:44 PM Shuo via gem5-users 
wrote:

> hello,
>
> Does Gem5 support arm64 SVE2(Scalable Vector Extension2)?
>
> Yours
> Shuo
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[gem5-users] Re: gem5

[Ayaz Akram via gem5-users]

Hi,

You can configure some aspects of functional units (including ALU) in
detailed CPU models of gem5 (e.g., count, the particular type of operations
the unit will perform, latency etc.). For reference, please look
at src/cpu/o3/FuncUnitConfig.py.

-Ayaz

On Mon, Apr 10, 2023 at 8:32 PM 中国石油大学张天 via gem5-users 
wrote:

> Hello everyone. I wonder if it is possible to customize the ALU in gem5?
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[gem5-users] Re: SPEC2017 - Most of the metrics in m5.out/stats.txt are 0 or undefined

[Ayaz Akram via gem5-users]

Hi,

@Humza or @Farbin: Can you please push the spec-2017 change that worked for
you to the mainline gem5 as well?

Thanks,
-Ayaz

On Thu, Apr 6, 2023 at 9:03 PM Ayaz Akram  wrote:

> Hi Farbin,
>
> However, now they're taking so much time to run. I'm trying to run
>> perlbench, gcc, bwaves, and mcf with the "test" size, and they're running
>> for more than 10 hours and still, none of them aren't finished. Is this
>> normal? Could you tell me how long they usually take?
>
>
> I would expect these benchmarks (with test input) to take days to simulate
> completely. The actual simulation time would depend on the CPU type you are
> simulating and the hardware platform where the simulations are run. I think
> for Timing/Minor CPU you can expect a simulation rate of 400K-500K
> (simulated) instructions per host second.
>
> -Ayaz
>
> On Thu, Apr 6, 2023 at 10:36 AM Farbin Fayza via gem5-users <
> gem5-users@gem5.org> wrote:
>
>> Hi Humza,
>> Thank you so much for your help. I added the processor.switch() command
>> as you said and now the simulations are running.
>>
>> However, now they're taking so much time to run. I'm trying to run
>> perlbench, gcc, bwaves, and mcf with the "test" size, and they're running
>> for more than 10 hours and still, none of them aren't finished. Is this
>> normal? Could you tell me how long they usually take?
>>
>> Also, is there any way to verify that they are indeed running correctly?
>> Because in the m5out folder, there are no logs or something that I can
>> verify.
>>
>> About the index error, yes, I had the same issue too. Unfortunately, we
>> only have spec2017 currently and we urgently need to get things running. I
>> believe the index issue doesn't cause any other problems or affect the
>> stats, am I correct?
>>
>> Thanks so much again!
>> Farbin.
>>
>>
>> On Wed, Apr 5, 2023 at 7:52 PM Humza Ikram via gem5-users <
>> gem5-users@gem5.org> wrote:
>>
>>> Hi,
>>>
>>> I believe the reason for this is that the
>>> "x86-spec-cpu2017-benchmarks.py" file does not have a "process.switch()"
>>> statement and, as such, the processor remains in "CPUTypes.KVM" mode.
>>>
>>> If there is no other error when your script finishes, you could try
>>> adding "processor.switch()" infront of line number 290 in this file and
>>> trying again (before "yield False").
>>>
>>> I encountered the same issue in the spec-2006 benchmarks.
>>>
>>> Another issue I encountered in the spec-2006 benchmarks was related to
>>> an error you *may* face at the end that relates to accessing an out of
>>> bounds index of a python list. (This is because "ExitEvent.WORKBEGIN" and
>>> "ExitEvent.WORKEND" may not be defined in the workload.)
>>>
>>> Both of these are fixed in the spec-2006 benchmarks file (link below) in
>>> the develop branch and you could try moving them over to the spec-2017
>>> benchmarks file.
>>>
>>> https://gem5.googlesource.com/public/gem5/+/refs/heads/develop/configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py
>>>
>>> Thanks.
>>> Humza Ikram.
>>>
>>> --
>>> *From:* Farbin Fayza via gem5-users 
>>> *Sent:* Thursday, April 6, 2023 12:20 AM
>>> *To:* gem5-users@gem5.org 
>>> *Cc:* Farbin Fayza 
>>> *Subject:* [gem5-users] SPEC2017 - Most of the metrics in
>>> m5.out/stats.txt are 0 or undefined
>>>
>>> Hi,
>>> I'm trying to run spec2017 benchmark in full system mode with gem5. I
>>> followed this tutorial to build the disk image file for spec
>>> https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/src/spec-2017/
>>> .
>>> The only difference with the tutorial is that I have spec version, 1.1.9
>>> and in the tutorial they use 1.1.0. So I just changed the version in
>>> their scripts.
>>> The build was successful although it had some errors for some peak
>>> benchmarks.
>>>
>>> When I'm trying to run gem5 with this command:
>>> build/X86/gem5.opt \
>>> configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py \
>>> --image ../disk-image/spec-2017/spec-2017-image/spec-2017 \
>>> --partition 1 \
>>> --benchmark  \
>>> --size 
>>>
>>> The simulation is ending within minutes regardless of the workload size
>>> and all of the contents of the stat file (m5out/stats.txt) after hostOprate
>>> are 0 or undefined.
>>> Could anyone help with this issue?
>>>
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>>>
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[gem5-users] Re: Pretending totalOps is equivalent to totalInsts()

[Ayaz Akram via gem5-users]

Hi Kazi,

If you are referring to the "Pretending totalOps is equivalent to
totalInsts()", that is not really an error. It means that KVM CPU is
approximating totalOps with totalInsts (as the KVM model cannot count the
number of micro-ops that got executed on the native hardware) in the
generated stats.

-Ayaz

On Fri, Apr 7, 2023 at 5:05 AM Mejbaul Islam, Kazi M. via gem5-users <
gem5-users@gem5.org> wrote:

> Hello,
>
> I was trying to run gpu-fs following the instructions from
> https://resources.gem5.org/resources/rocm42 and when running PrefixSum
> using
>
> hip_samples.py, I have encountered following issue:
>
> Exiting @ tick 7022077441500 because m5_exit instruction encountered
> build/VEGA_X86/cpu/kvm/base.cc:572: hack: Pretending totalOps is equivalent 
> to totalInsts()
>
>
> I have not used gpu-fs before. I have gone through 
> build/VEGA_X86/cpu/kvm/base.cc but could not understand what is causing the 
> error. Can someone please clarify?
>
> Regards,
> Kazi
>
>
>
>
>
>
>
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[gem5-users] Re: SPEC2017 - Most of the metrics in m5.out/stats.txt are 0 or undefined

[Ayaz Akram via gem5-users]

Hi Farbin,

However, now they're taking so much time to run. I'm trying to run
> perlbench, gcc, bwaves, and mcf with the "test" size, and they're running
> for more than 10 hours and still, none of them aren't finished. Is this
> normal? Could you tell me how long they usually take?


I would expect these benchmarks (with test input) to take days to simulate
completely. The actual simulation time would depend on the CPU type you are
simulating and the hardware platform where the simulations are run. I think
for Timing/Minor CPU you can expect a simulation rate of 400K-500K
(simulated) instructions per host second.

-Ayaz

On Thu, Apr 6, 2023 at 10:36 AM Farbin Fayza via gem5-users <
gem5-users@gem5.org> wrote:

> Hi Humza,
> Thank you so much for your help. I added the processor.switch() command as
> you said and now the simulations are running.
>
> However, now they're taking so much time to run. I'm trying to run
> perlbench, gcc, bwaves, and mcf with the "test" size, and they're running
> for more than 10 hours and still, none of them aren't finished. Is this
> normal? Could you tell me how long they usually take?
>
> Also, is there any way to verify that they are indeed running correctly?
> Because in the m5out folder, there are no logs or something that I can
> verify.
>
> About the index error, yes, I had the same issue too. Unfortunately, we
> only have spec2017 currently and we urgently need to get things running. I
> believe the index issue doesn't cause any other problems or affect the
> stats, am I correct?
>
> Thanks so much again!
> Farbin.
>
>
> On Wed, Apr 5, 2023 at 7:52 PM Humza Ikram via gem5-users <
> gem5-users@gem5.org> wrote:
>
>> Hi,
>>
>> I believe the reason for this is that the
>> "x86-spec-cpu2017-benchmarks.py" file does not have a "process.switch()"
>> statement and, as such, the processor remains in "CPUTypes.KVM" mode.
>>
>> If there is no other error when your script finishes, you could try
>> adding "processor.switch()" infront of line number 290 in this file and
>> trying again (before "yield False").
>>
>> I encountered the same issue in the spec-2006 benchmarks.
>>
>> Another issue I encountered in the spec-2006 benchmarks was related to an
>> error you *may* face at the end that relates to accessing an out of
>> bounds index of a python list. (This is because "ExitEvent.WORKBEGIN" and
>> "ExitEvent.WORKEND" may not be defined in the workload.)
>>
>> Both of these are fixed in the spec-2006 benchmarks file (link below) in
>> the develop branch and you could try moving them over to the spec-2017
>> benchmarks file.
>>
>> https://gem5.googlesource.com/public/gem5/+/refs/heads/develop/configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py
>>
>> Thanks.
>> Humza Ikram.
>>
>> --
>> *From:* Farbin Fayza via gem5-users 
>> *Sent:* Thursday, April 6, 2023 12:20 AM
>> *To:* gem5-users@gem5.org 
>> *Cc:* Farbin Fayza 
>> *Subject:* [gem5-users] SPEC2017 - Most of the metrics in
>> m5.out/stats.txt are 0 or undefined
>>
>> Hi,
>> I'm trying to run spec2017 benchmark in full system mode with gem5. I
>> followed this tutorial to build the disk image file for spec
>> https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/src/spec-2017/
>> .
>> The only difference with the tutorial is that I have spec version, 1.1.9
>> and in the tutorial they use 1.1.0. So I just changed the version in
>> their scripts.
>> The build was successful although it had some errors for some peak
>> benchmarks.
>>
>> When I'm trying to run gem5 with this command:
>> build/X86/gem5.opt \
>> configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py \
>> --image ../disk-image/spec-2017/spec-2017-image/spec-2017 \
>> --partition 1 \
>> --benchmark  \
>> --size 
>>
>> The simulation is ending within minutes regardless of the workload size
>> and all of the contents of the stat file (m5out/stats.txt) after hostOprate
>> are 0 or undefined.
>> Could anyone help with this issue?
>>
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>>
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[gem5-users] Re: Running FS in example/gem5_library/x86-spec-cpu2017-benchmarks.py

[Ayaz Akram via gem5-users]

Hi Manish,

Can you provide more information about your test system? If you are running
gem5 inside a virtual machine, you should ensure the KVM configuration
change is also done on the host system.

-Ayaz

On Sun, Apr 2, 2023 at 5:24 PM Manish manchali via gem5-users <
gem5-users@gem5.org> wrote:

>
>
>  Hello
> I was also trying to do the same.
> /home/mmanchali/run_2_rsca/gem5-resources/src/spec-2017/gem5/build/X86/gem5.opt
> --outdir /home/mmanchali/project/gem5-resources/output/
> configs/run_spec.py  vmlinux-4.19.83
> disk-image/spec-2017/spec-2017-image/spec-2017  o3  503.bwaves_r test
>
>
>
> I get the same  fatal   PerfKvmCounter::attach failed (2) error.
> Everything else is similar to what  Abdelrahman was doing.
>
> The setting of perf_event_paranoid to 0 didn’t help.
>
> Is there something else missing?
> I would really appreciate the help.
> Thanks,
> Manish M
>
>
>
> Sent from Mail  for
> Windows
>
>
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[gem5-users] Re: Strange Behavior of checkpoint in multicore

[Ayaz Akram via gem5-users]

Hi Abdlerhman,

One possible explanation is as follows: You are running the same program on
all cores with the m5 checkpoint call and then you take at maximum one
checkpoint, which will be taken by whichever core hits the checkpoint call
first. In the first two cases you mentioned (Atomic vs. O3 CPU), the core
which takes the checkpoint could be different in both cases (and in
addition all the cores could be in a different state), and that means the
system state at the point of restore could be different which can lead to
difference in statistics you are observing. Please, note that the Atomic
CPU does not model timing of cache/memory accesses (in contrast to O3 CPU)
and as a result you might not be able to see the effects of shared
resources (e.g. LLC).

-Ayaz


On Fri, Mar 24, 2023 at 4:07 PM Abdlerhman Abotaleb via gem5-users <
gem5-users@gem5.org> wrote:

> I have a program bin.riscv that is running on 4 prcoessors simulatenously.
> Inside riscv.bin:
> // some code
> m5_checkpoint(0,0);
> m5_reset_stats(0,0);
> // some code
> I'm running GEM5 using the following commands:
>
>1. First
>gem5.opt ./configs/example/se.py -n 4 --caches --max-checkpoints 1
> --cpu-type AtomicSimpleCPU --cmd 'a.riscv;a.riscv;a.riscv;a.riscv'
>
>2. Then
>gem5.opt ./configs/example/se.py -n 4 --caches --checkpoint-restore=1
>--restore-with-cpu DerivO3CPU --cmd 'a.riscv;a.riscv;a.riscv;a.riscv'
>
> The statistics are different than if I run the same code (including
> writing checkpints and reset stats) but with the following gem5 command:
>
>1. gem5.opt ./configs/example/se.py -n 4 --caches --cpu-type
>DerivO3CPU --cmd 'a.riscv;a.riscv;a.riscv;a.riscv'
>
>
> It is worth mentioning that also the different CPUs don't have the same
> number of instructions instsIssued or numInsts (i.e committed instructions)
> (from GEM5 generated stats file) .
>
> Do you have explanations or any useful suggestions?
> Thanks.
>
>
>
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[gem5-users] Re: Demo problems

[Ayaz Akram via gem5-users]

Hi Kofi,

If you can list the specific problems you are running into, someone might
be able to help.

-Ayaz

On Fri, Mar 24, 2023 at 10:41 AM Kofi AN via gem5-users 
wrote:

> Hello all –
>
>
>
> I am trying to demonstrate effectiveness of cache replacement policies
> against cache attacks such as evict reload attack. I am emulating the SHARP
> paper. I have authored my benchmark, attack and defense programs. The
> benchmark runs fine but I am having trouble getting all 3 programs to run
> and produce the required data for analysis. I have had headache customizing
> the se.py file or getting a custom config to work.
>
>
>
> I am at this point trying to keep it simple with just running it on native
> se.py with no additional modifications. Any advice is welcome. I am willing
> to have a remote session to explain my issue if anyone is available.
>
>
>
> Thank you.
>
> Kofi AN
>
>
>
>
>
>
>
> Sent from Mail  for
> Windows
>
>
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[gem5-users] Re: Question about setting up to use NVM

[Ayaz Akram via gem5-users]

Hi Eliot,

Yes, that's right. The reason is that the parameter for memory interface in
MemCtrl.py (
https://gem5.googlesource.com/public/gem5/+/refs/heads/develop/src/mem/MemCtrl.py)
is called dram even though it can be an NVM interface. I think this should
be fixed to remove the confusion, but the change can also break existing
gem5 run scripts. In any case, I will try to push a change to make it less
confusing.

-Ayaz

On Sun, Mar 19, 2023 at 3:43 AM Eliot Moss  wrote:

> On 3/18/2023 10:40 PM, Ayaz Akram via gem5-users wrote:
> > Hi Eliot,
> >
> > MemCtrl() memory controller in gem5 can control a single DRAM interface
> or a single NVM interface at
> > a time. I think one way to verify that things are set-up correctly is to
> confirm this from the
> > "m5out/config.ini". If config.ini seems to be using 'MemCtrl' type for
> the memory controller and the
> > memory interface connected to the controller is of the type
> 'NVMInterface', I think that should
> > confirm that you are simulating an NVM device.
>
> Thanks, Ayaz!  Yes, that's what I get.  It seems odd that the component
> gets named blah-blah.dram, but it clearly says NVMInterface, so that's ok.
>
> I appreciate the confirmation.
>
> Eliot
>
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[gem5-users] Re: Question about setting up to use NVM

[Ayaz Akram via gem5-users]

Hi Eliot,

MemCtrl() memory controller in gem5 can control a single DRAM interface or
a single NVM interface at a time. I think one way to verify that things are
set-up correctly is to confirm this from the "m5out/config.ini". If
config.ini seems to be using 'MemCtrl' type for the memory controller and
the memory interface connected to the controller is of the type
'NVMInterface', I think that should confirm that you are simulating an NVM
device.

-Ayaz

On Sat, Mar 18, 2023 at 2:52 PM Eliot Moss via gem5-users <
gem5-users@gem5.org> wrote:

> Dear gem5-ers -
>
> I wanted to set up to use NVM only, so I tried this on the command line:
>
>--nvm-type=NVM_2400_1x64
>
> This had no effect.  Digging into configs/common/MemConfig.py was not
> directly
> enlightening.  However, it seems that Options.py sets mem-type to a
> particular
> DRAM by default.  Doing --mem-type=None does not work, giving an error
> message
> that None is not a valid memory type.
>
> What *seems* to work is saying this:
>
>--mem-type=NVM_2400_1x64
>
> If that is the "approved" way, then fine, but I wanted to make sure that I
> am
> not ending up with some strange mix of controller and device, part intended
> for DRAM and part for NVM ...
>
> (Maybe mem-type should be set to that default only if neither mem-type nor
> nvm-type are given?  I also noticed that the default and flags for "colors"
> are such that one cannot get colors printed any more.  I did a local fix,
> but maybe that was not intended?)
>
> Regards - Eliot Moss
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[gem5-users] Re: TLB Miss penalty in O3CPU and se.py

[Ayaz Akram via gem5-users]

Hi Haseung,

I am not sure if I have fully understood the question, but I will try to
answer based on my understanding (please let me know if I misunderstood).
SE mode, on a TLB miss, makes use of the gem5 managed page table for the
simulated process instead of modeling a page table walk and I guess that
might mean smaller TLB miss latency compared to a full system simulation
which uses page table walker and also the OS itself is simulated. Also, as
far as I remember there is not an explicit parameter for the tlb miss
penalty and in SE mode it might look similar to hit latency. Overall, I
think full-system simulation is a better choice if you care about the TLB
system latencies.

-Ayaz

On Tue, Mar 14, 2023 at 12:21 AM 봉하승 via gem5-users 
wrote:

> Hi,
>
>
> I’m currently simulating ARM O3CPU through SE mode.
>
> It was confirmed that generic page fault occurred and was restored in mmu.
>
>
> Does this process affect the entire cycle as a penalty?
>
>
> Regards,
>
> Haseung
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[gem5-users] Re: Adding new X86 memory instruction for O3CPU

[Ayaz Akram via gem5-users]

Hi Le Minh Son,

In my opinion, if you are well aware of the ISA specs and know how your new
instruction will fit in with the existing instructions, you might add a
real instruction. Otherwise, adding a pseudo instruction might be a better
option. Following are some of the references that you might find useful
while trying to add instructions in gem5 (please, note that some might be a
bit outdated):

-
https://gem5bootcamp.github.io/gem5-bootcamp-env/modules/developing%20gem5%20models/instructions/
- https://www.gem5.org/documentation/learning_gem5/gem5_101/homework-2
-
https://www.gem5.org/documentation/general_docs/architecture_support/x86_microop_isa/
-
https://www.eecg.utoronto.ca/~elsayed9/website/blog/gem5_arm_pseudo_inst.php
-
http://gedare-csphd.blogspot.com/2013/02/add-pseudo-instruction-to-gem5.html

-Ayaz


On Tue, Mar 14, 2023 at 8:07 PM ‍LE MINH SON[학생](대학원 전자공학과) via gem5-users <
gem5-users@gem5.org> wrote:

> Hello everyone,
>
> I am new to gem5.
> I want to do some computing-in-memory experiments by adding new x86 memory
> instructions for O3CPU in gem5.
> Should I add pseudo instruction or real instruction for this work?
> And How can I add it?
>
> Thank you!
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[gem5-users] Re: connect 2 memory devices on SystemXBus

[Ayaz Akram via gem5-users]

Hi Brian,

Can you share the script/configuration that ran into the problem with the
stable branch? I did a quick test with the traffic generator (with two
different mem devices) and things seem to work ok on my end.

Thanks,
-Ayaz

On Sat, Mar 11, 2023 at 9:33 AM Brian Chan via gem5-users <
gem5-users@gem5.org> wrote:

> it may be a bug of stable branch, after i checkout v21.0.0.0 it runs ok
>
> Brian Chan  于2023年3月11日周六 02:00写道：
>
>> Hello,
>> I'm trying to connect 2 different memory devices on a membus, it is like
>> cpu->membus->ctrls, and i set mem ranges to be [AddrRange('1MB'),
>> AddrRange('1MB', ''8MB')], I get Out of memory, but when i swap the ranges,
>> it runs ok, it seems only the first memory device is recognized.I'm not
>> sure if this is expected or i made some mistakes?
>> Thanks!
>>
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[gem5-users] Re: Documentation / explanation on configuring memory (also: thoughts on offering cache flush patches)

[Ayaz Akram via gem5-users]

Hi Eliot,

gem5 splits the memory system modeling into two parts: 1) the memory
controller and 2) the memory interface. The memory interface can be a
DRAMInterface or NVMInterface and provides many parameters that are
configured to achieve a specific memory device model (e.g., DDR4, GDDR5).
The available configuration parameters and their values for different
devices can be found in src/mem/DRAMInterface.py (this file provides
definitions of different timing parameters).

The memory controller usually is agnostic to the actual timing parameters
used by a memory interface and relies on a fixed interface to talk to the
device. However, we currently have three types of memory controllers in
gem5: MemCtrl (which can be used with a single memory interface of any
type), HeteroMemCtrl (which can be used with two memory interfaces at the
same time, a DRAM and an NVM interface), and HBMCtrl (which is used with
two HBM2 interfaces, where each interface is modeling a pseudo channel).

Some references that might be helpful to understand gem5's memory system
model include:

- gem5 workshop presentation should help explain the NVM model of gem5:
https://www.gem5.org/2020/05/27/memory-controller.html (Also, one of the
videos in this presentation discusses the refactorization of the original
mem controller into mem controller and memory interface).
- Minutes 37-52 of this gem5 bootcamp presentation:
https://www.youtube.com/live/hciJ9rguats?feature=share
- The original gem5 memory controller model paper:
https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6844484

-Ayaz

On Thu, Mar 9, 2023 at 2:12 PM Eliot Moss via gem5-users <
gem5-users@gem5.org> wrote:

> On 3/9/2023 3:01 PM, Eliot Moss via gem5-users wrote:
> > Dear gem5'ers - In my current simulation work it would be helpful to
> > understand better DRAM and NVM configuration.  How do I determine, and
> how do
> > I set, the number of channels, interleaving, etc.?  I'm far from being an
> > expert in memory devices / boards, so something that starts more from
> > fundamentals would be helpful (channels, ranks, banks, devices, etc.).
>
> Ok, in terms of the usual meaning of the concepts, I have found a
> number of resources on the web.  However, that still leaves a gap
> as to how to configure things in gem5 :-) ...  I'm hoping someone
> can enlighten me or points me to resources that can :-) ...
>
> Thanks - EM
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[gem5-users] Re: Interactive simulation with statistics per executable

[Ayaz Akram via gem5-users]

Hi Sebastian,

I am not aware of an existing example which does what are you looking for.
But, I think the best way to achieve this will be annotating your workloads
using m5 ops (you might have to add special m5 ops to recognize what
workload finished) to move control from the simulated system to your run
script if you want to analyze the state of the simulated system or change
something about it (there are limitations to what you can change though).

If you do not want to change the simulated system or want to analyze the
state of the simulated system, maybe the best option is to do everything
inside the simulated system (as you would typically run similar workloads
on a real machine with Linux OS on it). Basically, you can add any scripts
in your disk image to do what you are looking for.

As far as annotating the workloads is concerned, I think the following
references might be useful:

https://www.youtube.com/watch?v=0Gxuc8lel3Y
https://www.gem5.org/documentation/general_docs/m5ops/

-Ayaz

On Sun, Mar 5, 2023 at 11:49 PM Sebastian Weber 
wrote:

> Hi Ayaz,
>
>
>
> do you know any examples or specific parts of the source code that I
> should look at? Do you have any hints or tips how I can implement my use
> case?
>
>
>
> Thank you in advance,
>
> Sebastian
>
>
>
> *Von:* Sebastian Weber via gem5-users 
> *Gesendet:* Montag, 20. Februar 2023 11:27
> *An:* Ayaz Akram 
> *Cc:* The gem5 Users mailing list ; Sebastian Weber <
> sebastian.we...@fzi.de>
> *Betreff:* [gem5-users] Re: Interactive simulation with statistics per
> executable
>
>
>
> Hi Ayaz,
>
>
>
> yes, my goal is to analyze the execution of multiple independent workloads
> on a single hardware platform. Additionally, I need to be able to either
> adapt these workloads or add new workloads during the simulation, because
> the execution (results) of a workloads can influence when other workloads
> should be simulated.
>
>
>
> Best regards,
>
> Sebastian
>
>
>
> *Von:* Ayaz Akram 
> *Gesendet:* Donnerstag, 16. Februar 2023 11:12
> *An:* Sebastian Weber 
> *Cc:* The gem5 Users mailing list 
> *Betreff:* Re: [gem5-users] Re: Interactive simulation with statistics
> per executable
>
>
>
> Hi Sebastian,
>
>
>
> I don't think you can collect per-binary statistics (at least without
> changes in gem5 and potentially the guest OS) while simulating them
> simultaneously in a full-system simulation. Also, I am assuming you want to
> study the interaction of multiple workloads, and that's why you do not want
> to run multiple independent simulations (gem5 processes). Please, let me
> know if that is not your use case.
>
>
>
> -Ayaz
>
>
>
> On Tue, Feb 14, 2023 at 11:45 PM Sebastian Weber 
> wrote:
>
> Hi Ayaz,
>
>
>
> is it possible to use gem5 in the way described in my previous mail? I
> need to be able to dynamically add binaries to the current workload of gem5
> while other binaries are still running and to get statistics specific for
> single binaries, despite multiple binaries being executed simultaneously.
>
>
>
> Best regards,
>
> Sebastian
>
>
>
> *Von:* Sebastian Weber via gem5-users 
> *Gesendet:* Donnerstag, 2. Februar 2023 14:51
> *An:* Ayaz Akram ; The gem5 Users mailing list <
> gem5-users@gem5.org>
> *Cc:* Sebastian Weber 
> *Betreff:* [gem5-users] Re: Interactive simulation with statistics per
> executable
>
>
>
> Hi Ayaz,
>
>
>
> thank you for your quick response. My goal is to be able to initiate the
> execution of a binary in a FS simulation independently of currently running
> binaries, so I can’t use exit events. Keeping the control in the python
> script should be possible by only simulating a certain amount of cycles
> each step and managing the simulation between these steps, but I can’t
> change the workload from the python script without having to start another
> simulation. A predefined workload (board.set_kernel_disk_workload(…))
> won’t work therefore.
>
>
>
> Best regards,
>
> Sebastian
>
>
>
> *Von:* Ayaz Akram 
> *Gesendet:* Montag, 30. Januar 2023 23:17
> *An:* The gem5 Users mailing list 
> *Cc:* Sebastian Weber 
> *Betreff:* Re: [gem5-users] Interactive simulation with statistics per
> executable
>
>
>
> Hi Sebastian,
>
>
>
> I use [2] as starting point but I can’t change workloads in the python
> script and rerun the simulation because this would simulate another system
> instead of simulating another executable in the same system.
>
>
>
> Going to python script should not simulate another system, rather once you
> go back to the simulation loop your simulation will resume from the 

[gem5-users] Re: Retired instructions versus ticks

[Ayaz Akram via gem5-users]

Hi Priyanka,

By default, the dumped stats have the total number of instructions and
cycles/ticks for a specific simulation. If you want to look at these stats
over smaller time intervals, one possible option is to change your gem5 run
script to simulate for a specific time, dump stats, and keep repeating this
process until the finish point. As a result, your stats file will have
multiple instances of dumped stats.

For example, if you run something like the following in a loop:

m5.simulate(1000)
m5.stats.dump()

You will have stats corresponding to each "1000" ticks interval.

-Ayaz

On Thu, Feb 23, 2023 at 1:32 AM Priyanka Ankolekar via gem5-users <
gem5-users@gem5.org> wrote:

> Hello,
> Is there a way to get data for "instructions retired versus cycle or
> ticks" (system.cpu.exec_context.thread_0.numInsts versus cycle (or tick),
> and what are those instructions per tick)? Currently I can see the
> cumulative number for numInsts.
>
> Thanks,
> Priyanka.
>
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[gem5-users] Re: Questions about using gem5

[Ayaz Akram via gem5-users]

Hi,

Is there a way to simulate using DDR5 memory in gem5?


Currently, there is no DDR5 interface in gem5. I just pushed an in-progress
change here (
https://gem5-review.googlesource.com/c/public/gem5/+/68257/1/src/mem/DRAMInterface.py)
to support a single channel of DDR5.
This configuration still needs to be fully validated. But I will try to
merge it in the next few days (please, check back in a week or so).

Could you tell me in detail how to configure C code to access a specific
> address in memory to read and write data?


You can write or use any program/application accessing memory and use it as
a custom resource. If you do not care much about the CPU model, I suggest
looking at the traffic generator in gem5. You can find more information
about traffic generators here: https://www.youtube.com/watch?v=7QX-QdBtFGY

-Ayaz

On Mon, Feb 20, 2023 at 8:17 PM 한수진 via gem5-users 
wrote:

> Hi,
>
>
> I've been using gem5 simulator recently for some validation in my research.
>
> I have a question about using gem5, so I'm sending an email.
>
>
>
>
>
> 1.
>
>
> As a first question,
>
>
> Is there a way to simulate using DDR5 memory in gem5?
>
>
> I read the configuration of the different memory types available in gem5, but
> DDR5 memory type did not exist.
>
>
> Will DDR5 be updated? If so, when is it?
>
>
> If there is no update scheduled, is there any other way to simulate DDR5?
>
>
>
>
>
> 2.
>
>
> As a second question,
>
>
> I am trying to simulate a custom resource by direct C coding.
>
>
> How do I configure C code to make data read and write to a specific
> address in memory?
>
>
> Custom resource example provided by gem5 is simply a code that outputs
> "hello world" or performs addition and multiplication operations, so it is
> difficult to get ideas.
>
>
> Could you tell me in detail how to configure C code to access a specific
> address in memory to read and write data?
>
>
>
>
>
>
>
> Thank you in advance for your help!
>
>
>
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[gem5-users] Re: Requestor ID of a Packet - How it is generated

[Ayaz Akram via gem5-users]

Hi Abdlerhman,

I think your understanding of different requestor IDs for a single core is
correct i.e., these specify instruction and data requests.
"dataRequestorId()" and "instRequestorId()" functions in src/cpu/base.hh
verify this. I think prefetchers should also have their own requestor ids
as any object that can issue memory requests is assigned an id at the start
of the simulation.

-Ayaz

On Wed, Feb 15, 2023 at 8:51 PM Abdlerhman Abotaleb via gem5-users <
gem5-users@gem5.org> wrote:

> I want to identify the source CPU# of a packet.
> I found a field called "pkt->requestorId()"
> 
> This field originally can have the following options: "*Source:
> gem5/src/mem/request.hh*"
> *wbRequestorId *= 0, /* writeback requests by the caches */
> *funcRequestorId *= 1, /*  functional requests that  don't come from a
> particular device*/
> *intRequestorId *= 2,  /* message signaled interrupts */
> *invldRequestorId *= std::numeric_limits::max() /* Invalid
> requestor id for assertion checking only*/
> """
> Then inside the processor, when create a request this ID is assigned
> either _instRequestorId or _dataRequestorId.
>
> Now when run experiments with 4 cores , single thread :
> I have the following requestor ID values:
> Core 0 (IDs = 0x5,0x6)
> Core 1 (IDs = 0x9,0xA)
> Core 2 (IDs = 0xE,0xD)
> Core 3 (IDs = 0x11,0x12)
> *When have hardware prefetcher enabled*, the IDs get increased.
> ""
> Now my questions:
> How to associate the IDs found with the source core? How they IDs are
> being assigned?
> Why the same core can generate different requests with different IDs (May
> be one is data and other is instruction) ?
>  In case of HWP enabled , is it considered as an additional source ?
>
> Thank you so much for the help.
>
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[gem5-users] Re: Interactive simulation with statistics per executable

[Ayaz Akram via gem5-users]

Hi Sebastian,

I don't think you can collect per-binary statistics (at least without
changes in gem5 and potentially the guest OS) while simulating them
simultaneously in a full-system simulation. Also, I am assuming you want to
study the interaction of multiple workloads, and that's why you do not want
to run multiple independent simulations (gem5 processes). Please, let me
know if that is not your use case.

-Ayaz

On Tue, Feb 14, 2023 at 11:45 PM Sebastian Weber 
wrote:

> Hi Ayaz,
>
>
>
> is it possible to use gem5 in the way described in my previous mail? I
> need to be able to dynamically add binaries to the current workload of gem5
> while other binaries are still running and to get statistics specific for
> single binaries, despite multiple binaries being executed simultaneously.
>
>
>
> Best regards,
>
> Sebastian
>
>
>
> *Von:* Sebastian Weber via gem5-users 
> *Gesendet:* Donnerstag, 2. Februar 2023 14:51
> *An:* Ayaz Akram ; The gem5 Users mailing list <
> gem5-users@gem5.org>
> *Cc:* Sebastian Weber 
> *Betreff:* [gem5-users] Re: Interactive simulation with statistics per
> executable
>
>
>
> Hi Ayaz,
>
>
>
> thank you for your quick response. My goal is to be able to initiate the
> execution of a binary in a FS simulation independently of currently running
> binaries, so I can’t use exit events. Keeping the control in the python
> script should be possible by only simulating a certain amount of cycles
> each step and managing the simulation between these steps, but I can’t
> change the workload from the python script without having to start another
> simulation. A predefined workload (board.set_kernel_disk_workload(…))
> won’t work therefore.
>
>
>
> Best regards,
>
> Sebastian
>
>
>
> *Von:* Ayaz Akram 
> *Gesendet:* Montag, 30. Januar 2023 23:17
> *An:* The gem5 Users mailing list 
> *Cc:* Sebastian Weber 
> *Betreff:* Re: [gem5-users] Interactive simulation with statistics per
> executable
>
>
>
> Hi Sebastian,
>
>
>
> I use [2] as starting point but I can’t change workloads in the python
> script and rerun the simulation because this would simulate another system
> instead of simulating another executable in the same system.
>
>
>
> Going to python script should not simulate another system, rather once you
> go back to the simulation loop your simulation will resume from the point
> where it stopped.
>
>
>
> One way of what you are trying to achieve is to execute m5 utility (with
> the exit input for example, more on m5:
> https://www.gem5.org/documentation/general_docs/m5ops/) in the guest
> whenever one benchmark has finished. This will take stop the simulation and
> take the control to the python script where you can dump the stats
> (m5.stats.dump()), and then resume the simulation to execute the next
> benchmark. I will suggest taking a look at the following example script:
>
>
>
>
> https://github.com/gem5/gem5/blob/stable/configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py
>
>
>
> -Ayaz
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
> On Mon, Jan 30, 2023 at 12:46 AM Sebastian Weber via gem5-users <
> gem5-users@gem5.org> wrote:
>
> Hello,
>
>
>
> I am trying to use the current version of gem5 in full system mode
> interactively (--interactive) to be able to dump or reset statistics
> while connecting to the simulated console with m5term [1] (--listener-mode)
> to trigger the execution of executables. The goal is using gem5 in a
> co-simulation and being able to execute (multiple) binaries at arbitrary
> points in time during the simulation and getting binary-specific statistics
> after their execution. I use [2] as starting point but I can’t change
> workloads in the python script and rerun the simulation because this would
> simulate another system instead of simulating another executable in the
> same system. At the moment I am not able to trigger the execution of
> binaries with m5term and getting the statistics with the interactive mode,
> instead I always get empty statistics. My question is whether this setup of
> gem5 and m5term is able to generate statistics and if so, how to get them?
>
>
>
> Best regards,
>
> Sebastian Weber
>
>
>
> [1] https://www.gem5.org/documentation/general_docs/fullsystem/m5term
>
> [2]
> https://github.com/gem5/gem5/blob/stable/configs/example/gem5_library/x86-ubuntu-run-with-kvm.py
>
>
>
>
>
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[gem5-users] Re: Memory traces using CommMonitor

[Ayaz Akram via gem5-users]

Hi Sadhana,

SE mode, by default, uses a 4KB page size. You can convert the pkt
addresses generated by the commMonitor to page addresses manually or change
the commMonitor code to dump the page addresses.

-Ayaz

On Wed, Feb 15, 2023 at 9:08 PM Sadhana . 
wrote:

> Hai Ayaz,
> In addition to the previous query, is it possible to determine the page
> size supported during the simulation in SE mode. I understood that the
> commMonitor generates the physical address. Whether my understanding is
> correct. Since address length varies, I had doubts regarding this page
> size. Traces look like this:
>
> 7,r,980,4,256,0
> 7,r,984,4,256,77000
> 7,r,988,4,256,126000
> 8,r,474576,4,10,175000
> 7,r,992,4,256,238000
> 7,r,996,4,256,287000
> 8,w,474576,4,10,336000
> 7,r,1000,4,256,357000
> 8,w,474572,4,10,406000
> 7,r,1004,4,256,427000
> 8,r,1028,4,10,476000
> 7,r,1008,4,256,525000
> 8,w,474568,4,10,574000
>
> On Wed, Feb 15, 2023 at 9:12 AM Sadhana . 
> wrote:
>
>> Thank you.
>>
>> On Tue, Feb 14, 2023 at 4:34 PM Ayaz Akram  wrote:
>>
>>> Hi Sadhana,
>>>
>>> I think the first number is the requestor port id (IIRC). The above
>>> trace should have all requests to the main memory as your CommMonitor is
>>> connected between the membus and MemCtrl (and all memory traffic should go
>>> through it).
>>>
>>> -Ayaz
>>>
>>> On Mon, Feb 13, 2023 at 7:52 PM Sadhana . via gem5-users <
>>> gem5-users@gem5.org> wrote:
>>>
>>>> I am using gem5 for generation of memory traces. While going through
>>>> gem5 videos I found a method to generate traces using commMonitor. I have
>>>> modified the code as follows:
>>>> system.comm_monitor=CommMonitor()
>>>> system.comm_monitor.cpu_side_port=system.membus.mem_side_ports
>>>>
>>>> system.comm_monitor.trace=MemTraceProbe(trace_file=f"mem_trace",trace_compress=True)
>>>> #system.system_port = system.membus.slave
>>>> system.mem_ctrl=MemCtrl()
>>>> system.mem_ctrl.dram = DDR3_1600_8x8()
>>>> system.mem_ctrl.dram.range = system.mem_ranges[0]
>>>> #system.mem_ctrl.port = #system.membus.mem_side_ports
>>>> system.mem_ctrl.port = system.comm_monitor.mem_side_port
>>>> system.system_port = system.membus.cpu_side_ports
>>>> I am running SE mode using arm ISA. I have got the traces as well:
>>>> 7,r,980,4,256,0
>>>> 7,r,984,4,256,77000
>>>> 7,r,988,4,256,126000
>>>> 8,r,474576,4,10,175000
>>>> 7,r,992,4,256,238000
>>>> 7,r,996,4,256,287000
>>>> 8,w,474576,4,10,336000
>>>> 7,r,1000,4,256,357000
>>>> 8,w,474572,4,10,406000
>>>> 7,r,1004,4,256,427000
>>>> 8,r,1028,4,10,476000
>>>> 7,r,1008,4,256,525000
>>>> 8,w,474568,4,10,574000
>>>> Now my doubt is what does port number 7,8 mean. should I consider the
>>>> entire trace as a memory trace? I want only traces of the main memory.
>>>>
>>>>
>>>>
>>>>
>>>> Thanks and Regards,
>>>> Sadhana,
>>>> Research Scholar-NITK,
>>>> Dept. of Computer Science and Engineering
>>>> .
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>>>>
>>>
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[gem5-users] Re: Memory traces using CommMonitor

[Ayaz Akram via gem5-users]

Hi Sadhana,

I think the first number is the requestor port id (IIRC). The above trace
should have all requests to the main memory as your CommMonitor is
connected between the membus and MemCtrl (and all memory traffic should go
through it).

-Ayaz

On Mon, Feb 13, 2023 at 7:52 PM Sadhana . via gem5-users <
gem5-users@gem5.org> wrote:

> I am using gem5 for generation of memory traces. While going through gem5
> videos I found a method to generate traces using commMonitor. I have
> modified the code as follows:
> system.comm_monitor=CommMonitor()
> system.comm_monitor.cpu_side_port=system.membus.mem_side_ports
>
> system.comm_monitor.trace=MemTraceProbe(trace_file=f"mem_trace",trace_compress=True)
> #system.system_port = system.membus.slave
> system.mem_ctrl=MemCtrl()
> system.mem_ctrl.dram = DDR3_1600_8x8()
> system.mem_ctrl.dram.range = system.mem_ranges[0]
> #system.mem_ctrl.port = #system.membus.mem_side_ports
> system.mem_ctrl.port = system.comm_monitor.mem_side_port
> system.system_port = system.membus.cpu_side_ports
> I am running SE mode using arm ISA. I have got the traces as well:
> 7,r,980,4,256,0
> 7,r,984,4,256,77000
> 7,r,988,4,256,126000
> 8,r,474576,4,10,175000
> 7,r,992,4,256,238000
> 7,r,996,4,256,287000
> 8,w,474576,4,10,336000
> 7,r,1000,4,256,357000
> 8,w,474572,4,10,406000
> 7,r,1004,4,256,427000
> 8,r,1028,4,10,476000
> 7,r,1008,4,256,525000
> 8,w,474568,4,10,574000
> Now my doubt is what does port number 7,8 mean. should I consider the
> entire trace as a memory trace? I want only traces of the main memory.
>
>
>
>
> Thanks and Regards,
> Sadhana,
> Research Scholar-NITK,
> Dept. of Computer Science and Engineering
> .
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[gem5-users] Re: SE Mode DMA Engine

[Ayaz Akram via gem5-users]

Hi Siddharth,

There is an existing CopyEngine in gem5 (src/dev/pci/copy_engine.cc) which
might be similar (and helpful) to what you are trying to do.

-Ayaz

On Thu, Feb 2, 2023 at 2:37 AM Siddharth Sahay via gem5-users <
gem5-users@gem5.org> wrote:

> Hi!
> What would be the best strategy for creating a DMA engine for SE mode?
> Does something like this already exist? I'd like to be able to write
> something like this in the code being simulated (with dma_copy()
> implemented in a library that I'd also write)
>
> dma_copy(src_addr, target_addr, size);
>
> and have the DMA device "eventually" copy over the required data without
> the CPU doing anything else about it. It is fine for our uses for the CPU
> to poll a memory location to check for DMA completion.
>
> I was considering developing a custom dcache that would interpret a
> certain address range as controlling DMA operations, so it would flush the
> dcache and send memory requests for DMA operation when the CPU issues a
> store with the source, target, and size to pre-configured locations in the
> special address range. I don't really need it to resemble how real DMA
> devices work with OS integration, interrupts, iommu etc. However, if there
> is a guide somewhere on how to use the existing DmaDevice with FS mode,
> that would also be of great help (I wasn't able to find one).
>
> Thanks!
> Siddharth
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[gem5-users] Re: handle syscalls in FS (bare-metal) mode for RISCV

[Ayaz Akram via gem5-users]

Hi Priyanka,

If you want syscall handling you can use full-system simulation with Linux
as the OS (instead of the bare metal full system). gem5 also provides a
syscall emulation (SE) mode where you do not need to run any OS, and gem5
would emulate most of the system calls.

-Ayaz

On Wed, Feb 1, 2023 at 11:02 AM Priyanka Ankolekar via gem5-users <
gem5-users@gem5.org> wrote:

> Hello,
> I am trying to run the dhrystone benchmark (from this repo: 
> https://github.com/riscv-software-src/riscv-tests) on RISCV bare-metal mode 
> using gem5 in full-system simulation model (fs_linux.py). I have compiled the 
> dhrystone code using riscv64-unknown-elf-gcc compiler.
> When I run this, the simulation never exits because it cannot handle the 
> syscall coming from the dhrystone.riscv binary.
>
> How can I make changes to the simulator so it can handle syscalls (for 
> example, to perform a printf or std::cout)?
>
> I am new to this, so any help understanding this would be very useful.
>
> Thank you.
>
> Priyanka.
>
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[gem5-users] Re: RISC-V FS stuck at login

[Ayaz Akram via gem5-users]

Hi Joao,

I will suggest looking at the last part of the following README file to
understand how this disk image should be used (I think your simulation is
executing an m5 exit at the boot up) :

https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/develop/src/riscv-ubuntu/README.md

-Ayaz

On Wed, Feb 1, 2023 at 12:18 AM João Vieira via gem5-users <
gem5-users@gem5.org> wrote:

> Hi,
>
> I am trying to run a RISC-V FS simulation in gem5 using the provided
> kernel and image, but the system seems to get stuck at login (see below).
>
> At first, I thought there was something wrong with my simulation script,
> but then I tried to run the example
> (configs/example/gem5_library/riscv-ubuntu-run.py) and the same happens.
>
> I was expecting to have a bash shell after login.
>
> Does anyone ran into the same problem?
>
> Kind regards,
> Joao Vieira
>
> --
> Joao Vieira
> ECE PhD Student at Tecnico Lisboa | INESC-ID, Portugal
>
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[gem5-users] Re: gem5 always adds PCID to vaddr to lookup TLB

[Ayaz Akram via gem5-users]

Another thing to notice is that the current PCID change is intended for SE
mode only (as you might have seen in the comments of the JIRA issue:
https://gem5.atlassian.net/browse/GEM5-332). So, the global bit probably
would not be used anyways.

-Ayaz

On Wed, Feb 1, 2023 at 4:14 PM Ayaz Akram  wrote:

> Hi Soramichi,
>
> I agree with the change you are proposing.
>
> May I open an issue on Jira on this and assign myself?
>
>
> Yes, please do that.
>
> -Ayaz
>
> On Tue, Jan 31, 2023 at 11:07 PM Soramichi Akiyama <
> s-a...@fc.ritsumei.ac.jp> wrote:
>
>> Hi Ayaz,
>>
>> thank you for your reply and I really appreciate your effort for making
>> SMT work.
>>
>> As far as I understand, the stackoverflow entry you mentioned assumes
>> that every process uses the same PTE for the same vaddr if there is one
>> with global = 1.
>> (I am not sure if this is correct as the manual says the processor "may"
>> use it, implying that it can choose NOT to use it depending on some other
>> conditions.)
>>
>> In terms of the gem5 code, what I think should be done is:
>> 1. Copy the global bit of a PTE to the corresponding TLB entry in
>> TLB::insert.
>> 2. In TLB::translate, search the TLB with the bare vaddr (with PCID not
>> concatenated).
>> 3-A. If the found TLB entry's global bit is 1, use it even if CR4.pcide
>> is 1.
>> 3-B. If the found TLB entry's global bit is 0 and CR4.pcide is 1, compare
>> the PCID associated with the found TLB entry with the current process to
>> decide whether it should be used.
>>
>> May I open an issue on Jira on this and assign myself? I think I have a
>> somewhat clear plan on how the code should be changed, but the contributing
>> guide says it is better to ask a developer for advise.
>>
>> Best regards,
>>
>> Soramichi
>>
>>
>> On 2023/01/31 4:39, Ayaz Akram wrote:
>> > Hi Soramichi,
>> >
>> > We recently added the concatenation change to distinguish TLB entries of
>> > different processes to make SMT work. You can check more details here:
>> >
>> > https://gem5.atlassian.net/browse/GEM5-332
>> >
>> > I am not sure what the behavior should be for global pages.  From some
>> > discussion here:
>> >
>> https://stackoverflow.com/questions/41986862/x86-64-page-table-global-bit
>> ,
>> > it seems we should have the option to flag a TLB entry as a global
>> entry.
>> >
>> > -Ayaz
>> >
>> > On Sat, Jan 28, 2023 at 1:04 AM Soramichi Akiyama via gem5-users <
>> > gem5-users@gem5.org> wrote:
>> >
>> >> Hello,
>> >>
>> >> I am trying something related to the global bit of a TLB entry and
>> found
>> >> that the gem5 code might have inconsistency with the Intel manual.
>> >>
>> >> The Intel manual says that
>> >> "a logical processor may use a global TLB entry to translate a linear
>> >> address,
>> >> even if the TLB entry is associated with a PCID different from the
>> current
>> >> PCID".
>> >>
>> >> However in TLB::translate(), gem5 concatenates the PCID to the vaddr
>> when
>> >> CR4.pcide
>> >> is true and lookup the trie containing the TLB entries using [vaddr +
>> PCID]
>> >> without considering the global bits of the entries.
>> >>
>> >> Is the gem5 behavior a bug, or is it a subset of allowed behaviors?
>> >> I guess it depends on what the word "may" in the manual means, but not
>> >> quite sure.
>> >>
>> >> Best regards,
>> >>
>> >> Soramichi Akiyama
>> >> ___
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>> >> To unsubscribe send an email to gem5-users-le...@gem5.org
>> >>
>> >
>>
>
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[gem5-users] Re: gem5 always adds PCID to vaddr to lookup TLB

[Ayaz Akram via gem5-users]

Hi Soramichi,

I agree with the change you are proposing.

May I open an issue on Jira on this and assign myself?


Yes, please do that.

-Ayaz

On Tue, Jan 31, 2023 at 11:07 PM Soramichi Akiyama 
wrote:

> Hi Ayaz,
>
> thank you for your reply and I really appreciate your effort for making
> SMT work.
>
> As far as I understand, the stackoverflow entry you mentioned assumes that
> every process uses the same PTE for the same vaddr if there is one with
> global = 1.
> (I am not sure if this is correct as the manual says the processor "may"
> use it, implying that it can choose NOT to use it depending on some other
> conditions.)
>
> In terms of the gem5 code, what I think should be done is:
> 1. Copy the global bit of a PTE to the corresponding TLB entry in
> TLB::insert.
> 2. In TLB::translate, search the TLB with the bare vaddr (with PCID not
> concatenated).
> 3-A. If the found TLB entry's global bit is 1, use it even if CR4.pcide is
> 1.
> 3-B. If the found TLB entry's global bit is 0 and CR4.pcide is 1, compare
> the PCID associated with the found TLB entry with the current process to
> decide whether it should be used.
>
> May I open an issue on Jira on this and assign myself? I think I have a
> somewhat clear plan on how the code should be changed, but the contributing
> guide says it is better to ask a developer for advise.
>
> Best regards,
>
> Soramichi
>
>
> On 2023/01/31 4:39, Ayaz Akram wrote:
> > Hi Soramichi,
> >
> > We recently added the concatenation change to distinguish TLB entries of
> > different processes to make SMT work. You can check more details here:
> >
> > https://gem5.atlassian.net/browse/GEM5-332
> >
> > I am not sure what the behavior should be for global pages.  From some
> > discussion here:
> >
> https://stackoverflow.com/questions/41986862/x86-64-page-table-global-bit,
> > it seems we should have the option to flag a TLB entry as a global entry.
> >
> > -Ayaz
> >
> > On Sat, Jan 28, 2023 at 1:04 AM Soramichi Akiyama via gem5-users <
> > gem5-users@gem5.org> wrote:
> >
> >> Hello,
> >>
> >> I am trying something related to the global bit of a TLB entry and found
> >> that the gem5 code might have inconsistency with the Intel manual.
> >>
> >> The Intel manual says that
> >> "a logical processor may use a global TLB entry to translate a linear
> >> address,
> >> even if the TLB entry is associated with a PCID different from the
> current
> >> PCID".
> >>
> >> However in TLB::translate(), gem5 concatenates the PCID to the vaddr
> when
> >> CR4.pcide
> >> is true and lookup the trie containing the TLB entries using [vaddr +
> PCID]
> >> without considering the global bits of the entries.
> >>
> >> Is the gem5 behavior a bug, or is it a subset of allowed behaviors?
> >> I guess it depends on what the word "may" in the manual means, but not
> >> quite sure.
> >>
> >> Best regards,
> >>
> >> Soramichi Akiyama
> >> ___
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> >> To unsubscribe send an email to gem5-users-le...@gem5.org
> >>
> >
>
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[gem5-users] Re: Interactive simulation with statistics per executable

[Ayaz Akram via gem5-users]

Hi Sebastian,

I use [2] as starting point but I can’t change workloads in the python
> script and rerun the simulation because this would simulate another system
> instead of simulating another executable in the same system.


Going to python script should not simulate another system, rather once you
go back to the simulation loop your simulation will resume from the point
where it stopped.

One way of what you are trying to achieve is to execute m5 utility (with
the exit input for example, more on m5:
https://www.gem5.org/documentation/general_docs/m5ops/) in the guest
whenever one benchmark has finished. This will take stop the simulation and
take the control to the python script where you can dump the stats
(m5.stats.dump()), and then resume the simulation to execute the next
benchmark. I will suggest taking a look at the following example script:

https://github.com/gem5/gem5/blob/stable/configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py

-Ayaz







On Mon, Jan 30, 2023 at 12:46 AM Sebastian Weber via gem5-users <
gem5-users@gem5.org> wrote:

> Hello,
>
>
>
> I am trying to use the current version of gem5 in full system mode
> interactively (--interactive) to be able to dump or reset statistics
> while connecting to the simulated console with m5term [1] (--listener-mode)
> to trigger the execution of executables. The goal is using gem5 in a
> co-simulation and being able to execute (multiple) binaries at arbitrary
> points in time during the simulation and getting binary-specific statistics
> after their execution. I use [2] as starting point but I can’t change
> workloads in the python script and rerun the simulation because this would
> simulate another system instead of simulating another executable in the
> same system. At the moment I am not able to trigger the execution of
> binaries with m5term and getting the statistics with the interactive mode,
> instead I always get empty statistics. My question is whether this setup of
> gem5 and m5term is able to generate statistics and if so, how to get them?
>
>
>
> Best regards,
>
> Sebastian Weber
>
>
>
> [1] https://www.gem5.org/documentation/general_docs/fullsystem/m5term
>
> [2]
> https://github.com/gem5/gem5/blob/stable/configs/example/gem5_library/x86-ubuntu-run-with-kvm.py
>
>
>
>
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[gem5-users] Re: gem5 always adds PCID to vaddr to lookup TLB

[Ayaz Akram via gem5-users]

Hi Soramichi,

We recently added the concatenation change to distinguish TLB entries of
different processes to make SMT work. You can check more details here:

https://gem5.atlassian.net/browse/GEM5-332

I am not sure what the behavior should be for global pages.  From some
discussion here:
https://stackoverflow.com/questions/41986862/x86-64-page-table-global-bit,
it seems we should have the option to flag a TLB entry as a global entry.

-Ayaz

On Sat, Jan 28, 2023 at 1:04 AM Soramichi Akiyama via gem5-users <
gem5-users@gem5.org> wrote:

> Hello,
>
> I am trying something related to the global bit of a TLB entry and found
> that the gem5 code might have inconsistency with the Intel manual.
>
> The Intel manual says that
> "a logical processor may use a global TLB entry to translate a linear
> address,
> even if the TLB entry is associated with a PCID different from the current
> PCID".
>
> However in TLB::translate(), gem5 concatenates the PCID to the vaddr when
> CR4.pcide
> is true and lookup the trie containing the TLB entries using [vaddr + PCID]
> without considering the global bits of the entries.
>
> Is the gem5 behavior a bug, or is it a subset of allowed behaviors?
> I guess it depends on what the word "may" in the manual means, but not
> quite sure.
>
> Best regards,
>
> Soramichi Akiyama
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[gem5-users] Re: cache line data based on memory accesses

[Ayaz Akram via gem5-users]

[Copying my response from gem5 slack in case you don't see there]

Hi Ghadeer,

I think you should be able to dump packet data with your changes in
abstract_mem.cc. access() function eventually calls getData() and
writeData() of packet.hh which use getSize() which gives the size of the
packet. Normally, the packet size here is same as the cache line size.
mem_ctrl.cc maintains two types of packets: 1) packet : which is same as
outer world packet and is a single cache line size, and 2) mem_pkt: which
is memory interface specific and can be smaller in size compared to a cache
line. Whenever mem_ctrl.cc calls access() function of abstract_mem.cc it
passes the the first type of packet (same as cache line size).

The packets that are added to read/write queue are mem_pkts and can be
smaller than 64B (cache line size). The size of mem_pkt depends on the
burst length (atom size) of the memory interface that is used. For example
for DDR4, mem_pkt size will be 64B as well.

-Ayaz



On Thu, Jan 26, 2023 at 11:55 PM Ghadeer Almusaddar via gem5-users <
gem5-users@gem5.org> wrote:

> Hello All,
>
> Is there any direct way in gem5 by which I can get the data of the whole
> cache line for every memory read or write regardless of how many bytes are
> read or written from that cache line? I also want to dump cache line data
> due to memory accesses from a specific core (requestorId)?
>
> Thank you,
> Ghadeer
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[gem5-users] Re: RISCV fs mode - code won't stop running

[Ayaz Akram via gem5-users]

Hi Priyanka,

I am assuming you don't see any new instructions in the "trace.out" after a
specific time. My understanding is that since this program is run
in full system mode (bare metal), even when the program finishes the
simulation loop still keeps executing (simulating the bare metal system).
One possible option, I think, is to add an m5 instruction (
https://www.gem5.org/documentation/general_docs/m5ops/) at the end of your
program which will move the control from C++ simulation loop to the python
run script where you can terminate the simulation yourself. Another option
is to set the maximum time the simulation should run for by passing a tick
value to the m5.simulate() call.

-Ayaz

On Thu, Jan 26, 2023 at 1:17 PM Priyanka Ankolekar via gem5-users <
gem5-users@gem5.org> wrote:

> Hello,
> I am new to gem5.
> I am trying to run Dhrystone on gem5 RISCV using the fs_linux.py file in
> the gem5 repo.
>
> configs/example/riscv/fs_linux.py
>
> Here is the command I am using:
>
> ./build/RISCV/gem5.opt --debug-start=0 --debug-flags=Exec
> --debug-file=trace.out ./configs/example/riscv/fs_linux.py --bare-metal
> --kernel ../riscv-tests/benchmarks/dhrystone.riscv
>
>
> The issue is that it won't stop running. Do I have to add an ExitEvent or
> some exit criteria? How should I do that?
>
> Thanks for your help.
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[gem5-users] Re: Accessing CPU cycles in Ruby components

[Ayaz Akram via gem5-users]

Hi Ziyao,

Based on my understanding, I guess for the Ruby stats that are not in
Ticks, you can rely on the Ruby ClockDomain value from the configuration to
convert the cycles to CPU cycles or ticks.

-Ayaz

On Tue, Jan 24, 2023 at 12:48 AM Ziyao Yan via gem5-users <
gem5-users@gem5.org> wrote:

> Hi all,
>
> I am currently trying to gather cycle information of events and wondering
> how I should access CPU cycles in the Ruby port component. It seems like,
> although tick is used universally across the simulation, Ruby has its own
> cycle setting that is different from the CPU cycle.
>
> Thanks,
> Ziyao
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[gem5-users] Re: Simulation error for hello world workload

[Ayaz Akram via gem5-users]

Hi Ikram,

It seems like your program is using a system call (#398) which has not been
tested or implemented in gem5. This can be because of a newer version of
the c library or compiler. One option is to ignore this system call and see
if your program still works. As a reference you can look at how the other
system call in your program is ignored (set_robust_list) in the gem5 source
code here: "src/arch/arm/linux/se_workload.cc".

-Ayaz

On Tue, Jan 24, 2023 at 10:12 AM IKRAM via gem5-users 
wrote:

> Hi Team,
>
> I have written a c code (hello world program) and compiled using the arm
> cross compiler. When I run the simple.py config file with new helloworld
> binary updated in simple.py file I am getting simulation failure.
>
> c code is as shown below:
>
>
>
>
>
> *#include int main(int argc, char* argv[]) {   // printf()
> displays the string inside quotation   printf("Hello, World!");   return
> 0;}*
>
>
> ARM cross compiler used : *aarch64-linux-gnu-gcc*
>
> Below are the commands I used:
>
> *aarch64-linux-gnu-gcc -static -static-libgcc -static-libstdc++ myhello.c
> -o myhellobuild/ARM/gem5.opt configs/learning_gem5/part1/simple.py*
>
> Below is the error:
> gem5 Simulator System.  http://gem5.org
> gem5 is copyrighted software; use the --copyright option for details.
>
> gem5 version 21.2.0.0
> gem5 compiled Jan 24 2023 23:16:23
> gem5 started Jan 24 2023 23:21:13
> gem5 executing on ubuntu-linux-22-04-desktop, pid 156963
> command line: build/ARM/gem5.opt configs/learning_gem5/part1/simple.py
>
> Global frequency set at 1 ticks per second
> warn: failed to generate dot output from m5out/config.dot
> build/ARM/mem/mem_interface.cc:791: warn: DRAM device capacity (8192
> Mbytes) does not match the address range assigned (512 Mbytes)
> 0: system.remote_gdb: listening for remote gdb on port 7000
> Beginning simulation!
> build/ARM/sim/simulate.cc:194: info: Entering event queue @ 0.  Starting
> simulation...
> build/ARM/sim/syscall_emul.cc:74: warn: ignoring syscall
> set_robust_list(...)
> build/ARM/sim/syscall_desc.hh:209: fatal: Syscall 398 out of range
> Memory Usage: 649816 KBytes
>
>
> If anyone knows how to solve the cross compiler issue, please give a reply.
>
> Thanks
> - Ikram
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[gem5-users] Re: Limit FS memory through kernel args

[Ayaz Akram via gem5-users]

Hi Joao,

If you look at the source code here (in case you haven't previously):
src/python/gem5/components/boards/kernel_disk_workload.py, I think the
expectation is that the user-provided kernel arguments will replace the
default ones. However, I agree that it might be useful to have the ability
to append new arguments to the default ones.

-Ayaz

On Tue, Jan 24, 2023 at 7:36 AM João Vieira via gem5-users <
gem5-users@gem5.org> wrote:

> Hi again,
>
> I found the issue.
>
> When we add arguments to the kernel, the default arguments that are
> required for the FS to work properly are erased from the kernel_command!
>
> The default kernel_command is "earlyprintk=ttyS0 console=ttyS0
> lpj=723 root=/dev/hda". But if kernel_args != [] in
> set_kernel_disk_workload, the only arguments added are the ones
> specified in that list!
>
> Is this a feature or a bug? I was expecting the optional kernel
> arguments to be ADDED to the default arguments, and not replace them...
>
> Kind regards,
> Joao Vieira
>
> On 24/01/23 12:10, João Vieira via gem5-users wrote:
> > Hi,
> >
> > I am trying to limit the memory used by Linux so that I am left with
> > some physically addressable memory to use with accelerators in FS mode.
> >
> > In physical systems, to do this, it suffices to boot the kernel with
> > the argument "mem=MAX_MEM", where MAX_MEM represents the maximum
> > memory that Linux can access and also the corresponding upper address.
> >
> > However, when I add that kernel argument, the system just does not
> > boot (I get no output in the m5 terminal). If I remove that argument,
> > everything works fine. I am using the gem5 standard library and my
> > code is as follows:
> >
> > 
> >
> > requires(
> > isa_required=ISA.X86,
> > coherence_protocol_required=CoherenceProtocol.MESI_TWO_LEVEL,
> > )
> >
> > memory = SingleChannelDDR3_1600(size="3GB")
> > processor = SimpleProcessor(cpu_type=CPUTypes.TIMING, num_cores=1)
> > cache_hierarchy = MESITwoLevelCacheHierarchy(
> > l1d_size="32kB",
> > l1d_assoc=8,
> > l1i_size="32kB",
> > l1i_assoc=8,
> > l2_size="1MB",
> > l2_assoc=16,
> > num_l2_banks=1,
> > )
> >
> > board = X86Board(
> > clk_freq="3GHz",
> > processor=processor,
> > memory=memory,
> > cache_hierarchy=cache_hierarchy,
> > )
> >
> > board.set_kernel_disk_workload(
> > kernel=CustomResource("fs_x86/binaries/vmlinux"),
> > kernel_args=["mem=2G"],
> > disk_image=CustomDiskImageResource("fs_x86/disks/gem5_base.img"),
> > )
> >
> > simulator = Simulator(board=board)
> > simulator.run()
> >
> > 
> >
> > Does anyone have a clue of what the problem is or is there any other
> > logs that I can look at to understand where the boot process halts?
> >
> > Thanks in advance!
> >
> > Kind regards,
> > Joao Vieira
> >
> --
> Joao Vieira
> ECE PhD Student at Tecnico Lisboa | INESC-ID, Portugal
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[gem5-users] Re: Running gem5 RISCV in bare-metal mode

[Ayaz Akram via gem5-users]

Hi Priyanka,

I think adding something like the following line in your script should
solve the problem you are running into:

system.platform.pci_host.pio = system.iobus.mem_side_ports

-Ayaz

On Tue, Jan 24, 2023 at 6:48 AM Priyanka Ankolekar via gem5-users <
gem5-users@gem5.org> wrote:

> Hello,
>
> I am trying to run RISCV in bare-metal mode using the fs_linux.py script.
> Here is the command I am using:
>
> /build/RISCV/gem5.opt --debug-start=0 --debug-flags=Exec
> --debug-file=trace.out ./configs/example/riscv/fs_linux.py --bare-metal
> --kernel ../riscv-tests/benchmarks/dhrystone.riscv
>
> I get this error message which seems to suggest that the pci_host needs is
> not tied off correctly. I am running this script as is from the repo.
>
>
> warn: The `get_runtime_isa` function is deprecated. Please migrate away
> from using this function.
>
> Global frequency set at 1 ticks per second
>
> warn: No dot file generated. Please install pydot to generate the dot file
> and pdf.
>
> build/RISCV/mem/dram_interface.cc:690: warn: DRAM device capacity (8192
> Mbytes) does not match the address range assigned (512 Mbytes)
>
> system.platform.terminal: Listening for connections on port 3456
>
> 0: system.remote_gdb: listening for remote gdb on port 7000
>
> build/RISCV/dev/io_device.cc:62: panic: Pio port of
> system.platform.pci_host not connected to anything!
>
> Memory Usage: 621368 KBytes
>
> Program aborted at tick 0
>
> --- BEGIN LIBC BACKTRACE ---
>
> ./build/RISCV/gem5.opt(+0x736170)[0x55f0810bd170]
>
> ./build/RISCV/gem5.opt(+0x75ba7c)[0x55f0810e2a7c]
>
> /lib/x86_64-linux-gnu/libc.so.6(+0x42520)[0x7f8a37b2e520]
>
> /lib/x86_64-linux-gnu/libc.so.6(pthread_kill+0x12c)[0x7f8a37b82a7c]
>
> /lib/x86_64-linux-gnu/libc.so.6(raise+0x16)[0x7f8a37b2e476]
>
> /lib/x86_64-linux-gnu/libc.so.6(abort+0xd3)[0x7f8a37b147f3]
>
> ./build/RISCV/gem5.opt(+0x463d55)[0x55f080dead55]
>
> ./build/RISCV/gem5.opt(+0x12cec1e)[0x55f081c55c1e]
>
> ./build/RISCV/gem5.opt(+0x63ddc3)[0x55f080fc4dc3]
>
> ./build/RISCV/gem5.opt(+0x5412a2)[0x55f080ec82a2]
>
> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(+0x12b6d3)[0x7f8a386526d3]
>
>
> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(_PyObject_MakeTpCall+0x8c)[0x7f8a3860d1ac]
>
> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(+0xe765a)[0x7f8a3860e65a]
>
>
> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(_PyEval_EvalFrameDefault+0x9d78)[0x7f8a385a29b8]
>
> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(+0x1c681f)[0x7f8a386ed81f]
>
>
> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(_PyEval_EvalFrameDefault+0x9d78)[0x7f8a385a29b8]
>
> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(+0x1c681f)[0x7f8a386ed81f]
>
>
> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(_PyEval_EvalFrameDefault+0x9d78)[0x7f8a385a29b8]
>
> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(+0x1c681f)[0x7f8a386ed81f]
>
>
> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(PyEval_EvalCode+0xbe)[0x7f8a386e894e]
>
> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(+0x1c1edd)[0x7f8a386e8edd]
>
> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(+0x12eb13)[0x7f8a38655b13]
>
>
> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(_PyEval_EvalFrameDefault+0x69ee)[0x7f8a3859f62e]
>
> /lib/x86_64-linux-gnu/libpython3.10.so.1.0(+0x1c681f)[0x7f8a386ed81f]
>
> ./build/RISCV/gem5.opt(+0x6365f7)[0x55f080fbd5f7]
>
> ./build/RISCV/gem5.opt(+0x39b858)[0x55f080d22858]
>
> /lib/x86_64-linux-gnu/libc.so.6(+0x29d90)[0x7f8a37b15d90]
>
> /lib/x86_64-linux-gnu/libc.so.6(__libc_start_main+0x80)[0x7f8a37b15e40]
>
> ./build/RISCV/gem5.opt(+0x45d3a5)[0x55f080de43a5]
>
> --- END LIBC BACKTRACE ---
>
> Aborted (core dumped)
>
> The dhrystone.riscv file is of this type:
>
> ../riscv-tests/benchmarks/dhrystone.riscv: ELF 64-bit LSB executable, UCB
> RISC-V, RVC, double-float ABI, version 1 (SYSV), statically linked, not
> stripped
>
> Am I running this correctly? What am I missing here?
>
> Thank you for your help.
>
> Priyanka.
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[gem5-users] Re: Set number of register file read and write ports

[Ayaz Akram via gem5-users]

Hi,

Based on my understanding of O3CPU, I think your assumption is correct.
However, probably parameters like issueWidth and wbWidth can be used to
control maximum register read/writes indirectly.

-Ayaz

On Tue, Jan 17, 2023 at 3:32 AM pedro--- via gem5-users 
wrote:

> Hi,
>
> I'm trying to check the influence of the number of read and write register
> file ports on the maximum IPC achieved by the OoO model. However, I could
> not find any parameter that models the number of register file ports. Is
> there any?
>
> For example, in none of the methods chain: readIntRegOperand (dyn_inst.hh)
> -> readIntReg (cpu.hh) -> readIntReg (regfile.hh) the number of ports is
> verified.
>
> Could anyone confirm if gem5 OoO model assumes there will always be enough
> ports to feed all functional units?
>
> Thank you.
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[gem5-users] Re: Running OpenMP version of SPEC CPU speed 2017 benchmarks

[Ayaz Akram via gem5-users]

Hi Vipin,

I guess that you will have to create a new disk image by changing the
benchmark build and run scripts from
https://gem5.googlesource.com/public/gem5-resources/+/refs/tags/v20.1.0.5/src/spec-2017/disk-image/spec-2017/
 (install-spec2017.sh and runscript.sh). You will have to add openmp
related flags in the relevant runcpu commands in the previous two files.
The gem5 run scripts probably would not require many changes assuming that
they already have the support to run multiple CPUs.

-Ayaz

On Tue, Jan 10, 2023 at 10:43 PM VIPIN PATEL via gem5-users <
gem5-users@gem5.org> wrote:

> Hi All,
>
> SPEC CPU 2017 benchmarks now support OpenMP parallelization (
> https://www.spec.org/cpu2017/Docs/overview.html#Q14).
> I plan to include the SPEC CPU 2017 parallel benchmarks in my study.
> The gem5-resources for version 20 provide scripts for single-core
> execution.
> Does anyone know what needs to be changed so that the parallel version of
> benchmarks can be run?
>
>
> Regards,
> Vipin
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[gem5-users] Re: PerfKvmCounter::attach failed (2)

[Ayaz Akram via gem5-users]

Hi Atlas,

I think the host machine means the bare metal host. I have not personally
run KVM CPU of gem5 on a VM, but you might find this post on the mailing
list relevant:

https://www.mail-archive.com/gem5-users@gem5.org/msg20996.html

-Ayaz

On Tue, Jan 10, 2023 at 11:16 AM Atlas Kaan Yilmaz via gem5-users <
gem5-users@gem5.org> wrote:

> Hi Everyone,
>
> I’ve been trying to use KvmCPU in gem5 simulation; however, when I try to
> run I get the output below with PerfKvmCounter::attach failed (2) error.
>
> I’m running gem5 on an Azure VM with Ubuntu 20.04. I’m trying to run the
> vSwarm-u suite for serverless architecture.
>
> I have found a proposed fix on a previous thread that said to 'echo -1 >
> /proc/sys/kernel/perf_event_paranoid’ on the host machine. I have done this
> (assuming the host machine means the VM I’m running gem5 on or does it mean
> the bare metal host?) but there has been no changes to the output message.
>
> Any help or ideas about how to go about this would be greatly appreciated!
>
> Thanks,
> Atlas
>
> Create CPU:  X86KvmCPU
> Created CPU: 2x X86KvmCPU, Mem mode: atomic_noncaching
> --- Setup Mode ---
> Global frequency set at 1 ticks per second
> warn: system.workload.acpi_description_table_pointer.rsdt adopting orphan
> SimObject param 'entries'
> warn: failed to generate dot output from results/fibonacci-go/config.dot
> build/X86/sim/kernel_workload.cc:46: info: kernel located at: kernel
>   0: system.pc.south_bridge.cmos.rtc: Real-time clock set to Sun Jan
> 1 00:00:00 2012
> system.pc.com_1.device: Listening for connections on port 3456
> 0: system.remote_gdb: listening for remote gdb on port 7000
> build/X86/mem/coherent_xbar.cc:140: warn: CoherentXBar system.llc_bus has
> no snooping ports attached!
> build/X86/dev/intel_8254_timer.cc:128: warn: Reading current count from
> inactive timer.
> Start simulation...
> build/X86/cpu/kvm/base.cc:150: info: KVM: Coalesced MMIO disabled by
> config.
> build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x:
> unimplemented function 2
> build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x:
> unimplemented function 3
> build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x:
> unimplemented function 4
> build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x:
> unimplemented function 5
> build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x:
> unimplemented function 6
> build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x:
> unimplemented function 8
> build/X86/cpu/kvm/base.cc:150: info: KVM: Coalesced MMIO disabled by
> config.
> build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x:
> unimplemented function 2
> build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x:
> unimplemented function 3
> build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x:
> unimplemented function 4
> build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x:
> unimplemented function 5
> build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x:
> unimplemented function 6
> build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x:
> unimplemented function 8
> build/X86/sim/simulate.cc:194: info: Entering event queue @ 0.  Starting
> simulation...
> build/X86/cpu/kvm/perfevent.cc:183: panic: PerfKvmCounter::attach failed
> (2)
> Memory Usage: 2390716 KBytes
> build/X86/cpu/kvm/perfevent.cc:183: panic: PerfKvmCounter::attach failed
> (2)
> Memory Usage: 2390716 KBytes
> Program aborted at tick 0
>
>
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[gem5-users] Re: Is there actual data in the DRAM?

[Ayaz Akram via gem5-users]

Hi Daniel,

The memory interfaces inherit from AbstractMemory, which is where the
actual data is stored. I will suggest looking at src/mem/abstract_mem.cc to
get a better understanding of this.

-Ayaz

On Mon, Dec 26, 2022 at 5:42 AM 李信德 via gem5-users 
wrote:

> Hi everyone,
>
> I would like to load the data in the DRAM at the beginning of the
> simulation, but it seems like there is no actual data stored in the DRAM.
> It only evaluates the performance and power consumption. The code I look at
> is src/mem/DRAMInterface.cc. Is my understanding correct?
>
> Besides, is there any DRAM module that actually stores the data? (so that
> I can write data into or read data from the DRAM)
>
> Thank you for reading this email.
>
> Sincerely,
> Daniel
>
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[gem5-users] Re: Not able to access webpage to run_npb.py

[Ayaz Akram via gem5-users]

Hi David,

Please find my response to your questions below:



>
>1. It seems like I don’t need to do the “Setting up the environment”
>since I don’t plan to create or modify npb-tests.
>
> I thought the npb tests are already on the disk image from “Creating a
> disk image” section.
> Please confirm.
> If the npb-tests are necessary please explain “your-remote-add”.  Is this
> on my host machine and needs to be accessible as a webpage on my local hard
> disk?
> git remote add origin https://your-remote-add/npb-tests.git


The tutorial you have referenced provides instructions to run NPB with
gem5art. Since, gem5art tries to create a reproducible test environment
where every change can be tracked (more details on gem5art can be found
here: https://arch.cs.ucdavis.edu/simulation/2021/03/28/gem5art.html),
"Setting up the environment" section of the tutorial provides
the instructions to set up the base environment. Basically, we create  a
github repo to treat it as the primary directory from where all the tests
would be run. gem5art uses the metadata of this github repo to track any
changes to it. The "your-remote-add" is meant to be a user-defined remote
where they might keep this github repo.




>
>1. To run one test I just use at gem5 directory
>
> `./build/X86/gem5.opt configs/example/gem5_library/x86-npb-benchmarks.py
> --benchmark ep --size A`
>
>
>1. To run a suite of NPB benchmark tests I can create the
>launch_npb_tests.py
>
> This file seems to rebuild everything from scratch and run a regression
> As a first order I prefer to not get so sophisticated until I get a few
> simple tests to run.


> Could I run in sequential order something like below
> `./build/X86/gem5.opt configs/example/gem5_library/x86-npb-benchmarks.py
> --benchmark ep --size A`
> `./build/X86/gem5.opt configs/example/gem5_library/x86-npb-benchmarks.py
> --benchmark bt --size A`
> `./build/X86/gem5.opt configs/example/gem5_library/x86-npb-benchmarks.py
> --benchmark cg --size A`
> `./build/X86/gem5.opt configs/example/gem5_library/x86-npb-benchmarks.py
> --benchmark ft --size A`


You should be able to run the single tests using the above commands.
`launch_npb_tests.py`
runs a suite of tests using gem5art, by registering/documenting different
artifacts that will be used to run this suite of tests.



>
>1. Extract NPB performance data
>
> I’m not familiar with celery and but familiar with python.
> Do I need to install celery on host system ?
> Which directory and how to extract the NPB run data which is on the
> virtual machine over to the host machine ?
> What kind of statistics are output : runtime of test , latencies of
> certain paths ?


You do not need celery to run your jobs with gem5art. Please look at the
reference to 'python multiprocessing library' on this page:
https://www.gem5.org/documentation/gem5art/main/faq.
The results of your tests will be stored both on your file system, and the
gem5art database. The result files include normal gem5 results files like
stats.txt (which has the performance statistics about your simulation run)
and some other gem5art related files like info.json (which will contain
some high level information about your gem5 run).

Hope this helps!
Thanks,
-Ayaz


On Fri, Feb 18, 2022 at 11:40 AM David Fong via gem5-users <
gem5-users@gem5.org> wrote:

> Hi Bobby,
>
>
>
> Thanks for your recommendations.
>
>
>
> We will stick to X86 to test the flow for NPB tests and adjust to ARM when
> needed.
>
>
>
> But I have a few questions about the flow.
>
>
>
> From just a user perspective and NOT a developer and following this
> webpage instructions:
>
>
>
> https://www.gem5.org/documentation/gem5art/tutorials/npb-tutorial
>
>
>
>1. It seems like I don’t need to do the “Setting up the environment”
>since I don’t plan to create or modify npb-tests.
>
> I thought the npb tests are already on the disk image from “Creating a
> disk image” section.
>
> Please confirm.
>
> If the npb-tests are necessary please explain “your-remote-add”.  Is this
> on my host machine and needs to be accessible as a webpage on my local hard
> disk?
>
> git remote add origin https://your-remote-add/npb-tests.git
>
>
>
>1. To run one test I just use at gem5 directory
>
> `./build/X86/gem5.opt configs/example/gem5_library/x86-npb-benchmarks.py
> --benchmark ep --size A`
>
>
>
>1. To run a suite of NPB benchmark tests I can create the
>launch_npb_tests.py
>
> This file seems to rebuild everything from scratch and run a regression
>
> As a first order I prefer to not get so sophisticated until I get a few
> simple tests to run.
>
>
>
> Could I run in sequential order something like below
>
> `./build/X86/gem5.opt configs/example/gem5_library/x86-npb-benchmarks.py
> --benchmark ep --size A`
>
> `./build/X86/gem5.opt configs/example/gem5_library/x86-npb-benchmarks.py
> --benchmark bt --size A`
>
> `./build/X86/gem5.opt configs/example/gem5_library/x86-npb-benchmarks.py
> --benchmark cg 

[gem5-users] Re: Implicit Register Dependencies in x86

[Ayaz Akram via gem5-users]

Hi Mohit,

I wonder if the number of Physical register file entries is becoming a
bottleneck in the configuration you are using? Normally, I would expect
that 'ProdLo' and 'ProdHi' registers will be renamed to some physical
register and should not cause any dependency between two independent
multiply operations.

-Ayaz

On Tue, Jul 20, 2021 at 5:27 PM Mohit Gambhir via gem5-users <
gem5-users@gem5.org> wrote:

> Hi all,
>
>
>
> I am running a DerivO3CPU basesd SE mode simulation with x86 ISA. The
> micro benchmark that I am running contains a loop with independent multiply
> instructions. An excerpt from the disassembly of the benchmark loop looks
> something like this
>
>
>
>   400c07: 48 0f af d2 imul   %rdx,%rdx
>
>   400c0b: 48 0f af db imul   %rbx,%rbx
>
> …
>
>
>
> When I look at the O3PipeView, I see that all the independent multiply
> instructions are issued sequentially, even though there are 2 multiply
> functional units and each of them is pipelined
>
>
>
> [fdn.pi..c.r.]-(
> 16664000.0) 0x00400c07.0 IMUL_R_R  [ 34983]
>
> [fdn.p...ic.r]-(
> 16664000.0) 0x00400c07.1 IMUL_R_R  [ 34984]
>
> [fdn.p...ic.r]-(
> 16664000.0) 0x00400c07.2 IMUL_R_R  [ 34985]
>
> [fdn.p...i..c.r..]-(
> 16664000.0) 0x00400c0b.0 IMUL_R_R  [ 34986]
>
> [fdn.p..ic.r.]-(
> 16664000.0) 0x00400c0b.1 IMUL_R_R  [ 34987]
>
> [fdn.p..ic.r.]-(
> 16664000.0) 0x00400c0b.2 IMUL_R_R  [ 34988]
>
> …
>
>
>
> Digging into it further I found that each of the IMUL_R_R instructions
> have Implicit Register 0 and 1 (ProdHi and ProdLow) added as a source and
> destination in the generated code. Following is the excerpt from
>  decoder-ns-cc.inc.
>
>
>
> Mul1sFlags::Mul1sFlags(…)
>
> {
>
>
>
> …
>
> ….
>
>setSrcRegIdx(_numSrcRegs++, RegId(IntRegClass,
> INTREG_FOLDED(src1, foldOBit)));
>
>setSrcRegIdx(_numSrcRegs++, RegId(IntRegClass,
> INTREG_FOLDED(src2, foldOBit)));
>
>setSrcRegIdx(_numSrcRegs++, RegId(IntRegClass,
> INTREG_IMPLICIT(0)));
>
>setDestRegIdx(_numDestRegs++, RegId(IntRegClass,
> INTREG_IMPLICIT(0)));
>
>_numIntDestRegs++;
>
>setSrcRegIdx(_numSrcRegs++, RegId(IntRegClass,
> INTREG_IMPLICIT(1)));
>
>setDestRegIdx(_numDestRegs++, RegId(IntRegClass,
> INTREG_IMPLICIT(1)));
>
>
>
> …
>
> }
>
>
>
> This results in all the independent multiply instructions to execute
> sequentially and multiply throughput is 1/3.
>
> If we have multiple functional units, then should these implicit registers
> (ProdHi and ProdLo) be replicated for each of them, and if so, why add them
> as source and destination at all?
>
> Any clarifications or workaround for this?
>
>
>
> Thanks,
>
> Mohit
>
>
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[gem5-users] Re: Fwd: Making an address range uncacheable RISCV FS.

[Ayaz Akram via gem5-users]

Hi Deepak,

I guess, if you care about more accurate implementation you might have to
add new instruction in the ISA or maybe adding a new gem5 pseudo
instruction will be easier.
Also, according to my understanding, you might be able to use the cache
invalidation/flushing related functionality in gem5 that exists there to
implement similar instructions of other ISAs. For example, for reference,
you can search for flush/invalidate in these files:

https://gem5.googlesource.com/public/gem5/+/refs/heads/develop/src/mem/cache/cache.cc
https://gem5.googlesource.com/public/gem5/+/refs/heads/develop/src/mem/cache/cache_blk.hh

Specially, you might be able to use the invalidate function from cache
block to invalidate (or effectively flush) a cache line (depending on what
details you care about).

-Ayaz


On Wed, Jun 16, 2021 at 5:19 AM Deepak Mohan via gem5-users <
gem5-users@gem5.org> wrote:

> -- Forwarded message -
> From: Deepak Mohan 
> Date: Wed, Jun 16, 2021 at 5:16 PM
> Subject: Re: [gem5-users] Making an address range uncacheable RISCV FS.
> To: Ayaz Akram 
>
>
> Hi Ayaz,
> Thank you, it looks great, I was working with a previous version of
> gem5. I would like to know one more thing, is there any way to flush a
> cache line in gem5 RISCV, from my initial research I found that RISCV
> currently doesn't provide any instruction to achieve this, is there
> any way to achieve this in gem5 currently or should I try to add a new
> instruction for this.
>
> Thank you, Regards
> Deepak Mohan
>
> On Wed, Jun 16, 2021 at 2:20 AM Ayaz Akram  wrote:
> >
> > Hi Deepak,
> >
> > RISC-V PMA is supported in gem5. You can have a look at the source here:
> https://gem5.googlesource.com/public/gem5/+/refs/heads/develop/src/arch/riscv/PMAChecker.py
> >
> > Also, here is an example of how this can be used in the gem5 config
> script:
> >
> >
> https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/develop/src/riscv-fs/configs-riscv-fs/system/system.py#214
> >
> > -Ayaz
> >
> > On Tue, Jun 15, 2021 at 1:23 PM Deepak Mohan via gem5-users <
> gem5-users@gem5.org> wrote:
> >>
> >> Hi,
> >>   I was writing an OS that can run on RISC-V FS mode in gem5. I want
> >> to make certain address ranges uncacheable (for some memory mapped
> >> devices). RISCV page table entries doesn't provide any flags to
> >> achieve this. The proper way to do this in RISCV seems to be using PMA
> >> (Physical Memory Attributes), but I couldn't find any implementations
> >> of PMA in gem5. Is PMA implemented for RISCV in gem5 ? Is this the
> >> right approach to solve this problem ? Can anybody give me any ideas
> >> to solve this problem ? It will be great if anyone can provide some
> >> ideas.
> >>
> >> Thanks,
> >> Deepak Mohan
> >> ___
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> >> To unsubscribe send an email to gem5-users-le...@gem5.org
> >> %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
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[gem5-users] Re: Making an address range uncacheable RISCV FS.

[Ayaz Akram via gem5-users]

Hi Deepak,

RISC-V PMA is supported in gem5. You can have a look at the source here:
https://gem5.googlesource.com/public/gem5/+/refs/heads/develop/src/arch/riscv/PMAChecker.py

Also, here is an example of how this can be used in the gem5 config script:

https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/develop/src/riscv-fs/configs-riscv-fs/system/system.py#214

-Ayaz

On Tue, Jun 15, 2021 at 1:23 PM Deepak Mohan via gem5-users <
gem5-users@gem5.org> wrote:

> Hi,
>   I was writing an OS that can run on RISC-V FS mode in gem5. I want
> to make certain address ranges uncacheable (for some memory mapped
> devices). RISCV page table entries doesn't provide any flags to
> achieve this. The proper way to do this in RISCV seems to be using PMA
> (Physical Memory Attributes), but I couldn't find any implementations
> of PMA in gem5. Is PMA implemented for RISCV in gem5 ? Is this the
> right approach to solve this problem ? Can anybody give me any ideas
> to solve this problem ? It will be great if anyone can provide some
> ideas.
>
> Thanks,
> Deepak Mohan
> ___
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>
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[gem5-users] Re: gem5 Intel SGX model

[Ayaz Akram via gem5-users]

Hi Jared,

Not SGX, but we recently did some work on running RISC-V-based TEEs
(Keystone specifically) in gem5, which you might find useful.
You can look at the documentation here:
https://github.com/darchr/Keystone-experiments

-Ayaz

On Thu, Jun 10, 2021 at 11:41 AM Jared Nye  wrote:

> Hello,
>
> Good afternoon. Is anyone aware of a gem5 simulator which models Intel SGX
> or if one is currently being worked on?
>
> Thank you,
> Jared
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[gem5-users] Re: KVM patch for FS mode and PARSEC on gem5-21

[Ayaz Akram via gem5-users]

Hi Rajesh,

I think the error you are seeing is because tlbs are exposed through an mmu
unit in gem5 now. I guess changing line 117 in caches.py as in this file (
https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/src/boot-exit/configs/system/caches.py)
should work for you.

-Ayaz

On Wed, Jun 9, 2021 at 2:04 PM Rajesh Shashi Kumar via gem5-users <
gem5-users@gem5.org> wrote:

> Thank you for the quick response.
>
>
>- Thank you for confirming that the KVM fix has been integrated into
>the stable branch (pointing to gem5-v21.0). At this time, I have not
>managed to get PARSEC working in FS mode on the stable branch (v21.0) and I
>am debugging the issue described below
>- For context, I encountered the following error on gem5-v21.0 while
>running PARSEC which made me explore reverting back to v20.1 (and the KVM
>patch) as described in the gem5art documentation. I'm using the latest
>PARSEC config run scripts from the gem5-resources repository
>
> 
>
> gem5 version 21.0.0.0
> gem5 compiled Jun 10 2021 01:34:21
> gem5 started Jun 10 2021 01:57:17
> gem5 executing on lenovo, pid 20958
> command line: gem5/build/X86/gem5.opt 
> /home/rajesh/tests/configs/run_parsec.py 
> /home/rajesh/tests/linux-stable/vmlinux-4.19.83 
> /home/rajesh/tests/disk-image/parsec/image/parsec.img kvm streamcluster 
> simsmall 1
>
> Traceback (most recent call last):
>   File "", line 1, in 
>   File "build/X86/python/m5/main.py", line 455, in main
>   File "/home/rajesh/tests/configs/run_parsec.py", line 79, in 
> system = MySystem(kernel, disk, cpu, int(num_cpus))
>   File "/home/rajesh/tests/configs/system/system.py", line 78, in __init__
> self.createCacheHierarchy()
>   File "/home/rajesh/tests/configs/system/system.py", line 158, in 
> createCacheHierarchy
> cpu.mmucache.connectCPU(cpu)
>   File "/home/rajesh/tests/configs/system/caches.py", line 117, in connectCPU
> for tlb in [cpu.itb, cpu.dtb]:
>   File "build/X86/python/m5/SimObject.py", line 1379, in __getattr__
> AttributeError: object 'X86KvmCPU' has no attribute 'itb'
>   (C++ object is not yet constructed, so wrapped C++ methods are unavailable.)
>
> Thank you for your time.
>
> -- Rajesh Shashi Kumar
>
> On Thu, Jun 10, 2021 at 12:51 AM Bobby Bruce  wrote:
>
>> The "Fix KVM on Intel platforms" patch is on stable, it was added here:
>> https://gem5-review.googlesource.com/c/public/gem5/+/12278
>>
>> The other patch your cherry-picking I'm less sure of, but I dont think
>> it's a relevant problem anymore from what I can ascertain.
>>
>> I apologize that the gem5art documentation is using such an old version
>> of gem5. Have you managed to get this working with the stable branch
>> (version 21.0)? I'm not aware of any reason why it shouldn't work.
>>
>> --
>> Dr. Bobby R. Bruce
>> Room 3050,
>> Kemper Hall, UC Davis
>> Davis,
>> CA, 95616
>>
>> web: https://www.bobbybruce.net
>>
>>
>> On Wed, Jun 9, 2021 at 7:06 AM Rajesh Shashi Kumar via gem5-users <
>> gem5-users@gem5.org> wrote:
>>
>>> Hi,
>>>
>>> I'm attempting to run PARSEC benchmarks in FS mode on gem5-v21.0. I have
>>> encountered an issue with KVM on Intel machine. I believe the same was
>>> addressed by this patch
>>>  recommended
>>> earlier in the mailing list
>>> 
>>> .
>>>
>>> panic: KVM: Failed to enter virtualized mode (hw reason: 0x8021)
>>>
>>> Most of the tutorials on gem5art
>>>  in
>>> gem5 documentation recommend using gem5-v20.1, but I noticed that applying
>>> the patch on 20.1 or 21 is not a trivial merge. For the time being, I've
>>> been able to use this specific commit tag described in
>>> gem5art-experiments .
>>>
>>> git clone https://gem5.googlesource.com/public/gem5cd gem5
>>> git checkout *d40f0bc579fb8b10da7181*
>>> git remote add darchr https://github.com/darchr/gem5
>>> git fetch darchr*git cherry-pick 
>>> 6450aaa7ca9e3040fb9eecf69c51a01884ac370c**git cherry-pick 
>>> 3403665994b55f664f4edfc9074650aaa7ddcd2c*
>>> scons build/X86/gem5.opt -j8
>>>
>>> At this point, I have two questions:
>>>
>>>1. Is the KVM patch necessary on gem5-v21?
>>>2. In case someone has encountered a similar issue previously, were
>>>you able to find a way to merge the patch on newer gem5 releases
>>>
>>> Thank you for your time.
>>>
>>> Regards,
>>> Rajesh Shashi Kumar
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>>
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[gem5-users] Re: Copying/Writing data from one packet to another packet in gem5

[Ayaz Akram via gem5-users]

Hi Aritra,

As you might have already noticed that there is a ptr to the data being
transferred (PacketDataPtr data) in the packet class:

http://doxygen.gem5.org/release/current/classPacket.html

I think you should be able to use methods like setData(), writeData() from
the same class to copy data from one packet to the other using a ptr to
that data.

-Ayaz

On Fri, Apr 9, 2021 at 12:42 PM bagchi95aritra--- via gem5-users <
gem5-users@gem5.org> wrote:

> Hi all,
>
> In gem5, the data a packet brings from the main memory to the cache is
> first written into a particular cache block. Later, that cache block
> supplies the data to the outstanding misses at the MSHR (targets). gem5 has
> some built-in methods defined under the “Packet” class for transferring
> data between a cache block and a packet.
>
> Is there any way/method in gem5 by which the data of a packet can directly
> be written/copied to another packet? Can anyone put some light on it?
>
> Thanks and regards,
> Aritra
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[gem5-users] Re: FS RISCV PCI

[Ayaz Akram via gem5-users]

Hi Nikolaos,

Thanks for bringing this to our attention. We are looking at this problem
here at Davis and will try to respond soon.

-Ayaz

On Sat, Apr 10, 2021 at 4:42 AM Νικόλαος Ταμπουρατζής via gem5-users <
gem5-users@gem5.org> wrote:

>
> Dear Gem5 community,
>
> I try to add PCI interface in RISCV arch doing the following steps
> (similar with ARM RealView - I use the gem5-v21):
>
> 1) Create a file gem5/src/dev/riscv/pci_host.cc with the following code:
>
> #include "dev/riscv/pci_host.hh"
> #include "params/GenericRiscvPciHost.hh"
>
> GenericRiscvPciHost::GenericRiscvPciHost(const GenericRiscvPciHostParams
> )
>  : GenericPciHost(p), intBase(p.int_base), intCount(p.int_count)
> {
> }
>
> uint32_t
> GenericRiscvPciHost::mapPciInterrupt(
>  const PciBusAddr , PciIntPin pin) const
> {
>
>  fatal_if(pin == PciIntPin::NO_INT,
>   "%02x:%02x.%i: Interrupt from a device without interrupts\n",
>   addr.bus, addr.dev, addr.func);
>
>  return intBase + (addr.dev % intCount);
> }
>
> 2) Create a file gem5/src/dev/riscv/pci_host.hh with the following code:
>
> #ifndef __DEV_RISCV_PCI_HOST_HH__
> #define __DEV_RISCV_PCI_HOST_HH__
>
> #include "dev/pci/host.hh"
>
> struct GenericRiscvPciHostParams;
>
> class GenericRiscvPciHost : public GenericPciHost
> {
>private:
>  const uint32_t intBase;
>  const uint32_t intCount;
>
>public:
>  GenericRiscvPciHost(const GenericRiscvPciHostParams );
>  virtual ~GenericRiscvPciHost() {}
>
>protected:
>  uint32_t mapPciInterrupt(const PciBusAddr ,
>   PciIntPin pin) const override;
> };
>
> #endif // __DEV_RISCV_PCI_HOST_HH__
>
> 3) Add the "Source('pci_host.cc')" to gem5/src/dev/riscv/SConscript
>
> 4) Add the following code in gem5/src/dev/riscv/HiFive.py according to
> RealView GenericArmPciHost:
>
> from m5.objects.Ethernet import NSGigE, IGbE_igb, IGbE_e1000
>
> from m5.objects.Device import BasicPioDevice
> from m5.objects.PciHost import *
> from m5.SimObject import SimObject
>
> class GenericRiscvPciHost(GenericPciHost): #Add this class (PCI)
>  type = 'GenericRiscvPciHost'
>  cxx_header = "dev/riscv/pci_host.hh"
>  int_base   = Param.Unsigned("PCI interrupt base")
>  int_count  = Param.Unsigned("Maximum number of interrupts used by
> this host")
>
>  # This python parameter can be used in configuration scripts to turn
>  # on/off the fdt dma-coherent flag when doing dtb autogeneration
>  _dma_coherent = True
>
>  def generateDeviceTree(self, state):
>  local_state = FdtState(
>  addr_cells=3, size_cells=2,
>  cpu_cells=1, interrupt_cells=1)
>
>  node = FdtNode("pci")
>
>  if int(self.conf_device_bits) == 8:
>  node.appendCompatible("pci-host-cam-generic")
>  elif int(self.conf_device_bits) == 12:
>  node.appendCompatible("pci-host-ecam-generic")
>  else:
>  m5.fatal("No compatibility string for the set
> conf_device_width")
>
>  node.append(FdtPropertyStrings("device_type", ["pci"]))
>
>  # Cell sizes of child nodes/peripherals
>  node.append(local_state.addrCellsProperty())
>  node.append(local_state.sizeCellsProperty())
>  node.append(local_state.interruptCellsProperty())
>  # PCI address for CPU
>  node.append(FdtPropertyWords("reg",
>  state.addrCells(self.conf_base) +
>  state.sizeCells(self.conf_size) ))
>
>  # Ranges mapping
>  # For now some of this is hard coded, because the PCI module does
> not
>  # have a proper full understanding of the memory map, but
> adapting the
>  # PCI module is beyond the scope of what I'm trying to do here.
>  # Values are taken from the VExpress_GEM5_V1 platform.
>  ranges = []
>  # Pio address range
>  ranges += self.pciFdtAddr(space=1, addr=0)
>  ranges += state.addrCells(self.pci_pio_base)
>  ranges += local_state.sizeCells(0x1)  # Fixed size
>
>  # AXI memory address range
>  ranges += self.pciFdtAddr(space=2, addr=0)
>  ranges += state.addrCells(self.pci_mem_base)
>  ranges += local_state.sizeCells(0x4000) # Fixed size
>  node.append(FdtPropertyWords("ranges", ranges))
>
>  if True:
>#Change this to True because Realview calls always
> ARM_PCI_INT_DEV
>  plic = self._parent.unproxy(self).plic
>  int_phandle = state.phandle(plic)
>  # Interrupt mapping
>  interrupts = []
>
>  # child interrupt specifier
>  child_interrupt = local_state.interruptCells(0x0)
>
>  # parent unit address
>  parent_addr = 0x0
>#get this from /gem5/system/arm/dt/platforms file
>
>  for i in range(int(self.int_count)):
>  parent_interrupt = int(self.int_base) + i
>

[gem5-users] Re: Creating a disk image for FS mode

[Ayaz Akram via gem5-users]

Hi Ahmed,

Did the scons command in the file you referred above not work for you?

Btw, you might find more information on the m5 utility in this README
inside the source:

https://gem5.googlesource.com/public/gem5/+/refs/heads/develop/util/m5/README.md

-Ayaz

On Thu, Feb 4, 2021 at 2:40 AM ahmed.gheith--- via gem5-users <
gem5-users@gem5.org> wrote:

> Hi everyone,
>
> I'm trying to create a disk image. I tried using method 2 and 3 from this
> page (https://www.gem5.org/documentation/general_docs/fullsystem/disks).
> In both methods its required to create an m5 binary file using a Makefile
> which should be in util/m5, but I can't find the Makefile.
> I found in a previous thread that the new method can be found in (
> https://www.gem5.org/documentation/general_docs/m5ops/) but I couldn't
> find anything regarding building an m5 binary file here.
>
> Can someone please give me some guidance?
> Thanks in advance.
>
> Best regards,
> Ahmed Gheith
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[gem5-users] Re: How to disable branch predictor in MinorCPU

[Ayaz Akram via gem5-users]

Hi,

In my opinion, you might not be able to disable a branch predictor using
NULL assignment. A way to make this possible is to add your own (simple)
branch predictor (or hack one of the existing branch predictors) which will
always return not-taken.

-Ayaz

On Thu, Dec 24, 2020 at 6:00 AM -17 via gem5-users 
wrote:

>
> Hi all
>
> Hello everyone, I am exploring the use of MinorCPU's branch predictor
> recently.
> I want to know whether it is possible to use NULL assignment
> to directly disable the branch predictor like disabling the Cache
> prefetcher, or is there any other way?
>
> In addition, is there any documentation for the complex branch predictor
> in gem5?
>
> Thanks a lot in advance!
> --
> /**/
> NUDTSiqing Fu
>
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[gem5-users] Re: Run spec cpu 2006 on gem5

[Ayaz Akram via gem5-users]

///
>
> According to the file ""speccmds.cmd""  in "
> cpu2006/benchspec/CPU2006/401.bzip2/run/ run_base_ref_gcc43-64bit.", the
> bzip2  built with  6 input( input.source , chicken.jpg , liberty.jpg ,
> input.program , text.html , input.combined )  , should I use 6 input(
> input.source , chicken.jpg , liberty.jpg , input.program , text.html ,
> input.combined ) for running bzip2 on gem5-fullsystem-arm or just use
> input.combined for input of  bzip2?
>
>   /
>
> What arguments are usually used to implement the "spec cpu 2006" on
> gem5-fullsysytem and how should they be used?
>
>
> When I ran 401.bzip2 ,it finished after 10days.  I need to  know between
> "429.mcf, 445.gobmk, 
> 456.hmmer,458.sjeng,462.libquantum,473.astar,483.xalancbmk
> and 998.specrand"",Which one runs in 10 short days?
>
> /
>
> and Is it not problem , if I use 4cores and cpu-type=DerivO3CPU for
> running "spec cpu 2006" on gem5-fullsystem ?
>
>
> For the last question, if I use sript file for running  bzip2 on
> gem5-fullsystem   the following command, is it correct?
>
>
>
> #!/bin/sh
> cd /cpu2006/benchspec/CPU2006/401.bzip2/run/ run_base_ref_gcc43-64bit.
> /sbin/m5 resetstats
> /cpu2006/benchspec/CPU2006/401.bzip2/run/ run_base_ref_gcc43-64bit.
> /bzip2_base.gcc43-64bit   input.combined  200  >  input.combined.out  2 >
> input.combined.err
> /sbin/m5 exit
>
>
> Best regards.
>
>
>
>
>
>
>
>
>
>
> On Sun, Dec 20, 2020 at 1:16 PM Ayaz Akram  wrote:
>
>> Hi,
>>
>> The output you are seeing indicates a successful bzip run. As far as I
>> remember bzip binary inside run folder (the one you referred to above) uses
>> "data/all/input/input.combined" file  by default and the output you are
>> seeing definitely shows that bzip ran with input.combined. If you want to
>> use a different input you can pass that as an argument to bzip. Having said
>> that, I think it is generally better to run spec workloads using runspec
>> tool. I think you can find more information on how to do it on SPEC website.
>>
>> -Ayaz
>>
>
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[gem5-users] Re: Run spec cpu 2006 on gem5

[Ayaz Akram via gem5-users]

Hi,

The output you are seeing indicates a successful bzip run. As far as I
remember bzip binary inside run folder (the one you referred to above) uses
"data/all/input/input.combined" file  by default and the output you are
seeing definitely shows that bzip ran with input.combined. If you want to
use a different input you can pass that as an argument to bzip. Having said
that, I think it is generally better to run spec workloads using runspec
tool. I think you can find more information on how to do it on SPEC website.

-Ayaz
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[gem5-users] Re: PTE Flags

[Ayaz Akram via gem5-users]

Hi,

Based on my understanding of what you are trying to do, I would suggest
looking into src/arch/x86/tlb.cc (assuming you want to use x86) around line
400, to see how to access page table entries from a process pointer.
syscall_emul.hh already includes sim/process.hh, so you can follow what is
done in tlb.cc and play with the flags that you want to change.

-Ayaz

On Fri, Dec 11, 2020 at 5:08 PM ABD ALRHMAN ABO ALKHEEL via gem5-users <
gem5-users@gem5.org> wrote:

> Hello Everyone,
>
> I am currently working on write_func system call in syscall_hh and i want
> to prevent writing to the file by changing the page table entry (PTE) flag.
> Where should i change?
>
> Any help would be appreciated.
>
> Thanks
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[gem5-users] Re: TLB in SE simulation

[Ayaz Akram via gem5-users]

Hi Francisco,

Based on my understanding, TLBs are modeled in SE mode for x86. With what
accuracy and preciseness TLB timing is modeled is debatable though.
However, it does not seem like that is the case for RISC-V. Specifically,
if you take a look at the src/arch/riscv/tlb.cc (TLB::translate()), you
will notice that the address translation request is sent to the process
page table (rather than looking into the tlb) if FullSystem mode is not
used. I guess that is the reason you do not see any TLB related debug
printings.

-Ayaz

On Fri, Dec 11, 2020 at 12:55 PM Francisco Carlos via gem5-users <
gem5-users@gem5.org> wrote:

> Hello everyone,
>
> I am using gem5 SE mode and investigating memory operation latencies and
> how virtual memory can affect them in a superscalar processor (DerivO3CPU).
>
> Does the SE mode consider TLB delays, TLB hit and miss, for instance, or
> this is implemented only in FullSystem mode?
>
> I saw in the stats file that there are stats related to itb and dtb, but
> in my simulations, they are always zero. Is that an expected behavior?
>
> Additionally, I was trying to have a better understanding of how TLB works
> in gem5, so I enabled TLB debug flag and nothing was printed.
>
> I am currently using the gem5 20.1.0.2 Risc-V ISA and se.py as the
> configuration file, so there is nothing special in my configuration file.
> Any help would be appreciated.
>
>
>
>
> --
> Francisco Carlos Silva Junior
> Phd Student at University of Brasilia
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[gem5-users] Re: how to add more than 1 ide disk in gem5 fullsystem

[Ayaz Akram via gem5-users]

Hi,

I think the config script (system.py) in boot tests on gem5-resources (
https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/develop/src/boot-exit/configs/)
shows how to add two disks in your configuration. Specifically, looking
into setDiskImages()might be helpful.

-Ayaz

On Tue, Nov 24, 2020 at 8:35 AM Liyichao via gem5-users 
wrote:

>
> hi all：
>  how to add more than 1 ide disks in gem5 fullsystem？
>
>
> I want to see that sda sdb sdc ... in OS so that I can test some 
> distribution application like ceph.
>
>
>
> --
>
> 李翼超 charlie
> Mobile：+86-15858232899
> Email：liyic...@huawei.com
>
>
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[gem5-users] Re: Instruction execute stage clock cycles in MinorCPU

[Ayaz Akram via gem5-users]

Yeah, it does not seem like m5ops are implemented in RISC-V yet. I did not
see any RISC-V specific code in "util/m5/src/abi/". One workaround could be
to stop simulation at a particular instruction count (e.g. if you know at
what instruction number your function of interest starts and ends) from the
Python run script and dump stats. Please, note that there might be other
(and better) ways to do this.

-Ayaz

On Wed, Nov 25, 2020 at 9:37 PM Volkan Mutlu via gem5-users <
gem5-users@gem5.org> wrote:

> Hi Ayaz,
>
> Thank you so much for your answers, these definitely cleared things up a
> bit. I'll try to look deeper in the code and see if I can navigate the
> Python interface to adjust latencies. Also thanks for pointing out m5ops, I
> was not aware. Though I wonder whether the documentation has not been
> updated or if RISC-V has not been provided as a target ISA option for this
> yet, I'll check that out as well.
>
> Best,
> Volkan
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[gem5-users] Re: Instruction execute stage clock cycles in MinorCPU

[Ayaz Akram via gem5-users]

Hi Volkan,

Following is my understanding of the issues you mentioned in your email (I
hope someone with more RISCV experience can augment/correct this):

1. Each functional unit can be responsible for execution of multiple
classes of instructions and you can configure the latency of each class of
instructions using the Python interface.
The class that an instruction belongs to is decided through the ISA
specific instruction decoding module (the "execute" function which can
execute a particular instruction is also decided at this point). If you
have not already, I will suggest having a look at this page:
https://www.gem5.org/documentation/general_docs/cpu_models/execution_basics
Once the instruction reaches the execute stage, the class of the
instruction and the corresponding latency are used to decide when the
results of the operation will be available.

2.  gem5 tries to keep the ISA independent parts of micro-architecture same
for all ISAs. So, mostly MinorCPU will behave similarly irrespective of the
ISA. But, ISA specific things will be handled differently. For example,
when you build the MinorCPU for RISC vs x86, the build system generates ISA
specific instruction classes with different execute methods for example.
Moreover, some parts of the CPU micro-architecture could be ISA specific
and you might occasionally find ISA specific directives in the code for
conditional compilation.

3. If you wish to instrument individual functions of your code, you can
rely on m5ops (https://www.gem5.org/documentation/general_docs/m5ops/)
which allow you to move control out of the simulated code to potentially do
things like generating stats at that particular point of execution or
switching to different CPU models.

-Ayaz

On Wed, Nov 25, 2020 at 6:53 PM Volkan Mutlu via gem5-users <
gem5-users@gem5.org> wrote:

> Hello all, I'm new to gem5 and I'm trying to use it as a simulation
> environment for a RISC-V related project. I'll first ask my questions, and
> if there are any confusions as to what I'm trying to achieve please see
> description below. Any help or response is much appreciated!
> 1) For the MinorCPU model, how does gem5 know how many clock cycles an
> instruction's execution would take? For instance, in most
> microarchitectures, the instructions ADDI, MUL and DIV would all take
> different number of cycles to execute. Where is timing information for this
> set? Digging into the code a bit, I've noticed there is a class called
> MinorFUTimings where some timing properties can be set for a functional
> unit which seems like the answer to my question, but I couldn't find
> anything that indicates this is used for each standard instruction to
> adjust their timings. There is likely a more systematic way this is
> managed, which makes more sense of course, but I wasn't able to figure it
> out after looking through the documentation on Minor CPU model and the
> source code.
> 2) Seeing as the CPU models in gem5 span all ISAs, I'm assuming these
> models don't necessarily reflect any particular microarchitecture's
> details. Is there any difference between the MinorCPU when I build gem5 for
> RISC-V vs. x86? Especially pertaining to this timing information I
> mentioned in my first question. How does gem5 know, for instance, how many
> cycles a simple multiply with register operands would take for RISC-V vs.
> x86, both with the MinorCPU model?
> 3) What would be the best way to get information on time spent in
> functions when running gem5 in SE mode for RISC-V? I tried using the
> clock() function from the C time library and I get results that roughly
> make sense but I'm not sure if this is accurate. For now I am only taking
> the number of CPU cycles reported in stats at face value, but it would be
> convenient to actually instrument the code.
> Thanks in advance for your attention and responses! Below are more details
> if needed.
> Basically, I'm trying to extend RV64 with some custom instructions and run
> certain benchmarks to see what performance improvement I can get compared
> to standard software libraries that provide the functions that these
> instructions will fulfill. One good example I'm particularly trying are SHA
> instructions (x86 provides an extension for these, for instance, but as far
> as I know RISC-V doesn't have a standard extension for them).
> To keep things simpler, I wanted to use the MinorCPU model. Now, I was
> able to add custom instructions and run compiled code invoking those, but I
> have not specified any details regarding the execution of these custom
> instructions. As far as I know, gem5 only knows which 'class' of
> instructions they belong to, their opcodes and their functional
> description. Yet, when I look at the stats after running my code its clear
> that gem5 is making some assumptions as to how many clock cycles these
> instructions are taking. To get a better sense of this I included a new
> instruction that's basically a duplicate of an already existing 

[gem5-users] Re: How to use CommMonitor in gem5

[Ayaz Akram via gem5-users]

Hi,

1. I remember using CommMonitor with DerivO3CPU for a small example and the
output looked fine to me. Maybe someone else can point out if there is
something fundamentally broken.

2. You should be able to use gem5/util/decode_packet_trace.py to convert
the generated trace (after decompressing it) to human readable format. I
think the trace will generally have a time stamp, information about the
request, and physical address (as far as I remember).

3. I think you should be able to connect it between l1dcache and cpu the
same way you do between l2 cache and membus. For example, cpu's requestor
port should be connected with the comm monitor's responder port and
monitor's requestor port should be connected with dcache's responder port.

-Ayaz

On Sun, Nov 22, 2020 at 7:50 PM yujiecui--- via gem5-users <
gem5-users@gem5.org> wrote:

> I want to record the access details of the cache. I saw some answers,
> saying that CommMonitor can help. But no more details were found.
>
> I have some questions about CommMonitor?
>
> 1. First of all, can Commmonitor be used for DerivO3CPU or only
> TimingSimpleCPU? I tried it on DerivO3CPU and there was output. But
> somewhere I seem to hear that it cannot be used for DerivO3CPU.
>
> 2. My understanding of CommMonitor is that it is like a filter. The data
> flowing through it is recorded. For example, add commMonitor between l2 and
> membus,
>
>  system.monitor2 = CommMonitor()
>  system.monitor2.trace = MemTraceProbe(trace_file = "CT_mon2.trc.gz")
>  system.monitor2.slave = system.l2.mem_side
>  system.membus.slave = system.monitor2.master
>  system.l2.cpu_side = system.tol2bus.master
> The output format is :
>
>  11500: system.monitor2: Forwarded read request
>   77000: system.monitor2: Latency: 65500
>   77000: system.monitor2: Received read response
>  103000: system.monitor2: Forwarded read request
>  104000: system.monitor2: Forwarded read request
>  165000: system.monitor2: Latency: 62000
>  165000: system.monitor2: Received read response
>  17: system.monitor2: Latency: 66000
>  17: system.monitor2: Received read response
>  194500: system.monitor2: Forwarded read request
>  200500: system.monitor2: Forwarded read request
>  243000: system.monitor2: Latency: 48500
>  243000: system.monitor2: Received read response
>  249000: system.monitor2: Latency: 48500
>  249000: system.monitor2: Received read response
>  267500: system.monitor2: Forwarded read request
>  269500: system.monitor2: Forwarded read request
>  274000: system.monitor2: Forwarded read request
>
> The generated CT_mon2.trc.gz file is a binary file after decompression,
> what should I do to see the data inside? It would be better if I can output
> the address and data
>
> 3. How to use it between l1dcache and cpu?
>
> Thanks for all related answers. I also put the question on Stackoverflow.
> Below is the website.
> https://stackoverflow.com/questions/64962277/how-to-use-commmonitor-in-gem5
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[gem5-users] Re: How to simulate multithread, multicore and multiprocessor system ?

[Ayaz Akram via gem5-users]

Hi Duc,

By passing  a list of CPUs to the system.cpu (as in the attached Python
script), you are creating a multicore CPU (CPU here refers to a core).
Secondly, if your CPU has SMT enabled, you should be able to pass multiple
processes to the workload option.

Btw, there is already a JIRA issue created for the problem you are running
into: https://gem5.atlassian.net/browse/GEM5-803

-Ayaz

On Mon, Nov 9, 2020 at 2:18 AM Đức Anh via gem5-users 
wrote:

> Hello all,
>
> I am trying to create a system having multiple CPUs by passing a list of
> CPU to the system.cpu. So far it works with TimingSimpleCPU, but for the
> DerivO3CPU it crashes. I include the crash log, the python config file, and
> the C workload file. I am using gem5 20.1, pulled from the stable
> branch, gcc version 7.5.0 (Ubuntu 7.5.0-3ubuntu1~18.04), python 2.7.17. The
> command line I use is:
> ./build/X86/gem5.opt configs/tutorial/two_core.py
> The 2 binary files for 2 workloads are almost the same, I just change the
> text in printf, and the number of loops.
>
> I also wonder that by passing a list of CPU to the system.cpu, am I
> creating a system is 1 multicore CPU or a system with multiple separate
> CPU? And how to pass multiple workloads on 1 CPU? I saw it accept a list,
> but it throws an error if I pass a list with more than 1 workload.
>
> Best regards,
> Duc Anh
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[gem5-users] Re: A question regarding to VIPT/PIPT

[Ayaz Akram via gem5-users]

Hi Leon,

I think you can use lower than normal latency values (what would be
reasonable for PIPT) to model VIPT cache in gem5. To understand how to
configure cache latencies, have a look here (if you have not already):

https://www.gem5.org/documentation/learning_gem5/part1/cache_config/

-Ayaz



On Wed, Nov 4, 2020 at 11:53 PM Leon Zhao via gem5-users <
gem5-users@gem5.org> wrote:

> Hi Ayaz,
>
> Sorry to bother you again, but the aforementioned approach that you
> proposed to model a VIPT in gem5 has struck me lately, since implementing a
> real VIPT is, now I see, not worth the fight. Any chance you could
> elaborate on your earlier proposition? Like, what latency I can change and
> how, or how to calculate the latency.
>
> Looking forward to your reply.
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[gem5-users] Re: Why are there still so many decoding-related operations when fetching instructions into the instruction queue?

[Ayaz Akram via gem5-users]

Hi Yujiecui,

The fetch stage in O3CPU fetches cache lines from instruction cache and
also calls ISA specific decoder implementation to decode the raw bytes into
instructions and access the corresponding micro-ops for these instructions
(In other words, fetch stage outputs the micrco-ops). That's why you are
seeing all these decode calls. As far as I understand (specifically for
x86),  the functions you are referring to will decode a machine instruction
corresponding to the given PC, check if the instruction exist across the
cache block boundary and fetch more bytes (i.e. next cache block) etc.  As
far as Rom is concerned, I think it holds the micro-ops.

I will suggest you have a look at the following page:

http://www.m5sim.org/X86_Instruction_decoding

and decoder implementation for some ISA e.g. src/arch/x86/decoder.hh

-Ayaz

On Tue, Nov 3, 2020 at 4:52 AM yujiecui--- via gem5-users <
gem5-users@gem5.org> wrote:

> In the fetch function in the src/cpu/O3/fetch.impl file, when fetching
> instructions to the fetch queue, I saw some operations on the decoder,
> which made me very confused. For example, decoder[tid]->decode(thisPC),
> decoder[tid]->instReady(), decoder[tid]->needMoreBytes(),
> decoder[tid]->moreBytes(thisPC, fetchAddr, inst). Why are there so many
> decoding operations when fetching instructions into the fetch queue? What
> is the role of decoder[tid] here? What does needMoreBytes() do?
>
> Still fetch function in the src/cpu/O3/fetch.impl file, I saw some
> RomMicroPC. I want to know what kind of instructions are in rom?
>
> I stepped through it many times, but I still have trouble understanding.
> All related answers are very welcome. Thanks
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[gem5-users] Re: A question regarding to VIPT/PIPT

[Ayaz Akram via gem5-users]

Hi,

I am not totally sure how easy would it be to modify the current
implementation, but following pointers to understand the codebase and where
to make modifications might be useful:

to understand how virtual to physical address translation takes place look
at:

src/arch/[your ISA e.g. x86]/tlb.cc and tlb.hh

how the tlb translation functions are called by the pipeline stages (e.g.
in case of O3 CPU) and their output is used to access caches:

src/cpu/o3/fetch_impl.hh
src/cpu/o3/lsq_impl.hh

how cache tags are created and accessed

src/mem/cache/tags/*

-Ayaz

On Tue, Oct 20, 2020 at 7:43 AM Leon Zhao via gem5-users <
gem5-users@gem5.org> wrote:

> Hi Ayaz,
>
> Thank you for your reply. In spite of your proposal, I still hope to
> implement real VIPT in gem5 (20.0.0.3). If I'm to do that, do you know what
> files I should modify or add and maybe something important to notice?
>
> Looking forward to your reply!
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[gem5-users] Re: A question regarding to VIPT/PIPT

[Ayaz Akram via gem5-users]

Hi Leon,

Since, gem5's caches are PIPT so there should not be an aliasing problem
and you can change the latency of the cache to model a VIPT cache. Since, a
VIPT cache should not have aliasing problem if all index bits come from the
page offset (as far as I understand), maybe for a realistic (non aliasing)
VIPT cache model, you can try to configure the size of the cache such that
the previously stated condition is met. Others might have better answers
though.

As far as "arch/arm/kernel/setup.c" is concerned, it is from the Linux
kernel source (e.g.
https://elixir.bootlin.com/linux/latest/source/arch/arm/kernel/setup.c).

-Ayaz

On Mon, Oct 19, 2020 at 6:35 PM Leon Zhao via gem5-users <
gem5-users@gem5.org> wrote:

> Hi Ayaz,
>
> I can't thank you enough for you reply. I'm aware of the fact that from
> software's perspective, VIPT and PIPT should be functioning equally but
> what piqued my interest is what it looks like from hardware's perspective.
>
> Let's say both i-cache and d-cache are working under PIPT, do you have any
> idea about what I should do if I want to implement VIPT in gem5, hopefully
> with no aliasing problem? Any pointers would do.
>
> Also, I scrutinized the page you mentioned above, but sadly there's no
> arch/arm/kernel/setup.c in my gem5 directory.
>
> Thank you again and looking forward to your reply!
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[gem5-users] Re: A question regarding to VIPT/PIPT

[Ayaz Akram via gem5-users]

Hi Leon,

In gem5, the caches are PIPT technically. But, you can model the timing of
a VIPT cache by changing the latency of your cache. As far as the kernel
boot log is concerned, I am not fully sure if "CPU: PIPT / VIPT nonaliasing
data cache, PIPT instruction cache" refers to the actual hardware cache.
Even if it is, VIPT and PIPT should be treated in the same way from
software's perspective. Following link might be helpful to know what kernel
is exactly doing when this message is printed:

https://linux-arm-kernel.infradead.narkive.com/xBwIht4D/about-cachetype-on-armv7

-Ayaz

On Sat, Oct 17, 2020 at 12:21 AM Leon Zhao via gem5-users <
gem5-users@gem5.org> wrote:

> Hi everyone,
> I was running the following command in gem5 the other day:
>
> ..gem5.opt configs/example/fs.py --ruby --cpu-type=O3_ARM_N1
> --script=tests/test-progs/hello/bin/arm/linux/hello
> --kernel=/home/hippo/full_system_images/binaries/vmlinux.vexpress_gem5_v1.20170616
>
> and I noticed this appeared in the output:
>
> [0.00] CPU: ARMv7 Processor [410fc0f0] revision 0 (ARMv7),
> cr=14c5387d
> [0.00] CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction
> cache
>
> So when it says "PIPT / VIPT nonaliasing data cache", does it mean that on
> the level of data cache, there are two different routes (a) PIPT and (b)
> VIPT with no aliasing, or are they basically the same thing just with a
> difference in names?
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[gem5-users] Re: X86KvmCPU fails -- reason code 0x80000021

[Ayaz Akram via gem5-users]

Hello Ryan,

I think, if you are using an Intel machine, you will still need to apply
those patches. The conversation on this issue might be useful for you:

https://github.com/darchr/gem5art-experiments/issues/60

-Ayaz

On Thu, Oct 15, 2020 at 5:20 PM Gambord, Ryan via gem5-users <
gem5-users@gem5.org> wrote:

> Hello all,
>
> I'm working off commit b1b8af04439240c532d3530a02773b75b9853f77
>
> I get the following error when I try to run a full-system
> (configs/example/fs.py) with the X86KvmCPU:
>
> panic: KVM: Failed to enter virtualized mode (hw reason: 0x8021)
>
> I used to have kvm working with a pre-2018 version of gem5 on this server,
> so I know it should be possible. There were a few patches floating around
> that I had to apply, but they seem to have been merged by now, so I was
> hoping it would work oob.
>
> Can anyone confirm that this is a known good commit, or share one that is?
> The server I work on was recently upgraded and I am trying to figure out if
> it's a problem with gem5 or a problem with settings on the server that got
> wiped.
>
> Thank you,
> Ryan Gambord
> 
>
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[gem5-users] Re: CPU switching after booting system into FS mode.

[Ayaz Akram via gem5-users]

Hi Vipin,

You can boot Linux using KVM CPU in gem5 and then switch to a more detailed
CPU model to simulate your workloads. Please, have a look at the gem5 run
scripts for npb and parsec benchmarks in gem5 resources as examples:

https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/develop/src/

As far as gem5's support to boot x86 Linux is concerned, gem5-20 or
gem5-develop branch provide better support. You can find the working status
with gem5-20 here:

http://www.gem5.org/documentation/benchmark_status/

This page would soon be updated with the status of gem5-20.1.

-Ayaz


On Thu, Sep 17, 2020 at 6:10 AM VIPIN PATEL via gem5-users <
gem5-users@gem5.org> wrote:

> Hi All,
> I need to model a multicore system with a detailed out-of-order CPU for my
> research for executing multithreaded program in full system simulation.
> After following the documentation about the "X86 Linux Boot Status on
> gem5-19"
> (https://www.gem5.org/project/2020/03/09/boot-tests.html), I concluded
> booting linux for multicore in X86 is not supported in Gem5.
> Is there a work around for this? Something like booting the Linux with
> atomic CPU and after booting switching to DetailedO3 CPU.
>
> Any help would be appreciated.
>
> Thanks and regards,
> Vipin Patel
> Ph.D. Scholar IIT Kanpur
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[gem5-users] Re: An error occurred in i8237 DMA controller when running CPU SPEC 2017 benchmarks

[Ayaz Akram via gem5-users]

Hi Jinpeng,

First of all, you will have to recompile gem5 to use Ruby with
MESI_Two_Level (the default protocol is MI_example):

scons build/X86_MESI_Two_Level/gem5.opt --default=X86
PROTOCOL=MESI_Two_Level

Secondly, I will suggest you to compile your kernel following the
instructions here:
https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/develop/src/boot-exit/README.md
and use the referred linux config file (your kernel boot log makes me feel
that it is compiled with a different configuration)

Finally, the current develop branch of gem5 should have the best support to
boot Linux kernel with different configurations, so you might want to try
using that as well.

-Ayaz


On Mon, Jul 20, 2020 at 8:37 AM Jinpeng Miao via gem5-users <
gem5-users@gem5.org> wrote:

> Hi Hoa,
>
> Thanks so much for your help! I just tested it and it worked perfectly.
>
> Another question is that based on your test here(
> http://www.gem5.org/documentation/benchmark_status/#spec-2017-tests),
> gem5-20 along with linux-5.4 is able to support 2 O3 CPUs with the protocol
> MESI_Two-Level. But I cannot boot it successfully. It just stop running
> further at one point but not terminated either.
>
> *The command I run:*
> build/X86/gem5.opt configs/example/fs.py --kernel=vmlinux-5.4
> --disk-image=ubuntu-18.04.img --num-cpus=2 --ruby --cpu-type=DerivO3CPU
>
> *Output:*
> warn: instruction 'sgdt_Ms' unimplemented
> warn: x86 cpuid family 0x: unimplemented function 6
> warn: x86 cpuid family 0x: unimplemented function 6
> warn: x86 cpuid family 0x: unimplemented function 6
>
> *warn: Address 0xffc0 is outside of physical memory, stopping
> fetchwarn: Address 0xffc0 is outside of physical memory, stopping fetch*
> warn: instruction 'wbinvd' unimplemented
> warn: x86 cpuid family 0x: unimplemented function 6
> warn: x86 cpuid family 0x: unimplemented function 6
> warn: x86 cpuid family 0x: unimplemented function 6
> *hack: Assuming logical destinations are 1 << id.*
> warn: x86 cpuid: unknown family 0x4000
> warn: instruction 'fwait’ unimplemented
>
> *And the output at the VM terminal:*
> [0.383486] check: Scanning for low memory corruption every 60 seconds
> [0.383705] Initialise system trusted keyrings
> [0.383705] Key type blacklist registered
> [0.383705] workingset: timestamp_bits=36 max_order=17 bucket_order=0
> [0.388387] zbud: loaded
> [0.389302] squashfs: version 4.0 (2009/01/31) Phillip Lougher
> [0.389737] fuse: init (API version 7.31)
> [0.389737] *** VALIDATE fuse ***
> [0.389737] *** VALIDATE fuse ***
> [0.389737] Platform Keyring initialized
> [0.393641] Key type asymmetric registered
> [0.393641] Asymmetric key parser 'x509' registered
> [0.393641] Block layer SCSI generic (bsg) driver version 0.4 loaded
> (major 244)
> [0.393641] io scheduler mq-deadline registered
> [0.393641] shpchp: Standard Hot Plug PCI Controller Driver version: 0.4
> *!!! HERE STOP MOVING FURTHER !!!*
>
> Could anyone give some hints on how to solve this problem? Really
> appreciate it!
>
> Thanks,
> Jinpeng
>
>
> On Jul 17, 2020, at 3:11 PM, Hoa Nguyen  wrote:
>
> Hi Jinpeng,
>
> The error seems to cause by 'sysinfo', which is called by SPEC 2017
> before it starts running a workload. SPEC 2017 documents how to turn
> it off here: https://www.spec.org/cpu2017/Docs/utility.html#sysinfo.
>
> Basically, the fix is to add this line:
>
> sysinfo_program =
>
> to the SPEC config file. The SPEC config file used in the tutorial is
> /home/gem5/spec2017/config/myconfig.x86.cfg
>
> Regards,
> Hoa Nguyen
>
> On 7/17/20, Jinpeng Miao via gem5-users  wrote:
>
> Hello all,
>
> I am trying to build and run CPU SPEC 2017 benchmarks in the FS mode, but
> the process terminated unexpectedly with an error happening in i8237 DMA
> controller. I did not change the source code. I do not quite understand
> what
> causes this bug and how to fix it. Any help would be really appreciated.
> Thanks!
>
> Output as below:
>
>  REAL SIMULATION 
> info: Entering event queue @ 0.  Starting simulation...
> warn: x86 cpuid family 0x: unimplemented function 6
> warn: x86 cpuid family 0x: unimplemented function 6
> warn: x86 cpuid family 0x: unimplemented function 6
> warn: instruction 'fninit' unimplemented
> warn: Don't know what interrupt to clear for console.
> 3575291925: system.pc.com_1.device: attach terminal 0
> warn: instruction 'sgdt_Ms' unimplemented
> warn: x86 cpuid family 0x: unimplemented function 6
> warn: x86 cpuid family 0x: unimplemented function 6
> warn: x86 cpuid family 0x: unimplemented function 6
> warn: x86 cpuid: unknown family 0x4000
> warn: Tried to clear PCI interrupt 14
> warn: Write to unknown i8042 (keyboard controller) command port.
> warn: instruction 'verw_Mw_or_Rv' unimplemented
> warn: instruction 'verw_Mw_or_Rv' unimplemented
> warn: instruction 'verw_Mw_or_Rv' unimplemented
> warn: MOVNTDQ: Ignoring