[PATCH] watchdog: stop wdd when watchdog hw running in reboot_notifier
From: Zhao Qiang
In watchdog_reboot_notifier, wdd should be stopped when the device
is in hw_running state
Signed-off-by: Zhao Qiang
---
drivers/watchdog/watchdog_core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/watchdog/watchdog_core.c b/drivers/watchdog/watchdog_core.c
index 861daf4..ec670cc 100644
--- a/drivers/watchdog/watchdog_core.c
+++ b/drivers/watchdog/watchdog_core.c
@@ -154,7 +154,7 @@ static int watchdog_reboot_notifier(struct notifier_block
*nb,
wdd = container_of(nb, struct watchdog_device, reboot_nb);
if (code == SYS_DOWN || code == SYS_HALT) {
- if (watchdog_active(wdd)) {
+ if (watchdog_active(wdd) || watchdog_hw_running(wdd)) {
int ret;
ret = wdd->ops->stop(wdd);
--
2.7.4
RE: [PATCH 00/20] ethernet: ucc_geth: assorted fixes and simplifications
On 06/12/2020 05:12, Rasmus Villemoes wrote: > -Original Message- > From: Rasmus Villemoes > Sent: 2020年12月6日 5:12 > To: Jakub Kicinski > Cc: Leo Li ; David S. Miller ; > Qiang Zhao ; net...@vger.kernel.org; > linuxppc-...@lists.ozlabs.org; linux-kernel@vger.kernel.org; > linux-arm-ker...@lists.infradead.org; Vladimir Oltean > > Subject: Re: [PATCH 00/20] ethernet: ucc_geth: assorted fixes and > simplifications > > On 05/12/2020 21.53, Jakub Kicinski wrote: > > On Sat, 5 Dec 2020 20:17:23 +0100 Rasmus Villemoes wrote: > >> While trying to figure out how to allow bumping the MTU with the > >> ucc_geth driver, I fell into a rabbit hole and stumbled on a whole > >> bunch of issues of varying importance - some are outright bug fixes, > >> while most are a matter of simplifying the code to make it more > >> accessible. > >> > >> At the end of digging around the code and data sheet to figure out > >> how it all works, I think the MTU issue might be fixed by a > >> one-liner, but I'm not sure it can be that simple. It does seem to > >> work (ping -s X works for larger values of X, and wireshark confirms > >> that the packets are not fragmented). > >> > >> Re patch 2, someone in NXP should check how the hardware actually > >> works and make an updated reference manual available. > > > > Looks like a nice clean up on a quick look. > > > > Please separate patches 1 and 11 (which are the two bug fixes I see) > > I think patch 2 is a bug fix as well, but I'd like someone from NXP to > comment. It 's ok for me. Best Regards, Qiang Zhao
[PATCH] wdt: sp805: add watchdog_stop on reboot
From: Zhao Qiang Call watchdog_stop_on_reboot in probe func Signed-off-by: Zhao Qiang --- drivers/watchdog/sp805_wdt.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/watchdog/sp805_wdt.c b/drivers/watchdog/sp805_wdt.c index 190d26e..958dc32 100644 --- a/drivers/watchdog/sp805_wdt.c +++ b/drivers/watchdog/sp805_wdt.c @@ -291,6 +291,7 @@ sp805_wdt_probe(struct amba_device *adev, const struct amba_id *id) set_bit(WDOG_HW_RUNNING, >wdd.status); } + watchdog_stop_on_reboot(>wdd); ret = watchdog_register_device(>wdd); if (ret) goto err; -- 2.7.4
[Patch v2] spi: fsl-dspi: fix wrong pointer in suspend/resume
From: Zhao Qiang
Since commit 530b5affc675 ("spi: fsl-dspi: fix use-after-free in
remove path"), this driver causes a "NULL pointer dereference"
in dspi_suspend/resume.
This is because since this commit, the drivers private data point to
"dspi" instead of "ctlr", the codes in suspend and resume func were
not modified correspondly.
Fixes: 530b5affc675 ("spi: fsl-dspi: fix use-after-free in remove path")
Signed-off-by: Zhao Qiang
---
Changes for v2:
- modify commit msg
drivers/spi/spi-fsl-dspi.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c
index 3967afa..1a08c1d 100644
--- a/drivers/spi/spi-fsl-dspi.c
+++ b/drivers/spi/spi-fsl-dspi.c
@@ -1080,12 +1080,11 @@ MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids);
#ifdef CONFIG_PM_SLEEP
static int dspi_suspend(struct device *dev)
{
- struct spi_controller *ctlr = dev_get_drvdata(dev);
- struct fsl_dspi *dspi = spi_controller_get_devdata(ctlr);
+ struct fsl_dspi *dspi = dev_get_drvdata(dev);
if (dspi->irq)
disable_irq(dspi->irq);
- spi_controller_suspend(ctlr);
+ spi_controller_suspend(dspi->ctlr);
clk_disable_unprepare(dspi->clk);
pinctrl_pm_select_sleep_state(dev);
@@ -1095,8 +1094,7 @@ static int dspi_suspend(struct device *dev)
static int dspi_resume(struct device *dev)
{
- struct spi_controller *ctlr = dev_get_drvdata(dev);
- struct fsl_dspi *dspi = spi_controller_get_devdata(ctlr);
+ struct fsl_dspi *dspi = dev_get_drvdata(dev);
int ret;
pinctrl_pm_select_default_state(dev);
@@ -1104,7 +1102,7 @@ static int dspi_resume(struct device *dev)
ret = clk_prepare_enable(dspi->clk);
if (ret)
return ret;
- spi_controller_resume(ctlr);
+ spi_controller_resume(dspi->ctlr);
if (dspi->irq)
enable_irq(dspi->irq);
--
2.7.4
RE: [PATCH] spi: fsl-dspi: fix NULL pointer dereference
On Thu, Oct 30, 2020 at 21:18PM +0800, Vladimir Oltean
wrote:
> -Original Message-
> From: Vladimir Oltean
> Sent: 2020年10月30日 21:18
> To: Qiang Zhao
> Cc: broo...@kernel.org; linux-...@vger.kernel.org;
> linux-kernel@vger.kernel.org
> Subject: Re: [PATCH] spi: fsl-dspi: fix NULL pointer dereference
>
> On Thu, Oct 29, 2020 at 04:40:35PM +0800, Qiang Zhao wrote:
> > From: Zhao Qiang
> >
> > Since commit 530b5affc675 ("spi: fsl-dspi: fix use-after-free in
> > remove path"), this driver causes a kernel oops:
> >
> > [ 64.587431] Unable to handle kernel NULL pointer dereference at
> > virtual address 0020
> > [..]
> > [ 64.756080] Call trace:
> > [ 64.758526] dspi_suspend+0x30/0x78
> > [ 64.762012] platform_pm_suspend+0x28/0x70
> >
> > This is because since this commit, the drivers private data point to
> > "dspi" instead of "ctlr", the codes in suspend and resume func were
> > not modified correspondly.
> >
> > Fixes: 530b5affc675 ("spi: fsl-dspi: fix use-after-free in remove
> > path")
> > Signed-off-by: Zhao Qiang
> > ---
>
> Reviewed-by: Vladimir Oltean
>
> Please resend with Mark's comment. I would prefer that you even remove the
> stack trace completely and make it more obvious in the commit message itself
> that the NULL pointer occurs during suspend/resume.
> Somehow that managed to get obscured in your current version. It is also not
> helpful at all that there already exists a commit titled 'spi:
> fsl-dspi: fix NULL pointer dereference' on this driver. This causes confusion
> for
> backporters. Please provide a unique commit message.
> Thanks.
How about it looks like below:
spi: fsl-dspi: fix wrong pointer in suspend/resume
Since commit 530b5affc675 ("spi: fsl-dspi: fix use-after-free in
remove path"), this driver causes a "NULL pointer dereference"
in dspi_suspend/resume.
This is because since this commit, the drivers private data point to
"dspi" instead of "ctlr", the codes in suspend and resume func were
not modified correspondly.
Best Regards,
Qiang Zhao
RE: [PATCH] spi: fsl-dspi: fix NULL pointer dereference
On Thu, Oct 30, 2020 at 21:02PM, Mark Brown wrote: > -Original Message- > From: Mark Brown > Sent: 2020年10月30日 21:02 > To: Qiang Zhao > Cc: olte...@gmail.com; linux-...@vger.kernel.org; > linux-kernel@vger.kernel.org > Subject: Re: [PATCH] spi: fsl-dspi: fix NULL pointer dereference > > On Thu, Oct 29, 2020 at 04:40:35PM +0800, Qiang Zhao wrote: > > > [ 64.587431] Unable to handle kernel NULL pointer dereference at > > virtual address 0020 > > [..] > > [ 64.756080] Call trace: > > [ 64.758526] dspi_suspend+0x30/0x78 > > [ 64.762012] platform_pm_suspend+0x28/0x70 > > [ 64.766107] dpm_run_callback.isra.19+0x24/0x70 > > [ 64.770635] __device_suspend+0xf4/0x2f0 > > [ 64.774553] dpm_suspend+0xec/0x1e0 > > [ 64.778036] dpm_suspend_start+0x80/0xa0 > > [ 64.781957] suspend_devices_and_enter+0x118/0x4f0 > > [ 64.786743] pm_suspend+0x1e0/0x260 > > [ 64.790227] state_store+0x8c/0x118 > > [ 64.793712] kobj_attr_store+0x18/0x30 > > [ 64.797459] sysfs_kf_write+0x40/0x58 > > [ 64.801118] kernfs_fop_write+0x148/0x240 > > [ 64.805126] vfs_write+0xc0/0x230 > > [ 64.808436] ksys_write+0x6c/0x100 > > [ 64.811833] __arm64_sys_write+0x1c/0x28 > > [ 64.815753] el0_svc_common.constprop.3+0x68/0x170 > > [ 64.820541] do_el0_svc+0x24/0x90 > > [ 64.823853] el0_sync_handler+0x118/0x168 > > [ 64.827858] el0_sync+0x158/0x180 > > Please think hard before including complete backtraces in upstream reports, > they are very large and contain almost no useful information relative to their > size so often obscure the relevant content in your message. If part of the > backtrace is usefully illustrative (it often is for search engines if nothing > else) > then it's usually better to pull out the relevant sections. Ok, will modified in next version. Best Regards, Qiang Zhao
RE: [PATCH] spi: fsl-dspi: fix NULL pointer dereference
On Thu, Oct 29, 2020 at 19:03PM, Vladimir Oltean wrote:
> -Original Message-
> From: Vladimir Oltean
> Sent: 2020年10月29日 19:03
> To: Qiang Zhao
> Cc: broo...@kernel.org; linux-...@vger.kernel.org;
> linux-kernel@vger.kernel.org
> Subject: Re: [PATCH] spi: fsl-dspi: fix NULL pointer dereference
>
> On Thu, Oct 29, 2020 at 04:40:35PM +0800, Qiang Zhao wrote:
> > From: Zhao Qiang
> >
> > Since commit 530b5affc675 ("spi: fsl-dspi: fix use-after-free in
> > remove path"), this driver causes a kernel oops:
> >
> > [ 64.587431] Unable to handle kernel NULL pointer dereference at
> > virtual address 0020
> > [..]
> > [ 64.756080] Call trace:
> > [ 64.758526] dspi_suspend+0x30/0x78
> > [ 64.762012] platform_pm_suspend+0x28/0x70
> > [ 64.766107] dpm_run_callback.isra.19+0x24/0x70
> > [ 64.770635] __device_suspend+0xf4/0x2f0
> > [ 64.774553] dpm_suspend+0xec/0x1e0
> > [ 64.778036] dpm_suspend_start+0x80/0xa0
> > [ 64.781957] suspend_devices_and_enter+0x118/0x4f0
> > [ 64.786743] pm_suspend+0x1e0/0x260
> > [ 64.790227] state_store+0x8c/0x118
> > [ 64.793712] kobj_attr_store+0x18/0x30
> > [ 64.797459] sysfs_kf_write+0x40/0x58
> > [ 64.801118] kernfs_fop_write+0x148/0x240
> > [ 64.805126] vfs_write+0xc0/0x230
> > [ 64.808436] ksys_write+0x6c/0x100
> > [ 64.811833] __arm64_sys_write+0x1c/0x28
> > [ 64.815753] el0_svc_common.constprop.3+0x68/0x170
> > [ 64.820541] do_el0_svc+0x24/0x90
> > [ 64.823853] el0_sync_handler+0x118/0x168
> > [ 64.827858] el0_sync+0x158/0x180
> >
> > This is because since this commit, the drivers private data point to
> > "dspi" instead of "ctlr", the codes in suspend and resume func were
> > not modified correspondly.
> >
> > Fixes: 530b5affc675 ("spi: fsl-dspi: fix use-after-free in remove
> > path")
> > Signed-off-by: Zhao Qiang
> > ---
>
> Please update your tree.
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.c
> om%2Ftorvalds%2Flinux%2Fcommit%2F6e3837668e00fb914ac2b43158ef51b0
> 27ec385cdata=04%7C01%7Cqiang.zhao%40nxp.com%7C50171bf65a5e
> 4f24e0c208d87bfa3fe9%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0
> %7C637395662023835048%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjA
> wMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000sda
> ta=NlmOj1SfvKu2V7nrSYF3lDji25xbP5PeDl1PcwlKyr4%3Dreserved=0
I saw the patch, it just fix the issue when the kernel are booted up.
But there still have the issue when the driver suspend and resume.
Best Regards
Qiang Zhao
[PATCH] spi: fsl-dspi: fix NULL pointer dereference
From: Zhao Qiang
Since commit 530b5affc675 ("spi: fsl-dspi: fix use-after-free in
remove path"), this driver causes a kernel oops:
[ 64.587431] Unable to handle kernel NULL pointer dereference at
virtual address 0020
[..]
[ 64.756080] Call trace:
[ 64.758526] dspi_suspend+0x30/0x78
[ 64.762012] platform_pm_suspend+0x28/0x70
[ 64.766107] dpm_run_callback.isra.19+0x24/0x70
[ 64.770635] __device_suspend+0xf4/0x2f0
[ 64.774553] dpm_suspend+0xec/0x1e0
[ 64.778036] dpm_suspend_start+0x80/0xa0
[ 64.781957] suspend_devices_and_enter+0x118/0x4f0
[ 64.786743] pm_suspend+0x1e0/0x260
[ 64.790227] state_store+0x8c/0x118
[ 64.793712] kobj_attr_store+0x18/0x30
[ 64.797459] sysfs_kf_write+0x40/0x58
[ 64.801118] kernfs_fop_write+0x148/0x240
[ 64.805126] vfs_write+0xc0/0x230
[ 64.808436] ksys_write+0x6c/0x100
[ 64.811833] __arm64_sys_write+0x1c/0x28
[ 64.815753] el0_svc_common.constprop.3+0x68/0x170
[ 64.820541] do_el0_svc+0x24/0x90
[ 64.823853] el0_sync_handler+0x118/0x168
[ 64.827858] el0_sync+0x158/0x180
This is because since this commit, the drivers private data point to
"dspi" instead of "ctlr", the codes in suspend and resume func were
not modified correspondly.
Fixes: 530b5affc675 ("spi: fsl-dspi: fix use-after-free in remove path")
Signed-off-by: Zhao Qiang
---
drivers/spi/spi-fsl-dspi.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c
index 3967afa..1a08c1d 100644
--- a/drivers/spi/spi-fsl-dspi.c
+++ b/drivers/spi/spi-fsl-dspi.c
@@ -1080,12 +1080,11 @@ MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids);
#ifdef CONFIG_PM_SLEEP
static int dspi_suspend(struct device *dev)
{
- struct spi_controller *ctlr = dev_get_drvdata(dev);
- struct fsl_dspi *dspi = spi_controller_get_devdata(ctlr);
+ struct fsl_dspi *dspi = dev_get_drvdata(dev);
if (dspi->irq)
disable_irq(dspi->irq);
- spi_controller_suspend(ctlr);
+ spi_controller_suspend(dspi->ctlr);
clk_disable_unprepare(dspi->clk);
pinctrl_pm_select_sleep_state(dev);
@@ -1095,8 +1094,7 @@ static int dspi_suspend(struct device *dev)
static int dspi_resume(struct device *dev)
{
- struct spi_controller *ctlr = dev_get_drvdata(dev);
- struct fsl_dspi *dspi = spi_controller_get_devdata(ctlr);
+ struct fsl_dspi *dspi = dev_get_drvdata(dev);
int ret;
pinctrl_pm_select_default_state(dev);
@@ -1104,7 +1102,7 @@ static int dspi_resume(struct device *dev)
ret = clk_prepare_enable(dspi->clk);
if (ret)
return ret;
- spi_controller_resume(ctlr);
+ spi_controller_resume(dspi->ctlr);
if (dspi->irq)
enable_irq(dspi->irq);
--
2.7.4
RE: [PATCH 0/2] rtc: pcf2127: only use watchdog when explicitly available
Any update for this patchset? Best Regards Qiang Zhao > -Original Message- > From: Uwe Kleine-König > Sent: 2020年9月24日 18:53 > To: Alexandre Belloni ; Qiang Zhao > ; Bruno Thomsen > Cc: linux-...@vger.kernel.org; a.zu...@towertech.it; > linux-watch...@vger.kernel.org; devicet...@vger.kernel.org; > linux-kernel@vger.kernel.org; robh...@kernel.org; ker...@pengutronix.de; > Wim Van Sebroeck ; Guenter Roeck > > Subject: [PATCH 0/2] rtc: pcf2127: only use watchdog when explicitly available > > Hello, > > now that there are two people stumbling over the pcf2127 driver providing a > non-functional watchdog device, here comes an RFC patch to address this. > > Note this is only compile tested and dt-documentation is still missing. > Still send this series because the cleanup is nice independent of this > discussion > and to have something to argue about. > > Does someone can offer a better name than "has-watchdog", is there a scheme > that could be used already that I'm not aware of? > > Best regards > Uwe > > Uwe Kleine-König (2): > rtc: pcf2127: move watchdog initialisation to a separate function > [RFC] rtc: pcf2127: only use watchdog when explicitly available > > drivers/rtc/rtc-pcf2127.c | 57 ++- > 1 file changed, 32 insertions(+), 25 deletions(-) > > -- > 2.28.0
RE: [Patch v2 1/3] dt-bindings: rtc: pcf2127: Add bindings for nxp,pcf2127
On Thu, Sep 24, 2020 at 15:05AM +, Uwe Kleine-König wrote: > -Original Message- > From: Uwe Kleine-König > Sent: 2020年9月24日 15:05 > To: Qiang Zhao > Cc: Alexandre Belloni ; Wim Van Sebroeck > ; Guenter Roeck ; > linux-watch...@vger.kernel.org; a.zu...@towertech.it; robh...@kernel.org; > linux-...@vger.kernel.org; devicet...@vger.kernel.org; > linux-kernel@vger.kernel.org; ker...@pengutronix.de > Subject: Re: [Patch v2 1/3] dt-bindings: rtc: pcf2127: Add bindings for > nxp,pcf2127 > > Hello, > > On Thu, Sep 24, 2020 at 03:20:33AM +, Qiang Zhao wrote: > > On 21/09/2020 13:48:19+0800, Qiang Zhao wrote: > > > > > -Original Message- > > > From: Alexandre Belloni > > > Sent: 2020年9月23日 17:45 > > > To: Qiang Zhao > > > Cc: Wim Van Sebroeck ; Guenter Roeck > > > ; linux-watch...@vger.kernel.org; > > > a.zu...@towertech.it; robh...@kernel.org; linux-...@vger.kernel.org; > > > devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; Uwe > > > Kleine-König > > > Subject: Re: [Patch v2 1/3] dt-bindings: rtc: pcf2127: Add bindings > > > for > > > nxp,pcf2127 > > > > > > Hi, > > > > > > You forgot to copy the watchdog maintainers, I think such a property > > > should be discussed with them. > > > > > > Note that I'm still convinced this is not a complete solution, see: > > > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flo > > > re.kern > > > > el.org%2Flinux-rtc%2F20200716181816.GF3428%40piout.net%2Fdata= > > > > 02%7C01%7Cqiang.zhao%40nxp.com%7Cb71f79a044b0493d6d4f08d85fa551c > > > > b%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C1%7C637364510931174 > > > > 355sdata=%2BOxrzB8RIuxM9Let5slhfCVmMm6PMNoERDeHC9%2Fdxng > > > %3Dreserved=0 > > haha > > > Yes, you are right, There is not a fundamental solution. > > However it somewhat avoid this situation at least. > > > > And if without this issue, > > is it correct to register a rtc device as watchdog no matter it is used as > watchdog on the board? > > Every time Linux are booted up, watchdog device should be configured to the > right one manually. > > So the patch are useful, even though it is not for the issue. > > > > What should we do to really resolve this issue? > > I still think we need a kernel solution here. I would expect that most > assembled > pcf2127 chips are unable to act as a watchdog (i.e. don't have the RST output > connected to something that resets the machine). > > So my favoured solution would be a positive property like: > > has-watchdog; > > or something similar. In my eyes this is definitely something we want to > specify > in the device tree because it is a relevant hardware property. > I consider it a bug to give a watchdog device to userspace that isn't > functional. > > Best regards > Uwe I strongly agree with you! It should be positive property. However, we couldn't identify which board are using pcf2127 as watchdog, So we are unable to modify the boards' dts to correct (watchdog or not) in this patchset. I noticed that only LS series platforms and imx6 have pcf2127 node, as far as I know, the LS platforms don't use it as watchdog, But I am not sure about imx6 > > -- > Pengutronix e.K. | Uwe Kleine-König > | > Industrial Linux Solutions | https://www.pengutronix.de/ | Best Regards Qiang Zhao
RE: [Patch v2 1/3] dt-bindings: rtc: pcf2127: Add bindings for nxp,pcf2127
On 21/09/2020 13:48:19+0800, Qiang Zhao wrote: > -Original Message- > From: Alexandre Belloni > Sent: 2020年9月23日 17:45 > To: Qiang Zhao > Cc: Wim Van Sebroeck ; Guenter Roeck > ; linux-watch...@vger.kernel.org; > a.zu...@towertech.it; robh...@kernel.org; linux-...@vger.kernel.org; > devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; Uwe Kleine-König > > Subject: Re: [Patch v2 1/3] dt-bindings: rtc: pcf2127: Add bindings for > nxp,pcf2127 > > Hi, > > You forgot to copy the watchdog maintainers, I think such a property should be > discussed with them. > > Note that I'm still convinced this is not a complete solution, see: > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.kern > el.org%2Flinux-rtc%2F20200716181816.GF3428%40piout.net%2Fdata= > 02%7C01%7Cqiang.zhao%40nxp.com%7Cb71f79a044b0493d6d4f08d85fa551c > b%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C1%7C637364510931174 > 355sdata=%2BOxrzB8RIuxM9Let5slhfCVmMm6PMNoERDeHC9%2Fdxng > %3Dreserved=0 > Yes, you are right, There is not a fundamental solution. However it somewhat avoid this situation at least. And if without this issue, is it correct to register a rtc device as watchdog no matter it is used as watchdog on the board? Every time Linux are booted up, watchdog device should be configured to the right one manually. So the patch are useful, even though it is not for the issue. What should we do to really resolve this issue? Best Regards Qiang Zhao
RE: [PATCH] arm64: dts: layerscape: correct watchdog clocks for LS1088A
On Mon, Sep 14, 2020 at 03:52:02PM +0800, Qiang Zhao wrote: > -Original Message- > From: Shawn Guo > Sent: 2020年9月22日 10:18 > To: Qiang Zhao > Cc: robh...@kernel.org; linux-kernel@vger.kernel.org; > devicet...@vger.kernel.org > Subject: Re: [PATCH] arm64: dts: layerscape: correct watchdog clocks for > LS1088A > > On Mon, Sep 14, 2020 at 03:52:02PM +0800, Qiang Zhao wrote: > > From: Zhao Qiang > > > > On LS1088A, watchdog clk are divided by 16, correct it in dts. > > > > Signed-off-by: Zhao Qiang > > It doesn't apply to my imx/dt64 branch. > > Shawn > Have pushed version 2 to rebase. Best Regards Qiang Zhao
[Patch v2] arm64: dts: layerscape: correct watchdog clocks for LS1088A
From: Zhao Qiang
On LS1088A, watchdog clk are divided by 16, correct it in dts.
Signed-off-by: Zhao Qiang
---
Changes for v2:
- rebase
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index c909ad1..80448b4 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -675,56 +675,56 @@
cluster1_core0_watchdog: wdt@c00 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc00 0x0 0x1000>;
- clocks = < 4 3>, < 4 3>;
+ clocks = < 4 15>, < 4 15>;
clock-names = "wdog_clk", "apb_pclk";
};
cluster1_core1_watchdog: wdt@c01 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc01 0x0 0x1000>;
- clocks = < 4 3>, < 4 3>;
+ clocks = < 4 15>, < 4 15>;
clock-names = "wdog_clk", "apb_pclk";
};
cluster1_core2_watchdog: wdt@c02 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc02 0x0 0x1000>;
- clocks = < 4 3>, < 4 3>;
+ clocks = < 4 15>, < 4 15>;
clock-names = "wdog_clk", "apb_pclk";
};
cluster1_core3_watchdog: wdt@c03 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc03 0x0 0x1000>;
- clocks = < 4 3>, < 4 3>;
+ clocks = < 4 15>, < 4 15>;
clock-names = "wdog_clk", "apb_pclk";
};
cluster2_core0_watchdog: wdt@c10 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc10 0x0 0x1000>;
- clocks = < 4 3>, < 4 3>;
+ clocks = < 4 15>, < 4 15>;
clock-names = "wdog_clk", "apb_pclk";
};
cluster2_core1_watchdog: wdt@c11 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc11 0x0 0x1000>;
- clocks = < 4 3>, < 4 3>;
+ clocks = < 4 15>, < 4 15>;
clock-names = "wdog_clk", "apb_pclk";
};
cluster2_core2_watchdog: wdt@c12 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc12 0x0 0x1000>;
- clocks = < 4 3>, < 4 3>;
+ clocks = < 4 15>, < 4 15>;
clock-names = "wdog_clk", "apb_pclk";
};
cluster2_core3_watchdog: wdt@c13 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc13 0x0 0x1000>;
- clocks = < 4 3>, < 4 3>;
+ clocks = < 4 15>, < 4 15>;
clock-names = "wdog_clk", "apb_pclk";
};
--
2.7.4
[Patch v2 2/3] rtc: pcf2127: add "no-watchdog" property
From: Zhao Qiang
Commit 0e735eaae165 ("rtc: pcf2127: add watchdog feature support")
adds watchdog feature for pcf2127, then it will be registered as
a watchdog device even though it is not used as watchdog.
Pcf2127 always be registered as watchdog0(default watchdog device),
even though it is not used as watchdog, meanwhile there is another
real watchdog device registered as watchdog1.
So add "no-watchdog" property, if the node has this property,
driver will not register it as a watchdog device
Signed-off-by: Zhao Qiang
---
drivers/rtc/rtc-pcf2127.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/rtc/rtc-pcf2127.c b/drivers/rtc/rtc-pcf2127.c
index ed63169..b50158a 100644
--- a/drivers/rtc/rtc-pcf2127.c
+++ b/drivers/rtc/rtc-pcf2127.c
@@ -624,9 +624,11 @@ static int pcf2127_probe(struct device *dev, struct regmap
*regmap,
set_bit(WDOG_HW_RUNNING, >wdd.status);
#ifdef CONFIG_WATCHDOG
- ret = devm_watchdog_register_device(dev, >wdd);
- if (ret)
- return ret;
+ if (!of_property_read_bool(dev->of_node, "no-watchdog")) {
+ ret = devm_watchdog_register_device(dev, >wdd);
+ if (ret)
+ return ret;
+ }
#endif /* CONFIG_WATCHDOG */
/*
--
2.7.4
[Patch v2 1/3] dt-bindings: rtc: pcf2127: Add bindings for nxp,pcf2127
From: Zhao Qiang Add bindings for nxp,pcf2127 Signed-off-by: Zhao Qiang --- Changes for v2: - modify the format to yaml - add compitable "nxp,pca2129" .../devicetree/bindings/rtc/nxp,pcf2127.yaml | 41 ++ 1 file changed, 41 insertions(+) create mode 100644 Documentation/devicetree/bindings/rtc/nxp,pcf2127.yaml diff --git a/Documentation/devicetree/bindings/rtc/nxp,pcf2127.yaml b/Documentation/devicetree/bindings/rtc/nxp,pcf2127.yaml new file mode 100644 index 000..226a0b2 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/nxp,pcf2127.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/nxp,pcf2127.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: PCF RTCs + +maintainers: + - Qiang Zhao + +allOf: + - $ref: "rtc.yaml#" + +properties: + compatible: +enum: + - nxp,pcf2127 + - nxp,pcf2129 + - nxp,pca2129 + + reg: +maxItems: 1 + + interrupts: +maxItems: 1 + + no-watchdog: +$ref: /schemas/types.yaml#/definitions/flag +description: + With this property, the device will not registered as a watchdog device. + + start-year: true + +required: + - compatible + - reg + +additionalProperties: false + +... -- 2.7.4
[Patch v2 3/3] arm64: dts: lx2160a: Add "no-watchdog" property to pcf2127
From: Zhao Qiang pcf2127 on lx2160a are not used as watchdog. Signed-off-by: Zhao Qiang --- arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts index 54fe8cd..6181371 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts @@ -153,6 +153,7 @@ reg = <0x51>; // IRQ10_B interrupts = <0 150 0x4>; + no-watchdog; }; }; -- 2.7.4
RE: [PATCH 1/3] dt-bindings: rtc-2127: Add bindings for nxp,rtc-2127.txt
On Fri, Sep 18, 2020 at 03:29, Bruno Thomsen wrote: > -Original Message- > From: Bruno Thomsen > Sent: 2020年9月18日 3:29 > To: Qiang Zhao > Cc: Rob Herring ; a.zu...@towertech.it; > alexandre.bell...@bootlin.com; linux-...@vger.kernel.org; > devicet...@vger.kernel.org; linux-kernel@vger.kernel.org > Subject: Re: [PATCH 1/3] dt-bindings: rtc-2127: Add bindings for > nxp,rtc-2127.txt > > Den man. 14. sep. 2020 kl. 09.08 skrev Qiang Zhao : > > > > On Fri, Sep 11, 2020 at 22:03, Rob Herring wrote: > > > Please help to review as below, if it is ok, I will send the new version > > patch. > Thank you! > > > > diff --git a/Documentation/devicetree/bindings/rtc/nxp,pcf2127.yaml > > b/Documentation/devicetree/bindings/rtc/nxp,pcf2127.yaml > > new file mode 100644 > > index 000..809dd59 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/rtc/nxp,pcf2127.yaml > > @@ -0,0 +1,38 @@ > > +# SPDX-License-Identifier: GPL-2.0 > > +%YAML 1.2 > > +--- > > +$id: > > +https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi > > > +cetree.org%2Fschemas%2Frtc%2Fnxp%2Cpcf2127.yaml%23data=02%7 > C01%7 > > > +Cqiang.zhao%40nxp.com%7C5a271aa3d1ed46ea578108d85b3ff9f6%7C686e > a1d3bc > > > +2b4c6fa92cd99c5c301635%7C0%7C0%7C637359677624002617sdata > =UGZ9B6E > > +xteIMvxc3zvPfr%2FjZVQuPD6DJ6b2kZ%2BOO%2BIA%3Dreserved=0 > > +$schema: > > +https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi > > > +cetree.org%2Fmeta-schemas%2Fcore.yaml%23data=02%7C01%7Cqiang > .zha > > > +o%40nxp.com%7C5a271aa3d1ed46ea578108d85b3ff9f6%7C686ea1d3bc2b4 > c6fa92c > > > +d99c5c301635%7C0%7C0%7C637359677624002617sdata=7P2m9OvIs > FS6Q2By9 > > +DNmK9Oq5Ff6B%2BNSEA4F7otTT8g%3Dreserved=0 > > + > > +title: PCF RTCs > > + > > +maintainers: > > + - Qiang Zhao > > + > > +allOf: > > + - $ref: "rtc.yaml#" > > + > > +properties: > > + compatible: > > +enum: > > + - nxp,pcf2127 > > + - nxp,pcf2129 > > The device driver have 3 compatible strings, "nxp,pca2129" is missing. Thank you for your reminder, I will add in next version. > > /Bruno > > > + > > + reg: > > +maxItems: 1 > > + > > + interrupts: > > +maxItems: 1 > > + > > + no-watchdog: > > +maxItems: 1 > > + > > + start-year: true > > + > > +required: > > + - compatible > > + - reg > > + > > +additionalProperties: false > > + > > +... > > > > > > > > Documentation/devicetree/writing-schema.rst and about 1000 examples > > > in the kernel tree. > > > > > > Rob Best Regards Qiang Zhao
[PATCH 2/2] arm64: dts: layerscape: modify clocks divider to 32 for wdt
From: Zhao Qiang
On LX2088A, wdt's clock are get from clockgen divided by 32,
so modify clocks in device tree.
Signed-off-by: Zhao Qiang
---
arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
index 7016791..de6c751 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
@@ -194,56 +194,56 @@
cluster1_core0_watchdog: wdt@c00 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc00 0x0 0x1000>;
- clocks = < 4 3>, < 4 3>;
+ clocks = < 4 31>, < 4 31>;
clock-names = "apb_pclk", "wdog_clk";
};
cluster1_core1_watchdog: wdt@c01 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc01 0x0 0x1000>;
- clocks = < 4 3>, < 4 3>;
+ clocks = < 4 31>, < 4 31>;
clock-names = "apb_pclk", "wdog_clk";
};
cluster2_core0_watchdog: wdt@c10 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc10 0x0 0x1000>;
- clocks = < 4 3>, < 4 3>;
+ clocks = < 4 31>, < 4 31>;
clock-names = "apb_pclk", "wdog_clk";
};
cluster2_core1_watchdog: wdt@c11 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc11 0x0 0x1000>;
- clocks = < 4 3>, < 4 3>;
+ clocks = < 4 31>, < 4 31>;
clock-names = "apb_pclk", "wdog_clk";
};
cluster3_core0_watchdog: wdt@c20 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc20 0x0 0x1000>;
- clocks = < 4 3>, < 4 3>;
+ clocks = < 4 31>, < 4 31>;
clock-names = "apb_pclk", "wdog_clk";
};
cluster3_core1_watchdog: wdt@c21 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc21 0x0 0x1000>;
- clocks = < 4 3>, < 4 3>;
+ clocks = < 4 31>, < 4 31>;
clock-names = "apb_pclk", "wdog_clk";
};
cluster4_core0_watchdog: wdt@c30 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc30 0x0 0x1000>;
- clocks = < 4 3>, < 4 3>;
+ clocks = < 4 31>, < 4 31>;
clock-names = "apb_pclk", "wdog_clk";
};
cluster4_core1_watchdog: wdt@c31 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc31 0x0 0x1000>;
- clocks = < 4 3>, < 4 3>;
+ clocks = < 4 31>, < 4 31>;
clock-names = "apb_pclk", "wdog_clk";
};
--
2.7.4
[PATCH 1/2] clk: qoriq: modify MAX_PLL_DIV to 32
From: Zhao Qiang
On LS2088A, Watchdog need clk divided by 32,
so modify MAX_PLL_DIV to 32
Signed-off-by: Zhao Qiang
---
drivers/clk/clk-qoriq.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index 5942e98..46101c6 100644
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -31,7 +31,7 @@
#define CGA_PLL4 4 /* only on clockgen-1.0, which lacks CGB */
#define CGB_PLL1 4
#define CGB_PLL2 5
-#define MAX_PLL_DIV16
+#define MAX_PLL_DIV32
struct clockgen_pll_div {
struct clk *clk;
--
2.7.4
RE: [PATCH 1/3] dt-bindings: rtc-2127: Add bindings for nxp,rtc-2127.txt
On Thu, Sep 14, 2020 at 22:36, Rob Herring wrote: > -Original Message- > From: Rob Herring > Sent: 2020年9月14日 22:36 > To: Qiang Zhao > Cc: a.zu...@towertech.it; alexandre.bell...@bootlin.com; > linux-...@vger.kernel.org; devicet...@vger.kernel.org; > linux-kernel@vger.kernel.org > Subject: Re: [PATCH 1/3] dt-bindings: rtc-2127: Add bindings for > nxp,rtc-2127.txt > > > > > > > > > > > Please help to review as below, if it is ok, I will send the new version > > patch. > Thank you! > > > > diff --git a/Documentation/devicetree/bindings/rtc/nxp,pcf2127.yaml > > b/Documentation/devicetree/bindings/rtc/nxp,pcf2127.yaml > > new file mode 100644 > > index 000..809dd59 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/rtc/nxp,pcf2127.yaml > > @@ -0,0 +1,38 @@ > > +# SPDX-License-Identifier: GPL-2.0 > > Dual license new bindings please: > > + > > +title: PCF RTCs > > + > > +maintainers: > > + - Qiang Zhao > > + > > + > > + no-watchdog: > > +maxItems: 1 > > maxItems is for arrays. What's the type here? It should have a description > too. Is it ok as below? no-watchdog: $ref: /schemas/types.yaml#/definitions/flag description: With this property, the device will not registered as a watchdog device. > > > > > > Documentation/devicetree/writing-schema.rst and about 1000 examples > > > in the kernel tree. > > > > > > Rob Best Regards Qiang Zhao
[PATCH] arm64: dts: layerscape: correct watchdog clocks for LS1088A
From: Zhao Qiang
On LS1088A, watchdog clk are divided by 16, correct it in dts.
Signed-off-by: Zhao Qiang
---
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index b0bbe57..2bd0a71 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -712,56 +712,56 @@
cluster1_core0_watchdog: wdt@c00 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc00 0x0 0x1000>;
- clocks = < 4 3>, < 4 3>;
+ clocks = < 4 15>, < 4 15>;
clock-names = "apb_pclk", "wdog_clk";
};
cluster1_core1_watchdog: wdt@c01 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc01 0x0 0x1000>;
- clocks = < 4 3>, < 4 3>;
+ clocks = < 4 15>, < 4 15>;
clock-names = "apb_pclk", "wdog_clk";
};
cluster1_core2_watchdog: wdt@c02 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc02 0x0 0x1000>;
- clocks = < 4 3>, < 4 3>;
+ clocks = < 4 15>, < 4 15>;
clock-names = "apb_pclk", "wdog_clk";
};
cluster1_core3_watchdog: wdt@c03 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc03 0x0 0x1000>;
- clocks = < 4 3>, < 4 3>;
+ clocks = < 4 15>, < 4 15>;
clock-names = "apb_pclk", "wdog_clk";
};
cluster2_core0_watchdog: wdt@c10 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc10 0x0 0x1000>;
- clocks = < 4 3>, < 4 3>;
+ clocks = < 4 15>, < 4 15>;
clock-names = "apb_pclk", "wdog_clk";
};
cluster2_core1_watchdog: wdt@c11 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc11 0x0 0x1000>;
- clocks = < 4 3>, < 4 3>;
+ clocks = < 4 15>, < 4 15>;
clock-names = "apb_pclk", "wdog_clk";
};
cluster2_core2_watchdog: wdt@c12 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc12 0x0 0x1000>;
- clocks = < 4 3>, < 4 3>;
+ clocks = < 4 15>, < 4 15>;
clock-names = "apb_pclk", "wdog_clk";
};
cluster2_core3_watchdog: wdt@c13 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc13 0x0 0x1000>;
- clocks = < 4 3>, < 4 3>;
+ clocks = < 4 15>, < 4 15>;
clock-names = "apb_pclk", "wdog_clk";
};
--
2.7.4
RE: [PATCH 1/3] dt-bindings: rtc-2127: Add bindings for nxp,rtc-2127.txt
On Fri, Sep 11, 2020 at 22:03, Rob Herring wrote: > -Original Message- > From: Rob Herring > Sent: 2020年9月11日 22:03 > To: Qiang Zhao > Cc: a.zu...@towertech.it; alexandre.bell...@bootlin.com; > linux-...@vger.kernel.org; devicet...@vger.kernel.org; > linux-kernel@vger.kernel.org > Subject: Re: [PATCH 1/3] dt-bindings: rtc-2127: Add bindings for > nxp,rtc-2127.txt > > On Wed, Sep 9, 2020 at 9:16 PM Qiang Zhao wrote: > > > > On Thu, Sep 10, 2020 at 04:25AM, Rob Herring wrote: > > > -Original Message- > > > From: Rob Herring > > > Sent: 2020年9月10日 4:25 > > > To: Qiang Zhao > > > Cc: a.zu...@towertech.it; alexandre.bell...@bootlin.com; > > > linux-...@vger.kernel.org; devicet...@vger.kernel.org; > > > linux-kernel@vger.kernel.org > > > Subject: Re: [PATCH 1/3] dt-bindings: rtc-2127: Add bindings for > > > nxp,rtc-2127.txt > > > > > > On Thu, Aug 27, 2020 at 05:14:39PM +0800, Qiang Zhao wrote: > > > > From: Zhao Qiang > > > > Please help to review as below, if it is ok, I will send the new version patch. Thank you! diff --git a/Documentation/devicetree/bindings/rtc/nxp,pcf2127.yaml b/Documentation/devicetree/bindings/rtc/nxp,pcf2127.yaml new file mode 100644 index 000..809dd59 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/nxp,pcf2127.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/nxp,pcf2127.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: PCF RTCs + +maintainers: + - Qiang Zhao + +allOf: + - $ref: "rtc.yaml#" + +properties: + compatible: +enum: + - nxp,pcf2127 + - nxp,pcf2129 + + reg: +maxItems: 1 + + interrupts: +maxItems: 1 + + no-watchdog: +maxItems: 1 + + start-year: true + +required: + - compatible + - reg + +additionalProperties: false + +... > > Documentation/devicetree/writing-schema.rst and about 1000 examples in the > kernel tree. > > Rob
RE: [PATCH 1/3] dt-bindings: rtc-2127: Add bindings for nxp,rtc-2127.txt
On Thu, Sep 10, 2020 at 04:25AM, Rob Herring wrote: > -Original Message- > From: Rob Herring > Sent: 2020年9月10日 4:25 > To: Qiang Zhao > Cc: a.zu...@towertech.it; alexandre.bell...@bootlin.com; > linux-...@vger.kernel.org; devicet...@vger.kernel.org; > linux-kernel@vger.kernel.org > Subject: Re: [PATCH 1/3] dt-bindings: rtc-2127: Add bindings for > nxp,rtc-2127.txt > > On Thu, Aug 27, 2020 at 05:14:39PM +0800, Qiang Zhao wrote: > > From: Zhao Qiang > > > > Add bindings for nxp,rtc-2127 > > > > Signed-off-by: Zhao Qiang > > --- > > Documentation/devicetree/bindings/rtc/nxp,rtc-2127.txt | 18 > ++ > > 1 file changed, 18 insertions(+) > > create mode 100644 > Documentation/devicetree/bindings/rtc/nxp,rtc-2127.txt > > Bindings should be in DT schema format now. Is there any doc description for DT schema format or example So that I can take as a reference. Thank you! Best Regards Qiang Zhao
[PATCH 3/3] arm64: dts: lx2160a: Add "no-watchdog" property to pcf2127
From: Zhao Qiang pcf2127 on lx2160a are not used as watchdog. Signed-off-by: Zhao Qiang --- arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts index 2ec43c6..4d14c91 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts @@ -149,6 +149,7 @@ reg = <0x51>; // IRQ10_B interrupts = <0 150 0x4>; + no-watchdog; }; }; -- 2.7.4
[PATCH 2/3] rtc: pcf2127: add "no-watchdog" property
From: Zhao Qiang
Commit 0e735eaae165 ("rtc: pcf2127: add watchdog feature support")
adds watchdog feature for pcf2127, then it will be registered as
a watchdog device even though it is not used as watchdog.
Pcf2127 always be registered as watchdog0(default watchdog device),
even though it is not used as watchdog, meanwhile there is another
real watchdog device registered as watchdog1.
So add "no-watchdog" property, if the node has this property,
driver will not register it as a watchdog device
Signed-off-by: Zhao Qiang
---
drivers/rtc/rtc-pcf2127.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/rtc/rtc-pcf2127.c b/drivers/rtc/rtc-pcf2127.c
index 02b069c..38d30e2 100644
--- a/drivers/rtc/rtc-pcf2127.c
+++ b/drivers/rtc/rtc-pcf2127.c
@@ -476,9 +476,11 @@ static int pcf2127_probe(struct device *dev, struct regmap
*regmap,
}
#ifdef CONFIG_WATCHDOG
- ret = devm_watchdog_register_device(dev, >wdd);
- if (ret)
- return ret;
+ if (!of_property_read_bool(dev->of_node, "no-watchdog")) {
+ ret = devm_watchdog_register_device(dev, >wdd);
+ if (ret)
+ return ret;
+ }
#endif /* CONFIG_WATCHDOG */
/*
--
2.7.4
[PATCH 1/3] dt-bindings: rtc-2127: Add bindings for nxp,rtc-2127.txt
From: Zhao Qiang
Add bindings for nxp,rtc-2127
Signed-off-by: Zhao Qiang
---
Documentation/devicetree/bindings/rtc/nxp,rtc-2127.txt | 18 ++
1 file changed, 18 insertions(+)
create mode 100644 Documentation/devicetree/bindings/rtc/nxp,rtc-2127.txt
diff --git a/Documentation/devicetree/bindings/rtc/nxp,rtc-2127.txt
b/Documentation/devicetree/bindings/rtc/nxp,rtc-2127.txt
new file mode 100644
index 000..c822e10
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/nxp,rtc-2127.txt
@@ -0,0 +1,18 @@
+NXP PCF2127 SPI Real Time Clock
+
+Required properties:
+- compatible: should be: "nxp,pcf2127"
+ or "nxp,pcf2129"
+- reg: should be the SPI slave chipselect address
+
+Optional properties:
+- no-watchdog: PCF2127 is not used as watchdog
+
+Example:
+
+pcf2127: rtc@51 {
+ compatible = "nxp,pcf2127";
+ reg = <0x51>;
+ interrupts = <0 150 0x4>;
+ no-watchdog;
+};
--
2.7.4
RE: [PATCH] watchdog: sbsa_gwdt: add shutdown hook to driver
On 8/24/20 21:29 AM, Guenter Roeck wrote: > -Original Message- > From: Guenter Roeck On Behalf Of Guenter Roeck > Sent: 2020年8月24日 21:29 > To: Qiang Zhao ; w...@linux-watchdog.org > Cc: linux-watch...@vger.kernel.org; linux-kernel@vger.kernel.org > Subject: Re: [PATCH] watchdog: sbsa_gwdt: add shutdown hook to driver > > On 8/24/20 1:18 AM, Qiang Zhao wrote: > > From: Zhao Qiang > > > > Kexec maybe need more time than timeout of wdt(sbsa) which will reset > > the system. > > So it is necessary to add shutdown hook to disable the wdt when run > > kexec. > > > > Please explain why watchdog_stop_on_reboot() does not work. > Thank you for your comments, it is helpful. I investigate this issue again, found that this watchdog are enabled by uboot, Meanwhile in kernel, it is not the default watchdog, in another words, it is not active in kernel. So watchdog_stop_on_reboot() does not work. This patch is not the right solution for the situation, I will abandon it. Best Regards Qiang Zhao
RE: [PATCH] spi: spi-fsl-dspi: Add ACPI support
On Sat, Aug 22, 2020 at 23:21PM, Vladimir Oltean wrote:
> -Original Message-
> From: Vladimir Oltean
> Sent: 2020年8月22日 23:21
> To: kuldip dwivedi
> Cc: Mark Brown ; linux-...@vger.kernel.org;
> linux-kernel@vger.kernel.org; Qiang Zhao ; Pankaj
> Bansal ; Varun Sethi ; Tanveer
> Alam
> Subject: Re: [PATCH] spi: spi-fsl-dspi: Add ACPI support
>
> On Sat, Aug 22, 2020 at 07:37:25PM +0530, Kuldip Dwivedi wrote:
> > > -Original Message-
> > > From: Mark Brown
> > > Sent: Friday, August 21, 2020 7:37 PM
> > > To: kuldip dwivedi
> > > Cc: linux-...@vger.kernel.org; linux-kernel@vger.kernel.org; Qiang
> > > Zhao ; Pankaj Bansal ;
> > > Varun Sethi ; tanveer
> > >
> > > Subject: Re: [PATCH] spi: spi-fsl-dspi: Add ACPI support
> > >
> > > On Fri, Aug 21, 2020 at 06:40:29PM +0530, kuldip dwivedi wrote:
> > >
> > > > +static const struct acpi_device_id fsl_dspi_acpi_ids[] = {
> > > > + { "NXP0005", .driver_data =
> > (kernel_ulong_t)_data[LS2085A], },
> > > > + {},
> > > > +};
> > > > +MODULE_DEVICE_TABLE(acpi, fsl_dspi_acpi_ids);
> > >
> > > Does NXP know about this ID assignment from their namespace? ACPI
> > > IDs should be namespaced by whoever's assigning the ID to avoid
> > > collisions.
> > Yes, I got HID from NXP only.
> > >
> > > > - ret = of_property_read_u32(np, "spi-num-chipselects",
> > _num);
> > > > + if (is_acpi_node(pdev->dev.fwnode))
> > > > + ret = device_property_read_u32(>dev,
> > > > + "spi-num-chipselects", _num);
> > > > + else
> > > > + ret = of_property_read_u32(np,
> > > > + "spi-num-chipselects", _num);
> > >
> > > The whole point with the device property API is that it works with
> > > both DT and ACPI without needing separate parsing, though in this
> > > case I'm wondering why we'd need to specify this in an ACPI system
> > > at all?
> > Understood. Will take care in v2 PATCH
> > >
>
> IMO there is zero reason for the existence of the "spi-num-chipselects"
> property even for DT. We should deprecate it (start ignoring it in existing
> device
> tree deployments) and populate struct fsl_dspi_devtype_data with that info
> based on SoC compatible string.
>
> > > > - of_property_read_u32(np, "bus-num", _num);
> > > > + if (is_acpi_node(pdev->dev.fwnode)) {
> > > > + ret = device_property_read_u32(>dev,
> > > > + "bus-num",
> > _num);
> > >
> > > This is a bad idea for DT and I can't understand why you'd carry it
> > > over for ACPI - why would an ACPI system ever care about this? It's
> > > Linux internal at the best of times.
> > Will take care in v2 PATCH
>
> Yes, definitely bloatware from the old days. I think this driver needs the
> existing
> device tree bindings rethought a little bit before mindlessly porting them to
> ACPI.
Could you give more details?
Best Regards
Qiang Zhao
RE: [PATCH] spi: spi-fsl-dspi: Add ACPI support
On Mon, Aug 24, 2020 at 19:25, Mark Brown wrote: > -Original Message- > From: Mark Brown > Sent: 2020年8月24日 19:25 > To: Vladimir Oltean > Cc: kuldip dwivedi ; > linux-...@vger.kernel.org; linux-kernel@vger.kernel.org; Qiang Zhao > ; Pankaj Bansal ; Varun Sethi > ; Tanveer Alam > Subject: Re: [PATCH] spi: spi-fsl-dspi: Add ACPI support > > On Sat, Aug 22, 2020 at 06:21:18PM +0300, Vladimir Oltean wrote: > > On Sat, Aug 22, 2020 at 07:37:25PM +0530, Kuldip Dwivedi wrote: > > > > > The whole point with the device property API is that it works with > > > > both DT and ACPI without needing separate parsing, though in this > > > > case I'm wondering why we'd need to specify this in an ACPI system > > > > at all? > > > > Understood. Will take care in v2 PATCH > > > IMO there is zero reason for the existence of the "spi-num-chipselects" > > property even for DT. We should deprecate it (start ignoring it in > > existing device tree deployments) and populate struct > > fsl_dspi_devtype_data with that info based on SoC compatible string. > > Yes, it's a legacy from bad board file conversions and shouldn't be used at > all. I saw a lot of driver assign spi_controller -> num_chipselect directly, should we do like that? BR Qiang Zhao
[PATCH] watchdog: sbsa_gwdt: add shutdown hook to driver
From: Zhao Qiang
Kexec maybe need more time than timeout of wdt(sbsa)
which will reset the system.
So it is necessary to add shutdown hook to disable the
wdt when run kexec.
Signed-off-by: Zhao Qiang
---
drivers/watchdog/sbsa_gwdt.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/watchdog/sbsa_gwdt.c b/drivers/watchdog/sbsa_gwdt.c
index f0f1e3b..bbcd04d 100644
--- a/drivers/watchdog/sbsa_gwdt.c
+++ b/drivers/watchdog/sbsa_gwdt.c
@@ -313,6 +313,14 @@ static int sbsa_gwdt_probe(struct platform_device *pdev)
return 0;
}
+static void sbsa_gwdt_shutdown(struct platform_device *pdev)
+{
+ struct sbsa_gwdt *gwdt;
+
+ gwdt = platform_get_drvdata(pdev);
+ sbsa_gwdt_stop(>wdd);
+}
+
/* Disable watchdog if it is active during suspend */
static int __maybe_unused sbsa_gwdt_suspend(struct device *dev)
{
@@ -357,6 +365,7 @@ static struct platform_driver sbsa_gwdt_driver = {
.pm = _gwdt_pm_ops,
.of_match_table = sbsa_gwdt_of_match,
},
+ .shutdown = sbsa_gwdt_shutdown,
.probe = sbsa_gwdt_probe,
.id_table = sbsa_gwdt_pdev_match,
};
--
2.7.4
RE: [RESEND PATCH 1/2] arm64: dts: lx2160a: add dspi controller DT nodes
On Sat, July 11, 2020 at 22:23PM +0800, Shawn Guo wrote:
> -Original Message-
> From: Shawn Guo
> Sent: 2020年7月11日 22:23
> To: Qiang Zhao
> Cc: devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; Leo Li
> ; Chuanhua Han
> Subject: Re: [RESEND PATCH 1/2] arm64: dts: lx2160a: add dspi controller DT
> nodes
>
> On Mon, Jun 22, 2020 at 04:31:08PM +0800, Qiang Zhao wrote:
> > From: Chuanhua Han
> >
> > Add the dspi support on lx2160
> >
> > Signed-off-by: Chuanhua Han
> > Signed-off-by: Bao Xiaowei
> > Signed-off-by: Hou Zhiqiang
> > Signed-off-by: Zhao Qiang
>
> When you resend patches, please state why. Should I drop the patches I just
> applied and pick up this version instead?
>
Sorry for that, I resend just because I forgot to add myself in cc list.
>
> > ---
> > arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 39
> > ++
> > 1 file changed, 39 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> > b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> > index abaeb58..f56172f 100644
> > --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> > @@ -777,6 +777,45 @@
> > status = "disabled";
> > };
> >
> > + dspi0: spi@210 {
> > + compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <0x0 0x210 0x0 0x1>;
> > + interrupts = ;
> > + clocks = < 4 7>;
> > + clock-names = "dspi";
> > + spi-num-chipselects = <5>;
> > + bus-num = <0>;
> > + status = "disabled";
> > + };
> > +
> > + dspi1: spi@211 {
> > + compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <0x0 0x211 0x0 0x1>;
> > + interrupts = ;
> > + clocks = < 4 7>;
> > + clock-names = "dspi";
> > + spi-num-chipselects = <5>;
> > + bus-num = <1>;
> > + status = "disabled";
> > + };
> > +
> > + dspi2: spi@212 {
> > + compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <0x0 0x212 0x0 0x1>;
> > + interrupts = ;
> > + clocks = < 4 7>;
> > + clock-names = "dspi";
> > + spi-num-chipselects = <5>;
> > + bus-num = <2>;
> > + status = "disabled";
> > + };
> > +
> > esdhc0: esdhc@214 {
> > compatible = "fsl,esdhc";
> > reg = <0x0 0x214 0x0 0x1>;
> > --
> > 2.7.4
> >
Best Regards
Qiang Zhao
[Patch V2] arm64: dts: ls1028a: Add DSPI flash nodes for LS1028a-qds
From: Xiaowei Bao
Add the DSPI flash nodes into fsl-ls1028a-qds.dts
Signed-off-by: Xiaowei Bao
Signed-off-by: Zhao Qiang
---
Changes for v2
- correct commit msg
arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts | 85 +++
1 file changed, 85 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
index dd69c5b..e4f00c2 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
@@ -107,6 +107,91 @@
};
};
+ {
+ bus-num = <0>;
+ status = "okay";
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-cpol;
+ spi-cpha;
+ reg = <0>;
+ spi-max-frequency = <1000>;
+ };
+
+ flash@1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-cpol;
+ spi-cpha;
+ reg = <1>;
+ spi-max-frequency = <1000>;
+ };
+
+ flash@2 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-cpol;
+ spi-cpha;
+ reg = <2>;
+ spi-max-frequency = <1000>;
+ };
+};
+
+ {
+ bus-num = <1>;
+ status = "okay";
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-cpol;
+ spi-cpha;
+ reg = <0>;
+ spi-max-frequency = <1000>;
+ };
+
+ flash@1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-cpol;
+ spi-cpha;
+ reg = <1>;
+ spi-max-frequency = <1000>;
+ };
+
+ flash@2 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-cpol;
+ spi-cpha;
+ reg = <2>;
+ spi-max-frequency = <1000>;
+ };
+};
+
+ {
+ bus-num = <2>;
+ status = "okay";
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-cpol;
+ spi-cpha;
+ reg = <0>;
+ spi-max-frequency = <1000>;
+ };
+};
+
{
status = "okay";
};
--
2.7.4
RE: [RESEND PATCH] arm64: dts: ls1028a: Add DSPI nodes
On 2020/6/24, Leo Li wrote:
> -Original Message-
> From: Leo Li
> Sent: 2020年6月24日 7:12
> To: Qiang Zhao ; shawn...@kernel.org
> Cc: devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; Qiang Zhao
> ; Xiaowei Bao
> Subject: RE: [RESEND PATCH] arm64: dts: ls1028a: Add DSPI nodes
>
>
>
> > -Original Message-
> > From: Qiang Zhao
> > Sent: Monday, June 22, 2020 3:29 AM
> > To: shawn...@kernel.org
> > Cc: devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; Leo Li
> > ; Qiang Zhao ; Xiaowei Bao
> >
> > Subject: [RESEND PATCH] arm64: dts: ls1028a: Add DSPI nodes
>
> This patch is actually defining dspi flash nodes for LS1028a-qds board instead
> of adding dspi nodes for the soc.
Thank you! Will correct next version.
>
> >
> > From: Xiaowei Bao
> >
> > Add the DSPI nodes for ls1028a.
> >
> > Signed-off-by: Xiaowei Bao
> > Signed-off-by: Zhao Qiang
> > ---
> > arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts | 85
> > +++
> > 1 file changed, 85 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> > b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> > index dd69c5b..e4f00c2 100644
> > --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> > @@ -107,6 +107,91 @@
> > };
> > };
> >
> > + {
> > + bus-num = <0>;
> > + status = "okay";
> > +
> > + flash@0 {
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + compatible = "jedec,spi-nor";
> > + spi-cpol;
> > + spi-cpha;
> > + reg = <0>;
> > + spi-max-frequency = <1000>;
> > + };
> > +
> > + flash@1 {
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + compatible = "jedec,spi-nor";
> > + spi-cpol;
> > + spi-cpha;
> > + reg = <1>;
> > + spi-max-frequency = <1000>;
> > + };
> > +
> > + flash@2 {
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + compatible = "jedec,spi-nor";
> > + spi-cpol;
> > + spi-cpha;
> > + reg = <2>;
> > + spi-max-frequency = <1000>;
> > + };
> > +};
> > +
> > + {
> > + bus-num = <1>;
> > + status = "okay";
> > +
> > + flash@0 {
> > + #address-cells = <1>;
> > + #size-cells = <1>;
>
> These probably are not needed when no sub nodes are defined.
>
> > + compatible = "jedec,spi-nor";
> > + spi-cpol;
> > + spi-cpha;
> > + reg = <0>;
> > + spi-max-frequency = <1000>;
> > + };
> > +
> > + flash@1 {
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + compatible = "jedec,spi-nor";
> > + spi-cpol;
> > + spi-cpha;
> > + reg = <1>;
> > + spi-max-frequency = <1000>;
> > + };
> > +
> > + flash@2 {
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + compatible = "jedec,spi-nor";
> > + spi-cpol;
> > + spi-cpha;
> > + reg = <2>;
> > + spi-max-frequency = <1000>;
> > + };
> > +};
> > +
> > + {
> > + bus-num = <2>;
> > + status = "okay";
> > +
> > + flash@0 {
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + compatible = "jedec,spi-nor";
> > + spi-cpol;
> > + spi-cpha;
> > + reg = <0>;
> > + spi-max-frequency = <1000>;
> > + };
> > +};
> > +
> > {
> > status = "okay";
> > };
> > --
> > 2.7.4
Best Regards
Qiang Zhao
[RESEND PATCH 1/2] arm64: dts: lx2160a: add dspi controller DT nodes
From: Chuanhua Han
Add the dspi support on lx2160
Signed-off-by: Chuanhua Han
Signed-off-by: Bao Xiaowei
Signed-off-by: Hou Zhiqiang
Signed-off-by: Zhao Qiang
---
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 39 ++
1 file changed, 39 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index abaeb58..f56172f 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -777,6 +777,45 @@
status = "disabled";
};
+ dspi0: spi@210 {
+ compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x210 0x0 0x1>;
+ interrupts = ;
+ clocks = < 4 7>;
+ clock-names = "dspi";
+ spi-num-chipselects = <5>;
+ bus-num = <0>;
+ status = "disabled";
+ };
+
+ dspi1: spi@211 {
+ compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x211 0x0 0x1>;
+ interrupts = ;
+ clocks = < 4 7>;
+ clock-names = "dspi";
+ spi-num-chipselects = <5>;
+ bus-num = <1>;
+ status = "disabled";
+ };
+
+ dspi2: spi@212 {
+ compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x212 0x0 0x1>;
+ interrupts = ;
+ clocks = < 4 7>;
+ clock-names = "dspi";
+ spi-num-chipselects = <5>;
+ bus-num = <2>;
+ status = "disabled";
+ };
+
esdhc0: esdhc@214 {
compatible = "fsl,esdhc";
reg = <0x0 0x214 0x0 0x1>;
--
2.7.4
[RESEND PATCH 2/2] arm64: dts: lx2160a: add DT node for all DSPI controller
From: Chuanhua Han
Add device tree node for first flash (CS0) connected
to all dspi controller.
Signed-off-by: Chuanhua Han
Signed-off-by: Wasim Khan
Signed-off-by: Zhao Qiang
---
arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts | 36 +++
1 file changed, 36 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
index 3b88e1e..2d1fe6c 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
@@ -35,6 +35,42 @@
status = "okay";
};
+ {
+ status = "okay";
+
+ dflash0: flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <100>;
+ };
+};
+
+ {
+ status = "okay";
+
+ dflash1: flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <100>;
+ };
+};
+
+ {
+ status = "okay";
+
+ dflash2: flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <100>;
+ };
+};
+
{
status = "okay";
};
--
2.7.4
[RESEND PATCH] arm64: dts: ls1028a: Add DSPI nodes
From: Xiaowei Bao
Add the DSPI nodes for ls1028a.
Signed-off-by: Xiaowei Bao
Signed-off-by: Zhao Qiang
---
arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts | 85 +++
1 file changed, 85 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
index dd69c5b..e4f00c2 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
@@ -107,6 +107,91 @@
};
};
+ {
+ bus-num = <0>;
+ status = "okay";
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-cpol;
+ spi-cpha;
+ reg = <0>;
+ spi-max-frequency = <1000>;
+ };
+
+ flash@1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-cpol;
+ spi-cpha;
+ reg = <1>;
+ spi-max-frequency = <1000>;
+ };
+
+ flash@2 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-cpol;
+ spi-cpha;
+ reg = <2>;
+ spi-max-frequency = <1000>;
+ };
+};
+
+ {
+ bus-num = <1>;
+ status = "okay";
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-cpol;
+ spi-cpha;
+ reg = <0>;
+ spi-max-frequency = <1000>;
+ };
+
+ flash@1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-cpol;
+ spi-cpha;
+ reg = <1>;
+ spi-max-frequency = <1000>;
+ };
+
+ flash@2 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-cpol;
+ spi-cpha;
+ reg = <2>;
+ spi-max-frequency = <1000>;
+ };
+};
+
+ {
+ bus-num = <2>;
+ status = "okay";
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-cpol;
+ spi-cpha;
+ reg = <0>;
+ spi-max-frequency = <1000>;
+ };
+};
+
{
status = "okay";
};
--
2.7.4
[PATCH] arm64: dts: ls1028a: Add DSPI nodes
From: Xiaowei Bao
Add the DSPI nodes for ls1028a.
Signed-off-by: Xiaowei Bao
Signed-off-by: Zhao Qiang
---
arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts | 85 +++
1 file changed, 85 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
index dd69c5b..e4f00c2 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
@@ -107,6 +107,91 @@
};
};
+ {
+ bus-num = <0>;
+ status = "okay";
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-cpol;
+ spi-cpha;
+ reg = <0>;
+ spi-max-frequency = <1000>;
+ };
+
+ flash@1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-cpol;
+ spi-cpha;
+ reg = <1>;
+ spi-max-frequency = <1000>;
+ };
+
+ flash@2 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-cpol;
+ spi-cpha;
+ reg = <2>;
+ spi-max-frequency = <1000>;
+ };
+};
+
+ {
+ bus-num = <1>;
+ status = "okay";
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-cpol;
+ spi-cpha;
+ reg = <0>;
+ spi-max-frequency = <1000>;
+ };
+
+ flash@1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-cpol;
+ spi-cpha;
+ reg = <1>;
+ spi-max-frequency = <1000>;
+ };
+
+ flash@2 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-cpol;
+ spi-cpha;
+ reg = <2>;
+ spi-max-frequency = <1000>;
+ };
+};
+
+ {
+ bus-num = <2>;
+ status = "okay";
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-cpol;
+ spi-cpha;
+ reg = <0>;
+ spi-max-frequency = <1000>;
+ };
+};
+
{
status = "okay";
};
--
2.7.4
[PATCH 1/2] arm64: dts: lx2160a: add dspi controller DT nodes
From: Chuanhua Han
Add the dspi support on lx2160
Signed-off-by: Chuanhua Han
Signed-off-by: Bao Xiaowei
Signed-off-by: Hou Zhiqiang
Signed-off-by: Zhao Qiang
---
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 39 ++
1 file changed, 39 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index abaeb58..f56172f 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -777,6 +777,45 @@
status = "disabled";
};
+ dspi0: spi@210 {
+ compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x210 0x0 0x1>;
+ interrupts = ;
+ clocks = < 4 7>;
+ clock-names = "dspi";
+ spi-num-chipselects = <5>;
+ bus-num = <0>;
+ status = "disabled";
+ };
+
+ dspi1: spi@211 {
+ compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x211 0x0 0x1>;
+ interrupts = ;
+ clocks = < 4 7>;
+ clock-names = "dspi";
+ spi-num-chipselects = <5>;
+ bus-num = <1>;
+ status = "disabled";
+ };
+
+ dspi2: spi@212 {
+ compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x212 0x0 0x1>;
+ interrupts = ;
+ clocks = < 4 7>;
+ clock-names = "dspi";
+ spi-num-chipselects = <5>;
+ bus-num = <2>;
+ status = "disabled";
+ };
+
esdhc0: esdhc@214 {
compatible = "fsl,esdhc";
reg = <0x0 0x214 0x0 0x1>;
--
2.7.4
[PATCH 2/2] arm64: dts: lx2160a: add DT node for all DSPI controller
From: Chuanhua Han
Add device tree node for first flash (CS0) connected
to all dspi controller.
Signed-off-by: Chuanhua Han
Signed-off-by: Wasim Khan
Signed-off-by: Zhao Qiang
---
arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts | 36 +++
1 file changed, 36 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
index 3b88e1e..2d1fe6c 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
@@ -35,6 +35,42 @@
status = "okay";
};
+ {
+ status = "okay";
+
+ dflash0: flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <100>;
+ };
+};
+
+ {
+ status = "okay";
+
+ dflash1: flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <100>;
+ };
+};
+
+ {
+ status = "okay";
+
+ dflash2: flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <100>;
+ };
+};
+
{
status = "okay";
};
--
2.7.4
RE: [PATCH] soc: fsl: qe: Replace one-element array and use struct_size() helper
On Wed, May 23, 2020 at 5:22 PM Li Yang
> -Original Message-
> From: Li Yang
> Sent: 2020年5月23日 5:22
> To: Kees Cook
> Cc: Gustavo A. R. Silva ; Qiang Zhao
> ; linuxppc-dev ;
> moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
> ; lkml ;
> Gustavo A. R. Silva
> Subject: Re: [PATCH] soc: fsl: qe: Replace one-element array and use
> struct_size() helper
>
> On Wed, May 20, 2020 at 10:24 PM Kees Cook
> wrote:
> >
> > On Wed, May 20, 2020 at 06:52:21PM -0500, Li Yang wrote:
> > > On Mon, May 18, 2020 at 5:57 PM Kees Cook
> wrote:
> > > > Hm, looking at this code, I see a few other things that need to be
> > > > fixed:
> > > >
> > > > 1) drivers/tty/serial/ucc_uart.c does not do a be32_to_cpu() conversion
> > > >on the length test (understandably, a little-endian system has never
> run
> > > >this code since it's ppc specific), but it's still wrong:
> > > >
> > > > if (firmware->header.length != fw->size) {
> > > >
> > > >compare to the firmware loader:
> > > >
> > > > length = be32_to_cpu(hdr->length);
> > > >
> > > > 2) drivers/soc/fsl/qe/qe.c does not perform bounds checking on the
> > > >per-microcode offsets, so the uploader might send data outside the
> > > >firmware buffer. Perhaps:
> > >
> > > We do validate the CRC for each microcode, it is unlikely the CRC
> > > check can pass if the offset or length is not correct. But you are
> > > probably right that it will be safer to check the boundary and fail
> >
> > Right, but a malicious firmware file could still match CRC but trick
> > the kernel code.
> >
> > > quicker before we actually start the CRC check. Will you come up
> > > with a formal patch or you want us to deal with it?
> >
> > It sounds like Gustavo will be sending one, though I don't think
> > either of us have the hardware to test it with, so if you could do
> > that part, that would be great! :)
>
> That will be great. I think Zhao Qiang can help with the testing part.
>
Now the firmware are loaded in uboot, and kernel will do nothing for it.
So testing on it maybe need some extra codes both in driver and dts.
In the meanwhile, I am so busy on some high priority work that maybe test work
could not be done in time.
Once I am free, I will do it.
Best Regards
Qiang Zhao
[PATCH v3 1/2] arm64: dts: add qe node to ls1043ardb
From: Zhao Qiang
Add qe node to fsl-ls1043a.dtsi and fsl-ls1043a-rdb.dts
Signed-off-by: Zhao Qiang
---
v2:
- add commit msg and drop a new blank line
v3:
- Keep labeling node sort alphabetically
- remove unused device_type
- use GIC_SPI and IRQ_TYPE_LEVEL_HIGH
- use "arm64: dts:" format for subject
arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 16 ++
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi| 65 +++
2 files changed, 81 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
index dde50c8..44d9343 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
@@ -176,3 +176,19 @@
};
};
};
+
+ {
+ ucc_hdlc: ucc@2000 {
+ compatible = "fsl,ucc-hdlc";
+ rx-clock-name = "clk8";
+ tx-clock-name = "clk9";
+ fsl,rx-sync-clock = "rsync_pin";
+ fsl,tx-sync-clock = "tsync_pin";
+ fsl,tx-timeslot-mask = <0xfffe>;
+ fsl,rx-timeslot-mask = <0xfffe>;
+ fsl,tdm-framer-type = "e1";
+ fsl,tdm-id = <0>;
+ fsl,siram-entry-id = <0>;
+ fsl,tdm-interface;
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index c084c7a4..3b641bd 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -525,6 +525,71 @@
#interrupt-cells = <2>;
};
+ uqe: uqe@240 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,qe", "simple-bus";
+ ranges = <0x0 0x0 0x240 0x4>;
+ reg = <0x0 0x240 0x0 0x480>;
+ brg-frequency = <1>;
+ bus-frequency = <2>;
+ fsl,qe-num-riscs = <1>;
+ fsl,qe-num-snums = <28>;
+
+ qeic: qeic@80 {
+ compatible = "fsl,qe-ic";
+ reg = <0x80 0x80>;
+ #address-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupts = ,
+;
+ };
+
+ si1: si@700 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,ls1043-qe-si",
+ "fsl,t1040-qe-si";
+ reg = <0x700 0x80>;
+ };
+
+ siram1: siram@1000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,ls1043-qe-siram",
+ "fsl,t1040-qe-siram";
+ reg = <0x1000 0x800>;
+ };
+
+ ucc@2000 {
+ cell-index = <1>;
+ reg = <0x2000 0x200>;
+ interrupts = <32>;
+ interrupt-parent = <>;
+ };
+
+ ucc@2200 {
+ cell-index = <3>;
+ reg = <0x2200 0x200>;
+ interrupts = <34>;
+ interrupt-parent = <>;
+ };
+
+ muram@1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,qe-muram", "fsl,cpm-muram";
+ ranges = <0x0 0x1 0x6000>;
+
+ data-only@0 {
+ compatible = "fsl,qe-muram-data",
+ "fsl,cpm-muram-data";
+ reg = <0x0 0x6000>;
+ };
+ };
+ };
+
lpuart0: serial@295 {
compatible = "fsl,ls1021a-lpuart";
reg = <0x0 0x295 0x0 0x1000>;
--
2.7.4
[PATCH v3 2/2] arm64: dts: Add ds26522 node to dts to ls1043ardb
From: Zhao Qiang
Add ds26522 node to fsl-ls1043a-rdb.dts
Signed-off-by: Zhao Qiang
---
v3:
- use "arm64: dts:" format for subject
arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
index 44d9343..1cb265f 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
@@ -94,6 +94,22 @@
reg = <0>;
spi-max-frequency = <100>; /* input clock */
};
+
+ slic@2 {
+ compatible = "maxim,ds26522";
+ reg = <2>;
+ spi-max-frequency = <200>;
+ fsl,spi-cs-sck-delay = <100>;
+ fsl,spi-sck-cs-delay = <50>;
+ };
+
+ slic@3 {
+ compatible = "maxim,ds26522";
+ reg = <3>;
+ spi-max-frequency = <200>;
+ fsl,spi-cs-sck-delay = <100>;
+ fsl,spi-sck-cs-delay = <50>;
+ };
};
{
--
2.7.4
RE: [PATCH] soc: fsl: qe: Replace one-element array and use struct_size() helper
On 2020/5/19 6:19, Gustavo A. R. Silva wrote:
> -Original Message-
> From: Gustavo A. R. Silva
> Sent: 2020年5月19日 6:19
> To: Qiang Zhao ; Leo Li
> Cc: linuxppc-...@lists.ozlabs.org; linux-arm-ker...@lists.infradead.org;
> linux-kernel@vger.kernel.org; Gustavo A. R. Silva ;
> Kees Cook
> Subject: [PATCH] soc: fsl: qe: Replace one-element array and use struct_size()
> helper
>
> The current codebase makes use of one-element arrays in the following
> form:
>
> struct something {
> int length;
> u8 data[1];
> };
>
> struct something *instance;
>
> instance = kmalloc(sizeof(*instance) + size, GFP_KERNEL);
> instance->length = size;
> memcpy(instance->data, source, size);
>
> but the preferred mechanism to declare variable-length types such as these
> ones is a flexible array member[1][2], introduced in C99:
>
> struct foo {
> int stuff;
> struct boo array[];
> };
>
> By making use of the mechanism above, we will get a compiler warning in case
> the flexible array does not occur last in the structure, which will help us
> prevent
> some kind of undefined behavior bugs from being inadvertently introduced[3]
> to the codebase from now on. So, replace the one-element array with a
> flexible-array member.
>
> Also, make use of the new struct_size() helper to properly calculate the size
> of
> struct qe_firmware.
>
> This issue was found with the help of Coccinelle and, audited and fixed
> _manually_.
>
> [1]
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgcc.gnu.
> org%2Fonlinedocs%2Fgcc%2FZero-Length.htmldata=02%7C01%7Cqiang.
> zhao%40nxp.com%7Cb058bcb9af134df8446808d7fb78cfa9%7C686ea1d3bc2b
> 4c6fa92cd99c5c301635%7C0%7C0%7C637254368610203908sdata=70
> a6VBg3oWQf9a5KICuCEuIj6gw57NKYhNv2JL8JdDY%3Dreserved=0
> [2]
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.c
> om%2FKSPP%2Flinux%2Fissues%2F21data=02%7C01%7Cqiang.zhao%40
> nxp.com%7Cb058bcb9af134df8446808d7fb78cfa9%7C686ea1d3bc2b4c6fa92c
> d99c5c301635%7C0%7C0%7C637254368610213901sdata=kVyNBYHbm
> a5jCO9pbkoHMetHEYGvWDq6Xw%2BBeC7uHII%3Dreserved=0
> [3] commit 76497732932f ("cxgb3/l2t: Fix undefined behaviour")
>
> Signed-off-by: Gustavo A. R. Silva
> ---
> drivers/soc/fsl/qe/qe.c | 4 ++--
> include/soc/fsl/qe/qe.h | 2 +-
> 2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c index
> 447146861c2c1..2df20d6f85fa4 100644
> --- a/drivers/soc/fsl/qe/qe.c
> +++ b/drivers/soc/fsl/qe/qe.c
> @@ -448,7 +448,7 @@ int qe_upload_firmware(const struct qe_firmware
> *firmware)
> unsigned int i;
> unsigned int j;
> u32 crc;
> - size_t calc_size = sizeof(struct qe_firmware);
> + size_t calc_size;
> size_t length;
> const struct qe_header *hdr;
>
> @@ -480,7 +480,7 @@ int qe_upload_firmware(const struct qe_firmware
> *firmware)
> }
>
> /* Validate the length and check if there's a CRC */
> - calc_size += (firmware->count - 1) * sizeof(struct qe_microcode);
> + calc_size = struct_size(firmware, microcode, firmware->count);
>
> for (i = 0; i < firmware->count; i++)
> /*
> diff --git a/include/soc/fsl/qe/qe.h b/include/soc/fsl/qe/qe.h index
> e282ac01ec081..3feddfec9f87d 100644
> --- a/include/soc/fsl/qe/qe.h
> +++ b/include/soc/fsl/qe/qe.h
> @@ -307,7 +307,7 @@ struct qe_firmware {
> u8 revision;/* The microcode version revision */
> u8 padding; /* Reserved, for alignment */
> u8 reserved[4]; /* Reserved, for future expansion */
> - } __attribute__ ((packed)) microcode[1];
> + } __packed microcode[];
> /* All microcode binaries should be located here */
> /* CRC32 should be located here, after the microcode binaries */ }
> __attribute__ ((packed));
> --
> 2.26.2
[>]
Reviewed-by: Qiang Zhao
Best Regards
Qiang Zhao
RE: [patch v2 1/2] ls1043ardb: add qe node to ls1043ardb
On Wed, Apr 29, 2020 at 04:20:51PM +0800, Shawn Guo wrote:
> -Original Message-
> From: Shawn Guo
> Sent: 2020年5月17日 22:10
> To: Qiang Zhao
> Cc: Leo Li ; devicet...@vger.kernel.org;
> linux-kernel@vger.kernel.org
> Subject: Re: [patch v2 1/2] ls1043ardb: add qe node to ls1043ardb
>
> On Wed, Apr 29, 2020 at 04:20:51PM +0800, Qiang Zhao wrote:
> > From: Zhao Qiang
> >
> > Add qe node to fsl-ls1043a.dtsi and fsl-ls1043a-rdb.dts
> >
> > Signed-off-by: Zhao Qiang
>
> Subject prefix should be like 'arm64: dts: ...'
>
>
> > ---
> > v2:
> > - add commit msg and drop a new blank line
> >
> > arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 16 ++
> > arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi| 65
> +++
> > 2 files changed, 81 insertions(+)
> >
> > + compatible = "fsl,qe", "simple-bus";
> > + ranges = <0x0 0x0 0x240 0x4>;
> > + reg = <0x0 0x240 0x0 0x480>;
> > + brg-frequency = <1>;
> > + bus-frequency = <2>;
> > + fsl,qe-num-riscs = <1>;
> > + fsl,qe-num-snums = <28>;
> > +
> > + qeic: qeic@80 {
> > + compatible = "fsl,qe-ic";
> > + reg = <0x80 0x80>;
> > + #address-cells = <0>;
> > + interrupt-controller;
> > + #interrupt-cells = <1>;
> > + interrupts = <0 77 0x04 0 77 0x04>;
>
> Two identical interrupts?
Thank you for comments.
On some boards for QE, There are two different interrupts.
And On others, there is only one interrupt.
In order to make it compatible, QE interrupts used to be wrote like this.
The driver also handle the situation like this.
Best Regards
Qiang Zhao
[patch v2 1/2] ls1043ardb: add qe node to ls1043ardb
From: Zhao Qiang
Add qe node to fsl-ls1043a.dtsi and fsl-ls1043a-rdb.dts
Signed-off-by: Zhao Qiang
---
v2:
- add commit msg and drop a new blank line
arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 16 ++
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi| 65 +++
2 files changed, 81 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
index 4223a23..96e87ba 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
@@ -96,6 +96,22 @@
};
};
+ {
+ ucc_hdlc: ucc@2000 {
+ compatible = "fsl,ucc-hdlc";
+ rx-clock-name = "clk8";
+ tx-clock-name = "clk9";
+ fsl,rx-sync-clock = "rsync_pin";
+ fsl,tx-sync-clock = "tsync_pin";
+ fsl,tx-timeslot-mask = <0xfffe>;
+ fsl,rx-timeslot-mask = <0xfffe>;
+ fsl,tdm-framer-type = "e1";
+ fsl,tdm-id = <0>;
+ fsl,siram-entry-id = <0>;
+ fsl,tdm-interface;
+ };
+};
+
{
status = "okay";
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index c084c7a4..674e671 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -525,6 +525,71 @@
#interrupt-cells = <2>;
};
+ uqe: uqe@240 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "qe";
+ compatible = "fsl,qe", "simple-bus";
+ ranges = <0x0 0x0 0x240 0x4>;
+ reg = <0x0 0x240 0x0 0x480>;
+ brg-frequency = <1>;
+ bus-frequency = <2>;
+ fsl,qe-num-riscs = <1>;
+ fsl,qe-num-snums = <28>;
+
+ qeic: qeic@80 {
+ compatible = "fsl,qe-ic";
+ reg = <0x80 0x80>;
+ #address-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupts = <0 77 0x04 0 77 0x04>;
+ };
+
+ si1: si@700 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,ls1043-qe-si",
+ "fsl,t1040-qe-si";
+ reg = <0x700 0x80>;
+ };
+
+ siram1: siram@1000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,ls1043-qe-siram",
+ "fsl,t1040-qe-siram";
+ reg = <0x1000 0x800>;
+ };
+
+ ucc@2000 {
+ cell-index = <1>;
+ reg = <0x2000 0x200>;
+ interrupts = <32>;
+ interrupt-parent = <>;
+ };
+
+ ucc@2200 {
+ cell-index = <3>;
+ reg = <0x2200 0x200>;
+ interrupts = <34>;
+ interrupt-parent = <>;
+ };
+
+ muram@1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,qe-muram", "fsl,cpm-muram";
+ ranges = <0x0 0x1 0x6000>;
+
+ data-only@0 {
+ compatible = "fsl,qe-muram-data",
+ "fsl,cpm-muram-data";
+ reg = <0x0 0x6000>;
+ };
+ };
+ };
+
lpuart0: serial@295 {
compatible = "fsl,ls1021a-lpuart";
reg = <0x0 0x295 0x0 0x1000>;
--
2.9.5
[patch v2 2/2] ls1043ardb: add ds26522 node to dts
From: Zhao Qiang
add ds26522 node to fsl-ls1043a-rdb.dts
Signed-off-by: Zhao Qiang
---
arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
index 96e87ba..b60c742 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
@@ -94,6 +94,22 @@
reg = <0>;
spi-max-frequency = <100>; /* input clock */
};
+
+ slic@2 {
+ compatible = "maxim,ds26522";
+ reg = <2>;
+ spi-max-frequency = <200>;
+ fsl,spi-cs-sck-delay = <100>;
+ fsl,spi-sck-cs-delay = <50>;
+ };
+
+ slic@3 {
+ compatible = "maxim,ds26522";
+ reg = <3>;
+ spi-max-frequency = <200>;
+ fsl,spi-cs-sck-delay = <100>;
+ fsl,spi-sck-cs-delay = <50>;
+ };
};
{
--
2.9.5
RE: [PATCH 0/7] towards QE support on ARM
On 22/10/2019 18:18, Rasmus Villemoes wrote: > -Original Message- > From: Rasmus Villemoes > Sent: 2019年10月22日 18:18 > To: Qiang Zhao ; Leo Li > Cc: Timur Tabi ; Greg Kroah-Hartman > ; linux-kernel@vger.kernel.org; > linux-ser...@vger.kernel.org; Jiri Slaby ; > linuxppc-...@lists.ozlabs.org; linux-arm-ker...@lists.infradead.org > Subject: Re: [PATCH 0/7] towards QE support on ARM > > On 22/10/2019 04.24, Qiang Zhao wrote: > > On Mon, Oct 22, 2019 at 6:11 AM Leo Li wrote > > >> Right. I'm really interested in getting this applied to my tree and > >> make it upstream. Zhao Qiang, can you help to review Rasmus's > >> patches and comment? > > > > As you know, I maintained a similar patchset removing PPC, and someone > told me qe_ic should moved into drivers/irqchip/. > > I also thought qe_ic is a interrupt control driver, should be moved into dir > irqchip. > > Yes, and I also plan to do that at some point. However, that's orthogonal to > making the driver build on ARM, so I don't want to mix the two. Making it > usable on ARM is my/our priority currently. > > I'd appreciate your input on my patches. Yes, we can put this patchset in first place, ensure it can build and work on ARM, then push another patchset to move qe_ic. Best Regards, Qiang
RE: [PATCH 0/7] towards QE support on ARM
On Mon, Oct 22, 2019 at 6:11 AM Leo Li wrote > -Original Message- > From: Li Yang > Sent: 2019年10月22日 6:11 > To: Rasmus Villemoes > Cc: Timur Tabi ; Greg Kroah-Hartman > ; linux-kernel@vger.kernel.org; > linux-ser...@vger.kernel.org; Jiri Slaby ; > linuxppc-...@lists.ozlabs.org; linux-arm-ker...@lists.infradead.org; Qiang > Zhao > Subject: Re: [PATCH 0/7] towards QE support on ARM > > On Mon, Oct 21, 2019 at 3:46 AM Rasmus Villemoes > wrote: > > > > On 18/10/2019 23.52, Li Yang wrote: > > > On Fri, Oct 18, 2019 at 3:54 PM Rasmus Villemoes > > > wrote: > > >> > > >> On 18/10/2019 22.16, Leo Li wrote: > > >>> > > >>>> > > >>>> There have been several attempts in the past few years to allow > > >>>> building the QUICC engine drivers for platforms other than PPC. > > >>>> This is (the beginning of) yet another attempt. I hope I can get > > >>>> someone to pick up these relatively trivial patches (I _think_ > > >>>> they shouldn't change functionality at all), and then I'll > > >>>> continue slowly working towards removing the PPC32 dependency for > CONFIG_QUICC_ENGINE. > > >>> > > >>> Hi Rasmus, > > >>> > > >>> I don't fully understand the motivation of this work. As far as I know > the QUICC ENGINE is only used on PowerPC based SoCs. > > >> > > >> Hm, you're not the Leo Li that participated in this thread > > >> > <https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.ke > rnel.org%2Flkml%2FAM3PR04MB11857AE8D2B0BE56121B97D391C90%40A > M3PR04MB1185.eurprd04.prod.outlook.com%2FT%2F%23udata=02%7 > C01%7Cqiang.zhao%40nxp.com%7C1ba8c50c2db14b22bef608d756739d82% > 7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C6370729268771788 > 75sdata=k4zM75OczXwZF%2Br9ec4RxiVR2a%2F8GhSZmK70JYddIck%3 > Dreserved=0>? > > > > > > Oops, I totally forgot about this discussion which is just three > > > years ago. :) The QE-HDLC on LS1021a is kind of a special case. > > > > > >> > > >> > > >> Can you give an example on how is it used on ARM system? > > >> > > >> LS1021A, for example, which is the one I'm aiming for getting fully > > >> supported in mainline. > > >> <https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2F > > >> > www.nxp.com%2Fproducts%2Fprocessors-and-microcontrollers%2Farm-proc > > >> essors%2Flayerscape-communication-process%2Fqoriq-layerscape-1021a- > > >> > dual-core-communications-processor-with-lcd-controller%3ALS1021A > > >> > p;data=02%7C01%7Cqiang.zhao%40nxp.com%7C1ba8c50c2db14b22bef608d > 7567 > > >> > 39d82%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C6370729268 > 771788 > > >> > 75sdata=vqPYSZqEv6vCEIxJshLuA4gngh9J4IsFAQrTwJKMjm4%3Dr > es > > >> erved=0> > > >> > > >> The forks at > > >> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub. > com%2Fqoriq-open-source%2Flinux.gitdata=02%7C01%7Cqiang.zhao% > 40nxp.com%7C1ba8c50c2db14b22bef608d756739d82%7C686ea1d3bc2b4c6 > fa92cd99c5c301635%7C0%7C0%7C637072926877178875sdata=v4eG > 4KqGTWQkQHp%2FYg2OHCKITLWaOgH64JYpY%2B1LilA%3Dreserved=0 > have various degrees of support (grep for commits saying stuff like "remove > PPCisms" > > >> - some versions can be found on > > >> <https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2F > > >> > lore.kernel.org%2Flkml%2F%3Fq%3Dremove%2Bppcismsdata=02%7C0 > 1%7 > > >> > Cqiang.zhao%40nxp.com%7C1ba8c50c2db14b22bef608d756739d82%7C686e > a1d3 > > >> > bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637072926877178875sdat > a=i2WdKNHLV68a1mTOMQ%2FoMr0y5ee8edS07xq61M8%2BvPU%3Dr > eserved=0>). Our current kernel is based on commits from the now-vanished > 4.1 branch, and unfortunately at least the 4.14 branch (LSDK-18.06-V4.14) > trivially doesn't build on ARM, despite the PPC32 dependency having been > removed from CONFIG_QUICC_ENGINE. > > > > > > Can you try the 4.14 branch from a newer LSDK release? LS1021a > > > should be supported platform on LSDK. If it is broken, something is > wrong. > > > > What newer release? LSDK-18.06-V4.14 is the latest -V4.14 tag at > > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgith > > > ub.com%2Fqoriq-open-source%2Flinux.gitdata=02%7C01%7Cqiang.zha > o%4 > > > 0nxp.com%7C1ba8c50c2db14b22bef
[PATCH] i2c: layerscape: use PIO when fail to request dma channel
When fail to request DMA TX/RX channel, use PIO instead for layerscape.
Signed-off-by: Zhao Qiang
---
drivers/i2c/busses/i2c-imx.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c
index 98b278613cf2..39a5ab4cf332 100644
--- a/drivers/i2c/busses/i2c-imx.c
+++ b/drivers/i2c/busses/i2c-imx.c
@@ -347,9 +347,13 @@ static int i2c_imx_dma_request(struct imx_i2c_struct
*i2c_imx,
dma->chan_tx = dma_request_chan(dev, "tx");
if (IS_ERR(dma->chan_tx)) {
+#ifdef CONFIG_ARCH_LAYERSCAPE
+ dev_dbg(dev, "can't request DMA tx channel\n");
+#else
ret = PTR_ERR(dma->chan_tx);
if (ret != -ENODEV && ret != -EPROBE_DEFER)
dev_err(dev, "can't request DMA tx channel (%d)\n",
ret);
+#endif
goto fail_al;
}
@@ -366,9 +370,13 @@ static int i2c_imx_dma_request(struct imx_i2c_struct
*i2c_imx,
dma->chan_rx = dma_request_chan(dev, "rx");
if (IS_ERR(dma->chan_rx)) {
+#ifdef CONFIG_ARCH_LAYERSCAPE
+ dev_dbg(dev, "can't request DMA rx channel\n");
+#else
ret = PTR_ERR(dma->chan_rx);
if (ret != -ENODEV && ret != -EPROBE_DEFER)
dev_err(dev, "can't request DMA rx channel (%d)\n",
ret);
+#endif
goto fail_tx;
}
@@ -396,6 +404,9 @@ static int i2c_imx_dma_request(struct imx_i2c_struct
*i2c_imx,
dma_release_channel(dma->chan_tx);
fail_al:
devm_kfree(dev, dma);
+#ifdef CONFIG_ARCH_LAYERSCAPE
+ dev_info(dev, "can't use DMA, using PIO instead.\n");
+#endif
/* return successfully if there is no dma support */
return ret == -ENODEV ? 0 : ret;
}
--
2.17.1
RE: [EXT] [PATCH v2 6/6] soc/fsl/qe: qe.c: fold qe_get_num_of_snums into qe_snums_init
On 2019/5/1 17:29, Rasmus Villemoes wrote:
> -Original Message-
> From: Rasmus Villemoes
> Sent: 2019年5月1日 17:29
> To: devicet...@vger.kernel.org; Qiang Zhao ; Leo Li
>
> Cc: linuxppc-...@lists.ozlabs.org; linux-arm-ker...@lists.infradead.org;
> linux-kernel@vger.kernel.org; Rob Herring ; Scott Wood
> ; Christophe Leroy ; Mark
> Rutland ; Rasmus Villemoes
>
> Subject: [PATCH v2 6/6] soc/fsl/qe: qe.c: fold qe_get_num_of_snums into
> qe_snums_init
>
> The comment "No QE ever has fewer than 28 SNUMs" is false; e.g. the
> MPC8309 has 14. The code path returning -EINVAL is also a recipe for instant
> disaster, since the caller (qe_snums_init) uncritically assigns the return
> value to
> the unsigned qe_num_of_snum, and would thus proceed to attempt to copy
> 4GB from snum_init_46[] to the snum[] array.
>
> So fold the handling of the legacy fsl,qe-num-snums into qe_snums_init, and
> make sure we do not end up using the snum_init_46 array in cases other than
> the two where we know it makes sense.
>
> Signed-off-by: Rasmus Villemoes
> ---
Reviewed-by: Qiang Zhao
> drivers/soc/fsl/qe/qe.c | 46 ++---
> 1 file changed, 16 insertions(+), 30 deletions(-)
>
> diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c index
> 325d689cbf5c..276d7d78ebfc 100644
> --- a/drivers/soc/fsl/qe/qe.c
> +++ b/drivers/soc/fsl/qe/qe.c
> @@ -308,24 +308,33 @@ static void qe_snums_init(void)
> int i;
>
> bitmap_zero(snum_state, QE_NUM_OF_SNUM);
> + qe_num_of_snum = 28; /* The default number of snum for threads
> + is 28 */
> qe = qe_get_device_node();
> if (qe) {
> i = of_property_read_variable_u8_array(qe, "fsl,qe-snums",
>snums, 1,
> QE_NUM_OF_SNUM);
> - of_node_put(qe);
> if (i > 0) {
> + of_node_put(qe);
> qe_num_of_snum = i;
> return;
> }
> + /*
> +* Fall back to legacy binding of using the value of
> +* fsl,qe-num-snums to choose one of the static arrays
> +* above.
> +*/
> + of_property_read_u32(qe, "fsl,qe-num-snums",
> _num_of_snum);
> + of_node_put(qe);
> }
>
> - qe_num_of_snum = qe_get_num_of_snums();
> -
> - if (qe_num_of_snum == 76)
> + if (qe_num_of_snum == 76) {
> snum_init = snum_init_76;
> - else
> + } else if (qe_num_of_snum == 28 || qe_num_of_snum == 46) {
> snum_init = snum_init_46;
> -
> + } else {
> + pr_err("QE: unsupported value of fsl,qe-num-snums: %u\n",
> qe_num_of_snum);
> + return;
> + }
> memcpy(snums, snum_init, qe_num_of_snum); }
>
> @@ -641,30 +650,7 @@ EXPORT_SYMBOL(qe_get_num_of_risc);
>
> unsigned int qe_get_num_of_snums(void)
> {
> - struct device_node *qe;
> - int size;
> - unsigned int num_of_snums;
> - const u32 *prop;
> -
> - num_of_snums = 28; /* The default number of snum for threads is 28
> */
> - qe = qe_get_device_node();
> - if (!qe)
> - return num_of_snums;
> -
> - prop = of_get_property(qe, "fsl,qe-num-snums", );
> - if (prop && size == sizeof(*prop)) {
> - num_of_snums = *prop;
> - if ((num_of_snums < 28) || (num_of_snums >
> QE_NUM_OF_SNUM)) {
> - /* No QE ever has fewer than 28 SNUMs */
> - pr_err("QE: number of snum is invalid\n");
> - of_node_put(qe);
> - return -EINVAL;
> - }
> - }
> -
> - of_node_put(qe);
> -
> - return num_of_snums;
> + return qe_num_of_snum;
> }
> EXPORT_SYMBOL(qe_get_num_of_snums);
>
> --
> 2.20.1
Best Regards
Qiang Zhao
[patch v14 4/4] irqchip/qeic: remove PPCisms for QEIC
QEIC was supported on PowerPC, and dependent on PPC, Now it is supported on other platforms, so remove PPCisms. Signed-off-by: Zhao Qiang --- arch/powerpc/platforms/83xx/km83xx.c |1 - arch/powerpc/platforms/83xx/misc.c|1 - arch/powerpc/platforms/83xx/mpc832x_mds.c |1 - arch/powerpc/platforms/83xx/mpc832x_rdb.c |1 - arch/powerpc/platforms/83xx/mpc836x_mds.c |1 - arch/powerpc/platforms/83xx/mpc836x_rdk.c |1 - arch/powerpc/platforms/85xx/corenet_generic.c |1 - arch/powerpc/platforms/85xx/mpc85xx_mds.c |1 - arch/powerpc/platforms/85xx/mpc85xx_rdb.c |1 - arch/powerpc/platforms/85xx/twr_p102x.c |1 - drivers/irqchip/irq-qeic.c| 188 +++-- include/soc/fsl/qe/qe_ic.h| 132 - 12 files changed, 80 insertions(+), 250 deletions(-) delete mode 100644 include/soc/fsl/qe/qe_ic.h diff --git a/arch/powerpc/platforms/83xx/km83xx.c b/arch/powerpc/platforms/83xx/km83xx.c index d8642a4..b1cef0a 100644 --- a/arch/powerpc/platforms/83xx/km83xx.c +++ b/arch/powerpc/platforms/83xx/km83xx.c @@ -38,7 +38,6 @@ #include #include #include -#include #include "mpc83xx.h" diff --git a/arch/powerpc/platforms/83xx/misc.c b/arch/powerpc/platforms/83xx/misc.c index 4150b56..b033a10 100644 --- a/arch/powerpc/platforms/83xx/misc.c +++ b/arch/powerpc/platforms/83xx/misc.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include diff --git a/arch/powerpc/platforms/83xx/mpc832x_mds.c b/arch/powerpc/platforms/83xx/mpc832x_mds.c index 74c154e..f86371b 100644 --- a/arch/powerpc/platforms/83xx/mpc832x_mds.c +++ b/arch/powerpc/platforms/83xx/mpc832x_mds.c @@ -37,7 +37,6 @@ #include #include #include -#include #include "mpc83xx.h" diff --git a/arch/powerpc/platforms/83xx/mpc832x_rdb.c b/arch/powerpc/platforms/83xx/mpc832x_rdb.c index 4389865..da91395 100644 --- a/arch/powerpc/platforms/83xx/mpc832x_rdb.c +++ b/arch/powerpc/platforms/83xx/mpc832x_rdb.c @@ -26,7 +26,6 @@ #include #include #include -#include #include #include diff --git a/arch/powerpc/platforms/83xx/mpc836x_mds.c b/arch/powerpc/platforms/83xx/mpc836x_mds.c index fd44dd0..9b8bc8b 100644 --- a/arch/powerpc/platforms/83xx/mpc836x_mds.c +++ b/arch/powerpc/platforms/83xx/mpc836x_mds.c @@ -45,7 +45,6 @@ #include #include #include -#include #include "mpc83xx.h" diff --git a/arch/powerpc/platforms/83xx/mpc836x_rdk.c b/arch/powerpc/platforms/83xx/mpc836x_rdk.c index 93f024f..82fa344 100644 --- a/arch/powerpc/platforms/83xx/mpc836x_rdk.c +++ b/arch/powerpc/platforms/83xx/mpc836x_rdk.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include diff --git a/arch/powerpc/platforms/85xx/corenet_generic.c b/arch/powerpc/platforms/85xx/corenet_generic.c index e44bb44..ac2478d 100644 --- a/arch/powerpc/platforms/85xx/corenet_generic.c +++ b/arch/powerpc/platforms/85xx/corenet_generic.c @@ -28,7 +28,6 @@ #include #include #include -#include #include #include diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c index 6892bc1..809266d 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c @@ -49,7 +49,6 @@ #include #include #include -#include #include #include #include "smp.h" diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c index 000d385..f806b6b 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c @@ -27,7 +27,6 @@ #include #include #include -#include #include #include diff --git a/arch/powerpc/platforms/85xx/twr_p102x.c b/arch/powerpc/platforms/85xx/twr_p102x.c index 6be9b33..4f620f2 100644 --- a/arch/powerpc/platforms/85xx/twr_p102x.c +++ b/arch/powerpc/platforms/85xx/twr_p102x.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include diff --git a/drivers/irqchip/irq-qeic.c b/drivers/irqchip/irq-qeic.c index a6ccbfb..723c52e 100644 --- a/drivers/irqchip/irq-qeic.c +++ b/drivers/irqchip/irq-qeic.c @@ -18,8 +18,11 @@ #include #include #include +#include #include #include +#include +#include #include #include #include @@ -27,9 +30,8 @@ #include #include #include -#include +#include #include -#include #define NR_QE_IC_INTS 64 @@ -87,6 +89,43 @@ #define SIGNAL_HIGH2 #define SIGNAL_LOW 0 +#define NUM_OF_QE_IC_GROUPS6 + +/* Flags when we init the QE IC */ +#define QE_IC_SPREADMODE_GRP_W BIT(0) +#define QE_IC_SPREADMODE_GRP_X BIT(1) +#define QE_IC_SPREADMODE_GRP_Y BIT(2) +#define QE_IC_SPREADMODE_GRP_Z BIT(3) +#define QE_IC_SPREADMODE_GRP_RISCA BIT(4) +#define QE_IC_SPREADMODE_GRP_RISCB BIT(5) +
[patch v14 1/4] irqchip/qeic: move qeic driver from drivers/soc/fsl/qe
move the driver from drivers/soc/fsl/qe to drivers/irqchip,
merge qe_ic.h and qe_ic.c into irq-qeic.c.
Signed-off-by: Zhao Qiang
---
MAINTAINERS|6 +
drivers/irqchip/Makefile |1 +
drivers/{soc/fsl/qe/qe_ic.c => irqchip/irq-qeic.c} | 141
drivers/soc/fsl/qe/Makefile|2 +-
drivers/soc/fsl/qe/qe_ic.h | 103 --
5 files changed, 123 insertions(+), 130 deletions(-)
rename drivers/{soc/fsl/qe/qe_ic.c => irqchip/irq-qeic.c} (81%)
delete mode 100644 drivers/soc/fsl/qe/qe_ic.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 3e5a5d2..540a82d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6255,6 +6255,12 @@ F: drivers/soc/fsl/qe/
F: include/soc/fsl/*qe*.h
F: include/soc/fsl/*ucc*.h
+FREESCALE QEIC DRIVERS
+M: Qiang Zhao
+L: linux-kernel@vger.kernel.org
+S: Maintained
+F: drivers/irqchip/irq-qeic.c
+
FREESCALE QUICC ENGINE UCC ETHERNET DRIVER
M: Li Yang
L: net...@vger.kernel.org
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 85972ae..726c0ba 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -97,3 +97,4 @@ obj-$(CONFIG_SIFIVE_PLIC) += irq-sifive-plic.o
obj-$(CONFIG_IMX_IRQSTEER) += irq-imx-irqsteer.o
obj-$(CONFIG_MADERA_IRQ) += irq-madera.o
obj-$(CONFIG_LS1X_IRQ) += irq-ls1x.o
+obj-$(CONFIG_QUICC_ENGINE) += irq-qeic.o
diff --git a/drivers/soc/fsl/qe/qe_ic.c b/drivers/irqchip/irq-qeic.c
similarity index 81%
rename from drivers/soc/fsl/qe/qe_ic.c
rename to drivers/irqchip/irq-qeic.c
index ec2ca86..aba7135 100644
--- a/drivers/soc/fsl/qe/qe_ic.c
+++ b/drivers/irqchip/irq-qeic.c
@@ -1,7 +1,7 @@
/*
- * arch/powerpc/sysdev/qe_lib/qe_ic.c
+ * drivers/irqchip/irq-qeic.c
*
- * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
+ * Copyright (C) 2016 Freescale Semiconductor, Inc. All rights reserved.
*
* Author: Li Yang
* Based on code from Shlomi Gridish
@@ -30,145 +30,234 @@
#include
#include
-#include "qe_ic.h"
+#define NR_QE_IC_INTS 64
+
+/* QE IC registers offset */
+#define QEIC_CICR 0x00
+#define QEIC_CIVEC 0x04
+#define QEIC_CRIPNR0x08
+#define QEIC_CIPNR 0x0c
+#define QEIC_CIPXCC0x10
+#define QEIC_CIPYCC0x14
+#define QEIC_CIPWCC0x18
+#define QEIC_CIPZCC0x1c
+#define QEIC_CIMR 0x20
+#define QEIC_CRIMR 0x24
+#define QEIC_CICNR 0x28
+#define QEIC_CIPRTA0x30
+#define QEIC_CIPRTB0x34
+#define QEIC_CRICR 0x3c
+#define QEIC_CHIVEC0x60
+
+/* Interrupt priority registers */
+#define CIPCC_SHIFT_PRI0 29
+#define CIPCC_SHIFT_PRI1 26
+#define CIPCC_SHIFT_PRI2 23
+#define CIPCC_SHIFT_PRI3 20
+#define CIPCC_SHIFT_PRI4 13
+#define CIPCC_SHIFT_PRI5 10
+#define CIPCC_SHIFT_PRI6 7
+#define CIPCC_SHIFT_PRI7 4
+
+/* CICR priority modes */
+#define CICR_GWCC BIT(18)
+#define CICR_GXCC BIT(17)
+#define CICR_GYCC BIT(16)
+#define CICR_GZCC BIT(19)
+#define CICR_GRTA BIT(21)
+#define CICR_GRTB BIT(22)
+#define CICR_HPIT_SHIFT8
+#define CICR_HPIT_MASK 0x0300
+#define CICR_HP_SHIFT 24
+#define CICR_HP_MASK 0x3f00
+
+/* CICNR */
+#define CICNR_WCC1T_SHIFT 20
+#define CICNR_ZCC1T_SHIFT 28
+#define CICNR_YCC1T_SHIFT 12
+#define CICNR_XCC1T_SHIFT 4
+
+/* CRICR */
+#define CRICR_RTA1T_SHIFT 20
+#define CRICR_RTB1T_SHIFT 28
+
+/* Signal indicator */
+#define SIGNAL_MASK3
+#define SIGNAL_HIGH2
+#define SIGNAL_LOW 0
+
+struct qe_ic {
+ /* Control registers offset */
+ u32 __iomem *regs;
+
+ /* The remapper for this QEIC */
+ struct irq_domain *irqhost;
+
+ /* The "linux" controller struct */
+ struct irq_chip hc_irq;
+
+ /* VIRQ numbers of QE high/low irqs */
+ unsigned int virq_high;
+ unsigned int virq_low;
+};
+
+/*
+ * QE interrupt controller internal structure
+ */
+struct qe_ic_info {
+ /* location of this source at the QIMR register. */
+ u32 mask;
+
+ /* Mask register offset */
+ u32 mask_reg;
+
+ /*
+* for grouped interrupts sources - the interrupt
+* code as appears at the group priority register
+*/
+ u8 pri_code;
+
+ /* Group priority register offset */
+ u32 pri_reg;
+};
static DEFINE_RAW_SPINLOCK(qe_ic_lock);
static struct qe_ic_info qe_ic_info[] = {
[1] = {
- .mask = 0x8000,
+ .mask = BIT(15),
.mask_reg = QEIC_CIMR,
[patch v14 2/4] irqchip/qeic: merge qeic init code from platforms to a common function
The codes of qe_ic init from a variety of platforms are redundant,
merge them to a common function and put it to irqchip/irq-qeic.c
For non-p1021_mds mpc85xx_mds boards, use "qe_ic_init(np, 0,
qe_ic_cascade_low_mpic, qe_ic_cascade_high_mpic);" instead of
"qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);".
qe_ic_cascade_muxed_mpic was used for boards has the same interrupt
number for low interrupt and high interrupt, qe_ic_init has checked
if "low interrupt == high interrupt"
Signed-off-by: Zhao Qiang
---
arch/powerpc/platforms/83xx/misc.c| 15 ---
arch/powerpc/platforms/85xx/corenet_generic.c |9 -
arch/powerpc/platforms/85xx/mpc85xx_mds.c | 14 --
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 16
arch/powerpc/platforms/85xx/twr_p102x.c | 14 --
drivers/irqchip/irq-qeic.c| 13 +
6 files changed, 13 insertions(+), 68 deletions(-)
diff --git a/arch/powerpc/platforms/83xx/misc.c
b/arch/powerpc/platforms/83xx/misc.c
index 2b6589f..4150b56 100644
--- a/arch/powerpc/platforms/83xx/misc.c
+++ b/arch/powerpc/platforms/83xx/misc.c
@@ -94,24 +94,9 @@ void __init mpc83xx_ipic_init_IRQ(void)
}
#ifdef CONFIG_QUICC_ENGINE
-void __init mpc83xx_qe_init_IRQ(void)
-{
- struct device_node *np;
-
- np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
- if (!np) {
- np = of_find_node_by_type(NULL, "qeic");
- if (!np)
- return;
- }
- qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
- of_node_put(np);
-}
-
void __init mpc83xx_ipic_and_qe_init_IRQ(void)
{
mpc83xx_ipic_init_IRQ();
- mpc83xx_qe_init_IRQ();
}
#endif /* CONFIG_QUICC_ENGINE */
diff --git a/arch/powerpc/platforms/85xx/corenet_generic.c
b/arch/powerpc/platforms/85xx/corenet_generic.c
index 785e964..e44bb44 100644
--- a/arch/powerpc/platforms/85xx/corenet_generic.c
+++ b/arch/powerpc/platforms/85xx/corenet_generic.c
@@ -42,8 +42,6 @@ void __init corenet_gen_pic_init(void)
unsigned int flags = MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU |
MPIC_NO_RESET;
- struct device_node *np;
-
if (ppc_md.get_irq == mpic_get_coreint_irq)
flags |= MPIC_ENABLE_COREINT;
@@ -51,13 +49,6 @@ void __init corenet_gen_pic_init(void)
BUG_ON(mpic == NULL);
mpic_init(mpic);
-
- np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
- if (np) {
- qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
- qe_ic_cascade_high_mpic);
- of_node_put(np);
- }
}
/*
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index 80939a4..6892bc1 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -283,20 +283,6 @@ static void __init mpc85xx_mds_qeic_init(void)
of_node_put(np);
return;
}
-
- np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
- if (!np) {
- np = of_find_node_by_type(NULL, "qeic");
- if (!np)
- return;
- }
-
- if (machine_is(p1021_mds))
- qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
- qe_ic_cascade_high_mpic);
- else
- qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
- of_node_put(np);
}
#else
static void __init mpc85xx_mds_qe_init(void) { }
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index 1006950..000d385 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -48,10 +48,6 @@ void __init mpc85xx_rdb_pic_init(void)
{
struct mpic *mpic;
-#ifdef CONFIG_QUICC_ENGINE
- struct device_node *np;
-#endif
-
if (of_machine_is_compatible("fsl,MPC85XXRDB-CAMP")) {
mpic = mpic_alloc(NULL, 0, MPIC_NO_RESET |
MPIC_BIG_ENDIAN |
@@ -66,18 +62,6 @@ void __init mpc85xx_rdb_pic_init(void)
BUG_ON(mpic == NULL);
mpic_init(mpic);
-
-#ifdef CONFIG_QUICC_ENGINE
- np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
- if (np) {
- qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
- qe_ic_cascade_high_mpic);
- of_node_put(np);
-
- } else
- pr_err("%s: Could not find qe-ic node\n", __func__);
-#endif
-
}
/*
diff --git a/arch/powerpc/platforms/85xx/twr_p102x.c
b/arch/powerpc/platforms/85xx/twr_p102x.c
index 360f625..6be9b33 100644
--- a/arch/powerpc/platforms/85xx/twr_p102x.c
+++ b/arch/powerpc/platforms/85xx/twr_p102x.c
@@ -35,26 +35,12 @@ static void __init twr_p1025_pic_init(void)
{
struct mpic *mpic;
-#ifdef CONFIG_QUICC_ENGINE
- struct
[PATCH 0/4] This patchset is to remove PPCisms for QEIC
QE is an IP block included in SoC of fsl PowerPC series and layerscape series,
its interrupt contoller was put under drivers/soc/fsl/qe, now move to
driver/irqchip.
And QEIC is supported more than just powerpc boards, so remove PPCisms.
changelog:
Changes for v2:
- modify the subject and commit msg
Changes for v3:
- merge .h file to .c, rename it with irq-qeic.c
Changes for v4:
- modify comments
Changes for v5:
- disable rename detection
Changes for v6:
- rebase
Changes for v7:
- na
Changes for v8:
- use IRQCHIP_DECLARE() instead of subsys_initcall in qeic driver
- remove include/soc/fsl/qe/qe_ic.h
Changes for v9:
- rebase
- fix the compile issue when apply the second patch, in fact, there was
no compile issue
when apply all the patches of this patchset
Changes for v10:
- simplify codes, remove duplicated codes
Changes for v11:
- rebase
Changes for v12:
Changes for v13:
- rewrite single-bit constants to BIT(x) to make the code more readable
Changes for v14:
- rebase
Zhao Qiang (4):
irqchip/qeic: move qeic driver from drivers/soc/fsl/qe
irqchip/qeic: merge qeic init code from platforms to a common
function
irqchip/qeic: merge qeic_of_init into qe_ic_init
irqchip/qeic: remove PPCisms for QEIC
MAINTAINERS|6 +
arch/powerpc/platforms/83xx/km83xx.c |1 -
arch/powerpc/platforms/83xx/misc.c | 16 -
arch/powerpc/platforms/83xx/mpc832x_mds.c |1 -
arch/powerpc/platforms/83xx/mpc832x_rdb.c |1 -
arch/powerpc/platforms/83xx/mpc836x_mds.c |1 -
arch/powerpc/platforms/83xx/mpc836x_rdk.c |1 -
arch/powerpc/platforms/85xx/corenet_generic.c | 10 -
arch/powerpc/platforms/85xx/mpc85xx_mds.c | 15 -
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 17 -
arch/powerpc/platforms/85xx/twr_p102x.c| 15 -
drivers/irqchip/Makefile |1 +
drivers/{soc/fsl/qe/qe_ic.c => irqchip/irq-qeic.c} | 423 ++-
drivers/soc/fsl/qe/Makefile|2 +-
drivers/soc/fsl/qe/qe_ic.h | 103 -
include/soc/fsl/qe/qe_ic.h | 139 ---
16 files changed, 231 insertions(+), 521 deletions(-)
rename drivers/{soc/fsl/qe/qe_ic.c => irqchip/irq-qeic.c} (53%)
delete mode 100644 drivers/soc/fsl/qe/qe_ic.h
delete mode 100644 include/soc/fsl/qe/qe_ic.h
[patch v14 3/4] irqchip/qeic: merge qeic_of_init into qe_ic_init
qeic_of_init just get device_node of qeic from dtb and call qe_ic_init,
pass the device_node to qe_ic_init.
So merge qeic_of_init into qe_ic_init to get the qeic node in
qe_ic_init.
Signed-off-by: Zhao Qiang
---
drivers/irqchip/irq-qeic.c | 110
include/soc/fsl/qe/qe_ic.h |7 ---
2 files changed, 30 insertions(+), 87 deletions(-)
diff --git a/drivers/irqchip/irq-qeic.c b/drivers/irqchip/irq-qeic.c
index 673afb4..a6ccbfb 100644
--- a/drivers/irqchip/irq-qeic.c
+++ b/drivers/irqchip/irq-qeic.c
@@ -407,27 +407,30 @@ unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
return irq_linear_revmap(qe_ic->irqhost, irq);
}
-void __init qe_ic_init(struct device_node *node, unsigned int flags,
- void (*low_handler)(struct irq_desc *desc),
- void (*high_handler)(struct irq_desc *desc))
+static int __init qe_ic_init(struct device_node *node,
+struct device_node *parent)
{
struct qe_ic *qe_ic;
struct resource res;
- u32 temp = 0, ret, high_active = 0;
+ int ret = 0;
ret = of_address_to_resource(node, 0, );
- if (ret)
- return;
+ if (ret) {
+ ret = -ENODEV;
+ goto err_put_node;
+ }
qe_ic = kzalloc(sizeof(*qe_ic), GFP_KERNEL);
- if (qe_ic == NULL)
- return;
+ if (qe_ic == NULL) {
+ ret = -ENOMEM;
+ goto err_put_node;
+ }
qe_ic->irqhost = irq_domain_add_linear(node, NR_QE_IC_INTS,
_ic_host_ops, qe_ic);
if (qe_ic->irqhost == NULL) {
- kfree(qe_ic);
- return;
+ ret = -ENOMEM;
+ goto err_free_qe_ic;
}
qe_ic->regs = ioremap(res.start, resource_size());
@@ -438,42 +441,30 @@ void __init qe_ic_init(struct device_node *node, unsigned
int flags,
qe_ic->virq_low = irq_of_parse_and_map(node, 1);
if (qe_ic->virq_low == NO_IRQ) {
- printk(KERN_ERR "Failed to map QE_IC low IRQ\n");
- kfree(qe_ic);
- return;
- }
-
- /* default priority scheme is grouped. If spread mode is*/
- /* required, configure cicr accordingly.*/
- if (flags & QE_IC_SPREADMODE_GRP_W)
- temp |= CICR_GWCC;
- if (flags & QE_IC_SPREADMODE_GRP_X)
- temp |= CICR_GXCC;
- if (flags & QE_IC_SPREADMODE_GRP_Y)
- temp |= CICR_GYCC;
- if (flags & QE_IC_SPREADMODE_GRP_Z)
- temp |= CICR_GZCC;
- if (flags & QE_IC_SPREADMODE_GRP_RISCA)
- temp |= CICR_GRTA;
- if (flags & QE_IC_SPREADMODE_GRP_RISCB)
- temp |= CICR_GRTB;
-
- /* choose destination signal for highest priority interrupt */
- if (flags & QE_IC_HIGH_SIGNAL) {
- temp |= (SIGNAL_HIGH << CICR_HPIT_SHIFT);
- high_active = 1;
+ pr_err("Failed to map QE_IC low IRQ\n");
+ ret = -ENOMEM;
+ goto err_domain_remove;
}
- qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
-
irq_set_handler_data(qe_ic->virq_low, qe_ic);
- irq_set_chained_handler(qe_ic->virq_low, low_handler);
+ irq_set_chained_handler(qe_ic->virq_low, qe_ic_cascade_low_mpic);
if (qe_ic->virq_high != NO_IRQ &&
qe_ic->virq_high != qe_ic->virq_low) {
irq_set_handler_data(qe_ic->virq_high, qe_ic);
- irq_set_chained_handler(qe_ic->virq_high, high_handler);
+ irq_set_chained_handler(qe_ic->virq_high,
+ qe_ic_cascade_high_mpic);
}
+ of_node_put(node);
+ return 0;
+
+err_domain_remove:
+ irq_domain_remove(qe_ic->irqhost);
+err_free_qe_ic:
+ kfree(qe_ic);
+err_put_node:
+ of_node_put(node);
+ return ret;
}
void qe_ic_set_highest_priority(unsigned int virq, int high)
@@ -570,45 +561,4 @@ int qe_ic_set_high_priority(unsigned int virq, unsigned
int priority, int high)
return 0;
}
-static struct bus_type qe_ic_subsys = {
- .name = "qe_ic",
- .dev_name = "qe_ic",
-};
-
-static struct device device_qe_ic = {
- .id = 0,
- .bus = _ic_subsys,
-};
-
-static int __init init_qe_ic_sysfs(void)
-{
- int rc;
-
- printk(KERN_DEBUG "Registering qe_ic with sysfs...\n");
-
- rc = subsys_system_register(_ic_subsys, NULL);
- if (rc) {
- printk(KERN_ERR "Failed registering qe_ic sys class\n");
- return -ENODEV;
- }
- rc = device_register(_qe_ic);
- if (rc) {
- printk(KERN_ERR "Failed registering qe_ic sys device\n");
- return -ENODEV;
- }
- return 0;
-}
-
-static int __init qeic_of_init(struct device_node *node,
-
RE: [PATCH 4/4] soc/fsl/qe: qe.c: support fsl,qe-snums property
On 01/03/2019 15.50，Rasmus Villemoes wrote:
> -Original Message-
> From: Rasmus Villemoes
> Sent: 2019年3月1日 15:50
> To: Qiang Zhao ; Leo Li
> Cc: Scott Wood ; linux-kernel@vger.kernel.org; Timur Tabi
> ; Rasmus Villemoes
> Subject: Re: [PATCH 4/4] soc/fsl/qe: qe.c: support fsl,qe-snums property
>
> On 01/03/2019 04.36, Qiang Zhao wrote:
> > On 2019年2月28日 18:31，Rasmus Villemoes wrote:
> >
> >> -Original Message-
> >> From: Rasmus Villemoes
> >> Sent: 2019年2月28日 18:31
> >> To: Qiang Zhao ; Leo Li
> >> Cc: Scott Wood ; linux-kernel@vger.kernel.org;
> >> Timur Tabi ; Rasmus Villemoes
> >>
> >> Subject: [PATCH 4/4] soc/fsl/qe: qe.c: support fsl,qe-snums property
> >>
> >
> > So you define 14 snums for MPC8309, but there still be the comment "/*
> > No QE ever has fewer than 28 SNUMs */" and it will check if The
> num_of_snums "is >28", it will cause confusion, so I suggest to modify 28 to
> 14.
>
> Sure, that needs updating. My thinking was that only legacy DTs would use the
> fsl,qe-num-snums, and there would be no need to support lower values than
> we used to, since the logic back in qe_snums_init wouldn't handle such values
> appropriately anyway.
>
> > I read the old version QUICC Engine Block Reference Manual, it said
> > snums table is not available on MPC8306/MPC8306S/MPC8309, So I think
> the code it written long before with this version RM, and at that time, the
> snums is at least 28, and nobody modify the code later.
> > And now with the new version RM, it support
> MPC8306/MPC8306S/MPC8309
> > with snums and have snums fewer then 28, so I think the minimum value
> should Be modified to 14.
>
> Yes. I'll do an extra cleanup patch modifying the code comments appropriately.
> But what do you think about the core idea behind this change (and the
> preceding cleanup patches)?
Maybe we could modify the comments in this patch, Anyway, the
MPC8306/MPC8306S/MPC8309
Is supported with snums and the number is 14, In addition, you assign
qe_num_of_snum to i as below.
The variable stands for num of snums.
Or we could add comments to explain it clearly why qe_num_of_snum is assign to
a value fewer than 28
While it says " No QE ever has fewer than 28 SNUMs ".
+ qe = qe_get_device_node();
+ if (qe) {
+ i = of_property_read_variable_u8_array(qe, "fsl,qe-snums",
+ snums, 14,
QE_NUM_OF_SNUM);
+ of_node_put(qe);
+ if (i > 0) {
+ qe_num_of_snum = i;
+ return;
+ }
+ }
Best Regards
Qiang Zhao
RE: [PATCH 4/4] soc/fsl/qe: qe.c: support fsl,qe-snums property
On 2019年2月28日 18:31，Rasmus Villemoes wrote:
> -Original Message-
> From: Rasmus Villemoes
> Sent: 2019年2月28日 18:31
> To: Qiang Zhao ; Leo Li
> Cc: Scott Wood ; linux-kernel@vger.kernel.org; Timur Tabi
> ; Rasmus Villemoes
> Subject: [PATCH 4/4] soc/fsl/qe: qe.c: support fsl,qe-snums property
>
> The current code assumes that the set of snum _values_ to populate the
> snums[] array with is a function of the _number_ of snums alone. However,
> reading table 4-30, and its footnotes, of the QUICC Engine Block Reference
> Manual shows that that is a bit too naive.
>
> As an alternative, this introduces a new binding fsl,qe-snums, which
> automatically encodes both the number of snums and the actual values to use.
> Conveniently, of_property_read_variable_u8_array does exactly what we need.
>
> For example, for the MPC8309, one would specify the property as
>
>fsl,qe-snums = /bits/ 8 <
>0x88 0x89 0x98 0x99 0xa8 0xa9 0xb8 0xb9
>0xc8 0xc9 0xd8 0xd9 0xe8 0xe9>;
>
> Signed-off-by: Rasmus Villemoes
> ---
> .../devicetree/bindings/soc/fsl/cpm_qe/qe.txt | 8 +++-
> drivers/soc/fsl/qe/qe.c| 14 +-
> 2 files changed, 20 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe.txt
> b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe.txt
> index d7afaff5faff..05f5f485562a 100644
> --- a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe.txt
> +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe.txt
> @@ -18,7 +18,8 @@ Required properties:
> - reg : offset and length of the device registers.
> - bus-frequency : the clock frequency for QUICC Engine.
> - fsl,qe-num-riscs: define how many RISC engines the QE has.
> -- fsl,qe-num-snums: define how many serial number(SNUM) the QE can use
> for the
> +- fsl,qe-snums: This property has to be specified as '/bits/ 8' value,
> + defining the array of serial number (SNUM) values for the virtual
>threads.
>
> Optional properties:
> @@ -34,6 +35,11 @@ Recommended properties
> - brg-frequency : the internal clock source frequency for baud-rate
>generators in Hz.
>
> +Deprecated properties
> +- fsl,qe-num-snums: define how many serial number(SNUM) the QE can use
> + for the threads. Use fsl,qe-snums instead to not only specify the
> + number of snums, but also their values.
> +
> Example:
> qe@e010 {
> #address-cells = <1>;
> diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c index
> 71beeb72eee4..049b36d6aeee 100644
> --- a/drivers/soc/fsl/qe/qe.c
> +++ b/drivers/soc/fsl/qe/qe.c
> @@ -283,7 +283,6 @@ EXPORT_SYMBOL(qe_clock_source);
> */
> static void qe_snums_init(void)
> {
> - int i;
> static const u8 snum_init_76[] = {
> 0x04, 0x05, 0x0C, 0x0D, 0x14, 0x15, 0x1C, 0x1D,
> 0x24, 0x25, 0x2C, 0x2D, 0x34, 0x35, 0x88, 0x89, @@ -304,9
> +303,22 @@ static void qe_snums_init(void)
> 0x28, 0x29, 0x38, 0x39, 0x48, 0x49, 0x58, 0x59,
> 0x68, 0x69, 0x78, 0x79, 0x80, 0x81,
> };
> + struct device_node *qe;
> const u8 *snum_init;
> + int i;
>
> bitmap_zero(snum_state, QE_NUM_OF_SNUM);
> + qe = qe_get_device_node();
> + if (qe) {
> + i = of_property_read_variable_u8_array(qe, "fsl,qe-snums",
> +snums, 14,
> QE_NUM_OF_SNUM);
> + of_node_put(qe);
> + if (i > 0) {
> + qe_num_of_snum = i;
> + return;
> + }
> + }
> +
> qe_num_of_snum = qe_get_num_of_snums();
>
> if (qe_num_of_snum == 76)
So you define 14 snums for MPC8309, but there still be the comment "/* No QE
ever has fewer than 28 SNUMs */" and it will check if
The num_of_snums "is >28", it will cause confusion, so I suggest to modify 28
to 14.
I read the old version QUICC Engine Block Reference Manual, it said snums table
is not available on MPC8306/MPC8306S/MPC8309,
So I think the code it written long before with this version RM, and at that
time, the snums is at least 28, and nobody modify the code later.
And now with the new version RM, it support MPC8306/MPC8306S/MPC8309 with snums
and have snums fewer then 28, so I think the minimum value should
Be modified to 14.
Thank you!
-Qiang Zhao
RE: [Patch v13 0/4] This patchset is to remove PPCisms for QEIC
Anybody help to review on this patchset?
Best Regards
Qiang Zhao
> -Original Message-
> From: Qiang Zhao
> Sent: 2017年11月30日 9:11
> To: Qiang Zhao ; t...@linutronix.de;
> marc.zyng...@arm.com; ja...@lakedaemon.net
> Cc: linux-kernel@vger.kernel.org
> Subject: RE: [Patch v13 0/4] This patchset is to remove PPCisms for QEIC
>
> Hi Thomas and Marc,
>
> Is there any feedback? Thank you!
>
> Best Regards
> Qiang Zhao
>
> > -Original Message-
> > From: Zhao Qiang [mailto:qiang.z...@nxp.com]
> > Sent: Friday, November 10, 2017 11:31 AM
> > To: t...@linutronix.de; marc.zyng...@arm.com; ja...@lakedaemon.net
> > Cc: linux-kernel@vger.kernel.org; Qiang Zhao
> > Subject: [Patch v13 0/4] This patchset is to remove PPCisms for QEIC
> >
> > QEIC is an interrupt controller for QE, was put under
> > drivers/soc/fsl/qe, and now move to driver/irqchip.
> > And QEIC is supported more than just powerpc boards, so remove PPCisms.
> >
> > changelog:
> > Changes for v8:
> > - use IRQCHIP_DECLARE() instead of subsys_initcall in qeic driver
> > - remove include/soc/fsl/qe/qe_ic.h
> > Changes for v9:
> > - rebase
> > - fix the compile issue when apply the second patch, in fact, there
> > was no compile issue
> > when apply all the patches of this patchset
> > Changes for v10:
> > - simplify codes, remove duplicated codes
> > Changes for v11:
> > - rebase
> > Changes for v13:
> > - rewrite single-bit constants to BIT(x) to make the code more
> > readable
> >
> > Zhao Qiang (4):
> > irqchip/qeic: move qeic driver from drivers/soc/fsl/qe
> > Changes for v2:
> > - modify the subject and commit msg
> > Changes for v3:
> > - merge .h file to .c, rename it with irq-qeic.c
> > Changes for v4:
> > - modify comments
> > Changes for v5:
> > - disable rename detection
> > Changes for v6:
> > - rebase
> > Changes for v7:
> > - na
> >
> > irqchip/qeic: merge qeic init code from platforms to a common function
> > Changes for v2:
> > - modify subject and commit msg
> > - add check for qeic by type
> > Changes for v3:
> > - na
> > Changes for v4:
> > - na
> > Changes for v5:
> > - na
> > Changes for v6:
> > - rebase
> > Changes for v7:
> > - na
> > Changes for v8:
> > - use IRQCHIP_DECLARE() instead of subsys_initcall
> >
> > irqchip/qeic: merge qeic_of_init into qe_ic_init
> > Changes for v2:
> > - modify subject and commit msg
> > - return 0 and add put node when return in qe_ic_init
> > Changes for v3:
> > - na
> > Changes for v4:
> > - na
> > Changes for v5:
> > - na
> > Changes for v6:
> > - rebase
> > Changes for v7:
> > - na
> > Changes for v12:
> > - remove unused code
> >
> > irqchip/qeic: remove PPCisms for QEIC
> > Changes for v6:
> > - new added
> > Changes for v7:
> > - fix warning
> > Changes for v8:
> > - remove include/soc/fsl/qe/qe_ic.h
> >
> > Zhao Qiang (4):
> > irqchip/qeic: move qeic driver from drivers/soc/fsl/qe
> > irqchip/qeic: merge qeic init code from platforms to a common function
> > irqchip/qeic: merge qeic_of_init into qe_ic_init
> > irqchip/qeic: remove PPCisms for QEIC
> >
> > MAINTAINERS| 6 +
> > arch/powerpc/platforms/83xx/km83xx.c | 1 -
> > arch/powerpc/platforms/83xx/misc.c | 16 -
> > arch/powerpc/platforms/83xx/mpc832x_mds.c | 1 -
> > arch/powerpc/platforms/83xx/mpc832x_rdb.c | 1 -
> > arch/powerpc/platforms/83xx/mpc836x_mds.c | 1 -
> > arch/powerpc/platforms/83xx/mpc836x_rdk.c | 1 -
> > arch/powerpc/platforms/85xx/corenet_generic.c | 10 -
> > arch/powerpc/platforms/85xx/mpc85xx_mds.c | 15 -
> > arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 17 -
> > arch/powerpc/platforms/85xx/twr_p102x.c| 15 -
> > drivers/irqchip/Makefile | 1 +
> > drivers/{soc/fsl/qe/qe_ic.c => irqchip/irq-qeic.c} | 423
> > +++--
> > drivers/soc/fsl/qe/Makefile| 2 +-
> > drivers/soc/fsl/qe/qe_ic.h | 103 -
> > include/soc/fsl/qe/qe_ic.h | 139 ---
> > 16 files changed, 231 insertions(+), 521 deletions(-) rename
> > drivers/{soc/fsl/qe/qe_ic.c => irqchip/irq-qeic.c} (53%) delete mode
> > 100644 drivers/soc/fsl/qe/qe_ic.h delete mode 100644
> > include/soc/fsl/qe/qe_ic.h
> >
> > --
> > 2.14.1
RE: [RFC PATCH] soc/fsl/qe: support MPC8309
On Tue, Feb 26, 2019 at 2:49 AM Rasmus Villemoes
wrote:
> -Original Message-
> From: Rasmus Villemoes
> Sent: 2019年2月26日 16:48
> To: Qiang Zhao ; Leo Li
> Cc: linux-kernel@vger.kernel.org; Valentin Longchamp
> ; Scott Wood ;
> Rasmus Villemoes
> Subject: [RFC PATCH] soc/fsl/qe: support MPC8309
>
> Currently, when device tree specifies fsl,qe-num-snums = 28 (which a number
> of in-tree .dts files do, and which is the default when that property is
> missing),
> qe_snums_init() ends up using the first 28 elements of the snum_init_46[]
> array.
>
> The situation is quite messy. This patch may break existing setups that for
> some reason work with specifying fsl,qe-num-snums = 28 and using the
> existing snum_init_46 array. OTOH, the current code certainly does not work
> for the MPC8309-based board we're working on, since the first 14 of the
> elements in snum_init_46 are "Not available on
> MPC8306/MPC8306S/MPC8309" according to the QUICC Engine Reference
> Manual (Table 4-30) - and indeed, without this patch (or something to the
> same effect), we get
According to the QUICC Engine Reference Manual (Table 4-30), the number of
snums used for
" MPC8306/MPC8306S/MPC8309" should be 14 instead of 28, so maybe we should
assign "fsl,qe-num-snums = 14"
And define a new snum_init_14 array, meanwhile, modify the minimum value of
"num_of_snums" to 14 in function "qe_get_num_of_snums"
(I mean: " if ((num_of_snums < 14) || (num_of_snums > QE_NUM_OF_SNUM)) {")
Best Regards
Qiang Zhao
RE: [PATCH] soc/fsl/qe: fix err handling of ucc_of_parse_tdm
Hi Wen,
Will you send another version to resolve the issue described in the comments?
BR
Qiang
> -Original Message-
> From: Li Yang
> Sent: 2018年12月6日 4:10
> To: wang.y...@zte.com.cn
> Cc: Qiang Zhao ; zhong.weid...@zte.com.cn; lkml
> ; julia.law...@lip6.fr; linuxppc-dev
> ; wen.yan...@zte.com.cn; moderated
> list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
>
> Subject: Re: [PATCH] soc/fsl/qe: fix err handling of ucc_of_parse_tdm
>
> On Thu, Nov 22, 2018 at 2:42 PM Yi Wang wrote:
> >
> > From: Wen Yang
> >
> > Currently there are 2 problems with the ucc_of_parse_tdm function:
> > 1,a possible null pointer dereference in ucc_of_parse_tdm, detected by
> > the semantic patch deref_null.cocci, with the following warning:
> > drivers/soc/fsl/qe/qe_tdm.c:177:21-24: ERROR: pdev is NULL but
> dereferenced.
> > 2,dev gets modified, so in any case that devm_iounmap() will fail even
> > when the new pdev is valid, because the iomap was done with a different
> pdev.
> > This patch fixes them.
>
> While we are at this, I think this logic need more serious fixing. I see
> there is
> no driver bind with the "fsl,t1040-qe-si" or "fsl,t1040-qe-siram" device. So
> allocating resources using devm_*() with these devices won't provide a
> cleanup path for these resources when the caller fails. I think we should
> probably allocate resource under device of caller (e.g. ucc-hdlc), so that
> when
> caller probe fails or is removed it will trigger the cleanup.
>
> >
> > Suggested-by: Christophe LEROY
> > Signed-off-by: Wen Yang
> > CC: Julia Lawall
> > CC: Zhao Qiang
> > ---
> > drivers/soc/fsl/qe/qe_tdm.c | 20 ++--
> > 1 file changed, 10 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/soc/fsl/qe/qe_tdm.c b/drivers/soc/fsl/qe/qe_tdm.c
> > index f78c346..9a29f0b 100644
> > --- a/drivers/soc/fsl/qe/qe_tdm.c
> > +++ b/drivers/soc/fsl/qe/qe_tdm.c
> > @@ -47,7 +47,7 @@ int ucc_of_parse_tdm(struct device_node *np, struct
> ucc_tdm *utdm,
> > struct resource *res;
> > struct device_node *np2;
> > static int siram_init_flag;
> > - struct platform_device *pdev;
> > + struct platform_device *pdev_si, *pdev_siram;
> >
> > sprop = of_get_property(np, "fsl,rx-sync-clock", NULL);
> > if (sprop) {
> > @@ -129,16 +129,16 @@ int ucc_of_parse_tdm(struct device_node *np,
> struct ucc_tdm *utdm,
> > if (!np2)
> > return -EINVAL;
> >
> > - pdev = of_find_device_by_node(np2);
> > - if (!pdev) {
> > + pdev_si = of_find_device_by_node(np2);
> > + if (!pdev_si) {
> > pr_err("%pOFn: failed to lookup pdev\n", np2);
> > of_node_put(np2);
> > return -EINVAL;
> > }
> >
> > of_node_put(np2);
> > - res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > - utdm->si_regs = devm_ioremap_resource(>dev, res);
> > + res = platform_get_resource(pdev_si, IORESOURCE_MEM, 0);
> > + utdm->si_regs = devm_ioremap_resource(_si->dev, res);
> > if (IS_ERR(utdm->si_regs)) {
> > ret = PTR_ERR(utdm->si_regs);
> > goto err_miss_siram_property; @@ -150,8 +150,8 @@
> int
> > ucc_of_parse_tdm(struct device_node *np, struct ucc_tdm *utdm,
> > goto err_miss_siram_property;
> > }
> >
> > - pdev = of_find_device_by_node(np2);
> > - if (!pdev) {
> > + pdev_siram = of_find_device_by_node(np2);
> > + if (!pdev_siram) {
> > ret = -EINVAL;
> > pr_err("%pOFn: failed to lookup pdev\n", np2);
> > of_node_put(np2);
> > @@ -159,8 +159,8 @@ int ucc_of_parse_tdm(struct device_node *np, struct
> ucc_tdm *utdm,
> > }
> >
> > of_node_put(np2);
> > - res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > - utdm->siram = devm_ioremap_resource(>dev, res);
> > + res = platform_get_resource(pdev_siram, IORESOURCE_MEM, 0);
> > + utdm->siram = devm_ioremap_resource(_siram->dev, res);
> > if (IS_ERR(utdm->siram)) {
> > ret = PTR_ERR(utdm->siram);
> > goto err_miss_siram_property; @@ -174,7 +174,7 @@
> int
> > ucc_of_parse_tdm(struct device_node *np, struct ucc_tdm *utdm,
> > return ret;
> >
> > err_miss_siram_property:
> > - devm_iounmap(>dev, utdm->si_regs);
> > + devm_iounmap(_si->dev, utdm->si_regs);
> > return ret;
> > }
> > EXPORT_SYMBOL(ucc_of_parse_tdm);
> > --
> > 2.9.5
> >
RE: [Patch v13 0/4] This patchset is to remove PPCisms for QEIC
Hi all,
Is there any comments on this patchset?
Best Regards
Qiang Zhao
-Original Message-
From: Zhao Qiang [mailto:qiang.z...@nxp.com]
Sent: 2017年11月10日 11:31
To: t...@linutronix.de; marc.zyng...@arm.com; ja...@lakedaemon.net
Cc: linux-kernel@vger.kernel.org; Qiang Zhao <qiang.z...@nxp.com>
Subject: [Patch v13 0/4] This patchset is to remove PPCisms for QEIC
QEIC is an interrupt controller for QE, was put under drivers/soc/fsl/qe, and
now move to driver/irqchip.
And QEIC is supported more than just powerpc boards, so remove PPCisms.
changelog:
Changes for v8:
- use IRQCHIP_DECLARE() instead of subsys_initcall in qeic driver
- remove include/soc/fsl/qe/qe_ic.h
Changes for v9:
- rebase
- fix the compile issue when apply the second patch, in fact, there was
no compile issue
when apply all the patches of this patchset
Changes for v10:
- simplify codes, remove duplicated codes
Changes for v11:
- rebase
Changes for v13:
- rewrite single-bit constants to BIT(x) to make the code more readable
Zhao Qiang (4):
irqchip/qeic: move qeic driver from drivers/soc/fsl/qe
Changes for v2:
- modify the subject and commit msg
Changes for v3:
- merge .h file to .c, rename it with irq-qeic.c
Changes for v4:
- modify comments
Changes for v5:
- disable rename detection
Changes for v6:
- rebase
Changes for v7:
- na
irqchip/qeic: merge qeic init code from platforms to a common function
Changes for v2:
- modify subject and commit msg
- add check for qeic by type
Changes for v3:
- na
Changes for v4:
- na
Changes for v5:
- na
Changes for v6:
- rebase
Changes for v7:
- na
Changes for v8:
- use IRQCHIP_DECLARE() instead of subsys_initcall
irqchip/qeic: merge qeic_of_init into qe_ic_init
Changes for v2:
- modify subject and commit msg
- return 0 and add put node when return in qe_ic_init
Changes for v3:
- na
Changes for v4:
- na
Changes for v5:
- na
Changes for v6:
- rebase
Changes for v7:
- na
Changes for v12:
- remove unused code
irqchip/qeic: remove PPCisms for QEIC
Changes for v6:
- new added
Changes for v7:
- fix warning
Changes for v8:
- remove include/soc/fsl/qe/qe_ic.h
Zhao Qiang (4):
irqchip/qeic: move qeic driver from drivers/soc/fsl/qe
irqchip/qeic: merge qeic init code from platforms to a common function
irqchip/qeic: merge qeic_of_init into qe_ic_init
irqchip/qeic: remove PPCisms for QEIC
MAINTAINERS| 6 +
arch/powerpc/platforms/83xx/km83xx.c | 1 -
arch/powerpc/platforms/83xx/misc.c | 16 -
arch/powerpc/platforms/83xx/mpc832x_mds.c | 1 -
arch/powerpc/platforms/83xx/mpc832x_rdb.c | 1 -
arch/powerpc/platforms/83xx/mpc836x_mds.c | 1 -
arch/powerpc/platforms/83xx/mpc836x_rdk.c | 1 -
arch/powerpc/platforms/85xx/corenet_generic.c | 10 -
arch/powerpc/platforms/85xx/mpc85xx_mds.c | 15 -
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 17 -
arch/powerpc/platforms/85xx/twr_p102x.c| 15 -
drivers/irqchip/Makefile | 1 +
drivers/{soc/fsl/qe/qe_ic.c => irqchip/irq-qeic.c} | 423 +++--
drivers/soc/fsl/qe/Makefile| 2 +-
drivers/soc/fsl/qe/qe_ic.h | 103 -
include/soc/fsl/qe/qe_ic.h | 139 ---
16 files changed, 231 insertions(+), 521 deletions(-) rename
drivers/{soc/fsl/qe/qe_ic.c => irqchip/irq-qeic.c} (53%) delete mode 100644
drivers/soc/fsl/qe/qe_ic.h delete mode 100644 include/soc/fsl/qe/qe_ic.h
--
2.14.1
RE: [Patch v13 0/4] This patchset is to remove PPCisms for QEIC
Hi all,
Is there any comments on this patchset?
Best Regards
Qiang Zhao
-Original Message-
From: Zhao Qiang [mailto:qiang.z...@nxp.com]
Sent: 2017年11月10日 11:31
To: t...@linutronix.de; marc.zyng...@arm.com; ja...@lakedaemon.net
Cc: linux-kernel@vger.kernel.org; Qiang Zhao
Subject: [Patch v13 0/4] This patchset is to remove PPCisms for QEIC
QEIC is an interrupt controller for QE, was put under drivers/soc/fsl/qe, and
now move to driver/irqchip.
And QEIC is supported more than just powerpc boards, so remove PPCisms.
changelog:
Changes for v8:
- use IRQCHIP_DECLARE() instead of subsys_initcall in qeic driver
- remove include/soc/fsl/qe/qe_ic.h
Changes for v9:
- rebase
- fix the compile issue when apply the second patch, in fact, there was
no compile issue
when apply all the patches of this patchset
Changes for v10:
- simplify codes, remove duplicated codes
Changes for v11:
- rebase
Changes for v13:
- rewrite single-bit constants to BIT(x) to make the code more readable
Zhao Qiang (4):
irqchip/qeic: move qeic driver from drivers/soc/fsl/qe
Changes for v2:
- modify the subject and commit msg
Changes for v3:
- merge .h file to .c, rename it with irq-qeic.c
Changes for v4:
- modify comments
Changes for v5:
- disable rename detection
Changes for v6:
- rebase
Changes for v7:
- na
irqchip/qeic: merge qeic init code from platforms to a common function
Changes for v2:
- modify subject and commit msg
- add check for qeic by type
Changes for v3:
- na
Changes for v4:
- na
Changes for v5:
- na
Changes for v6:
- rebase
Changes for v7:
- na
Changes for v8:
- use IRQCHIP_DECLARE() instead of subsys_initcall
irqchip/qeic: merge qeic_of_init into qe_ic_init
Changes for v2:
- modify subject and commit msg
- return 0 and add put node when return in qe_ic_init
Changes for v3:
- na
Changes for v4:
- na
Changes for v5:
- na
Changes for v6:
- rebase
Changes for v7:
- na
Changes for v12:
- remove unused code
irqchip/qeic: remove PPCisms for QEIC
Changes for v6:
- new added
Changes for v7:
- fix warning
Changes for v8:
- remove include/soc/fsl/qe/qe_ic.h
Zhao Qiang (4):
irqchip/qeic: move qeic driver from drivers/soc/fsl/qe
irqchip/qeic: merge qeic init code from platforms to a common function
irqchip/qeic: merge qeic_of_init into qe_ic_init
irqchip/qeic: remove PPCisms for QEIC
MAINTAINERS| 6 +
arch/powerpc/platforms/83xx/km83xx.c | 1 -
arch/powerpc/platforms/83xx/misc.c | 16 -
arch/powerpc/platforms/83xx/mpc832x_mds.c | 1 -
arch/powerpc/platforms/83xx/mpc832x_rdb.c | 1 -
arch/powerpc/platforms/83xx/mpc836x_mds.c | 1 -
arch/powerpc/platforms/83xx/mpc836x_rdk.c | 1 -
arch/powerpc/platforms/85xx/corenet_generic.c | 10 -
arch/powerpc/platforms/85xx/mpc85xx_mds.c | 15 -
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 17 -
arch/powerpc/platforms/85xx/twr_p102x.c| 15 -
drivers/irqchip/Makefile | 1 +
drivers/{soc/fsl/qe/qe_ic.c => irqchip/irq-qeic.c} | 423 +++--
drivers/soc/fsl/qe/Makefile| 2 +-
drivers/soc/fsl/qe/qe_ic.h | 103 -
include/soc/fsl/qe/qe_ic.h | 139 ---
16 files changed, 231 insertions(+), 521 deletions(-) rename
drivers/{soc/fsl/qe/qe_ic.c => irqchip/irq-qeic.c} (53%) delete mode 100644
drivers/soc/fsl/qe/qe_ic.h delete mode 100644 include/soc/fsl/qe/qe_ic.h
--
2.14.1
RE: [Patch v13 0/4] This patchset is to remove PPCisms for QEIC
Hi Thomas and Marc,
Is there any feedback? Thank you!
Best Regards
Qiang Zhao
> -Original Message-
> From: Zhao Qiang [mailto:qiang.z...@nxp.com]
> Sent: Friday, November 10, 2017 11:31 AM
> To: t...@linutronix.de; marc.zyng...@arm.com; ja...@lakedaemon.net
> Cc: linux-kernel@vger.kernel.org; Qiang Zhao <qiang.z...@nxp.com>
> Subject: [Patch v13 0/4] This patchset is to remove PPCisms for QEIC
>
> QEIC is an interrupt controller for QE, was put under drivers/soc/fsl/qe, and
> now
> move to driver/irqchip.
> And QEIC is supported more than just powerpc boards, so remove PPCisms.
>
> changelog:
> Changes for v8:
> - use IRQCHIP_DECLARE() instead of subsys_initcall in qeic driver
> - remove include/soc/fsl/qe/qe_ic.h
> Changes for v9:
> - rebase
> - fix the compile issue when apply the second patch, in fact, there was
> no compile issue
> when apply all the patches of this patchset
> Changes for v10:
> - simplify codes, remove duplicated codes
> Changes for v11:
> - rebase
> Changes for v13:
> - rewrite single-bit constants to BIT(x) to make the code more readable
>
> Zhao Qiang (4):
> irqchip/qeic: move qeic driver from drivers/soc/fsl/qe
> Changes for v2:
> - modify the subject and commit msg
> Changes for v3:
> - merge .h file to .c, rename it with irq-qeic.c
> Changes for v4:
> - modify comments
> Changes for v5:
> - disable rename detection
> Changes for v6:
> - rebase
> Changes for v7:
> - na
>
> irqchip/qeic: merge qeic init code from platforms to a common function
> Changes for v2:
> - modify subject and commit msg
> - add check for qeic by type
> Changes for v3:
> - na
> Changes for v4:
> - na
> Changes for v5:
> - na
> Changes for v6:
> - rebase
> Changes for v7:
> - na
> Changes for v8:
> - use IRQCHIP_DECLARE() instead of subsys_initcall
>
> irqchip/qeic: merge qeic_of_init into qe_ic_init
> Changes for v2:
> - modify subject and commit msg
> - return 0 and add put node when return in qe_ic_init
> Changes for v3:
> - na
> Changes for v4:
> - na
> Changes for v5:
> - na
> Changes for v6:
> - rebase
> Changes for v7:
> - na
> Changes for v12:
> - remove unused code
>
> irqchip/qeic: remove PPCisms for QEIC
> Changes for v6:
> - new added
> Changes for v7:
> - fix warning
> Changes for v8:
> - remove include/soc/fsl/qe/qe_ic.h
>
> Zhao Qiang (4):
> irqchip/qeic: move qeic driver from drivers/soc/fsl/qe
> irqchip/qeic: merge qeic init code from platforms to a common function
> irqchip/qeic: merge qeic_of_init into qe_ic_init
> irqchip/qeic: remove PPCisms for QEIC
>
> MAINTAINERS| 6 +
> arch/powerpc/platforms/83xx/km83xx.c | 1 -
> arch/powerpc/platforms/83xx/misc.c | 16 -
> arch/powerpc/platforms/83xx/mpc832x_mds.c | 1 -
> arch/powerpc/platforms/83xx/mpc832x_rdb.c | 1 -
> arch/powerpc/platforms/83xx/mpc836x_mds.c | 1 -
> arch/powerpc/platforms/83xx/mpc836x_rdk.c | 1 -
> arch/powerpc/platforms/85xx/corenet_generic.c | 10 -
> arch/powerpc/platforms/85xx/mpc85xx_mds.c | 15 -
> arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 17 -
> arch/powerpc/platforms/85xx/twr_p102x.c| 15 -
> drivers/irqchip/Makefile | 1 +
> drivers/{soc/fsl/qe/qe_ic.c => irqchip/irq-qeic.c} | 423
> +++--
> drivers/soc/fsl/qe/Makefile| 2 +-
> drivers/soc/fsl/qe/qe_ic.h | 103 -
> include/soc/fsl/qe/qe_ic.h | 139 ---
> 16 files changed, 231 insertions(+), 521 deletions(-) rename
> drivers/{soc/fsl/qe/qe_ic.c => irqchip/irq-qeic.c} (53%) delete mode 100644
> drivers/soc/fsl/qe/qe_ic.h delete mode 100644 include/soc/fsl/qe/qe_ic.h
>
> --
> 2.14.1
RE: [Patch v13 0/4] This patchset is to remove PPCisms for QEIC
Hi Thomas and Marc,
Is there any feedback? Thank you!
Best Regards
Qiang Zhao
> -Original Message-
> From: Zhao Qiang [mailto:qiang.z...@nxp.com]
> Sent: Friday, November 10, 2017 11:31 AM
> To: t...@linutronix.de; marc.zyng...@arm.com; ja...@lakedaemon.net
> Cc: linux-kernel@vger.kernel.org; Qiang Zhao
> Subject: [Patch v13 0/4] This patchset is to remove PPCisms for QEIC
>
> QEIC is an interrupt controller for QE, was put under drivers/soc/fsl/qe, and
> now
> move to driver/irqchip.
> And QEIC is supported more than just powerpc boards, so remove PPCisms.
>
> changelog:
> Changes for v8:
> - use IRQCHIP_DECLARE() instead of subsys_initcall in qeic driver
> - remove include/soc/fsl/qe/qe_ic.h
> Changes for v9:
> - rebase
> - fix the compile issue when apply the second patch, in fact, there was
> no compile issue
> when apply all the patches of this patchset
> Changes for v10:
> - simplify codes, remove duplicated codes
> Changes for v11:
> - rebase
> Changes for v13:
> - rewrite single-bit constants to BIT(x) to make the code more readable
>
> Zhao Qiang (4):
> irqchip/qeic: move qeic driver from drivers/soc/fsl/qe
> Changes for v2:
> - modify the subject and commit msg
> Changes for v3:
> - merge .h file to .c, rename it with irq-qeic.c
> Changes for v4:
> - modify comments
> Changes for v5:
> - disable rename detection
> Changes for v6:
> - rebase
> Changes for v7:
> - na
>
> irqchip/qeic: merge qeic init code from platforms to a common function
> Changes for v2:
> - modify subject and commit msg
> - add check for qeic by type
> Changes for v3:
> - na
> Changes for v4:
> - na
> Changes for v5:
> - na
> Changes for v6:
> - rebase
> Changes for v7:
> - na
> Changes for v8:
> - use IRQCHIP_DECLARE() instead of subsys_initcall
>
> irqchip/qeic: merge qeic_of_init into qe_ic_init
> Changes for v2:
> - modify subject and commit msg
> - return 0 and add put node when return in qe_ic_init
> Changes for v3:
> - na
> Changes for v4:
> - na
> Changes for v5:
> - na
> Changes for v6:
> - rebase
> Changes for v7:
> - na
> Changes for v12:
> - remove unused code
>
> irqchip/qeic: remove PPCisms for QEIC
> Changes for v6:
> - new added
> Changes for v7:
> - fix warning
> Changes for v8:
> - remove include/soc/fsl/qe/qe_ic.h
>
> Zhao Qiang (4):
> irqchip/qeic: move qeic driver from drivers/soc/fsl/qe
> irqchip/qeic: merge qeic init code from platforms to a common function
> irqchip/qeic: merge qeic_of_init into qe_ic_init
> irqchip/qeic: remove PPCisms for QEIC
>
> MAINTAINERS| 6 +
> arch/powerpc/platforms/83xx/km83xx.c | 1 -
> arch/powerpc/platforms/83xx/misc.c | 16 -
> arch/powerpc/platforms/83xx/mpc832x_mds.c | 1 -
> arch/powerpc/platforms/83xx/mpc832x_rdb.c | 1 -
> arch/powerpc/platforms/83xx/mpc836x_mds.c | 1 -
> arch/powerpc/platforms/83xx/mpc836x_rdk.c | 1 -
> arch/powerpc/platforms/85xx/corenet_generic.c | 10 -
> arch/powerpc/platforms/85xx/mpc85xx_mds.c | 15 -
> arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 17 -
> arch/powerpc/platforms/85xx/twr_p102x.c| 15 -
> drivers/irqchip/Makefile | 1 +
> drivers/{soc/fsl/qe/qe_ic.c => irqchip/irq-qeic.c} | 423
> +++--
> drivers/soc/fsl/qe/Makefile| 2 +-
> drivers/soc/fsl/qe/qe_ic.h | 103 -
> include/soc/fsl/qe/qe_ic.h | 139 ---
> 16 files changed, 231 insertions(+), 521 deletions(-) rename
> drivers/{soc/fsl/qe/qe_ic.c => irqchip/irq-qeic.c} (53%) delete mode 100644
> drivers/soc/fsl/qe/qe_ic.h delete mode 100644 include/soc/fsl/qe/qe_ic.h
>
> --
> 2.14.1
RE: [PATCH 1/8] ls1043ardb: add qe node to ls1043ardb
On 03/11/17 07:07, Marc Zyngier wrote: > -Original Message- > From: Marc Zyngier [mailto:marc.zyng...@arm.com] > Sent: Friday, November 03, 2017 7:07 PM > To: Qiang Zhao <qiang.z...@nxp.com>; t...@linutronix.de; > ja...@lakedaemon.net > Cc: linux-kernel@vger.kernel.org > Subject: Re: [PATCH 1/8] ls1043ardb: add qe node to ls1043ardb > > On 01/11/17 01:34, Zhao Qiang wrote: > > Signed-off-by: Zhao Qiang <qiang.z...@nxp.com> > > --- > > arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 16 ++ > > arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi| 66 > +++ > > 2 files changed, 82 insertions(+) > > This patch needs to gain a commit log, and be sent (together with the > following > one) to armsoc, as they deal with the platform DT files. > Sorry, This patchset has been superseded. Best Regards Qiang Zhao
RE: [PATCH 1/8] ls1043ardb: add qe node to ls1043ardb
On 03/11/17 07:07, Marc Zyngier wrote: > -Original Message- > From: Marc Zyngier [mailto:marc.zyng...@arm.com] > Sent: Friday, November 03, 2017 7:07 PM > To: Qiang Zhao ; t...@linutronix.de; > ja...@lakedaemon.net > Cc: linux-kernel@vger.kernel.org > Subject: Re: [PATCH 1/8] ls1043ardb: add qe node to ls1043ardb > > On 01/11/17 01:34, Zhao Qiang wrote: > > Signed-off-by: Zhao Qiang > > --- > > arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 16 ++ > > arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi| 66 > +++ > > 2 files changed, 82 insertions(+) > > This patch needs to gain a commit log, and be sent (together with the > following > one) to armsoc, as they deal with the platform DT files. > Sorry, This patchset has been superseded. Best Regards Qiang Zhao
RE: [PATCH v10 0/4] this patchset is to remove PPCisms for QEIC
On Wed, 1 Nov 2017, Thomas Gleixner <t...@linutronix.de> wrote: > -Original Message- > From: Thomas Gleixner [mailto:t...@linutronix.de] > Sent: Thursday, November 02, 2017 1:10 AM > To: Qiang Zhao <qiang.z...@nxp.com> > Cc: Michael Ellerman <m...@ellerman.id.au>; Jason Cooper > <ja...@lakedaemon.net>; Marc Zyngier <marc.zyng...@arm.com>; > o...@buserror.net; linuxppc-...@lists.ozlabs.org; Xiaobo Xie > <xiaobo@nxp.com>; linux-kernel@vger.kernel.org > Subject: RE: [PATCH v10 0/4] this patchset is to remove PPCisms for QEIC > > On Wed, 1 Nov 2017, Qiang Zhao wrote: > > Michael Ellerman <m...@ellerman.id.au> wrote > > > > > > Qiang Zhao <qiang.z...@nxp.com> writes: > > > > > > > Hi all, > > > > > > > > Could anybody review this patchset and take action on them? Thank you! > > > > > > Who maintains this? I don't actually know, it's not powerpc code, or is > > > it? > > > > Yes, it's not powerpc code, it is irqchip code, maintained by Thomas, Jason > > and > Marc according to MAINTAINERS file. > > > > Hi Thomas, Jason and Marc, > > > > Could you keep an eye on this patchset? Thank you! > > It's on my radar, but I have zero capacity at the moment. Hopefully Marc can > spare a few cycles. > > Thanks, > > tglx Thank you! Best Regards Qiang Zhao
RE: [PATCH v10 0/4] this patchset is to remove PPCisms for QEIC
On Wed, 1 Nov 2017, Thomas Gleixner wrote: > -Original Message- > From: Thomas Gleixner [mailto:t...@linutronix.de] > Sent: Thursday, November 02, 2017 1:10 AM > To: Qiang Zhao > Cc: Michael Ellerman ; Jason Cooper > ; Marc Zyngier ; > o...@buserror.net; linuxppc-...@lists.ozlabs.org; Xiaobo Xie > ; linux-kernel@vger.kernel.org > Subject: RE: [PATCH v10 0/4] this patchset is to remove PPCisms for QEIC > > On Wed, 1 Nov 2017, Qiang Zhao wrote: > > Michael Ellerman wrote > > > > > > Qiang Zhao writes: > > > > > > > Hi all, > > > > > > > > Could anybody review this patchset and take action on them? Thank you! > > > > > > Who maintains this? I don't actually know, it's not powerpc code, or is > > > it? > > > > Yes, it's not powerpc code, it is irqchip code, maintained by Thomas, Jason > > and > Marc according to MAINTAINERS file. > > > > Hi Thomas, Jason and Marc, > > > > Could you keep an eye on this patchset? Thank you! > > It's on my radar, but I have zero capacity at the moment. Hopefully Marc can > spare a few cycles. > > Thanks, > > tglx Thank you! Best Regards Qiang Zhao
RE: [PATCH v10 0/4] this patchset is to remove PPCisms for QEIC
Michael Ellerman <m...@ellerman.id.au> wrote > > Qiang Zhao <qiang.z...@nxp.com> writes: > > > Hi all, > > > > Could anybody review this patchset and take action on them? Thank you! > > Who maintains this? I don't actually know, it's not powerpc code, or is it? Yes, it's not powerpc code, it is irqchip code, maintained by Thomas, Jason and Marc according to MAINTAINERS file. Hi Thomas, Jason and Marc, Could you keep an eye on this patchset? Thank you! Best Regards Qiang Zhao
RE: [PATCH v10 0/4] this patchset is to remove PPCisms for QEIC
Michael Ellerman wrote > > Qiang Zhao writes: > > > Hi all, > > > > Could anybody review this patchset and take action on them? Thank you! > > Who maintains this? I don't actually know, it's not powerpc code, or is it? Yes, it's not powerpc code, it is irqchip code, maintained by Thomas, Jason and Marc according to MAINTAINERS file. Hi Thomas, Jason and Marc, Could you keep an eye on this patchset? Thank you! Best Regards Qiang Zhao
RE: [PATCH v10 0/4] this patchset is to remove PPCisms for QEIC
Hi all,
Could anybody review this patchset and take action on them? Thank you!
Best Regards
Qiang Zhao
> > -Original Message-
> > From: Zhao Qiang [mailto:qiang.z...@nxp.com]
> > Sent: Monday, August 07, 2017 11:07 AM
> > To: t...@linutronix.de
> > Cc: o...@buserror.net; Xiaobo Xie <xiaobo@nxp.com>; linux-
> > ker...@vger.kernel.org; linuxppc-...@lists.ozlabs.org; Qiang Zhao
> > <qiang.z...@nxp.com>
> > Subject: [PATCH v10 0/4] this patchset is to remove PPCisms for QEIC
> >
> > QEIC is supported more than just powerpc boards, so remove PPCisms.
> >
> > changelog:
> > Changes for v8:
> > - use IRQCHIP_DECLARE() instead of subsys_initcall in qeic driver
> > - remove include/soc/fsl/qe/qe_ic.h
> > Changes for v9:
> > - rebase
> > - fix the compile issue when apply the second patch, in fact, there
> > was no compile issue
> > when apply all the patches of this patchset
> > Changes for v10:
> > - simplify codes, remove duplicated codes
> >
> > Zhao Qiang (4):
> > irqchip/qeic: move qeic driver from drivers/soc/fsl/qe
> > Changes for v2:
> > - modify the subject and commit msg
> > Changes for v3:
> > - merge .h file to .c, rename it with irq-qeic.c
> > Changes for v4:
> > - modify comments
> > Changes for v5:
> > - disable rename detection
> > Changes for v6:
> > - rebase
> > Changes for v7:
> > - na
> >
> > irqchip/qeic: merge qeic init code from platforms to a common function
> > Changes for v2:
> > - modify subject and commit msg
> > - add check for qeic by type
> > Changes for v3:
> > - na
> > Changes for v4:
> > - na
> > Changes for v5:
> > - na
> > Changes for v6:
> > - rebase
> > Changes for v7:
> > - na
> > Changes for v8:
> > - use IRQCHIP_DECLARE() instead of subsys_initcall
> >
> > irqchip/qeic: merge qeic_of_init into qe_ic_init
> > Changes for v2:
> > - modify subject and commit msg
> > - return 0 and add put node when return in qe_ic_init
> > Changes for v3:
> > - na
> > Changes for v4:
> > - na
> > Changes for v5:
> > - na
> > Changes for v6:
> > - rebase
> > Changes for v7:
> > - na
> >
> > irqchip/qeic: remove PPCisms for QEIC
> > Changes for v6:
> > - new added
> > Changes for v7:
> > - fix warning
> > Changes for v8:
> > - remove include/soc/fsl/qe/qe_ic.h
> >
> > Zhao Qiang (4):
> > irqchip/qeic: move qeic driver from drivers/soc/fsl/qe
> > irqchip/qeic: merge qeic init code from platforms to a common function
> > irqchip/qeic: merge qeic_of_init into qe_ic_init
> > irqchip/qeic: remove PPCisms for QEIC
> >
> > MAINTAINERS| 6 +
> > arch/powerpc/platforms/83xx/km83xx.c | 1 -
> > arch/powerpc/platforms/83xx/misc.c | 16 -
> > arch/powerpc/platforms/83xx/mpc832x_mds.c | 1 -
> > arch/powerpc/platforms/83xx/mpc832x_rdb.c | 1 -
> > arch/powerpc/platforms/83xx/mpc836x_mds.c | 1 -
> > arch/powerpc/platforms/83xx/mpc836x_rdk.c | 1 -
> > arch/powerpc/platforms/85xx/corenet_generic.c | 10 -
> > arch/powerpc/platforms/85xx/mpc85xx_mds.c | 15 -
> > arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 17 -
> > arch/powerpc/platforms/85xx/twr_p102x.c| 15 -
> > drivers/irqchip/Makefile | 1 +
> > drivers/{soc/fsl/qe/qe_ic.c => irqchip/irq-qeic.c} | 358
> > -
> > drivers/soc/fsl/qe/Makefile| 2 +-
> > drivers/soc/fsl/qe/qe_ic.h | 103 --
> > include/soc/fsl/qe/qe_ic.h | 139
> > 16 files changed, 218 insertions(+), 469 deletions(-) rename
> > drivers/{soc/fsl/qe/qe_ic.c => irqchip/irq-qeic.c} (58%) delete mode
> > 100644 drivers/soc/fsl/qe/qe_ic.h delete mode 100644
> > include/soc/fsl/qe/qe_ic.h
> >
> > --
> > 2.1.0.27.g96db324
RE: [PATCH v10 0/4] this patchset is to remove PPCisms for QEIC
Hi all,
Could anybody review this patchset and take action on them? Thank you!
Best Regards
Qiang Zhao
> > -Original Message-
> > From: Zhao Qiang [mailto:qiang.z...@nxp.com]
> > Sent: Monday, August 07, 2017 11:07 AM
> > To: t...@linutronix.de
> > Cc: o...@buserror.net; Xiaobo Xie ; linux-
> > ker...@vger.kernel.org; linuxppc-...@lists.ozlabs.org; Qiang Zhao
> >
> > Subject: [PATCH v10 0/4] this patchset is to remove PPCisms for QEIC
> >
> > QEIC is supported more than just powerpc boards, so remove PPCisms.
> >
> > changelog:
> > Changes for v8:
> > - use IRQCHIP_DECLARE() instead of subsys_initcall in qeic driver
> > - remove include/soc/fsl/qe/qe_ic.h
> > Changes for v9:
> > - rebase
> > - fix the compile issue when apply the second patch, in fact, there
> > was no compile issue
> > when apply all the patches of this patchset
> > Changes for v10:
> > - simplify codes, remove duplicated codes
> >
> > Zhao Qiang (4):
> > irqchip/qeic: move qeic driver from drivers/soc/fsl/qe
> > Changes for v2:
> > - modify the subject and commit msg
> > Changes for v3:
> > - merge .h file to .c, rename it with irq-qeic.c
> > Changes for v4:
> > - modify comments
> > Changes for v5:
> > - disable rename detection
> > Changes for v6:
> > - rebase
> > Changes for v7:
> > - na
> >
> > irqchip/qeic: merge qeic init code from platforms to a common function
> > Changes for v2:
> > - modify subject and commit msg
> > - add check for qeic by type
> > Changes for v3:
> > - na
> > Changes for v4:
> > - na
> > Changes for v5:
> > - na
> > Changes for v6:
> > - rebase
> > Changes for v7:
> > - na
> > Changes for v8:
> > - use IRQCHIP_DECLARE() instead of subsys_initcall
> >
> > irqchip/qeic: merge qeic_of_init into qe_ic_init
> > Changes for v2:
> > - modify subject and commit msg
> > - return 0 and add put node when return in qe_ic_init
> > Changes for v3:
> > - na
> > Changes for v4:
> > - na
> > Changes for v5:
> > - na
> > Changes for v6:
> > - rebase
> > Changes for v7:
> > - na
> >
> > irqchip/qeic: remove PPCisms for QEIC
> > Changes for v6:
> > - new added
> > Changes for v7:
> > - fix warning
> > Changes for v8:
> > - remove include/soc/fsl/qe/qe_ic.h
> >
> > Zhao Qiang (4):
> > irqchip/qeic: move qeic driver from drivers/soc/fsl/qe
> > irqchip/qeic: merge qeic init code from platforms to a common function
> > irqchip/qeic: merge qeic_of_init into qe_ic_init
> > irqchip/qeic: remove PPCisms for QEIC
> >
> > MAINTAINERS| 6 +
> > arch/powerpc/platforms/83xx/km83xx.c | 1 -
> > arch/powerpc/platforms/83xx/misc.c | 16 -
> > arch/powerpc/platforms/83xx/mpc832x_mds.c | 1 -
> > arch/powerpc/platforms/83xx/mpc832x_rdb.c | 1 -
> > arch/powerpc/platforms/83xx/mpc836x_mds.c | 1 -
> > arch/powerpc/platforms/83xx/mpc836x_rdk.c | 1 -
> > arch/powerpc/platforms/85xx/corenet_generic.c | 10 -
> > arch/powerpc/platforms/85xx/mpc85xx_mds.c | 15 -
> > arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 17 -
> > arch/powerpc/platforms/85xx/twr_p102x.c| 15 -
> > drivers/irqchip/Makefile | 1 +
> > drivers/{soc/fsl/qe/qe_ic.c => irqchip/irq-qeic.c} | 358
> > -
> > drivers/soc/fsl/qe/Makefile| 2 +-
> > drivers/soc/fsl/qe/qe_ic.h | 103 --
> > include/soc/fsl/qe/qe_ic.h | 139
> > 16 files changed, 218 insertions(+), 469 deletions(-) rename
> > drivers/{soc/fsl/qe/qe_ic.c => irqchip/irq-qeic.c} (58%) delete mode
> > 100644 drivers/soc/fsl/qe/qe_ic.h delete mode 100644
> > include/soc/fsl/qe/qe_ic.h
> >
> > --
> > 2.1.0.27.g96db324
RE: [PATCH v10 0/4] this patchset is to remove PPCisms for QEIC
Hi all,
Could anybody review this patchset and take action on them? Thank you!
Best Regards
Qiang Zhao
> -Original Message-
> From: Zhao Qiang [mailto:qiang.z...@nxp.com]
> Sent: Monday, August 07, 2017 11:07 AM
> To: t...@linutronix.de
> Cc: o...@buserror.net; Xiaobo Xie <xiaobo@nxp.com>; linux-
> ker...@vger.kernel.org; linuxppc-...@lists.ozlabs.org; Qiang Zhao
> <qiang.z...@nxp.com>
> Subject: [PATCH v10 0/4] this patchset is to remove PPCisms for QEIC
>
> QEIC is supported more than just powerpc boards, so remove PPCisms.
>
> changelog:
> Changes for v8:
> - use IRQCHIP_DECLARE() instead of subsys_initcall in qeic driver
> - remove include/soc/fsl/qe/qe_ic.h
> Changes for v9:
> - rebase
> - fix the compile issue when apply the second patch, in fact, there was
> no compile issue
> when apply all the patches of this patchset
> Changes for v10:
> - simplify codes, remove duplicated codes
>
> Zhao Qiang (4):
> irqchip/qeic: move qeic driver from drivers/soc/fsl/qe
> Changes for v2:
> - modify the subject and commit msg
> Changes for v3:
> - merge .h file to .c, rename it with irq-qeic.c
> Changes for v4:
> - modify comments
> Changes for v5:
> - disable rename detection
> Changes for v6:
> - rebase
> Changes for v7:
> - na
>
> irqchip/qeic: merge qeic init code from platforms to a common function
> Changes for v2:
> - modify subject and commit msg
> - add check for qeic by type
> Changes for v3:
> - na
> Changes for v4:
> - na
> Changes for v5:
> - na
> Changes for v6:
> - rebase
> Changes for v7:
> - na
> Changes for v8:
> - use IRQCHIP_DECLARE() instead of subsys_initcall
>
> irqchip/qeic: merge qeic_of_init into qe_ic_init
> Changes for v2:
> - modify subject and commit msg
> - return 0 and add put node when return in qe_ic_init
> Changes for v3:
> - na
> Changes for v4:
> - na
> Changes for v5:
> - na
> Changes for v6:
> - rebase
> Changes for v7:
> - na
>
> irqchip/qeic: remove PPCisms for QEIC
> Changes for v6:
> - new added
> Changes for v7:
> - fix warning
> Changes for v8:
> - remove include/soc/fsl/qe/qe_ic.h
>
> Zhao Qiang (4):
> irqchip/qeic: move qeic driver from drivers/soc/fsl/qe
> irqchip/qeic: merge qeic init code from platforms to a common function
> irqchip/qeic: merge qeic_of_init into qe_ic_init
> irqchip/qeic: remove PPCisms for QEIC
>
> MAINTAINERS| 6 +
> arch/powerpc/platforms/83xx/km83xx.c | 1 -
> arch/powerpc/platforms/83xx/misc.c | 16 -
> arch/powerpc/platforms/83xx/mpc832x_mds.c | 1 -
> arch/powerpc/platforms/83xx/mpc832x_rdb.c | 1 -
> arch/powerpc/platforms/83xx/mpc836x_mds.c | 1 -
> arch/powerpc/platforms/83xx/mpc836x_rdk.c | 1 -
> arch/powerpc/platforms/85xx/corenet_generic.c | 10 -
> arch/powerpc/platforms/85xx/mpc85xx_mds.c | 15 -
> arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 17 -
> arch/powerpc/platforms/85xx/twr_p102x.c| 15 -
> drivers/irqchip/Makefile | 1 +
> drivers/{soc/fsl/qe/qe_ic.c => irqchip/irq-qeic.c} | 358
> -
> drivers/soc/fsl/qe/Makefile| 2 +-
> drivers/soc/fsl/qe/qe_ic.h | 103 --
> include/soc/fsl/qe/qe_ic.h | 139
> 16 files changed, 218 insertions(+), 469 deletions(-) rename
> drivers/{soc/fsl/qe/qe_ic.c => irqchip/irq-qeic.c} (58%) delete mode 100644
> drivers/soc/fsl/qe/qe_ic.h delete mode 100644 include/soc/fsl/qe/qe_ic.h
>
> --
> 2.1.0.27.g96db324
RE: [PATCH v10 0/4] this patchset is to remove PPCisms for QEIC
Hi all,
Could anybody review this patchset and take action on them? Thank you!
Best Regards
Qiang Zhao
> -Original Message-
> From: Zhao Qiang [mailto:qiang.z...@nxp.com]
> Sent: Monday, August 07, 2017 11:07 AM
> To: t...@linutronix.de
> Cc: o...@buserror.net; Xiaobo Xie ; linux-
> ker...@vger.kernel.org; linuxppc-...@lists.ozlabs.org; Qiang Zhao
>
> Subject: [PATCH v10 0/4] this patchset is to remove PPCisms for QEIC
>
> QEIC is supported more than just powerpc boards, so remove PPCisms.
>
> changelog:
> Changes for v8:
> - use IRQCHIP_DECLARE() instead of subsys_initcall in qeic driver
> - remove include/soc/fsl/qe/qe_ic.h
> Changes for v9:
> - rebase
> - fix the compile issue when apply the second patch, in fact, there was
> no compile issue
> when apply all the patches of this patchset
> Changes for v10:
> - simplify codes, remove duplicated codes
>
> Zhao Qiang (4):
> irqchip/qeic: move qeic driver from drivers/soc/fsl/qe
> Changes for v2:
> - modify the subject and commit msg
> Changes for v3:
> - merge .h file to .c, rename it with irq-qeic.c
> Changes for v4:
> - modify comments
> Changes for v5:
> - disable rename detection
> Changes for v6:
> - rebase
> Changes for v7:
> - na
>
> irqchip/qeic: merge qeic init code from platforms to a common function
> Changes for v2:
> - modify subject and commit msg
> - add check for qeic by type
> Changes for v3:
> - na
> Changes for v4:
> - na
> Changes for v5:
> - na
> Changes for v6:
> - rebase
> Changes for v7:
> - na
> Changes for v8:
> - use IRQCHIP_DECLARE() instead of subsys_initcall
>
> irqchip/qeic: merge qeic_of_init into qe_ic_init
> Changes for v2:
> - modify subject and commit msg
> - return 0 and add put node when return in qe_ic_init
> Changes for v3:
> - na
> Changes for v4:
> - na
> Changes for v5:
> - na
> Changes for v6:
> - rebase
> Changes for v7:
> - na
>
> irqchip/qeic: remove PPCisms for QEIC
> Changes for v6:
> - new added
> Changes for v7:
> - fix warning
> Changes for v8:
> - remove include/soc/fsl/qe/qe_ic.h
>
> Zhao Qiang (4):
> irqchip/qeic: move qeic driver from drivers/soc/fsl/qe
> irqchip/qeic: merge qeic init code from platforms to a common function
> irqchip/qeic: merge qeic_of_init into qe_ic_init
> irqchip/qeic: remove PPCisms for QEIC
>
> MAINTAINERS| 6 +
> arch/powerpc/platforms/83xx/km83xx.c | 1 -
> arch/powerpc/platforms/83xx/misc.c | 16 -
> arch/powerpc/platforms/83xx/mpc832x_mds.c | 1 -
> arch/powerpc/platforms/83xx/mpc832x_rdb.c | 1 -
> arch/powerpc/platforms/83xx/mpc836x_mds.c | 1 -
> arch/powerpc/platforms/83xx/mpc836x_rdk.c | 1 -
> arch/powerpc/platforms/85xx/corenet_generic.c | 10 -
> arch/powerpc/platforms/85xx/mpc85xx_mds.c | 15 -
> arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 17 -
> arch/powerpc/platforms/85xx/twr_p102x.c| 15 -
> drivers/irqchip/Makefile | 1 +
> drivers/{soc/fsl/qe/qe_ic.c => irqchip/irq-qeic.c} | 358
> -
> drivers/soc/fsl/qe/Makefile| 2 +-
> drivers/soc/fsl/qe/qe_ic.h | 103 --
> include/soc/fsl/qe/qe_ic.h | 139
> 16 files changed, 218 insertions(+), 469 deletions(-) rename
> drivers/{soc/fsl/qe/qe_ic.c => irqchip/irq-qeic.c} (58%) delete mode 100644
> drivers/soc/fsl/qe/qe_ic.h delete mode 100644 include/soc/fsl/qe/qe_ic.h
>
> --
> 2.1.0.27.g96db324
RE: [PATCH v10 4/4] irqchip/qeic: remove PPCisms for QEIC
On Tue 8/8/2017 6:05 PM, Michael Ellerman <m...@ellerman.id.au> wrote: > -Original Message- > From: Michael Ellerman [mailto:m...@ellerman.id.au] > Sent: Tuesday, August 08, 2017 6:05 PM > To: Qiang Zhao <qiang.z...@nxp.com>; t...@linutronix.de > Cc: o...@buserror.net; linuxppc-...@lists.ozlabs.org; Xiaobo Xie > <xiaobo@nxp.com>; linux-kernel@vger.kernel.org > Subject: RE: [PATCH v10 4/4] irqchip/qeic: remove PPCisms for QEIC > > Qiang Zhao <qiang.z...@nxp.com> writes: > > > On Mon 8/7/2017 3:02 PM, Michael Ellerman <m...@ellerman.id.au> wrote: > > > >> -Original Message- > >> From: Michael Ellerman [mailto:m...@ellerman.id.au] > >> Sent: Monday, August 07, 2017 3:02 PM > >> To: Qiang Zhao <qiang.z...@nxp.com>; t...@linutronix.de > >> Cc: o...@buserror.net; Qiang Zhao <qiang.z...@nxp.com>; linuxppc- > >> d...@lists.ozlabs.org; Xiaobo Xie <xiaobo@nxp.com>; linux- > >> ker...@vger.kernel.org > >> Subject: Re: [PATCH v10 4/4] irqchip/qeic: remove PPCisms for QEIC > >> > >> Zhao Qiang <qiang.z...@nxp.com> writes: > >> > >> > QEIC was supported on PowerPC, and dependent on PPC, Now it is > >> > supported on other platforms, so remove PPCisms. > >> > > >> > Signed-off-by: Zhao Qiang <qiang.z...@nxp.com> > >> > --- > >> > arch/powerpc/platforms/83xx/km83xx.c | 1 - > >> > arch/powerpc/platforms/83xx/misc.c| 1 - > >> > arch/powerpc/platforms/83xx/mpc832x_mds.c | 1 - > >> > arch/powerpc/platforms/83xx/mpc832x_rdb.c | 1 - > >> > arch/powerpc/platforms/83xx/mpc836x_mds.c | 1 - > >> > arch/powerpc/platforms/83xx/mpc836x_rdk.c | 1 - > >> > arch/powerpc/platforms/85xx/corenet_generic.c | 1 - > >> > arch/powerpc/platforms/85xx/mpc85xx_mds.c | 1 - > >> > arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 1 - > >> > arch/powerpc/platforms/85xx/twr_p102x.c | 1 - > >> > drivers/irqchip/irq-qeic.c| 188 > >> > +++--- > >> > include/soc/fsl/qe/qe_ic.h| 132 -- > >> > 12 files changed, 80 insertions(+), 250 deletions(-) delete mode > >> > 100644 include/soc/fsl/qe/qe_ic.h > >> > > >> > diff --git a/arch/powerpc/platforms/83xx/km83xx.c > >> > b/arch/powerpc/platforms/83xx/km83xx.c > >> > index d8642a4..b1cef0a 100644 > >> > --- a/arch/powerpc/platforms/83xx/km83xx.c > >> > +++ b/arch/powerpc/platforms/83xx/km83xx.c > >> > @@ -38,7 +38,6 @@ > >> > #include > >> > #include > >> > #include > >> > -#include > >> > >> You deleted that file in patch 2. So didn't you just break the build > >> for the last two commits? > > > > Sorry, I am not sure what you said. Could you explain? > > Don't worry about it. I was confused by the fact that we have both: > > drivers/soc/fsl/qe/qe_ic.h > > and: > > include/soc/fsl/qe/qe_ic.h > > cheers I think this is a issue left over by history. In patch with commit id 7aa1aa6ecec2af19d9aa85430ce3e56119e21626, I just move them out from arch/powerpc. Maybe need to ask the original author why there are 2 qe_ic.h. Best Regards Qiang Zhao
RE: [PATCH v10 4/4] irqchip/qeic: remove PPCisms for QEIC
On Tue 8/8/2017 6:05 PM, Michael Ellerman wrote: > -Original Message- > From: Michael Ellerman [mailto:m...@ellerman.id.au] > Sent: Tuesday, August 08, 2017 6:05 PM > To: Qiang Zhao ; t...@linutronix.de > Cc: o...@buserror.net; linuxppc-...@lists.ozlabs.org; Xiaobo Xie > ; linux-kernel@vger.kernel.org > Subject: RE: [PATCH v10 4/4] irqchip/qeic: remove PPCisms for QEIC > > Qiang Zhao writes: > > > On Mon 8/7/2017 3:02 PM, Michael Ellerman wrote: > > > >> -Original Message- > >> From: Michael Ellerman [mailto:m...@ellerman.id.au] > >> Sent: Monday, August 07, 2017 3:02 PM > >> To: Qiang Zhao ; t...@linutronix.de > >> Cc: o...@buserror.net; Qiang Zhao ; linuxppc- > >> d...@lists.ozlabs.org; Xiaobo Xie ; linux- > >> ker...@vger.kernel.org > >> Subject: Re: [PATCH v10 4/4] irqchip/qeic: remove PPCisms for QEIC > >> > >> Zhao Qiang writes: > >> > >> > QEIC was supported on PowerPC, and dependent on PPC, Now it is > >> > supported on other platforms, so remove PPCisms. > >> > > >> > Signed-off-by: Zhao Qiang > >> > --- > >> > arch/powerpc/platforms/83xx/km83xx.c | 1 - > >> > arch/powerpc/platforms/83xx/misc.c| 1 - > >> > arch/powerpc/platforms/83xx/mpc832x_mds.c | 1 - > >> > arch/powerpc/platforms/83xx/mpc832x_rdb.c | 1 - > >> > arch/powerpc/platforms/83xx/mpc836x_mds.c | 1 - > >> > arch/powerpc/platforms/83xx/mpc836x_rdk.c | 1 - > >> > arch/powerpc/platforms/85xx/corenet_generic.c | 1 - > >> > arch/powerpc/platforms/85xx/mpc85xx_mds.c | 1 - > >> > arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 1 - > >> > arch/powerpc/platforms/85xx/twr_p102x.c | 1 - > >> > drivers/irqchip/irq-qeic.c| 188 > >> > +++--- > >> > include/soc/fsl/qe/qe_ic.h| 132 -- > >> > 12 files changed, 80 insertions(+), 250 deletions(-) delete mode > >> > 100644 include/soc/fsl/qe/qe_ic.h > >> > > >> > diff --git a/arch/powerpc/platforms/83xx/km83xx.c > >> > b/arch/powerpc/platforms/83xx/km83xx.c > >> > index d8642a4..b1cef0a 100644 > >> > --- a/arch/powerpc/platforms/83xx/km83xx.c > >> > +++ b/arch/powerpc/platforms/83xx/km83xx.c > >> > @@ -38,7 +38,6 @@ > >> > #include > >> > #include > >> > #include > >> > -#include > >> > >> You deleted that file in patch 2. So didn't you just break the build > >> for the last two commits? > > > > Sorry, I am not sure what you said. Could you explain? > > Don't worry about it. I was confused by the fact that we have both: > > drivers/soc/fsl/qe/qe_ic.h > > and: > > include/soc/fsl/qe/qe_ic.h > > cheers I think this is a issue left over by history. In patch with commit id 7aa1aa6ecec2af19d9aa85430ce3e56119e21626, I just move them out from arch/powerpc. Maybe need to ask the original author why there are 2 qe_ic.h. Best Regards Qiang Zhao
RE: [PATCH v10 4/4] irqchip/qeic: remove PPCisms for QEIC
On Mon 8/7/2017 3:02 PM, Michael Ellerman <m...@ellerman.id.au> wrote: > -Original Message- > From: Michael Ellerman [mailto:m...@ellerman.id.au] > Sent: Monday, August 07, 2017 3:02 PM > To: Qiang Zhao <qiang.z...@nxp.com>; t...@linutronix.de > Cc: o...@buserror.net; Qiang Zhao <qiang.z...@nxp.com>; linuxppc- > d...@lists.ozlabs.org; Xiaobo Xie <xiaobo@nxp.com>; linux- > ker...@vger.kernel.org > Subject: Re: [PATCH v10 4/4] irqchip/qeic: remove PPCisms for QEIC > > Zhao Qiang <qiang.z...@nxp.com> writes: > > > QEIC was supported on PowerPC, and dependent on PPC, Now it is > > supported on other platforms, so remove PPCisms. > > > > Signed-off-by: Zhao Qiang <qiang.z...@nxp.com> > > --- > > arch/powerpc/platforms/83xx/km83xx.c | 1 - > > arch/powerpc/platforms/83xx/misc.c| 1 - > > arch/powerpc/platforms/83xx/mpc832x_mds.c | 1 - > > arch/powerpc/platforms/83xx/mpc832x_rdb.c | 1 - > > arch/powerpc/platforms/83xx/mpc836x_mds.c | 1 - > > arch/powerpc/platforms/83xx/mpc836x_rdk.c | 1 - > > arch/powerpc/platforms/85xx/corenet_generic.c | 1 - > > arch/powerpc/platforms/85xx/mpc85xx_mds.c | 1 - > > arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 1 - > > arch/powerpc/platforms/85xx/twr_p102x.c | 1 - > > drivers/irqchip/irq-qeic.c| 188 > > +++--- > > include/soc/fsl/qe/qe_ic.h| 132 -- > > 12 files changed, 80 insertions(+), 250 deletions(-) delete mode > > 100644 include/soc/fsl/qe/qe_ic.h > > > > diff --git a/arch/powerpc/platforms/83xx/km83xx.c > > b/arch/powerpc/platforms/83xx/km83xx.c > > index d8642a4..b1cef0a 100644 > > --- a/arch/powerpc/platforms/83xx/km83xx.c > > +++ b/arch/powerpc/platforms/83xx/km83xx.c > > @@ -38,7 +38,6 @@ > > #include > > #include > > #include > > -#include > > You deleted that file in patch 2. So didn't you just break the build for the > last two > commits? Sorry, I am not sure what you said. Could you explain? Thank you! BR Qiang Zhao
RE: [PATCH v10 4/4] irqchip/qeic: remove PPCisms for QEIC
On Mon 8/7/2017 3:02 PM, Michael Ellerman wrote: > -Original Message- > From: Michael Ellerman [mailto:m...@ellerman.id.au] > Sent: Monday, August 07, 2017 3:02 PM > To: Qiang Zhao ; t...@linutronix.de > Cc: o...@buserror.net; Qiang Zhao ; linuxppc- > d...@lists.ozlabs.org; Xiaobo Xie ; linux- > ker...@vger.kernel.org > Subject: Re: [PATCH v10 4/4] irqchip/qeic: remove PPCisms for QEIC > > Zhao Qiang writes: > > > QEIC was supported on PowerPC, and dependent on PPC, Now it is > > supported on other platforms, so remove PPCisms. > > > > Signed-off-by: Zhao Qiang > > --- > > arch/powerpc/platforms/83xx/km83xx.c | 1 - > > arch/powerpc/platforms/83xx/misc.c| 1 - > > arch/powerpc/platforms/83xx/mpc832x_mds.c | 1 - > > arch/powerpc/platforms/83xx/mpc832x_rdb.c | 1 - > > arch/powerpc/platforms/83xx/mpc836x_mds.c | 1 - > > arch/powerpc/platforms/83xx/mpc836x_rdk.c | 1 - > > arch/powerpc/platforms/85xx/corenet_generic.c | 1 - > > arch/powerpc/platforms/85xx/mpc85xx_mds.c | 1 - > > arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 1 - > > arch/powerpc/platforms/85xx/twr_p102x.c | 1 - > > drivers/irqchip/irq-qeic.c| 188 > > +++--- > > include/soc/fsl/qe/qe_ic.h| 132 -- > > 12 files changed, 80 insertions(+), 250 deletions(-) delete mode > > 100644 include/soc/fsl/qe/qe_ic.h > > > > diff --git a/arch/powerpc/platforms/83xx/km83xx.c > > b/arch/powerpc/platforms/83xx/km83xx.c > > index d8642a4..b1cef0a 100644 > > --- a/arch/powerpc/platforms/83xx/km83xx.c > > +++ b/arch/powerpc/platforms/83xx/km83xx.c > > @@ -38,7 +38,6 @@ > > #include > > #include > > #include > > -#include > > You deleted that file in patch 2. So didn't you just break the build for the > last two > commits? Sorry, I am not sure what you said. Could you explain? Thank you! BR Qiang Zhao
QRE: [PATCH v2] qe: fix compile issue for arm64
Michael Ellerman <m...@ellerman.id.au> wrote: > -Original Message- > From: Michael Ellerman [mailto:m...@ellerman.id.au] > Sent: Monday, July 31, 2017 6:37 PM > To: Qiang Zhao <qiang.z...@nxp.com>; o...@buserror.net > Cc: valentin.longch...@keymile.com; linuxppc-...@lists.ozlabs.org; linux- > ker...@vger.kernel.org > Subject: RE: [PATCH v2] qe: fix compile issue for arm64 > > Qiang Zhao <qiang.z...@nxp.com> writes: > > > Fri 7/28/2017 2:14 PM, Michael Ellerman <m...@ellerman.id.au> wrote: > > > >> -Original Message- > >> From: Michael Ellerman [mailto:m...@ellerman.id.au] > >> Sent: Friday, July 28, 2017 2:14 PM > >> To: Qiang Zhao <qiang.z...@nxp.com>; o...@buserror.net > >> Cc: valentin.longch...@keymile.com; linuxppc-...@lists.ozlabs.org; > >> linux- ker...@vger.kernel.org; Qiang Zhao <qiang.z...@nxp.com> > >> Subject: Re: [PATCH v2] qe: fix compile issue for arm64 > >> > >> Zhao Qiang <qiang.z...@nxp.com> writes: > >> > >> > Signed-off-by: Zhao Qiang <qiang.z...@nxp.com> > >> > --- > >> > Changes for v2: > >> > - include all Errata QE_General4 in #ifdef > >> > > >> > drivers/soc/fsl/qe/qe.c | 2 ++ > >> > 1 file changed, 2 insertions(+) > >> > >> AFAICS this driver can only be built on PPC, what am I missing? > >> > >> config QUICC_ENGINE > >> bool "Freescale QUICC Engine (QE) Support" > >> depends on FSL_SOC && PPC32 > >> > >> cheers > > > > I sent another patchset to support it on arm64. > > Where? I don't see it. > > Shouldn't this patch be part of that series? Otherwise when that series is > merged > the build will break on arm64. > You are correct, thanks for your recommend. I will add this patch to the patchset. Thank you! BR Qiang Zhao
QRE: [PATCH v2] qe: fix compile issue for arm64
Michael Ellerman wrote: > -Original Message- > From: Michael Ellerman [mailto:m...@ellerman.id.au] > Sent: Monday, July 31, 2017 6:37 PM > To: Qiang Zhao ; o...@buserror.net > Cc: valentin.longch...@keymile.com; linuxppc-...@lists.ozlabs.org; linux- > ker...@vger.kernel.org > Subject: RE: [PATCH v2] qe: fix compile issue for arm64 > > Qiang Zhao writes: > > > Fri 7/28/2017 2:14 PM, Michael Ellerman wrote: > > > >> -Original Message- > >> From: Michael Ellerman [mailto:m...@ellerman.id.au] > >> Sent: Friday, July 28, 2017 2:14 PM > >> To: Qiang Zhao ; o...@buserror.net > >> Cc: valentin.longch...@keymile.com; linuxppc-...@lists.ozlabs.org; > >> linux- ker...@vger.kernel.org; Qiang Zhao > >> Subject: Re: [PATCH v2] qe: fix compile issue for arm64 > >> > >> Zhao Qiang writes: > >> > >> > Signed-off-by: Zhao Qiang > >> > --- > >> > Changes for v2: > >> > - include all Errata QE_General4 in #ifdef > >> > > >> > drivers/soc/fsl/qe/qe.c | 2 ++ > >> > 1 file changed, 2 insertions(+) > >> > >> AFAICS this driver can only be built on PPC, what am I missing? > >> > >> config QUICC_ENGINE > >> bool "Freescale QUICC Engine (QE) Support" > >> depends on FSL_SOC && PPC32 > >> > >> cheers > > > > I sent another patchset to support it on arm64. > > Where? I don't see it. > > Shouldn't this patch be part of that series? Otherwise when that series is > merged > the build will break on arm64. > You are correct, thanks for your recommend. I will add this patch to the patchset. Thank you! BR Qiang Zhao
RE: [PATCH v2] qe: fix compile issue for arm64
Fri 7/28/2017 2:14 PM, Michael Ellerman <m...@ellerman.id.au> wrote: > -Original Message- > From: Michael Ellerman [mailto:m...@ellerman.id.au] > Sent: Friday, July 28, 2017 2:14 PM > To: Qiang Zhao <qiang.z...@nxp.com>; o...@buserror.net > Cc: valentin.longch...@keymile.com; linuxppc-...@lists.ozlabs.org; linux- > ker...@vger.kernel.org; Qiang Zhao <qiang.z...@nxp.com> > Subject: Re: [PATCH v2] qe: fix compile issue for arm64 > > Zhao Qiang <qiang.z...@nxp.com> writes: > > > Signed-off-by: Zhao Qiang <qiang.z...@nxp.com> > > --- > > Changes for v2: > > - include all Errata QE_General4 in #ifdef > > > > drivers/soc/fsl/qe/qe.c | 2 ++ > > 1 file changed, 2 insertions(+) > > AFAICS this driver can only be built on PPC, what am I missing? > > config QUICC_ENGINE > bool "Freescale QUICC Engine (QE) Support" > depends on FSL_SOC && PPC32 > > cheers I sent another patchset to support it on arm64. Thank you! Best Regards Qiang Zhao
RE: [PATCH v2] qe: fix compile issue for arm64
Fri 7/28/2017 2:14 PM, Michael Ellerman wrote: > -Original Message- > From: Michael Ellerman [mailto:m...@ellerman.id.au] > Sent: Friday, July 28, 2017 2:14 PM > To: Qiang Zhao ; o...@buserror.net > Cc: valentin.longch...@keymile.com; linuxppc-...@lists.ozlabs.org; linux- > ker...@vger.kernel.org; Qiang Zhao > Subject: Re: [PATCH v2] qe: fix compile issue for arm64 > > Zhao Qiang writes: > > > Signed-off-by: Zhao Qiang > > --- > > Changes for v2: > > - include all Errata QE_General4 in #ifdef > > > > drivers/soc/fsl/qe/qe.c | 2 ++ > > 1 file changed, 2 insertions(+) > > AFAICS this driver can only be built on PPC, what am I missing? > > config QUICC_ENGINE > bool "Freescale QUICC Engine (QE) Support" > depends on FSL_SOC && PPC32 > > cheers I sent another patchset to support it on arm64. Thank you! Best Regards Qiang Zhao
RE: [PATCH] qe: fix compile issue for arm64
On Fri, 2017-07-21 at 02:34PM, Michael Ellerman <m...@ellerman.id.au> wrote: > -Original Message- > From: Michael Ellerman [mailto:m...@ellerman.id.au] > Sent: Friday, July 21, 2017 2:34 PM > To: Qiang Zhao <qiang.z...@nxp.com>; o...@buserror.net > Cc: valentin.longch...@keymile.com; linuxppc-...@lists.ozlabs.org; linux- > ker...@vger.kernel.org; Qiang Zhao <qiang.z...@nxp.com> > Subject: Re: [PATCH] qe: fix compile issue for arm64 > > Zhao Qiang <qiang.z...@nxp.com> writes: > > > Signed-off-by: Zhao Qiang <qiang.z...@nxp.com> > > --- > > drivers/soc/fsl/qe/qe.c | 2 ++ > > 1 file changed, 2 insertions(+) > > > > diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c index > > 2ef6fc6..d48fa4a 100644 > > --- a/drivers/soc/fsl/qe/qe.c > > +++ b/drivers/soc/fsl/qe/qe.c > > @@ -229,7 +229,9 @@ int qe_setbrg(enum qe_clock brg, unsigned int rate, > unsigned int multiplier) > > /* Errata QE_General4, which affects some MPC832x and MPC836x > SOCs, says > >that the BRG divisor must be even if you're not using divide-by-16 > >mode. */ > > +#ifdef CONFIG_PPC > > if (pvr_version_is(PVR_VER_836x) || pvr_version_is(PVR_VER_832x) > > +#endif > > if (!div16 && (divisor & 1) && (divisor > 3)) > > divisor++; > > Are you sure that's what you want to do on arm64 ? Is there any problem? Best Regards Qiang Zhao
RE: [PATCH] qe: fix compile issue for arm64
On Fri, 2017-07-21 at 02:34PM, Michael Ellerman wrote: > -Original Message- > From: Michael Ellerman [mailto:m...@ellerman.id.au] > Sent: Friday, July 21, 2017 2:34 PM > To: Qiang Zhao ; o...@buserror.net > Cc: valentin.longch...@keymile.com; linuxppc-...@lists.ozlabs.org; linux- > ker...@vger.kernel.org; Qiang Zhao > Subject: Re: [PATCH] qe: fix compile issue for arm64 > > Zhao Qiang writes: > > > Signed-off-by: Zhao Qiang > > --- > > drivers/soc/fsl/qe/qe.c | 2 ++ > > 1 file changed, 2 insertions(+) > > > > diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c index > > 2ef6fc6..d48fa4a 100644 > > --- a/drivers/soc/fsl/qe/qe.c > > +++ b/drivers/soc/fsl/qe/qe.c > > @@ -229,7 +229,9 @@ int qe_setbrg(enum qe_clock brg, unsigned int rate, > unsigned int multiplier) > > /* Errata QE_General4, which affects some MPC832x and MPC836x > SOCs, says > >that the BRG divisor must be even if you're not using divide-by-16 > >mode. */ > > +#ifdef CONFIG_PPC > > if (pvr_version_is(PVR_VER_836x) || pvr_version_is(PVR_VER_832x) > > +#endif > > if (!div16 && (divisor & 1) && (divisor > 3)) > > divisor++; > > Are you sure that's what you want to do on arm64 ? Is there any problem? Best Regards Qiang Zhao
RE: [PATCH v6 1/4] irqchip/qeic: move qeic driver from drivers/soc/fsl/qe
Hello,
Any comments on this patchset?
Best Regards
Zhao Qiang
> -Original Message-
> From: Zhao Qiang [mailto:qiang.z...@nxp.com]
> Sent: Wednesday, September 28, 2016 11:25 AM
> To: o...@buserror.net; t...@linutronix.de
> Cc: ja...@lakedaemon.net; marc.zyng...@arm.com; X.B. Xie
> <xiaobo@nxp.com>; linux-kernel@vger.kernel.org; linuxppc-
> d...@lists.ozlabs.org; Qiang Zhao <qiang.z...@nxp.com>
> Subject: [PATCH v6 1/4] irqchip/qeic: move qeic driver from drivers/soc/fsl/qe
>
> move the driver from drivers/soc/fsl/qe to drivers/irqchip, merge qe_ic.h and
> qe_ic.c into irq-qeic.c.
>
> Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
> ---
> Changes for v2:
> - modify the subject and commit msg
> Changes for v3:
> - merge .h file to .c, rename it with irq-qeic.c Changes for v4:
> - modify comments
> Changes for v5:
> - disable rename detection
> Changes for v6:
> - rebase
>
> drivers/irqchip/Makefile | 1 +
> drivers/{soc/fsl/qe/qe_ic.c => irqchip/irq-qeic.c} | 95 ++-
> drivers/soc/fsl/qe/Makefile| 2 +-
> drivers/soc/fsl/qe/qe_ic.h | 103
> -
> 4 files changed, 94 insertions(+), 107 deletions(-) rename
> drivers/{soc/fsl/qe/qe_ic.c => irqchip/irq-qeic.c} (85%) delete mode 100644
> drivers/soc/fsl/qe/qe_ic.h
>
> diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index
> 4c203b6..face608 100644
> --- a/drivers/irqchip/Makefile
> +++ b/drivers/irqchip/Makefile
> @@ -71,3 +71,4 @@ obj-$(CONFIG_MVEBU_ODMI)+= irq-mvebu-
> odmi.o
> obj-$(CONFIG_LS_SCFG_MSI)+= irq-ls-scfg-msi.o
> obj-$(CONFIG_EZNPS_GIC) += irq-eznps.o
> obj-$(CONFIG_ARCH_ASPEED)+= irq-aspeed-vic.o
> +obj-$(CONFIG_QUICC_ENGINE) += irq-qeic.o
> diff --git a/drivers/soc/fsl/qe/qe_ic.c b/drivers/irqchip/irq-qeic.c
> similarity
> index 85% rename from drivers/soc/fsl/qe/qe_ic.c rename to
> drivers/irqchip/irq-qeic.c index ec2ca86..48ceded 100644
> --- a/drivers/soc/fsl/qe/qe_ic.c
> +++ b/drivers/irqchip/irq-qeic.c
> @@ -1,7 +1,7 @@
> /*
> - * arch/powerpc/sysdev/qe_lib/qe_ic.c
> + * drivers/irqchip/irq-qeic.c
> *
> - * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
> + * Copyright (C) 2016 Freescale Semiconductor, Inc. All rights reserved.
> *
> * Author: Li Yang <le...@freescale.com>
> * Based on code from Shlomi Gridish <grid...@freescale.com> @@ -30,7
> +30,96 @@ #include #include
>
> -#include "qe_ic.h"
> +#define NR_QE_IC_INTS64
> +
> +/* QE IC registers offset */
> +#define QEIC_CICR0x00
> +#define QEIC_CIVEC 0x04
> +#define QEIC_CRIPNR 0x08
> +#define QEIC_CIPNR 0x0c
> +#define QEIC_CIPXCC 0x10
> +#define QEIC_CIPYCC 0x14
> +#define QEIC_CIPWCC 0x18
> +#define QEIC_CIPZCC 0x1c
> +#define QEIC_CIMR0x20
> +#define QEIC_CRIMR 0x24
> +#define QEIC_CICNR 0x28
> +#define QEIC_CIPRTA 0x30
> +#define QEIC_CIPRTB 0x34
> +#define QEIC_CRICR 0x3c
> +#define QEIC_CHIVEC 0x60
> +
> +/* Interrupt priority registers */
> +#define CIPCC_SHIFT_PRI0 29
> +#define CIPCC_SHIFT_PRI1 26
> +#define CIPCC_SHIFT_PRI2 23
> +#define CIPCC_SHIFT_PRI3 20
> +#define CIPCC_SHIFT_PRI4 13
> +#define CIPCC_SHIFT_PRI5 10
> +#define CIPCC_SHIFT_PRI6 7
> +#define CIPCC_SHIFT_PRI7 4
> +
> +/* CICR priority modes */
> +#define CICR_GWCC0x0004
> +#define CICR_GXCC0x0002
> +#define CICR_GYCC0x0001
> +#define CICR_GZCC0x0008
> +#define CICR_GRTA0x0020
> +#define CICR_GRTB0x0040
> +#define CICR_HPIT_SHIFT 8
> +#define CICR_HPIT_MASK 0x0300
> +#define CICR_HP_SHIFT24
> +#define CICR_HP_MASK 0x3f00
> +
> +/* CICNR */
> +#define CICNR_WCC1T_SHIFT20
> +#define CICNR_ZCC1T_SHIFT28
> +#define CICNR_YCC1T_SHIFT12
> +#define CICNR_XCC1T_SHIFT4
> +
> +/* CRICR */
> +#define CRICR_RTA1T_SHIFT20
> +#define CRICR_RTB1T_SHIFT28
> +
> +/* Signal indicator */
> +#define SIGNAL_MASK 3
> +#define SIGNAL_HIGH 2
> +#define SIGNAL_LOW 0
> +
> +struct qe_ic {
> + /* Control registers offset */
> + volatile u32 __iomem *regs;
> +
> + /* The remapper for this QEIC */
> + struct irq_domain *irqhos
RE: [PATCH v6 1/4] irqchip/qeic: move qeic driver from drivers/soc/fsl/qe
Hello,
Any comments on this patchset?
Best Regards
Zhao Qiang
> -Original Message-
> From: Zhao Qiang [mailto:qiang.z...@nxp.com]
> Sent: Wednesday, September 28, 2016 11:25 AM
> To: o...@buserror.net; t...@linutronix.de
> Cc: ja...@lakedaemon.net; marc.zyng...@arm.com; X.B. Xie
> ; linux-kernel@vger.kernel.org; linuxppc-
> d...@lists.ozlabs.org; Qiang Zhao
> Subject: [PATCH v6 1/4] irqchip/qeic: move qeic driver from drivers/soc/fsl/qe
>
> move the driver from drivers/soc/fsl/qe to drivers/irqchip, merge qe_ic.h and
> qe_ic.c into irq-qeic.c.
>
> Signed-off-by: Zhao Qiang
> ---
> Changes for v2:
> - modify the subject and commit msg
> Changes for v3:
> - merge .h file to .c, rename it with irq-qeic.c Changes for v4:
> - modify comments
> Changes for v5:
> - disable rename detection
> Changes for v6:
> - rebase
>
> drivers/irqchip/Makefile | 1 +
> drivers/{soc/fsl/qe/qe_ic.c => irqchip/irq-qeic.c} | 95 ++-
> drivers/soc/fsl/qe/Makefile| 2 +-
> drivers/soc/fsl/qe/qe_ic.h | 103
> -
> 4 files changed, 94 insertions(+), 107 deletions(-) rename
> drivers/{soc/fsl/qe/qe_ic.c => irqchip/irq-qeic.c} (85%) delete mode 100644
> drivers/soc/fsl/qe/qe_ic.h
>
> diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index
> 4c203b6..face608 100644
> --- a/drivers/irqchip/Makefile
> +++ b/drivers/irqchip/Makefile
> @@ -71,3 +71,4 @@ obj-$(CONFIG_MVEBU_ODMI)+= irq-mvebu-
> odmi.o
> obj-$(CONFIG_LS_SCFG_MSI)+= irq-ls-scfg-msi.o
> obj-$(CONFIG_EZNPS_GIC) += irq-eznps.o
> obj-$(CONFIG_ARCH_ASPEED)+= irq-aspeed-vic.o
> +obj-$(CONFIG_QUICC_ENGINE) += irq-qeic.o
> diff --git a/drivers/soc/fsl/qe/qe_ic.c b/drivers/irqchip/irq-qeic.c
> similarity
> index 85% rename from drivers/soc/fsl/qe/qe_ic.c rename to
> drivers/irqchip/irq-qeic.c index ec2ca86..48ceded 100644
> --- a/drivers/soc/fsl/qe/qe_ic.c
> +++ b/drivers/irqchip/irq-qeic.c
> @@ -1,7 +1,7 @@
> /*
> - * arch/powerpc/sysdev/qe_lib/qe_ic.c
> + * drivers/irqchip/irq-qeic.c
> *
> - * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
> + * Copyright (C) 2016 Freescale Semiconductor, Inc. All rights reserved.
> *
> * Author: Li Yang
> * Based on code from Shlomi Gridish @@ -30,7
> +30,96 @@ #include #include
>
> -#include "qe_ic.h"
> +#define NR_QE_IC_INTS64
> +
> +/* QE IC registers offset */
> +#define QEIC_CICR0x00
> +#define QEIC_CIVEC 0x04
> +#define QEIC_CRIPNR 0x08
> +#define QEIC_CIPNR 0x0c
> +#define QEIC_CIPXCC 0x10
> +#define QEIC_CIPYCC 0x14
> +#define QEIC_CIPWCC 0x18
> +#define QEIC_CIPZCC 0x1c
> +#define QEIC_CIMR0x20
> +#define QEIC_CRIMR 0x24
> +#define QEIC_CICNR 0x28
> +#define QEIC_CIPRTA 0x30
> +#define QEIC_CIPRTB 0x34
> +#define QEIC_CRICR 0x3c
> +#define QEIC_CHIVEC 0x60
> +
> +/* Interrupt priority registers */
> +#define CIPCC_SHIFT_PRI0 29
> +#define CIPCC_SHIFT_PRI1 26
> +#define CIPCC_SHIFT_PRI2 23
> +#define CIPCC_SHIFT_PRI3 20
> +#define CIPCC_SHIFT_PRI4 13
> +#define CIPCC_SHIFT_PRI5 10
> +#define CIPCC_SHIFT_PRI6 7
> +#define CIPCC_SHIFT_PRI7 4
> +
> +/* CICR priority modes */
> +#define CICR_GWCC0x0004
> +#define CICR_GXCC0x0002
> +#define CICR_GYCC0x0001
> +#define CICR_GZCC0x0008
> +#define CICR_GRTA0x0020
> +#define CICR_GRTB0x0040
> +#define CICR_HPIT_SHIFT 8
> +#define CICR_HPIT_MASK 0x0300
> +#define CICR_HP_SHIFT24
> +#define CICR_HP_MASK 0x3f00
> +
> +/* CICNR */
> +#define CICNR_WCC1T_SHIFT20
> +#define CICNR_ZCC1T_SHIFT28
> +#define CICNR_YCC1T_SHIFT12
> +#define CICNR_XCC1T_SHIFT4
> +
> +/* CRICR */
> +#define CRICR_RTA1T_SHIFT20
> +#define CRICR_RTB1T_SHIFT28
> +
> +/* Signal indicator */
> +#define SIGNAL_MASK 3
> +#define SIGNAL_HIGH 2
> +#define SIGNAL_LOW 0
> +
> +struct qe_ic {
> + /* Control registers offset */
> + volatile u32 __iomem *regs;
> +
> + /* The remapper for this QEIC */
> + struct irq_domain *irqhost;
> +
> + /* The "linux" controller struct */
> + struct irq_chip hc_irq;
> +
> + /* VIRQ numbers of QE hi
RE: [PATCH v6 2/4] irqchip/qeic: merge qeic init code from platforms to a common function
On 16/12/16 04:33, Marc Zyngier <marc.zyng...@arm.com> wrote:
> -Original Message-
> From: Marc Zyngier [mailto:marc.zyng...@arm.com]
> Sent: Friday, December 16, 2016 4:33 PM
> To: Qiang Zhao <qiang.z...@nxp.com>; o...@buserror.net; t...@linutronix.de
> Cc: ja...@lakedaemon.net; Xiaobo Xie <xiaobo@nxp.com>; linux-
> ker...@vger.kernel.org; linuxppc-...@lists.ozlabs.org
> Subject: Re: [PATCH v6 2/4] irqchip/qeic: merge qeic init code from platforms
> to
> a common function
>
> On 28/09/16 04:25, Zhao Qiang wrote:
> > The codes of qe_ic init from a variety of platforms are redundant,
> > merge them to a common function and put it to irqchip/irq-qeic.c
> >
> > For non-p1021_mds mpc85xx_mds boards, use "qe_ic_init(np, 0,
> > qe_ic_cascade_low_mpic, qe_ic_cascade_high_mpic);" instead of
> > "qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);".
> >
> > qe_ic_cascade_muxed_mpic was used for boards has the same interrupt
> > number for low interrupt and high interrupt, qe_ic_init has checked if
> > "low interrupt == high interrupt"
> >
> > Signed-off-by: Zhao Qiang <qiang.z...@nxp.com>
> > ---
> > Changes for v2:
> > - modify subject and commit msg
> > - add check for qeic by type
> > Changes for v3:
> > - na
> > Changes for v4:
> > - na
> > Changes for v5:
> > - na
> > Changes for v6:
> > - rebase
> >
> > arch/powerpc/platforms/83xx/misc.c| 15 ---
> > arch/powerpc/platforms/85xx/corenet_generic.c | 9 -
> > arch/powerpc/platforms/85xx/mpc85xx_mds.c | 14 --
> > arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 16
> > arch/powerpc/platforms/85xx/twr_p102x.c | 14 --
> > drivers/irqchip/irq-qeic.c| 16
> > 6 files changed, 16 insertions(+), 68 deletions(-)
> >
>
> [...]
>
> > --- a/drivers/irqchip/irq-qeic.c
> > +++ b/drivers/irqchip/irq-qeic.c
> > @@ -598,4 +598,20 @@ static int __init init_qe_ic_sysfs(void)
> > return 0;
> > }
> >
> > +static int __init qeic_of_init(void)
> > +{
> > + struct device_node *np;
> > +
> > + np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
> > + if (!np) {
> > + np = of_find_node_by_type(NULL, "qeic");
> > + if (!np)
> > + return;
> > + }
> > + qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
> > + qe_ic_cascade_high_mpic);
> > + of_node_put(np);
> > +}
>
> Have you actually compiled that code?
Yes.
Best Regards
Zhao Qiang
RE: [PATCH v6 2/4] irqchip/qeic: merge qeic init code from platforms to a common function
On 16/12/16 04:33, Marc Zyngier wrote:
> -Original Message-
> From: Marc Zyngier [mailto:marc.zyng...@arm.com]
> Sent: Friday, December 16, 2016 4:33 PM
> To: Qiang Zhao ; o...@buserror.net; t...@linutronix.de
> Cc: ja...@lakedaemon.net; Xiaobo Xie ; linux-
> ker...@vger.kernel.org; linuxppc-...@lists.ozlabs.org
> Subject: Re: [PATCH v6 2/4] irqchip/qeic: merge qeic init code from platforms
> to
> a common function
>
> On 28/09/16 04:25, Zhao Qiang wrote:
> > The codes of qe_ic init from a variety of platforms are redundant,
> > merge them to a common function and put it to irqchip/irq-qeic.c
> >
> > For non-p1021_mds mpc85xx_mds boards, use "qe_ic_init(np, 0,
> > qe_ic_cascade_low_mpic, qe_ic_cascade_high_mpic);" instead of
> > "qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);".
> >
> > qe_ic_cascade_muxed_mpic was used for boards has the same interrupt
> > number for low interrupt and high interrupt, qe_ic_init has checked if
> > "low interrupt == high interrupt"
> >
> > Signed-off-by: Zhao Qiang
> > ---
> > Changes for v2:
> > - modify subject and commit msg
> > - add check for qeic by type
> > Changes for v3:
> > - na
> > Changes for v4:
> > - na
> > Changes for v5:
> > - na
> > Changes for v6:
> > - rebase
> >
> > arch/powerpc/platforms/83xx/misc.c| 15 ---
> > arch/powerpc/platforms/85xx/corenet_generic.c | 9 -
> > arch/powerpc/platforms/85xx/mpc85xx_mds.c | 14 --
> > arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 16
> > arch/powerpc/platforms/85xx/twr_p102x.c | 14 --
> > drivers/irqchip/irq-qeic.c| 16
> > 6 files changed, 16 insertions(+), 68 deletions(-)
> >
>
> [...]
>
> > --- a/drivers/irqchip/irq-qeic.c
> > +++ b/drivers/irqchip/irq-qeic.c
> > @@ -598,4 +598,20 @@ static int __init init_qe_ic_sysfs(void)
> > return 0;
> > }
> >
> > +static int __init qeic_of_init(void)
> > +{
> > + struct device_node *np;
> > +
> > + np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
> > + if (!np) {
> > + np = of_find_node_by_type(NULL, "qeic");
> > + if (!np)
> > + return;
> > + }
> > + qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
> > + qe_ic_cascade_high_mpic);
> > + of_node_put(np);
> > +}
>
> Have you actually compiled that code?
Yes.
Best Regards
Zhao Qiang
RE: [PATCH v9] QE: remove PPCisms for QE
This patch depends on the patchset of QEIC as following links:
http://patchwork.ozlabs.org/patch/675925/
http://patchwork.ozlabs.org/patch/675926/
http://patchwork.ozlabs.org/patch/675927/
http://patchwork.ozlabs.org/patch/675928/
> -Original Message-
> From: kbuild test robot [mailto:l...@intel.com]
> Sent: Monday, December 05, 2016 3:00 PM
> To: Qiang Zhao <qiang.z...@nxp.com>
> Cc: kbuild-...@01.org; o...@buserror.net; ba...@kernel.org;
> gre...@linuxfoundation.org; Xiaobo Xie <xiaobo@nxp.com>; linux-
> ker...@vger.kernel.org; linuxppc-...@lists.ozlabs.org; Qiang Zhao
> <qiang.z...@nxp.com>
> Subject: Re: [PATCH v9] QE: remove PPCisms for QE
>
> Hi Zhao,
>
> [auto build test ERROR on linus/master]
> [also build test ERROR on v4.9-rc8]
> [cannot apply to next-20161202]
> [if your patch is applied to the wrong git tree, please drop us a note to help
> improve the system]
>
> url:https://github.com/0day-ci/linux/commits/Zhao-Qiang/QE-remove-
> PPCisms-for-QE/20161205-131352
> config: i386-allmodconfig (attached as .config)
> compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901
> reproduce:
> # save the attached .config to linux build tree
> make ARCH=i386
>
> All errors (new ones prefixed by >>):
>
>In file included from drivers/soc/fsl/qe/qe_ic.c:31:0:
>include/soc/fsl/qe/qe_ic.h: In function 'qe_ic_cascade_low_ipic':
> >> include/soc/fsl/qe/qe_ic.h:86:21: error: 'NO_IRQ' undeclared (first use in
> this function)
> if (cascade_irq != NO_IRQ)
> ^~
>include/soc/fsl/qe/qe_ic.h:86:21: note: each undeclared identifier is
> reported
> only once for each function it appears in
>include/soc/fsl/qe/qe_ic.h: In function 'qe_ic_cascade_high_ipic':
>include/soc/fsl/qe/qe_ic.h:95:21: error: 'NO_IRQ' undeclared (first use in
> this
> function)
> if (cascade_irq != NO_IRQ)
> ^~
>include/soc/fsl/qe/qe_ic.h: In function 'qe_ic_cascade_low_mpic':
>include/soc/fsl/qe/qe_ic.h:105:21: error: 'NO_IRQ' undeclared (first use in
> this function)
> if (cascade_irq != NO_IRQ)
> ^~
>include/soc/fsl/qe/qe_ic.h: In function 'qe_ic_cascade_high_mpic':
>include/soc/fsl/qe/qe_ic.h:117:21: error: 'NO_IRQ' undeclared (first use in
> this function)
> if (cascade_irq != NO_IRQ)
> ^~
>include/soc/fsl/qe/qe_ic.h: In function 'qe_ic_cascade_muxed_mpic':
>include/soc/fsl/qe/qe_ic.h:130:21: error: 'NO_IRQ' undeclared (first use in
> this function)
> if (cascade_irq == NO_IRQ)
> ^~
>drivers/soc/fsl/qe/qe_ic.c: In function 'qe_ic_read':
> >> drivers/soc/fsl/qe/qe_ic.c:180:9: error: implicit declaration of function
> 'in_be32' [-Werror=implicit-function-declaration]
> return in_be32(base + (reg >> 2));
> ^~~
>drivers/soc/fsl/qe/qe_ic.c: In function 'qe_ic_write':
> >> drivers/soc/fsl/qe/qe_ic.c:186:2: error: implicit declaration of function
> 'out_be32' [-Werror=implicit-function-declaration]
> out_be32(base + (reg >> 2), value);
> ^~~~
>drivers/soc/fsl/qe/qe_ic.c: In function 'qe_ic_get_low_irq':
> >> drivers/soc/fsl/qe/qe_ic.c:299:10: error: 'NO_IRQ' undeclared (first use in
> this function)
> return NO_IRQ;
> ^~
>drivers/soc/fsl/qe/qe_ic.c: In function 'qe_ic_get_high_irq':
>drivers/soc/fsl/qe/qe_ic.c:315:10: error: 'NO_IRQ' undeclared (first use
> in this
> function)
> return NO_IRQ;
> ^~
>drivers/soc/fsl/qe/qe_ic.c: In function 'qe_ic_init':
>drivers/soc/fsl/qe/qe_ic.c:350:25: error: 'NO_IRQ' undeclared (first use
> in this
> function)
> if (qe_ic->virq_low == NO_IRQ) {
> ^~
>drivers/soc/fsl/qe/qe_ic.c: In function 'qe_ic_set_highest_priority':
> >> drivers/soc/fsl/qe/qe_ic.c:392:21: error: implicit declaration of function
> 'virq_to_hw' [-Werror=implicit-function-declaration]
> unsigned int src = virq_to_hw(virq);
> ^~
>cc1: some warnings being treated as errors
>
> vim +/in_be32 +180 drivers/soc/fsl/qe/qe_ic.c
>
> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03
> 174
> .pri_reg = QEIC_CIPYCC,
> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03
> 175
> },
> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03
> 176 };
> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03
> 177
&
RE: [PATCH v9] QE: remove PPCisms for QE
This patch depends on the patchset of QEIC as following links:
http://patchwork.ozlabs.org/patch/675925/
http://patchwork.ozlabs.org/patch/675926/
http://patchwork.ozlabs.org/patch/675927/
http://patchwork.ozlabs.org/patch/675928/
> -Original Message-
> From: kbuild test robot [mailto:l...@intel.com]
> Sent: Monday, December 05, 2016 3:00 PM
> To: Qiang Zhao
> Cc: kbuild-...@01.org; o...@buserror.net; ba...@kernel.org;
> gre...@linuxfoundation.org; Xiaobo Xie ; linux-
> ker...@vger.kernel.org; linuxppc-...@lists.ozlabs.org; Qiang Zhao
>
> Subject: Re: [PATCH v9] QE: remove PPCisms for QE
>
> Hi Zhao,
>
> [auto build test ERROR on linus/master]
> [also build test ERROR on v4.9-rc8]
> [cannot apply to next-20161202]
> [if your patch is applied to the wrong git tree, please drop us a note to help
> improve the system]
>
> url:https://github.com/0day-ci/linux/commits/Zhao-Qiang/QE-remove-
> PPCisms-for-QE/20161205-131352
> config: i386-allmodconfig (attached as .config)
> compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901
> reproduce:
> # save the attached .config to linux build tree
> make ARCH=i386
>
> All errors (new ones prefixed by >>):
>
>In file included from drivers/soc/fsl/qe/qe_ic.c:31:0:
>include/soc/fsl/qe/qe_ic.h: In function 'qe_ic_cascade_low_ipic':
> >> include/soc/fsl/qe/qe_ic.h:86:21: error: 'NO_IRQ' undeclared (first use in
> this function)
> if (cascade_irq != NO_IRQ)
> ^~
>include/soc/fsl/qe/qe_ic.h:86:21: note: each undeclared identifier is
> reported
> only once for each function it appears in
>include/soc/fsl/qe/qe_ic.h: In function 'qe_ic_cascade_high_ipic':
>include/soc/fsl/qe/qe_ic.h:95:21: error: 'NO_IRQ' undeclared (first use in
> this
> function)
> if (cascade_irq != NO_IRQ)
> ^~
>include/soc/fsl/qe/qe_ic.h: In function 'qe_ic_cascade_low_mpic':
>include/soc/fsl/qe/qe_ic.h:105:21: error: 'NO_IRQ' undeclared (first use in
> this function)
> if (cascade_irq != NO_IRQ)
> ^~
>include/soc/fsl/qe/qe_ic.h: In function 'qe_ic_cascade_high_mpic':
>include/soc/fsl/qe/qe_ic.h:117:21: error: 'NO_IRQ' undeclared (first use in
> this function)
> if (cascade_irq != NO_IRQ)
> ^~
>include/soc/fsl/qe/qe_ic.h: In function 'qe_ic_cascade_muxed_mpic':
>include/soc/fsl/qe/qe_ic.h:130:21: error: 'NO_IRQ' undeclared (first use in
> this function)
> if (cascade_irq == NO_IRQ)
> ^~
>drivers/soc/fsl/qe/qe_ic.c: In function 'qe_ic_read':
> >> drivers/soc/fsl/qe/qe_ic.c:180:9: error: implicit declaration of function
> 'in_be32' [-Werror=implicit-function-declaration]
> return in_be32(base + (reg >> 2));
> ^~~
>drivers/soc/fsl/qe/qe_ic.c: In function 'qe_ic_write':
> >> drivers/soc/fsl/qe/qe_ic.c:186:2: error: implicit declaration of function
> 'out_be32' [-Werror=implicit-function-declaration]
> out_be32(base + (reg >> 2), value);
> ^~~~
>drivers/soc/fsl/qe/qe_ic.c: In function 'qe_ic_get_low_irq':
> >> drivers/soc/fsl/qe/qe_ic.c:299:10: error: 'NO_IRQ' undeclared (first use in
> this function)
> return NO_IRQ;
> ^~
>drivers/soc/fsl/qe/qe_ic.c: In function 'qe_ic_get_high_irq':
>drivers/soc/fsl/qe/qe_ic.c:315:10: error: 'NO_IRQ' undeclared (first use
> in this
> function)
> return NO_IRQ;
> ^~
>drivers/soc/fsl/qe/qe_ic.c: In function 'qe_ic_init':
>drivers/soc/fsl/qe/qe_ic.c:350:25: error: 'NO_IRQ' undeclared (first use
> in this
> function)
> if (qe_ic->virq_low == NO_IRQ) {
> ^~
>drivers/soc/fsl/qe/qe_ic.c: In function 'qe_ic_set_highest_priority':
> >> drivers/soc/fsl/qe/qe_ic.c:392:21: error: implicit declaration of function
> 'virq_to_hw' [-Werror=implicit-function-declaration]
> unsigned int src = virq_to_hw(virq);
> ^~
>cc1: some warnings being treated as errors
>
> vim +/in_be32 +180 drivers/soc/fsl/qe/qe_ic.c
>
> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03
> 174
> .pri_reg = QEIC_CIPYCC,
> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03
> 175
> },
> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03
> 176 };
> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03
> 177
> 98658538 arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10
RE: [v6,2/2] QE: remove PPCisms for QE
On Tue, Sep 27, 2016 at 7:12AM -0500, Scott Wood wrote: > -Original Message- > From: Scott Wood [mailto:o...@buserror.net] > Sent: Tuesday, September 27, 2016 7:12 AM > To: Qiang Zhao <qiang.z...@nxp.com> > Cc: linuxppc-...@lists.ozlabs.org; pku@gmail.com; X.B. Xie > <xiaobo@nxp.com>; linux-kernel@vger.kernel.org > Subject: Re: [v6,2/2] QE: remove PPCisms for QE > > On Mon, 2016-09-26 at 01:46 +, Qiang Zhao wrote: > > On Sun, Sep 25, 2016 at 12:19PM -0500, Scott Wood wrote: > > > > > > > > -Original Message- > > > From: Scott Wood [mailto:o...@buserror.net] > > > Sent: Sunday, September 25, 2016 12:19 PM > > > To: Qiang Zhao <qiang.z...@nxp.com> > > > Cc: linuxppc-...@lists.ozlabs.org; pku@gmail.com; X.B. Xie > > > <xiaobo@nxp.com>; linux-kernel@vger.kernel.org > > > Subject: Re: [v6,2/2] QE: remove PPCisms for QE > > > > > > On Sat, Sep 24, 2016 at 11:14:11PM -0500, Scott Wood wrote: > > > > > > > > On Fri, Sep 23, 2016 at 10:20:32AM +0800, Zhao Qiang wrote: > > > > > > > > > > QE was supported on PowerPC, and dependent on PPC, Now it is > > > > > supported on other platforms. so remove PPCisms. > > > > > > > > > > Signed-off-by: Zhao Qiang <qiang.z...@nxp.com> > > > > > --- > > > > > Changes for v2: > > > > > - na > > > > > Changes for v3: > > > > > - add NO_IRQ > > > > > Changes for v4: > > > > > - modify spin_event_timeout to opencoded timeout loop > > > > > - remove NO_IRQ > > > > > - modify virq_to_hw to opencoed code Changes for v5: > > > > > - modify commit msg > > > > > - modify depends of QUICC_ENGINE > > > > > - add kerneldoc header for qe_issue_cmd Changes for v6: > > > > > - add dependency on FSL_SOC and PPC32 for drivers > > > > > depending on QUICC_ENGING but not available on ARM > > > > > > > > > > drivers/irqchip/qe_ic.c| 28 +++- > > > > > drivers/net/ethernet/freescale/Kconfig | 10 ++--- > > > > > drivers/soc/fsl/qe/Kconfig | 2 +- > > > > > drivers/soc/fsl/qe/qe.c| 80 > > > > > - > > > > > - > > > > > drivers/soc/fsl/qe/qe_io.c | 42 -- > > > > > drivers/soc/fsl/qe/qe_tdm.c| 8 ++-- > > > > > drivers/soc/fsl/qe/ucc.c | 10 ++--- > > > > > drivers/soc/fsl/qe/ucc_fast.c | 68 > > > > > ++--- > > > > > > > > > > drivers/tty/serial/Kconfig | 2 +- > > > > > drivers/usb/gadget/udc/Kconfig | 2 +- > > > > > drivers/usb/host/Kconfig | 2 +- > > > > > include/soc/fsl/qe/qe.h| 1 - > > > > > include/soc/fsl/qe/qe_ic.h | 12 ++--- > > > > > 13 files changed, 141 insertions(+), 126 deletions(-) > > > > I assume this means you'll be updating > > > > http://patchwork.ozlabs.org/patch/654473/ > > > > to be based on top of this... > > > Apparently that assumption was wrong, since I now see that you're > > > patching drivers/irqchip/qe_ic.c rather than drivers/soc/fsl/qe/qe_ic.c. > > > Please keep the drivers/irqchip stuff separate and send to the > > > appropriate maintainers. > > > > > You means separate drivers/irqchip/qe_ic.c part from this patch and > > send it with the other qe_ic patches? > > Is it acceptable if I modify qe_ic.c with drivers/soc/fsl/qe/qe_ic.c, > > then send qe_ic patches to move qe_ic to drivers/irqchip? > > I'd recommend against it. It would complicate getting the drivers/irqchip > patchset merged. In any case, it's too late for 4.9. Ok, thank you for your recommend. BR -Zhao Qiang
RE: [v6,2/2] QE: remove PPCisms for QE
On Tue, Sep 27, 2016 at 7:12AM -0500, Scott Wood wrote: > -Original Message- > From: Scott Wood [mailto:o...@buserror.net] > Sent: Tuesday, September 27, 2016 7:12 AM > To: Qiang Zhao > Cc: linuxppc-...@lists.ozlabs.org; pku@gmail.com; X.B. Xie > ; linux-kernel@vger.kernel.org > Subject: Re: [v6,2/2] QE: remove PPCisms for QE > > On Mon, 2016-09-26 at 01:46 +, Qiang Zhao wrote: > > On Sun, Sep 25, 2016 at 12:19PM -0500, Scott Wood wrote: > > > > > > > > -Original Message- > > > From: Scott Wood [mailto:o...@buserror.net] > > > Sent: Sunday, September 25, 2016 12:19 PM > > > To: Qiang Zhao > > > Cc: linuxppc-...@lists.ozlabs.org; pku@gmail.com; X.B. Xie > > > ; linux-kernel@vger.kernel.org > > > Subject: Re: [v6,2/2] QE: remove PPCisms for QE > > > > > > On Sat, Sep 24, 2016 at 11:14:11PM -0500, Scott Wood wrote: > > > > > > > > On Fri, Sep 23, 2016 at 10:20:32AM +0800, Zhao Qiang wrote: > > > > > > > > > > QE was supported on PowerPC, and dependent on PPC, Now it is > > > > > supported on other platforms. so remove PPCisms. > > > > > > > > > > Signed-off-by: Zhao Qiang > > > > > --- > > > > > Changes for v2: > > > > > - na > > > > > Changes for v3: > > > > > - add NO_IRQ > > > > > Changes for v4: > > > > > - modify spin_event_timeout to opencoded timeout loop > > > > > - remove NO_IRQ > > > > > - modify virq_to_hw to opencoed code Changes for v5: > > > > > - modify commit msg > > > > > - modify depends of QUICC_ENGINE > > > > > - add kerneldoc header for qe_issue_cmd Changes for v6: > > > > > - add dependency on FSL_SOC and PPC32 for drivers > > > > > depending on QUICC_ENGING but not available on ARM > > > > > > > > > > drivers/irqchip/qe_ic.c| 28 +++- > > > > > drivers/net/ethernet/freescale/Kconfig | 10 ++--- > > > > > drivers/soc/fsl/qe/Kconfig | 2 +- > > > > > drivers/soc/fsl/qe/qe.c| 80 > > > > > - > > > > > - > > > > > drivers/soc/fsl/qe/qe_io.c | 42 -- > > > > > drivers/soc/fsl/qe/qe_tdm.c| 8 ++-- > > > > > drivers/soc/fsl/qe/ucc.c | 10 ++--- > > > > > drivers/soc/fsl/qe/ucc_fast.c | 68 > > > > > ++--- > > > > > > > > > > drivers/tty/serial/Kconfig | 2 +- > > > > > drivers/usb/gadget/udc/Kconfig | 2 +- > > > > > drivers/usb/host/Kconfig | 2 +- > > > > > include/soc/fsl/qe/qe.h| 1 - > > > > > include/soc/fsl/qe/qe_ic.h | 12 ++--- > > > > > 13 files changed, 141 insertions(+), 126 deletions(-) > > > > I assume this means you'll be updating > > > > http://patchwork.ozlabs.org/patch/654473/ > > > > to be based on top of this... > > > Apparently that assumption was wrong, since I now see that you're > > > patching drivers/irqchip/qe_ic.c rather than drivers/soc/fsl/qe/qe_ic.c. > > > Please keep the drivers/irqchip stuff separate and send to the > > > appropriate maintainers. > > > > > You means separate drivers/irqchip/qe_ic.c part from this patch and > > send it with the other qe_ic patches? > > Is it acceptable if I modify qe_ic.c with drivers/soc/fsl/qe/qe_ic.c, > > then send qe_ic patches to move qe_ic to drivers/irqchip? > > I'd recommend against it. It would complicate getting the drivers/irqchip > patchset merged. In any case, it's too late for 4.9. Ok, thank you for your recommend. BR -Zhao Qiang
RE: [v6,2/2] QE: remove PPCisms for QE
On Sun, Sep 25, 2016 at 12:19PM -0500, Scott Wood wrote: > -Original Message- > From: Scott Wood [mailto:o...@buserror.net] > Sent: Sunday, September 25, 2016 12:19 PM > To: Qiang Zhao <qiang.z...@nxp.com> > Cc: linuxppc-...@lists.ozlabs.org; pku@gmail.com; X.B. Xie > <xiaobo@nxp.com>; linux-kernel@vger.kernel.org > Subject: Re: [v6,2/2] QE: remove PPCisms for QE > > On Sat, Sep 24, 2016 at 11:14:11PM -0500, Scott Wood wrote: > > On Fri, Sep 23, 2016 at 10:20:32AM +0800, Zhao Qiang wrote: > > > QE was supported on PowerPC, and dependent on PPC, Now it is > > > supported on other platforms. so remove PPCisms. > > > > > > Signed-off-by: Zhao Qiang <qiang.z...@nxp.com> > > > --- > > > Changes for v2: > > > - na > > > Changes for v3: > > > - add NO_IRQ > > > Changes for v4: > > > - modify spin_event_timeout to opencoded timeout loop > > > - remove NO_IRQ > > > - modify virq_to_hw to opencoed code Changes for v5: > > > - modify commit msg > > > - modify depends of QUICC_ENGINE > > > - add kerneldoc header for qe_issue_cmd Changes for v6: > > > - add dependency on FSL_SOC and PPC32 for drivers > > > depending on QUICC_ENGING but not available on ARM > > > > > > drivers/irqchip/qe_ic.c| 28 +++- > > > drivers/net/ethernet/freescale/Kconfig | 10 ++--- > > > drivers/soc/fsl/qe/Kconfig | 2 +- > > > drivers/soc/fsl/qe/qe.c| 80 > > > -- > > > drivers/soc/fsl/qe/qe_io.c | 42 -- > > > drivers/soc/fsl/qe/qe_tdm.c| 8 ++-- > > > drivers/soc/fsl/qe/ucc.c | 10 ++--- > > > drivers/soc/fsl/qe/ucc_fast.c | 68 ++--- > > > drivers/tty/serial/Kconfig | 2 +- > > > drivers/usb/gadget/udc/Kconfig | 2 +- > > > drivers/usb/host/Kconfig | 2 +- > > > include/soc/fsl/qe/qe.h| 1 - > > > include/soc/fsl/qe/qe_ic.h | 12 ++--- > > > 13 files changed, 141 insertions(+), 126 deletions(-) > > > > I assume this means you'll be updating > > http://patchwork.ozlabs.org/patch/654473/ > > to be based on top of this... > > Apparently that assumption was wrong, since I now see that you're patching > drivers/irqchip/qe_ic.c rather than drivers/soc/fsl/qe/qe_ic.c. > Please keep the drivers/irqchip stuff separate and send to the appropriate > maintainers. > You means separate drivers/irqchip/qe_ic.c part from this patch and send it with the other qe_ic patches? Is it acceptable if I modify qe_ic.c with drivers/soc/fsl/qe/qe_ic.c, then send qe_ic patches to move qe_ic to drivers/irqchip? BR -Zhao Qiang
RE: [v6,2/2] QE: remove PPCisms for QE
On Sun, Sep 25, 2016 at 12:19PM -0500, Scott Wood wrote: > -Original Message- > From: Scott Wood [mailto:o...@buserror.net] > Sent: Sunday, September 25, 2016 12:19 PM > To: Qiang Zhao > Cc: linuxppc-...@lists.ozlabs.org; pku@gmail.com; X.B. Xie > ; linux-kernel@vger.kernel.org > Subject: Re: [v6,2/2] QE: remove PPCisms for QE > > On Sat, Sep 24, 2016 at 11:14:11PM -0500, Scott Wood wrote: > > On Fri, Sep 23, 2016 at 10:20:32AM +0800, Zhao Qiang wrote: > > > QE was supported on PowerPC, and dependent on PPC, Now it is > > > supported on other platforms. so remove PPCisms. > > > > > > Signed-off-by: Zhao Qiang > > > --- > > > Changes for v2: > > > - na > > > Changes for v3: > > > - add NO_IRQ > > > Changes for v4: > > > - modify spin_event_timeout to opencoded timeout loop > > > - remove NO_IRQ > > > - modify virq_to_hw to opencoed code Changes for v5: > > > - modify commit msg > > > - modify depends of QUICC_ENGINE > > > - add kerneldoc header for qe_issue_cmd Changes for v6: > > > - add dependency on FSL_SOC and PPC32 for drivers > > > depending on QUICC_ENGING but not available on ARM > > > > > > drivers/irqchip/qe_ic.c| 28 +++- > > > drivers/net/ethernet/freescale/Kconfig | 10 ++--- > > > drivers/soc/fsl/qe/Kconfig | 2 +- > > > drivers/soc/fsl/qe/qe.c| 80 > > > -- > > > drivers/soc/fsl/qe/qe_io.c | 42 -- > > > drivers/soc/fsl/qe/qe_tdm.c| 8 ++-- > > > drivers/soc/fsl/qe/ucc.c | 10 ++--- > > > drivers/soc/fsl/qe/ucc_fast.c | 68 ++--- > > > drivers/tty/serial/Kconfig | 2 +- > > > drivers/usb/gadget/udc/Kconfig | 2 +- > > > drivers/usb/host/Kconfig | 2 +- > > > include/soc/fsl/qe/qe.h| 1 - > > > include/soc/fsl/qe/qe_ic.h | 12 ++--- > > > 13 files changed, 141 insertions(+), 126 deletions(-) > > > > I assume this means you'll be updating > > http://patchwork.ozlabs.org/patch/654473/ > > to be based on top of this... > > Apparently that assumption was wrong, since I now see that you're patching > drivers/irqchip/qe_ic.c rather than drivers/soc/fsl/qe/qe_ic.c. > Please keep the drivers/irqchip stuff separate and send to the appropriate > maintainers. > You means separate drivers/irqchip/qe_ic.c part from this patch and send it with the other qe_ic patches? Is it acceptable if I modify qe_ic.c with drivers/soc/fsl/qe/qe_ic.c, then send qe_ic patches to move qe_ic to drivers/irqchip? BR -Zhao Qiang
RE: [PATCH v5 2/2] QE: remove PPCisms for QE
On Fri, Sep 23, 2016 at 3:39 AM, Leo Li wrote: > -Original Message- > From: Leo Li [mailto:pku@gmail.com] > Sent: Friday, September 23, 2016 3:39 AM > To: Qiang Zhao <qiang.z...@nxp.com> > Cc: Scott Wood <o...@buserror.net>; linuxppc-dev d...@lists.ozlabs.org>; lkml <linux-kernel@vger.kernel.org>; X.B. Xie > <xiaobo@nxp.com> > Subject: Re: [PATCH v5 2/2] QE: remove PPCisms for QE > > On Wed, Sep 21, 2016 at 8:43 PM, Qiang Zhao <qiang.z...@nxp.com> wrote: > > On Mon, Sep 22, 2016 at 2:19 AM, Leo Li wrote: > >> -Original Message- > >> From: Leo Li [mailto:pku@gmail.com] > >> Sent: Thursday, September 22, 2016 2:19 AM > >> To: Qiang Zhao <qiang.z...@nxp.com> > >> Cc: Scott Wood <o...@buserror.net>; linuxppc-dev >> d...@lists.ozlabs.org>; lkml <linux-kernel@vger.kernel.org>; X.B. Xie > >> <xiaobo@nxp.com> > >> Subject: Re: [PATCH v5 2/2] QE: remove PPCisms for QE > >> > >> On Tue, Sep 20, 2016 at 8:13 PM, Qiang Zhao <qiang.z...@nxp.com> wrote: > >> > On Mon, Sep 20, 2016 at 4:13 AM, Leo Li wrote: > >> >> -Original Message- > >> >> From: Leo Li [mailto:pku@gmail.com] > >> >> Sent: Tuesday, September 20, 2016 4:13 AM > >> >> To: Qiang Zhao <qiang.z...@nxp.com> > >> >> Cc: Scott Wood <o...@buserror.net>; linuxppc-dev >> >> d...@lists.ozlabs.org>; lkml <linux-kernel@vger.kernel.org>; X.B. > >> >> Xie <xiaobo@nxp.com> > >> >> Subject: Re: [PATCH v5 2/2] QE: remove PPCisms for QE > >> >> > >> >> On Mon, Jul 25, 2016 at 12:43 AM, Zhao Qiang <qiang.z...@nxp.com> > >> wrote: > >> >> > QE was supported on PowerPC, and dependent on PPC, Now it is > >> >> > supported on other platforms. so remove PPCisms. > >> >> > > >> >> > Signed-off-by: Zhao Qiang <qiang.z...@nxp.com> > >> >> > --- > >> >> > Changes for v2: > >> >> > - na > >> >> > Changes for v3: > >> >> > - add NO_IRQ > >> >> > Changes for v4: > >> >> > - modify spin_event_timeout to opencoded timeout loop > >> >> > - remove NO_IRQ > >> >> > - modify virq_to_hw to opencoed code Changes for v5: > >> >> > - modify commit msg > >> >> > - modify depends of QUICC_ENGINE > >> >> > - add kerneldoc header for qe_issue_cmd > >> >> > > >> >> > drivers/irqchip/qe_ic.c | 28 +-- > >> >> > drivers/soc/fsl/qe/Kconfig| 2 +- > >> >> > drivers/soc/fsl/qe/qe.c | 80 ++-- > > >> > >> >> --- > >> >> > drivers/soc/fsl/qe/qe_io.c| 42 ++- > >> >> > drivers/soc/fsl/qe/qe_tdm.c | 8 ++--- > >> >> > drivers/soc/fsl/qe/ucc.c | 10 +++--- > >> >> > drivers/soc/fsl/qe/ucc_fast.c | 68 ++ > -- > >> >> > include/soc/fsl/qe/qe.h | 1 - > >> >> > include/soc/fsl/qe/qe_ic.h| 12 +++ > >> >> > 9 files changed, 133 insertions(+), 118 deletions(-) > >> >> > > >> >> > >> >> [snip] > >> >> > >> >> > diff --git a/drivers/soc/fsl/qe/Kconfig > >> >> > b/drivers/soc/fsl/qe/Kconfig index 73a2e08..b26b643 100644 > >> >> > --- a/drivers/soc/fsl/qe/Kconfig > >> >> > +++ b/drivers/soc/fsl/qe/Kconfig > >> >> > @@ -4,7 +4,7 @@ > >> >> > > >> >> > config QUICC_ENGINE > >> >> > bool "Freescale QUICC Engine (QE) Support" > >> >> > - depends on FSL_SOC && PPC32 > >> >> > + depends on OF && HAS_IOMEM > >> >> > select GENERIC_ALLOCATOR > >> >> > select CRC32 > >> >> > help > >> >> > >> >> You make it possible to build QE drivers on ARM, but the UCC_GETH > >> >> fails to build on arm64. Please make sure all these drivers can > >> >> build on other architectures. Or you can simply make them only > >> >> build for Power architecture as most of them are not available on ARM. > >> >> > >> > > >> > Most of them are not available on ARM and ARM64. > >> > Now, only qe-hdlc is available on ARM64. > >> > >> Then you should update the Kconfig for these drivers too, if they are > >> only depending on CONFIG_QUICC_ENGINE. > > > > You mean adding "depends on FSL_SOC && PPC32 " to the drivers that are > not available for ARM? > > Yes. Previously these drivers get the architecture limitation from > CONFIG_QUICC_ENGINE, but now they need them by their own. > Ok, I will modify it in the next vertion. BR -Zhao Qiang
RE: [PATCH v5 2/2] QE: remove PPCisms for QE
On Fri, Sep 23, 2016 at 3:39 AM, Leo Li wrote: > -Original Message- > From: Leo Li [mailto:pku@gmail.com] > Sent: Friday, September 23, 2016 3:39 AM > To: Qiang Zhao > Cc: Scott Wood ; linuxppc-dev d...@lists.ozlabs.org>; lkml ; X.B. Xie > > Subject: Re: [PATCH v5 2/2] QE: remove PPCisms for QE > > On Wed, Sep 21, 2016 at 8:43 PM, Qiang Zhao wrote: > > On Mon, Sep 22, 2016 at 2:19 AM, Leo Li wrote: > >> -Original Message- > >> From: Leo Li [mailto:pku@gmail.com] > >> Sent: Thursday, September 22, 2016 2:19 AM > >> To: Qiang Zhao > >> Cc: Scott Wood ; linuxppc-dev >> d...@lists.ozlabs.org>; lkml ; X.B. Xie > >> > >> Subject: Re: [PATCH v5 2/2] QE: remove PPCisms for QE > >> > >> On Tue, Sep 20, 2016 at 8:13 PM, Qiang Zhao wrote: > >> > On Mon, Sep 20, 2016 at 4:13 AM, Leo Li wrote: > >> >> -Original Message- > >> >> From: Leo Li [mailto:pku@gmail.com] > >> >> Sent: Tuesday, September 20, 2016 4:13 AM > >> >> To: Qiang Zhao > >> >> Cc: Scott Wood ; linuxppc-dev >> >> d...@lists.ozlabs.org>; lkml ; X.B. > >> >> Xie > >> >> Subject: Re: [PATCH v5 2/2] QE: remove PPCisms for QE > >> >> > >> >> On Mon, Jul 25, 2016 at 12:43 AM, Zhao Qiang > >> wrote: > >> >> > QE was supported on PowerPC, and dependent on PPC, Now it is > >> >> > supported on other platforms. so remove PPCisms. > >> >> > > >> >> > Signed-off-by: Zhao Qiang > >> >> > --- > >> >> > Changes for v2: > >> >> > - na > >> >> > Changes for v3: > >> >> > - add NO_IRQ > >> >> > Changes for v4: > >> >> > - modify spin_event_timeout to opencoded timeout loop > >> >> > - remove NO_IRQ > >> >> > - modify virq_to_hw to opencoed code Changes for v5: > >> >> > - modify commit msg > >> >> > - modify depends of QUICC_ENGINE > >> >> > - add kerneldoc header for qe_issue_cmd > >> >> > > >> >> > drivers/irqchip/qe_ic.c | 28 +-- > >> >> > drivers/soc/fsl/qe/Kconfig| 2 +- > >> >> > drivers/soc/fsl/qe/qe.c | 80 ++-- > > >> > >> >> --- > >> >> > drivers/soc/fsl/qe/qe_io.c| 42 ++- > >> >> > drivers/soc/fsl/qe/qe_tdm.c | 8 ++--- > >> >> > drivers/soc/fsl/qe/ucc.c | 10 +++--- > >> >> > drivers/soc/fsl/qe/ucc_fast.c | 68 ++ > -- > >> >> > include/soc/fsl/qe/qe.h | 1 - > >> >> > include/soc/fsl/qe/qe_ic.h| 12 +++ > >> >> > 9 files changed, 133 insertions(+), 118 deletions(-) > >> >> > > >> >> > >> >> [snip] > >> >> > >> >> > diff --git a/drivers/soc/fsl/qe/Kconfig > >> >> > b/drivers/soc/fsl/qe/Kconfig index 73a2e08..b26b643 100644 > >> >> > --- a/drivers/soc/fsl/qe/Kconfig > >> >> > +++ b/drivers/soc/fsl/qe/Kconfig > >> >> > @@ -4,7 +4,7 @@ > >> >> > > >> >> > config QUICC_ENGINE > >> >> > bool "Freescale QUICC Engine (QE) Support" > >> >> > - depends on FSL_SOC && PPC32 > >> >> > + depends on OF && HAS_IOMEM > >> >> > select GENERIC_ALLOCATOR > >> >> > select CRC32 > >> >> > help > >> >> > >> >> You make it possible to build QE drivers on ARM, but the UCC_GETH > >> >> fails to build on arm64. Please make sure all these drivers can > >> >> build on other architectures. Or you can simply make them only > >> >> build for Power architecture as most of them are not available on ARM. > >> >> > >> > > >> > Most of them are not available on ARM and ARM64. > >> > Now, only qe-hdlc is available on ARM64. > >> > >> Then you should update the Kconfig for these drivers too, if they are > >> only depending on CONFIG_QUICC_ENGINE. > > > > You mean adding "depends on FSL_SOC && PPC32 " to the drivers that are > not available for ARM? > > Yes. Previously these drivers get the architecture limitation from > CONFIG_QUICC_ENGINE, but now they need them by their own. > Ok, I will modify it in the next vertion. BR -Zhao Qiang
RE: [PATCH v5 2/2] QE: remove PPCisms for QE
On Mon, Sep 22, 2016 at 2:19 AM, Leo Li wrote: > -Original Message- > From: Leo Li [mailto:pku@gmail.com] > Sent: Thursday, September 22, 2016 2:19 AM > To: Qiang Zhao <qiang.z...@nxp.com> > Cc: Scott Wood <o...@buserror.net>; linuxppc-dev d...@lists.ozlabs.org>; lkml <linux-kernel@vger.kernel.org>; X.B. Xie > <xiaobo@nxp.com> > Subject: Re: [PATCH v5 2/2] QE: remove PPCisms for QE > > On Tue, Sep 20, 2016 at 8:13 PM, Qiang Zhao <qiang.z...@nxp.com> wrote: > > On Mon, Sep 20, 2016 at 4:13 AM, Leo Li wrote: > >> -Original Message- > >> From: Leo Li [mailto:pku@gmail.com] > >> Sent: Tuesday, September 20, 2016 4:13 AM > >> To: Qiang Zhao <qiang.z...@nxp.com> > >> Cc: Scott Wood <o...@buserror.net>; linuxppc-dev >> d...@lists.ozlabs.org>; lkml <linux-kernel@vger.kernel.org>; X.B. Xie > >> <xiaobo@nxp.com> > >> Subject: Re: [PATCH v5 2/2] QE: remove PPCisms for QE > >> > >> On Mon, Jul 25, 2016 at 12:43 AM, Zhao Qiang <qiang.z...@nxp.com> > wrote: > >> > QE was supported on PowerPC, and dependent on PPC, Now it is > >> > supported on other platforms. so remove PPCisms. > >> > > >> > Signed-off-by: Zhao Qiang <qiang.z...@nxp.com> > >> > --- > >> > Changes for v2: > >> > - na > >> > Changes for v3: > >> > - add NO_IRQ > >> > Changes for v4: > >> > - modify spin_event_timeout to opencoded timeout loop > >> > - remove NO_IRQ > >> > - modify virq_to_hw to opencoed code Changes for v5: > >> > - modify commit msg > >> > - modify depends of QUICC_ENGINE > >> > - add kerneldoc header for qe_issue_cmd > >> > > >> > drivers/irqchip/qe_ic.c | 28 +-- > >> > drivers/soc/fsl/qe/Kconfig| 2 +- > >> > drivers/soc/fsl/qe/qe.c | 80 ++-- > > >> --- > >> > drivers/soc/fsl/qe/qe_io.c| 42 ++- > >> > drivers/soc/fsl/qe/qe_tdm.c | 8 ++--- > >> > drivers/soc/fsl/qe/ucc.c | 10 +++--- > >> > drivers/soc/fsl/qe/ucc_fast.c | 68 ++-- > >> > include/soc/fsl/qe/qe.h | 1 - > >> > include/soc/fsl/qe/qe_ic.h| 12 +++ > >> > 9 files changed, 133 insertions(+), 118 deletions(-) > >> > > >> > >> [snip] > >> > >> > diff --git a/drivers/soc/fsl/qe/Kconfig > >> > b/drivers/soc/fsl/qe/Kconfig index 73a2e08..b26b643 100644 > >> > --- a/drivers/soc/fsl/qe/Kconfig > >> > +++ b/drivers/soc/fsl/qe/Kconfig > >> > @@ -4,7 +4,7 @@ > >> > > >> > config QUICC_ENGINE > >> > bool "Freescale QUICC Engine (QE) Support" > >> > - depends on FSL_SOC && PPC32 > >> > + depends on OF && HAS_IOMEM > >> > select GENERIC_ALLOCATOR > >> > select CRC32 > >> > help > >> > >> You make it possible to build QE drivers on ARM, but the UCC_GETH > >> fails to build on arm64. Please make sure all these drivers can > >> build on other architectures. Or you can simply make them only build > >> for Power architecture as most of them are not available on ARM. > >> > > > > Most of them are not available on ARM and ARM64. > > Now, only qe-hdlc is available on ARM64. > > Then you should update the Kconfig for these drivers too, if they are only > depending on CONFIG_QUICC_ENGINE. You mean adding "depends on FSL_SOC && PPC32 " to the drivers that are not available for ARM? BR -Zhao Qiang
RE: [PATCH v5 2/2] QE: remove PPCisms for QE
On Mon, Sep 22, 2016 at 2:19 AM, Leo Li wrote: > -Original Message- > From: Leo Li [mailto:pku@gmail.com] > Sent: Thursday, September 22, 2016 2:19 AM > To: Qiang Zhao > Cc: Scott Wood ; linuxppc-dev d...@lists.ozlabs.org>; lkml ; X.B. Xie > > Subject: Re: [PATCH v5 2/2] QE: remove PPCisms for QE > > On Tue, Sep 20, 2016 at 8:13 PM, Qiang Zhao wrote: > > On Mon, Sep 20, 2016 at 4:13 AM, Leo Li wrote: > >> -Original Message- > >> From: Leo Li [mailto:pku@gmail.com] > >> Sent: Tuesday, September 20, 2016 4:13 AM > >> To: Qiang Zhao > >> Cc: Scott Wood ; linuxppc-dev >> d...@lists.ozlabs.org>; lkml ; X.B. Xie > >> > >> Subject: Re: [PATCH v5 2/2] QE: remove PPCisms for QE > >> > >> On Mon, Jul 25, 2016 at 12:43 AM, Zhao Qiang > wrote: > >> > QE was supported on PowerPC, and dependent on PPC, Now it is > >> > supported on other platforms. so remove PPCisms. > >> > > >> > Signed-off-by: Zhao Qiang > >> > --- > >> > Changes for v2: > >> > - na > >> > Changes for v3: > >> > - add NO_IRQ > >> > Changes for v4: > >> > - modify spin_event_timeout to opencoded timeout loop > >> > - remove NO_IRQ > >> > - modify virq_to_hw to opencoed code Changes for v5: > >> > - modify commit msg > >> > - modify depends of QUICC_ENGINE > >> > - add kerneldoc header for qe_issue_cmd > >> > > >> > drivers/irqchip/qe_ic.c | 28 +-- > >> > drivers/soc/fsl/qe/Kconfig| 2 +- > >> > drivers/soc/fsl/qe/qe.c | 80 ++-- > > >> --- > >> > drivers/soc/fsl/qe/qe_io.c| 42 ++- > >> > drivers/soc/fsl/qe/qe_tdm.c | 8 ++--- > >> > drivers/soc/fsl/qe/ucc.c | 10 +++--- > >> > drivers/soc/fsl/qe/ucc_fast.c | 68 ++-- > >> > include/soc/fsl/qe/qe.h | 1 - > >> > include/soc/fsl/qe/qe_ic.h| 12 +++ > >> > 9 files changed, 133 insertions(+), 118 deletions(-) > >> > > >> > >> [snip] > >> > >> > diff --git a/drivers/soc/fsl/qe/Kconfig > >> > b/drivers/soc/fsl/qe/Kconfig index 73a2e08..b26b643 100644 > >> > --- a/drivers/soc/fsl/qe/Kconfig > >> > +++ b/drivers/soc/fsl/qe/Kconfig > >> > @@ -4,7 +4,7 @@ > >> > > >> > config QUICC_ENGINE > >> > bool "Freescale QUICC Engine (QE) Support" > >> > - depends on FSL_SOC && PPC32 > >> > + depends on OF && HAS_IOMEM > >> > select GENERIC_ALLOCATOR > >> > select CRC32 > >> > help > >> > >> You make it possible to build QE drivers on ARM, but the UCC_GETH > >> fails to build on arm64. Please make sure all these drivers can > >> build on other architectures. Or you can simply make them only build > >> for Power architecture as most of them are not available on ARM. > >> > > > > Most of them are not available on ARM and ARM64. > > Now, only qe-hdlc is available on ARM64. > > Then you should update the Kconfig for these drivers too, if they are only > depending on CONFIG_QUICC_ENGINE. You mean adding "depends on FSL_SOC && PPC32 " to the drivers that are not available for ARM? BR -Zhao Qiang
RE: [PATCH v5 2/2] QE: remove PPCisms for QE
On Mon, Sep 20, 2016 at 4:13 AM, Leo Li wrote: > -Original Message- > From: Leo Li [mailto:pku@gmail.com] > Sent: Tuesday, September 20, 2016 4:13 AM > To: Qiang Zhao <qiang.z...@nxp.com> > Cc: Scott Wood <o...@buserror.net>; linuxppc-dev d...@lists.ozlabs.org>; lkml <linux-kernel@vger.kernel.org>; X.B. Xie > <xiaobo@nxp.com> > Subject: Re: [PATCH v5 2/2] QE: remove PPCisms for QE > > On Mon, Jul 25, 2016 at 12:43 AM, Zhao Qiang <qiang.z...@nxp.com> wrote: > > QE was supported on PowerPC, and dependent on PPC, Now it is supported > > on other platforms. so remove PPCisms. > > > > Signed-off-by: Zhao Qiang <qiang.z...@nxp.com> > > --- > > Changes for v2: > > - na > > Changes for v3: > > - add NO_IRQ > > Changes for v4: > > - modify spin_event_timeout to opencoded timeout loop > > - remove NO_IRQ > > - modify virq_to_hw to opencoed code Changes for v5: > > - modify commit msg > > - modify depends of QUICC_ENGINE > > - add kerneldoc header for qe_issue_cmd > > > > drivers/irqchip/qe_ic.c | 28 +-- > > drivers/soc/fsl/qe/Kconfig| 2 +- > > drivers/soc/fsl/qe/qe.c | 80 ++-- > --- > > drivers/soc/fsl/qe/qe_io.c| 42 ++- > > drivers/soc/fsl/qe/qe_tdm.c | 8 ++--- > > drivers/soc/fsl/qe/ucc.c | 10 +++--- > > drivers/soc/fsl/qe/ucc_fast.c | 68 ++-- > > include/soc/fsl/qe/qe.h | 1 - > > include/soc/fsl/qe/qe_ic.h| 12 +++ > > 9 files changed, 133 insertions(+), 118 deletions(-) > > > > [snip] > > > diff --git a/drivers/soc/fsl/qe/Kconfig b/drivers/soc/fsl/qe/Kconfig > > index 73a2e08..b26b643 100644 > > --- a/drivers/soc/fsl/qe/Kconfig > > +++ b/drivers/soc/fsl/qe/Kconfig > > @@ -4,7 +4,7 @@ > > > > config QUICC_ENGINE > > bool "Freescale QUICC Engine (QE) Support" > > - depends on FSL_SOC && PPC32 > > + depends on OF && HAS_IOMEM > > select GENERIC_ALLOCATOR > > select CRC32 > > help > > You make it possible to build QE drivers on ARM, but the UCC_GETH fails to > build on arm64. Please make sure all these drivers can build on other > architectures. Or you can simply make them only build for Power architecture > as most of them are not available on ARM. > Most of them are not available on ARM and ARM64. Now, only qe-hdlc is available on ARM64. BR -Zhao Qiang
RE: [PATCH v5 2/2] QE: remove PPCisms for QE
On Mon, Sep 20, 2016 at 4:13 AM, Leo Li wrote: > -Original Message- > From: Leo Li [mailto:pku@gmail.com] > Sent: Tuesday, September 20, 2016 4:13 AM > To: Qiang Zhao > Cc: Scott Wood ; linuxppc-dev d...@lists.ozlabs.org>; lkml ; X.B. Xie > > Subject: Re: [PATCH v5 2/2] QE: remove PPCisms for QE > > On Mon, Jul 25, 2016 at 12:43 AM, Zhao Qiang wrote: > > QE was supported on PowerPC, and dependent on PPC, Now it is supported > > on other platforms. so remove PPCisms. > > > > Signed-off-by: Zhao Qiang > > --- > > Changes for v2: > > - na > > Changes for v3: > > - add NO_IRQ > > Changes for v4: > > - modify spin_event_timeout to opencoded timeout loop > > - remove NO_IRQ > > - modify virq_to_hw to opencoed code Changes for v5: > > - modify commit msg > > - modify depends of QUICC_ENGINE > > - add kerneldoc header for qe_issue_cmd > > > > drivers/irqchip/qe_ic.c | 28 +-- > > drivers/soc/fsl/qe/Kconfig| 2 +- > > drivers/soc/fsl/qe/qe.c | 80 ++-- > --- > > drivers/soc/fsl/qe/qe_io.c| 42 ++- > > drivers/soc/fsl/qe/qe_tdm.c | 8 ++--- > > drivers/soc/fsl/qe/ucc.c | 10 +++--- > > drivers/soc/fsl/qe/ucc_fast.c | 68 ++-- > > include/soc/fsl/qe/qe.h | 1 - > > include/soc/fsl/qe/qe_ic.h| 12 +++ > > 9 files changed, 133 insertions(+), 118 deletions(-) > > > > [snip] > > > diff --git a/drivers/soc/fsl/qe/Kconfig b/drivers/soc/fsl/qe/Kconfig > > index 73a2e08..b26b643 100644 > > --- a/drivers/soc/fsl/qe/Kconfig > > +++ b/drivers/soc/fsl/qe/Kconfig > > @@ -4,7 +4,7 @@ > > > > config QUICC_ENGINE > > bool "Freescale QUICC Engine (QE) Support" > > - depends on FSL_SOC && PPC32 > > + depends on OF && HAS_IOMEM > > select GENERIC_ALLOCATOR > > select CRC32 > > help > > You make it possible to build QE drivers on ARM, but the UCC_GETH fails to > build on arm64. Please make sure all these drivers can build on other > architectures. Or you can simply make them only build for Power architecture > as most of them are not available on ARM. > Most of them are not available on ARM and ARM64. Now, only qe-hdlc is available on ARM64. BR -Zhao Qiang
