[llvm-commits] [llvm] r42906 - /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Author: djg
Date: Fri Oct 12 09:13:46 2007
New Revision: 42906
URL: http://llvm.org/viewvc/llvm-project?rev=42906view=rev
Log:
Add support to SplitVectorOp for powi, where the second operand
is a scalar integer.
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=42906r1=42905r2=42906view=diff
==
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Oct 12 09:13:46 2007
@@ -6335,6 +6335,12 @@
NewVT,
ScalarizeVectorOp(Node-getOperand(0)));
break;
+ case ISD::FPOWI:
+Result = DAG.getNode(Node-getOpcode(),
+ NewVT,
+ ScalarizeVectorOp(Node-getOperand(0)),
+ Node-getOperand(1));
+break;
case ISD::LOAD: {
LoadSDNode *LD = castLoadSDNode(Node);
SDOperand Ch = LegalizeOp(LD-getChain()); // Legalize the chain.
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[llvm-commits] [llvm] r42905 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Author: djg
Date: Fri Oct 12 09:09:42 2007
New Revision: 42905
URL: http://llvm.org/viewvc/llvm-project?rev=42905view=rev
Log:
Mark vector ctpop, cttz, and ctlz as Expand on x86.
Modified:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=42905r1=42904r2=42905view=diff
==
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Oct 12 09:09:42 2007
@@ -477,6 +477,9 @@
setOperationAction(ISD::SDIVREM, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::UDIVREM, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::FPOW, (MVT::ValueType)VT, Expand);
+setOperationAction(ISD::CTPOP, (MVT::ValueType)VT, Expand);
+setOperationAction(ISD::CTTZ, (MVT::ValueType)VT, Expand);
+setOperationAction(ISD::CTLZ, (MVT::ValueType)VT, Expand);
}
if (Subtarget-hasMMX()) {
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[llvm-commits] [llvm] r42904 - /llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
Author: djg Date: Fri Oct 12 09:08:57 2007 New Revision: 42904 URL: http://llvm.org/viewvc/llvm-project?rev=42904view=rev Log: Mark vector pow, ctpop, cttz, and ctlz as Expand on PowerPC. Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=42904r1=42903r2=42904view=diff == --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Fri Oct 12 09:08:57 2007 @@ -284,8 +284,11 @@ setOperationAction(ISD::SMUL_LOHI, (MVT::ValueType)VT, Expand); setOperationAction(ISD::UDIVREM, (MVT::ValueType)VT, Expand); setOperationAction(ISD::SDIVREM, (MVT::ValueType)VT, Expand); - setOperationAction(ISD::SCALAR_TO_VECTOR, (MVT::ValueType)VT, Expand); + setOperationAction(ISD::FPOW, (MVT::ValueType)VT, Expand); + setOperationAction(ISD::CTPOP, (MVT::ValueType)VT, Expand); + setOperationAction(ISD::CTLZ, (MVT::ValueType)VT, Expand); + setOperationAction(ISD::CTTZ, (MVT::ValueType)VT, Expand); } // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r42932 - /llvm/trunk/test/CodeGen/X86/fp_constant_op.llx
Author: djg
Date: Fri Oct 12 15:42:14 2007
New Revision: 42932
URL: http://llvm.org/viewvc/llvm-project?rev=42932view=rev
Log:
Fix this test to not depend on the assembly output containing something
that includes the string st. This probably fixes the regression on
Darwin.
Modified:
llvm/trunk/test/CodeGen/X86/fp_constant_op.llx
Modified: llvm/trunk/test/CodeGen/X86/fp_constant_op.llx
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fp_constant_op.llx?rev=42932r1=42931r2=42932view=diff
==
--- llvm/trunk/test/CodeGen/X86/fp_constant_op.llx (original)
+++ llvm/trunk/test/CodeGen/X86/fp_constant_op.llx Fri Oct 12 15:42:14 2007
@@ -1,5 +1,5 @@
; RUN: llvm-upgrade %s | llvm-as | llc -march=x86 -x86-asm-syntax=intel
-mcpu=i486 | \
-; RUN: grep -i ST | not grep {fadd\\|fsub\\|fdiv\\|fmul}
+; RUN: grep {fadd\\|fsub\\|fdiv\\|fmul} | not grep -i ST
; Test that the load of the constant is folded into the operation.
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Re: [llvm-commits] darwin x86 make check failures
Anyone want to claim them? ;)
I confirm this is happening, but it was not happening until I did a
checkout.
They're both due to 42908.
2006-10-19-SwitchUnnecessaryBranching.ll was introduced by the change
in label names.
It looks like there was an attempt to fix it once, so it's probably
OS dependent. On darwin
it's trying to match LBB1__main (2 underscores) with BB1_main (1
underscore).
I'll add a target triple to make this one behave consistently.
The other one is failing doing
grep -i ST | not grep {fadd\\|fsub\\|fdiv\\|fmul}
There are no lines that match ST (correctly IMO). I would expect
not grep to succeed
on null input, but apparently it doesn't. It's not obvious what the
grep for ST is trying to
do, but I doubt this is still testing what it was supposed to test.
I just submitted a fix for this one. I believe it now tests what
it's supposed to.
Dan
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Re: [llvm-commits] [llvm] r42864 - in /llvm/trunk: lib/Transforms/Scalar/InstructionCombining.cpp test/Transforms/InstCombine/2007-10-10-EliminateMemCpy.ll
+ // If MemCpyInst length is 1/2/4/8 bytes then replace memcpy with
load/store
Neat!
+ ConstantInt *MemOpLength = dyn_castConstantInt(CI.getOperand(3));
+ if (isaMemCpyInst(MI))
+if (MemOpLength) {
Can you replace these two if statements with
if (isaMemCpyInst(MI) MemOpLength) {
?
Then the indentation of what follows won't be wrong either :-)
+unsigned Size = MemOpLength-getZExtValue();
+unsigned Align = castConstantInt(CI.getOperand(4))-getZExtValue();
+const PointerType *PTy =
castPointerType(CI.getOperand(1)-getType());
+const Type *MTy = PTy-getElementType();
+PointerType *NewPtrTy = NULL;
+if (MTy == Type::Int8Ty) {
+ if (Size == 8)
+NewPtrTy = PointerType::get(Type::Int64Ty);
+ else if (Size == 4)
+NewPtrTy = PointerType::get(Type::Int32Ty);
+ else if (Size == 2)
+NewPtrTy = PointerType::get(Type::Int16Ty);
+ else if (Size == 1)
+NewPtrTy = PointerType::get(Type::Int8Ty);
+} else if (MTy == Type::Int16Ty) {
+ if (Size == 4)
+NewPtrTy = PointerType::get(Type::Int64Ty);
+ else if (Size == 2)
+NewPtrTy = PointerType::get(Type::Int32Ty);
+ else if (Size == 1)
+NewPtrTy = PointerType::get(Type::Int16Ty);
+} else if (MTy == Type::Int32Ty) {
+ if (Size == 2)
+NewPtrTy = PointerType::get(Type::Int64Ty);
+ else if (Size == 1)
+NewPtrTy = PointerType::get(Type::Int32Ty);
+} else if (MTy == Type::Int64Ty) {
+ if (Size == 1)
+NewPtrTy = PointerType::get(Type::Int64Ty);
+}
It'd be great it this worked for non-scalar-integer types as well.
Maybe you could do something like (warning, untested):
if (Size == 1 MTy-isFirstClassType())
NewPtrTy = PointerType::get(MTy)
else {
CopySize = Size * TD-getABITypeSizeInBits(MTy);
if (CopySize == 8 || CopySize == 4 || CopySize == 2 || CopySize == 1)
NewPtrTy = PointerType::get(IntegerType::get(CopySize));
}
?
+if (NewPtrTy)
+{
LLVM style.
+ Value *Src = InsertCastBefore(Instruction::BitCast,
CI.getOperand(2), NewPtrTy, CI);
+ Value *Dest = InsertCastBefore(Instruction::BitCast,
CI.getOperand(1), NewPtrTy, CI);
This is more than 80 columns.
+ Value *L = new LoadInst(Src, tmp, false, Align, CI);
+ Value *NS = new StoreInst(L, Dest, false, Align, CI);
+ CI.replaceAllUsesWith(NS);
+ Changed = true;
+ return EraseInstFromFunction(CI);
+}
+ }
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Re: [llvm-commits] [llvm] r42864 - in /llvm/trunk: lib/Transforms/Scalar/InstructionCombining.cpp test/Transforms/InstCombine/2007-10-10-EliminateMemCpy.ll
On Thu, Oct 11, 2007 at 05:08:55PM -0500, Dan Gohman wrote:
+unsigned Size = MemOpLength-getZExtValue();
+unsigned Align =
castConstantInt(CI.getOperand(4))-getZExtValue();
+const PointerType *PTy =
castPointerType(CI.getOperand(1)-getType());
+const Type *MTy = PTy-getElementType();
+PointerType *NewPtrTy = NULL;
+if (MTy == Type::Int8Ty) {
+ if (Size == 8)
+NewPtrTy = PointerType::get(Type::Int64Ty);
+ else if (Size == 4)
+NewPtrTy = PointerType::get(Type::Int32Ty);
+ else if (Size == 2)
+NewPtrTy = PointerType::get(Type::Int16Ty);
+ else if (Size == 1)
+NewPtrTy = PointerType::get(Type::Int8Ty);
+} else if (MTy == Type::Int16Ty) {
+ if (Size == 4)
+NewPtrTy = PointerType::get(Type::Int64Ty);
+ else if (Size == 2)
+NewPtrTy = PointerType::get(Type::Int32Ty);
+ else if (Size == 1)
+NewPtrTy = PointerType::get(Type::Int16Ty);
+} else if (MTy == Type::Int32Ty) {
+ if (Size == 2)
+NewPtrTy = PointerType::get(Type::Int64Ty);
+ else if (Size == 1)
+NewPtrTy = PointerType::get(Type::Int32Ty);
+} else if (MTy == Type::Int64Ty) {
+ if (Size == 1)
+NewPtrTy = PointerType::get(Type::Int64Ty);
+}
It'd be great it this worked for non-scalar-integer types as well.
Maybe you could do something like (warning, untested):
if (Size == 1 MTy-isFirstClassType())
NewPtrTy = PointerType::get(MTy)
else {
CopySize = Size * TD-getABITypeSizeInBits(MTy);
if (CopySize == 8 || CopySize == 4 || CopySize == 2 || CopySize == 1)
NewPtrTy = PointerType::get(IntegerType::get(CopySize));
}
?
Oops, looking at this a little more, isn't the Size operand always in
straight bytes, and MTy always i8, just because of how llvm.memcpy is
declared?
Also, this code can be used for memmove as well as memcpy; since the load
grabs the entire source before anything is stored, overlap cases would work
correctly.
Dan
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[llvm-commits] [llvm] r42878 - /llvm/trunk/test/CodeGen/X86/2007-09-17-ObjcFrameEH.ll
Author: djg
Date: Thu Oct 11 18:04:36 2007
New Revision: 42878
URL: http://llvm.org/viewvc/llvm-project?rev=42878view=rev
Log:
Add an explicit target triple to make this test behave as expected on
non-Apple hosts. And use the count script instead of wc + grep.
Modified:
llvm/trunk/test/CodeGen/X86/2007-09-17-ObjcFrameEH.ll
Modified: llvm/trunk/test/CodeGen/X86/2007-09-17-ObjcFrameEH.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2007-09-17-ObjcFrameEH.ll?rev=42878r1=42877r2=42878view=diff
==
--- llvm/trunk/test/CodeGen/X86/2007-09-17-ObjcFrameEH.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2007-09-17-ObjcFrameEH.ll Thu Oct 11 18:04:36
2007
@@ -1,4 +1,4 @@
-; RUN: llvm-as %s | llc -march=x86 -enable-eh | grep {isNullOrNil].eh} | wc
-l | grep 2
+; RUN: llvm-as %s | llc -march=x86 -mtriple=i686-apple-darwin -enable-eh |
grep {isNullOrNil].eh} | count 2
%struct.NSString = type { }
%struct._objc__method_prototype_list = type opaque
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[llvm-commits] [llvm] r42879 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAGNodes.h lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Author: djg Date: Thu Oct 11 18:06:37 2007 New Revision: 42879 URL: http://llvm.org/viewvc/llvm-project?rev=42879view=rev Log: Add an ISD::FPOW node type. Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=42879r1=42878r2=42879view=diff == --- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Thu Oct 11 18:06:37 2007 @@ -408,10 +408,10 @@ // conversions, but that is a noop, deleted by getNode(). BIT_CONVERT, -// FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI - Perform unary floating point -// negation, absolute value, square root, sine and cosine, and powi +// FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW - Perform unary floating point +// negation, absolute value, square root, sine and cosine, powi, and pow // operations. -FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, +FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, // LOAD and STORE have token chains as their first operand, then the same // operands as an LLVM load/store instruction, then an offset node that Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=42879r1=42878r2=42879view=diff == --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Thu Oct 11 18:06:37 2007 @@ -3602,6 +3602,7 @@ case ISD::FSIN: return fsin; case ISD::FCOS: return fcos; case ISD::FPOWI: return fpowi; + case ISD::FPOW: return fpow; // Binary operators case ISD::ADD:return add; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r42880 - in /llvm/trunk: include/llvm/CodeGen/RuntimeLibcalls.h lib/CodeGen/SelectionDAG/TargetLowering.cpp
Author: djg Date: Thu Oct 11 18:09:10 2007 New Revision: 42880 URL: http://llvm.org/viewvc/llvm-project?rev=42880view=rev Log: Add runtime library names for pow. Modified: llvm/trunk/include/llvm/CodeGen/RuntimeLibcalls.h llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Modified: llvm/trunk/include/llvm/CodeGen/RuntimeLibcalls.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/RuntimeLibcalls.h?rev=42880r1=42879r2=42880view=diff == --- llvm/trunk/include/llvm/CodeGen/RuntimeLibcalls.h (original) +++ llvm/trunk/include/llvm/CodeGen/RuntimeLibcalls.h Thu Oct 11 18:09:10 2007 @@ -72,6 +72,10 @@ SIN_F64, COS_F32, COS_F64, +POW_F32, +POW_F64, +POW_F80, +POW_PPCF128, // CONVERSION FPEXT_F32_F64, Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=42880r1=42879r2=42880view=diff == --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Thu Oct 11 18:09:10 2007 @@ -73,6 +73,10 @@ Names[RTLIB::SIN_F64] = sin; Names[RTLIB::COS_F32] = cosf; Names[RTLIB::COS_F64] = cos; + Names[RTLIB::POW_F32] = powf; + Names[RTLIB::POW_F64] = pow; + Names[RTLIB::POW_F80] = powl; + Names[RTLIB::POW_PPCF128] = powl; Names[RTLIB::FPEXT_F32_F64] = __extendsfdf2; Names[RTLIB::FPROUND_F64_F32] = __truncdfsf2; Names[RTLIB::FPTOSINT_F32_I32] = __fixsfsi; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r42881 - in /llvm/trunk/lib/Target: ARM/ARMISelLowering.cpp Alpha/AlphaISelLowering.cpp IA64/IA64ISelLowering.cpp PowerPC/PPCISelLowering.cpp Sparc/SparcISelDAGToDAG.cpp X86/X86I
Author: djg Date: Thu Oct 11 18:21:31 2007 New Revision: 42881 URL: http://llvm.org/viewvc/llvm-project?rev=42881view=rev Log: Set ISD::FPOW to Expand. Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=42881r1=42880r2=42881view=diff == --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Oct 11 18:21:31 2007 @@ -240,7 +240,7 @@ setOperationAction(ISD::ConstantFP, MVT::f64, Expand); setOperationAction(ISD::ConstantFP, MVT::f32, Expand); - // We don't support sin/cos/fmod/copysign + // We don't support sin/cos/fmod/copysign/pow setOperationAction(ISD::FSIN , MVT::f64, Expand); setOperationAction(ISD::FSIN , MVT::f32, Expand); setOperationAction(ISD::FCOS , MVT::f32, Expand); @@ -249,6 +249,8 @@ setOperationAction(ISD::FREM , MVT::f32, Expand); setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); + setOperationAction(ISD::FPOW , MVT::f64, Expand); + setOperationAction(ISD::FPOW , MVT::f32, Expand); // int - fp are custom expanded into bit_convert + ARMISD ops. setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); Modified: llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp?rev=42881r1=42880r2=42881view=diff == --- llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp Thu Oct 11 18:21:31 2007 @@ -93,7 +93,7 @@ setOperationAction(ISD::MEMSET , MVT::Other, Expand); setOperationAction(ISD::MEMCPY , MVT::Other, Expand); - // We don't support sin/cos/sqrt + // We don't support sin/cos/sqrt/pow setOperationAction(ISD::FSIN , MVT::f64, Expand); setOperationAction(ISD::FCOS , MVT::f64, Expand); setOperationAction(ISD::FSIN , MVT::f32, Expand); @@ -101,6 +101,9 @@ setOperationAction(ISD::FSQRT, MVT::f64, Expand); setOperationAction(ISD::FSQRT, MVT::f32, Expand); + + setOperationAction(ISD::FPOW , MVT::f32, Expand); + setOperationAction(ISD::FPOW , MVT::f64, Expand); setOperationAction(ISD::SETCC, MVT::f32, Promote); Modified: llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp?rev=42881r1=42880r2=42881view=diff == --- llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp Thu Oct 11 18:21:31 2007 @@ -73,13 +73,15 @@ setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); - // We don't support sin/cos/sqrt + // We don't support sin/cos/sqrt/pow setOperationAction(ISD::FSIN , MVT::f64, Expand); setOperationAction(ISD::FCOS , MVT::f64, Expand); setOperationAction(ISD::FSQRT, MVT::f64, Expand); + setOperationAction(ISD::FPOW , MVT::f64, Expand); setOperationAction(ISD::FSIN , MVT::f32, Expand); setOperationAction(ISD::FCOS , MVT::f32, Expand); setOperationAction(ISD::FSQRT, MVT::f32, Expand); + setOperationAction(ISD::FPOW , MVT::f32, Expand); // FIXME: IA64 supports fcopysign natively! setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=42881r1=42880r2=42881view=diff == --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Thu Oct 11 18:21:31 2007 @@ -101,13 +101,15 @@ setOperationAction(ISD::UDIVREM, MVT::i64, Expand); setOperationAction(ISD::SDIVREM, MVT::i64, Expand); - // We don't support sin/cos/sqrt/fmod + // We don't support sin/cos/sqrt/fmod/pow setOperationAction(ISD::FSIN , MVT::f64, Expand); setOperationAction(ISD::FCOS , MVT::f64, Expand); setOperationAction(ISD::FREM , MVT::f64, Expand); + setOperationAction(ISD::FPOW , MVT::f64, Expand); setOperationAction(ISD::FSIN , MVT::f32, Expand); setOperationAction(ISD::FCOS , MVT::f32, Expand);
[llvm-commits] [llvm] r42884 - /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Author: djg
Date: Thu Oct 11 18:57:53 2007
New Revision: 42884
URL: http://llvm.org/viewvc/llvm-project?rev=42884view=rev
Log:
Codegen support for vector intrinsics.
Factor out the code that expands the nasty scalar code for unrolling
vectors into a separate routine, teach it how to handle mixed
vector/scalar operands, as seen in powi, and use it for several operators,
including sin, cos, powi, and pow.
Add support in SplitVectorOp for fpow, fpowi and for several unary
operators.
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=42884r1=42883r2=42884view=diff
==
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Thu Oct 11 18:57:53 2007
@@ -147,6 +147,12 @@
/// result.
SDOperand LegalizeOp(SDOperand O);
+ /// UnrollVectorOp - We know that the given vector has a legal type, however
+ /// the operation it performs is not legal and is an operation that we have
+ /// no way of lowering. Unroll the vector, splitting out the scalars and
+ /// operating on each element individually.
+ SDOperand UnrollVectorOp(SDOperand O);
+
/// PromoteOp - Given an operation that produces a value in an invalid type,
/// promote it to compute the value into a larger type. The produced value
/// will have the correct bits for the low portion of the register, but no
@@ -679,6 +685,44 @@
return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), Ops, 2);
}
+/// UnrollVectorOp - We know that the given vector has a legal type, however
+/// the operation it performs is not legal and is an operation that we have
+/// no way of lowering. Unroll the vector, splitting out the scalars and
+/// operating on each element individually.
+SDOperand SelectionDAGLegalize::UnrollVectorOp(SDOperand Op) {
+ MVT::ValueType VT = Op.getValueType();
+ assert(isTypeLegal(VT)
+ Caller should expand or promote operands that are not legal!);
+ assert(Op.Val-getNumValues() == 1
+ Can't unroll a vector with multiple results!);
+ unsigned NE = MVT::getVectorNumElements(VT);
+ MVT::ValueType EltVT = MVT::getVectorElementType(VT);
+
+ SmallVectorSDOperand, 8 Scalars;
+ SmallVectorSDOperand, 4 Operands(Op.getNumOperands());
+ for (unsigned i = 0; i != NE; ++i) {
+for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
+ SDOperand Operand = Op.getOperand(j);
+ MVT::ValueType OperandVT = Operand.getValueType();
+ if (MVT::isVector(OperandVT)) {
+// A vector operand; extract a single element.
+MVT::ValueType OperandEltVT = MVT::getVectorElementType(OperandVT);
+Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
+ OperandEltVT,
+ Operand,
+ DAG.getConstant(i, MVT::i32));
+ } else {
+// A scalar operand; just use it as is.
+Operands[j] = Operand;
+ }
+}
+Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT,
+ Operands[0], Operands.size()));
+ }
+
+ return DAG.getNode(ISD::BUILD_VECTOR, VT, Scalars[0], Scalars.size());
+}
+
/// LegalizeOp - We know that the specified value has a legal type, and
/// that its operands are legal. Now ensure that the operation itself
/// is legal, recursively ensuring that the operands' operations remain
@@ -2556,6 +2600,7 @@
case ISD::FSUB:
case ISD::FMUL:
case ISD::FDIV:
+ case ISD::FPOW:
Tmp1 = LegalizeOp(Node-getOperand(0)); // LHS
switch (getTypeAction(Node-getOperand(1).getValueType())) {
case Expand: assert(0 Not possible);
@@ -2626,35 +2671,37 @@
break;
}
- if (Node-getValueType(0) == MVT::i32) {
-switch (Node-getOpcode()) {
-default: assert(0 Do not know how to expand this integer BinOp!);
-case ISD::UDIV:
-case ISD::SDIV:
- RTLIB::Libcall LC = Node-getOpcode() == ISD::UDIV
+ // Check to see if we have a libcall for this operator.
+ RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
+ bool isSigned = false;
+ switch (Node-getOpcode()) {
+ case ISD::UDIV:
+ case ISD::SDIV:
+if (VT == MVT::i32) {
+ LC = Node-getOpcode() == ISD::UDIV
? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
- SDOperand Dummy;
- bool isSigned = Node-getOpcode() == ISD::SDIV;
- Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned,
Dummy);
-};
+ isSigned = Node-getOpcode() == ISD::SDIV;
+}
+break;
+ case ISD::FPOW:
+LC = VT == MVT::f32 ? RTLIB::POW_F32 :
+ VT == MVT::f64 ? RTLIB::POW_F64 :
+ VT == MVT::f80 ? RTLIB::POW_F80 :
[llvm-commits] [llvm] r42885 - in /llvm/trunk: include/llvm/Intrinsics.td lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp test/CodeGen/X86/vector-intrinsics.ll
Author: djg
Date: Thu Oct 11 19:01:22 2007
New Revision: 42885
URL: http://llvm.org/viewvc/llvm-project?rev=42885view=rev
Log:
Add intrinsics for sin, cos, and pow. These use llvm_anyfloat_ty, and so
may be overloaded with vector types. And add a testcase for codegen for
these.
Added:
llvm/trunk/test/CodeGen/X86/vector-intrinsics.ll
Modified:
llvm/trunk/include/llvm/Intrinsics.td
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Modified: llvm/trunk/include/llvm/Intrinsics.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Intrinsics.td?rev=42885r1=42884r2=42885view=diff
==
--- llvm/trunk/include/llvm/Intrinsics.td (original)
+++ llvm/trunk/include/llvm/Intrinsics.td Thu Oct 11 19:01:22 2007
@@ -184,6 +184,10 @@
let Properties = [IntrNoMem] in {
def int_sqrt : Intrinsic[llvm_anyfloat_ty, LLVMMatchType0];
def int_powi : Intrinsic[llvm_anyfloat_ty, LLVMMatchType0, llvm_i32_ty];
+ def int_sin : Intrinsic[llvm_anyfloat_ty, LLVMMatchType0];
+ def int_cos : Intrinsic[llvm_anyfloat_ty, LLVMMatchType0];
+ def int_pow : Intrinsic[llvm_anyfloat_ty,
+LLVMMatchType0, LLVMMatchType0];
}
// NOTE: these are internal interfaces.
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=42885r1=42884r2=42885view=diff
==
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu Oct 11
19:01:22 2007
@@ -2807,6 +2807,22 @@
getValue(I.getOperand(1)),
getValue(I.getOperand(2;
return 0;
+ case Intrinsic::sin:
+setValue(I, DAG.getNode(ISD::FSIN,
+ getValue(I.getOperand(1)).getValueType(),
+ getValue(I.getOperand(1;
+return 0;
+ case Intrinsic::cos:
+setValue(I, DAG.getNode(ISD::FCOS,
+ getValue(I.getOperand(1)).getValueType(),
+ getValue(I.getOperand(1;
+return 0;
+ case Intrinsic::pow:
+setValue(I, DAG.getNode(ISD::FPOW,
+ getValue(I.getOperand(1)).getValueType(),
+ getValue(I.getOperand(1)),
+ getValue(I.getOperand(2;
+return 0;
case Intrinsic::pcmarker: {
SDOperand Tmp = getValue(I.getOperand(1));
DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
Added: llvm/trunk/test/CodeGen/X86/vector-intrinsics.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-intrinsics.ll?rev=42885view=auto
==
--- llvm/trunk/test/CodeGen/X86/vector-intrinsics.ll (added)
+++ llvm/trunk/test/CodeGen/X86/vector-intrinsics.ll Thu Oct 11 19:01:22 2007
@@ -0,0 +1,27 @@
+; RUN: llvm-as %s | llc -march=x86-64 | grep call | count 16
+
+declare 4 x double @llvm.sin.v4f64(4 x double %p)
+declare 4 x double @llvm.cos.v4f64(4 x double %p)
+declare 4 x double @llvm.pow.v4f64(4 x double %p, 4 x double %q)
+declare 4 x double @llvm.powi.v4f64(4 x double %p, i32)
+
+define 4 x double @foo(4 x double %p)
+{
+ %t = call 4 x double @llvm.sin.v4f64(4 x double %p)
+ ret 4 x double %t
+}
+define 4 x double @goo(4 x double %p)
+{
+ %t = call 4 x double @llvm.cos.v4f64(4 x double %p)
+ ret 4 x double %t
+}
+define 4 x double @moo(4 x double %p, 4 x double %q)
+{
+ %t = call 4 x double @llvm.pow.v4f64(4 x double %p, 4 x double %q)
+ ret 4 x double %t
+}
+define 4 x double @zoo(4 x double %p, i32 %q)
+{
+ %t = call 4 x double @llvm.powi.v4f64(4 x double %p, i32 %q)
+ ret 4 x double %t
+}
___
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[llvm-commits] RFC: internal label names
The attached patch changes the names of internal labels used by
codegen. In place of the function number, which is a number that
codegen itself assigns specifically for this purpose, it uses the
(mangled) name of the function, which is already sufficiently unique.
For example, what currently looks like this:
.LCPI1_3:
where 1 is the function number and 3 is the constant index would
look like this:
.LCPI3_foo:
Note that the constant index is now first, so the name can go last
to avoid problems with names containing underscores.
I saw this in another compiler and liked it. Does anyone here
dislike it?
Dan
--
Dan Gohman, Cray Inc.
Index: test/CodeGen/X86/2006-10-19-SwitchUnnecessaryBranching.ll
===
--- test/CodeGen/X86/2006-10-19-SwitchUnnecessaryBranching.ll (revision 42821)
+++ test/CodeGen/X86/2006-10-19-SwitchUnnecessaryBranching.ll (working copy)
@@ -1,5 +1,5 @@
; RUN: llvm-upgrade %s | llvm-as | llc -march=x86 | %prcontext je 1 | \
-; RUN: grep BB1_1:
+; RUN: grep BB1_main:
%str = internal constant [14 x sbyte] cHello world!\0A\00; [14
x sbyte]* [#uses=1]
%str = internal constant [13 x sbyte] cBlah world!\0A\00 ; [13
x sbyte]* [#uses=1]
Index: test/CodeGen/X86/2007-01-08-InstrSched.ll
===
--- test/CodeGen/X86/2007-01-08-InstrSched.ll (revision 42821)
+++ test/CodeGen/X86/2007-01-08-InstrSched.ll (working copy)
@@ -1,6 +1,6 @@
; PR1075
; RUN: llvm-as %s | llc -mtriple=x86_64-apple-darwin | \
-; RUN: %prcontext {mulss LCPI1_3} 1 | grep mulss | count 1
+; RUN: %prcontext {mulss LCPI3__foo} 1 | grep mulss | count 1
define float @foo(float %x) {
%tmp1 = mul float %x, 3.00e+00
Index: test/CodeGen/X86/fp_constant_op.llx
===
--- test/CodeGen/X86/fp_constant_op.llx (revision 42821)
+++ test/CodeGen/X86/fp_constant_op.llx (working copy)
@@ -3,32 +3,32 @@
; Test that the load of the constant is folded into the operation.
-double %test_add(double %P) {
+double %foo_add(double %P) {
%tmp.1 = add double %P, 0x405EC000
ret double %tmp.1
}
-double %test_mul(double %P) {
+double %foo_mul(double %P) {
%tmp.1 = mul double %P, 0x405EC000
ret double %tmp.1
}
-double %test_sub(double %P) {
+double %foo_sub(double %P) {
%tmp.1 = sub double %P, 0x405EC000
ret double %tmp.1
}
-double %test_subr(double %P) {
+double %foo_subr(double %P) {
%tmp.1 = sub double 0x405EC000, %P
ret double %tmp.1
}
-double %test_div(double %P) {
+double %foo_div(double %P) {
%tmp.1 = div double %P, 0x405EC000
ret double %tmp.1
}
-double %test_divr(double %P) {
+double %foo_divr(double %P) {
%tmp.1 = div double 0x405EC000, %P
ret double %tmp.1
}
Index: include/llvm/CodeGen/AsmPrinter.h
===
--- include/llvm/CodeGen/AsmPrinter.h (revision 42821)
+++ include/llvm/CodeGen/AsmPrinter.h (working copy)
@@ -36,13 +36,6 @@
class AsmPrinter : public MachineFunctionPass {
static char ID;
-/// FunctionNumber - This provides a unique ID for each function emitted in
-/// this translation unit. It is autoincremented by SetupMachineFunction,
-/// and can be accessed with getFunctionNumber() and
-/// IncrementFunctionNumber().
-///
-unsigned FunctionNumber;
-
protected:
// Necessary for external weak linkage support
std::setconst GlobalValue* ExtWeakSymbols;
@@ -160,15 +153,6 @@
/// is being processed from runOnMachineFunction.
void SetupMachineFunction(MachineFunction MF);
-/// getFunctionNumber - Return a unique ID for the current function.
-///
-unsigned getFunctionNumber() const { return FunctionNumber; }
-
-/// IncrementFunctionNumber - Increase Function Number. AsmPrinters should
-/// not normally call this, as the counter is automatically bumped by
-/// SetupMachineFunction.
-void IncrementFunctionNumber() { FunctionNumber++; }
-
/// EmitConstantPool - Print to the current output stream assembly
/// representations of the constants in the constant pool MCP. This is
/// used to print out constants which have been spilled to memory by
Index: lib/CodeGen/AsmPrinter.cpp
===
--- lib/CodeGen/AsmPrinter.cpp (revision 42821)
+++ lib/CodeGen/AsmPrinter.cpp (working copy)
@@ -35,7 +35,7 @@
char AsmPrinter::ID = 0;
AsmPrinter::AsmPrinter(std::ostream o, TargetMachine tm,
const TargetAsmInfo *T)
- : MachineFunctionPass((intptr_t)ID), FunctionNumber(0), O(o), TM(tm), TAI(T)
+ : MachineFunctionPass((intptr_t)ID), O(o), TM(tm), TAI(T)
{}
std::string
Re: [llvm-commits] RFC: internal label names
My only concern is it won't look as pleasant if the function name is long. Which happens with C++ mangled names all the time :( a potentially solution to this (which may be over complex :) is to have two options: 1. if the name is short, print it as you propose. 2. if the name is long, print it with a number and optionally with a subset of the name (last 10 chars?) This could be implemented by just adding a new ivar like CurrentFunctionName that holds this. I think that is over complex :). C++ mangled names are ok with me here, but if they're unpleasant for others that's fine. Dan -- Dan Gohman, Cray Inc. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r42784 - in /llvm/trunk/test/CodeGen/X86: extmul128.ll extmul64.ll
Author: djg
Date: Tue Oct 9 10:39:37 2007
New Revision: 42784
URL: http://llvm.org/viewvc/llvm-project?rev=42784view=rev
Log:
These two tests now require only two multiply instructions,
instead of four.
Added:
llvm/trunk/test/CodeGen/X86/extmul128.ll
llvm/trunk/test/CodeGen/X86/extmul64.ll
Added: llvm/trunk/test/CodeGen/X86/extmul128.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/extmul128.ll?rev=42784view=auto
==
--- llvm/trunk/test/CodeGen/X86/extmul128.ll (added)
+++ llvm/trunk/test/CodeGen/X86/extmul128.ll Tue Oct 9 10:39:37 2007
@@ -0,0 +1,14 @@
+; RUN: llvm-as %s | llc -march=x86-64 | grep mul | count 2
+
+define i128 @i64_sext_i128(i64 %a, i64 %b) {
+ %aa = sext i64 %a to i128
+ %bb = sext i64 %b to i128
+ %cc = mul i128 %aa, %bb
+ ret i128 %cc
+}
+define i128 @i64_zext_i128(i64 %a, i64 %b) {
+ %aa = zext i64 %a to i128
+ %bb = zext i64 %b to i128
+ %cc = mul i128 %aa, %bb
+ ret i128 %cc
+}
Added: llvm/trunk/test/CodeGen/X86/extmul64.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/extmul64.ll?rev=42784view=auto
==
--- llvm/trunk/test/CodeGen/X86/extmul64.ll (added)
+++ llvm/trunk/test/CodeGen/X86/extmul64.ll Tue Oct 9 10:39:37 2007
@@ -0,0 +1,14 @@
+; RUN: llvm-as %s | llc -march=x86 | grep mul | count 2
+
+define i64 @i32_sext_i64(i32 %a, i32 %b) {
+ %aa = sext i32 %a to i64
+ %bb = sext i32 %b to i64
+ %cc = mul i64 %aa, %bb
+ ret i64 %cc
+}
+define i64 @i32_zext_i64(i32 %a, i32 %b) {
+ %aa = zext i32 %a to i64
+ %bb = zext i32 %b to i64
+ %cc = mul i64 %aa, %bb
+ ret i64 %cc
+}
___
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[llvm-commits] [llvm] r42785 - /llvm/trunk/lib/Target/X86/README.txt
Author: djg
Date: Tue Oct 9 10:42:21 2007
New Revision: 42785
URL: http://llvm.org/viewvc/llvm-project?rev=42785view=rev
Log:
This is done.
Modified:
llvm/trunk/lib/Target/X86/README.txt
Modified: llvm/trunk/lib/Target/X86/README.txt
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/README.txt?rev=42785r1=42784r2=42785view=diff
==
--- llvm/trunk/lib/Target/X86/README.txt (original)
+++ llvm/trunk/lib/Target/X86/README.txt Tue Oct 9 10:42:21 2007
@@ -10,36 +10,6 @@
//===-===//
-Add a MUL2U and MUL2S nodes to represent a multiply that returns both the
-Hi and Lo parts (combination of MUL and MULH[SU] into one node). Add this to
-X86, make the dag combiner produce it when needed. This will eliminate one
-imul from the code generated for:
-
-long long test(long long X, long long Y) { return X*Y; }
-
-by using the EAX result from the mul. We should add a similar node for
-DIVREM.
-
-another case is:
-
-long long test(int X, int Y) { return (long long)X*Y; }
-
-... which should only be one imul instruction.
-
-or:
-
-unsigned long long int t2(unsigned int a, unsigned int b) {
- return (unsigned long long)a * b;
-}
-
-... which should be one mul instruction.
-
-
-This can be done with a custom expander, but it would be nice to move this to
-generic code.
-
-//===-===//
-
CodeGen/X86/lea-3.ll:test3 should be a single LEA, not a shift/move. The X86
backend knows how to three-addressify this shift, but it appears the register
allocator isn't even asking it to do so in this case. We should investigate
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[llvm-commits] [llvm] r42786 - /llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
Author: djg
Date: Tue Oct 9 10:44:37 2007
New Revision: 42786
URL: http://llvm.org/viewvc/llvm-project?rev=42786view=rev
Log:
Fix grammar in a comment.
Modified:
llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=42786r1=42785r2=42786view=diff
==
--- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Tue Oct 9 10:44:37 2007
@@ -1090,9 +1090,9 @@
SDOperand N0 = Node-getOperand(0);
SDOperand N1 = Node-getOperand(1);
- // There are several forms of IMUL just return the low part and don't
- // have fixed-register operands. If we don't need the high part, use
- // these instead. They can be selected with the generated ISel code.
+ // There are several forms of IMUL that just return the low part and
+ // don't have fixed-register operands. If we don't need the high part,
+ // use these instead. They can be selected with the generated ISel code.
if (NVT != MVT::i8
N.getValue(1).use_empty()) {
N = CurDAG-getNode(ISD::MUL, NVT, N0, N1);
___
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[llvm-commits] [llvm] r42787 - /llvm/trunk/lib/Target/X86/X86ISelLowering.h
Author: djg Date: Tue Oct 9 10:45:13 2007 New Revision: 42787 URL: http://llvm.org/viewvc/llvm-project?rev=42787view=rev Log: LowerIntegerDivOrRem no longer exists. Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=42787r1=42786r2=42787view=diff == --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Tue Oct 9 10:45:13 2007 @@ -416,7 +416,6 @@ SDOperand LowerGlobalTLSAddress(SDOperand Op, SelectionDAG DAG); SDOperand LowerExternalSymbol(SDOperand Op, SelectionDAG DAG); SDOperand LowerShift(SDOperand Op, SelectionDAG DAG); -SDOperand LowerIntegerDivOrRem(SDOperand Op, SelectionDAG DAG); SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG DAG); SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG DAG); SDOperand LowerFABS(SDOperand Op, SelectionDAG DAG); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r42788 - in /llvm/trunk: include/llvm/Support/CommandLine.h lib/Support/CommandLine.cpp
Author: djg
Date: Tue Oct 9 11:04:57 2007
New Revision: 42788
URL: http://llvm.org/viewvc/llvm-project?rev=42788view=rev
Log:
Pass argc by value, not by reference, since it isn't modified.
Modified:
llvm/trunk/include/llvm/Support/CommandLine.h
llvm/trunk/lib/Support/CommandLine.cpp
Modified: llvm/trunk/include/llvm/Support/CommandLine.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/CommandLine.h?rev=42788r1=42787r2=42788view=diff
==
--- llvm/trunk/include/llvm/Support/CommandLine.h (original)
+++ llvm/trunk/include/llvm/Support/CommandLine.h Tue Oct 9 11:04:57 2007
@@ -40,7 +40,7 @@
//===--===//
// ParseCommandLineOptions - Command line option processing entry point.
//
-void ParseCommandLineOptions(int argc, char **argv,
+void ParseCommandLineOptions(int argc, char **argv,
const char *Overview = 0);
//===--===//
Modified: llvm/trunk/lib/Support/CommandLine.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/CommandLine.cpp?rev=42788r1=42787r2=42788view=diff
==
--- llvm/trunk/lib/Support/CommandLine.cpp (original)
+++ llvm/trunk/lib/Support/CommandLine.cpp Tue Oct 9 11:04:57 2007
@@ -332,7 +332,7 @@
free (*i);
}
-void cl::ParseCommandLineOptions(int argc, char **argv,
+void cl::ParseCommandLineOptions(int argc, char **argv,
const char *Overview) {
// Process all registered options.
std::vectorOption* PositionalOpts;
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[llvm-commits] [llvm] r42805 - /llvm/trunk/include/llvm/Support/CommandLine.h
Author: djg
Date: Tue Oct 9 13:39:48 2007
New Revision: 42805
URL: http://llvm.org/viewvc/llvm-project?rev=42805view=rev
Log:
Remove an unnecessary friend declaration.
Modified:
llvm/trunk/include/llvm/Support/CommandLine.h
Modified: llvm/trunk/include/llvm/Support/CommandLine.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/CommandLine.h?rev=42805r1=42804r2=42805view=diff
==
--- llvm/trunk/include/llvm/Support/CommandLine.h (original)
+++ llvm/trunk/include/llvm/Support/CommandLine.h Tue Oct 9 13:39:48 2007
@@ -133,7 +133,6 @@
//
class alias;
class Option {
- friend void cl::ParseCommandLineOptions(int, char **, const char *);
friend class alias;
// handleOccurrences - Overriden by subclasses to handle the value passed
into
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[llvm-commits] [llvm] r42747 - in /llvm/trunk: include/llvm/Bitcode/Archive.h include/llvm/Bitcode/BitCodes.h include/llvm/Bitcode/BitstreamWriter.h include/llvm/Support/CommandLine.h include/llvm/Tar
Author: djg
Date: Mon Oct 8 10:08:41 2007
New Revision: 42747
URL: http://llvm.org/viewvc/llvm-project?rev=42747view=rev
Log:
Add explicit keywords.
Modified:
llvm/trunk/include/llvm/Bitcode/Archive.h
llvm/trunk/include/llvm/Bitcode/BitCodes.h
llvm/trunk/include/llvm/Bitcode/BitstreamWriter.h
llvm/trunk/include/llvm/Support/CommandLine.h
llvm/trunk/include/llvm/Target/SubtargetFeature.h
llvm/trunk/lib/VMCore/PassManager.cpp
Modified: llvm/trunk/include/llvm/Bitcode/Archive.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Bitcode/Archive.h?rev=42747r1=42746r2=42747view=diff
==
--- llvm/trunk/include/llvm/Bitcode/Archive.h (original)
+++ llvm/trunk/include/llvm/Bitcode/Archive.h Mon Oct 8 10:08:41 2007
@@ -198,7 +198,7 @@
private:
/// Used internally by the Archive class to construct an ArchiveMember.
/// The contents of the ArchiveMember are filled out by the Archive class.
-ArchiveMember(Archive *PAR);
+explicit ArchiveMember(Archive *PAR);
// So Archive can construct an ArchiveMember
friend class llvm::Archive;
@@ -461,7 +461,7 @@
protected:
/// @brief Construct an Archive for \p filename and optionally map it
/// into memory.
-Archive(const sys::Path filename);
+explicit Archive(const sys::Path filename);
/// @param data The symbol table data to be parsed
/// @param len The length of the symbol table data
Modified: llvm/trunk/include/llvm/Bitcode/BitCodes.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Bitcode/BitCodes.h?rev=42747r1=42746r2=42747view=diff
==
--- llvm/trunk/include/llvm/Bitcode/BitCodes.h (original)
+++ llvm/trunk/include/llvm/Bitcode/BitCodes.h Mon Oct 8 10:08:41 2007
@@ -91,8 +91,8 @@
Char6 = 4 // A 6-bit fixed field which maps to [a-zA-Z0-9._].
};
- BitCodeAbbrevOp(uint64_t V) : Val(V), IsLiteral(true) {}
- BitCodeAbbrevOp(Encoding E, uint64_t Data = 0)
+ explicit BitCodeAbbrevOp(uint64_t V) : Val(V), IsLiteral(true) {}
+ explicit BitCodeAbbrevOp(Encoding E, uint64_t Data = 0)
: Val(Data), IsLiteral(false), Enc(E) {}
bool isLiteral() const { return IsLiteral; }
Modified: llvm/trunk/include/llvm/Bitcode/BitstreamWriter.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Bitcode/BitstreamWriter.h?rev=42747r1=42746r2=42747view=diff
==
--- llvm/trunk/include/llvm/Bitcode/BitstreamWriter.h (original)
+++ llvm/trunk/include/llvm/Bitcode/BitstreamWriter.h Mon Oct 8 10:08:41 2007
@@ -59,7 +59,7 @@
std::vectorBlockInfo BlockInfoRecords;
public:
- BitstreamWriter(std::vectorunsigned char O)
+ explicit BitstreamWriter(std::vectorunsigned char O)
: Out(O), CurBit(0), CurValue(0), CurCodeSize(2) {}
~BitstreamWriter() {
Modified: llvm/trunk/include/llvm/Support/CommandLine.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/CommandLine.h?rev=42747r1=42746r2=42747view=diff
==
--- llvm/trunk/include/llvm/Support/CommandLine.h (original)
+++ llvm/trunk/include/llvm/Support/CommandLine.h Mon Oct 8 10:08:41 2007
@@ -838,7 +838,7 @@
// One option...
templateclass M0t
- opt(const M0t M0) : Option(Optional | NotHidden) {
+ explicit opt(const M0t M0) : Option(Optional | NotHidden) {
apply(M0, this);
done();
}
@@ -998,7 +998,7 @@
// One option...
templateclass M0t
- list(const M0t M0) : Option(ZeroOrMore | NotHidden) {
+ explicit list(const M0t M0) : Option(ZeroOrMore | NotHidden) {
apply(M0, this);
done();
}
@@ -1184,7 +1184,7 @@
// One option...
templateclass M0t
- bits(const M0t M0) : Option(ZeroOrMore | NotHidden) {
+ explicit bits(const M0t M0) : Option(ZeroOrMore | NotHidden) {
apply(M0, this);
done();
}
@@ -1277,7 +1277,7 @@
// One option...
templateclass M0t
- alias(const M0t M0) : Option(Optional | Hidden), AliasFor(0) {
+ explicit alias(const M0t M0) : Option(Optional | Hidden), AliasFor(0) {
apply(M0, this);
done();
}
@@ -1306,7 +1306,7 @@
// aliasfor - Modifier to set the option an alias aliases.
struct aliasopt {
Option Opt;
- aliasopt(Option O) : Opt(O) {}
+ explicit aliasopt(Option O) : Opt(O) {}
void apply(alias A) const { A.setAliasFor(Opt); }
};
Modified: llvm/trunk/include/llvm/Target/SubtargetFeature.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/SubtargetFeature.h?rev=42747r1=42746r2=42747view=diff
==
--- llvm/trunk/include/llvm/Target/SubtargetFeature.h (original)
+++ llvm/trunk/include/llvm/Target/SubtargetFeature.h Mon Oct 8 10:08:41 2007
@@
[llvm-commits] [llvm] r42748 - /llvm/trunk/include/llvm/Support/CommandLine.h
Author: djg Date: Mon Oct 8 10:10:04 2007 New Revision: 42748 URL: http://llvm.org/viewvc/llvm-project?rev=42748view=rev Log: Fix grammar in a comment. Modified: llvm/trunk/include/llvm/Support/CommandLine.h Modified: llvm/trunk/include/llvm/Support/CommandLine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/CommandLine.h?rev=42748r1=42747r2=42748view=diff == --- llvm/trunk/include/llvm/Support/CommandLine.h (original) +++ llvm/trunk/include/llvm/Support/CommandLine.h Mon Oct 8 10:10:04 2007 @@ -53,7 +53,7 @@ ///===-===// /// SetVersionPrinter - Override the default (LLVM specific) version printer /// used to print out the version when --version is given -/// on the command line. This gives other systems using the +/// on the command line. This allows other systems using the /// CommandLine utilities to print their own version string. void SetVersionPrinter(void (*func)()); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r42749 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Author: djg
Date: Mon Oct 8 10:12:17 2007
New Revision: 42749
URL: http://llvm.org/viewvc/llvm-project?rev=42749view=rev
Log:
In -debug mode, dump SelectionDAGs both before and after the
optimization passes.
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=42749r1=42748r2=42749view=diff
==
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Mon Oct 8
10:12:17 2007
@@ -4624,10 +4624,13 @@
}
void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG DAG) {
+ DOUT Lowered selection DAG:\n;
+ DEBUG(DAG.dump());
+
// Run the DAG combiner in pre-legalize mode.
DAG.Combine(false, *AA);
- DOUT Lowered selection DAG:\n;
+ DOUT Optimized lowered selection DAG:\n;
DEBUG(DAG.dump());
// Second step, hack on the DAG until it only uses operations and types that
@@ -4640,6 +4643,9 @@
// Run the DAG combiner in post-legalize mode.
DAG.Combine(true, *AA);
+ DOUT Optimized legalized selection DAG:\n;
+ DEBUG(DAG.dump());
+
if (ViewISelDAGs) DAG.viewGraph();
// Third, instruction select all of the operations to machine code, adding
the
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[llvm-commits] [llvm] r42750 - /llvm/trunk/lib/Linker/LinkModules.cpp
Author: djg Date: Mon Oct 8 10:13:30 2007 New Revision: 42750 URL: http://llvm.org/viewvc/llvm-project?rev=42750view=rev Log: Use correct parentheses with the ' ...' idiom in an assert. Modified: llvm/trunk/lib/Linker/LinkModules.cpp Modified: llvm/trunk/lib/Linker/LinkModules.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Linker/LinkModules.cpp?rev=42750r1=42749r2=42750view=diff == --- llvm/trunk/lib/Linker/LinkModules.cpp (original) +++ llvm/trunk/lib/Linker/LinkModules.cpp Mon Oct 8 10:13:30 2007 @@ -469,8 +469,8 @@ if (DGV DGV-hasInternalLinkage()) DGV = 0; -assert(SGV-hasInitializer() || SGV-hasExternalWeakLinkage() || - SGV-hasExternalLinkage() || SGV-hasDLLImportLinkage() +assert((SGV-hasInitializer() || SGV-hasExternalWeakLinkage() || +SGV-hasExternalLinkage() || SGV-hasDLLImportLinkage()) Global must either be external or have an initializer!); GlobalValue::LinkageTypes NewLinkage = GlobalValue::InternalLinkage; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r42752 - in /llvm/trunk: lib/Support/ tools/bugpoint/ tools/llc/ tools/lli/ tools/llvm-ar/ tools/llvm-as/ tools/llvm-bcanalyzer/ tools/llvm-db/ tools/llvm-dis/ tools/llvm-extract
Author: djg
Date: Mon Oct 8 10:45:12 2007
New Revision: 42752
URL: http://llvm.org/viewvc/llvm-project?rev=42752view=rev
Log:
Move the space in overview output for commands out of each of the
commands and into the common code.
Modified:
llvm/trunk/lib/Support/CommandLine.cpp
llvm/trunk/tools/bugpoint/bugpoint.cpp
llvm/trunk/tools/llc/llc.cpp
llvm/trunk/tools/lli/lli.cpp
llvm/trunk/tools/llvm-ar/llvm-ar.cpp
llvm/trunk/tools/llvm-as/llvm-as.cpp
llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp
llvm/trunk/tools/llvm-db/llvm-db.cpp
llvm/trunk/tools/llvm-dis/llvm-dis.cpp
llvm/trunk/tools/llvm-extract/llvm-extract.cpp
llvm/trunk/tools/llvm-ld/llvm-ld.cpp
llvm/trunk/tools/llvm-link/llvm-link.cpp
llvm/trunk/tools/llvm-nm/llvm-nm.cpp
llvm/trunk/tools/llvm-prof/llvm-prof.cpp
llvm/trunk/tools/llvm-ranlib/llvm-ranlib.cpp
llvm/trunk/tools/llvm-upgrade/llvm-upgrade.cpp
llvm/trunk/tools/llvm2cpp/llvm2cpp.cpp
llvm/trunk/tools/llvmc/llvmc.cpp
llvm/trunk/tools/opt/opt.cpp
Modified: llvm/trunk/lib/Support/CommandLine.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/CommandLine.cpp?rev=42752r1=42751r2=42752view=diff
==
--- llvm/trunk/lib/Support/CommandLine.cpp (original)
+++ llvm/trunk/lib/Support/CommandLine.cpp Mon Oct 8 10:45:12 2007
@@ -951,7 +951,7 @@
}
if (ProgramOverview)
- cout OVERVIEW: ProgramOverview \n;
+ cout OVERVIEW: ProgramOverview \n;
cout USAGE: ProgramName [options];
Modified: llvm/trunk/tools/bugpoint/bugpoint.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/bugpoint/bugpoint.cpp?rev=42752r1=42751r2=42752view=diff
==
--- llvm/trunk/tools/bugpoint/bugpoint.cpp (original)
+++ llvm/trunk/tools/bugpoint/bugpoint.cpp Mon Oct 8 10:45:12 2007
@@ -66,7 +66,7 @@
int main(int argc, char **argv) {
llvm_shutdown_obj X; // Call llvm_shutdown() on exit.
cl::ParseCommandLineOptions(argc, argv,
- LLVM automatic testcase reducer. See\nhttp://;
+ LLVM automatic testcase reducer. See\nhttp://;
llvm.org/docs/CommandGuide/bugpoint.html
for more information.\n);
sys::PrintStackTraceOnErrorSignal();
Modified: llvm/trunk/tools/llc/llc.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llc/llc.cpp?rev=42752r1=42751r2=42752view=diff
==
--- llvm/trunk/tools/llc/llc.cpp (original)
+++ llvm/trunk/tools/llc/llc.cpp Mon Oct 8 10:45:12 2007
@@ -172,7 +172,7 @@
//
int main(int argc, char **argv) {
llvm_shutdown_obj X; // Call llvm_shutdown() on exit.
- cl::ParseCommandLineOptions(argc, argv, llvm system compiler\n);
+ cl::ParseCommandLineOptions(argc, argv, llvm system compiler\n);
sys::PrintStackTraceOnErrorSignal();
// Load the module to be compiled...
Modified: llvm/trunk/tools/lli/lli.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lli/lli.cpp?rev=42752r1=42751r2=42752view=diff
==
--- llvm/trunk/tools/lli/lli.cpp (original)
+++ llvm/trunk/tools/lli/lli.cpp Mon Oct 8 10:45:12 2007
@@ -67,7 +67,7 @@
int main(int argc, char **argv, char * const *envp) {
atexit(do_shutdown); // Call llvm_shutdown() on exit.
cl::ParseCommandLineOptions(argc, argv,
- llvm interpreter dynamic compiler\n);
+ llvm interpreter dynamic compiler\n);
sys::PrintStackTraceOnErrorSignal();
// If the user doesn't want core files, disable them.
Modified: llvm/trunk/tools/llvm-ar/llvm-ar.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-ar/llvm-ar.cpp?rev=42752r1=42751r2=42752view=diff
==
--- llvm/trunk/tools/llvm-ar/llvm-ar.cpp (original)
+++ llvm/trunk/tools/llvm-ar/llvm-ar.cpp Mon Oct 8 10:45:12 2007
@@ -690,7 +690,7 @@
// Have the command line options parsed and handle things
// like --help and --version.
cl::ParseCommandLineOptions(argc, argv,
- LLVM Archiver (llvm-ar)\n\n
+LLVM Archiver (llvm-ar)\n\n
This program archives bitcode files into single libraries\n
);
Modified: llvm/trunk/tools/llvm-as/llvm-as.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-as/llvm-as.cpp?rev=42752r1=42751r2=42752view=diff
==
--- llvm/trunk/tools/llvm-as/llvm-as.cpp (original)
+++ llvm/trunk/tools/llvm-as/llvm-as.cpp Mon Oct 8 10:45:12 2007
@@ -48,7 +48,7 @@
int main(int argc, char **argv) {
llvm_shutdown_obj X; // Call llvm_shutdown() on
[llvm-commits] [llvm] r42753 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAG.h lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Author: djg
Date: Mon Oct 8 10:49:58 2007
New Revision: 42753
URL: http://llvm.org/viewvc/llvm-project?rev=42753view=rev
Log:
Add convenience overloads of SelectionDAG::getNode that take a SDVTList
and individual SDOperand operands.
Modified:
llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=42753r1=42752r2=42753view=diff
==
--- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Mon Oct 8 10:49:58 2007
@@ -287,6 +287,17 @@
const SDOperand *Ops, unsigned NumOps);
SDOperand getNode(unsigned Opcode, const MVT::ValueType *VTs, unsigned
NumVTs,
const SDOperand *Ops, unsigned NumOps);
+ SDOperand getNode(unsigned Opcode, SDVTList VTs);
+ SDOperand getNode(unsigned Opcode, SDVTList VTs, SDOperand N);
+ SDOperand getNode(unsigned Opcode, SDVTList VTs,
+SDOperand N1, SDOperand N2);
+ SDOperand getNode(unsigned Opcode, SDVTList VTs,
+SDOperand N1, SDOperand N2, SDOperand N3);
+ SDOperand getNode(unsigned Opcode, SDVTList VTs,
+SDOperand N1, SDOperand N2, SDOperand N3, SDOperand N4);
+ SDOperand getNode(unsigned Opcode, SDVTList VTs,
+SDOperand N1, SDOperand N2, SDOperand N3, SDOperand N4,
+SDOperand N5);
SDOperand getNode(unsigned Opcode, SDVTList VTs,
const SDOperand *Ops, unsigned NumOps);
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=42753r1=42752r2=42753view=diff
==
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Mon Oct 8 10:49:58
2007
@@ -2595,6 +2595,42 @@
return SDOperand(N, 0);
}
+SDOperand SelectionDAG::getNode(unsigned Opcode, SDVTList VTList) {
+ return getNode(Opcode, VTList, 0, 0);
+}
+
+SDOperand SelectionDAG::getNode(unsigned Opcode, SDVTList VTList,
+SDOperand N1) {
+ SDOperand Ops[] = { N1 };
+ return getNode(Opcode, VTList, Ops, 1);
+}
+
+SDOperand SelectionDAG::getNode(unsigned Opcode, SDVTList VTList,
+SDOperand N1, SDOperand N2) {
+ SDOperand Ops[] = { N1, N2 };
+ return getNode(Opcode, VTList, Ops, 2);
+}
+
+SDOperand SelectionDAG::getNode(unsigned Opcode, SDVTList VTList,
+SDOperand N1, SDOperand N2, SDOperand N3) {
+ SDOperand Ops[] = { N1, N2, N3 };
+ return getNode(Opcode, VTList, Ops, 3);
+}
+
+SDOperand SelectionDAG::getNode(unsigned Opcode, SDVTList VTList,
+SDOperand N1, SDOperand N2, SDOperand N3,
+SDOperand N4) {
+ SDOperand Ops[] = { N1, N2, N3, N4 };
+ return getNode(Opcode, VTList, Ops, 4);
+}
+
+SDOperand SelectionDAG::getNode(unsigned Opcode, SDVTList VTList,
+SDOperand N1, SDOperand N2, SDOperand N3,
+SDOperand N4, SDOperand N5) {
+ SDOperand Ops[] = { N1, N2, N3, N4, N5 };
+ return getNode(Opcode, VTList, Ops, 5);
+}
+
SDVTList SelectionDAG::getVTList(MVT::ValueType VT) {
if (!MVT::isExtendedVT(VT))
return makeVTList(SDNode::getValueTypeList(VT), 1);
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[llvm-commits] [llvm] r42755 - /llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
Author: djg Date: Mon Oct 8 12:28:24 2007 New Revision: 42755 URL: http://llvm.org/viewvc/llvm-project?rev=42755view=rev Log: When we start enabling SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM in target-indepenent lowering, don't use them on PowerPC. Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=42755r1=42754r2=42755view=diff == --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Mon Oct 8 12:28:24 2007 @@ -87,6 +87,16 @@ setOperationAction(ISD::UREM, MVT::i32, Expand); setOperationAction(ISD::SREM, MVT::i64, Expand); setOperationAction(ISD::UREM, MVT::i64, Expand); + + // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM. + setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); + setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); + setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); + setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); + setOperationAction(ISD::UDIVREM, MVT::i32, Expand); + setOperationAction(ISD::SDIVREM, MVT::i32, Expand); + setOperationAction(ISD::UDIVREM, MVT::i64, Expand); + setOperationAction(ISD::SDIVREM, MVT::i64, Expand); // We don't support sin/cos/sqrt/fmod setOperationAction(ISD::FSIN , MVT::f64, Expand); @@ -265,6 +275,10 @@ setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand); setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand); setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand); + setOperationAction(ISD::UMUL_LOHI, (MVT::ValueType)VT, Expand); + setOperationAction(ISD::SMUL_LOHI, (MVT::ValueType)VT, Expand); + setOperationAction(ISD::UDIVREM, (MVT::ValueType)VT, Expand); + setOperationAction(ISD::SDIVREM, (MVT::ValueType)VT, Expand); setOperationAction(ISD::SCALAR_TO_VECTOR, (MVT::ValueType)VT, Expand); } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r42759 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Author: djg
Date: Mon Oct 8 12:57:15 2007
New Revision: 42759
URL: http://llvm.org/viewvc/llvm-project?rev=42759view=rev
Log:
DAGCombiner support for UDIVREM/SDIVREM and UMUL_LOHI/SMUL_LOHI.
Check if one of the two results unneeded so see if a simpler operator
could bs used. Also check to see if each of the two computations could be
simplified if they were split into separate operators. Factor out the code
that calls visit() so that it can be used for this purpose.
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=42759r1=42758r2=42759view=diff
==
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Oct 8 12:57:15 2007
@@ -101,6 +101,10 @@
WorkList.end());
}
+/// visit - call the node-specific routine that knows how to fold each
+/// particular type of node.
+SDOperand visit(SDNode *N);
+
public:
/// AddToWorkList - Add to the work list making sure it's instance is at
the
/// the back (next to be processed.)
@@ -201,9 +205,10 @@
bool CombineToPostIndexedLoadStore(SDNode *N);
-/// visit - call the node-specific routine that knows how to fold each
-/// particular type of node.
-SDOperand visit(SDNode *N);
+/// combine - call the node-specific routine that knows how to fold each
+/// particular type of node. If that doesn't do anything, try the
+/// target-specific DAG combines.
+SDOperand combine(SDNode *N);
// Visitation implementation - Implement dag node combining for different
// node types. The semantics are as follows:
@@ -224,6 +229,10 @@
SDOperand visitUREM(SDNode *N);
SDOperand visitMULHU(SDNode *N);
SDOperand visitMULHS(SDNode *N);
+SDOperand visitSMUL_LOHI(SDNode *N);
+SDOperand visitUMUL_LOHI(SDNode *N);
+SDOperand visitSDIVREM(SDNode *N);
+SDOperand visitUDIVREM(SDNode *N);
SDOperand visitAND(SDNode *N);
SDOperand visitOR(SDNode *N);
SDOperand visitXOR(SDNode *N);
@@ -279,6 +288,7 @@
bool NotExtCompare = false);
SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
ISD::CondCode Cond, bool foldBooleans = true);
+bool SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, unsigned HiOp);
SDOperand ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT::ValueType);
SDOperand BuildSDIV(SDNode *N);
SDOperand BuildUDIV(SDNode *N);
@@ -555,10 +565,6 @@
// done. Set it to null to avoid confusion.
DAG.setRoot(SDOperand());
- /// DagCombineInfo - Expose the DAG combiner to the target combiner impls.
- TargetLowering::DAGCombinerInfo
-DagCombineInfo(DAG, !RunningAfterLegalize, false, this);
-
// while the worklist isn't empty, inspect the node on the end of it and
// try and combine it.
while (!WorkList.empty()) {
@@ -576,16 +582,7 @@
continue;
}
-SDOperand RV = visit(N);
-
-// If nothing happened, try a target-specific DAG combine.
-if (RV.Val == 0) {
- assert(N-getOpcode() != ISD::DELETED_NODE
- Node was deleted but visit returned NULL!);
- if (N-getOpcode() = ISD::BUILTIN_OP_END ||
- TLI.hasTargetDAGCombine((ISD::NodeType)N-getOpcode()))
-RV = TLI.PerformDAGCombine(N, DagCombineInfo);
-}
+SDOperand RV = combine(N);
if (RV.Val) {
++NodesCombined;
@@ -645,6 +642,10 @@
case ISD::UREM: return visitUREM(N);
case ISD::MULHU: return visitMULHU(N);
case ISD::MULHS: return visitMULHS(N);
+ case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
+ case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
+ case ISD::SDIVREM:return visitSDIVREM(N);
+ case ISD::UDIVREM:return visitUDIVREM(N);
case ISD::AND:return visitAND(N);
case ISD::OR: return visitOR(N);
case ISD::XOR:return visitXOR(N);
@@ -691,6 +692,29 @@
return SDOperand();
}
+SDOperand DAGCombiner::combine(SDNode *N) {
+
+ SDOperand RV = visit(N);
+
+ // If nothing happened, try a target-specific DAG combine.
+ if (RV.Val == 0) {
+assert(N-getOpcode() != ISD::DELETED_NODE
+ Node was deleted but visit returned NULL!);
+
+if (N-getOpcode() = ISD::BUILTIN_OP_END ||
+TLI.hasTargetDAGCombine((ISD::NodeType)N-getOpcode())) {
+
+ // Expose the DAG combiner to the target combiner impls.
+ TargetLowering::DAGCombinerInfo
+DagCombineInfo(DAG, !AfterLegalize, false, this);
+
+ RV = TLI.PerformDAGCombine(N, DagCombineInfo);
+}
+ }
+
+ return RV;
+}
+
///
[llvm-commits] [llvm] r42762 - in /llvm/trunk/lib: CodeGen/SelectionDAG/LegalizeDAG.cpp CodeGen/SelectionDAG/TargetLowering.cpp Target/ARM/ARMISelDAGToDAG.cpp Target/ARM/ARMISelLowering.cpp Target/ARM
Author: djg
Date: Mon Oct 8 13:33:35 2007
New Revision: 42762
URL: http://llvm.org/viewvc/llvm-project?rev=42762view=rev
Log:
Migrate X86 and ARM from using X86ISD::{,I}DIV and ARMISD::MULHILO{U,S} to
use ISD::{S,U}DIVREM and ISD::{S,U}MUL_HIO. Move the lowering code
associated with these operators into target-independent in LegalizeDAG.cpp
and TargetLowering.cpp.
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
llvm/trunk/lib/Target/ARM/ARMISelLowering.h
llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
llvm/trunk/lib/Target/X86/X86ISelLowering.h
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=42762r1=42761r2=42762view=diff
==
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Oct 8 13:33:35 2007
@@ -2577,6 +2577,55 @@
if (Tmp1.Val) Result = Tmp1;
break;
case TargetLowering::Expand: {
+ MVT::ValueType VT = Op.getValueType();
+
+ // See if multiply or divide can be lowered using two-result operations.
+ SDVTList VTs = DAG.getVTList(VT, VT);
+ if (Node-getOpcode() == ISD::MUL) {
+// We just need the low half of the multiply; try both the signed
+// and unsigned forms. If the target supports both SMUL_LOHI and
+// UMUL_LOHI, form a preference by checking which forms of plain
+// MULH it supports.
+bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT);
+bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT);
+bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT);
+bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT);
+unsigned OpToUse = 0;
+if (HasSMUL_LOHI !HasMULHS) {
+ OpToUse = ISD::SMUL_LOHI;
+} else if (HasUMUL_LOHI !HasMULHU) {
+ OpToUse = ISD::UMUL_LOHI;
+} else if (HasSMUL_LOHI) {
+ OpToUse = ISD::SMUL_LOHI;
+} else if (HasUMUL_LOHI) {
+ OpToUse = ISD::UMUL_LOHI;
+}
+if (OpToUse) {
+ Result = SDOperand(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).Val, 0);
+ break;
+}
+ }
+ if (Node-getOpcode() == ISD::MULHS
+ TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) {
+Result = SDOperand(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).Val,
1);
+break;
+ }
+ if (Node-getOpcode() == ISD::MULHU
+ TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) {
+Result = SDOperand(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).Val,
1);
+break;
+ }
+ if (Node-getOpcode() == ISD::SDIV
+ TLI.isOperationLegal(ISD::SDIVREM, VT)) {
+Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 0);
+break;
+ }
+ if (Node-getOpcode() == ISD::UDIV
+ TLI.isOperationLegal(ISD::UDIVREM, VT)) {
+Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 0);
+break;
+ }
+
if (Node-getValueType(0) == MVT::i32) {
switch (Node-getOpcode()) {
default: assert(0 Do not know how to expand this integer BinOp!);
@@ -2638,6 +2687,10 @@
// they shouldn't be here if they aren't legal.
assert(TLI.isOperationLegal(Node-getValueType(0), Node-getValueType(0))
This must be legal!);
+
+Tmp1 = LegalizeOp(Node-getOperand(0)); // LHS
+Tmp2 = LegalizeOp(Node-getOperand(1)); // RHS
+Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
break;
case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
@@ -2764,19 +2817,33 @@
if (Tmp1.Val) Result = Tmp1;
}
break;
-case TargetLowering::Expand:
+case TargetLowering::Expand: {
unsigned DivOpc= (Node-getOpcode() == ISD::UREM) ? ISD::UDIV :
ISD::SDIV;
bool isSigned = DivOpc == ISD::SDIV;
- if (MVT::isInteger(Node-getValueType(0))) {
-if (TLI.getOperationAction(DivOpc, Node-getValueType(0)) ==
+ MVT::ValueType VT = Node-getValueType(0);
+
+ // See if remainder can be lowered using two-result operations.
+ SDVTList VTs = DAG.getVTList(VT, VT);
+ if (Node-getOpcode() == ISD::SREM
+ TLI.isOperationLegal(ISD::SDIVREM, VT)) {
+Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 1);
+break;
+ }
+ if (Node-getOpcode() == ISD::UREM
+ TLI.isOperationLegal(ISD::UDIVREM, VT)) {
+Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 1);
+break;
+ }
+
+ if (MVT::isInteger(VT)) {
+if
[llvm-commits] [llvm] r42765 - in /llvm/trunk/test/CodeGen/X86: mul128.ll mul64.ll
Author: djg
Date: Mon Oct 8 15:48:12 2007
New Revision: 42765
URL: http://llvm.org/viewvc/llvm-project?rev=42765view=rev
Log:
These two tests now require only three multiply instructions,
instead of four.
Added:
llvm/trunk/test/CodeGen/X86/mul128.ll
llvm/trunk/test/CodeGen/X86/mul64.ll
Added: llvm/trunk/test/CodeGen/X86/mul128.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/mul128.ll?rev=42765view=auto
==
--- llvm/trunk/test/CodeGen/X86/mul128.ll (added)
+++ llvm/trunk/test/CodeGen/X86/mul128.ll Mon Oct 8 15:48:12 2007
@@ -0,0 +1,6 @@
+; RUN: llvm-as %s | llc -march=x86-64 | grep mul | count 3
+
+define i128 @foo(i128 %t, i128 %u) {
+ %k = mul i128 %t, %u
+ ret i128 %k
+}
Added: llvm/trunk/test/CodeGen/X86/mul64.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/mul64.ll?rev=42765view=auto
==
--- llvm/trunk/test/CodeGen/X86/mul64.ll (added)
+++ llvm/trunk/test/CodeGen/X86/mul64.ll Mon Oct 8 15:48:12 2007
@@ -0,0 +1,6 @@
+; RUN: llvm-as %s | llc -march=x86 | grep mul | count 3
+
+define i64 @foo(i64 %t, i64 %u) {
+ %k = mul i64 %t, %u
+ ret i64 %k
+}
___
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[llvm-commits] [llvm] r42768 - /llvm/trunk/include/llvm/Intrinsics.td
Author: djg Date: Mon Oct 8 16:15:07 2007 New Revision: 42768 URL: http://llvm.org/viewvc/llvm-project?rev=42768view=rev Log: Mark the prefetch intrinsic as IntrWriteArgMem, instead of the default of IntrWriteMem, to at least indicate that it doesn't capture the argument pointer. Modified: llvm/trunk/include/llvm/Intrinsics.td Modified: llvm/trunk/include/llvm/Intrinsics.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Intrinsics.td?rev=42768r1=42767r2=42768view=diff == --- llvm/trunk/include/llvm/Intrinsics.td (original) +++ llvm/trunk/include/llvm/Intrinsics.td Mon Oct 8 16:15:07 2007 @@ -153,8 +153,12 @@ GCCBuiltin__builtin_stack_save; def int_stackrestore : Intrinsic[llvm_void_ty, llvm_ptr_ty], GCCBuiltin__builtin_stack_restore; +// IntrWriteArgMem is more pessimistic than strictly necessary for prefetch, +// however it does conveniently prevent the prefetch from being reordered +// with respect to nearby accesses to the same memory. def int_prefetch : Intrinsic[llvm_void_ty, llvm_ptr_ty, - llvm_i32_ty, llvm_i32_ty]; + llvm_i32_ty, llvm_i32_ty], + [IntrWriteArgMem]; def int_pcmarker : Intrinsic[llvm_void_ty, llvm_i32_ty]; def int_readcyclecounter : Intrinsic[llvm_i64_ty]; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r42769 - /llvm/trunk/lib/CodeGen/AsmPrinter.cpp
Author: djg
Date: Mon Oct 8 16:27:12 2007
New Revision: 42769
URL: http://llvm.org/viewvc/llvm-project?rev=42769view=rev
Log:
Call getFunctionNumber() instead of referencing FunctionNumber directly,
for consistency.
Modified:
llvm/trunk/lib/CodeGen/AsmPrinter.cpp
Modified: llvm/trunk/lib/CodeGen/AsmPrinter.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter.cpp?rev=42769r1=42768r2=42769view=diff
==
--- llvm/trunk/lib/CodeGen/AsmPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter.cpp Mon Oct 8 16:27:12 2007
@@ -1209,7 +1209,7 @@
void AsmPrinter::printBasicBlockLabel(const MachineBasicBlock *MBB,
bool printColon,
bool printComment) const {
- O TAI-getPrivateGlobalPrefix() BB FunctionNumber _
+ O TAI-getPrivateGlobalPrefix() BB getFunctionNumber() _
MBB-getNumber();
if (printColon)
O ':';
___
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[llvm-commits] [llvm] r42632 - /llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
Author: djg Date: Fri Oct 5 09:07:56 2007 New Revision: 42632 URL: http://llvm.org/viewvc/llvm-project?rev=42632view=rev Log: Define target-indepenent SDNode types for multiply and divide that produce two results. Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=42632r1=42631r2=42632view=diff == --- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Fri Oct 5 09:07:56 2007 @@ -233,6 +233,15 @@ // Simple integer binary arithmetic operators. ADD, SUB, MUL, SDIV, UDIV, SREM, UREM, + +// SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing +// a signed/unsigned value of type i[2*n], and return the full value as +// two results, each of type iN. +SMUL_LOHI, UMUL_LOHI, + +// SDIVREM/UDIVREM - Divide two integers and produce both a quotient and +// remainder result. +SDIVREM, UDIVREM, // CARRY_FALSE - This node is used when folding other nodes, // like ADDC/SUBC, which indicate the carry result is always false. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r42633 - /llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
Author: djg Date: Fri Oct 5 09:09:33 2007 New Revision: 42633 URL: http://llvm.org/viewvc/llvm-project?rev=42633view=rev Log: SMUL_LOHI and UMUL_LOHI are commutative. Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=42633r1=42632r2=42633view=diff == --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Fri Oct 5 09:09:33 2007 @@ -457,6 +457,8 @@ case ISD::MUL: case ISD::MULHU: case ISD::MULHS: +case ISD::SMUL_LOHI: +case ISD::UMUL_LOHI: case ISD::FADD: case ISD::FMUL: case ISD::AND: ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r42634 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Author: djg Date: Fri Oct 5 09:11:04 2007 New Revision: 42634 URL: http://llvm.org/viewvc/llvm-project?rev=42634view=rev Log: Provide names for MUL_LOHI and DIVREM operators. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=42634r1=42633r2=42634view=diff == --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Fri Oct 5 09:11:04 2007 @@ -3571,6 +3571,10 @@ case ISD::UDIV: return udiv; case ISD::SREM: return srem; case ISD::UREM: return urem; + case ISD::SMUL_LOHI: return smul_lohi; + case ISD::UMUL_LOHI: return umul_lohi; + case ISD::SDIVREM:return sdivrem; + case ISD::UDIVREM:return divrem; case ISD::AND:return and; case ISD::OR: return or; case ISD::XOR:return xor; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r42635 - /llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
Author: djg
Date: Fri Oct 5 09:11:58 2007
New Revision: 42635
URL: http://llvm.org/viewvc/llvm-project?rev=42635view=rev
Log:
Fix a typo in a comment.
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=42635r1=42634r2=42635view=diff
==
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Fri Oct 5
09:11:58 2007
@@ -1301,7 +1301,7 @@
I != E; ++I) {
if (I-isCtrl) continue;
SUnit *SuccSU = I-Dep;
- // Don't constraint nodes with implicit defs. It can create cycles
+ // Don't constrain nodes with implicit defs. It can create cycles
// plus it may increase register pressures.
if (SuccSU == SU || SuccSU-hasPhysRegDefs)
continue;
___
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[llvm-commits] [llvm] r42636 - /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Author: djg
Date: Fri Oct 5 09:17:22 2007
New Revision: 42636
URL: http://llvm.org/viewvc/llvm-project?rev=42636view=rev
Log:
Legalize support for MUL_LOHI and DIVREM.
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=42636r1=42635r2=42636view=diff
==
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Oct 5 09:17:22 2007
@@ -2630,6 +2630,16 @@
}
break;
+ case ISD::SMUL_LOHI:
+ case ISD::UMUL_LOHI:
+ case ISD::SDIVREM:
+ case ISD::UDIVREM:
+// These nodes will only be produced by target-specific lowering, so
+// they shouldn't be here if they aren't legal.
+assert(TLI.isOperationLegal(Node-getValueType(0), Node-getValueType(0))
+ This must be legal!);
+break;
+
case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
Tmp1 = LegalizeOp(Node-getOperand(0)); // LHS
switch (getTypeAction(Node-getOperand(1).getValueType())) {
___
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[llvm-commits] [llvm] r42637 - /llvm/trunk/lib/Target/X86/X86ATTAsmPrinter.cpp
Author: djg
Date: Fri Oct 5 10:54:58 2007
New Revision: 42637
URL: http://llvm.org/viewvc/llvm-project?rev=42637view=rev
Log:
Change a space to a tab in the assembly output of a .globl directive
for consistency.
Modified:
llvm/trunk/lib/Target/X86/X86ATTAsmPrinter.cpp
Modified: llvm/trunk/lib/Target/X86/X86ATTAsmPrinter.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ATTAsmPrinter.cpp?rev=42637r1=42636r2=42637view=diff
==
--- llvm/trunk/lib/Target/X86/X86ATTAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ATTAsmPrinter.cpp Fri Oct 5 10:54:58 2007
@@ -126,7 +126,7 @@
O \t.weak_definition\t CurrentFnName \n;
} else if (Subtarget-isTargetCygMing()) {
EmitAlignment(4, F); // FIXME: This should be parameterized
somewhere.
- O \t.globl CurrentFnName \n;
+ O \t.globl\t CurrentFnName \n;
O \t.linkonce discard\n;
} else {
EmitAlignment(4, F); // FIXME: This should be parameterized
somewhere.
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[llvm-commits] [llvm] r42638 - /llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp
Author: djg
Date: Fri Oct 5 10:58:41 2007
New Revision: 42638
URL: http://llvm.org/viewvc/llvm-project?rev=42638view=rev
Log:
Change a few more spaces to tabs in assembly output.
Modified:
llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp
Modified: llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp?rev=42638r1=42637r2=42638view=diff
==
--- llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp Fri Oct 5 10:58:41 2007
@@ -213,7 +213,7 @@
case GlobalValue::LinkOnceLinkage:
case GlobalValue::WeakLinkage:
if (Subtarget-isTargetDarwin()) {
-O \t.globl name \n
+O \t.globl\t name \n
\t.weak_definition name \n;
SwitchToDataSection(.section __DATA,__const_coal,coalesced, I);
} else if (Subtarget-isTargetCygMing()) {
@@ -221,7 +221,7 @@
name +
,\aw\);
SwitchToDataSection(SectionName.c_str(), I);
-O \t.globl name \n
+O \t.globl\t name \n
\t.linkonce same_size\n;
} else {
std::string SectionName(\t.section\t.llvm.linkonce.d. +
@@ -239,7 +239,7 @@
// their name or something. For now, just emit them as external.
case GlobalValue::ExternalLinkage:
// If external or appending, declare as a global symbol
- O \t.globl name \n;
+ O \t.globl\t name \n;
// FALL THROUGH
case GlobalValue::InternalLinkage: {
if (I-isConstant()) {
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[llvm-commits] [llvm] r42584 - in /llvm/trunk: include/llvm/PassManagers.h lib/VMCore/PassManager.cpp
Author: djg Date: Wed Oct 3 14:04:09 2007 New Revision: 42584 URL: http://llvm.org/viewvc/llvm-project?rev=42584view=rev Log: Fix a using namespace llvm; in a header file. Modified: llvm/trunk/include/llvm/PassManagers.h llvm/trunk/lib/VMCore/PassManager.cpp Modified: llvm/trunk/include/llvm/PassManagers.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/PassManagers.h?rev=42584r1=42583r2=42584view=diff == --- llvm/trunk/include/llvm/PassManagers.h (original) +++ llvm/trunk/include/llvm/PassManagers.h Wed Oct 3 14:04:09 2007 @@ -13,7 +13,6 @@ #include llvm/PassManager.h #include llvm/ADT/SmallVector.h -using namespace llvm; class llvm::PMDataManager; class llvm::PMStack; @@ -381,8 +380,8 @@ } -extern void StartPassTimer(Pass *); -extern void StopPassTimer(Pass *); +extern void StartPassTimer(llvm::Pass *); +extern void StopPassTimer(llvm::Pass *); #endif Modified: llvm/trunk/lib/VMCore/PassManager.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/PassManager.cpp?rev=42584r1=42583r2=42584view=diff == --- llvm/trunk/lib/VMCore/PassManager.cpp (original) +++ llvm/trunk/lib/VMCore/PassManager.cpp Wed Oct 3 14:04:09 2007 @@ -22,6 +22,7 @@ #include algorithm #include vector #include map +using namespace llvm; // See PassManagers.h for Pass Manager infrastructure overview. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r42585 - in /llvm/trunk/lib: Analysis/ CodeGen/ CodeGen/SelectionDAG/ Target/ARM/ Target/IA64/ Target/PowerPC/ Target/X86/ Transforms/IPO/ Transforms/Scalar/ VMCore/
Author: djg
Date: Wed Oct 3 14:26:29 2007
New Revision: 42585
URL: http://llvm.org/viewvc/llvm-project?rev=42585view=rev
Log:
Use empty() member functions when that's what's being tested for instead
of comparing begin() and end().
Modified:
llvm/trunk/lib/Analysis/AliasSetTracker.cpp
llvm/trunk/lib/Analysis/LoopPass.cpp
llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp
llvm/trunk/lib/CodeGen/MachineFunction.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
llvm/trunk/lib/Target/IA64/IA64AsmPrinter.cpp
llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp
llvm/trunk/lib/Target/X86/X86ATTAsmPrinter.cpp
llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp
llvm/trunk/lib/Target/X86/X86IntelAsmPrinter.cpp
llvm/trunk/lib/Transforms/IPO/Inliner.cpp
llvm/trunk/lib/Transforms/IPO/RaiseAllocations.cpp
llvm/trunk/lib/Transforms/Scalar/LICM.cpp
llvm/trunk/lib/Transforms/Scalar/SCCP.cpp
llvm/trunk/lib/VMCore/Value.cpp
Modified: llvm/trunk/lib/Analysis/AliasSetTracker.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/AliasSetTracker.cpp?rev=42585r1=42584r2=42585view=diff
==
--- llvm/trunk/lib/Analysis/AliasSetTracker.cpp (original)
+++ llvm/trunk/lib/Analysis/AliasSetTracker.cpp Wed Oct 3 14:26:29 2007
@@ -520,7 +520,7 @@
OS forwarding to (void*)Forward;
- if (begin() != end()) {
+ if (!empty()) {
OS Pointers: ;
for (iterator I = begin(), E = end(); I != E; ++I) {
if (I != begin()) OS , ;
Modified: llvm/trunk/lib/Analysis/LoopPass.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/LoopPass.cpp?rev=42585r1=42584r2=42585view=diff
==
--- llvm/trunk/lib/Analysis/LoopPass.cpp (original)
+++ llvm/trunk/lib/Analysis/LoopPass.cpp Wed Oct 3 14:26:29 2007
@@ -54,7 +54,7 @@
}
// Move all subloops into the parent loop.
-while (L-begin() != L-end())
+while (!L-empty())
ParentLoop-addChildLoop(L-removeChildLoop(L-end()-1));
} else {
// Reparent all of the blocks in this loop. Since BBLoop had no parent,
@@ -78,7 +78,7 @@
}
// Move all of the subloops to the top-level.
-while (L-begin() != L-end())
+while (!L-empty())
LI-addTopLevelLoop(L-removeChildLoop(L-end()-1));
}
Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=42585r1=42584r2=42585view=diff
==
--- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Wed Oct 3 14:26:29 2007
@@ -817,17 +817,15 @@
MachineBasicBlock::iterator MI = MBB-begin(), miEnd = MBB-end();
-if (MBB-livein_begin() != MBB-livein_end()) {
- // Create intervals for live-ins to this BB first.
- for (MachineBasicBlock::const_livein_iterator LI = MBB-livein_begin(),
- LE = MBB-livein_end(); LI != LE; ++LI) {
-handleLiveInRegister(MBB, MIIndex, getOrCreateInterval(*LI));
-// Multiple live-ins can alias the same register.
-for (const unsigned* AS = mri_-getSubRegisters(*LI); *AS; ++AS)
- if (!hasInterval(*AS))
-handleLiveInRegister(MBB, MIIndex, getOrCreateInterval(*AS),
- true);
- }
+// Create intervals for live-ins to this BB first.
+for (MachineBasicBlock::const_livein_iterator LI = MBB-livein_begin(),
+ LE = MBB-livein_end(); LI != LE; ++LI) {
+ handleLiveInRegister(MBB, MIIndex, getOrCreateInterval(*LI));
+ // Multiple live-ins can alias the same register.
+ for (const unsigned* AS = mri_-getSubRegisters(*LI); *AS; ++AS)
+if (!hasInterval(*AS))
+ handleLiveInRegister(MBB, MIIndex, getOrCreateInterval(*AS),
+ true);
}
for (; MI != miEnd; ++MI) {
Modified: llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp?rev=42585r1=42584r2=42585view=diff
==
--- llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp Wed Oct 3 14:26:29 2007
@@ -119,7 +119,7 @@
OS :\n;
const MRegisterInfo *MRI = MF-getTarget().getRegisterInfo();
- if (livein_begin() != livein_end()) {
+ if (!livein_empty()) {
OS Live Ins:;
for (const_livein_iterator I = livein_begin(),E = livein_end(); I != E;
++I)
OutputReg(OS, *I, MRI);
Modified: llvm/trunk/lib/CodeGen/MachineFunction.cpp
URL:
[llvm-commits] [llvm] r42487 - in /llvm/trunk/include/llvm: Analysis/CallGraph.h Analysis/LoopInfo.h Support/CallSite.h
Author: djg
Date: Mon Oct 1 11:01:23 2007
New Revision: 42487
URL: http://llvm.org/viewvc/llvm-project?rev=42487view=rev
Log:
Add empty() member functions to a few container-like classes.
Modified:
llvm/trunk/include/llvm/Analysis/CallGraph.h
llvm/trunk/include/llvm/Analysis/LoopInfo.h
llvm/trunk/include/llvm/Support/CallSite.h
Modified: llvm/trunk/include/llvm/Analysis/CallGraph.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/CallGraph.h?rev=42487r1=42486r2=42487view=diff
==
--- llvm/trunk/include/llvm/Analysis/CallGraph.h (original)
+++ llvm/trunk/include/llvm/Analysis/CallGraph.h Mon Oct 1 11:01:23 2007
@@ -189,6 +189,7 @@
inline iterator end() { return CalledFunctions.end(); }
inline const_iterator begin() const { return CalledFunctions.begin(); }
inline const_iterator end() const { return CalledFunctions.end(); }
+ inline bool empty() const { return CalledFunctions.empty(); }
inline unsigned size() const { return CalledFunctions.size(); }
// Subscripting operator - Return the i'th called function...
Modified: llvm/trunk/include/llvm/Analysis/LoopInfo.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/LoopInfo.h?rev=42487r1=42486r2=42487view=diff
==
--- llvm/trunk/include/llvm/Analysis/LoopInfo.h (original)
+++ llvm/trunk/include/llvm/Analysis/LoopInfo.h Mon Oct 1 11:01:23 2007
@@ -79,6 +79,7 @@
typedef std::vectorLoop*::const_iterator iterator;
iterator begin() const { return SubLoops.begin(); }
iterator end() const { return SubLoops.end(); }
+ bool empty() const { return SubLoops.empty(); }
/// getBlocks - Get a list of the basic blocks which make up this loop.
///
Modified: llvm/trunk/include/llvm/Support/CallSite.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/CallSite.h?rev=42487r1=42486r2=42487view=diff
==
--- llvm/trunk/include/llvm/Support/CallSite.h (original)
+++ llvm/trunk/include/llvm/Support/CallSite.h Mon Oct 1 11:01:23 2007
@@ -110,6 +110,7 @@
return I-op_begin()+3; // Skip Function, BB, BB
}
arg_iterator arg_end() const { return I-op_end(); }
+ bool arg_empty() const { return arg_end() == arg_begin(); }
unsigned arg_size() const { return unsigned(arg_end() - arg_begin()); }
bool operator(const CallSite CS) const {
___
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[llvm-commits] [llvm] r42506 - /llvm/trunk/lib/CodeGen/DwarfWriter.cpp
Author: djg
Date: Mon Oct 1 17:40:20 2007
New Revision: 42506
URL: http://llvm.org/viewvc/llvm-project?rev=42506view=rev
Log:
Move the code that emits the .file directives so that it runs after the
SourceFiles list is fully filled in so that it sees all of the files.
Modified:
llvm/trunk/lib/CodeGen/DwarfWriter.cpp
Modified: llvm/trunk/lib/CodeGen/DwarfWriter.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/DwarfWriter.cpp?rev=42506r1=42505r2=42506view=diff
==
--- llvm/trunk/lib/CodeGen/DwarfWriter.cpp (original)
+++ llvm/trunk/lib/CodeGen/DwarfWriter.cpp Mon Oct 1 17:40:20 2007
@@ -1971,19 +1971,6 @@
if (didInitial) return;
didInitial = true;
-// Print out .file directives to specify files for .loc directives.
-if (TAI-hasDotLocAndDotFile()) {
- const UniqueVectorSourceFileInfo SourceFiles = MMI-getSourceFiles();
- const UniqueVectorstd::string Directories = MMI-getDirectories();
- for (unsigned i = 1, e = SourceFiles.size(); i = e; ++i) {
-sys::Path FullPath(Directories[SourceFiles[i].getDirectoryID()]);
-bool AppendOk = FullPath.appendComponent(SourceFiles[i].getName());
-assert(AppendOk Could not append filename to directory!);
-Asm-EmitFile(i, FullPath.toString());
-Asm-EOL();
- }
-}
-
// Dwarf sections base addresses.
if (TAI-doesDwarfRequireFrameSection()) {
Asm-SwitchToDataSection(TAI-getDwarfFrameSection());
@@ -2626,9 +2613,6 @@
MMI = mmi;
shouldEmit = true;
- // Emit initial sections
- EmitInitial();
-
// Create all the compile unit DIEs.
ConstructCompileUnitDIEs();
@@ -2640,6 +2624,23 @@
// Prime section data.
SectionMap.insert(TAI-getTextSection());
+
+ // Print out .file directives to specify files for .loc directives. These
+ // are printed out early so that they precede any .loc directives.
+ if (TAI-hasDotLocAndDotFile()) {
+const UniqueVectorSourceFileInfo SourceFiles =
MMI-getSourceFiles();
+const UniqueVectorstd::string Directories = MMI-getDirectories();
+for (unsigned i = 1, e = SourceFiles.size(); i = e; ++i) {
+ sys::Path FullPath(Directories[SourceFiles[i].getDirectoryID()]);
+ bool AppendOk = FullPath.appendComponent(SourceFiles[i].getName());
+ assert(AppendOk Could not append filename to directory!);
+ Asm-EmitFile(i, FullPath.toString());
+ Asm-EOL();
+}
+ }
+
+ // Emit initial sections
+ EmitInitial();
}
}
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[llvm-commits] [llvm] r42434 - /llvm/trunk/lib/CodeGen/DwarfWriter.cpp
Author: djg
Date: Fri Sep 28 10:43:33 2007
New Revision: 42434
URL: http://llvm.org/viewvc/llvm-project?rev=42434view=rev
Log:
Use 32-bit data directives for DW_FORM_data4 format data, even on
targets with 64-bit addresses.
Modified:
llvm/trunk/lib/CodeGen/DwarfWriter.cpp
Modified: llvm/trunk/lib/CodeGen/DwarfWriter.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/DwarfWriter.cpp?rev=42434r1=42433r2=42434view=diff
==
--- llvm/trunk/lib/CodeGen/DwarfWriter.cpp (original)
+++ llvm/trunk/lib/CodeGen/DwarfWriter.cpp Fri Sep 28 10:43:33 2007
@@ -870,18 +870,20 @@
/// EmitReference - Emit a reference to a label.
///
- void EmitReference(DWLabel Label, bool IsPCRelative = false) const {
-EmitReference(Label.Tag, Label.Number, IsPCRelative);
+ void EmitReference(DWLabel Label, bool IsPCRelative = false,
+ bool Force32Bit = false) const {
+EmitReference(Label.Tag, Label.Number, IsPCRelative, Force32Bit);
}
void EmitReference(const char *Tag, unsigned Number,
- bool IsPCRelative = false) const {
-PrintRelDirective();
+ bool IsPCRelative = false, bool Force32Bit = false) const
{
+PrintRelDirective(Force32Bit);
PrintLabelName(Tag, Number);
if (IsPCRelative) O - TAI-getPCSymbol();
}
- void EmitReference(const std::string Name, bool IsPCRelative = false) const
{
-PrintRelDirective();
+ void EmitReference(const std::string Name, bool IsPCRelative = false,
+ bool Force32Bit = false) const {
+PrintRelDirective(Force32Bit);
O Name;
@@ -3479,7 +3481,7 @@
/// EmitValue - Emit label value.
///
void DIEDwarfLabel::EmitValue(DwarfDebug DD, unsigned Form) {
- DD.EmitReference(Label);
+ DD.EmitReference(Label, false, Form == DW_FORM_data4);
}
/// SizeOf - Determine size of label value in bytes.
@@ -3493,7 +3495,7 @@
/// EmitValue - Emit label value.
///
void DIEObjectLabel::EmitValue(DwarfDebug DD, unsigned Form) {
- DD.EmitReference(Label);
+ DD.EmitReference(Label, false, Form == DW_FORM_data4);
}
/// SizeOf - Determine size of label value in bytes.
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Re: [llvm-commits] [llvm] r42285 - in /llvm/trunk/lib/Target/X86: X86FloatingPoint.cpp X86ISelLowering.cpp X86ISelLowering.h X86InstrFPStack.td X86InstrInfo.cpp X86InstrInfo.td X86InstrSSE.td X86Instr
+def X86cmp_new : SDNodeX86ISD::CMP_NEW , SDTX86CmpTest; X86ISD::CMP_NEW SelectionDAG nodes return an i32 flags value, however the corresponding X86cmp_new pattern-matching nodes use SDTX86CmpTest, which has no result values. Is this intentional? If so, how is the discrepancy handled? X86ISD::CMP_NEW does *not* return an flag result. It returns an result in a physical register EFLAGS. It's up to the scheduler to ensure nothing that can potentially modify EFLAGS is scheduled between CMP_NEW and its users. The goal of what I've been doing is to eliminate the need for the MVT::Flag hackery (which prevents SDNode CSE, scheduling, etc.). It returns an MVT::i32 flags result, rather than an MVT::Flag flags result. Or at least, that's how I interpreted this code in X86ISelLowering.cpp: Cond = DAG.getNode(X86ISD::CMP_NEW, MVT::i32, Op0, Op1); Now, X86InstrInfo.td has the following: def SDTX86CmpTest : SDTypeProfile0, 2, [SDTCisSameAs0, 1]; def X86cmp_new : SDNodeX86ISD::CMP_NEW , SDTX86CmpTest; At an initial glance, these are inconsistent. Does the let Defs = [EFLAGS] around each of the instructions that uses X86cmp_new automatically get used for the result value of a node? That doesn't appear to be the case in other instruction patterns that have implicit defs. +def : Pat(parallel (X86cmp_new GR8:$src1, 0), (implicit EFLAGS)), + (NEW_TEST8rr GR8:$src1, GR8:$src1); In the SelectionDAG IR, an SDNode can return multiple results. However, in this GCC-RTL-like pattern langauge, where many things are supposed to directly correspond to SelectionDAG counterparts, nodes can return at most one result. They must be grouped together in a parallel to represent operations that have multiple results. It seems like this will result in more discrepancies. Am I misunderstanding something? Again, no discrepancies. Instruction NEW_TEST8rr produces an implicit result in EFLAGS. What the pattern is saying is the target independent node expects the implicit result EFLAGS to be modeled as an explicit result. BTW, I intend to get rid of parallel. I just haven't gotten around to it. Ok, cool. I'll take a closer look at this when it's ready. Dan -- Dan Gohman, Cray Inc. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r42435 - /llvm/trunk/lib/CodeGen/DwarfWriter.cpp
Author: djg
Date: Fri Sep 28 11:50:28 2007
New Revision: 42435
URL: http://llvm.org/viewvc/llvm-project?rev=42435view=rev
Log:
Make the checks for DW_FORM_data4 consistent with the others, and
add more such code for DIEDwarfLabel::SizeOf and DIEObjectLabel::SizeOf.
Modified:
llvm/trunk/lib/CodeGen/DwarfWriter.cpp
Modified: llvm/trunk/lib/CodeGen/DwarfWriter.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/DwarfWriter.cpp?rev=42435r1=42434r2=42435view=diff
==
--- llvm/trunk/lib/CodeGen/DwarfWriter.cpp (original)
+++ llvm/trunk/lib/CodeGen/DwarfWriter.cpp Fri Sep 28 11:50:28 2007
@@ -3481,12 +3481,14 @@
/// EmitValue - Emit label value.
///
void DIEDwarfLabel::EmitValue(DwarfDebug DD, unsigned Form) {
- DD.EmitReference(Label, false, Form == DW_FORM_data4);
+ bool IsSmall = Form == DW_FORM_data4;
+ DD.EmitReference(Label, false, IsSmall);
}
/// SizeOf - Determine size of label value in bytes.
///
unsigned DIEDwarfLabel::SizeOf(const DwarfDebug DD, unsigned Form) const {
+ if (Form == DW_FORM_data4) return 4;
return DD.getTargetData()-getPointerSize();
}
@@ -3495,12 +3497,14 @@
/// EmitValue - Emit label value.
///
void DIEObjectLabel::EmitValue(DwarfDebug DD, unsigned Form) {
- DD.EmitReference(Label, false, Form == DW_FORM_data4);
+ bool IsSmall = Form == DW_FORM_data4;
+ DD.EmitReference(Label, false, IsSmall);
}
/// SizeOf - Determine size of label value in bytes.
///
unsigned DIEObjectLabel::SizeOf(const DwarfDebug DD, unsigned Form) const {
+ if (Form == DW_FORM_data4) return 4;
return DD.getTargetData()-getPointerSize();
}
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Re: [llvm-commits] lib/CodeGen/SelectionDAG/TargetLowering.cpp test/CodeGen/X86/2007-09-27-LDIntrinsics.ll utils/TableGen/CodeGenTarget.cpp utils/TableGen/IntrinsicEmitter.cpp
Why not use anyfp? This would allow us to have one sqrt and one powi definition. Hard to explain; it just feels like the sort of thing where all the values ought to be spelled out. FWIW, sqrt was one of the main reasons we created anyfloat. The codegen portion of the vector-intrinsics patch depends on sqrt using anyfloat. Dan -- Dan Gohman, Cray Inc. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] lib/CodeGen/SelectionDAG/TargetLowering.cpp test/CodeGen/X86/2007-09-27-LDIntrinsics.ll utils/TableGen/CodeGenTarget.cpp utils/TableGen/IntrinsicEmitter.cpp
FWIW, sqrt was one of the main reasons we created anyfloat. The codegen portion of the vector-intrinsics patch depends on sqrt using anyfloat. ? It wasn't before my change, either. The codegen portion of that patch isn't committed yet. But if there's any reason why anyfloat isn't suitable for the likes of sqrt, I'd like to know of it before I get around to updating and submitting the patch :-). Dan -- Dan Gohman, Cray Inc. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r42457 - in /llvm/trunk: lib/CodeGen/SelectionDAG/LegalizeDAG.cpp test/CodeGen/X86/illegal-insert.ll
Author: djg
Date: Fri Sep 28 18:53:40 2007
New Revision: 42457
URL: http://llvm.org/viewvc/llvm-project?rev=42457view=rev
Log:
Teach SplitVectorOp how to split INSERT_VECTOR_ELT.
Added:
llvm/trunk/test/CodeGen/X86/illegal-insert.ll
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=42457r1=42456r2=42457view=diff
==
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Sep 28 18:53:40 2007
@@ -5837,6 +5837,18 @@
Lo = Node-getOperand(0);
Hi = Node-getOperand(1);
break;
+ case ISD::INSERT_VECTOR_ELT: {
+SplitVectorOp(Node-getOperand(0), Lo, Hi);
+unsigned Index = castConstantSDNode(Node-getOperand(2))-getValue();
+SDOperand ScalarOp = Node-getOperand(1);
+if (Index NewNumElts)
+ Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT, Lo, ScalarOp,
+ DAG.getConstant(Index, TLI.getPointerTy()));
+else
+ Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT, Hi, ScalarOp,
+ DAG.getConstant(Index - NewNumElts,
TLI.getPointerTy()));
+break;
+ }
case ISD::BUILD_VECTOR: {
SmallVectorSDOperand, 8 LoOps(Node-op_begin(),
Node-op_begin()+NewNumElts);
Added: llvm/trunk/test/CodeGen/X86/illegal-insert.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/illegal-insert.ll?rev=42457view=auto
==
--- llvm/trunk/test/CodeGen/X86/illegal-insert.ll (added)
+++ llvm/trunk/test/CodeGen/X86/illegal-insert.ll Fri Sep 28 18:53:40 2007
@@ -0,0 +1,18 @@
+; RUN: llvm-as %s -o - | llc -march=x86-64
+
+define 4 x double @foo0(4 x double %t) {
+ %r = insertelement 4 x double %t, double 2.3, i32 0
+ ret 4 x double %r
+}
+define 4 x double @foo1(4 x double %t) {
+ %r = insertelement 4 x double %t, double 2.3, i32 1
+ ret 4 x double %r
+}
+define 4 x double @foo2(4 x double %t) {
+ %r = insertelement 4 x double %t, double 2.3, i32 2
+ ret 4 x double %r
+}
+define 4 x double @foo3(4 x double %t) {
+ %r = insertelement 4 x double %t, double 2.3, i32 3
+ ret 4 x double %r
+}
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[llvm-commits] [llvm] r42419 - in /llvm/trunk: include/llvm/Target/TargetAsmInfo.h lib/CodeGen/DwarfWriter.cpp lib/Target/PowerPC/PPCTargetAsmInfo.cpp lib/Target/TargetAsmInfo.cpp lib/Target/X86/X86Re
Author: djg
Date: Thu Sep 27 18:12:31 2007
New Revision: 42419
URL: http://llvm.org/viewvc/llvm-project?rev=42419view=rev
Log:
TargetAsmInfo::getAddressSize() was incorrect for x86-64 and 64-bit targets
other than PPC64. Instead of fixing it, just remove it and fix all the
places that use it to use TargetData::getPointerSize() instead, as there
aren't very many. Most of the references were in DwarfWriter.cpp.
Modified:
llvm/trunk/include/llvm/Target/TargetAsmInfo.h
llvm/trunk/lib/CodeGen/DwarfWriter.cpp
llvm/trunk/lib/Target/PowerPC/PPCTargetAsmInfo.cpp
llvm/trunk/lib/Target/TargetAsmInfo.cpp
llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
Modified: llvm/trunk/include/llvm/Target/TargetAsmInfo.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetAsmInfo.h?rev=42419r1=42418r2=42419view=diff
==
--- llvm/trunk/include/llvm/Target/TargetAsmInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetAsmInfo.h Thu Sep 27 18:12:31 2007
@@ -56,10 +56,6 @@
/// section on this target. Null if this target doesn't support zerofill.
const char *ZeroFillDirective;// Default is null.
-/// AddressSize - Size of addresses used in file.
-///
-unsigned AddressSize; // Defaults to 4.
-
/// NeedsSet - True if target asm can't compute addresses on data
/// directives.
bool NeedsSet;// Defaults to false.
@@ -400,9 +396,6 @@
const char *getZeroFillDirective() const {
return ZeroFillDirective;
}
-unsigned getAddressSize() const {
- return AddressSize;
-}
bool needsSet() const {
return NeedsSet;
}
Modified: llvm/trunk/lib/CodeGen/DwarfWriter.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/DwarfWriter.cpp?rev=42419r1=42418r2=42419view=diff
==
--- llvm/trunk/lib/CodeGen/DwarfWriter.cpp (original)
+++ llvm/trunk/lib/CodeGen/DwarfWriter.cpp Thu Sep 27 18:12:31 2007
@@ -829,12 +829,13 @@
AsmPrinter *getAsm() const { return Asm; }
MachineModuleInfo *getMMI() const { return MMI; }
const TargetAsmInfo *getTargetAsmInfo() const { return TAI; }
+ const TargetData *getTargetData() const { return TD; }
void PrintRelDirective(bool Force32Bit = false, bool isInSection = false)
const
{
if (isInSection TAI-getDwarfSectionOffsetDirective())
O TAI-getDwarfSectionOffsetDirective();
-else if (Force32Bit || TAI-getAddressSize() == sizeof(int32_t))
+else if (Force32Bit || TD-getPointerSize() == sizeof(int32_t))
O TAI-getData32bitsDirective();
else
O TAI-getData64bitsDirective();
@@ -969,7 +970,7 @@
int stackGrowth =
Asm-TM.getFrameInfo()-getStackGrowthDirection() ==
TargetFrameInfo::StackGrowsUp ?
-TAI-getAddressSize() : -TAI-getAddressSize();
+TD-getPointerSize() : -TD-getPointerSize();
bool IsLocal = BaseLabel strcmp(BaseLabel, label) == 0;
for (unsigned i = 0, N = Moves.size(); i N; ++i) {
@@ -1392,7 +1393,7 @@
///
DIE *ConstructPointerType(CompileUnit *Unit, const std::string Name) {
DIE Buffer(DW_TAG_pointer_type);
-AddUInt(Buffer, DW_AT_byte_size, 0, TAI-getAddressSize());
+AddUInt(Buffer, DW_AT_byte_size, 0, TD-getPointerSize());
if (!Name.empty()) AddString(Buffer, DW_AT_name, DW_FORM_string, Name);
return Unit-AddDie(Buffer);
}
@@ -2146,7 +2147,7 @@
Asm-EmitInt16(DWARF_VERSION); Asm-EOL(DWARF version number);
EmitSectionOffset(abbrev_begin, section_abbrev, 0, 0, true, false);
Asm-EOL(Offset Into Abbrev. Section);
-Asm-EmitInt8(TAI-getAddressSize()); Asm-EOL(Address Size (in bytes));
+Asm-EmitInt8(TD-getPointerSize()); Asm-EOL(Address Size (in bytes));
EmitDIE(Die);
// FIXME - extra padding for gdb bug.
@@ -2297,7 +2298,7 @@
// Define the line address.
Asm-EmitInt8(0); Asm-EOL(Extended Op);
-Asm-EmitInt8(TAI-getAddressSize() + 1); Asm-EOL(Op size);
+Asm-EmitInt8(TD-getPointerSize() + 1); Asm-EOL(Op size);
Asm-EmitInt8(DW_LNE_set_address); Asm-EOL(DW_LNE_set_address);
EmitReference(label, LabelID); Asm-EOL(Location label);
@@ -2335,7 +2336,7 @@
// Define last address of section.
Asm-EmitInt8(0); Asm-EOL(Extended Op);
- Asm-EmitInt8(TAI-getAddressSize() + 1); Asm-EOL(Op size);
+ Asm-EmitInt8(TD-getPointerSize() + 1); Asm-EOL(Op size);
Asm-EmitInt8(DW_LNE_set_address); Asm-EOL(DW_LNE_set_address);
EmitReference(section_end, j + 1); Asm-EOL(Section end label);
@@ -2359,7 +2360,7 @@
int stackGrowth =
Asm-TM.getFrameInfo()-getStackGrowthDirection() ==
TargetFrameInfo::StackGrowsUp ?
-
[llvm-commits] [llvm] r42297 - in /llvm/trunk/lib: CodeGen/SelectionDAG/TargetLowering.cpp Target/X86/X86ISelLowering.cpp
Author: djg
Date: Tue Sep 25 10:10:49 2007
New Revision: 42297
URL: http://llvm.org/viewvc/llvm-project?rev=42297view=rev
Log:
Move the setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand) and
the check to see if the assembler supports .loc from X86TargetLowering
into the superclass TargetLowering.
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=42297r1=42296r2=42297view=diff
==
--- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Tue Sep 25 10:10:49
2007
@@ -20,6 +20,7 @@
#include llvm/ADT/StringExtras.h
#include llvm/ADT/STLExtras.h
#include llvm/Support/MathExtras.h
+#include llvm/Target/TargetAsmInfo.h
using namespace llvm;
/// InitLibcallNames - Set default libcall names.
@@ -169,6 +170,10 @@
InitLibcallNames(LibcallRoutineNames);
InitCmpLibcallCCs(CmpLibcallCCs);
+
+ // Tell Legalize whether the assembler supports DEBUG_LOC.
+ if (!TM.getTargetAsmInfo()-hasDotLocAndDotFile())
+setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
}
TargetLowering::~TargetLowering() {}
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=42297r1=42296r2=42297view=diff
==
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Sep 25 10:10:49 2007
@@ -33,7 +33,6 @@
#include llvm/CodeGen/SSARegMap.h
#include llvm/Support/CommandLine.h
#include llvm/Support/MathExtras.h
-#include llvm/Target/TargetAsmInfo.h
#include llvm/Target/TargetOptions.h
#include llvm/ADT/StringExtras.h
#include llvm/ParameterAttributes.h
@@ -231,13 +230,8 @@
setOperationAction(ISD::MEMSET , MVT::Other, Custom);
setOperationAction(ISD::MEMCPY , MVT::Other, Custom);
- // Use the default ISD::LOCATION expansion, and tell Legalize it's
- // ok to use DEBUG_LOC if we have an assembler that supports it.
+ // Use the default ISD::LOCATION expansion.
setOperationAction(ISD::LOCATION, MVT::Other, Expand);
- if (TM.getTargetAsmInfo()-hasDotLocAndDotFile())
-setOperationAction(ISD::DEBUG_LOC, MVT::Other, Legal);
- else
-setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
// FIXME - use subtarget debug flags
if (!Subtarget-isTargetDarwin()
!Subtarget-isTargetELF()
___
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Re: [llvm-commits] [llvm] r42285 - in /llvm/trunk/lib/Target/X86: X86FloatingPoint.cpp X86ISelLowering.cpp X86ISelLowering.h X86InstrFPStack.td X86InstrInfo.cpp X86InstrInfo.td X86InstrSSE.td X86Instr
+def X86cmp_new : SDNodeX86ISD::CMP_NEW , SDTX86CmpTest; X86ISD::CMP_NEW SelectionDAG nodes return an i32 flags value, however the corresponding X86cmp_new pattern-matching nodes use SDTX86CmpTest, which has no result values. Is this intentional? If so, how is the discrepancy handled? +def : Pat(parallel (X86cmp_new GR8:$src1, 0), (implicit EFLAGS)), + (NEW_TEST8rr GR8:$src1, GR8:$src1); In the SelectionDAG IR, an SDNode can return multiple results. However, in this GCC-RTL-like pattern langauge, where many things are supposed to directly correspond to SelectionDAG counterparts, nodes can return at most one result. They must be grouped together in a parallel to represent operations that have multiple results. It seems like this will result in more discrepancies. Am I misunderstanding something? Dan -- Dan Gohman, Cray Inc. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r42308 - in /llvm/trunk: lib/Target/X86/X86ISelDAGToDAG.cpp lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86ISelLowering.h test/CodeGen/X86/divrem.ll
Author: djg
Date: Tue Sep 25 13:23:27 2007
New Revision: 42308
URL: http://llvm.org/viewvc/llvm-project?rev=42308view=rev
Log:
When both x/y and x%y are needed (x and y both scalar integer), compute
both results with a single div or idiv instruction. This uses new X86ISD
nodes for DIV and IDIV which are introduced during the legalize phase
so that the SelectionDAG's CSE can automatically eliminate redundant
computations.
Added:
llvm/trunk/test/CodeGen/X86/divrem.ll
Modified:
llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
llvm/trunk/lib/Target/X86/X86ISelLowering.h
Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=42308r1=42307r2=42308view=diff
==
--- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Tue Sep 25 13:23:27 2007
@@ -1162,12 +1162,9 @@
return NULL;
}
-case ISD::SDIV:
-case ISD::UDIV:
-case ISD::SREM:
-case ISD::UREM: {
- bool isSigned = Opcode == ISD::SDIV || Opcode == ISD::SREM;
- bool isDiv= Opcode == ISD::SDIV || Opcode == ISD::UDIV;
+case X86ISD::DIV:
+case X86ISD::IDIV: {
+ bool isSigned = Opcode == X86ISD::IDIV;
if (!isSigned)
switch (NVT) {
default: assert(0 Unsupported VT!);
@@ -1275,31 +1272,49 @@
SDOperand(CurDAG-getTargetNode(Opc, MVT::Flag, N1, InFlag), 0);
}
- unsigned Reg = isDiv ? LoReg : HiReg;
- SDOperand Result;
- if (Reg == X86::AH Subtarget-is64Bit()) {
-// Prevent use of AH in a REX instruction by referencing AX instead.
-// Shift it down 8 bits.
-Result = CurDAG-getCopyFromReg(Chain, X86::AX, MVT::i16, InFlag);
-Chain = Result.getValue(1);
-Result = SDOperand(CurDAG-getTargetNode(X86::SHR16ri, MVT::i16,
Result,
- CurDAG-getTargetConstant(8, MVT::i8)),
0);
-// Then truncate it down to i8.
-SDOperand SRIdx = CurDAG-getTargetConstant(1, MVT::i32); // SubRegSet
1
-Result = SDOperand(CurDAG-getTargetNode(X86::EXTRACT_SUBREG,
- MVT::i8, Result, SRIdx), 0);
- } else {
-Result = CurDAG-getCopyFromReg(Chain, Reg, NVT, InFlag);
+ // Copy the division (low) result, if it is needed.
+ if (!N.getValue(0).use_empty()) {
+SDOperand Result = CurDAG-getCopyFromReg(Chain, LoReg, NVT, InFlag);
Chain = Result.getValue(1);
+InFlag = Result.getValue(2);
+ReplaceUses(N.getValue(0), Result);
+#ifndef NDEBUG
+DOUT std::string(Indent-2, ' ') = ;
+DEBUG(Result.Val-dump(CurDAG));
+DOUT \n;
+#endif
+ }
+ // Copy the remainder (high) result, if it is needed.
+ if (!N.getValue(1).use_empty()) {
+SDOperand Result;
+if (HiReg == X86::AH Subtarget-is64Bit()) {
+ // Prevent use of AH in a REX instruction by referencing AX instead.
+ // Shift it down 8 bits.
+ Result = CurDAG-getCopyFromReg(Chain, X86::AX, MVT::i16, InFlag);
+ Chain = Result.getValue(1);
+ InFlag = Result.getValue(2);
+ Result = SDOperand(CurDAG-getTargetNode(X86::SHR16ri, MVT::i16,
Result,
+ CurDAG-getTargetConstant(8, MVT::i8)),
0);
+ // Then truncate it down to i8.
+ SDOperand SRIdx = CurDAG-getTargetConstant(1, MVT::i32); //
SubRegSet 1
+ Result = SDOperand(CurDAG-getTargetNode(X86::EXTRACT_SUBREG,
+ MVT::i8, Result, SRIdx), 0);
+} else {
+ Result = CurDAG-getCopyFromReg(Chain, HiReg, NVT, InFlag);
+ Chain = Result.getValue(1);
+ InFlag = Result.getValue(2);
+}
+ReplaceUses(N.getValue(1), Result);
+#ifndef NDEBUG
+DOUT std::string(Indent-2, ' ') = ;
+DEBUG(Result.Val-dump(CurDAG));
+DOUT \n;
+#endif
}
- ReplaceUses(N.getValue(0), Result);
if (foldedLoad)
ReplaceUses(N1.getValue(1), Chain);
#ifndef NDEBUG
- DOUT std::string(Indent-2, ' ') = ;
- DEBUG(Result.Val-dump(CurDAG));
- DOUT \n;
Indent -= 2;
#endif
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=42308r1=42307r2=42308view=diff
==
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Sep 25 13:23:27 2007
@@ -155,6 +155,27 @@
setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
}
+ // Divide and remainder are lowered to use div or idiv in legalize in
[llvm-commits] [llvm] r42313 - /llvm/trunk/lib/Target/X86/X86ISelLowering.h
Author: djg Date: Tue Sep 25 14:37:26 2007 New Revision: 42313 URL: http://llvm.org/viewvc/llvm-project?rev=42313view=rev Log: Fix a typo in a comment. Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=42313r1=42312r2=42313view=diff == --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Tue Sep 25 14:37:26 2007 @@ -181,7 +181,7 @@ /// in order to obtain suitable precision. FRSQRT, FRCP, - /// DIV, IDIV - Unsigned and signed integer division and reciprocal. + /// DIV, IDIV - Unsigned and signed integer division and remainder. /// DIV, IDIV, ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r42316 - in /llvm/trunk/lib/Target: ARM/ARMTargetAsmInfo.h Alpha/AlphaTargetAsmInfo.h IA64/IA64TargetAsmInfo.h Mips/MipsTargetAsmInfo.h PowerPC/PPCTargetAsmInfo.h Sparc/SparcTarg
Author: djg
Date: Tue Sep 25 15:27:06 2007
New Revision: 42316
URL: http://llvm.org/viewvc/llvm-project?rev=42316view=rev
Log:
More explicit keywords.
Modified:
llvm/trunk/lib/Target/ARM/ARMTargetAsmInfo.h
llvm/trunk/lib/Target/Alpha/AlphaTargetAsmInfo.h
llvm/trunk/lib/Target/IA64/IA64TargetAsmInfo.h
llvm/trunk/lib/Target/Mips/MipsTargetAsmInfo.h
llvm/trunk/lib/Target/PowerPC/PPCTargetAsmInfo.h
llvm/trunk/lib/Target/Sparc/SparcTargetAsmInfo.h
llvm/trunk/lib/Target/X86/X86TargetAsmInfo.h
Modified: llvm/trunk/lib/Target/ARM/ARMTargetAsmInfo.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetAsmInfo.h?rev=42316r1=42315r2=42316view=diff
==
--- llvm/trunk/lib/Target/ARM/ARMTargetAsmInfo.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMTargetAsmInfo.h Tue Sep 25 15:27:06 2007
@@ -23,7 +23,7 @@
class ARMTargetMachine;
struct ARMTargetAsmInfo : public TargetAsmInfo {
-ARMTargetAsmInfo(const ARMTargetMachine TM);
+explicit ARMTargetAsmInfo(const ARMTargetMachine TM);
const ARMSubtarget *Subtarget;
Modified: llvm/trunk/lib/Target/Alpha/AlphaTargetAsmInfo.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaTargetAsmInfo.h?rev=42316r1=42315r2=42316view=diff
==
--- llvm/trunk/lib/Target/Alpha/AlphaTargetAsmInfo.h (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaTargetAsmInfo.h Tue Sep 25 15:27:06 2007
@@ -22,7 +22,7 @@
class AlphaTargetMachine;
struct AlphaTargetAsmInfo : public TargetAsmInfo {
-AlphaTargetAsmInfo(const AlphaTargetMachine TM);
+explicit AlphaTargetAsmInfo(const AlphaTargetMachine TM);
};
} // namespace llvm
Modified: llvm/trunk/lib/Target/IA64/IA64TargetAsmInfo.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64TargetAsmInfo.h?rev=42316r1=42315r2=42316view=diff
==
--- llvm/trunk/lib/Target/IA64/IA64TargetAsmInfo.h (original)
+++ llvm/trunk/lib/Target/IA64/IA64TargetAsmInfo.h Tue Sep 25 15:27:06 2007
@@ -22,7 +22,7 @@
class IA64TargetMachine;
struct IA64TargetAsmInfo : public TargetAsmInfo {
-IA64TargetAsmInfo(const IA64TargetMachine TM);
+explicit IA64TargetAsmInfo(const IA64TargetMachine TM);
};
Modified: llvm/trunk/lib/Target/Mips/MipsTargetAsmInfo.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetAsmInfo.h?rev=42316r1=42315r2=42316view=diff
==
--- llvm/trunk/lib/Target/Mips/MipsTargetAsmInfo.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsTargetAsmInfo.h Tue Sep 25 15:27:06 2007
@@ -22,7 +22,7 @@
class MipsTargetMachine;
struct MipsTargetAsmInfo : public TargetAsmInfo {
-MipsTargetAsmInfo(const MipsTargetMachine TM);
+explicit MipsTargetAsmInfo(const MipsTargetMachine TM);
};
} // namespace llvm
Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetAsmInfo.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetAsmInfo.h?rev=42316r1=42315r2=42316view=diff
==
--- llvm/trunk/lib/Target/PowerPC/PPCTargetAsmInfo.h (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCTargetAsmInfo.h Tue Sep 25 15:27:06 2007
@@ -22,15 +22,15 @@
class PPCTargetMachine;
struct PPCTargetAsmInfo : public TargetAsmInfo {
-PPCTargetAsmInfo(const PPCTargetMachine TM);
+explicit PPCTargetAsmInfo(const PPCTargetMachine TM);
};
struct DarwinTargetAsmInfo : public PPCTargetAsmInfo {
-DarwinTargetAsmInfo(const PPCTargetMachine TM);
+explicit DarwinTargetAsmInfo(const PPCTargetMachine TM);
};
struct LinuxTargetAsmInfo : public PPCTargetAsmInfo {
-LinuxTargetAsmInfo(const PPCTargetMachine TM);
+explicit LinuxTargetAsmInfo(const PPCTargetMachine TM);
};
} // namespace llvm
Modified: llvm/trunk/lib/Target/Sparc/SparcTargetAsmInfo.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcTargetAsmInfo.h?rev=42316r1=42315r2=42316view=diff
==
--- llvm/trunk/lib/Target/Sparc/SparcTargetAsmInfo.h (original)
+++ llvm/trunk/lib/Target/Sparc/SparcTargetAsmInfo.h Tue Sep 25 15:27:06 2007
@@ -22,7 +22,7 @@
class SparcTargetMachine;
struct SparcTargetAsmInfo : public TargetAsmInfo {
-SparcTargetAsmInfo(const SparcTargetMachine TM);
+explicit SparcTargetAsmInfo(const SparcTargetMachine TM);
};
Modified: llvm/trunk/lib/Target/X86/X86TargetAsmInfo.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetAsmInfo.h?rev=42316r1=42315r2=42316view=diff
==
---
[llvm-commits] [llvm] r42261 - /llvm/trunk/include/llvm/Instructions.h
Author: djg
Date: Mon Sep 24 10:46:02 2007
New Revision: 42261
URL: http://llvm.org/viewvc/llvm-project?rev=42261view=rev
Log:
Remove an unnecessary static_cast.
Modified:
llvm/trunk/include/llvm/Instructions.h
Modified: llvm/trunk/include/llvm/Instructions.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Instructions.h?rev=42261r1=42260r2=42261view=diff
==
--- llvm/trunk/include/llvm/Instructions.h (original)
+++ llvm/trunk/include/llvm/Instructions.h Mon Sep 24 10:46:02 2007
@@ -917,7 +917,7 @@
/// if it is a direct call. If it is a call through a function pointer,
/// return null.
Function *getCalledFunction() const {
-return static_castFunction*(dyn_castFunction(getOperand(0)));
+return dyn_castFunction(getOperand(0));
}
/// getCalledValue - Get a pointer to the function that is invoked by this
___
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[llvm-commits] [llvm] r42262 - in /llvm/trunk: include/llvm/CodeGen/MachineModuleInfo.h lib/Transforms/Scalar/GVNPRE.cpp
Author: djg
Date: Mon Sep 24 10:48:49 2007
New Revision: 42262
URL: http://llvm.org/viewvc/llvm-project?rev=42262view=rev
Log:
explicit keywords.
Modified:
llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h
llvm/trunk/lib/Transforms/Scalar/GVNPRE.cpp
Modified: llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h?rev=42262r1=42261r2=42262view=diff
==
--- llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h Mon Sep 24 10:48:49 2007
@@ -161,7 +161,7 @@
public:
AnchorDesc();
- AnchorDesc(AnchoredDesc *D);
+ explicit AnchorDesc(AnchoredDesc *D);
// Accessors
unsigned getAnchorTag() const { return AnchorTag; }
@@ -201,7 +201,7 @@
protected:
- AnchoredDesc(unsigned T);
+ explicit AnchoredDesc(unsigned T);
public:
// Accessors.
@@ -291,7 +291,7 @@
unsigned Flags; // Miscellaneous flags.
public:
- TypeDesc(unsigned T);
+ explicit TypeDesc(unsigned T);
// Accessors
DebugInfoDesc *getContext()const { return Context; }
@@ -382,7 +382,7 @@
DebugInfoDesc *FromType; // Type derived from.
public:
- DerivedTypeDesc(unsigned T);
+ explicit DerivedTypeDesc(unsigned T);
// Accessors
TypeDesc *getFromType() const {
@@ -421,7 +421,7 @@
std::vectorDebugInfoDesc * Elements;// Information used to compose type.
public:
- CompositeTypeDesc(unsigned T);
+ explicit CompositeTypeDesc(unsigned T);
// Accessors
std::vectorDebugInfoDesc * getElements() { return Elements; }
@@ -536,7 +536,7 @@
DebugInfoDesc *TyDesc;// Type of variable.
public:
- VariableDesc(unsigned T);
+ explicit VariableDesc(unsigned T);
// Accessors
DebugInfoDesc *getContext()const { return Context; }
@@ -595,7 +595,7 @@
bool IsDefinition;// Is the global defined in context.
protected:
- GlobalDesc(unsigned T);
+ explicit GlobalDesc(unsigned T);
public:
// Accessors
@@ -962,7 +962,7 @@
Function *Personality;// Personality function.
std::vectorint TypeIds; // List of type ids (filters negative)
- LandingPadInfo(MachineBasicBlock *MBB)
+ explicit LandingPadInfo(MachineBasicBlock *MBB)
: LandingPadBlock(MBB)
, LandingPadLabel(0)
, Personality(NULL)
Modified: llvm/trunk/lib/Transforms/Scalar/GVNPRE.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/GVNPRE.cpp?rev=42262r1=42261r2=42262view=diff
==
--- llvm/trunk/lib/Transforms/Scalar/GVNPRE.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/GVNPRE.cpp Mon Sep 24 10:48:49 2007
@@ -70,7 +70,7 @@
SmallVectoruint32_t, 4 varargs;
Expression() { }
- Expression(ExpressionOpcode o) : opcode(o) { }
+ explicit Expression(ExpressionOpcode o) : opcode(o) { }
bool operator==(const Expression other) const {
if (opcode != other.opcode)
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[llvm-commits] [llvm] r42263 - /llvm/trunk/test/CodeGen/Generic/fwdtwice.ll
Author: djg Date: Mon Sep 24 10:50:11 2007 New Revision: 42263 URL: http://llvm.org/viewvc/llvm-project?rev=42263view=rev Log: Fix a typo in a comment. Modified: llvm/trunk/test/CodeGen/Generic/fwdtwice.ll Modified: llvm/trunk/test/CodeGen/Generic/fwdtwice.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/fwdtwice.ll?rev=42263r1=42262r2=42263view=diff == --- llvm/trunk/test/CodeGen/Generic/fwdtwice.ll (original) +++ llvm/trunk/test/CodeGen/Generic/fwdtwice.ll Mon Sep 24 10:50:11 2007 @@ -4,7 +4,7 @@ ;; Test the sequence: ;; cast - setle 0, %cast - br %cond ;; This sequence should cause the cast value to be forwarded twice, -;; i.e., cast is forwarded to the setle and teh setle is forwarded +;; i.e., cast is forwarded to the setle and the setle is forwarded ;; to the branch. ;; register argument of the branch-on-register instruction, i.e., ;; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r42264 - in /llvm/trunk: lib/CodeGen/SelectionDAG/LegalizeDAG.cpp test/CodeGen/X86/extractelement-from-arg.ll
Author: djg
Date: Mon Sep 24 10:54:53 2007
New Revision: 42264
URL: http://llvm.org/viewvc/llvm-project?rev=42264view=rev
Log:
Use the correct result value type instead of using getValueType(0)
in ExpandEXTRACT_VECTOR_ELT and SplitVectorOp. This fixes an abort
in the included testcase.
Added:
llvm/trunk/test/CodeGen/X86/extractelement-from-arg.ll
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=42264r1=42263r2=42264view=diff
==
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Sep 24 10:54:53 2007
@@ -3870,8 +3870,7 @@
SDOperand Vec = Op.getOperand(0);
SDOperand Idx = Op.getOperand(1);
- SDNode *InVal = Vec.Val;
- MVT::ValueType TVT = InVal-getValueType(0);
+ MVT::ValueType TVT = Vec.getValueType();
unsigned NumElems = MVT::getVectorNumElements(TVT);
switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
@@ -5803,10 +5802,10 @@
SDOperand Hi) {
assert(MVT::isVector(Op.getValueType()) Cannot split non-vector type!);
SDNode *Node = Op.Val;
- unsigned NumElements = MVT::getVectorNumElements(Node-getValueType(0));
+ unsigned NumElements = MVT::getVectorNumElements(Op.getValueType());
assert(NumElements 1 Cannot split a single element vector!);
unsigned NewNumElts = NumElements/2;
- MVT::ValueType NewEltVT = MVT::getVectorElementType(Node-getValueType(0));
+ MVT::ValueType NewEltVT = MVT::getVectorElementType(Op.getValueType());
MVT::ValueType NewVT = MVT::getVectorType(NewEltVT, NewNumElts);
// See if we already split it.
Added: llvm/trunk/test/CodeGen/X86/extractelement-from-arg.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/extractelement-from-arg.ll?rev=42264view=auto
==
--- llvm/trunk/test/CodeGen/X86/extractelement-from-arg.ll (added)
+++ llvm/trunk/test/CodeGen/X86/extractelement-from-arg.ll Mon Sep 24 10:54:53
2007
@@ -0,0 +1,7 @@
+; RUN: llvm-as %s -o - | llc -march=x86-64
+
+define void @test(float* %R, 4 x float %X) {
+ %tmp = extractelement 4 x float %X, i32 3
+ store float %tmp, float* %R
+ ret void
+}
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[llvm-commits] [llvm] r42265 - /llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
Author: djg
Date: Mon Sep 24 11:44:26 2007
New Revision: 42265
URL: http://llvm.org/viewvc/llvm-project?rev=42265view=rev
Log:
The code that used the StartLabelId label was removed, so remove the
code that creates the label too.
Modified:
llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=42265r1=42264r2=42265view=diff
==
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Mon Sep 24 11:44:26 2007
@@ -1278,18 +1278,12 @@
MachineBasicBlock::iterator MBBI = MBB.begin();
// Prepare for frame info.
- unsigned FrameLabelId = 0, StartLabelId = 0;
+ unsigned FrameLabelId = 0;
// Get the number of bytes to allocate from the FrameInfo
uint64_t StackSize = MFI-getStackSize();
uint64_t NumBytes = StackSize - X86FI-getCalleeSavedFrameSize();
- if (MMI MMI-needsFrameInfo()) {
-// Mark function start
-StartLabelId = MMI-NextLabelID();
-BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(StartLabelId);
- }
-
if (hasFP(MF)) {
// Get the offset of the stack slot for the EBP register... which is
// guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
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[llvm-commits] [llvm] r42268 - /llvm/trunk/lib/Target/X86/X86InstrInfo.td
Author: djg
Date: Mon Sep 24 14:25:06 2007
New Revision: 42268
URL: http://llvm.org/viewvc/llvm-project?rev=42268view=rev
Log:
Fix the syntax for the .loc directive in preparation for using it.
Modified:
llvm/trunk/lib/Target/X86/X86InstrInfo.td
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=42268r1=42267r2=42268view=diff
==
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Mon Sep 24 14:25:06 2007
@@ -2434,7 +2434,7 @@
def DWARF_LOC : I0, Pseudo, (outs),
(ins i32imm:$line, i32imm:$col, i32imm:$file),
-; .loc ${file:debug}, ${line:debug}, ${col:debug},
+.loc\t${file:debug} ${line:debug} ${col:debug},
[(dwarf_loc (i32 imm:$line), (i32 imm:$col),
(i32 imm:$file))];
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Re: [llvm-commits] [llvm] r42270 - in /llvm/trunk: lib/Transforms/Scalar/LICM.cpp test/Transforms/LICM/2007-09-24-PromoteNullValue.ll
Do not promote null values because it may be unsafe to do so. Interesting. See our earlier discussion on LICM checking for NULL constants :-}. Dan -- Dan Gohman, Cray Inc. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r42272 - in /llvm/trunk: include/llvm/CodeGen/AsmPrinter.h lib/CodeGen/AsmPrinter.cpp
Author: djg
Date: Mon Sep 24 15:58:13 2007
New Revision: 42272
URL: http://llvm.org/viewvc/llvm-project?rev=42272view=rev
Log:
Add a routine for emitting .file directives, for setting up
file numbers to use with .loc directives.
Modified:
llvm/trunk/include/llvm/CodeGen/AsmPrinter.h
llvm/trunk/lib/CodeGen/AsmPrinter.cpp
Modified: llvm/trunk/include/llvm/CodeGen/AsmPrinter.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/AsmPrinter.h?rev=42272r1=42271r2=42272view=diff
==
--- llvm/trunk/include/llvm/CodeGen/AsmPrinter.h (original)
+++ llvm/trunk/include/llvm/CodeGen/AsmPrinter.h Mon Sep 24 15:58:13 2007
@@ -248,6 +248,9 @@
/// @verbatim (Eg. '\t') @endverbatim
void EmitString(const std::string String) const;
+/// EmitFile - Emit a .file directive.
+void EmitFile(unsigned Number, const std::string Name) const;
+
//===--===//
/// EmitAlignment - Emit an alignment directive to the specified power of
Modified: llvm/trunk/lib/CodeGen/AsmPrinter.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter.cpp?rev=42272r1=42271r2=42272view=diff
==
--- llvm/trunk/lib/CodeGen/AsmPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter.cpp Mon Sep 24 15:58:13 2007
@@ -618,6 +618,17 @@
}
+/// EmitFile - Emit a .file directive.
+void AsmPrinter::EmitFile(unsigned Number, const std::string Name) const {
+ O \t.file\t Number \;
+ for (unsigned i = 0, N = Name.size(); i N; ++i) {
+unsigned char C = Name[i];
+printStringChar(O, C);
+ }
+ O \;
+}
+
+
//===--===//
// EmitAlignment - Emit an alignment directive to the specified power of
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[llvm-commits] [llvm] r42274 - in /llvm/trunk: include/llvm/Target/TargetAsmInfo.h lib/Target/TargetAsmInfo.cpp
Author: djg
Date: Mon Sep 24 16:09:53 2007
New Revision: 42274
URL: http://llvm.org/viewvc/llvm-project?rev=42274view=rev
Log:
Merge hasDotLoc and hasDotFile into hasDotLocAndDotFile since .loc and .file
aren't really usable without each other.
Modified:
llvm/trunk/include/llvm/Target/TargetAsmInfo.h
llvm/trunk/lib/Target/TargetAsmInfo.cpp
Modified: llvm/trunk/include/llvm/Target/TargetAsmInfo.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetAsmInfo.h?rev=42274r1=42273r2=42274view=diff
==
--- llvm/trunk/include/llvm/Target/TargetAsmInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetAsmInfo.h Mon Sep 24 16:09:53 2007
@@ -286,14 +286,11 @@
///
bool HasLEB128; // Defaults to false.
-/// hasDotLoc - True if target asm supports .loc directives.
+/// hasDotLocAndDotFile - True if target asm supports .loc and .file
+/// directives for emitting debugging information.
///
-bool HasDotLoc; // Defaults to false.
+bool HasDotLocAndDotFile; // Defaults to false.
-/// HasDotFile - True if target asm supports .file directives.
-///
-bool HasDotFile; // Defaults to false.
-
/// SupportsDebugInformation - True if target supports emission of
debugging
/// information.
bool SupportsDebugInformation;
@@ -568,11 +565,8 @@
bool hasLEB128() const {
return HasLEB128;
}
-bool hasDotLoc() const {
- return HasDotLoc;
-}
-bool hasDotFile() const {
- return HasDotFile;
+bool hasDotLocAndDotFile() const {
+ return HasDotLocAndDotFile;
}
bool doesSupportDebugInformation() const {
return SupportsDebugInformation;
Modified: llvm/trunk/lib/Target/TargetAsmInfo.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetAsmInfo.cpp?rev=42274r1=42273r2=42274view=diff
==
--- llvm/trunk/lib/Target/TargetAsmInfo.cpp (original)
+++ llvm/trunk/lib/Target/TargetAsmInfo.cpp Mon Sep 24 16:09:53 2007
@@ -81,8 +81,7 @@
AbsoluteDebugSectionOffsets(false),
AbsoluteEHSectionOffsets(false),
HasLEB128(false),
- HasDotLoc(false),
- HasDotFile(false),
+ HasDotLocAndDotFile(false),
SupportsDebugInformation(false),
SupportsExceptionHandling(false),
DwarfRequiresFrameSection(true),
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[llvm-commits] [llvm] r42275 - /llvm/trunk/lib/CodeGen/DwarfWriter.cpp
Author: djg
Date: Mon Sep 24 16:32:18 2007
New Revision: 42275
URL: http://llvm.org/viewvc/llvm-project?rev=42275view=rev
Log:
Add support for emitting .file directives to set up file numbers for
use with .loc directives.
Modified:
llvm/trunk/lib/CodeGen/DwarfWriter.cpp
Modified: llvm/trunk/lib/CodeGen/DwarfWriter.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/DwarfWriter.cpp?rev=42275r1=42274r2=42275view=diff
==
--- llvm/trunk/lib/CodeGen/DwarfWriter.cpp (original)
+++ llvm/trunk/lib/CodeGen/DwarfWriter.cpp Mon Sep 24 16:32:18 2007
@@ -28,6 +28,7 @@
#include llvm/Support/CommandLine.h
#include llvm/Support/DataTypes.h
#include llvm/Support/Mangler.h
+#include llvm/System/Path.h
#include llvm/Target/TargetAsmInfo.h
#include llvm/Target/MRegisterInfo.h
#include llvm/Target/TargetData.h
@@ -1967,6 +1968,19 @@
if (didInitial) return;
didInitial = true;
+// Print out .file directives to specify files for .loc directives.
+if (TAI-hasDotLocAndDotFile()) {
+ const UniqueVectorSourceFileInfo SourceFiles = MMI-getSourceFiles();
+ const UniqueVectorstd::string Directories = MMI-getDirectories();
+ for (unsigned i = 1, e = SourceFiles.size(); i = e; ++i) {
+sys::Path FullPath(Directories[SourceFiles[i].getDirectoryID()]);
+bool AppendOk = FullPath.appendComponent(SourceFiles[i].getName());
+assert(AppendOk Could not append filename to directory!);
+Asm-EmitFile(i, FullPath.toString());
+Asm-EOL();
+ }
+}
+
// Dwarf sections base addresses.
if (TAI-doesDwarfRequireFrameSection()) {
Asm-SwitchToDataSection(TAI-getDwarfFrameSection());
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[llvm-commits] [llvm] r42276 - /llvm/trunk/lib/CodeGen/DwarfWriter.cpp
Author: djg Date: Mon Sep 24 16:36:21 2007 New Revision: 42276 URL: http://llvm.org/viewvc/llvm-project?rev=42276view=rev Log: Move the Asm-EOL() call for EmitDebugARanges outside the #ifdef for consistency with the other currently empty sections. Modified: llvm/trunk/lib/CodeGen/DwarfWriter.cpp Modified: llvm/trunk/lib/CodeGen/DwarfWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/DwarfWriter.cpp?rev=42276r1=42275r2=42276view=diff == --- llvm/trunk/lib/CodeGen/DwarfWriter.cpp (original) +++ llvm/trunk/lib/CodeGen/DwarfWriter.cpp Mon Sep 24 16:36:21 2007 @@ -2525,9 +2525,9 @@ Asm-EmitInt32(0); Asm-EOL(EOM (1)); Asm-EmitInt32(0); Asm-EOL(EOM (2)); + #endif Asm-EOL(); - #endif } /// EmitDebugRanges - Emit visible names into a debug ranges section. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r42277 - /llvm/trunk/lib/CodeGen/DwarfWriter.cpp
Author: djg
Date: Mon Sep 24 16:43:52 2007
New Revision: 42277
URL: http://llvm.org/viewvc/llvm-project?rev=42277view=rev
Log:
Don't emit .debug_line header data if there aren't any lines to put in it,
such as will happen when .loc directives are used.
Modified:
llvm/trunk/lib/CodeGen/DwarfWriter.cpp
Modified: llvm/trunk/lib/CodeGen/DwarfWriter.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/DwarfWriter.cpp?rev=42277r1=42276r2=42277view=diff
==
--- llvm/trunk/lib/CodeGen/DwarfWriter.cpp (original)
+++ llvm/trunk/lib/CodeGen/DwarfWriter.cpp Mon Sep 24 16:43:52 2007
@@ -2196,6 +2196,11 @@
/// EmitDebugLines - Emit source line information.
///
void EmitDebugLines() {
+// If there are no lines to emit (such as when we're using .loc directives
+// to emit .debug_line information) don't emit a .debug_line header.
+if (SectionSourceLines.empty())
+ return;
+
// Minimum line delta, thus ranging from -10..(255-10).
const int MinLineDelta = -(DW_LNS_fixed_advance_pc + 1);
// Maximum line delta, thus ranging from -10..(255-10).
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[llvm-commits] [llvm] r42278 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Author: djg Date: Mon Sep 24 16:54:14 2007 New Revision: 42278 URL: http://llvm.org/viewvc/llvm-project?rev=42278view=rev Log: Add support on x86 for having Legalize lower ISD::LOCATION to ISD::DEBUG_LOC instead of ISD::LABEL with a manual .debug_line entry when the assembler supports .file and .loc directives. Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=42278r1=42277r2=42278view=diff == --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Sep 24 16:54:14 2007 @@ -32,6 +32,7 @@ #include llvm/CodeGen/SelectionDAG.h #include llvm/CodeGen/SSARegMap.h #include llvm/Support/MathExtras.h +#include llvm/Target/TargetAsmInfo.h #include llvm/Target/TargetOptions.h #include llvm/ADT/StringExtras.h #include llvm/ParameterAttributes.h @@ -229,9 +230,13 @@ setOperationAction(ISD::MEMSET , MVT::Other, Custom); setOperationAction(ISD::MEMCPY , MVT::Other, Custom); - // We don't have line number support yet. + // Use the default ISD::LOCATION expansion, and tell Legalize it's + // ok to use DEBUG_LOC if we have an assembler that supports it. setOperationAction(ISD::LOCATION, MVT::Other, Expand); - setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); + if (TM.getTargetAsmInfo()-hasDotLocAndDotFile()) +setOperationAction(ISD::DEBUG_LOC, MVT::Other, Legal); + else +setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); // FIXME - use subtarget debug flags if (!Subtarget-isTargetDarwin() !Subtarget-isTargetELF() ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r42190 - /llvm/trunk/include/llvm/IntrinsicsX86.td
Author: djg
Date: Fri Sep 21 10:24:00 2007
New Revision: 42190
URL: http://llvm.org/viewvc/llvm-project?rev=42190view=rev
Log:
There is no {rsqrt,rcp}{p,s}d.
Modified:
llvm/trunk/include/llvm/IntrinsicsX86.td
Modified: llvm/trunk/include/llvm/IntrinsicsX86.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsX86.td?rev=42190r1=42189r2=42190view=diff
==
--- llvm/trunk/include/llvm/IntrinsicsX86.td (original)
+++ llvm/trunk/include/llvm/IntrinsicsX86.td Fri Sep 21 10:24:00 2007
@@ -185,18 +185,6 @@
def int_x86_sse2_sqrt_pd : GCCBuiltin__builtin_ia32_sqrtpd,
Intrinsic[llvm_v2f64_ty, llvm_v2f64_ty],
[IntrNoMem];
- def int_x86_sse2_rcp_sd : GCCBuiltin__builtin_ia32_rcpsd,
- Intrinsic[llvm_v2f64_ty, llvm_v2f64_ty],
-[IntrNoMem];
- def int_x86_sse2_rcp_pd : GCCBuiltin__builtin_ia32_rcppd,
- Intrinsic[llvm_v2f64_ty, llvm_v2f64_ty],
-[IntrNoMem];
- def int_x86_sse2_rsqrt_sd : GCCBuiltin__builtin_ia32_rsqrtsd,
- Intrinsic[llvm_v2f64_ty, llvm_v2f64_ty],
-[IntrNoMem];
- def int_x86_sse2_rsqrt_pd : GCCBuiltin__builtin_ia32_rsqrtpd,
- Intrinsic[llvm_v2f64_ty, llvm_v2f64_ty],
-[IntrNoMem];
def int_x86_sse2_min_sd : GCCBuiltin__builtin_ia32_minsd,
Intrinsic[llvm_v2f64_ty, llvm_v2f64_ty,
llvm_v2f64_ty], [IntrNoMem];
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[llvm-commits] [llvm] r42162 - in /llvm/trunk: lib/Target/X86/X86RegisterInfo.cpp test/CodeGen/X86/sse_reload_fold.ll
Author: djg
Date: Thu Sep 20 09:17:21 2007
New Revision: 42162
URL: http://llvm.org/viewvc/llvm-project?rev=42162view=rev
Log:
Fix several more entries in the x86 reload/remat folding tables.
Added:
llvm/trunk/test/CodeGen/X86/sse_reload_fold.ll
Modified:
llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=42162r1=42161r2=42162view=diff
==
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Thu Sep 20 09:17:21 2007
@@ -711,10 +711,6 @@
{ X86::CMP32rr, X86::CMP32rm },
{ X86::CMP64rr, X86::CMP64rm },
{ X86::CMP8rr, X86::CMP8rm },
- { X86::CMPPDrri,X86::CMPPDrmi },
- { X86::CMPPSrri,X86::CMPPSrmi },
- { X86::CMPSDrr, X86::CMPSDrm },
- { X86::CMPSSrr, X86::CMPSSrm },
{ X86::CVTSD2SSrr, X86::CVTSD2SSrm },
{ X86::CVTSI2SD64rr,X86::CVTSI2SD64rm },
{ X86::CVTSI2SDrr, X86::CVTSI2SDrm },
@@ -795,6 +791,20 @@
{ X86::PSHUFHWri, X86::PSHUFHWmi },
{ X86::PSHUFLWri, X86::PSHUFLWmi },
{ X86::PsMOVZX64rr32, X86::PsMOVZX64rm32 },
+ { X86::RCPPSr, X86::RCPPSm },
+ { X86::RCPPSr_Int, X86::RCPPSm_Int },
+ { X86::RSQRTPSr,X86::RSQRTPSm },
+ { X86::RSQRTPSr_Int,X86::RSQRTPSm_Int },
+ { X86::RSQRTSSr,X86::RSQRTSSm },
+ { X86::RSQRTSSr_Int,X86::RSQRTSSm_Int },
+ { X86::SQRTPDr, X86::SQRTPDm },
+ { X86::SQRTPDr_Int, X86::SQRTPDm_Int },
+ { X86::SQRTPSr, X86::SQRTPSm },
+ { X86::SQRTPSr_Int, X86::SQRTPSm_Int },
+ { X86::SQRTSDr, X86::SQRTSDm },
+ { X86::SQRTSDr_Int, X86::SQRTSDm_Int },
+ { X86::SQRTSSr, X86::SQRTSSm },
+ { X86::SQRTSSr_Int, X86::SQRTSSm_Int },
{ X86::TEST16rr,X86::TEST16rm },
{ X86::TEST32rr,X86::TEST32rm },
{ X86::TEST64rr,X86::TEST64rm },
@@ -875,6 +885,10 @@
{ X86::CMOVS16rr, X86::CMOVS16rm },
{ X86::CMOVS32rr, X86::CMOVS32rm },
{ X86::CMOVS64rr, X86::CMOVS64rm },
+ { X86::CMPPDrri,X86::CMPPDrmi },
+ { X86::CMPPSrri,X86::CMPPSrmi },
+ { X86::CMPSDrr, X86::CMPSDrm },
+ { X86::CMPSSrr, X86::CMPSSrm },
{ X86::DIVPDrr, X86::DIVPDrm },
{ X86::DIVPSrr, X86::DIVPSrm },
{ X86::DIVSDrr, X86::DIVSDrm },
@@ -965,24 +979,10 @@
{ X86::PUNPCKLQDQrr,X86::PUNPCKLQDQrm },
{ X86::PUNPCKLWDrr, X86::PUNPCKLWDrm },
{ X86::PXORrr, X86::PXORrm },
- { X86::RCPPSr, X86::RCPPSm },
- { X86::RCPPSr_Int, X86::RCPPSm_Int },
- { X86::RSQRTPSr,X86::RSQRTPSm },
- { X86::RSQRTPSr_Int,X86::RSQRTPSm_Int },
- { X86::RSQRTSSr,X86::RSQRTSSm },
- { X86::RSQRTSSr_Int,X86::RSQRTSSm_Int },
{ X86::SBB32rr, X86::SBB32rm },
{ X86::SBB64rr, X86::SBB64rm },
{ X86::SHUFPDrri, X86::SHUFPDrmi },
{ X86::SHUFPSrri, X86::SHUFPSrmi },
- { X86::SQRTPDr, X86::SQRTPDm },
- { X86::SQRTPDr_Int, X86::SQRTPDm_Int },
- { X86::SQRTPSr, X86::SQRTPSm },
- { X86::SQRTPSr_Int, X86::SQRTPSm_Int },
- { X86::SQRTSDr, X86::SQRTSDm },
- { X86::SQRTSDr_Int, X86::SQRTSDm_Int },
- { X86::SQRTSSr, X86::SQRTSSm },
- { X86::SQRTSSr_Int, X86::SQRTSSm_Int },
{ X86::SUB16rr, X86::SUB16rm },
{ X86::SUB32rr, X86::SUB32rm },
{ X86::SUB64rr, X86::SUB64rm },
Added: llvm/trunk/test/CodeGen/X86/sse_reload_fold.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse_reload_fold.ll?rev=42162view=auto
==
--- llvm/trunk/test/CodeGen/X86/sse_reload_fold.ll (added)
+++ llvm/trunk/test/CodeGen/X86/sse_reload_fold.ll Thu Sep 20 09:17:21 2007
@@ -0,0 +1,124 @@
+; RUN: llvm-as %s | \
+; RUN: llc -march=x86-64 -mattr=+64bit,+sse3 -print-failed-fuse-candidates | \
+; RUN: grep fail | count 1
+
+declare void @bar()
+declare 4 x float @qux()
+declare 2 x double @pin()
+declare float @llvm.sqrt.f32(float)
+declare double @llvm.sqrt.f64(double)
+
+declare 4 x float @llvm.x86.sse.rsqrt.ps(4 x float)
+declare 4 x float @llvm.x86.sse.sqrt.ps(4 x float)
+declare 4 x float @llvm.x86.sse.rcp.ps(4 x float)
+declare 4 x float @llvm.x86.sse.min.ps(4 x float, 4 x float)
+declare 4 x float @llvm.x86.sse.max.ps(4 x float, 4 x float)
+declare 4 x float @llvm.x86.sse.cmp.ps(4 x float, 4 x float, i8)
+declare 4 x float @llvm.x86.sse3.addsub.ps(4 x float, 4 x
Re: [llvm-commits] [llvm] r42075 - in /llvm/trunk: lib/Transforms/Scalar/LICM.cpp test/Transforms/LICM/2007-09-17-PrompteValue.ll
Exactly, that's what I meant to say when I said when loop
conditionals are runtime dependent. To ensure safety in
PromoteValuesInLoop(), one needs to prove that basic-block is executed
at least once. The question is how ?
The most general way to do this is to convert loops like this:
while (x) {
body;
}
to this:
if (x) {
do {
body;
} while (x);
}
In the second form, code hoisted/sunk/promoted out of the loop will
still be under the guard of the if. Also see tree-ssa-loop-ch.c in GCC,
for example.
Dan
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Re: [llvm-commits] [llvm] r42075 - in /llvm/trunk: lib/Transforms/Scalar/LICM.cpp test/Transforms/LICM/2007-09-17-PrompteValue.ll
+ // If GEP base is NULL then the calculated address used by Store or + // Load instruction is invalid. Do not promote this value because + // it may expose load and store instruction that are covered by + // condition which may not yet folded. + if (GetElementPtrInst *GEP = dyn_castGetElementPtrInst(V)) +if (isaConstantPointerNull(GEP-getOperand(0))) + PointerOk = false; + It looks like there's a larger problem here. The testcase's loop body may never be executed, so it isn't safe for LICM to hoist/sink anything out to an unguarded location, null pointer constants or otherwise. Dan -- Dan Gohman, Cray Inc. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r42094 - /llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
Author: djg
Date: Tue Sep 18 09:59:14 2007
New Revision: 42094
URL: http://llvm.org/viewvc/llvm-project?rev=42094view=rev
Log:
Move the entries for 64-bit CMP, IMUL, and a few others into the correct
tables so that they are eligible for reload/remat folding. And add
entries for JMP and CALL.
Modified:
llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=42094r1=42093r2=42094view=diff
==
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Tue Sep 18 09:59:14 2007
@@ -629,10 +629,14 @@
}
static const TableEntry OpcodeTable[] = {
+ { X86::CALL32r, X86::CALL32m },
+ { X86::CALL64r, X86::CALL64m },
{ X86::CMP16ri, X86::CMP16mi },
{ X86::CMP16ri8,X86::CMP16mi8 },
{ X86::CMP32ri, X86::CMP32mi },
{ X86::CMP32ri8,X86::CMP32mi8 },
+ { X86::CMP64ri32, X86::CMP64mi32 },
+ { X86::CMP64ri8,X86::CMP64mi8 },
{ X86::CMP8ri, X86::CMP8mi },
{ X86::DIV16r, X86::DIV16m },
{ X86::DIV32r, X86::DIV32m },
@@ -648,6 +652,8 @@
{ X86::IMUL32r, X86::IMUL32m },
{ X86::IMUL64r, X86::IMUL64m },
{ X86::IMUL8r, X86::IMUL8m },
+ { X86::JMP32r, X86::JMP32m },
+ { X86::JMP64r, X86::JMP64m },
{ X86::MOV16ri, X86::MOV16mi },
{ X86::MOV16rr, X86::MOV16mr },
{ X86::MOV32ri, X86::MOV32mi },
@@ -671,6 +677,9 @@
{ X86::MUL32r, X86::MUL32m },
{ X86::MUL64r, X86::MUL64m },
{ X86::MUL8r, X86::MUL8m },
+ { X86::PSHUFDri,X86::PSHUFDmi },
+ { X86::PSHUFHWri, X86::PSHUFHWmi },
+ { X86::PSHUFLWri, X86::PSHUFLWmi },
{ X86::SETAEr, X86::SETAEm },
{ X86::SETAr, X86::SETAm },
{ X86::SETBEr, X86::SETBEm },
@@ -685,6 +694,7 @@
{ X86::SETNSr, X86::SETNSm },
{ X86::SETPr, X86::SETPm },
{ X86::SETSr, X86::SETSm },
+ { X86::TAILJMPr,X86::TAILJMPm },
{ X86::TEST16ri,X86::TEST16mi },
{ X86::TEST32ri,X86::TEST32mi },
{ X86::TEST64ri32, X86::TEST64mi32 },
@@ -702,8 +712,6 @@
static const TableEntry OpcodeTable[] = {
{ X86::CMP16rr, X86::CMP16rm },
{ X86::CMP32rr, X86::CMP32rm },
- { X86::CMP64ri32, X86::CMP64mi32 },
- { X86::CMP64ri8,X86::CMP64mi8 },
{ X86::CMP64rr, X86::CMP64rm },
{ X86::CMP8rr, X86::CMP8rm },
{ X86::CMPPDrri,X86::CMPPDrmi },
@@ -726,7 +734,6 @@
{ X86::IMUL16rri8, X86::IMUL16rmi8 },
{ X86::IMUL32rri, X86::IMUL32rmi },
{ X86::IMUL32rri8, X86::IMUL32rmi8 },
- { X86::IMUL64rr,X86::IMUL64rm },
{ X86::IMUL64rri32, X86::IMUL64rmi32 },
{ X86::IMUL64rri8, X86::IMUL64rmi8 },
{ X86::Int_CMPSDrr, X86::Int_CMPSDrm },
@@ -787,9 +794,6 @@
{ X86::MOVZX32rr8, X86::MOVZX32rm8 },
{ X86::MOVZX64rr16, X86::MOVZX64rm16 },
{ X86::MOVZX64rr8, X86::MOVZX64rm8 },
- { X86::PSHUFDri,X86::PSHUFDmi },
- { X86::PSHUFHWri, X86::PSHUFHWmi },
- { X86::PSHUFLWri, X86::PSHUFLWmi },
{ X86::PsMOVZX64rr32, X86::PsMOVZX64rm32 },
{ X86::TEST16rr,X86::TEST16rm },
{ X86::TEST32rr,X86::TEST32rm },
@@ -881,6 +885,7 @@
{ X86::HSUBPSrr,X86::HSUBPSrm },
{ X86::IMUL16rr,X86::IMUL16rm },
{ X86::IMUL32rr,X86::IMUL32rm },
+ { X86::IMUL64rr,X86::IMUL64rm },
{ X86::MAXPDrr, X86::MAXPDrm },
{ X86::MAXPDrr_Int, X86::MAXPDrm_Int },
{ X86::MAXPSrr, X86::MAXPSrm },
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Re: [llvm-commits] [llvm] r42075 - in /llvm/trunk: lib/Transforms/Scalar/LICM.cpp test/Transforms/LICM/2007-09-17-PrompteValue.ll
We intend to split LICM into three passes - sink, hoist and promote-
values. Irrespective of sinking and hoisting, promote-values should
not promote values that are unsafe. Avoiding hoisting GEP here will
solve this test case, but promote-values bug will be exposed when it
is supplied manually hoisted GEP.
promote-values is not in business to identify dead loops. And when
loop conditionals are runtime dependent it is not possible to
determine it at compile time at all. The fix is to check unsafe stores
and loads before promoting value.
I don't quite follow. For example of what I'm saying, take this
testcase, which is only slightly different than the earlier one:
define i32 @foo(%struct.decision* %p) {
entry:
br label %blah.i
blah.i:; preds = %cond_true.i, %entry
%tmp3.i = icmp eq %struct.decision* null, null ; i1 [#uses=1]
br i1 %tmp3.i, label %clear_modes.exit, label %cond_true.i
cond_true.i: ; preds = %blah.i
%tmp1.i = getelementptr %struct.decision* %p, i32 0, i32 0;
i8* [#uses=1]
store i8 0, i8* %tmp1.i
br label %blah.i
clear_modes.exit: ; preds = %blah.i
call void @exit( i32 0 )
unreachable
}
declare void @exit(i32)
Even with the latest changes, LICM puts a load of %tmp1.i in the
entry block, which isn't safe.
Dan
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Re: [llvm-commits] [llvm] r42075 - in /llvm/trunk: lib/Transforms/Scalar/LICM.cpp test/Transforms/LICM/2007-09-17-PrompteValue.ll
It is not safe, because cond_true.i is a dead basic-block. The
question is -- Is it LICM's responsibility to evaluate conditions and
identify dead code or let other passes handle this earlier?. For
example here, instruction combiner will fold comparison and cfg
simplifier will take care of cond_true.i before LICM is executed in
standard pass sequence.
Ok, so let's tweak the testcase again:
define i32 @foo(%struct.decision* %p, %struct.decision* %q) {
entry:
br label %blah.i
blah.i:; preds = %cond_true.i, %entry
%tmp3.i = icmp eq %struct.decision* null, %q ; i1 [#uses=1]
br i1 %tmp3.i, label %clear_modes.exit, label %cond_true.i
cond_true.i: ; preds = %blah.i
%tmp1.i = getelementptr %struct.decision* %p, i32 0, i32 0;
i8* [#uses=1]
store i8 0, i8* %tmp1.i
br label %blah.i
clear_modes.exit: ; preds = %blah.i
call void @exit( i32 0 )
unreachable
}
declare void @exit(i32)
It's no longer possible for any part of the optimizer to prove the loop
is dead. LICM is still putting a load of %tmp1.i in the entry block for
this test, and that's unsafe.
Dan
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[llvm-commits] [llvm] r42024 - in /llvm/trunk: lib/Target/X86/X86InstrX86-64.td test/CodeGen/X86/cmp0.ll
Author: djg
Date: Mon Sep 17 09:35:24 2007
New Revision: 42024
URL: http://llvm.org/viewvc/llvm-project?rev=42024view=rev
Log:
Use test reg,reg in place of cmp reg,0 for 64-bit operands. This was
previously only done for 32-bit and smaller operands.
Added:
llvm/trunk/test/CodeGen/X86/cmp0.ll
Modified:
llvm/trunk/lib/Target/X86/X86InstrX86-64.td
Modified: llvm/trunk/lib/Target/X86/X86InstrX86-64.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrX86-64.td?rev=42024r1=42023r2=42024view=diff
==
--- llvm/trunk/lib/Target/X86/X86InstrX86-64.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrX86-64.td Mon Sep 17 09:35:24 2007
@@ -1076,6 +1076,12 @@
def : Pat(X86tailcall GR64:$dst),
(CALL64r GR64:$dst);
+// Comparisons.
+
+// TEST R,R is smaller than CMP R,0
+def : Pat(X86cmp GR64:$src1, 0),
+ (TEST64rr GR64:$src1, GR64:$src1);
+
// {s|z}extload bool - {s|z}extload byte
def : Pat(sextloadi64i1 addr:$src), (MOVSX64rm8 addr:$src);
def : Pat(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src);
Added: llvm/trunk/test/CodeGen/X86/cmp0.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/cmp0.ll?rev=42024view=auto
==
--- llvm/trunk/test/CodeGen/X86/cmp0.ll (added)
+++ llvm/trunk/test/CodeGen/X86/cmp0.ll Mon Sep 17 09:35:24 2007
@@ -0,0 +1,7 @@
+; RUN: llvm-as %s | llc -march=x86-64 | grep -v cmp
+
+define i64 @foo(i64 %x) {
+ %t = icmp eq i64 %x, 0
+ %r = zext i1 %t to i64
+ ret i64 %r
+}
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[llvm-commits] [llvm] r42026 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/cmp1.ll
Author: djg
Date: Mon Sep 17 09:49:27 2007
New Revision: 42026
URL: http://llvm.org/viewvc/llvm-project?rev=42026view=rev
Log:
Emit integer x1 as x=0, as comparisons with zero (now includeing
64-bit) can use test instead of cmp with an immediate.
Added:
llvm/trunk/test/CodeGen/X86/cmp1.ll
Modified:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=42026r1=42025r2=42026view=diff
==
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Sep 17 09:49:27 2007
@@ -1546,6 +1546,11 @@
// X 0 - X == 0, jump on sign.
X86CC = X86::COND_S;
return true;
+ } else if (SetCCOpcode == ISD::SETLT RHSC-getValue() == 1) {
+// X 1 - X = 0
+RHS = DAG.getConstant(0, RHS.getValueType());
+X86CC = X86::COND_LE;
+return true;
}
}
Added: llvm/trunk/test/CodeGen/X86/cmp1.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/cmp1.ll?rev=42026view=auto
==
--- llvm/trunk/test/CodeGen/X86/cmp1.ll (added)
+++ llvm/trunk/test/CodeGen/X86/cmp1.ll Mon Sep 17 09:49:27 2007
@@ -0,0 +1,7 @@
+; RUN: llvm-as %s | llc -march=x86-64 | grep -v cmp
+
+define i64 @foo(i64 %x) {
+ %t = icmp slt i64 %x, 1
+ %r = zext i1 %t to i64
+ ret i64 %r
+}
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[llvm-commits] [llvm] r42027 - /llvm/trunk/lib/Target/X86/X86InstrX86-64.td
Author: djg
Date: Mon Sep 17 09:55:08 2007
New Revision: 42027
URL: http://llvm.org/viewvc/llvm-project?rev=42027view=rev
Log:
Use xorl instead of xorq to enter a zero into a 64-bit register.
Modified:
llvm/trunk/lib/Target/X86/X86InstrX86-64.td
Modified: llvm/trunk/lib/Target/X86/X86InstrX86-64.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrX86-64.td?rev=42027r1=42026r2=42027view=diff
==
--- llvm/trunk/lib/Target/X86/X86InstrX86-64.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrX86-64.td Mon Sep 17 09:55:08 2007
@@ -1018,13 +1018,15 @@
[(set GR64:$dst, (zextloadi64i32 addr:$src))];
-// Alias instructions that map movr0 to xor.
+// Alias instructions that map movr0 to xor. Use xorl instead of xorq; it's
+// equivalent due to implicit zero-extending, and it sometimes has a smaller
+// encoding.
// FIXME: remove when we can teach regalloc that xor reg, reg is ok.
// FIXME: AddedComplexity gives MOV64r0 a higher priority than MOV64ri32.
Remove
// when we have a better way to specify isel priority.
let Defs = [EFLAGS], AddedComplexity = 1, isReMaterializable = 1 in
def MOV64r0 : RI0x31, MRMInitReg, (outs GR64:$dst), (ins),
- xor{q}\t$dst, $dst,
+ xor{l}\t${dst:subreg32}, ${dst:subreg32},
[(set GR64:$dst, 0)];
// Materialize i64 constant where top 32-bits are zero.
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[llvm-commits] [llvm] r42029 - /llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
Author: djg Date: Mon Sep 17 10:19:08 2007 New Revision: 42029 URL: http://llvm.org/viewvc/llvm-project?rev=42029view=rev Log: Add 64-bit jmp instructions to the list of instructions that can terminate a block with no fall-through. Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=42029r1=42028r2=42029view=diff == --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Mon Sep 17 10:19:08 2007 @@ -582,7 +582,9 @@ case X86::TAILJMPm: case X86::JMP: // Uncond branch. case X86::JMP32r: // Indirect branch. + case X86::JMP64r: // Indirect branch (64-bit). case X86::JMP32m: // Indirect branch through mem. + case X86::JMP64m: // Indirect branch through mem (64-bit). return true; default: return false; } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r42035 - in /llvm/trunk: lib/Transforms/Scalar/InstructionCombining.cpp test/Transforms/InstCombine/srem.ll test/Transforms/InstCombine/urem.ll
Author: djg
Date: Mon Sep 17 12:31:57 2007
New Revision: 42035
URL: http://llvm.org/viewvc/llvm-project?rev=42035view=rev
Log:
Instcombine x-((x/y)*y) into a remainder operator.
Added:
llvm/trunk/test/Transforms/InstCombine/srem.ll
llvm/trunk/test/Transforms/InstCombine/urem.ll
Modified:
llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp
Modified: llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp?rev=42035r1=42034r2=42035view=diff
==
--- llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Mon Sep 17
12:31:57 2007
@@ -2257,6 +2257,17 @@
Constant *CP1 = Subtract(ConstantInt::get(I.getType(), 1), C2);
return BinaryOperator::createMul(Op0, CP1);
}
+
+ // X - ((X / Y) * Y) -- X % Y
+ if (Op1I-getOpcode() == Instruction::Mul)
+if (Instruction *I = dyn_castInstruction(Op1I-getOperand(0)))
+ if (Op0 == I-getOperand(0)
+ Op1I-getOperand(1) == I-getOperand(1)) {
+if (I-getOpcode() == Instruction::SDiv)
+ return BinaryOperator::createSRem(Op0, Op1I-getOperand(1));
+if (I-getOpcode() == Instruction::UDiv)
+ return BinaryOperator::createURem(Op0, Op1I-getOperand(1));
+ }
}
}
@@ -2902,7 +2913,7 @@
/// getICmpValue - This is the complement of getICmpCode, which turns an
/// opcode and two operands into either a constant true or false, or a brand
-/// new /// ICmp instruction. The sign is passed in to determine which kind
+/// new ICmp instruction. The sign is passed in to determine which kind
/// of predicate to use in new icmp instructions.
static Value *getICmpValue(bool sign, unsigned code, Value *LHS, Value *RHS) {
switch (code) {
Added: llvm/trunk/test/Transforms/InstCombine/srem.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/srem.ll?rev=42035view=auto
==
--- llvm/trunk/test/Transforms/InstCombine/srem.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/srem.ll Mon Sep 17 12:31:57 2007
@@ -0,0 +1,8 @@
+; RUN: llvm-as %s | opt -instcombine | llvm-dis | grep srem
+
+define i64 @foo(i64 %x1, i64 %y2) {
+ %r = sdiv i64 %x1, %y2
+ %r7 = mul i64 %r, %y2
+ %r8 = sub i64 %x1, %r7
+ ret i64 %r8
+}
Added: llvm/trunk/test/Transforms/InstCombine/urem.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/urem.ll?rev=42035view=auto
==
--- llvm/trunk/test/Transforms/InstCombine/urem.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/urem.ll Mon Sep 17 12:31:57 2007
@@ -0,0 +1,8 @@
+; RUN: llvm-as %s | opt -instcombine | llvm-dis | grep urem
+
+define i64 @rem_unsigned(i64 %x1, i64 %y2) {
+ %r = udiv i64 %x1, %y2
+ %r7 = mul i64 %r, %y2
+ %r8 = sub i64 %x1, %r7
+ ret i64 %r8
+}
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[llvm-commits] [llvm] r42038 - /llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
Author: djg
Date: Mon Sep 17 12:44:31 2007
New Revision: 42038
URL: http://llvm.org/viewvc/llvm-project?rev=42038view=rev
Log:
Add a utility function to SDOperand for testing if a value is unused.
Modified:
llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=42038r1=42037r2=42038view=diff
==
--- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Mon Sep 17 12:44:31 2007
@@ -766,6 +766,10 @@
/// hasOneUse - Return true if there is exactly one operation using this
/// result value of the defining operator.
inline bool hasOneUse() const;
+
+ /// use_empty - Return true if there are no operations using this
+ /// result value of the defining operator.
+ inline bool use_empty() const;
};
@@ -1035,6 +1039,9 @@
inline bool SDOperand::hasOneUse() const {
return Val-hasNUsesOfValue(1, ResNo);
}
+inline bool SDOperand::use_empty() const {
+ return !Val-hasAnyUseOfValue(ResNo);
+}
/// UnarySDNode - This class is used for single-operand SDNodes. This is
solely
/// to allow co-allocation of node operands with the node itself.
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Re: [llvm-commits] [llvm] r42029 - /llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
Doh. Thanks Dan. Was this breaking anything? Seems to me this fix should be merged into the release branch. What do you say? The only in-tree user of BlockHasNoFallThrough appears to be BranchFolding, and there it's just guarding an optimization. Dan -- Dan Gohman, Cray Inc. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r41775 - in /llvm/trunk: lib/Target/X86/X86InstrInfo.td lib/Target/X86/X86InstrSSE.td lib/Target/X86/X86InstrX86-64.td test/CodeGen/X86/zero-remat.ll
Are you saying such a fix exists already, or that this is how a fix should work? If the latter, I'd prefer to just revert the change to the instructions that use xor so that they are not marked rematerializable for now (though the ones that use pxor/xorps/xorpd are ok). s/current/correct :-) I've already implemented it though. Ok, thanks! Why do you prefer to revert the change? I don't, now that the fix is in. Dan -- Dan Gohman, Cray Inc. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r41956 - in /llvm/trunk: include/llvm/CodeGen/MachineInstr.h lib/CodeGen/MachineInstr.cpp lib/Support/APFloat.cpp lib/System/Unix/Program.inc utils/TableGen/CodeGenRegisters.h
Author: djg
Date: Fri Sep 14 15:08:19 2007
New Revision: 41956
URL: http://llvm.org/viewvc/llvm-project?rev=41956view=rev
Log:
Remove spurious consts. This fixes warnings with compilers that
are strict about such things.
Modified:
llvm/trunk/include/llvm/CodeGen/MachineInstr.h
llvm/trunk/lib/CodeGen/MachineInstr.cpp
llvm/trunk/lib/Support/APFloat.cpp
llvm/trunk/lib/System/Unix/Program.inc
llvm/trunk/utils/TableGen/CodeGenRegisters.h
Modified: llvm/trunk/include/llvm/CodeGen/MachineInstr.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineInstr.h?rev=41956r1=41955r2=41956view=diff
==
--- llvm/trunk/include/llvm/CodeGen/MachineInstr.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineInstr.h Fri Sep 14 15:08:19 2007
@@ -363,7 +363,7 @@
/// getOpcode - Returns the opcode of this MachineInstr.
///
- const int getOpcode() const;
+ int getOpcode() const;
/// Access to explicit operands of the instruction.
///
Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=41956r1=41955r2=41956view=diff
==
--- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Fri Sep 14 15:08:19 2007
@@ -116,7 +116,7 @@
/// getOpcode - Returns the opcode of this MachineInstr.
///
-const int MachineInstr::getOpcode() const {
+int MachineInstr::getOpcode() const {
return TID-Opcode;
}
Modified: llvm/trunk/lib/Support/APFloat.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/APFloat.cpp?rev=41956r1=41955r2=41956view=diff
==
--- llvm/trunk/lib/Support/APFloat.cpp (original)
+++ llvm/trunk/lib/Support/APFloat.cpp Fri Sep 14 15:08:19 2007
@@ -1629,7 +1629,7 @@
APInt
APFloat::convertDoubleAPFloatToAPInt() const {
- assert(semantics == (const llvm::fltSemantics* const)IEEEdouble);
+ assert(semantics == (const llvm::fltSemantics*)IEEEdouble);
assert (partCount()==1);
uint64_t myexponent, mysignificand;
@@ -1659,7 +1659,7 @@
APInt
APFloat::convertFloatAPFloatToAPInt() const {
- assert(semantics == (const llvm::fltSemantics* const)IEEEsingle);
+ assert(semantics == (const llvm::fltSemantics*)IEEEsingle);
assert (partCount()==1);
uint32_t myexponent, mysignificand;
Modified: llvm/trunk/lib/System/Unix/Program.inc
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Unix/Program.inc?rev=41956r1=41955r2=41956view=diff
==
--- llvm/trunk/lib/System/Unix/Program.inc (original)
+++ llvm/trunk/lib/System/Unix/Program.inc Fri Sep 14 15:08:19 2007
@@ -196,9 +196,9 @@
// Execute!
if (envp != 0)
-execve (path.c_str(), (char** const)args, (char**)envp);
+execve (path.c_str(), (char**)args, (char**)envp);
else
-execv (path.c_str(), (char** const)args);
+execv (path.c_str(), (char**)args);
// If the execve() failed, we should exit and let the parent pick up
// our non-zero exit status.
exit (errno);
Modified: llvm/trunk/utils/TableGen/CodeGenRegisters.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenRegisters.h?rev=41956r1=41955r2=41956view=diff
==
--- llvm/trunk/utils/TableGen/CodeGenRegisters.h (original)
+++ llvm/trunk/utils/TableGen/CodeGenRegisters.h Fri Sep 14 15:08:19 2007
@@ -45,7 +45,7 @@
const std::vectorMVT::ValueType getValueTypes() const { return VTs; }
unsigned getNumValueTypes() const { return VTs.size(); }
-const MVT::ValueType getValueTypeNum(unsigned VTNum) const {
+MVT::ValueType getValueTypeNum(unsigned VTNum) const {
if (VTNum VTs.size())
return VTs[VTNum];
assert(0 VTNum greater than number of ValueTypes in RegClass!);
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[llvm-commits] [llvm] r41957 - /llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp
Author: djg
Date: Fri Sep 14 15:11:40 2007
New Revision: 41957
URL: http://llvm.org/viewvc/llvm-project?rev=41957view=rev
Log:
Change tmp. to tmp for temporaries created by ScalarEvolutionExpander
for consistency with many other transforms.
Modified:
llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp
Modified: llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp?rev=41957r1=41956r2=41957view=diff
==
--- llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp (original)
+++ llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp Fri Sep 14 15:11:40 2007
@@ -94,7 +94,7 @@
}
// If we don't have
- return BinaryOperator::create(Opcode, LHS, RHS, tmp., InsertPt);
+ return BinaryOperator::create(Opcode, LHS, RHS, tmp, InsertPt);
}
Value *SCEVExpander::visitMulExpr(SCEVMulExpr *S) {
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[llvm-commits] [llvm] r41958 - in /llvm/trunk: include/llvm/CodeGen/ lib/CodeGen/ lib/Target/ lib/Target/ARM/ lib/Target/PowerPC/ lib/Target/X86/
Author: djg
Date: Fri Sep 14 15:33:02 2007
New Revision: 41958
URL: http://llvm.org/viewvc/llvm-project?rev=41958view=rev
Log:
Remove isReg, isImm, and isMBB, and change all their users to use
isRegister, isImmediate, and isMachineBasicBlock, which are equivalent,
and more popular.
Modified:
llvm/trunk/include/llvm/CodeGen/LiveVariables.h
llvm/trunk/include/llvm/CodeGen/MachineInstr.h
llvm/trunk/lib/CodeGen/AsmPrinter.cpp
llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
llvm/trunk/lib/CodeGen/LiveVariables.cpp
llvm/trunk/lib/CodeGen/LowerSubregs.cpp
llvm/trunk/lib/CodeGen/MachineInstr.cpp
llvm/trunk/lib/CodeGen/RegisterScavenging.cpp
llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
llvm/trunk/lib/CodeGen/VirtRegMap.cpp
llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp
llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp
llvm/trunk/lib/Target/PowerPC/PPCBranchSelector.cpp
llvm/trunk/lib/Target/TargetInstrInfo.cpp
llvm/trunk/lib/Target/X86/X86ATTAsmPrinter.cpp
llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp
llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
Modified: llvm/trunk/include/llvm/CodeGen/LiveVariables.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LiveVariables.h?rev=41958r1=41957r2=41958view=diff
==
--- llvm/trunk/include/llvm/CodeGen/LiveVariables.h (original)
+++ llvm/trunk/include/llvm/CodeGen/LiveVariables.h Fri Sep 14 15:33:02 2007
@@ -229,7 +229,7 @@
bool Removed = false;
for (unsigned i = 0, e = MI-getNumOperands(); i != e; ++i) {
MachineOperand MO = MI-getOperand(i);
- if (MO.isReg() MO.isKill() MO.getReg() == reg) {
+ if (MO.isRegister() MO.isKill() MO.getReg() == reg) {
MO.unsetIsKill();
Removed = true;
break;
@@ -266,7 +266,7 @@
bool Removed = false;
for (unsigned i = 0, e = MI-getNumOperands(); i != e; ++i) {
MachineOperand MO = MI-getOperand(i);
- if (MO.isReg() MO.isDef() MO.getReg() == reg) {
+ if (MO.isRegister() MO.isDef() MO.getReg() == reg) {
MO.unsetIsDead();
Removed = true;
break;
Modified: llvm/trunk/include/llvm/CodeGen/MachineInstr.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineInstr.h?rev=41958r1=41957r2=41958view=diff
==
--- llvm/trunk/include/llvm/CodeGen/MachineInstr.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineInstr.h Fri Sep 14 15:33:02 2007
@@ -131,10 +131,6 @@
/// Accessors that tell you what kind of MachineOperand you're looking at.
///
- bool isReg() const { return opType == MO_Register; }
- bool isImm() const { return opType == MO_Immediate; }
- bool isMBB() const { return opType == MO_MachineBasicBlock; }
-
bool isRegister() const { return opType == MO_Register; }
bool isImmediate() const { return opType == MO_Immediate; }
bool isMachineBasicBlock() const { return opType == MO_MachineBasicBlock; }
@@ -145,12 +141,12 @@
bool isExternalSymbol() const { return opType == MO_ExternalSymbol; }
int64_t getImm() const {
-assert(isImm() Wrong MachineOperand accessor);
+assert(isImmediate() Wrong MachineOperand accessor);
return contents.immedVal;
}
int64_t getImmedValue() const {
-assert(isImm() Wrong MachineOperand accessor);
+assert(isImmediate() Wrong MachineOperand accessor);
return contents.immedVal;
}
MachineBasicBlock *getMBB() const {
@@ -257,11 +253,11 @@
}
void setImmedValue(int64_t immVal) {
-assert(isImm() Wrong MachineOperand mutator);
+assert(isImmediate() Wrong MachineOperand mutator);
contents.immedVal = immVal;
}
void setImm(int64_t immVal) {
-assert(isImm() Wrong MachineOperand mutator);
+assert(isImmediate() Wrong MachineOperand mutator);
contents.immedVal = immVal;
}
Modified: llvm/trunk/lib/CodeGen/AsmPrinter.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter.cpp?rev=41958r1=41957r2=41958view=diff
==
--- llvm/trunk/lib/CodeGen/AsmPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter.cpp Fri Sep 14 15:33:02 2007
@@ -982,7 +982,7 @@
// Count the number of register definitions.
unsigned NumDefs = 0;
- for (; MI-getOperand(NumDefs).isReg() MI-getOperand(NumDefs).isDef();
+ for (; MI-getOperand(NumDefs).isRegister()
MI-getOperand(NumDefs).isDef();
++NumDefs)
assert(NumDefs != NumOperands-1 No asm string?);
Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=41958r1=41957r2=41958view=diff
==
---
[llvm-commits] [llvm] r41960 - in /llvm/trunk: include/llvm/ADT/FoldingSet.h lib/Support/FoldingSet.cpp
Author: djg
Date: Fri Sep 14 15:48:42 2007
New Revision: 41960
URL: http://llvm.org/viewvc/llvm-project?rev=41960view=rev
Log:
And an FoldingSetImpl::NodeID::AddInteger overload for int64_t, to avoid
ambiguity.
Modified:
llvm/trunk/include/llvm/ADT/FoldingSet.h
llvm/trunk/lib/Support/FoldingSet.cpp
Modified: llvm/trunk/include/llvm/ADT/FoldingSet.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/FoldingSet.h?rev=41960r1=41959r2=41960view=diff
==
--- llvm/trunk/include/llvm/ADT/FoldingSet.h (original)
+++ llvm/trunk/include/llvm/ADT/FoldingSet.h Fri Sep 14 15:48:42 2007
@@ -149,6 +149,7 @@
void AddPointer(const void *Ptr);
void AddInteger(signed I);
void AddInteger(unsigned I);
+void AddInteger(int64_t I);
void AddInteger(uint64_t I);
void AddFloat(float F);
void AddDouble(double D);
Modified: llvm/trunk/lib/Support/FoldingSet.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/FoldingSet.cpp?rev=41960r1=41959r2=41960view=diff
==
--- llvm/trunk/lib/Support/FoldingSet.cpp (original)
+++ llvm/trunk/lib/Support/FoldingSet.cpp Fri Sep 14 15:48:42 2007
@@ -40,6 +40,9 @@
void FoldingSetImpl::NodeID::AddInteger(unsigned I) {
Bits.push_back(I);
}
+void FoldingSetImpl::NodeID::AddInteger(int64_t I) {
+ AddInteger((uint64_t)I);
+}
void FoldingSetImpl::NodeID::AddInteger(uint64_t I) {
Bits.push_back(unsigned(I));
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[llvm-commits] [llvm] r41959 - /llvm/trunk/test/CodeGen/PowerPC/fabs.ll
Author: djg
Date: Fri Sep 14 15:37:18 2007
New Revision: 41959
URL: http://llvm.org/viewvc/llvm-project?rev=41959view=rev
Log:
Add explicit triples to avoid default behavior that varies by host.
Modified:
llvm/trunk/test/CodeGen/PowerPC/fabs.ll
Modified: llvm/trunk/test/CodeGen/PowerPC/fabs.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/fabs.ll?rev=41959r1=41958r2=41959view=diff
==
--- llvm/trunk/test/CodeGen/PowerPC/fabs.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/fabs.ll Fri Sep 14 15:37:18 2007
@@ -1,4 +1,4 @@
-; RUN: llvm-as %s | llc -march=ppc32 | grep {fabs f1, f1}
+; RUN: llvm-as %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin | grep
{fabs f1, f1}
define double @fabs(double %f) {
entry:
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[llvm-commits] [llvm] r41975 - in /llvm/trunk/lib/Target/X86: X86InstrInfo.cpp X86InstrX86-64.td
Author: djg
Date: Fri Sep 14 18:17:45 2007
New Revision: 41975
URL: http://llvm.org/viewvc/llvm-project?rev=41975view=rev
Log:
Add patterns for SHLD64* and SHRD64*.
Modified:
llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
llvm/trunk/lib/Target/X86/X86InstrX86-64.td
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=41975r1=41974r2=41975view=diff
==
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Fri Sep 14 18:17:45 2007
@@ -338,7 +338,9 @@
case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I - A = SHLD16rri8 C, B,
(16-I)
case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I - A = SHRD16rri8 C, B,
(16-I)
case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I - A = SHLD32rri8 C, B,
(32-I)
- case X86::SHLD32rri8:{// A = SHLD32rri8 B, C, I - A = SHRD32rri8 C, B,
(32-I)
+ case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I - A = SHRD32rri8 C, B,
(32-I)
+ case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I - A = SHLD64rri8 C, B,
(64-I)
+ case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I - A = SHRD64rri8 C, B,
(64-I)
unsigned Opc;
unsigned Size;
switch (MI-getOpcode()) {
@@ -347,6 +349,8 @@
case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
+case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
+case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
}
unsigned Amt = MI-getOperand(3).getImmedValue();
unsigned A = MI-getOperand(0).getReg();
Modified: llvm/trunk/lib/Target/X86/X86InstrX86-64.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrX86-64.td?rev=41975r1=41974r2=41975view=diff
==
--- llvm/trunk/lib/Target/X86/X86InstrX86-64.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrX86-64.td Fri Sep 14 18:17:45 2007
@@ -564,38 +564,50 @@
let isTwoAddress = 1 in {
let Uses = [CL] in {
def SHLD64rrCL : RI0xA5, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1,
GR64:$src2),
-shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}, [], TB;
+shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL},
+[(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, CL))],
TB;
def SHRD64rrCL : RI0xAD, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1,
GR64:$src2),
-shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}, [], TB;
+shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL},
+[(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, CL))],
TB;
}
let isCommutable = 1 in { // FIXME: Update X86InstrInfo::commuteInstruction
def SHLD64rri8 : RIi80xA4, MRMDestReg,
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2,
i8imm:$src3),
- shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}, [],
- TB;
+ shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3},
+ [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2,
+ (i8 imm:$src3)))],
+ TB;
def SHRD64rri8 : RIi80xAC, MRMDestReg,
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2,
i8imm:$src3),
- shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}, [],
+ shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3},
+ [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2,
+ (i8 imm:$src3)))],
TB;
} // isCommutable
} // isTwoAddress
-// Temporary hack: there is no patterns associated with these instructions
-// so we have to tell tblgen that these do not produce results.
let Uses = [CL] in {
def SHLD64mrCL : RI0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
-shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}, [], TB;
+shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL},
+[(store (X86shld (loadi64 addr:$dst), GR64:$src2, CL),
+ addr:$dst)], TB;
def SHRD64mrCL : RI0xAD, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
-shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}, [], TB;
+shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL},
+[(store (X86shrd (loadi64 addr:$dst), GR64:$src2, CL),
+ addr:$dst)], TB;
}
def SHLD64mri8 : RIi80xA4, MRMDestMem,
(outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
- shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}, [],
+ shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3},
+
Re: [llvm-commits] [llvm] r41775 - in /llvm/trunk: lib/Target/X86/X86InstrInfo.td lib/Target/X86/X86InstrSSE.td lib/Target/X86/X86InstrX86-64.td test/CodeGen/X86/zero-remat.ll
Hi Dan, This is not safe because xor will clobber flags. It's a miscompilation if the user of the rematerialized value is a conditional move (e.g. cmovne). Thanks for spotting that! The current fix is to X86RegisterInfo::reMaterialize() should rematerialize it as a move instruction. Are you saying such a fix exists already, or that this is how a fix should work? If the latter, I'd prefer to just revert the change to the instructions that use xor so that they are not marked rematerializable for now (though the ones that use pxor/xorps/xorpd are ok). Dan -- Dan Gohman, Cray Inc. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r41775 - in /llvm/trunk: lib/Target/X86/X86InstrInfo.td lib/Target/X86/X86InstrSSE.td lib/Target/X86/X86InstrX86-64.td test/CodeGen/X86/zero-remat.ll
Author: djg
Date: Fri Sep 7 16:32:51 2007
New Revision: 41775
URL: http://llvm.org/viewvc/llvm-project?rev=41775view=rev
Log:
Avoid storing and reloading zeros and other constants from stack slots
by flagging the associated instructions as being trivially rematerializable.
Added:
llvm/trunk/test/CodeGen/X86/zero-remat.ll
Modified:
llvm/trunk/lib/Target/X86/X86InstrInfo.td
llvm/trunk/lib/Target/X86/X86InstrSSE.td
llvm/trunk/lib/Target/X86/X86InstrX86-64.td
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=41775r1=41774r2=41775view=diff
==
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Fri Sep 7 16:32:51 2007
@@ -2313,6 +2313,7 @@
// Alias instructions that map movr0 to xor.
// FIXME: remove when we can teach regalloc that xor reg, reg is ok.
+let isReMaterializable = 1 in {
def MOV8r0 : I0x30, MRMInitReg, (outs GR8 :$dst), (ins),
xor{b}\t$dst, $dst,
[(set GR8:$dst, 0)];
@@ -2322,6 +2323,7 @@
def MOV32r0 : I0x31, MRMInitReg, (outs GR32:$dst), (ins),
xor{l}\t$dst, $dst,
[(set GR32:$dst, 0)];
+}
// Basic operations on GR16 / GR32 subclasses GR16_ and GR32_ which contains
only
// those registers that have GR8 sub-registers (i.e. AX - DX, EAX - EDX).
Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=41775r1=41774r2=41775view=diff
==
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Fri Sep 7 16:32:51 2007
@@ -399,6 +399,7 @@
// start with 'Fs'.
// Alias instructions that map fld0 to pxor for sse.
+let isReMaterializable = 1 in
def FsFLD0SS : I0xEF, MRMInitReg, (outs FR32:$dst), (ins),
pxor\t$dst, $dst, [(set FR32:$dst, fp32imm0)],
Requires[HasSSE1], TB, OpSize;
@@ -1063,6 +1064,7 @@
// start with 'Fs'.
// Alias instructions that map fld0 to pxor for sse.
+let isReMaterializable = 1 in
def FsFLD0SD : I0xEF, MRMInitReg, (outs FR64:$dst), (ins),
pxor\t$dst, $dst, [(set FR64:$dst, fpimm0)],
Requires[HasSSE2], TB, OpSize;
Modified: llvm/trunk/lib/Target/X86/X86InstrX86-64.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrX86-64.td?rev=41775r1=41774r2=41775view=diff
==
--- llvm/trunk/lib/Target/X86/X86InstrX86-64.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrX86-64.td Fri Sep 7 16:32:51 2007
@@ -156,12 +156,14 @@
def MOV64rr : RI0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
mov{q}\t{$src, $dst|$dst, $src}, [];
+let isReMaterializable = 1 in {
def MOV64ri : RIi640xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
movabs{q}\t{$src, $dst|$dst, $src},
[(set GR64:$dst, imm:$src)];
def MOV64ri32 : RIi320xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
mov{q}\t{$src, $dst|$dst, $src},
[(set GR64:$dst, i64immSExt32:$src)];
+}
let isLoad = 1 in
def MOV64rm : RI0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
@@ -990,13 +992,13 @@
// FIXME: remove when we can teach regalloc that xor reg, reg is ok.
// FIXME: AddedComplexity gives MOV64r0 a higher priority than MOV64ri32.
Remove
// when we have a better way to specify isel priority.
-let AddedComplexity = 1 in
+let AddedComplexity = 1, isReMaterializable = 1 in
def MOV64r0 : RI0x31, MRMInitReg, (outs GR64:$dst), (ins),
xor{q}\t$dst, $dst,
[(set GR64:$dst, 0)];
// Materialize i64 constant where top 32-bits are zero.
-let AddedComplexity = 1 in
+let AddedComplexity = 1, isReMaterializable = 1 in
def MOV64ri64i32 : Ii320xB8, AddRegFrm, (outs GR64:$dst), (ins
i64i32imm:$src),
mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32},
$src},
[(set GR64:$dst, i64immZExt32:$src)];
Added: llvm/trunk/test/CodeGen/X86/zero-remat.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/zero-remat.ll?rev=41775view=auto
==
--- llvm/trunk/test/CodeGen/X86/zero-remat.ll (added)
+++ llvm/trunk/test/CodeGen/X86/zero-remat.ll Fri Sep 7 16:32:51 2007
@@ -0,0 +1,14 @@
+; RUN: llvm-as %s | llc -march=x86-64 | grep xor | count 4
+; RUN: llvm-as %s | llc -march=x86-64 -stats -info-output-file - | grep
asm-printer | grep 12
+
+declare void @bar(double %x)
+declare void @barf(float %x)
+
+define double @foo() {
+ call void @bar(double 0.0)
+ ret double 0.0
+}
Re: [llvm-commits] [patch] fix the alignment of i64 and f64 on linux x86-64
According to table 3.1 of http://www.x86-64.org/documentation/abi.pdf, the i64 and f64 types should have 8 byte alignment. The attached patch changes this for targets that are not darwin. Dan, Evan, is this ok? Evan, doesn't darwin follow the same ABI on x86-64? It looks good to me. Dan -- Dan Gohman, Cray Inc. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r41556 - in /llvm/trunk: include/llvm/CodeGen/ScheduleDAG.h lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
Author: djg
Date: Tue Aug 28 15:32:58 2007
New Revision: 41556
URL: http://llvm.org/viewvc/llvm-project?rev=41556view=rev
Log:
Add an option, -view-sunit-dags, for viewing the actual SUnit DAGs used by
scheduling.
Modified:
llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
Modified: llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h?rev=41556r1=41555r2=41556view=diff
==
--- llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h (original)
+++ llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h Tue Aug 28 15:32:58 2007
@@ -17,6 +17,7 @@
#include llvm/CodeGen/SelectionDAG.h
#include llvm/ADT/DenseMap.h
+#include llvm/ADT/GraphTraits.h
#include llvm/ADT/SmallSet.h
namespace llvm {
@@ -191,6 +192,11 @@
virtual ~ScheduleDAG() {}
+/// viewGraph - Pop up a GraphViz/gv window with the ScheduleDAG rendered
+/// using 'dot'.
+///
+void viewGraph();
+
/// Run - perform scheduling.
///
MachineBasicBlock *Run();
@@ -315,6 +321,68 @@
ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
SelectionDAG *DAG,
MachineBasicBlock *BB);
+
+ class SUnitIterator : public forward_iteratorSUnit, ptrdiff_t {
+SUnit *Node;
+unsigned Operand;
+
+SUnitIterator(SUnit *N, unsigned Op) : Node(N), Operand(Op) {}
+ public:
+bool operator==(const SUnitIterator x) const {
+ return Operand == x.Operand;
+}
+bool operator!=(const SUnitIterator x) const { return !operator==(x); }
+
+const SUnitIterator operator=(const SUnitIterator I) {
+ assert(I.Node == Node Cannot assign iterators to two different
nodes!);
+ Operand = I.Operand;
+ return *this;
+}
+
+pointer operator*() const {
+ return Node-Preds[Operand].first;
+}
+pointer operator-() const { return operator*(); }
+
+SUnitIterator operator++() {// Preincrement
+ ++Operand;
+ return *this;
+}
+SUnitIterator operator++(int) { // Postincrement
+ SUnitIterator tmp = *this; ++*this; return tmp;
+}
+
+static SUnitIterator begin(SUnit *N) { return SUnitIterator(N, 0); }
+static SUnitIterator end (SUnit *N) {
+ return SUnitIterator(N, N-Preds.size());
+}
+
+unsigned getOperand() const { return Operand; }
+const SUnit *getNode() const { return Node; }
+bool isChain() const { return Node-Preds[Operand].second; }
+ };
+
+ template struct GraphTraitsSUnit* {
+typedef SUnit NodeType;
+typedef SUnitIterator ChildIteratorType;
+static inline NodeType *getEntryNode(SUnit *N) { return N; }
+static inline ChildIteratorType child_begin(NodeType *N) {
+ return SUnitIterator::begin(N);
+}
+static inline ChildIteratorType child_end(NodeType *N) {
+ return SUnitIterator::end(N);
+}
+ };
+
+ template struct GraphTraitsScheduleDAG* : public GraphTraitsSUnit* {
+typedef std::vectorSUnit::iterator nodes_iterator;
+static nodes_iterator nodes_begin(ScheduleDAG *G) {
+ return G-SUnits.begin();
+}
+static nodes_iterator nodes_end(ScheduleDAG *G) {
+ return G-SUnits.end();
+}
+ };
}
#endif
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=41556r1=41555r2=41556view=diff
==
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Tue Aug 28
15:32:58 2007
@@ -54,8 +54,11 @@
static cl::optbool
ViewSchedDAGs(view-sched-dags, cl::Hidden,
cl::desc(Pop up a window to show sched dags as they are
processed));
+static cl::optbool
+ViewSUnitDAGs(view-sunit-dags, cl::Hidden,
+ cl::desc(Pop up a window to show SUnit dags after they are
processed));
#else
-static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0;
+static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0, ViewSUnitDAGs = 0;
#endif
//===-===//
@@ -4842,6 +4845,9 @@
ScheduleDAG *SL = Ctor(this, DAG, BB);
BB = SL-Run();
+
+ if (ViewSUnitDAGs) SL-viewGraph();
+
delete SL;
}
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp?rev=41556r1=41555r2=41556view=diff
==
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp (original)
+++
[llvm-commits] [llvm] r41482 - in /llvm/trunk: include/llvm/ADT/FoldingSet.h include/llvm/CodeGen/LiveInterval.h include/llvm/CodeGen/MachineConstantPool.h include/llvm/CodeGen/MachineFunction.h inclu
Author: djg
Date: Mon Aug 27 09:50:10 2007
New Revision: 41482
URL: http://llvm.org/viewvc/llvm-project?rev=41482view=rev
Log:
Add explicit keywords and remove spurious trailing semicolons.
Modified:
llvm/trunk/include/llvm/ADT/FoldingSet.h
llvm/trunk/include/llvm/CodeGen/LiveInterval.h
llvm/trunk/include/llvm/CodeGen/MachineConstantPool.h
llvm/trunk/include/llvm/CodeGen/MachineFunction.h
llvm/trunk/include/llvm/CodeGen/RegisterScavenging.h
llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
llvm/trunk/include/llvm/CodeGen/SimpleRegisterCoalescing.h
llvm/trunk/include/llvm/Support/FileUtilities.h
llvm/trunk/include/llvm/Target/TargetELFWriterInfo.h
llvm/trunk/include/llvm/Target/TargetLowering.h
llvm/trunk/lib/CodeGen/DwarfWriter.cpp
llvm/trunk/lib/CodeGen/PhysRegTracker.h
Modified: llvm/trunk/include/llvm/ADT/FoldingSet.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/FoldingSet.h?rev=41482r1=41481r2=41482view=diff
==
--- llvm/trunk/include/llvm/ADT/FoldingSet.h (original)
+++ llvm/trunk/include/llvm/ADT/FoldingSet.h Mon Aug 27 09:50:10 2007
@@ -119,7 +119,7 @@
unsigned NumNodes;
public:
- FoldingSetImpl(unsigned Log2InitSize = 6);
+ explicit FoldingSetImpl(unsigned Log2InitSize = 6);
virtual ~FoldingSetImpl();
// Forward declaration.
@@ -232,7 +232,7 @@
}
public:
- FoldingSet(unsigned Log2InitSize = 6)
+ explicit FoldingSet(unsigned Log2InitSize = 6)
: FoldingSetImpl(Log2InitSize)
{}
Modified: llvm/trunk/include/llvm/CodeGen/LiveInterval.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LiveInterval.h?rev=41482r1=41481r2=41482view=diff
==
--- llvm/trunk/include/llvm/CodeGen/LiveInterval.h (original)
+++ llvm/trunk/include/llvm/CodeGen/LiveInterval.h Mon Aug 27 09:50:10 2007
@@ -96,8 +96,8 @@
unsigned def;
unsigned reg;
SmallVectorunsigned, 4 kills;
- VNInfo() : def(~1U), reg(0) {};
- VNInfo(unsigned d, unsigned r) : def(d), reg(r) {};
+ VNInfo() : def(~1U), reg(0) {}
+ VNInfo(unsigned d, unsigned r) : def(d), reg(r) {}
};
private:
SmallVectorVNInfo, 4 ValueNumberInfo;
Modified: llvm/trunk/include/llvm/CodeGen/MachineConstantPool.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineConstantPool.h?rev=41482r1=41481r2=41482view=diff
==
--- llvm/trunk/include/llvm/CodeGen/MachineConstantPool.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineConstantPool.h Mon Aug 27 09:50:10
2007
@@ -36,7 +36,7 @@
public:
explicit MachineConstantPoolValue(const Type *ty) : Ty(ty) {}
- virtual ~MachineConstantPoolValue() {};
+ virtual ~MachineConstantPoolValue() {}
/// getType - get type of this MachineConstantPoolValue.
///
Modified: llvm/trunk/include/llvm/CodeGen/MachineFunction.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineFunction.h?rev=41482r1=41481r2=41482view=diff
==
--- llvm/trunk/include/llvm/CodeGen/MachineFunction.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineFunction.h Mon Aug 27 09:50:10 2007
@@ -73,7 +73,7 @@
/// of type are accessed/created with MF::getInfo and destroyed when the
/// MachineFunction is destroyed.
struct MachineFunctionInfo {
- virtual ~MachineFunctionInfo() {};
+ virtual ~MachineFunctionInfo() {}
};
class MachineFunction : private Annotation {
Modified: llvm/trunk/include/llvm/CodeGen/RegisterScavenging.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/RegisterScavenging.h?rev=41482r1=41481r2=41482view=diff
==
--- llvm/trunk/include/llvm/CodeGen/RegisterScavenging.h (original)
+++ llvm/trunk/include/llvm/CodeGen/RegisterScavenging.h Mon Aug 27 09:50:10
2007
@@ -55,11 +55,11 @@
public:
RegScavenger()
: MBB(NULL), NumPhysRegs(0), Tracking(false),
- ScavengingFrameIndex(-1), ScavengedReg(0), ScavengedRC(NULL) {};
+ ScavengingFrameIndex(-1), ScavengedReg(0), ScavengedRC(NULL) {}
explicit RegScavenger(MachineBasicBlock *mbb)
: MBB(mbb), NumPhysRegs(0), Tracking(false),
- ScavengingFrameIndex(-1), ScavengedReg(0), ScavengedRC(NULL) {};
+ ScavengingFrameIndex(-1), ScavengedReg(0), ScavengedRC(NULL) {}
/// enterBasicBlock - Start tracking liveness from the begin of the specific
/// basic block.
Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h?rev=41482r1=41481r2=41482view=diff
[llvm-commits] [llvm] r41488 - /llvm/trunk/lib/Transforms/IPO/RaiseAllocations.cpp
Author: djg
Date: Mon Aug 27 11:11:48 2007
New Revision: 41488
URL: http://llvm.org/viewvc/llvm-project?rev=41488view=rev
Log:
Change comments to refer to @malloc and @free instead of %malloc and %free.
Modified:
llvm/trunk/lib/Transforms/IPO/RaiseAllocations.cpp
Modified: llvm/trunk/lib/Transforms/IPO/RaiseAllocations.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/RaiseAllocations.cpp?rev=41488r1=41487r2=41488view=diff
==
--- llvm/trunk/lib/Transforms/IPO/RaiseAllocations.cpp (original)
+++ llvm/trunk/lib/Transforms/IPO/RaiseAllocations.cpp Mon Aug 27 11:11:48 2007
@@ -1,4 +1,4 @@
-//===- RaiseAllocations.cpp - Convert %malloc %free calls to insts
--===//
+//===- RaiseAllocations.cpp - Convert @malloc @free calls to insts
--===//
//
// The LLVM Compiler Infrastructure
//
@@ -28,7 +28,7 @@
STATISTIC(NumRaised, Number of allocations raised);
namespace {
- // RaiseAllocations - Turn %malloc and %free calls into the appropriate
+ // RaiseAllocations - Turn @malloc and @free calls into the appropriate
// instruction.
//
class VISIBILITY_HIDDEN RaiseAllocations : public ModulePass {
@@ -65,7 +65,7 @@
// free functions. If this is the case, grab the method pointers that the
// module is using.
//
-// Lookup %malloc and %free in the symbol table, for later use. If they don't
+// Lookup @malloc and @free in the symbol table, for later use. If they don't
// exist, or are not external, we do not worry about converting calls to that
// function into the appropriate instruction.
//
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r41489 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAGISel.h lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp test/CodeGen/X86/memmove-0.ll test/CodeGen/X86/memmove-1.ll test/Co
Author: djg
Date: Mon Aug 27 11:26:13 2007
New Revision: 41489
URL: http://llvm.org/viewvc/llvm-project?rev=41489view=rev
Log:
If the source and destination pointers in an llvm.memmove are known
to not alias each other, it can be translated as an llvm.memcpy.
Added:
llvm/trunk/test/CodeGen/X86/memmove-0.ll
llvm/trunk/test/CodeGen/X86/memmove-1.ll
llvm/trunk/test/CodeGen/X86/memmove-2.ll
llvm/trunk/test/CodeGen/X86/memmove-3.ll
Modified:
llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h?rev=41489r1=41488r2=41489view=diff
==
--- llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h Mon Aug 27 11:26:13 2007
@@ -39,6 +39,7 @@
SSARegMap *RegMap;
SelectionDAG *CurDAG;
MachineBasicBlock *BB;
+ AliasAnalysis *AA;
std::vectorSDNode* TopOrder;
unsigned DAGSize;
static char ID;
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=41489r1=41488r2=41489view=diff
==
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Mon Aug 27
11:26:13 2007
@@ -409,6 +409,7 @@
TargetLowering TLI;
SelectionDAG DAG;
const TargetData *TD;
+ AliasAnalysis AA;
/// SwitchCases - Vector of CaseBlock structures used to communicate
/// SwitchInst code generation information.
@@ -423,8 +424,9 @@
FunctionLoweringInfo FuncInfo;
SelectionDAGLowering(SelectionDAG dag, TargetLowering tli,
+ AliasAnalysis aa,
FunctionLoweringInfo funcinfo)
-: TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()),
+: TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()), AA(aa),
FuncInfo(funcinfo) {
}
@@ -4196,6 +4198,17 @@
unsigned Align = (unsigned)castConstantSDNode(Op4)-getValue();
if (Align == 0) Align = 1;
+ // If the source and destination are known to not be aliases, we can
+ // lower memmove as memcpy.
+ if (Op == ISD::MEMMOVE) {
+uint64_t Size = -1;
+if (ConstantSDNode *C = dyn_castConstantSDNode(Op3))
+ Size = C-getValue();
+if (AA.alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
+AliasAnalysis::NoAlias)
+ Op = ISD::MEMCPY;
+ }
+
if (ConstantSDNode *Size = dyn_castConstantSDNode(Op3)) {
std::vectorMVT::ValueType MemOps;
@@ -4307,6 +4320,9 @@
bool SelectionDAGISel::runOnFunction(Function Fn) {
+ // Get alias analysis for load/store combining.
+ AA = getAnalysisAliasAnalysis();
+
MachineFunction MF = MachineFunction::construct(Fn,
TLI.getTargetMachine());
RegMap = MF.getSSARegMap();
DOUT \n\n\n=== Fn.getName() \n;
@@ -4404,7 +4420,7 @@
void SelectionDAGISel::BuildSelectionDAG(SelectionDAG DAG, BasicBlock *LLVMBB,
std::vectorstd::pairMachineInstr*, unsigned PHINodesToUpdate,
FunctionLoweringInfo FuncInfo) {
- SelectionDAGLowering SDL(DAG, TLI, FuncInfo);
+ SelectionDAGLowering SDL(DAG, TLI, *AA, FuncInfo);
std::vectorSDOperand UnorderedChains;
@@ -4581,11 +4597,8 @@
}
void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG DAG) {
- // Get alias analysis for load/store combining.
- AliasAnalysis AA = getAnalysisAliasAnalysis();
-
// Run the DAG combiner in pre-legalize mode.
- DAG.Combine(false, AA);
+ DAG.Combine(false, *AA);
DOUT Lowered selection DAG:\n;
DEBUG(DAG.dump());
@@ -4598,7 +4611,7 @@
DEBUG(DAG.dump());
// Run the DAG combiner in post-legalize mode.
- DAG.Combine(true, AA);
+ DAG.Combine(true, *AA);
if (ViewISelDAGs) DAG.viewGraph();
@@ -4649,7 +4662,7 @@
if (!BitTestCases[i].Emitted) {
SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdateMachineModuleInfo());
CurDAG = HSDAG;
- SelectionDAGLowering HSDL(HSDAG, TLI, FuncInfo);
+ SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo);
// Set the current basic block to the mbb we wish to insert the code into
BB = BitTestCases[i].Parent;
HSDL.setCurrentBasicBlock(BB);
@@ -4662,7 +4675,7 @@
for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
SelectionDAG BSDAG(TLI, MF, getAnalysisToUpdateMachineModuleInfo());
CurDAG = BSDAG;
- SelectionDAGLowering BSDL(BSDAG, TLI, FuncInfo);
+ SelectionDAGLowering BSDL(BSDAG, TLI, *AA, FuncInfo);
// Set the current basic block to the mbb we wish to insert the code into
BB = BitTestCases[i].Cases[j].ThisBB;
[llvm-commits] [llvm] r41491 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Author: djg
Date: Mon Aug 27 11:32:11 2007
New Revision: 41491
URL: http://llvm.org/viewvc/llvm-project?rev=41491view=rev
Log:
Make DAGCombiner's global alias analysis query more precise in the case
where both pointers have non-zero offsets.
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=41491r1=41490r2=41491view=diff
==
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Aug 27 11:32:11 2007
@@ -4606,8 +4606,9 @@
if (CombinerGlobalAA) {
// Use alias analysis information.
-int Overlap1 = Size1 + SrcValueOffset1;
-int Overlap2 = Size2 + SrcValueOffset2;
+int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2);
+int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset;
+int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset;
AliasAnalysis::AliasResult AAResult =
AA.alias(SrcValue1, Overlap1, SrcValue2,
Overlap2);
if (AAResult == AliasAnalysis::NoAlias)
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Re: [llvm-commits] [llvm] r41489 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAGISel.h lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp test/CodeGen/X86/memmove-0.ll test/CodeGen/X86/memmove-1.ll tes
This is nifty, but shouldn't this be done at the LLVM IR level? I can't think of cases where lowering would create new memmove calls. I'm not aware of any cases where memmove vs. memcpy matters before codegen currently. If it were done at the LLVM IR level, would it be too trivial to be in a pass by itself, or would you want to add it, along with an addRequiredAliasAnalysis, to some existing pass? Dan -- Dan Gohman, Cray Inc. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm] r41510 - in /llvm/trunk/test/CodeGen/X86: memmove-0.ll memmove-1.ll memmove-2.ll memmove-3.ll
Author: djg
Date: Mon Aug 27 15:54:48 2007
New Revision: 41510
URL: http://llvm.org/viewvc/llvm-project?rev=41510view=rev
Log:
Add explicit triples to avoid default behavior that varies by host.
Modified:
llvm/trunk/test/CodeGen/X86/memmove-0.ll
llvm/trunk/test/CodeGen/X86/memmove-1.ll
llvm/trunk/test/CodeGen/X86/memmove-2.ll
llvm/trunk/test/CodeGen/X86/memmove-3.ll
Modified: llvm/trunk/test/CodeGen/X86/memmove-0.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/memmove-0.ll?rev=41510r1=41509r2=41510view=diff
==
--- llvm/trunk/test/CodeGen/X86/memmove-0.ll (original)
+++ llvm/trunk/test/CodeGen/X86/memmove-0.ll Mon Aug 27 15:54:48 2007
@@ -1,4 +1,4 @@
-; RUN: llvm-as %s | llc -march=x86 | grep {call memcpy}
+; RUN: llvm-as %s | llc -march=x86 -mtriple=i686-pc-linux-gnu | grep {call
memcpy}
declare void @llvm.memmove.i64(i8* %d, i8* %s, i64 %l, i32 %a)
Modified: llvm/trunk/test/CodeGen/X86/memmove-1.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/memmove-1.ll?rev=41510r1=41509r2=41510view=diff
==
--- llvm/trunk/test/CodeGen/X86/memmove-1.ll (original)
+++ llvm/trunk/test/CodeGen/X86/memmove-1.ll Mon Aug 27 15:54:48 2007
@@ -1,4 +1,4 @@
-; RUN: llvm-as %s | llc -march=x86 | grep {call memmove}
+; RUN: llvm-as %s | llc -march=x86 -mtriple=i686-pc-linux-gnu | grep {call
memmove}
declare void @llvm.memmove.i64(i8* %d, i8* %s, i64 %l, i32 %a)
Modified: llvm/trunk/test/CodeGen/X86/memmove-2.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/memmove-2.ll?rev=41510r1=41509r2=41510view=diff
==
--- llvm/trunk/test/CodeGen/X86/memmove-2.ll (original)
+++ llvm/trunk/test/CodeGen/X86/memmove-2.ll Mon Aug 27 15:54:48 2007
@@ -1,4 +1,4 @@
-; RUN: llvm-as %s | llc -march=x86 | not grep call
+; RUN: llvm-as %s | llc -march=x86 -mtriple=i686-pc-linux-gnu | not grep call
declare void @llvm.memmove.i64(i8* %d, i8* %s, i64 %l, i32 %a)
Modified: llvm/trunk/test/CodeGen/X86/memmove-3.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/memmove-3.ll?rev=41510r1=41509r2=41510view=diff
==
--- llvm/trunk/test/CodeGen/X86/memmove-3.ll (original)
+++ llvm/trunk/test/CodeGen/X86/memmove-3.ll Mon Aug 27 15:54:48 2007
@@ -1,4 +1,4 @@
-; RUN: llvm-as %s | llc -march=x86 | grep {call memmove}
+; RUN: llvm-as %s | llc -march=x86 -mtriple=i686-pc-linux-gnu | grep {call
memmove}
declare void @llvm.memmove.i64(i8* %d, i8* %s, i64 %l, i32 %a)
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