Re: [Mesa-dev] [PATCH] r600: don't emit vfetch if tess eval isn't accessing any inputs.

[Gert Wollny]

Hi Dave, 

tested on BARTS: the patch changes TESS_EVAL to end with a proper EOP
in 

  trivial-tess-gs_no-gs-inputs

(it doesn't fix the piglit though). However, it introduces a regression
in 

   vs-tcs-tes-tessinner-tessouter-inputs-quads
   vs-tes-tessinner-tessouter-inputs-quads

because in these two piglits in tgsi_declaration TESSINNER and
TESSOUTER are read from LDS, and this requires calling 
r600_fetch_tess_io_info first. Since the TESS_EVAL shader has no inputs
in these two cases the tests fail with the patch. 

One approach to solve this could be to scan the shader first for this
declaration (I'll do this is the experimental performance patches that
I'll send later), the other one could be to implement some kind of lazy
loading for the related fetch operation.

Best, 
Gert 

  
Am Mittwoch, den 15.11.2017, 11:25 +1000 schrieb Dave Airlie:
> From: Dave Airlie 
> 
> This should avoid emitting anything in the shader if we aren't
> accessing any inputs.
> 
> Signed-off-by: Dave Airlie 
> ---
>  src/gallium/drivers/r600/r600_shader.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/src/gallium/drivers/r600/r600_shader.c
> b/src/gallium/drivers/r600/r600_shader.c
> index 625537b48b..95a4c05e81 100644
> --- a/src/gallium/drivers/r600/r600_shader.c
> +++ b/src/gallium/drivers/r600/r600_shader.c
> @@ -3167,7 +3167,8 @@ static int r600_shader_from_tgsi(struct
> r600_context *rctx,
>   vs_add_primid_output(, key.vs.prim_id_out);
>  
>   if (ctx.type == PIPE_SHADER_TESS_EVAL)
> - r600_fetch_tess_io_info();
> + if (ctx.info.num_inputs)
> + r600_fetch_tess_io_info();
>  
>   while (!tgsi_parse_end_of_tokens()) {
>   tgsi_parse_token();
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [Bug 103699] Latest mesa breaks firefox on kde plasma with compositing on

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=103699

--- Comment #6 from Tapani Pälli  ---
Hello, could you please retry with using "sna" as the acceleration method? I
will attach here required configuration file for testing this. You will need to
copy this file to /usr/share/X11/xorg.conf.d/.

-- 
You are receiving this mail because:
You are the QA Contact for the bug.___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [Bug 103699] Latest mesa breaks firefox on kde plasma with compositing on

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=103699

--- Comment #7 from Tapani Pälli  ---
Created attachment 135480
  --> https://bugs.freedesktop.org/attachment.cgi?id=135480=edit
enable sna

-- 
You are receiving this mail because:
You are the QA Contact for the bug.___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH v2] anv: fix bug when using component qualifier in FS outputs

[Samuel Iglesias Gonsálvez]

We can write to the same output but in different components, like
in this example:

layout(location = 0, component = 0) out ivec2 dEQP_FragColor_0;
layout(location = 0, component = 2) out ivec2 dEQP_FragColor_1;

Therefore, they are not two different outputs but only one.

Fixes:

dEQP-VK.glsl.440.linkage.varying.component.frag_out.*

Signed-off-by: Samuel Iglesias Gonsálvez 
---
 src/compiler/shader_enums.h |  1 +
 src/intel/vulkan/anv_pipeline.c | 46 +++--
 2 files changed, 32 insertions(+), 15 deletions(-)

diff --git a/src/compiler/shader_enums.h b/src/compiler/shader_enums.h
index 9d229d4199e..90729dbfd96 100644
--- a/src/compiler/shader_enums.h
+++ b/src/compiler/shader_enums.h
@@ -603,6 +603,7 @@ typedef enum
FRAG_RESULT_DATA5,
FRAG_RESULT_DATA6,
FRAG_RESULT_DATA7,
+   FRAG_RESULT_MAX, /**< Number of fragment program results */
 } gl_frag_result;
 
 const char *gl_frag_result_name(gl_frag_result result);
diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index 907b24a758d..92cfc2898f5 100644
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -870,30 +870,28 @@ anv_pipeline_compile_fs(struct anv_pipeline *pipeline,
   }
 
   unsigned num_rts = 0;
-  struct anv_pipeline_binding rt_bindings[8];
+  const int max_rt = FRAG_RESULT_MAX - FRAG_RESULT_DATA0;
+  struct anv_pipeline_binding rt_bindings[max_rt];
   nir_function_impl *impl = nir_shader_get_entrypoint(nir);
+  int rt_to_bindings[max_rt];
+  memset(rt_to_bindings, -1, sizeof(int) * max_rt);
+
+  /* Set new, compacted, location */
   nir_foreach_variable_safe(var, >outputs) {
  if (var->data.location < FRAG_RESULT_DATA0)
 continue;
 
  unsigned rt = var->data.location - FRAG_RESULT_DATA0;
- if (rt >= key.nr_color_regions) {
-/* Out-of-bounds, throw it away */
-var->data.mode = nir_var_local;
-exec_node_remove(>node);
-exec_list_push_tail(>locals, >node);
+ if (rt_to_bindings[rt] != -1 || rt >= key.nr_color_regions)
 continue;
- }
-
- /* Give it a new, compacted, location */
- var->data.location = FRAG_RESULT_DATA0 + num_rts;
-
- unsigned array_len =
+ const unsigned array_len =
 glsl_type_is_array(var->type) ? glsl_get_length(var->type) : 1;
- assert(num_rts + array_len <= 8);
+ assert(num_rts + array_len <= max_rt);
+
+ rt_to_bindings[rt] = num_rts;
 
  for (unsigned i = 0; i < array_len; i++) {
-rt_bindings[num_rts + i] = (struct anv_pipeline_binding) {
+rt_bindings[rt_to_bindings[rt] + i] = (struct 
anv_pipeline_binding) {
.set = ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS,
.binding = 0,
.index = rt + i,
@@ -903,6 +901,24 @@ anv_pipeline_compile_fs(struct anv_pipeline *pipeline,
  num_rts += array_len;
   }
 
+  nir_foreach_variable_safe(var, >outputs) {
+ if (var->data.location < FRAG_RESULT_DATA0)
+continue;
+
+ unsigned rt = var->data.location - FRAG_RESULT_DATA0;
+ if (rt >= key.nr_color_regions) {
+/* Out-of-bounds, throw it away */
+var->data.mode = nir_var_local;
+exec_node_remove(>node);
+exec_list_push_tail(>locals, >node);
+continue;
+ }
+
+ /* Give it the new location */
+ assert(rt_to_bindings[rt] != -1);
+ var->data.location = rt_to_bindings[rt] + FRAG_RESULT_DATA0;
+  }
+
   if (num_rts == 0) {
  /* If we have no render targets, we need a null render target */
  rt_bindings[0] = (struct anv_pipeline_binding) {
@@ -913,7 +929,7 @@ anv_pipeline_compile_fs(struct anv_pipeline *pipeline,
  num_rts = 1;
   }
 
-  assert(num_rts <= 8);
+  assert(num_rts <= max_rt);
   map.surface_to_descriptor -= num_rts;
   map.surface_count += num_rts;
   assert(map.surface_count <= 256);
-- 
2.14.3

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] anv: fix bug when using component qualifier in FS outputs

[Samuel Iglesias Gonsálvez]

On Wed, 2017-11-08 at 08:19 -0800, Jason Ekstrand wrote:
> On Thu, Nov 2, 2017 at 12:28 AM, Samuel Iglesias Gonsálvez <
> sigles...@igalia.com> wrote:
> 
> > We can write to the same output but in different components, like
> > in this example:
> > 
> > layout(location = 0, component = 0) out ivec2 dEQP_FragColor_0;
> > layout(location = 0, component = 2) out ivec2 dEQP_FragColor_1;
> > 
> > Therefore, they are not two different outputs but only one.
> > 
> > Fixes:
> > 
> > dEQP-VK.glsl.440.linkage.varying.component.frag_out.*
> > 
> > Signed-off-by: Samuel Iglesias Gonsálvez 
> > ---
> >  src/compiler/shader_enums.h |  1 +
> >  src/intel/vulkan/anv_pipeline.c | 10 +-
> >  2 files changed, 10 insertions(+), 1 deletion(-)
> > 
> > diff --git a/src/compiler/shader_enums.h
> > b/src/compiler/shader_enums.h
> > index 9d229d4199e..90729dbfd96 100644
> > --- a/src/compiler/shader_enums.h
> > +++ b/src/compiler/shader_enums.h
> > @@ -603,6 +603,7 @@ typedef enum
> > FRAG_RESULT_DATA5,
> > FRAG_RESULT_DATA6,
> > FRAG_RESULT_DATA7,
> > +   FRAG_RESULT_MAX, /**< Number of fragment program results */
> >  } gl_frag_result;
> > 
> >  const char *gl_frag_result_name(gl_frag_result result);
> > diff --git a/src/intel/vulkan/anv_pipeline.c
> > b/src/intel/vulkan/anv_
> > pipeline.c
> > index 907b24a758d..be007f24e3f 100644
> > --- a/src/intel/vulkan/anv_pipeline.c
> > +++ b/src/intel/vulkan/anv_pipeline.c
> > @@ -872,6 +872,8 @@ anv_pipeline_compile_fs(struct anv_pipeline
> > *pipeline,
> >unsigned num_rts = 0;
> >struct anv_pipeline_binding rt_bindings[8];
> >nir_function_impl *impl = nir_shader_get_entrypoint(nir);
> > +  int map_old_to_new_loc[FRAG_RESULT_MAX];
> > +  memset(map_old_to_new_loc, -1, sizeof(int) *
> > FRAG_RESULT_MAX);
> >nir_foreach_variable_safe(var, >outputs) {
> >   if (var->data.location < FRAG_RESULT_DATA0)
> >  continue;
> > @@ -886,7 +888,13 @@ anv_pipeline_compile_fs(struct anv_pipeline
> > *pipeline,
> >   }
> > 
> >   /* Give it a new, compacted, location */
> > - var->data.location = FRAG_RESULT_DATA0 + num_rts;
> > + if (var->data.location != -1) {
> > 
> 
> How is this even possible?
> 
> 
> > +if (map_old_to_new_loc[var->data.location] == -1)
> > +   map_old_to_new_loc[var->data.location] =
> > FRAG_RESULT_DATA0 + num_rts;
> > +var->data.location = map_old_to_new_loc[var-
> > >data.location];
> > + } else {
> > +var->data.location = FRAG_RESULT_DATA0 + num_rts;
> > + }
> > 
> 
> I see what you are trying to fix.  However, if we're going to get
> composite
> types right, I think we need to do it in three passes:
> 
>  1) Define a `bool rt_used[MAX_RTS]` map and walk over everything and
> flag
> the given RT as used.
>  2) Walk over rt_used and generated a `int rt_to_binding[MAX_RTS]`
> map as
> well as set up the `rt_bindings` map (which is really just a map
> going in
> the other direction).
>  3) Walk the variables again and re-assign locations using
> `rt_to_binding`
> 

I wrote a patch without step 1) as I need to walk the variables for
`rt_bindings` map because of the array lenght.

I am going to send the patch now so you can comment about it.

Sam

> I don't see how any more direct method will actually yield the
> correct
> result in all of the crazy cases such as where you have an array of
> vec2s
> at component 0 and then a bunch of stray floats at components 2 and
> 3.
> 
> Sorry for not responding earlier,
> --Jason
> 
> 
> >   unsigned array_len =
> >  glsl_type_is_array(var->type) ? glsl_get_length(var-
> > >type) :
> > 1;
> > --
> > 2.14.2
> > 
> > ___
> > mesa-dev mailing list
> > mesa-dev@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
> > 
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 12/14] intel/blorp: Add indirect clear color support to mcs_partial_resolve

[Jason Ekstrand]

On Tue, Nov 14, 2017 at 3:28 PM, Lionel Landwerlin <
lionel.g.landwer...@intel.com> wrote:

> On 13/11/17 16:12, Jason Ekstrand wrote:
>
>> This is a bit complicated because we have to get the indirect clear
>> color in there somehow.  In order to not do any more work in the shader
>> than needed, we set it up as it's own vertex binding which points
>> directly at the clear color address specified by the client.
>> ---
>>   src/intel/blorp/blorp_clear.c | 25 +-
>>   src/intel/blorp/blorp_genX_exec.h | 54 ++
>> ++---
>>   src/intel/blorp/blorp_priv.h  |  1 +
>>   3 files changed, 70 insertions(+), 10 deletions(-)
>>
>> diff --git a/src/intel/blorp/blorp_clear.c b/src/intel/blorp/blorp_clear.
>> c
>> index 8e7bc9f..ac582e7 100644
>> --- a/src/intel/blorp/blorp_clear.c
>> +++ b/src/intel/blorp/blorp_clear.c
>> @@ -780,9 +780,18 @@ blorp_ccs_resolve(struct blorp_batch *batch,
>>  batch->blorp->exec(batch, );
>>   }
>>   +static nir_ssa_def *
>> +blorp_nir_bit(nir_builder *b, nir_ssa_def *src, unsigned bit)
>> +{
>> +   return nir_iand(b, nir_ushr(b, src, nir_imm_int(b, bit)),
>> +  nir_imm_int(b, 1));
>> +}
>> +
>>   struct blorp_mcs_partial_resolve_key
>>   {
>>  enum blorp_shader_type shader_type;
>> +   bool indirect_clear_color;
>> +   bool int_format;
>>  uint32_t num_samples;
>>   };
>>   @@ -792,6 +801,8 @@ blorp_params_get_mcs_partial_resolve_kernel(struct
>> blorp_context *blorp,
>>   {
>>  const struct blorp_mcs_partial_resolve_key blorp_key = {
>> .shader_type = BLORP_SHADER_TYPE_MCS_PARTIAL_RESOLVE,
>> +  .indirect_clear_color = params->dst.clear_color_addr.buffer !=
>> NULL,
>> +  .int_format = isl_format_has_int_channel(params->dst.view.format),
>> .num_samples = params->num_samples,
>>  };
>>   @@ -826,7 +837,18 @@ blorp_params_get_mcs_partial_resolve_kernel(struct
>> blorp_context *blorp,
>>  discard->src[0] = nir_src_for_ssa(nir_inot(, is_clear));
>>  nir_builder_instr_insert(, >instr);
>>   -   nir_copy_var(, frag_color, v_color);
>> +   nir_ssa_def *clear_color = nir_load_var(, v_color);
>> +   if (blorp_key.indirect_clear_color && blorp->isl_dev->info->gen <=
>> 8) {
>> +  /* Gen7-8 clear colors are stored as single 0/1 bits */
>> +  clear_color = nir_vec4(, blorp_nir_bit(, clear_color, 31),
>> + blorp_nir_bit(, clear_color, 30),
>> + blorp_nir_bit(, clear_color, 29),
>> + blorp_nir_bit(, clear_color, 28));
>>
>
> Won't this need some swizzling somewhere?
> Either when storing the color in the fast clear colors (behind the aux
> surface) or here in the shader?
>

Good question...  I'll have to think on it more but we probably do.

--Jason


> +
>> +  if (!blorp_key.int_format)
>> + clear_color = nir_i2f32(, clear_color);
>> +   }
>> +   nir_store_var(, frag_color, clear_color, 0xf);
>>struct brw_wm_prog_key wm_key;
>>  brw_blorp_init_wm_prog_key(_key);
>> @@ -872,6 +894,7 @@ blorp_mcs_partial_resolve(struct blorp_batch *batch,
>>params.num_samples = params.dst.surf.samples;
>>  params.num_layers = num_layers;
>> +   params.dst_clear_color_as_input = surf->clear_color_addr.buffer !=
>> NULL;
>>memcpy(_inputs.clear_color,
>> surf->clear_color.f32, sizeof(float) * 4);
>> diff --git a/src/intel/blorp/blorp_genX_exec.h
>> b/src/intel/blorp/blorp_genX_exec.h
>> index 7548392..c3df2d5 100644
>> --- a/src/intel/blorp/blorp_genX_exec.h
>> +++ b/src/intel/blorp/blorp_genX_exec.h
>> @@ -297,7 +297,7 @@ static void
>>   blorp_emit_vertex_buffers(struct blorp_batch *batch,
>> const struct blorp_params *params)
>>   {
>> -   struct GENX(VERTEX_BUFFER_STATE) vb[2];
>> +   struct GENX(VERTEX_BUFFER_STATE) vb[3];
>>  memset(vb, 0, sizeof(vb));
>>struct blorp_address addr;
>> @@ -308,12 +308,20 @@ blorp_emit_vertex_buffers(struct blorp_batch
>> *batch,
>>  blorp_emit_input_varying_data(batch, params, , );
>>  blorp_fill_vertex_buffer_state(batch, vb, 1, addr, size, 0);
>>   -   const unsigned num_dwords = 1 + GENX(VERTEX_BUFFER_STATE_length) *
>> 2;
>> +   uint32_t num_vbs = 2;
>> +   if (params->dst_clear_color_as_input) {
>> +  blorp_fill_vertex_buffer_state(batch, vb, num_vbs++,
>> + params->dst.clear_color_addr,
>> + batch->blorp->isl_dev->ss.cle
>> ar_value_size,
>> + 0);
>> +   }
>> +
>> +   const unsigned num_dwords = 1 + num_vbs *
>> GENX(VERTEX_BUFFER_STATE_length);
>>  uint32_t *dw = blorp_emitn(batch, GENX(3DSTATE_VERTEX_BUFFERS),
>> num_dwords);
>>  if (!dw)
>> return;
>>   -   for (unsigned i = 0; i < 2; i++) {
>> +   for (unsigned i = 0; i < num_vbs; i++) {
>> GENX(VERTEX_BUFFER_STATE_pack)(batch, dw, [i]);
>> dw += 

Re: [Mesa-dev] [AppVeyor] mesa master #6163 failed

[Roland Scheidegger]

Does someone know what's going on with that?

Build started
git clone -q --depth=100 --branch=master
git://anongit.freedesktop.org/mesa/mesa C:\projects\mesa
remote: fatal: unable to read 7a5d62c8e87c50bacaf697e05230ba49a71a0129

remote: aborting due to possible repository corruption on the remote side.
fatal: early EOF
fatal: index-pack failed
Command exited with code 128

I mean there were failures like this before. But now since a couple of
days, this seems to happen at least daily, which is quite annoying.

Roland

Am 15.11.2017 um 03:19 schrieb AppVeyor:
> 
>   Build mesa 6163 failed
>   
> 
> Commit 65123ee62c by Roland Scheidegger  on
> 11/9/2017 6:53 PM:
> r600: set the number type correctly for float rts in cb setup\n\nFloat
> rts were always set as unorm instead of float.\nNot sure of the
> consequences, but at least it looks like the blend clamp\nwould have
> been enabled, which is against the rules (only eg really bothered\nto
> even attempt to specify this correctly, r600 always used clamp
> anyway).\nAlbeit r600 (not r700) setup still looks bugged to me due to
> never setting\nBLEND_FLOAT32 which must be set according to docs...\nNot
> sure if the hw really cares, no piglit change (on
> eg/juniper).\n\nReviewed-by: Dave Airlie 
> 
> Configure your notification preferences
> 
> 
> 
> 
> ___
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
> 

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [AppVeyor] mesa master #6163 failed

[AppVeyor]

Build mesa 6163 failed


Commit 65123ee62c by Roland Scheidegger on 11/9/2017 6:53 PM:

r600: set the number type correctly for float rts in cb setup\n\nFloat rts were always set as unorm instead of float.\nNot sure of the consequences, but at least it looks like the blend clamp\nwould have been enabled, which is against the rules (only eg really bothered\nto even attempt to specify this correctly, r600 always used clamp anyway).\nAlbeit r600 (not r700) setup still looks bugged to me due to never setting\nBLEND_FLOAT32 which must be set according to docs...\nNot sure if the hw really cares, no piglit change (on eg/juniper).\n\nReviewed-by: Dave Airlie 


Configure your notification preferences

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [Bug 103748] [softpipe] pigilt arb_internalformat_query2-image-texture regression

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=103748

--- Comment #1 from Marek Olšák  ---
Not a regression. The test uses GL 3.0 and TBOs are now enabled with 3.0, which
means TBO subtests are enabled for the first time. The test also had some TBO
bugs and might have more. This is untested territory.

-- 
You are receiving this mail because:
You are the assignee for the bug.
You are the QA Contact for the bug.___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] mapi: Use correct shared library name on macOS.

[Dylan Baker]

I think "suffix" would be better for the title "name". Also, library ->
libraries.

With that changed:
Reviewed-by: Dylan Baker 

Quoting Vinson Lee (2017-11-14 17:17:49)
> Signed-off-by: Vinson Lee 
> ---
>  src/mapi/es1api/ABI-check | 7 ++-
>  src/mapi/es2api/ABI-check | 7 ++-
>  2 files changed, 12 insertions(+), 2 deletions(-)
> 
> diff --git a/src/mapi/es1api/ABI-check b/src/mapi/es1api/ABI-check
> index bd9d0288d60d..0a867343c79a 100755
> --- a/src/mapi/es1api/ABI-check
> +++ b/src/mapi/es1api/ABI-check
> @@ -9,7 +9,12 @@ set -eu
>  # or in extensions that are part of the ES 1.1 extension pack.
>  # (see 
> http://www.khronos.org/registry/gles/specs/1.1/opengles_spec_1_1_extension_pack.pdf)
>  
> -LIB=${1-es1api/.libs/libGLESv1_CM.so.1}
> +if [ $(uname) == "Darwin" ]
> +then
> +  LIB=${1-es1api/.libs/libGLESv1_CM.dylib}
> +else
> +  LIB=${1-es1api/.libs/libGLESv1_CM.so.1}
> +fi
>  
>  if ! [ -f "$LIB" ]
>  then
> diff --git a/src/mapi/es2api/ABI-check b/src/mapi/es2api/ABI-check
> index 179bea132e3b..716e6679a49f 100755
> --- a/src/mapi/es2api/ABI-check
> +++ b/src/mapi/es2api/ABI-check
> @@ -6,7 +6,12 @@ set -eu
>  # GL_EXT_multi_draw_arrays
>  # GL_OES_EGL_image
>  
> -LIB=${1-es2api/.libs/libGLESv2.so.2}
> +if [ $(uname) == "Darwin" ]
> +then
> +  LIB=${1-es2api/.libs/libGLESv2.dylib}
> +else
> +  LIB=${1-es2api/.libs/libGLESv2.so.2}
> +fi
>  
>  if ! [ -f "$LIB" ]
>  then
> -- 
> 2.15.0
> 
> ___
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev


signature.asc
Description: signature
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] r600: shader CF_OP_VTX also doesn't use the EOP bit.

[Dave Airlie]

On 15 November 2017 at 04:50, Gert Wollny  wrote:
> Although the EOP bit is documented for the vertex fetch clause, it is not
> properly interpreted. As a result the piglit
>   spec/arb_tessellation_shader/execution/trivial-tess-gs_no-gs-inputs
> creates a TESS_EVAL shader that does not have an EOP clause, which might
> result in a GPU lockup.
>
> This patch forces an additional CF_OP_NOP group like it is already done for
> other final CF_OP groups.

Although I think this is probably a good safety thing to add, I've
sent a patch that should
make it unneeded, it would be good if you could test it.

https://patchwork.freedesktop.org/series/33847/

I'll likely apply this as well at some point, that test however hangs
my cayman with or
without my patch (and your patch doesn't do anything on cayman).

Dave.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH] r600: don't emit vfetch if tess eval isn't accessing any inputs.

[Dave Airlie]

From: Dave Airlie 

This should avoid emitting anything in the shader if we aren't
accessing any inputs.

Signed-off-by: Dave Airlie 
---
 src/gallium/drivers/r600/r600_shader.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/r600/r600_shader.c 
b/src/gallium/drivers/r600/r600_shader.c
index 625537b48b..95a4c05e81 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -3167,7 +3167,8 @@ static int r600_shader_from_tgsi(struct r600_context 
*rctx,
vs_add_primid_output(, key.vs.prim_id_out);
 
if (ctx.type == PIPE_SHADER_TESS_EVAL)
-   r600_fetch_tess_io_info();
+   if (ctx.info.num_inputs)
+   r600_fetch_tess_io_info();
 
while (!tgsi_parse_end_of_tokens()) {
tgsi_parse_token();
-- 
2.14.3

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH] mapi: Use correct shared library name on macOS.

[Vinson Lee]

Signed-off-by: Vinson Lee 
---
 src/mapi/es1api/ABI-check | 7 ++-
 src/mapi/es2api/ABI-check | 7 ++-
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/src/mapi/es1api/ABI-check b/src/mapi/es1api/ABI-check
index bd9d0288d60d..0a867343c79a 100755
--- a/src/mapi/es1api/ABI-check
+++ b/src/mapi/es1api/ABI-check
@@ -9,7 +9,12 @@ set -eu
 # or in extensions that are part of the ES 1.1 extension pack.
 # (see 
http://www.khronos.org/registry/gles/specs/1.1/opengles_spec_1_1_extension_pack.pdf)
 
-LIB=${1-es1api/.libs/libGLESv1_CM.so.1}
+if [ $(uname) == "Darwin" ]
+then
+  LIB=${1-es1api/.libs/libGLESv1_CM.dylib}
+else
+  LIB=${1-es1api/.libs/libGLESv1_CM.so.1}
+fi
 
 if ! [ -f "$LIB" ]
 then
diff --git a/src/mapi/es2api/ABI-check b/src/mapi/es2api/ABI-check
index 179bea132e3b..716e6679a49f 100755
--- a/src/mapi/es2api/ABI-check
+++ b/src/mapi/es2api/ABI-check
@@ -6,7 +6,12 @@ set -eu
 # GL_EXT_multi_draw_arrays
 # GL_OES_EGL_image
 
-LIB=${1-es2api/.libs/libGLESv2.so.2}
+if [ $(uname) == "Darwin" ]
+then
+  LIB=${1-es2api/.libs/libGLESv2.dylib}
+else
+  LIB=${1-es2api/.libs/libGLESv2.so.2}
+fi
 
 if ! [ -f "$LIB" ]
 then
-- 
2.15.0

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 1/2] meson: don't build gallium subdir unless we're building gallium

[Dylan Baker]

This will allow us to simplify some guards within the gallium directory.

Signed-off-by: Dylan Baker 
---
 src/meson.build | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/meson.build b/src/meson.build
index 9232cc4ab18..00bbaa8989c 100644
--- a/src/meson.build
+++ b/src/meson.build
@@ -69,7 +69,9 @@ endif
 if with_egl
   subdir('egl')
 endif
-subdir('gallium')
+if with_gallium
+  subdir('gallium')
+endif
 
 # This must be after at least mesa, glx, and gallium, since libgl will be
 # defined in one of those subdirs depending on the glx provider.
-- 
2.15.0

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 2/2] meson: Guard the gallium dri componenet

[Dylan Baker]

Currently the target has a redundant guard, and the state tracker isn't
properly guarded.

Signed-off-by: Dylan Baker 
---
 src/gallium/meson.build | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/gallium/meson.build b/src/gallium/meson.build
index 7ccf4819079..07a97f72490 100644
--- a/src/gallium/meson.build
+++ b/src/gallium/meson.build
@@ -73,7 +73,9 @@ endif
 if with_glx == 'gallium-xlib'
   subdir('winsys/sw/xlib')
 endif
-subdir('state_trackers/dri')
+if with_dri
+  subdir('state_trackers/dri')
+endif
 if with_osmesa == 'gallium'
   subdir('state_trackers/osmesa')
 endif
@@ -87,7 +89,7 @@ endif
 # TODO: SWR
 # TODO: virgl
 # TODO: clover
-if with_dri and with_gallium
+if with_dri
   subdir('targets/dri')
 endif
 if with_osmesa == 'gallium'
-- 
2.15.0

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] mesa/teximage: add more targets for CompressedTexImage3D

[Nanley Chery]

On Wed, Nov 08, 2017 at 04:52:02PM +0100, Juan A. Suarez Romero wrote:
> From section 8.7, page 179 of OpenGL ES 3.2 spec:
> 
>   An INVALID_OPERATION error is generated by CompressedTexImage3D
>   if internalformat is one of the the formats in table 8.17 and target
>   is not TEXTURE_2D_ARRAY, TEXTURE_CUBE_MAP_ARRAY or TEXTURE_3D.
> 
> So far it was only considering TEXTURE_2D_ARRAY as valid target. Now it
> must consider also TEXTURE_CUBE_MAP_ARRAY and TEXTURE_3D.
> 

Not necessarily. The next sentence after the one you quoted states:

   An INVALID_OPERATION error is generated by CompressedTexImage3D if
   internalformat is TEXTURE_CUBE_MAP_ARRAY and the “Cube Map Array”
   column of table 8.17 is not checked, or if internalformat is
   TEXTURE_3D and the “3D Tex.” column of table 8.17 is not checked.

It seems that the OpenGL ES 3.2 spec has moved towards using a table to
determine valid compressed targets. It hasn't necessarily stated that
TEXTURE_CUBE_MAP_ARRAY and TEXTURE_3D are now valid. Though, by looking
at the table, I think we can conclude that TEXTURE_CUBE_MAP_ARRAY is now
valid.

> This fixes KHR-GLES32.core.texture_cube_map_array.etc2_texture
> ---
>  src/mesa/main/teximage.c | 17 ++---
>  1 file changed, 6 insertions(+), 11 deletions(-)
> 
> diff --git a/src/mesa/main/teximage.c b/src/mesa/main/teximage.c
> index 4ec6148bf42..2799669d28a 100644
> --- a/src/mesa/main/teximage.c
> +++ b/src/mesa/main/teximage.c
> @@ -1403,26 +1403,21 @@ _mesa_target_can_be_compressed(const struct 
> gl_context *ctx, GLenum target,
> * have already been handled by normal ETC2/EAC behavior.
> */
>  
> -  /* From section 3.8.6, page 146 of OpenGL ES 3.0 spec:
> +  /* From section 8.7, page 179 of OpenGL ES 3.2 spec:
> *
> -   *"The ETC2/EAC texture compression algorithm supports only
> -   * two-dimensional images. If internalformat is an ETC2/EAC format,
> -   * glCompressedTexImage3D will generate an INVALID_OPERATION error 
> if
> -   * target is not TEXTURE_2D_ARRAY."
> +   *"An INVALID_OPERATION error is generated by CompressedTexImage3D
> +   * if internalformat is one of the the formats in table 8.17 and 
> target is
> +   * not TEXTURE_2D_ARRAY, TEXTURE_CUBE_MAP_ARRAY or TEXTURE_3D."
> *
> -   * This should also be applicable for glTexStorage3D(). Other available
> -   * targets for these functions are: TEXTURE_3D and 
> TEXTURE_CUBE_MAP_ARRAY.
> +   * This should also be applicable for glTexStorage3D().
> */
> -  if (layout == MESA_FORMAT_LAYOUT_ETC2 && _mesa_is_gles3(ctx))
> -return write_error(error, GL_INVALID_OPERATION);

The OpenGL ES 3.2 spec seems to be adding support for compressed
CUBE_MAP_ARRAYs, and not clarifying what the behavior should have been
in OpenGL ES 3.0. In this case, I think we should have a additional
condition and not replace the existing one.

>target_can_be_compresed = _mesa_has_texture_cube_map_array(ctx);
>break;
> case GL_TEXTURE_3D:
>switch (layout) {
>case MESA_FORMAT_LAYOUT_ETC2:
>   /* See ETC2/EAC comment in case GL_TEXTURE_CUBE_MAP_ARRAY. */
> - if (_mesa_is_gles3(ctx))
> -return write_error(error, GL_INVALID_OPERATION);
> + target_can_be_compresed = GL_TRUE;

None of the formats listed in table 8.17 have their 3D Tex. entry
checked.

-Nanley

>   break;
>case MESA_FORMAT_LAYOUT_BPTC:
>   target_can_be_compresed = 
> ctx->Extensions.ARB_texture_compression_bptc;
> -- 
> 2.13.6
> 
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] r600: fix cubemap arrays

[Roland Scheidegger]

Makes sense.

Reviewed-by: Roland Scheidegger 

Am 14.11.2017 um 23:28 schrieb Dave Airlie:
> From: Dave Airlie 
> 
> A lot of cubemap array piglits fail, port the texture type
> picking code from radeonsi which seems to fix most of them.
> 
> For images I will port the rest of the code.
> 
> Fixes:
> getteximage-depth gl_texture_cube_map_array-*
> fbo-generatemipmap-cubemap array
> getteximage-targets cube_array
> amongst others.
> 
> Signed-off-by: Dave Airlie 
> ---
>  src/gallium/drivers/r600/evergreen_state.c | 26 +-
>  1 file changed, 17 insertions(+), 9 deletions(-)
> 
> diff --git a/src/gallium/drivers/r600/evergreen_state.c 
> b/src/gallium/drivers/r600/evergreen_state.c
> index 68977bb..b02d7ee 100644
> --- a/src/gallium/drivers/r600/evergreen_state.c
> +++ b/src/gallium/drivers/r600/evergreen_state.c
> @@ -169,9 +169,20 @@ static uint32_t r600_translate_blend_factor(int 
> blend_fact)
>   return 0;
>  }
>  
> -static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
> +static unsigned r600_tex_dim(struct r600_texture *rtex,
> +  unsigned view_target, unsigned nr_samples)
>  {
> - switch (dim) {
> + unsigned res_target = rtex->resource.b.b.target;
> +
> + if (view_target == PIPE_TEXTURE_CUBE ||
> + view_target == PIPE_TEXTURE_CUBE_ARRAY)
> + res_target = view_target;
> + /* If interpreting cubemaps as something else, set 2D_ARRAY. */
> + else if (res_target == PIPE_TEXTURE_CUBE ||
> +  res_target == PIPE_TEXTURE_CUBE_ARRAY)
> + res_target = PIPE_TEXTURE_2D_ARRAY;
> +
> + switch (res_target) {
>   default:
>   case PIPE_TEXTURE_1D:
>   return V_03_SQ_TEX_DIM_1D;
> @@ -805,13 +816,10 @@ static int evergreen_fill_tex_resource_words(struct 
> r600_context *rctx,
>   va = tmp->resource.gpu_address;
>  
>   /* array type views and views into array types need to use layer offset 
> */
> - dim = params->target;
> - if (params->target != PIPE_TEXTURE_CUBE)
> - dim = MAX2(params->target, texture->target);
> -
> - tex_resource_words[0] = (S_03_DIM(r600_tex_dim(dim, 
> texture->nr_samples)) |
> -S_03_PITCH((pitch / 8) - 1) |
> -S_03_TEX_WIDTH(width - 1));
> + dim = r600_tex_dim(tmp, params->target, texture->nr_samples);
> + tex_resource_words[0] = (S_03_DIM(dim) |
> +  S_03_PITCH((pitch / 8) - 1) |
> +  S_03_TEX_WIDTH(width - 1));
>   if (rscreen->b.chip_class == CAYMAN)
>   tex_resource_words[0] |= 
> CM_S_03_NON_DISP_TILING_ORDER(non_disp_tiling);
>   else
> 

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 1/2] tgsi: s/unsigned/enum tgsi_texture_type/

[Charmaine Lee]

>From: Brian Paul 
>Sent: Tuesday, November 14, 2017 3:42 PM
>To: mesa-dev@lists.freedesktop.org
>Cc: Charmaine Lee; Neha Bhende
>Subject: [PATCH 1/2] tgsi: s/unsigned/enum tgsi_texture_type/
...

>diff --git a/src/gallium/auxiliary/tgsi/tgsi_util.h 
>b/src/gallium/auxiliary/tgsi/tgsi_util.h
>index 534b5f7..6d56c5b 100644
>--- a/src/gallium/auxiliary/tgsi/tgsi_util.h
>+++ b/src/gallium/auxiliary/tgsi/tgsi_util.h
>@@ -82,24 +82,24 @@ struct tgsi_src_register
> tgsi_util_get_src_from_ind(const struct tgsi_ind_register *reg);

> int
>-tgsi_util_get_texture_coord_dim(unsigned tgsi_tex);
>+tgsi_util_get_texture_coord_dim(enum tgsi_texture_type tgsi_tex);

> int
>-tgsi_util_get_shadow_ref_src_index(unsigned tgsi_tex);
>+tgsi_util_get_shadow_ref_src_index(enum tgsi_texture_type tgsi_tex);

> boolean
>-tgsi_is_shadow_target(unsigned target);
>+tgsi_is_shadow_target(enum tgsi_texture_type);

Lets add the argument name "target" back to be consistent with the rest.

Other than that, this series looks good to me.

Reviewed-by: Charmaine Lee 

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 11/11] docs: update features/relnotes for r600 shader image support.

[Dave Airlie]

From: Dave Airlie 

Signed-off-by: Dave Airlie 
---
 docs/features.txt | 14 +++---
 docs/relnotes/17.4.0.html |  2 ++
 2 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/docs/features.txt b/docs/features.txt
index 86d07ba..f3665de 100644
--- a/docs/features.txt
+++ b/docs/features.txt
@@ -146,19 +146,19 @@ GL 4.1, GLSL 4.10 --- all DONE: i965/gen7+, nvc0, r600, 
radeonsi
   GL_ARB_viewport_array DONE (i965, nv50, 
llvmpipe, softpipe)
 
 
-GL 4.2, GLSL 4.20 -- all DONE: i965/gen7+, nvc0, radeonsi
+GL 4.2, GLSL 4.20 -- all DONE: i965/gen7+, nvc0, r600, radeonsi
 
-  GL_ARB_texture_compression_bptc   DONE (i965, r600)
+  GL_ARB_texture_compression_bptc   DONE (i965)
   GL_ARB_compressed_texture_pixel_storage   DONE (all drivers)
-  GL_ARB_shader_atomic_counters DONE (i965, r600, 
softpipe)
+  GL_ARB_shader_atomic_counters DONE (i965, softpipe)
   GL_ARB_texture_storageDONE (all drivers)
-  GL_ARB_transform_feedback_instanced   DONE (i965, nv50, 
r600, llvmpipe, softpipe, swr)
-  GL_ARB_base_instance  DONE (i965, nv50, 
r600, llvmpipe, softpipe, swr)
+  GL_ARB_transform_feedback_instanced   DONE (i965, nv50, 
llvmpipe, softpipe, swr)
+  GL_ARB_base_instance  DONE (i965, nv50, 
llvmpipe, softpipe, swr)
   GL_ARB_shader_image_load_storeDONE (i965, softpipe)
   GL_ARB_conservative_depth DONE (all drivers that 
support GLSL 1.30)
   GL_ARB_shading_language_420pack   DONE (all drivers that 
support GLSL 1.30)
   GL_ARB_shading_language_packing   DONE (all drivers)
-  GL_ARB_internalformat_query   DONE (i965, nv50, 
r600, llvmpipe, softpipe, swr)
+  GL_ARB_internalformat_query   DONE (i965, nv50, 
llvmpipe, softpipe, swr)
   GL_ARB_map_buffer_alignment   DONE (all drivers)
 
 
@@ -178,7 +178,7 @@ GL 4.3, GLSL 4.30 -- all DONE: i965/gen8+, nvc0, radeonsi
   GL_ARB_multi_draw_indirectDONE (i965, r600, 
llvmpipe, softpipe, swr)
   GL_ARB_program_interface_queryDONE (all drivers)
   GL_ARB_robust_buffer_access_behavior  DONE (i965)
-  GL_ARB_shader_image_size  DONE (i965, softpipe)
+  GL_ARB_shader_image_size  DONE (i965, r600, 
softpipe)
   GL_ARB_shader_storage_buffer_object   DONE (i965, softpipe)
   GL_ARB_stencil_texturing  DONE (i965/hsw+, nv50, 
r600, llvmpipe, softpipe, swr)
   GL_ARB_texture_buffer_range   DONE (nv50, i965, 
r600, llvmpipe)
diff --git a/docs/relnotes/17.4.0.html b/docs/relnotes/17.4.0.html
index 19e0c80..12a4864 100644
--- a/docs/relnotes/17.4.0.html
+++ b/docs/relnotes/17.4.0.html
@@ -46,6 +46,8 @@ Note: some of the new features are only available with 
certain drivers.
 
 Disk shader cache support for i965 when MESA_GLSL_CACHE_DISABLE 
environment variable is set to "0" or "false"
 GL_ARB_shader_atomic_counters and GL_ARB_shader_atomic_counter_ops on 
r600/evergreen+
+GL_ARB_shader_image_load_store and GL_ARB_shader_image_size on 
r600/evergreen+
+OpenGL 4.2 on r600/evergreen with hw fp64 support
 
 
 Bug fixes
-- 
2.9.5

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 05/11] r600/shader: implement getting thread id.

[Dave Airlie]

From: Dave Airlie 

We need the thread id to use the immediate buffer readback
mechanism, so add support for calculating it.

Signed-off-by: Dave Airlie 
---
 src/gallium/drivers/r600/r600_shader.c | 74 ++
 1 file changed, 74 insertions(+)

diff --git a/src/gallium/drivers/r600/r600_shader.c 
b/src/gallium/drivers/r600/r600_shader.c
index 3da0be3..73baa07 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -353,6 +353,7 @@ struct r600_shader_ctx {
unsignedenabled_stream_buffers_mask;
unsignedtess_input_info; /* temp with 
tess input offsets */
unsignedtess_output_info; /* temp with 
tess input offsets */
+   unsignedthread_id_gpr; /* temp with 
thread id calculated for images */
 };
 
 struct r600_shader_tgsi_instruction {
@@ -2935,6 +2936,69 @@ static int r600_emit_tess_factor(struct r600_shader_ctx 
*ctx)
return 0;
 }
 
+/*
+ * We have to work out the thread ID for load and atomic
+ * operations, which store the returned value to an index
+ * in an intermediate buffer.
+ * The index is calculated by taking the thread id,
+ * calculated from the MBCNT instructions.
+ * Then the shader engine ID is multiplied by 256,
+ * and the wave id is added.
+ * Then the result is multipled by 64 and thread id is
+ * added.
+ */
+static int load_thread_id_gpr(struct r600_shader_ctx *ctx)
+{
+   struct r600_bytecode_alu alu;
+   int r;
+
+   memset(, 0, sizeof(struct r600_bytecode_alu));
+   alu.op = ALU_OP1_MBCNT_32LO_ACCUM_PREV_INT;
+   alu.dst.sel = ctx->temp_reg;
+   alu.dst.chan = 0;
+   alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
+   alu.src[0].value = 0x;
+   alu.dst.write = 1;
+   r = r600_bytecode_add_alu(ctx->bc, );
+   if (r)
+   return r;
+
+   memset(, 0, sizeof(struct r600_bytecode_alu));
+   alu.op = ALU_OP1_MBCNT_32HI_INT;
+   alu.dst.sel = ctx->temp_reg;
+   alu.dst.chan = 1;
+   alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
+   alu.src[0].value = 0x;
+   alu.dst.write = 1;
+   r = r600_bytecode_add_alu(ctx->bc, );
+   if (r)
+   return r;
+
+   memset(, 0, sizeof(struct r600_bytecode_alu));
+   alu.op = ALU_OP3_MULADD_UINT24;
+   alu.dst.sel = ctx->temp_reg;
+   alu.dst.chan = 2;
+   alu.src[0].sel = EG_V_SQ_ALU_SRC_SE_ID;
+   alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
+   alu.src[1].value = 256;
+   alu.src[2].sel = EG_V_SQ_ALU_SRC_HW_WAVE_ID;
+   alu.dst.write = 1;
+   alu.is_op3 = 1;
+   alu.last = 1;
+   r = r600_bytecode_add_alu(ctx->bc, );
+   if (r)
+   return r;
+
+   r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
+  ctx->thread_id_gpr, 1,
+  ctx->temp_reg, 2,
+  V_SQ_ALU_SRC_LITERAL, 0x40,
+  ctx->temp_reg, 0);
+   if (r)
+   return r;
+   return 0;
+}
+
 static int r600_shader_from_tgsi(struct r600_context *rctx,
 struct r600_pipe_shader *pipeshader,
 union r600_shader_key key)
@@ -3138,6 +3202,12 @@ static int r600_shader_from_tgsi(struct r600_context 
*rctx,
ctx.temp_reg = ctx.bc->ar_reg + 3;
}
 
+   if (shader->uses_images && ctx.type == PIPE_SHADER_FRAGMENT) {
+   ctx.thread_id_gpr = ctx.temp_reg;
+   ctx.temp_reg++;
+   } else
+   ctx.thread_id_gpr = 0;
+
shader->max_arrays = 0;
shader->num_arrays = 0;
if (indirect_gprs) {
@@ -3281,6 +3351,10 @@ static int r600_shader_from_tgsi(struct r600_context 
*rctx,
}
}
 
+   if (ctx.thread_id_gpr) {
+   load_thread_id_gpr();
+   }
+
if (ctx.type == PIPE_SHADER_GEOMETRY) {
struct r600_bytecode_alu alu;
int r;
-- 
2.9.5

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 02/11] r600: allocate immed buffer resource for images.

[Dave Airlie]

From: Dave Airlie 

In order to image readback we have to execute a MEM_RAT instruction
that needs a buffer to transfer the result into until the shader
can fetch it.

Signed-off-by: Dave Airlie 
---
 src/gallium/drivers/r600/r600_buffer_common.c |  2 ++
 src/gallium/drivers/r600/r600_pipe_common.h   |  9 +
 src/gallium/drivers/r600/r600_texture.c   | 10 ++
 3 files changed, 21 insertions(+)

diff --git a/src/gallium/drivers/r600/r600_buffer_common.c 
b/src/gallium/drivers/r600/r600_buffer_common.c
index a6e3b7f..35a7023 100644
--- a/src/gallium/drivers/r600/r600_buffer_common.c
+++ b/src/gallium/drivers/r600/r600_buffer_common.c
@@ -251,6 +251,7 @@ static void r600_buffer_destroy(struct pipe_screen *screen,
 
threaded_resource_deinit(buf);
util_range_destroy(>valid_buffer_range);
+   pipe_resource_reference((struct pipe_resource**)>immed_buffer, 
NULL);
pb_reference(>buf, NULL);
FREE(rbuffer);
 }
@@ -606,6 +607,7 @@ r600_alloc_buffer_struct(struct pipe_screen *screen,
 
rbuffer->buf = NULL;
rbuffer->bind_history = 0;
+   rbuffer->immed_buffer = NULL;
util_range_init(>valid_buffer_range);
return rbuffer;
 }
diff --git a/src/gallium/drivers/r600/r600_pipe_common.h 
b/src/gallium/drivers/r600/r600_pipe_common.h
index a6406cf..c8b971a 100644
--- a/src/gallium/drivers/r600/r600_pipe_common.h
+++ b/src/gallium/drivers/r600/r600_pipe_common.h
@@ -171,6 +171,12 @@ struct r600_resource {
/* Whether this resource is referenced by bindless handles. */
booltexture_handle_allocated;
boolimage_handle_allocated;
+
+   /*
+* EG/Cayman only - for RAT operations hw need an immediate buffer
+* to store results in.
+*/
+   struct r600_resource*immed_buffer;
 };
 
 struct r600_transfer {
@@ -773,6 +779,9 @@ void evergreen_do_fast_color_clear(struct 
r600_common_context *rctx,
   const union pipe_color_union *color);
 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen);
 void r600_init_context_texture_functions(struct r600_common_context *rctx);
+void eg_resource_alloc_immed(struct r600_common_screen *rscreen,
+struct r600_resource *res,
+unsigned immed_size);
 
 /* r600_viewport.c */
 void evergreen_apply_scissor_bug_workaround(struct r600_common_context *rctx,
diff --git a/src/gallium/drivers/r600/r600_texture.c 
b/src/gallium/drivers/r600/r600_texture.c
index 3515d97..ee6ed64 100644
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -559,6 +559,7 @@ static void r600_texture_destroy(struct pipe_screen *screen,
struct r600_resource *resource = >resource;
 
r600_texture_reference(>flushed_depth_texture, NULL);
+   pipe_resource_reference((struct 
pipe_resource**)>immed_buffer, NULL);
 
if (rtex->cmask_buffer != >resource) {
r600_resource_reference(>cmask_buffer, NULL);
@@ -718,6 +719,15 @@ static void r600_texture_alloc_cmask_separate(struct 
r600_common_screen *rscreen
p_atomic_inc(>compressed_colortex_counter);
 }
 
+void eg_resource_alloc_immed(struct r600_common_screen *rscreen,
+struct r600_resource *res,
+unsigned immed_size)
+{
+   res->immed_buffer = (struct r600_resource *)
+   pipe_buffer_create(>b, PIPE_BIND_CUSTOM,
+  PIPE_USAGE_DEFAULT, immed_size);
+}
+
 static void r600_texture_get_htile_size(struct r600_common_screen *rscreen,
struct r600_texture *rtex)
 {
-- 
2.9.5

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 08/11] r600/sb: disable SB for images.

[Dave Airlie]

From: Dave Airlie 

Until we can work further on sb, disable it for images for now.

Signed-off-by: Dave Airlie 
---
 src/gallium/drivers/r600/r600_shader.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/gallium/drivers/r600/r600_shader.c 
b/src/gallium/drivers/r600/r600_shader.c
index d7cb52e..17b0099 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -195,6 +195,7 @@ int r600_pipe_shader_create(struct pipe_context *ctx,
use_sb &= !shader->shader.uses_doubles;
 
use_sb &= !shader->shader.uses_atomics;
+   use_sb &= !shader->shader.uses_images;
 
/* Check if the bytecode has already been built. */
if (!shader->shader.bc.bytecode) {
-- 
2.9.5

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 10/11] r600: enable ARB_shader_image_load_store, ARB_shader_image_size

[Dave Airlie]

From: Dave Airlie 

This also enables GL4.2 for gpus with hw fp64 (cayman, cypress)

Signed-off-by: Dave Airlie 
---
 src/gallium/drivers/r600/r600_pipe.c | 12 +---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_pipe.c 
b/src/gallium/drivers/r600/r600_pipe.c
index 96017dc..a232ee4 100644
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -332,7 +332,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum 
pipe_cap param)
 
case PIPE_CAP_GLSL_FEATURE_LEVEL:
if (family >= CHIP_CEDAR)
-  return 410;
+  return 420;
/* pre-evergreen geom shaders need newer kernel */
if (rscreen->b.info.drm_minor >= 37)
   return 330;
@@ -362,6 +362,9 @@ static int r600_get_param(struct pipe_screen* pscreen, enum 
pipe_cap param)
case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
return family >= CHIP_CEDAR ? 0 : 1;
 
+   case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
+   return 8;
+
/* Unsupported features. */
case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
@@ -409,7 +412,6 @@ static int r600_get_param(struct pipe_screen* pscreen, enum 
pipe_cap param)
case PIPE_CAP_LOAD_CONSTBUF:
case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
case PIPE_CAP_TILE_RASTER_ORDER:
-   case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
return 0;
 
@@ -607,10 +609,14 @@ static int r600_get_shader_param(struct pipe_screen* 
pscreen,
case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
-   case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
return 0;
+   case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
+   if (rscreen->b.family >= CHIP_CEDAR &&
+   (shader == PIPE_SHADER_FRAGMENT))
+   return 8;
+   return 0;
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
if (rscreen->b.family >= CHIP_CEDAR && rscreen->has_atomics)
return 8;
-- 
2.9.5

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 03/11] r600: implement basic memory barrier.

[Dave Airlie]

From: Dave Airlie 

This isn't 100% perfect (fglrx also fails a bunch of those tests)
but implement the start of a memory barrier for image support.

Signed-off-by: Dave Airlie 
---
 src/gallium/drivers/r600/r600_pipe_common.c  |  5 -
 src/gallium/drivers/r600/r600_state_common.c | 24 
 2 files changed, 24 insertions(+), 5 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_pipe_common.c 
b/src/gallium/drivers/r600/r600_pipe_common.c
index e2d0e32..23f7d74 100644
--- a/src/gallium/drivers/r600/r600_pipe_common.c
+++ b/src/gallium/drivers/r600/r600_pipe_common.c
@@ -321,10 +321,6 @@ void r600_need_dma_space(struct r600_common_context *ctx, 
unsigned num_dw,
ctx->num_dma_calls++;
 }
 
-static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
-{
-}
-
 void r600_preflush_suspend_features(struct r600_common_context *ctx)
 {
/* suspend queries */
@@ -664,7 +660,6 @@ bool r600_common_context_init(struct r600_common_context 
*rctx,
rctx->b.transfer_flush_region = u_transfer_flush_region_vtbl;
rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
rctx->b.texture_subdata = u_default_texture_subdata;
-   rctx->b.memory_barrier = r600_memory_barrier;
rctx->b.flush = r600_flush_from_st;
rctx->b.set_debug_callback = r600_set_debug_callback;
rctx->b.fence_server_sync = r600_fence_server_sync;
diff --git a/src/gallium/drivers/r600/r600_state_common.c 
b/src/gallium/drivers/r600/r600_state_common.c
index ead5b86..4ae18fc 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -91,6 +91,29 @@ void r600_emit_alphatest_state(struct r600_context *rctx, 
struct r600_atom *atom
radeon_set_context_reg(cs, R_028438_SX_ALPHA_REF, alpha_ref);
 }
 
+static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
+{
+   struct r600_context *rctx = (struct r600_context *)ctx;
+   if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
+   rctx->b.flags |= R600_CONTEXT_INV_CONST_CACHE;
+
+   if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
+PIPE_BARRIER_SHADER_BUFFER |
+PIPE_BARRIER_TEXTURE |
+PIPE_BARRIER_IMAGE |
+PIPE_BARRIER_STREAMOUT_BUFFER |
+PIPE_BARRIER_GLOBAL_BUFFER)) {
+   rctx->b.flags |= R600_CONTEXT_INV_VERTEX_CACHE|
+   R600_CONTEXT_INV_TEX_CACHE;
+   }
+
+   if (flags & (PIPE_BARRIER_FRAMEBUFFER|
+PIPE_BARRIER_IMAGE))
+   rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV;
+
+   rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
+}
+
 static void r600_texture_barrier(struct pipe_context *ctx, unsigned flags)
 {
struct r600_context *rctx = (struct r600_context *)ctx;
@@ -3014,6 +3037,7 @@ void r600_init_common_state_functions(struct r600_context 
*rctx)
rctx->b.b.set_vertex_buffers = r600_set_vertex_buffers;
rctx->b.b.set_sampler_views = r600_set_sampler_views;
rctx->b.b.sampler_view_destroy = r600_sampler_view_destroy;
+   rctx->b.b.memory_barrier = r600_memory_barrier;
rctx->b.b.texture_barrier = r600_texture_barrier;
rctx->b.b.set_stream_output_targets = r600_set_streamout_targets;
rctx->b.b.set_active_query_state = r600_set_active_query_state;
-- 
2.9.5

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 07/11] r600/shader: add support for load/store/atomic ops on images.

[Dave Airlie]

From: Dave Airlie 

This adds support to the shader assembler for load/store/atomic
ops on images which are handled via the RAT operations.

Signed-off-by: Dave Airlie 
---
 src/gallium/drivers/r600/r600_shader.c | 316 -
 1 file changed, 312 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_shader.c 
b/src/gallium/drivers/r600/r600_shader.c
index 73baa07..d7cb52e 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -969,6 +969,7 @@ static int tgsi_declaration(struct r600_shader_ctx *ctx)
case TGSI_FILE_SAMPLER:
case TGSI_FILE_SAMPLER_VIEW:
case TGSI_FILE_ADDRESS:
+   case TGSI_FILE_IMAGE:
break;
 
case TGSI_FILE_HW_ATOMIC:
@@ -3074,6 +3075,7 @@ static int r600_shader_from_tgsi(struct r600_context 
*rctx,
case PIPE_SHADER_FRAGMENT:
shader->two_side = key.ps.color_two_side;
shader->atomic_base = key.ps.first_atomic_counter;
+   shader->rat_base = key.ps.nr_cbufs;
break;
default:
break;
@@ -7779,14 +7781,318 @@ static int tgsi_load_gds(struct r600_shader_ctx *ctx)
return 0;
 }
 
+/* this fixes up 1D arrays properly */
+static int load_index_src(struct r600_shader_ctx *ctx, int src_index, int 
*idx_gpr)
+{
+   struct tgsi_full_instruction *inst = 
>parse.FullToken.FullInstruction;
+   int r, i;
+   struct r600_bytecode_alu alu;
+   int temp_reg = r600_get_temp(ctx);
+
+   for (i = 0; i < 4; i++) {
+   bool def_val = true, write_zero = false;
+   memset(, 0, sizeof(struct r600_bytecode_alu));
+   alu.op = ALU_OP1_MOV;
+   alu.dst.sel = temp_reg;
+   alu.dst.chan = i;
+
+   switch (inst->Memory.Texture) {
+   case TGSI_TEXTURE_BUFFER:
+   case TGSI_TEXTURE_1D:
+   if (i == 1 || i == 2 || i == 3) {
+   write_zero = true;
+   }
+   break;
+   case TGSI_TEXTURE_1D_ARRAY:
+   if (i == 1 || i == 3)
+   write_zero = true;
+   else if (i == 2) {
+   r600_bytecode_src([0], 
>src[src_index], 1);
+   def_val = false;
+   }
+   break;
+   case TGSI_TEXTURE_2D:
+   if (i == 2 || i == 3)
+   write_zero = true;
+   break;
+   default:
+   if (i == 3)
+   write_zero = true;
+   break;
+   }
+
+   if (write_zero) {
+   alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
+   alu.src[0].value = 0;
+   } else if (def_val) {
+   r600_bytecode_src([0], >src[src_index], i);
+   }
+
+   if (i == 3)
+   alu.last = 1;
+   alu.dst.write = 1;
+   r = r600_bytecode_add_alu(ctx->bc, );
+   if (r)
+   return r;
+   }
+   *idx_gpr = temp_reg;
+   return 0;
+}
+
+static int tgsi_load_rat(struct r600_shader_ctx *ctx)
+{
+   struct tgsi_full_instruction *inst = 
>parse.FullToken.FullInstruction;
+   /* have to work out the offset into the RAT immediate return buffer */
+   struct r600_bytecode_vtx vtx;
+   struct r600_bytecode_cf *cf;
+   int r;
+   int idx_gpr;
+   unsigned format, num_format, format_comp, endian;
+   const struct util_format_description *desc;
+   unsigned rat_index_mode;
+   unsigned immed_base;
+
+   rat_index_mode = inst->Src[0].Indirect.Index == 2 ? 2 : 0; // 
CF_INDEX_1 : CF_INDEX_NONE
+
+   immed_base = R600_IMAGE_IMMED_RESOURCE_OFFSET;
+   r = load_index_src(ctx, 1, _gpr);
+   if (r)
+   return r;
+
+   r600_bytecode_add_cfinst(ctx->bc, CF_OP_MEM_RAT);
+   cf = ctx->bc->cf_last;
+
+   cf->rat.id = ctx->shader->rat_base + inst->Src[0].Register.Index;
+   cf->rat.inst = V_RAT_INST_NOP_RTN;
+   cf->rat.index_mode = rat_index_mode;
+   cf->output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_READ_IND;
+   cf->output.gpr = ctx->thread_id_gpr;
+   cf->output.index_gpr = idx_gpr;
+   cf->output.comp_mask = 0xf;
+   cf->output.burst_count = 1;
+   cf->vpm = 1;
+   cf->barrier = 1;
+   cf->mark = 1;
+   cf->output.elem_size = 0;
+
+   r600_bytecode_add_cfinst(ctx->bc, CF_OP_WAIT_ACK);
+   cf = ctx->bc->cf_last;
+   cf->barrier = 1;
+
+   desc = util_format_description(inst->Memory.Format);
+   r600_vertex_data_type(inst->Memory.Format,
+ , _format, 

[Mesa-dev] [PATCH 01/11] r600: handle writes_memory properly

[Dave Airlie]

From: Dave Airlie 

This implements proper handling for shaders with side effects.

Signed-off-by: Dave Airlie 
---
 src/gallium/drivers/r600/evergreen_state.c | 10 +++---
 src/gallium/drivers/r600/evergreend.h  |  6 ++
 2 files changed, 13 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/r600/evergreen_state.c 
b/src/gallium/drivers/r600/evergreen_state.c
index b02d7ee..6920b74 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -3168,8 +3168,12 @@ void evergreen_update_ps_state(struct pipe_context *ctx, 
struct r600_pipe_shader
db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(stencil_export);
db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(mask_export);
 
-   if 
(shader->selector->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL])
-   db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1);
+   if 
(shader->selector->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
+   db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
+   
S_02880C_EXEC_ON_NOOP(shader->selector->info.writes_memory);
+   } else if (shader->selector->info.writes_memory) {
+   db_shader_control |= S_02880C_EXEC_ON_HIER_FAIL(1);
+   }
 
switch (rshader->ps_conservative_z) {
default: /* fall through */
@@ -3487,7 +3491,7 @@ void evergreen_update_db_shader_control(struct 
r600_context * rctx)
 * get a hang unless you flush the DB in between.  For now just use
 * LATE_Z.
 */
-   if (rctx->alphatest_state.sx_alpha_test_control) {
+   if (rctx->alphatest_state.sx_alpha_test_control || 
rctx->ps_shader->info.writes_memory) {
db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
} else {
db_shader_control |= 
S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
diff --git a/src/gallium/drivers/r600/evergreend.h 
b/src/gallium/drivers/r600/evergreend.h
index af79bb7..f8a256c 100644
--- a/src/gallium/drivers/r600/evergreend.h
+++ b/src/gallium/drivers/r600/evergreend.h
@@ -988,6 +988,12 @@
 #define   S_02880C_DUAL_EXPORT_ENABLE(x)   (((unsigned)(x) & 0x1) 
<< 9)
 #define   G_02880C_DUAL_EXPORT_ENABLE(x)   (((x) >> 9) & 0x1)
 #define   C_02880C_DUAL_EXPORT_ENABLE  0xFDFF
+#define   S_02880C_EXEC_ON_HIER_FAIL(x)(((unsigned)(x) & 0x1) 
<< 10)
+#define   G_02880C_EXEC_ON_HIER_FAIL(x)(((x) >> 10) & 0x1)
+#define   C_02880C_EXEC_ON_HIER_FAIL   0xFBFF
+#define   S_02880C_EXEC_ON_NOOP(x) (((unsigned)(x) & 0x1) 
<< 11)
+#define   G_02880C_EXEC_ON_NOOP(x) (((x) >> 11) & 0x1)
+#define   C_02880C_EXEC_ON_NOOP0xF7FF
 #define   S_02880C_DB_SOURCE_FORMAT(x) (((unsigned)(x) & 0x3) 
<< 13)
 #define   G_02880C_DB_SOURCE_FORMAT(x) (((x) >> 13) & 0x3)
 #define   C_02880C_DB_SOURCE_FORMAT0x9FFF
-- 
2.9.5

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 09/11] r600: handle image size support.

[Dave Airlie]

From: Dave Airlie 

This adds support for the RESQ opcode with the workaround
required due to hw bugs for buffers and cube arrays.

Signed-off-by: Dave Airlie 
---
 src/gallium/drivers/r600/r600_shader.c   | 78 ++--
 src/gallium/drivers/r600/r600_shader.h   |  2 +
 src/gallium/drivers/r600/r600_state_common.c | 30 +--
 3 files changed, 101 insertions(+), 9 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_shader.c 
b/src/gallium/drivers/r600/r600_shader.c
index 17b0099..37a8cea 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -3077,6 +3077,7 @@ static int r600_shader_from_tgsi(struct r600_context 
*rctx,
shader->two_side = key.ps.color_two_side;
shader->atomic_base = key.ps.first_atomic_counter;
shader->rat_base = key.ps.nr_cbufs;
+   shader->image_size_const_offset = 
key.ps.image_size_const_offset;
break;
default:
break;
@@ -6809,12 +6810,12 @@ static int do_vtx_fetch_inst(struct r600_shader_ctx 
*ctx, boolean src_requires_l
return 0;
 }
 
-static int r600_do_buffer_txq(struct r600_shader_ctx *ctx)
+static int r600_do_buffer_txq(struct r600_shader_ctx *ctx, int reg_idx, int 
offset)
 {
struct tgsi_full_instruction *inst = 
>parse.FullToken.FullInstruction;
struct r600_bytecode_alu alu;
int r;
-   int id = tgsi_tex_get_src_gpr(ctx, 1);
+   int id = tgsi_tex_get_src_gpr(ctx, reg_idx) + offset;
 
memset(, 0, sizeof(struct r600_bytecode_alu));
alu.op = ALU_OP1_MOV;
@@ -6891,7 +6892,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
if (inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ) {
ctx->shader->uses_tex_buffers = true;
-   return r600_do_buffer_txq(ctx);
+   return r600_do_buffer_txq(ctx, 1, 0);
}
else if (inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
if (ctx->bc->chip_class < EVERGREEN)
@@ -8199,6 +8200,73 @@ static int tgsi_atomic_op(struct r600_shader_ctx *ctx)
return 0;
 }
 
+static int tgsi_resq(struct r600_shader_ctx *ctx)
+{
+   struct tgsi_full_instruction *inst = 
>parse.FullToken.FullInstruction;
+   unsigned sampler_index_mode;
+   struct r600_bytecode_tex tex;
+   int r;
+   boolean has_txq_cube_array_z = false;
+
+   if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
+   ctx->shader->uses_tex_buffers = true;
+   return r600_do_buffer_txq(ctx, 0, 
ctx->shader->image_size_const_offset);
+   }
+
+   if (inst->Memory.Texture == TGSI_TEXTURE_CUBE_ARRAY &&
+   inst->Dst[0].Register.WriteMask & 4) {
+   ctx->shader->has_txq_cube_array_z_comp = true;
+   has_txq_cube_array_z = true;
+   }
+
+   sampler_index_mode = inst->Src[0].Indirect.Index == 2 ? 2 : 0; // 
CF_INDEX_1 : CF_INDEX_NONE
+   if (sampler_index_mode)
+   egcm_load_index_reg(ctx->bc, 1, false);
+
+
+   /* does this shader want a num layers from TXQ for a cube array? */
+   if (has_txq_cube_array_z) {
+   int id = tgsi_tex_get_src_gpr(ctx, 0) + 
ctx->shader->image_size_const_offset;
+   struct r600_bytecode_alu alu;
+
+   memset(, 0, sizeof(struct r600_bytecode_alu));
+   alu.op = ALU_OP1_MOV;
+
+   alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
+   /* channel 1 or 3 of each word */
+   alu.src[0].sel += (id / 2);
+   alu.src[0].chan = ((id % 2) * 2) + 1;
+   alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
+   tgsi_dst(ctx, >Dst[0], 2, );
+   alu.last = 1;
+   r = r600_bytecode_add_alu(ctx->bc, );
+   if (r)
+   return r;
+   /* disable writemask from texture instruction */
+   inst->Dst[0].Register.WriteMask &= ~4;
+   }
+   memset(, 0, sizeof(struct r600_bytecode_tex));
+   tex.op = ctx->inst_info->op;
+   tex.sampler_id = R600_IMAGE_REAL_RESOURCE_OFFSET + 
inst->Src[0].Register.Index;
+   tex.sampler_index_mode = sampler_index_mode;
+   tex.resource_id = tex.sampler_id;
+   tex.resource_index_mode = sampler_index_mode;
+   tex.src_sel_x = 4;
+   tex.src_sel_y = 4;
+   tex.src_sel_z = 4;
+   tex.src_sel_w = 4;
+   tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
+   tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
+   tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
+   tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
+   tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + 
inst->Dst[0].Register.Index;

[Mesa-dev] [PATCH 04/11] r600/shader: add flag to denote if shader uses images

[Dave Airlie]

From: Dave Airlie 

Signed-off-by: Dave Airlie 
---
 src/gallium/drivers/r600/r600_shader.c | 1 +
 src/gallium/drivers/r600/r600_shader.h | 1 +
 2 files changed, 2 insertions(+)

diff --git a/src/gallium/drivers/r600/r600_shader.c 
b/src/gallium/drivers/r600/r600_shader.c
index 0fa2a1f..3da0be3 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -2971,6 +2971,7 @@ static int r600_shader_from_tgsi(struct r600_context 
*rctx,
shader->uses_atomics = ctx.info.file_mask[TGSI_FILE_HW_ATOMIC];
shader->nsys_inputs = 0;
 
+   shader->uses_images = ctx.info.file_count[TGSI_FILE_IMAGE] > 0;
indirect_gprs = ctx.info.indirect_files & ~((1 << TGSI_FILE_CONSTANT) | 
(1 << TGSI_FILE_SAMPLER));
tgsi_parse_init(, tokens);
ctx.type = ctx.info.processor;
diff --git a/src/gallium/drivers/r600/r600_shader.h 
b/src/gallium/drivers/r600/r600_shader.h
index 40719d9..c6efbb9 100644
--- a/src/gallium/drivers/r600/r600_shader.h
+++ b/src/gallium/drivers/r600/r600_shader.h
@@ -116,6 +116,7 @@ struct r600_shader {
 
boolean uses_doubles;
boolean uses_atomics;
+   boolean uses_images;
uint8_t atomic_base;
 };
 
-- 
2.9.5

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 06/11] r600: add core pieces of image support.

[Dave Airlie]

From: Dave Airlie 

This adds the atoms and gallium api implementations,
along with support for compress/decompress paths for
shader images.

Signed-off-by: Dave Airlie 
---
 src/gallium/drivers/r600/evergreen_state.c   | 294 ++-
 src/gallium/drivers/r600/r600_blit.c |  59 ++
 src/gallium/drivers/r600/r600_hw_context.c   |   2 +
 src/gallium/drivers/r600/r600_pipe.h |  45 +++-
 src/gallium/drivers/r600/r600_shader.h   |   1 +
 src/gallium/drivers/r600/r600_state_common.c |  30 +++
 6 files changed, 428 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/r600/evergreen_state.c 
b/src/gallium/drivers/r600/evergreen_state.c
index 6920b74..ae7dc76 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1673,6 +1673,104 @@ static void evergreen_emit_msaa_state(struct 
r600_context *rctx, int nr_samples,
}
 }
 
+static void evergreen_emit_image_state(struct r600_context *rctx, struct 
r600_atom *atom,
+  int immed_id_base, int res_id_base)
+{
+   struct r600_image_state *state = (struct r600_image_state *)atom;
+   struct pipe_framebuffer_state *fb_state = >framebuffer.state;
+   struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
+   struct r600_texture *rtex;
+   struct r600_resource *resource;
+   uint32_t pkt_flags = 0;
+   int i;
+
+   for (i = 0; i < R600_MAX_IMAGES; i++) {
+   struct r600_image_view *image = >views[i];
+   unsigned reloc, immed_reloc;
+   int idx = i;
+
+   idx += fb_state->nr_cbufs + (rctx->dual_src_blend ? 1 : 0);
+   if (!image->base.resource)
+   continue;
+
+   resource = (struct r600_resource *)image->base.resource;
+   if (resource->b.b.target != PIPE_BUFFER)
+   rtex = (struct r600_texture *)image->base.resource;
+   else
+   rtex = NULL;
+
+   reloc = radeon_add_to_buffer_list(>b,
+ >b.gfx,
+ resource,
+ RADEON_USAGE_READWRITE,
+ RADEON_PRIO_SHADER_RW_BUFFER);
+
+   immed_reloc = radeon_add_to_buffer_list(>b,
+   >b.gfx,
+   resource->immed_buffer,
+   RADEON_USAGE_READWRITE,
+   
RADEON_PRIO_SHADER_RW_BUFFER);
+
+   radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + idx * 
0x3C, 13);
+
+   radeon_emit(cs, image->cb_color_base);  /* 
R_028C60_CB_COLOR0_BASE */
+   radeon_emit(cs, image->cb_color_pitch); /* 
R_028C64_CB_COLOR0_PITCH */
+   radeon_emit(cs, image->cb_color_slice); /* 
R_028C68_CB_COLOR0_SLICE */
+   radeon_emit(cs, image->cb_color_view);  /* 
R_028C6C_CB_COLOR0_VIEW */
+   radeon_emit(cs, image->cb_color_info); /* 
R_028C70_CB_COLOR0_INFO */
+   radeon_emit(cs, image->cb_color_attrib);/* 
R_028C74_CB_COLOR0_ATTRIB */
+   radeon_emit(cs, image->cb_color_dim);   /* 
R_028C78_CB_COLOR0_DIM */
+   radeon_emit(cs, rtex ? rtex->cmask.base_address_reg : 
image->cb_color_base);/* R_028C7C_CB_COLOR0_CMASK */
+   radeon_emit(cs, rtex ? rtex->cmask.slice_tile_max : 0); /* 
R_028C80_CB_COLOR0_CMASK_SLICE */
+   radeon_emit(cs, image->cb_color_fmask); /* 
R_028C84_CB_COLOR0_FMASK */
+   radeon_emit(cs, image->cb_color_fmask_slice); /* 
R_028C88_CB_COLOR0_FMASK_SLICE */
+   radeon_emit(cs, rtex ? rtex->color_clear_value[0] : 0); /* 
R_028C8C_CB_COLOR0_CLEAR_WORD0 */
+   radeon_emit(cs, rtex ? rtex->color_clear_value[1] : 0); /* 
R_028C90_CB_COLOR0_CLEAR_WORD1 */
+
+   radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* 
R_028C60_CB_COLOR0_BASE */
+   radeon_emit(cs, reloc);
+
+   radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* 
R_028C74_CB_COLOR0_ATTRIB */
+   radeon_emit(cs, reloc);
+
+   radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* 
R_028C7C_CB_COLOR0_CMASK */
+   radeon_emit(cs, reloc);
+
+   radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* 
R_028C84_CB_COLOR0_FMASK */
+   radeon_emit(cs, reloc);
+
+   radeon_set_context_reg(cs, R_028B9C_CB_IMMED0_BASE + (idx * 4), 
resource->immed_buffer->gpu_address >> 8);
+   radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /**/
+   radeon_emit(cs, immed_reloc);
+
+   radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
+   

[Mesa-dev] r600 evergreen+ shader image support

[Dave Airlie]

I've been hacking on this on/off for quite a while now, and I think
I'm finally happy with where is has reached.

It's not 100% on piglits, but it's quite close, and better than fglrx
does, so I'd probably prefer to land it before doing too much more
destructive hacking on it!

If you have a cayman, you now get GL4.2.

Dave.

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [Bug 103748] [softpipe] pigilt arb_internalformat_query2-image-texture regression

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=103748

Bug ID: 103748
   Summary: [softpipe] pigilt
arb_internalformat_query2-image-texture regression
   Product: Mesa
   Version: git
  Hardware: x86-64 (AMD64)
OS: Linux (All)
Status: NEW
  Keywords: bisected, regression
  Severity: normal
  Priority: medium
 Component: Mesa core
  Assignee: mesa-dev@lists.freedesktop.org
  Reporter: v...@freedesktop.org
QA Contact: mesa-dev@lists.freedesktop.org
CC: e...@anholt.net, mar...@gmail.com, nhaeh...@gmail.com

mesa: 5041ea96a0544283c3cf3885d6e2d2d0ba4857f5 (master 17.4.0-devel)

$  ./bin/arb_internalformat_query2-image-texture -auto
32 bit failing case: pname = GL_IMAGE_TEXEL_SIZE, target =
GL_TEXTURE_BUFFER, internalformat = GL_R11F_G11F_B10F, expected value = (32),
params[0] = (0,GL_POINTS), supported=1
32 bit failing case: pname = GL_IMAGE_TEXEL_SIZE, target =
GL_TEXTURE_BUFFER, internalformat = GL_RGB10_A2UI, expected value = (32),
params[0] = (0,GL_POINTS), supported=1
32 bit failing case: pname = GL_IMAGE_TEXEL_SIZE, target =
GL_TEXTURE_BUFFER, internalformat = GL_RGB10_A2, expected value = (32),
params[0] = (0,GL_POINTS), supported=1
32 bit failing case: pname = GL_IMAGE_TEXEL_SIZE, target =
GL_TEXTURE_BUFFER, internalformat = GL_RGBA16_SNORM, expected value = (64),
params[0] = (0,GL_POINTS), supported=1
32 bit failing case: pname = GL_IMAGE_TEXEL_SIZE, target =
GL_TEXTURE_BUFFER, internalformat = GL_RGBA8_SNORM, expected value = (32),
params[0] = (0,GL_POINTS), supported=1
32 bit failing case: pname = GL_IMAGE_TEXEL_SIZE, target =
GL_TEXTURE_BUFFER, internalformat = GL_RG16_SNORM, expected value = (32),
params[0] = (0,GL_POINTS), supported=1
32 bit failing case: pname = GL_IMAGE_TEXEL_SIZE, target =
GL_TEXTURE_BUFFER, internalformat = GL_RG8_SNORM, expected value = (16),
params[0] = (0,GL_POINTS), supported=1
32 bit failing case: pname = GL_IMAGE_TEXEL_SIZE, target =
GL_TEXTURE_BUFFER, internalformat = GL_R16_SNORM, expected value = (16),
params[0] = (0,GL_POINTS), supported=1
32 bit failing case: pname = GL_IMAGE_TEXEL_SIZE, target =
GL_TEXTURE_BUFFER, internalformat = GL_R8_SNORM, expected value = (8),
params[0] = (0,GL_POINTS), supported=1
64 bit failing case: pname = GL_IMAGE_TEXEL_SIZE, target =
GL_TEXTURE_BUFFER, internalformat = GL_R11F_G11F_B10F, expected value = (32),
params[0] = (0,GL_POINTS), supported=1
64 bit failing case: pname = GL_IMAGE_TEXEL_SIZE, target =
GL_TEXTURE_BUFFER, internalformat = GL_RGB10_A2UI, expected value = (32),
params[0] = (0,GL_POINTS), supported=1
64 bit failing case: pname = GL_IMAGE_TEXEL_SIZE, target =
GL_TEXTURE_BUFFER, internalformat = GL_RGB10_A2, expected value = (32),
params[0] = (0,GL_POINTS), supported=1
64 bit failing case: pname = GL_IMAGE_TEXEL_SIZE, target =
GL_TEXTURE_BUFFER, internalformat = GL_RGBA16_SNORM, expected value = (64),
params[0] = (0,GL_POINTS), supported=1
64 bit failing case: pname = GL_IMAGE_TEXEL_SIZE, target =
GL_TEXTURE_BUFFER, internalformat = GL_RGBA8_SNORM, expected value = (32),
params[0] = (0,GL_POINTS), supported=1
64 bit failing case: pname = GL_IMAGE_TEXEL_SIZE, target =
GL_TEXTURE_BUFFER, internalformat = GL_RG16_SNORM, expected value = (32),
params[0] = (0,GL_POINTS), supported=1
64 bit failing case: pname = GL_IMAGE_TEXEL_SIZE, target =
GL_TEXTURE_BUFFER, internalformat = GL_RG8_SNORM, expected value = (16),
params[0] = (0,GL_POINTS), supported=1
64 bit failing case: pname = GL_IMAGE_TEXEL_SIZE, target =
GL_TEXTURE_BUFFER, internalformat = GL_R16_SNORM, expected value = (16),
params[0] = (0,GL_POINTS), supported=1
64 bit failing case: pname = GL_IMAGE_TEXEL_SIZE, target =
GL_TEXTURE_BUFFER, internalformat = GL_R8_SNORM, expected value = (8),
params[0] = (0,GL_POINTS), supported=1
PIGLIT: {"subtest": {"GL_IMAGE_TEXEL_SIZE" : "fail"}}
32 bit failing case: pname = GL_IMAGE_COMPATIBILITY_CLASS, target =
GL_TEXTURE_BUFFER, internalformat = GL_R11F_G11F_B10F, expected value =
(33474), params[0] = (0,GL_POINTS), supported=1
32 bit failing case: pname = GL_IMAGE_COMPATIBILITY_CLASS, target =
GL_TEXTURE_BUFFER, internalformat = GL_RGB10_A2UI, expected value = (33475),
params[0] = (0,GL_POINTS), supported=1
32 bit failing case: pname = GL_IMAGE_COMPATIBILITY_CLASS, target =
GL_TEXTURE_BUFFER, internalformat = GL_RGB10_A2, expected value = (33475),
params[0] = (0,GL_POINTS), supported=1
32 bit failing case: pname = GL_IMAGE_COMPATIBILITY_CLASS, target =
GL_TEXTURE_BUFFER, internalformat = GL_RGBA16_SNORM, expected value = (33468),
params[0] = (0,GL_POINTS), supported=1
32 bit failing case: pname = GL_IMAGE_COMPATIBILITY_CLASS, target =
GL_TEXTURE_BUFFER, internalformat = GL_RGBA8_SNORM, expected value = (33471),
params[0] = (0,GL_POINTS), supported=1
32 bit failing case: pname = 

Re: [Mesa-dev] [PATCH] i965: Implement another VF cache invalidate workaround on Gen8+.

[Rafael Antognolli]

Reviewed-by: Rafael Antognolli 

On Tue, Nov 14, 2017 at 03:24:36PM -0800, Kenneth Graunke wrote:
> ...and provide a better citation for the existing one.
> 
> v2:
> - Apply the workaround to Gen8 too, as intended (caught by Topi).
> - Restructure to add bits instead of an extra flush (based on a similar
>   patch by Rafael Antognolli).
> ---
>  src/mesa/drivers/dri/i965/brw_pipe_control.c | 41 
> ++--
>  1 file changed, 33 insertions(+), 8 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c 
> b/src/mesa/drivers/dri/i965/brw_pipe_control.c
> index 39e8bff7309..c6e7dd15f4c 100644
> --- a/src/mesa/drivers/dri/i965/brw_pipe_control.c
> +++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c
> @@ -119,14 +119,39 @@ brw_emit_pipe_control(struct brw_context *brw, uint32_t 
> flags,
>if (devinfo->gen == 8)
>   gen8_add_cs_stall_workaround_bits();
>  
> -  if (devinfo->gen == 9 &&
> -  (flags & PIPE_CONTROL_VF_CACHE_INVALIDATE)) {
> - /* Hardware workaround: SKL
> -  *
> -  * Emit Pipe Control with all bits set to zero before emitting
> -  * a Pipe Control with VF Cache Invalidate set.
> -  */
> - brw_emit_pipe_control_flush(brw, 0);
> +  if (flags & PIPE_CONTROL_VF_CACHE_INVALIDATE) {
> + if (devinfo->gen == 9) {
> +/* The PIPE_CONTROL "VF Cache Invalidation Enable" bit 
> description
> + * lists several workarounds:
> + *
> + *"Project: SKL, KBL, BXT
> + *
> + * If the VF Cache Invalidation Enable is set to a 1 in a
> + * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields
> + * sets to 0, with the VF Cache Invalidation Enable set to 0
> + * needs to be sent prior to the PIPE_CONTROL with VF Cache
> + * Invalidation Enable set to a 1."
> + */
> +brw_emit_pipe_control_flush(brw, 0);
> + }
> +
> + if (devinfo->gen >= 8) {
> +/* THE PIPE_CONTROL "VF Cache Invalidation Enable" docs continue:
> + *
> + *"Project: BDW+
> + *
> + * When VF Cache Invalidate is set “Post Sync Operation” must
> + * be enabled to “Write Immediate Data” or “Write PS Depth
> + * Count” or “Write Timestamp”."
> + *
> + * If there's a BO, we're already doing some kind of write.
> + * If not, add a write to the workaround BO.
> + */
> +if (!bo) {
> +   flags |= PIPE_CONTROL_WRITE_IMMEDIATE;
> +   bo = brw->workaround_bo;
> +}
> + }
>}
>  
>if (devinfo->gen == 10)
> -- 
> 2.15.0
> 
> ___
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 2/2] svga: s/unsigned/enum tgsi_texture_type/

[Brian Paul]

---
 src/gallium/drivers/svga/svga_tgsi_vgpu10.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/gallium/drivers/svga/svga_tgsi_vgpu10.c 
b/src/gallium/drivers/svga/svga_tgsi_vgpu10.c
index 5fc93e2..c718eae 100644
--- a/src/gallium/drivers/svga/svga_tgsi_vgpu10.c
+++ b/src/gallium/drivers/svga/svga_tgsi_vgpu10.c
@@ -5043,7 +5043,7 @@ is_valid_tex_instruction(struct svga_shader_emitter_v10 
*emit,
  const struct tgsi_full_instruction *inst)
 {
const unsigned unit = inst->Src[1].Register.Index;
-   const unsigned target = inst->Texture.Texture;
+   const enum tgsi_texture_type target = inst->Texture.Texture;
boolean valid = TRUE;
 
if (tgsi_is_shadow_target(target) &&
@@ -5075,7 +5075,7 @@ emit_tex(struct svga_shader_emitter_v10 *emit,
  const struct tgsi_full_instruction *inst)
 {
const uint unit = inst->Src[1].Register.Index;
-   unsigned target = inst->Texture.Texture;
+   const enum tgsi_texture_type target = inst->Texture.Texture;
unsigned opcode;
struct tgsi_full_src_register coord;
int offsets[3];
@@ -5125,7 +5125,7 @@ emit_txp(struct svga_shader_emitter_v10 *emit,
  const struct tgsi_full_instruction *inst)
 {
const uint unit = inst->Src[1].Register.Index;
-   unsigned target = inst->Texture.Texture;
+   const enum tgsi_texture_type target = inst->Texture.Texture;
unsigned opcode;
int offsets[3];
unsigned tmp = get_temp_index(emit);
@@ -5187,7 +5187,7 @@ emit_txd(struct svga_shader_emitter_v10 *emit,
  const struct tgsi_full_instruction *inst)
 {
const uint unit = inst->Src[3].Register.Index;
-   unsigned target = inst->Texture.Texture;
+   const enum tgsi_texture_type target = inst->Texture.Texture;
int offsets[3];
struct tgsi_full_src_register coord;
struct tex_swizzle_info swz_info;
@@ -5277,7 +5277,7 @@ static boolean
 emit_txl_txb(struct svga_shader_emitter_v10 *emit,
  const struct tgsi_full_instruction *inst)
 {
-   unsigned target = inst->Texture.Texture;
+   const enum tgsi_texture_type target = inst->Texture.Texture;
unsigned opcode, unit;
int offsets[3];
struct tgsi_full_src_register coord, lod_bias;
-- 
1.9.1

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 1/2] tgsi: s/unsigned/enum tgsi_texture_type/

[Brian Paul]

---
 src/gallium/auxiliary/tgsi/tgsi_util.c |  6 +++---
 src/gallium/auxiliary/tgsi/tgsi_util.h | 10 +-
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/gallium/auxiliary/tgsi/tgsi_util.c 
b/src/gallium/auxiliary/tgsi/tgsi_util.c
index afe5690..6fc0530 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_util.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_util.c
@@ -452,7 +452,7 @@ tgsi_util_get_src_from_ind(const struct tgsi_ind_register 
*reg)
  * sample index.
  */
 int
-tgsi_util_get_texture_coord_dim(unsigned tgsi_tex)
+tgsi_util_get_texture_coord_dim(enum tgsi_texture_type tgsi_tex)
 {
/*
 * Depending on the texture target, (src0.xyzw, src1.x) is interpreted
@@ -513,7 +513,7 @@ tgsi_util_get_texture_coord_dim(unsigned tgsi_tex)
  * shadow reference coordinate.
  */
 int
-tgsi_util_get_shadow_ref_src_index(unsigned tgsi_tex)
+tgsi_util_get_shadow_ref_src_index(enum tgsi_texture_type tgsi_tex)
 {
switch (tgsi_tex) {
case TGSI_TEXTURE_SHADOW1D:
@@ -536,7 +536,7 @@ tgsi_util_get_shadow_ref_src_index(unsigned tgsi_tex)
 
 
 boolean
-tgsi_is_shadow_target(unsigned target)
+tgsi_is_shadow_target(enum tgsi_texture_type target)
 {
switch (target) {
case TGSI_TEXTURE_SHADOW1D:
diff --git a/src/gallium/auxiliary/tgsi/tgsi_util.h 
b/src/gallium/auxiliary/tgsi/tgsi_util.h
index 534b5f7..6d56c5b 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_util.h
+++ b/src/gallium/auxiliary/tgsi/tgsi_util.h
@@ -82,24 +82,24 @@ struct tgsi_src_register
 tgsi_util_get_src_from_ind(const struct tgsi_ind_register *reg);
 
 int
-tgsi_util_get_texture_coord_dim(unsigned tgsi_tex);
+tgsi_util_get_texture_coord_dim(enum tgsi_texture_type tgsi_tex);
 
 int
-tgsi_util_get_shadow_ref_src_index(unsigned tgsi_tex);
+tgsi_util_get_shadow_ref_src_index(enum tgsi_texture_type tgsi_tex);
 
 boolean
-tgsi_is_shadow_target(unsigned target);
+tgsi_is_shadow_target(enum tgsi_texture_type);
 
 
 static inline boolean
-tgsi_is_msaa_target(unsigned target)
+tgsi_is_msaa_target(enum tgsi_texture_type target)
 {
return (target == TGSI_TEXTURE_2D_MSAA ||
target == TGSI_TEXTURE_2D_ARRAY_MSAA);
 }
 
 static inline bool
-tgsi_is_array_sampler(unsigned target)
+tgsi_is_array_sampler(enum tgsi_texture_type target)
 {
return target == TGSI_TEXTURE_1D_ARRAY ||
   target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
-- 
1.9.1

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 8/8] radv: enable nir component packing

[Timothy Arceri]

SaschaWillems Vulkan demo tessellation:

~4000fps -> ~4600fps

Reviewed-by: Bas Nieuwenhuizen 
---
 src/amd/vulkan/radv_pipeline.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 9046960ad2..dad2b035c1 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1824,20 +1824,21 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
unsigned first = MESA_SHADER_STAGES;
unsigned last = 0;
for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
if (!pStages[i])
continue;
if (first == MESA_SHADER_STAGES)
first = i;
last = i;
}
 
+   int prev = -1;
for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
const VkPipelineShaderStageCreateInfo *stage = pStages[i];
 
if (!modules[i])
continue;
 
nir[i] = radv_shader_compile_to_nir(device, modules[i],
stage ? stage->pName : 
"main", i,
stage ? 
stage->pSpecializationInfo : NULL);
pipeline->active_stages |= mesa_to_vk_shader_stage(i);
@@ -1854,20 +1855,25 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
 
if (i != first)
mask = mask | nir_var_shader_in;
 
if (i != last)
mask = mask | nir_var_shader_out;
 
nir_lower_io_to_scalar_early(nir[i], mask);
radv_optimize_nir(nir[i]);
}
+
+   if (prev != -1) {
+   nir_compact_varyings(nir[prev], nir[i], true);
+   }
+   prev = i;
}
 
if (nir[MESA_SHADER_TESS_CTRL]) {
nir_lower_tes_patch_vertices(nir[MESA_SHADER_TESS_EVAL], 
nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out);
}
 
radv_link_shaders(pipeline, nir);
 
for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
if (!(device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS))
-- 
2.14.3

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 5/8] nir: add varying component packing helpers

[Timothy Arceri]

v2: update shader info input/output masks when pack components

Reviewed-by: Bas Nieuwenhuizen  (v1)
---
 src/compiler/nir/nir.h |   2 +
 src/compiler/nir/nir_linking_helpers.c | 272 +
 2 files changed, 274 insertions(+)

diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index c62af4afb9..5832c05680 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -2441,20 +2441,22 @@ void nir_lower_io_to_temporaries(nir_shader *shader,
  nir_function_impl *entrypoint,
  bool outputs, bool inputs);
 
 void nir_shader_gather_info(nir_shader *shader, nir_function_impl *entrypoint);
 
 void nir_assign_var_locations(struct exec_list *var_list, unsigned *size,
   int (*type_size)(const struct glsl_type *));
 
 /* Some helpers to do very simple linking */
 bool nir_remove_unused_varyings(nir_shader *producer, nir_shader *consumer);
+void nir_compact_varyings(nir_shader *producer, nir_shader *consumer,
+  bool default_to_smooth_interp);
 
 typedef enum {
/* If set, this forces all non-flat fragment shader inputs to be
 * interpolated as if with the "sample" qualifier.  This requires
 * nir_shader_compiler_options::use_interpolated_input_intrinsics.
 */
nir_lower_io_force_sample_interpolation = (1 << 1),
 } nir_lower_io_options;
 bool nir_lower_io(nir_shader *shader,
   nir_variable_mode modes,
diff --git a/src/compiler/nir/nir_linking_helpers.c 
b/src/compiler/nir/nir_linking_helpers.c
index 4d709c1b3c..f7355af219 100644
--- a/src/compiler/nir/nir_linking_helpers.c
+++ b/src/compiler/nir/nir_linking_helpers.c
@@ -166,10 +166,282 @@ nir_remove_unused_varyings(nir_shader *producer, 
nir_shader *consumer)
 
bool progress = false;
progress = remove_unused_io_vars(producer, >outputs, read,
 patches_read);
 
progress = remove_unused_io_vars(consumer, >inputs, written,
 patches_written) || progress;
 
return progress;
 }
+
+static uint8_t
+get_interp_type(nir_variable *var, bool default_to_smooth_interp)
+{
+   if (var->data.interpolation != INTERP_MODE_NONE)
+  return var->data.interpolation;
+   else if (default_to_smooth_interp)
+  return INTERP_MODE_SMOOTH;
+   else
+  return INTERP_MODE_NONE;
+}
+
+static void
+get_slot_component_masks_and_interp_types(struct exec_list *var_list,
+  uint8_t *comps,  uint8_t 
*interp_type,
+  gl_shader_stage stage,
+  bool default_to_smooth_interp)
+{
+   nir_foreach_variable_safe(var, var_list) {
+  assert(var->data.location >= 0);
+
+  /* Only remap things that aren't built-ins.
+   * TODO: add TES patch support.
+   */
+  if (var->data.location >= VARYING_SLOT_VAR0 &&
+  var->data.location - VARYING_SLOT_VAR0 < 32) {
+
+ const struct glsl_type *type = var->type;
+ if (nir_is_per_vertex_io(var, stage)) {
+assert(glsl_type_is_array(type));
+type = glsl_get_array_element(type);
+ }
+
+ unsigned location = var->data.location - VARYING_SLOT_VAR0;
+ unsigned elements =
+glsl_get_vector_elements(glsl_without_array(type));
+
+ bool dual_slot = glsl_type_is_dual_slot(glsl_without_array(type));
+ unsigned slots = glsl_count_attribute_slots(type, false);
+ unsigned comps_slot2 = 0;
+ for (unsigned i = 0; i < slots; i++) {
+interp_type[location + i] =
+   get_interp_type(var, default_to_smooth_interp);
+
+if (dual_slot) {
+   if (i & 1) {
+  comps[location + i] |= ((1 << comps_slot2) - 1);
+   } else {
+  unsigned num_comps = 4 - var->data.location_frac;
+  comps_slot2 = (elements * 2) - num_comps;
+
+  /* Assume ARB_enhanced_layouts packing rules for doubles */
+  assert(var->data.location_frac == 0 ||
+ var->data.location_frac == 2);
+  assert(comps_slot2 <= 4);
+
+  comps[location + i] |=
+ ((1 << num_comps) - 1) << var->data.location_frac;
+   }
+} else {
+   comps[location + i] |=
+  ((1 << elements) - 1) << var->data.location_frac;
+}
+ }
+  }
+   }
+}
+
+struct varying_loc
+{
+   uint8_t component;
+   uint32_t location;
+};
+
+static void
+remap_slots_and_components(struct exec_list *var_list, gl_shader_stage stage,
+   struct varying_loc (*remap)[4], uint64_t 
*slots_used)
+ {
+   /* We don't touch builtins so just copy the bitmask */
+   uint64_t slots_used_tmp =
+  *slots_used & 

[Mesa-dev] [PATCH 4/8] i965: call nir_lower_io_to_scalar() at link time for BDW and above

[Timothy Arceri]

This will allow dead components of varyings to be removed.

BDW shader-db results:

total instructions in shared programs: 13190730 -> 13108459 (-0.62%)
instructions in affected programs: 2110903 -> 2028632 (-3.90%)
helped: 14043
HURT: 486

total cycles in shared programs: 541148990 -> 540544072 (-0.11%)
cycles in affected programs: 290344296 -> 289739378 (-0.21%)
helped: 23418
HURT: 11623

total loops in shared programs: 3923 -> 3920 (-0.08%)
loops in affected programs: 3 -> 0
helped: 3
HURT: 0

total spills in shared programs: 85784 -> 85853 (0.08%)
spills in affected programs: 1374 -> 1443 (5.02%)
helped: 6
HURT: 15

total fills in shared programs: 88717 -> 88801 (0.09%)
fills in affected programs: 1719 -> 1803 (4.89%)
helped: 15
HURT: 9

LOST:   3
GAINED: 0

The fills/spills changes were all in the dolphin uber shaders.

I tested enabling this on IVB but the results went in the other
direction.
---
 src/mesa/drivers/dri/i965/brw_link.cpp | 35 --
 1 file changed, 25 insertions(+), 10 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp 
b/src/mesa/drivers/dri/i965/brw_link.cpp
index e6f93d37f0..465cab767d 100644
--- a/src/mesa/drivers/dri/i965/brw_link.cpp
+++ b/src/mesa/drivers/dri/i965/brw_link.cpp
@@ -221,20 +221,31 @@ extern "C" GLboolean
 brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg)
 {
struct brw_context *brw = brw_context(ctx);
const struct brw_compiler *compiler = brw->screen->compiler;
unsigned int stage;
struct shader_info *infos[MESA_SHADER_STAGES] = { 0, };
 
if (shProg->data->LinkStatus == linking_skipped)
   return GL_TRUE;
 
+   /* Determine first and last stage. */
+   unsigned first = MESA_SHADER_STAGES;
+   unsigned last = 0;
+   for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
+  if (!shProg->_LinkedShaders[i])
+ continue;
+  if (first == MESA_SHADER_STAGES)
+ first = i;
+  last = i;
+   }
+
for (stage = 0; stage < ARRAY_SIZE(shProg->_LinkedShaders); stage++) {
   struct gl_linked_shader *shader = shProg->_LinkedShaders[stage];
   if (!shader)
  continue;
 
   struct gl_program *prog = shader->Program;
   prog->Parameters = _mesa_new_parameter_list();
 
   process_glsl_ir(brw, shProg, shader);
 
@@ -248,31 +259,35 @@ brw_link_shader(struct gl_context *ctx, struct 
gl_shader_program *shProg)
 
   if (debug_enabled && shader->ir) {
  fprintf(stderr, "GLSL IR for native %s shader %d:\n",
  _mesa_shader_stage_to_string(shader->Stage), shProg->Name);
  _mesa_print_ir(stderr, shader->ir, NULL);
  fprintf(stderr, "\n\n");
   }
 
   prog->nir = brw_create_nir(brw, shProg, prog, (gl_shader_stage) stage,
  compiler->scalar_stage[stage]);
-   }
 
-   /* Determine first and last stage. */
-   unsigned first = MESA_SHADER_STAGES;
-   unsigned last = 0;
-   for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
-  if (!shProg->_LinkedShaders[i])
- continue;
-  if (first == MESA_SHADER_STAGES)
- first = i;
-  last = i;
+  if (brw->screen->devinfo.gen >= 8) {
+ nir_variable_mode mask = (nir_variable_mode) 0;
+
+ if (stage != first)
+mask = (nir_variable_mode)(mask | nir_var_shader_in);
+
+ if (stage != last)
+mask = (nir_variable_mode)(mask | nir_var_shader_out);
+
+ nir_lower_io_to_scalar_early(prog->nir, mask);
+
+ prog->nir = brw_nir_optimize(prog->nir, compiler,
+  compiler->scalar_stage[stage]);
+  }
}
 
/* Linking the stages in the opposite order (from fragment to vertex)
 * ensures that inter-shader outputs written to in an earlier stage
 * are eliminated if they are (transitively) not used in a later
 * stage.
 *
 * TODO: Look into Shadow of Mordor regressions on HSW and enable this for
 * all platforms. See: https://bugs.freedesktop.org/show_bug.cgi?id=103537
 */
-- 
2.14.3

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 6/8] i965: enable varying component packing for BDW+

[Timothy Arceri]

shader-db results BDW:

total instructions in shared programs: 13192895 -> 13182437 (-0.08%)
instructions in affected programs: 827145 -> 816687 (-1.26%)
helped: 5199
HURT: 116

total cycles in shared programs: 539249342 -> 539156566 (-0.02%)
cycles in affected programs: 21894552 -> 21801776 (-0.42%)
helped: 10667
HURT: 7196

LOST:   0
GAINED: 17
---
 src/mesa/drivers/dri/i965/brw_link.cpp | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp 
b/src/mesa/drivers/dri/i965/brw_link.cpp
index 465cab767d..e9cf88dc86 100644
--- a/src/mesa/drivers/dri/i965/brw_link.cpp
+++ b/src/mesa/drivers/dri/i965/brw_link.cpp
@@ -297,40 +297,47 @@ brw_link_shader(struct gl_context *ctx, struct 
gl_shader_program *shProg)
   if (shProg->_LinkedShaders[i] == NULL)
  continue;
 
   brw_nir_link_shaders(compiler,
>_LinkedShaders[i]->Program->nir,
>_LinkedShaders[next]->Program->nir);
   next = i;
}
 }
 
+   int prev = -1;
for (stage = 0; stage < ARRAY_SIZE(shProg->_LinkedShaders); stage++) {
   struct gl_linked_shader *shader = shProg->_LinkedShaders[stage];
   if (!shader)
  continue;
 
   struct gl_program *prog = shader->Program;
   brw_shader_gather_info(prog->nir, prog);
 
   NIR_PASS_V(prog->nir, nir_lower_samplers, shProg);
   NIR_PASS_V(prog->nir, nir_lower_atomics, shProg);
 
   if (brw->ctx.Cache) {
  struct blob writer;
  blob_init();
  nir_serialize(, prog->nir);
  prog->driver_cache_blob = ralloc_size(NULL, writer.size);
  memcpy(prog->driver_cache_blob, writer.data, writer.size);
  prog->driver_cache_blob_size = writer.size;
   }
 
+  if (brw->screen->devinfo.gen >= 8 && prev != -1) {
+ nir_compact_varyings(shProg->_LinkedShaders[prev]->Program->nir,
+  prog->nir, ctx->API != API_OPENGL_COMPAT);
+  }
+  prev = stage;
+
   infos[stage] = >nir->info;
 
   /* Make a pass over the IR to add state references for any built-in
* uniforms that are used.  This has to be done now (during linking).
* Code generation doesn't happen until the first time this shader is
* used for rendering.  Waiting until then to generate the parameters is
* too late.  At that point, the values for the built-in uniforms won't
* get sent to the shader.
*/
   nir_foreach_variable(var, >nir->uniforms) {
-- 
2.14.3

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 7/8] radv: enable nir varying array splitting

[Timothy Arceri]

---
 src/amd/vulkan/radv_pipeline.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index f006dc98c0..9046960ad2 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1675,20 +1675,23 @@ radv_link_shaders(struct radv_pipeline *pipeline, 
nir_shader **shaders)
ordered_shaders[shader_count++] = 
shaders[MESA_SHADER_TESS_EVAL];
}
if(shaders[MESA_SHADER_TESS_CTRL]) {
ordered_shaders[shader_count++] = 
shaders[MESA_SHADER_TESS_CTRL];
}
if(shaders[MESA_SHADER_VERTEX]) {
ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
}
 
for (int i = 1; i < shader_count; ++i)  {
+   nir_lower_io_arrays_to_elements(ordered_shaders[i],
+   ordered_shaders[i - 1]);
+
nir_remove_dead_variables(ordered_shaders[i],
  nir_var_shader_out);
nir_remove_dead_variables(ordered_shaders[i - 1],
  nir_var_shader_in);
 
bool progress = nir_remove_unused_varyings(ordered_shaders[i],
   ordered_shaders[i - 
1]);
 
if (progress) {
nir_lower_global_vars_to_local(ordered_shaders[i]);
-- 
2.14.3

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 3/8] i965: enable varying array splitting

[Timothy Arceri]

total instructions in shared programs: 13210579 -> 13199325 (-0.09%)
instructions in affected programs: 89043 -> 77789 (-12.64%)
helped: 430
HURT: 0

total cycles in shared programs: 539530190 -> 539493750 (-0.01%)
cycles in affected programs: 584860 -> 548420 (-6.23%)
helped: 437
HURT: 110

total spills in shared programs: 86646 -> 86640 (-0.01%)
spills in affected programs: 6 -> 0
helped: 1
HURT: 0

total fills in shared programs: 90955 -> 90946 (-0.01%)
fills in affected programs: 9 -> 0
helped: 1
HURT: 0
---
 src/intel/compiler/brw_nir.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
index 8f3f77f89a..26d17d8f0c 100644
--- a/src/intel/compiler/brw_nir.c
+++ b/src/intel/compiler/brw_nir.c
@@ -672,20 +672,22 @@ brw_preprocess_nir(const struct brw_compiler *compiler, 
nir_shader *nir)
 
OPT(nir_remove_dead_variables, nir_var_local);
 
return nir;
 }
 
 void
 brw_nir_link_shaders(const struct brw_compiler *compiler,
  nir_shader **producer, nir_shader **consumer)
 {
+   nir_lower_io_arrays_to_elements(*producer, *consumer);
+
NIR_PASS_V(*producer, nir_remove_dead_variables, nir_var_shader_out);
NIR_PASS_V(*consumer, nir_remove_dead_variables, nir_var_shader_in);
 
if (nir_remove_unused_varyings(*producer, *consumer)) {
   NIR_PASS_V(*producer, nir_lower_global_vars_to_local);
   NIR_PASS_V(*consumer, nir_lower_global_vars_to_local);
 
   /* The backend might not be able to handle indirects on
* temporaries so we need to lower indirects on any of the
* varyings we have demoted here.
-- 
2.14.3

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 1/8] nir: add varying array splitting pass

[Timothy Arceri]

---
 src/compiler/Makefile.sources  |   1 +
 src/compiler/nir/meson.build   |   1 +
 src/compiler/nir/nir.h |   1 +
 src/compiler/nir/nir_lower_io_arrays_to_elements.c | 371 +
 4 files changed, 374 insertions(+)
 create mode 100644 src/compiler/nir/nir_lower_io_arrays_to_elements.c

diff --git a/src/compiler/Makefile.sources b/src/compiler/Makefile.sources
index 2ab8e163a2..c5094b7f19 100644
--- a/src/compiler/Makefile.sources
+++ b/src/compiler/Makefile.sources
@@ -219,20 +219,21 @@ NIR_FILES = \
nir/nir_lower_double_ops.c \
nir/nir_lower_drawpixels.c \
nir/nir_lower_global_vars_to_local.c \
nir/nir_lower_gs_intrinsics.c \
nir/nir_lower_load_const_to_scalar.c \
nir/nir_lower_locals_to_regs.c \
nir/nir_lower_idiv.c \
nir/nir_lower_indirect_derefs.c \
nir/nir_lower_int64.c \
nir/nir_lower_io.c \
+   nir/nir_lower_io_arrays_to_elements.c \
nir/nir_lower_io_to_temporaries.c \
nir/nir_lower_io_to_scalar.c \
nir/nir_lower_io_types.c \
nir/nir_lower_passthrough_edgeflags.c \
nir/nir_lower_patch_vertices.c \
nir/nir_lower_phis_to_scalar.c \
nir/nir_lower_regs_to_ssa.c \
nir/nir_lower_returns.c \
nir/nir_lower_samplers.c \
nir/nir_lower_samplers_as_deref.c \
diff --git a/src/compiler/nir/meson.build b/src/compiler/nir/meson.build
index e5c8326aa0..b61a07773d 100644
--- a/src/compiler/nir/meson.build
+++ b/src/compiler/nir/meson.build
@@ -107,20 +107,21 @@ files_libnir = files(
   'nir_lower_double_ops.c',
   'nir_lower_drawpixels.c',
   'nir_lower_global_vars_to_local.c',
   'nir_lower_gs_intrinsics.c',
   'nir_lower_load_const_to_scalar.c',
   'nir_lower_locals_to_regs.c',
   'nir_lower_idiv.c',
   'nir_lower_indirect_derefs.c',
   'nir_lower_int64.c',
   'nir_lower_io.c',
+  'nir_lower_io_arrays_to_elements.c',
   'nir_lower_io_to_temporaries.c',
   'nir_lower_io_to_scalar.c',
   'nir_lower_io_types.c',
   'nir_lower_passthrough_edgeflags.c',
   'nir_lower_patch_vertices.c',
   'nir_lower_phis_to_scalar.c',
   'nir_lower_regs_to_ssa.c',
   'nir_lower_returns.c',
   'nir_lower_samplers.c',
   'nir_lower_samplers_as_deref.c',
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index f46f614711..c62af4afb9 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -2475,20 +2475,21 @@ bool nir_lower_constant_initializers(nir_shader *shader,
  nir_variable_mode modes);
 
 bool nir_move_vec_src_uses_to_dest(nir_shader *shader);
 bool nir_lower_vec_to_movs(nir_shader *shader);
 void nir_lower_alpha_test(nir_shader *shader, enum compare_func func,
   bool alpha_to_one);
 bool nir_lower_alu_to_scalar(nir_shader *shader);
 bool nir_lower_load_const_to_scalar(nir_shader *shader);
 bool nir_lower_read_invocation_to_scalar(nir_shader *shader);
 bool nir_lower_phis_to_scalar(nir_shader *shader);
+void nir_lower_io_arrays_to_elements(nir_shader *producer, nir_shader 
*consumer);
 void nir_lower_io_to_scalar(nir_shader *shader, nir_variable_mode mask);
 void nir_lower_io_to_scalar_early(nir_shader *shader, nir_variable_mode mask);
 
 bool nir_lower_samplers(nir_shader *shader,
 const struct gl_shader_program *shader_program);
 bool nir_lower_samplers_as_deref(nir_shader *shader,
  const struct gl_shader_program 
*shader_program);
 
 typedef struct nir_lower_subgroups_options {
uint8_t subgroup_size;
diff --git a/src/compiler/nir/nir_lower_io_arrays_to_elements.c 
b/src/compiler/nir/nir_lower_io_arrays_to_elements.c
new file mode 100644
index 00..3a8e2dc193
--- /dev/null
+++ b/src/compiler/nir/nir_lower_io_arrays_to_elements.c
@@ -0,0 +1,371 @@
+/*
+ * Copyright © 2017 Timothy Arceri
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE 

[Mesa-dev] [PATCH 2/8] i965: move update_xfb_info() call out of loop

[Timothy Arceri]

We can just call it once. Also a following patch will also introduce
link time component packing which modifies the outputs_written
bit mask, we want to avoid calling update_xfb_info() until after
packing is completed.
---
 src/mesa/drivers/dri/i965/brw_link.cpp | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp 
b/src/mesa/drivers/dri/i965/brw_link.cpp
index 24545d52ec..e6f93d37f0 100644
--- a/src/mesa/drivers/dri/i965/brw_link.cpp
+++ b/src/mesa/drivers/dri/i965/brw_link.cpp
@@ -304,42 +304,45 @@ brw_link_shader(struct gl_context *ctx, struct 
gl_shader_program *shProg)
  struct blob writer;
  blob_init();
  nir_serialize(, prog->nir);
  prog->driver_cache_blob = ralloc_size(NULL, writer.size);
  memcpy(prog->driver_cache_blob, writer.data, writer.size);
  prog->driver_cache_blob_size = writer.size;
   }
 
   infos[stage] = >nir->info;
 
-  update_xfb_info(prog->sh.LinkedTransformFeedback, infos[stage]);
-
   /* Make a pass over the IR to add state references for any built-in
* uniforms that are used.  This has to be done now (during linking).
* Code generation doesn't happen until the first time this shader is
* used for rendering.  Waiting until then to generate the parameters is
* too late.  At that point, the values for the built-in uniforms won't
* get sent to the shader.
*/
   nir_foreach_variable(var, >nir->uniforms) {
  if (strncmp(var->name, "gl_", 3) == 0) {
 const nir_state_slot *const slots = var->state_slots;
 assert(var->state_slots != NULL);
 
 for (unsigned int i = 0; i < var->num_state_slots; i++) {
_mesa_add_state_reference(prog->Parameters,
  (gl_state_index *)slots[i].tokens);
 }
  }
   }
}
 
+   if (shProg->last_vert_prog) {
+  update_xfb_info(shProg->last_vert_prog->sh.LinkedTransformFeedback,
+  >last_vert_prog->nir->info);
+   }
+
/* The linker tries to dead code eliminate unused varying components,
 * and make sure interfaces match.  But it isn't able to do so in all
 * cases.  So, explicitly make the interfaces match by OR'ing together
 * the inputs_read/outputs_written bitfields of adjacent stages.
 */
if (!shProg->SeparateShader)
   unify_interfaces(infos);
 
if ((ctx->_Shader->Flags & GLSL_DUMP) && shProg->Name != 0) {
   for (unsigned i = 0; i < shProg->NumShaders; i++) {
-- 
2.14.3

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 14/14] anv: Add support for MSAA fast-clears

[Lionel Landwerlin]

Reviewed-by: Lionel Landwerlin 
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] i RESEND More NIR linking optimisations

[Timothy Arceri]

This is a resend/rebase of the series I sent a couple of weeks ago,
its rebased on some of Jason's changes to i965 NIR linking that
landed in master.

This series adds a varying array splitting pass as well a previous
component packing series I sent out previously. This allows avoiding the
workaround of calling gather shader info twice since we can more easily
keep the input/output bitmasks in sync now that we don't need to worry
about partial marking of arrays.

Remaining improvements include adding a pass to compact varyings into 
consecutive
slots rather than leaving empty slots when removing dead varyings.

Shader-db results for serires on i965 (BDW):

total instructions in shared programs: 13298718 -> 13191284 (-0.81%)
instructions in affected programs: 2315180 -> 2207746 (-4.64%)
helped: 14956
HURT: 390

total cycles in shared programs: 540151400 -> 539397048 (-0.14%)
cycles in affected programs: 297905258 -> 297150906 (-0.25%)
helped: 25231
HURT: 13033

total loops in shared programs: 3807 -> 3804 (-0.08%)
loops in affected programs: 3 -> 0
helped: 3
HURT: 0

total spills in shared programs: 86577 -> 86640 (0.07%)
spills in affected programs: 1380 -> 1443 (4.57%)
helped: 7
HURT: 15

total fills in shared programs: 90871 -> 90946 (0.08%)
fills in affected programs: 1728 -> 1803 (4.34%)
helped: 16
HURT: 9

LOST:   4
GAINED: 15

The spill hurt is all in dolphin uber shaders (as is most of the spill
improvements).

Two of the lost programs are SIMD16 programs are from CS: GO because 80% of the
shaders get optimised away when we remove dead varying components, these are
also the shaders where the 3 loops go away.

Please review.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 13/14] anv/blorp: Add an mcs_partial_resolve helper

[Lionel Landwerlin]

Reviewed-by: Lionel Landwerlin 
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 12/14] intel/blorp: Add indirect clear color support to mcs_partial_resolve

[Lionel Landwerlin]

On 13/11/17 16:12, Jason Ekstrand wrote:

This is a bit complicated because we have to get the indirect clear
color in there somehow.  In order to not do any more work in the shader
than needed, we set it up as it's own vertex binding which points
directly at the clear color address specified by the client.
---
  src/intel/blorp/blorp_clear.c | 25 +-
  src/intel/blorp/blorp_genX_exec.h | 54 ---
  src/intel/blorp/blorp_priv.h  |  1 +
  3 files changed, 70 insertions(+), 10 deletions(-)

diff --git a/src/intel/blorp/blorp_clear.c b/src/intel/blorp/blorp_clear.c
index 8e7bc9f..ac582e7 100644
--- a/src/intel/blorp/blorp_clear.c
+++ b/src/intel/blorp/blorp_clear.c
@@ -780,9 +780,18 @@ blorp_ccs_resolve(struct blorp_batch *batch,
 batch->blorp->exec(batch, );
  }
  
+static nir_ssa_def *

+blorp_nir_bit(nir_builder *b, nir_ssa_def *src, unsigned bit)
+{
+   return nir_iand(b, nir_ushr(b, src, nir_imm_int(b, bit)),
+  nir_imm_int(b, 1));
+}
+
  struct blorp_mcs_partial_resolve_key
  {
 enum blorp_shader_type shader_type;
+   bool indirect_clear_color;
+   bool int_format;
 uint32_t num_samples;
  };
  
@@ -792,6 +801,8 @@ blorp_params_get_mcs_partial_resolve_kernel(struct blorp_context *blorp,

  {
 const struct blorp_mcs_partial_resolve_key blorp_key = {
.shader_type = BLORP_SHADER_TYPE_MCS_PARTIAL_RESOLVE,
+  .indirect_clear_color = params->dst.clear_color_addr.buffer != NULL,
+  .int_format = isl_format_has_int_channel(params->dst.view.format),
.num_samples = params->num_samples,
 };
  
@@ -826,7 +837,18 @@ blorp_params_get_mcs_partial_resolve_kernel(struct blorp_context *blorp,

 discard->src[0] = nir_src_for_ssa(nir_inot(, is_clear));
 nir_builder_instr_insert(, >instr);
  
-   nir_copy_var(, frag_color, v_color);

+   nir_ssa_def *clear_color = nir_load_var(, v_color);
+   if (blorp_key.indirect_clear_color && blorp->isl_dev->info->gen <= 8) {
+  /* Gen7-8 clear colors are stored as single 0/1 bits */
+  clear_color = nir_vec4(, blorp_nir_bit(, clear_color, 31),
+ blorp_nir_bit(, clear_color, 30),
+ blorp_nir_bit(, clear_color, 29),
+ blorp_nir_bit(, clear_color, 28));


Won't this need some swizzling somewhere?
Either when storing the color in the fast clear colors (behind the aux 
surface) or here in the shader?




+
+  if (!blorp_key.int_format)
+ clear_color = nir_i2f32(, clear_color);
+   }
+   nir_store_var(, frag_color, clear_color, 0xf);
  
 struct brw_wm_prog_key wm_key;

 brw_blorp_init_wm_prog_key(_key);
@@ -872,6 +894,7 @@ blorp_mcs_partial_resolve(struct blorp_batch *batch,
  
 params.num_samples = params.dst.surf.samples;

 params.num_layers = num_layers;
+   params.dst_clear_color_as_input = surf->clear_color_addr.buffer != NULL;
  
 memcpy(_inputs.clear_color,

surf->clear_color.f32, sizeof(float) * 4);
diff --git a/src/intel/blorp/blorp_genX_exec.h 
b/src/intel/blorp/blorp_genX_exec.h
index 7548392..c3df2d5 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -297,7 +297,7 @@ static void
  blorp_emit_vertex_buffers(struct blorp_batch *batch,
const struct blorp_params *params)
  {
-   struct GENX(VERTEX_BUFFER_STATE) vb[2];
+   struct GENX(VERTEX_BUFFER_STATE) vb[3];
 memset(vb, 0, sizeof(vb));
  
 struct blorp_address addr;

@@ -308,12 +308,20 @@ blorp_emit_vertex_buffers(struct blorp_batch *batch,
 blorp_emit_input_varying_data(batch, params, , );
 blorp_fill_vertex_buffer_state(batch, vb, 1, addr, size, 0);
  
-   const unsigned num_dwords = 1 + GENX(VERTEX_BUFFER_STATE_length) * 2;

+   uint32_t num_vbs = 2;
+   if (params->dst_clear_color_as_input) {
+  blorp_fill_vertex_buffer_state(batch, vb, num_vbs++,
+ params->dst.clear_color_addr,
+ 
batch->blorp->isl_dev->ss.clear_value_size,
+ 0);
+   }
+
+   const unsigned num_dwords = 1 + num_vbs * GENX(VERTEX_BUFFER_STATE_length);
 uint32_t *dw = blorp_emitn(batch, GENX(3DSTATE_VERTEX_BUFFERS), 
num_dwords);
 if (!dw)
return;
  
-   for (unsigned i = 0; i < 2; i++) {

+   for (unsigned i = 0; i < num_vbs; i++) {
GENX(VERTEX_BUFFER_STATE_pack)(batch, dw, [i]);
dw += GENX(VERTEX_BUFFER_STATE_length);
 }
@@ -440,21 +448,49 @@ blorp_emit_vertex_elements(struct blorp_batch *batch,
 };
 slot++;
  
-   for (unsigned i = 0; i < num_varyings; ++i) {

+   if (params->dst_clear_color_as_input) {
+  /* If the caller wants the destination indirect clear color, redirect
+   * to vertex buffer 2 where we stored it earlier.  The only users of
+   * an indirect clear color source have that as their only vertex
+   * attribute.
+  

[Mesa-dev] [PATCH] i965: Implement another VF cache invalidate workaround on Gen8+.

[Kenneth Graunke]

...and provide a better citation for the existing one.

v2:
- Apply the workaround to Gen8 too, as intended (caught by Topi).
- Restructure to add bits instead of an extra flush (based on a similar
  patch by Rafael Antognolli).
---
 src/mesa/drivers/dri/i965/brw_pipe_control.c | 41 ++--
 1 file changed, 33 insertions(+), 8 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c 
b/src/mesa/drivers/dri/i965/brw_pipe_control.c
index 39e8bff7309..c6e7dd15f4c 100644
--- a/src/mesa/drivers/dri/i965/brw_pipe_control.c
+++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c
@@ -119,14 +119,39 @@ brw_emit_pipe_control(struct brw_context *brw, uint32_t 
flags,
   if (devinfo->gen == 8)
  gen8_add_cs_stall_workaround_bits();
 
-  if (devinfo->gen == 9 &&
-  (flags & PIPE_CONTROL_VF_CACHE_INVALIDATE)) {
- /* Hardware workaround: SKL
-  *
-  * Emit Pipe Control with all bits set to zero before emitting
-  * a Pipe Control with VF Cache Invalidate set.
-  */
- brw_emit_pipe_control_flush(brw, 0);
+  if (flags & PIPE_CONTROL_VF_CACHE_INVALIDATE) {
+ if (devinfo->gen == 9) {
+/* The PIPE_CONTROL "VF Cache Invalidation Enable" bit description
+ * lists several workarounds:
+ *
+ *"Project: SKL, KBL, BXT
+ *
+ * If the VF Cache Invalidation Enable is set to a 1 in a
+ * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields
+ * sets to 0, with the VF Cache Invalidation Enable set to 0
+ * needs to be sent prior to the PIPE_CONTROL with VF Cache
+ * Invalidation Enable set to a 1."
+ */
+brw_emit_pipe_control_flush(brw, 0);
+ }
+
+ if (devinfo->gen >= 8) {
+/* THE PIPE_CONTROL "VF Cache Invalidation Enable" docs continue:
+ *
+ *"Project: BDW+
+ *
+ * When VF Cache Invalidate is set “Post Sync Operation” must
+ * be enabled to “Write Immediate Data” or “Write PS Depth
+ * Count” or “Write Timestamp”."
+ *
+ * If there's a BO, we're already doing some kind of write.
+ * If not, add a write to the workaround BO.
+ */
+if (!bo) {
+   flags |= PIPE_CONTROL_WRITE_IMMEDIATE;
+   bo = brw->workaround_bo;
+}
+ }
   }
 
   if (devinfo->gen == 10)
-- 
2.15.0

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] i965: Remove DWord length from MI_FLUSH_DW definition

[Kenneth Graunke]

On Tuesday, November 14, 2017 2:52:35 PM PST Anuj Phogat wrote:
> This fixes the changes introduced in commit 6165fda59b.
> 
> Signed-off-by: Anuj Phogat 
> Cc: 
> Cc: Nanley Chery 
> Cc: Kenneth Graunke 
> ---
>  src/mesa/drivers/dri/i965/brw_defines.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_defines.h 
> b/src/mesa/drivers/dri/i965/brw_defines.h
> index 26f6ae6b2f..59d9e5cf21 100644
> --- a/src/mesa/drivers/dri/i965/brw_defines.h
> +++ b/src/mesa/drivers/dri/i965/brw_defines.h
> @@ -1430,7 +1430,7 @@ enum brw_pixel_shader_coverage_mask_mode {
>  #define MI_LOAD_REGISTER_IMM (CMD_MI | (0x22 << 23))
>  #define MI_LOAD_REGISTER_REG (CMD_MI | (0x2A << 23))
>  
> -#define MI_FLUSH_DW  (CMD_MI | (0x26 << 23) | 2)
> +#define MI_FLUSH_DW  (CMD_MI | (0x26 << 23))
>  
>  #define MI_STORE_REGISTER_MEM(CMD_MI | (0x24 << 23))
>  # define MI_STORE_REGISTER_MEM_USE_GGTT  (1 << 22)
> 

Reviewed-by: Kenneth Graunke 


signature.asc
Description: This is a digitally signed message part.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 1/3] radv: drop radv_cmd_dirty_mask_t typedef

[Bas Nieuwenhuizen]

For the series

Reviewed-by: Bas Nieuwenhuizen 

On Tue, Nov 14, 2017 at 5:27 PM, Samuel Pitoiset
 wrote:
> I don't think we will need a 64-bit unsigned integer for the
> dirty flags in the future, and there is still 20 bits left.
>
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/amd/vulkan/radv_pipeline.c | 2 +-
>  src/amd/vulkan/radv_private.h  | 3 +--
>  2 files changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
> index f006dc98c0..faffca8330 100644
> --- a/src/amd/vulkan/radv_pipeline.c
> +++ b/src/amd/vulkan/radv_pipeline.c
> @@ -1019,7 +1019,7 @@ static void
>  radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
>  const VkGraphicsPipelineCreateInfo 
> *pCreateInfo)
>  {
> -   radv_cmd_dirty_mask_t states = RADV_CMD_DIRTY_DYNAMIC_ALL;
> +   uint32_t states = RADV_CMD_DIRTY_DYNAMIC_ALL;
> RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
> struct radv_subpass *subpass = >subpasses[pCreateInfo->subpass];
>
> diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
> index 4281cd39c1..2de3eccf0e 100644
> --- a/src/amd/vulkan/radv_private.h
> +++ b/src/amd/vulkan/radv_private.h
> @@ -702,7 +702,6 @@ enum radv_cmd_dirty_bits {
> RADV_CMD_DIRTY_INDEX_BUFFER  = 1 << 10,
> RADV_CMD_DIRTY_FRAMEBUFFER   = 1 << 11,
>  };
> -typedef uint32_t radv_cmd_dirty_mask_t;
>
>  enum radv_cmd_flush_bits {
> RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
> @@ -817,7 +816,7 @@ struct radv_cmd_state {
>
> bool  push_descriptors_dirty;
> bool predicating;
> -   radv_cmd_dirty_mask_t dirty;
> +   uint32_t  dirty;
>
> struct radv_pipeline *pipeline;
> struct radv_pipeline *emitted_pipeline;
> --
> 2.15.0
>
> ___
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 1/2] radv: do not add the image BO in radv_set_color_clear_regs()

[Bas Nieuwenhuizen]

Reviewed-by: Bas Nieuwenhuizen 

On Tue, Nov 14, 2017 at 4:38 PM, Samuel Pitoiset
 wrote:
> radv_fill_buffer() ensures that the image BO is added to the list.
>
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/amd/vulkan/radv_cmd_buffer.c | 2 --
>  1 file changed, 2 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_cmd_buffer.c 
> b/src/amd/vulkan/radv_cmd_buffer.c
> index 2e94c125be..95e3953118 100644
> --- a/src/amd/vulkan/radv_cmd_buffer.c
> +++ b/src/amd/vulkan/radv_cmd_buffer.c
> @@ -1396,8 +1396,6 @@ radv_set_color_clear_regs(struct radv_cmd_buffer 
> *cmd_buffer,
> if (!image->cmask.size && !image->surface.dcc_size)
> return;
>
> -   radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, image->bo, 
> 8);
> -
> radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
> radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
> S_370_WR_CONFIRM(1) |
> --
> 2.15.0
>
> ___
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 2/2] radv: do not add the image BO in radv_set_dcc_need_cmask_elim_pred()

[Bas Nieuwenhuizen]

Reviewed-by: Bas Nieuwenhuizen 

On Tue, Nov 14, 2017 at 4:38 PM, Samuel Pitoiset
 wrote:
> radv_fill_buffer() ensures that the image BO is added to the list.
>
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/amd/vulkan/radv_cmd_buffer.c | 2 --
>  1 file changed, 2 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_cmd_buffer.c 
> b/src/amd/vulkan/radv_cmd_buffer.c
> index 95e3953118..6503c031bd 100644
> --- a/src/amd/vulkan/radv_cmd_buffer.c
> +++ b/src/amd/vulkan/radv_cmd_buffer.c
> @@ -1372,8 +1372,6 @@ radv_set_dcc_need_cmask_elim_pred(struct 
> radv_cmd_buffer *cmd_buffer,
> if (!image->surface.dcc_size)
> return;
>
> -   radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, image->bo, 
> 8);
> -
> radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
> radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
> S_370_WR_CONFIRM(1) |
> --
> 2.15.0
>
> ___
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] radv: use an unsigned 32-bit integer for radv_queue::family_index

[Bas Nieuwenhuizen]

Reviewed-by: Bas Nieuwenhuizen 

On Tue, Nov 14, 2017 at 5:29 PM, Samuel Pitoiset
 wrote:
> VkDeviceQueueCreateInfo::queueFamilyIndex is an unsigned 32-bit
> integer.
>
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/amd/vulkan/radv_device.c  | 2 +-
>  src/amd/vulkan/radv_private.h | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
> index 50dbe061d5..b62aa2 100644
> --- a/src/amd/vulkan/radv_device.c
> +++ b/src/amd/vulkan/radv_device.c
> @@ -911,7 +911,7 @@ radv_get_queue_global_priority(const 
> VkDeviceQueueGlobalPriorityCreateInfoEXT *p
>
>  static int
>  radv_queue_init(struct radv_device *device, struct radv_queue *queue,
> -   int queue_family_index, int idx,
> +   uint32_t queue_family_index, int idx,
> const VkDeviceQueueGlobalPriorityCreateInfoEXT 
> *global_priority)
>  {
> queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
> diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
> index 3e5cd6562a..8b03591b5c 100644
> --- a/src/amd/vulkan/radv_private.h
> +++ b/src/amd/vulkan/radv_private.h
> @@ -506,7 +506,7 @@ struct radv_queue {
> struct radv_device * device;
> struct radeon_winsys_ctx*hw_ctx;
> enum radeon_ctx_priority priority;
> -   int queue_family_index;
> +   uint32_t queue_family_index;
> int queue_idx;
>
> uint32_t scratch_size;
> --
> 2.15.0
>
> ___
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] i965: Remove DWord length from MI_FLUSH_DW definition

[Nanley Chery]

On Tue, Nov 14, 2017 at 02:52:35PM -0800, Anuj Phogat wrote:
> This fixes the changes introduced in commit 6165fda59b.
> 
> Signed-off-by: Anuj Phogat 
> Cc: 
> Cc: Nanley Chery 
> Cc: Kenneth Graunke 
> ---
>  src/mesa/drivers/dri/i965/brw_defines.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 

This patch is
Reviewed-by: Nanley Chery 

> diff --git a/src/mesa/drivers/dri/i965/brw_defines.h 
> b/src/mesa/drivers/dri/i965/brw_defines.h
> index 26f6ae6b2f..59d9e5cf21 100644
> --- a/src/mesa/drivers/dri/i965/brw_defines.h
> +++ b/src/mesa/drivers/dri/i965/brw_defines.h
> @@ -1430,7 +1430,7 @@ enum brw_pixel_shader_coverage_mask_mode {
>  #define MI_LOAD_REGISTER_IMM (CMD_MI | (0x22 << 23))
>  #define MI_LOAD_REGISTER_REG (CMD_MI | (0x2A << 23))
>  
> -#define MI_FLUSH_DW  (CMD_MI | (0x26 << 23) | 2)
> +#define MI_FLUSH_DW  (CMD_MI | (0x26 << 23))
>  
>  #define MI_STORE_REGISTER_MEM(CMD_MI | (0x24 << 23))
>  # define MI_STORE_REGISTER_MEM_USE_GGTT  (1 << 22)
> -- 
> 2.13.5
> 
> ___
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 01/14] anv/cmd_buffer: Advance the address when initializing clear colors

[Nanley Chery]

On Tue, Nov 14, 2017 at 02:30:31PM +, Lionel Landwerlin wrote:
> On 13/11/17 22:07, Jason Ekstrand wrote:
> > On Mon, Nov 13, 2017 at 1:30 PM, Nanley Chery  > > wrote:
> > 
> > On Mon, Nov 13, 2017 at 08:12:41AM -0800, Jason Ekstrand wrote:
> > > Found by inspection
> > >
> > 
> > Good catch.
> > 
> > > Cc: mesa-sta...@lists.freedesktop.org
> > 
> > > ---
> > >  src/intel/vulkan/genX_cmd_buffer.c | 9 ++---
> > >  1 file changed, 6 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/src/intel/vulkan/genX_cmd_buffer.c
> > b/src/intel/vulkan/genX_cmd_buffer.c
> > > index fbb5706..2564976 100644
> > > --- a/src/intel/vulkan/genX_cmd_buffer.c
> > > +++ b/src/intel/vulkan/genX_cmd_buffer.c
> > > @@ -557,12 +557,13 @@ init_fast_clear_state_entry(struct
> > anv_cmd_buffer *cmd_buffer,
> > >     /* Other combinations of auxiliary buffers and platforms
> > require specific
> > >      * values in the clear value dword(s).
> > >      */
> > > +   struct anv_address addr =
> > > +      get_fast_clear_state_address(cmd_buffer->device, image,
> > aspect, level,
> > > +  FAST_CLEAR_STATE_FIELD_CLEAR_COLOR);
> > >     unsigned i = 0;
> > >     for (; i < cmd_buffer->device->isl_dev.ss.clear_value_size;
> > i += 4) {
> > >        anv_batch_emit(_buffer->batch,
> > GENX(MI_STORE_DATA_IMM), sdi) {
> > > -         sdi.Address =
> > > -            get_fast_clear_state_address(cmd_buffer->device,
> > image, aspect, level,
> > > -  FAST_CLEAR_STATE_FIELD_CLEAR_COLOR);
> > > +         sdi.Address = addr;
> > 
> > The loop increments the variable i by 4 with every iteration. How
> > about
> > the following instead:
> >             sdi.Address = addr + i;
> > 
> > 
> > I really wish we could do that but it's a struct.  I could do
> > 

Whoops.

> > sdi.Address = addr;
> > sdi.Address.offset += i;
> > 

That looks good to me. No worries if you choose to go with the fix you
mentioned below. With one of these fixes, this patch is
Reviewed-by: Nanley Chery 

> > --Jason
> > 
> > -Nanley
> > 
> > >
> > >           if (GEN_GEN >= 9) {
> > >              /* MCS buffers on SKL+ can only have 1/0 clear
> > colors. */
> > > @@ -586,6 +587,8 @@ init_fast_clear_state_entry(struct
> > anv_cmd_buffer *cmd_buffer,
> > >              sdi.ImmediateData = 0;
> > >           }
> > >        }
> > > +
> > > +      addr += 4;
> > 
> > 
> > Aparently, I didn't compile-test this because I need a .offset here. :/
> 
> Heh, I was confused too :)
> With that fixed :
> 
> Reviewed-by: Lionel Landwerlin 
> 
> > >     }
> > >  }
> > >
> > > --
> > > 2.5.0.400.gff86faf
> > >
> > > ___
> > > mesa-dev mailing list
> > > mesa-dev@lists.freedesktop.org
> > 
> > > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
> > 
> > 
> > 
> > 
> > 
> > ___
> > mesa-dev mailing list
> > mesa-dev@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
> 
> 
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 2/2] i965: Implement ARB_texture_filter_minmax

[Scott D Phillips]

On gen >= 9, minmax reduction modes are available as a flag in
SAMPLER_STATE.
---
 docs/features.txt |  2 +-
 src/mesa/drivers/dri/i965/brw_formatquery.c   |  4 
 src/mesa/drivers/dri/i965/genX_state_upload.c | 10 ++
 src/mesa/drivers/dri/i965/intel_extensions.c  |  1 +
 4 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/docs/features.txt b/docs/features.txt
index 86d07ba80b..9ec3f2b975 100644
--- a/docs/features.txt
+++ b/docs/features.txt
@@ -312,7 +312,7 @@ Khronos, ARB, and OES extensions that are not part of any 
OpenGL or OpenGL ES ve
   GL_ARB_sparse_texture not started
   GL_ARB_sparse_texture2not started
   GL_ARB_sparse_texture_clamp   not started
-  GL_ARB_texture_filter_minmax  not started
+  GL_ARB_texture_filter_minmax  DONE (i965)
   GL_EXT_memory_object  DONE (radeonsi)
   GL_EXT_memory_object_fd   DONE (radeonsi)
   GL_EXT_memory_object_win32not started
diff --git a/src/mesa/drivers/dri/i965/brw_formatquery.c 
b/src/mesa/drivers/dri/i965/brw_formatquery.c
index 4f3b9e467b..bb2281f571 100644
--- a/src/mesa/drivers/dri/i965/brw_formatquery.c
+++ b/src/mesa/drivers/dri/i965/brw_formatquery.c
@@ -107,6 +107,10 @@ brw_query_internal_format(struct gl_context *ctx, GLenum 
target,
   break;
}
 
+   case GL_TEXTURE_REDUCTION_MODE_ARB:
+  params[0] = GL_TRUE;
+  break;
+
default:
   /* By default, we call the driver hook's fallback function from the 
frontend,
* which has generic implementation for all pnames.
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c 
b/src/mesa/drivers/dri/i965/genX_state_upload.c
index 453b8e4add..8af907648b 100644
--- a/src/mesa/drivers/dri/i965/genX_state_upload.c
+++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
@@ -5094,6 +5094,16 @@ genX(update_sampler_state)(struct brw_context *brw,
samp_st.LODPreClampEnable = true;
 #endif
 
+#if GEN_GEN >= 9
+   if (sampler->ReductionMode != GL_WEIGHTED_AVERAGE_ARB) {
+  samp_st.ReductionTypeEnable = true;
+  if (sampler->ReductionMode == GL_MIN)
+ samp_st.ReductionType = MINIMUM;
+  else
+ samp_st.ReductionType = MAXIMUM;
+   }
+#endif
+
GENX(SAMPLER_STATE_pack)(brw, sampler_state, _st);
 }
 
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c 
b/src/mesa/drivers/dri/i965/intel_extensions.c
index 4d17393948..e280474875 100644
--- a/src/mesa/drivers/dri/i965/intel_extensions.c
+++ b/src/mesa/drivers/dri/i965/intel_extensions.c
@@ -285,6 +285,7 @@ intelInitExtensions(struct gl_context *ctx)
if (devinfo->gen >= 9) {
   ctx->Extensions.ANDROID_extension_pack_es31a = true;
   ctx->Extensions.ARB_shader_stencil_export = true;
+  ctx->Extensions.ARB_texture_filter_minmax = true;
   ctx->Extensions.KHR_blend_equation_advanced_coherent = true;
   ctx->Extensions.KHR_texture_compression_astc_ldr = true;
   ctx->Extensions.KHR_texture_compression_astc_sliced_3d = true;
-- 
2.14.3

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 1/2] mesa: Implement ARB_texture_filter_minmax

[Scott D Phillips]

This extension provides a new texture and sampler parameter
(TEXTURE_REDUCTION_MODE_ARB) which allows applications to produce
a filtered texel value by computing a component-wise minimum (MIN)
or maximum (MAX) of the texels that would normally be averaged.
---
CTS tests KHR-GL45.texture_filter_minmax_tests.* need a little TLC to
pass with this series. Details in VK-GL-CTS issue: 849

 src/mesa/main/attrib.c   |  4 
 src/mesa/main/extensions_table.h |  1 +
 src/mesa/main/formatquery.c  | 10 ++
 src/mesa/main/mtypes.h   |  2 ++
 src/mesa/main/samplerobj.c   | 37 +
 src/mesa/main/texobj.c   |  2 ++
 src/mesa/main/texobj.h   |  2 +-
 src/mesa/main/texparam.c | 33 +
 8 files changed, 90 insertions(+), 1 deletion(-)

diff --git a/src/mesa/main/attrib.c b/src/mesa/main/attrib.c
index 43b5856901..a5c9a32513 100644
--- a/src/mesa/main/attrib.c
+++ b/src/mesa/main/attrib.c
@@ -884,6 +884,10 @@ pop_texture_group(struct gl_context *ctx, struct 
texture_state *texstate)
 _mesa_TexParameterf(target, GL_TEXTURE_MAX_ANISOTROPY_EXT,
 samp->MaxAnisotropy);
  }
+ if (ctx->Extensions.ARB_texture_filter_minmax) {
+_mesa_TexParameteri(target, GL_TEXTURE_REDUCTION_MODE_ARB,
+samp->ReductionMode);
+ }
  if (ctx->Extensions.ARB_shadow) {
 _mesa_TexParameteri(target, GL_TEXTURE_COMPARE_MODE,
 samp->CompareMode);
diff --git a/src/mesa/main/extensions_table.h b/src/mesa/main/extensions_table.h
index 5b66e7d30d..c51ad80742 100644
--- a/src/mesa/main/extensions_table.h
+++ b/src/mesa/main/extensions_table.h
@@ -146,6 +146,7 @@ EXT(ARB_texture_env_combine , 
ARB_texture_env_combine
 EXT(ARB_texture_env_crossbar, ARB_texture_env_crossbar 
  , GLL,  x ,  x ,  x , 2001)
 EXT(ARB_texture_env_dot3, ARB_texture_env_dot3 
  , GLL,  x ,  x ,  x , 2001)
 EXT(ARB_texture_filter_anisotropic  , ARB_texture_filter_anisotropic   
  , GLL, GLC,  x ,  x , 2017)
+EXT(ARB_texture_filter_minmax   , ARB_texture_filter_minmax
  , GLL, GLC,  x ,  x , 2017)
 EXT(ARB_texture_float   , ARB_texture_float
  , GLL, GLC,  x ,  x , 2004)
 EXT(ARB_texture_gather  , ARB_texture_gather   
  , GLL, GLC,  x ,  x , 2009)
 EXT(ARB_texture_mirror_clamp_to_edge, ARB_texture_mirror_clamp_to_edge 
  , GLL, GLC,  x ,  x , 2013)
diff --git a/src/mesa/main/formatquery.c b/src/mesa/main/formatquery.c
index 61f798c88f..78f2bfabe9 100644
--- a/src/mesa/main/formatquery.c
+++ b/src/mesa/main/formatquery.c
@@ -218,6 +218,7 @@ _legal_parameters(struct gl_context *ctx, GLenum target, 
GLenum internalformat,
case GL_VIEW_COMPATIBILITY_CLASS:
case GL_NUM_TILING_TYPES_EXT:
case GL_TILING_TYPES_EXT:
+   case GL_TEXTURE_REDUCTION_MODE_ARB:
   /* The ARB_internalformat_query spec says:
*
* "If the  parameter to GetInternalformativ is not SAMPLES
@@ -375,6 +376,7 @@ _set_default_response(GLenum pname, GLint buffer[16])
case GL_STENCIL_RENDERABLE:
case GL_MIPMAP:
case GL_TEXTURE_COMPRESSED:
+   case GL_TEXTURE_REDUCTION_MODE_ARB:
   buffer[0] = GL_FALSE;
   break;
 
@@ -1542,6 +1544,14 @@ _mesa_GetInternalformativ(GLenum target, GLenum 
internalformat, GLenum pname,
   buffer);
   break;
 
+   case GL_TEXTURE_REDUCTION_MODE_ARB:
+  if (!_mesa_has_ARB_texture_filter_minmax(ctx))
+ goto end;
+
+  ctx->Driver.QueryInternalFormat(ctx, target, internalformat, pname,
+  buffer);
+  break;
+
default:
   unreachable("bad param");
}
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 6b5c5bbb36..3a6488d475 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -989,6 +989,7 @@ struct gl_sampler_object
GLenum CompareFunc; /**< GL_ARB_shadow */
GLenum sRGBDecode;   /**< GL_DECODE_EXT or GL_SKIP_DECODE_EXT */
GLboolean CubeMapSeamless;   /**< GL_AMD_seamless_cubemap_per_texture */
+   GLenum ReductionMode;/**< GL_ARB_texture_filter_minmax */
 
/** GL_ARB_bindless_texture */
bool HandleAllocated;
@@ -4107,6 +4108,7 @@ struct gl_extensions
GLboolean ARB_texture_env_crossbar;
GLboolean ARB_texture_env_dot3;
GLboolean ARB_texture_filter_anisotropic;
+   GLboolean ARB_texture_filter_minmax;
GLboolean ARB_texture_float;
GLboolean ARB_texture_gather;
GLboolean ARB_texture_mirror_clamp_to_edge;
diff --git a/src/mesa/main/samplerobj.c b/src/mesa/main/samplerobj.c
index 5ebf9e24f9..eb518ef25d 100644
--- a/src/mesa/main/samplerobj.c
+++ b/src/mesa/main/samplerobj.c
@@ -135,6 

[Mesa-dev] [PATCH] i965: Remove DWord length from MI_FLUSH_DW definition

[Anuj Phogat]

This fixes the changes introduced in commit 6165fda59b.

Signed-off-by: Anuj Phogat 
Cc: 
Cc: Nanley Chery 
Cc: Kenneth Graunke 
---
 src/mesa/drivers/dri/i965/brw_defines.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h 
b/src/mesa/drivers/dri/i965/brw_defines.h
index 26f6ae6b2f..59d9e5cf21 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1430,7 +1430,7 @@ enum brw_pixel_shader_coverage_mask_mode {
 #define MI_LOAD_REGISTER_IMM   (CMD_MI | (0x22 << 23))
 #define MI_LOAD_REGISTER_REG   (CMD_MI | (0x2A << 23))
 
-#define MI_FLUSH_DW(CMD_MI | (0x26 << 23) | 2)
+#define MI_FLUSH_DW(CMD_MI | (0x26 << 23))
 
 #define MI_STORE_REGISTER_MEM  (CMD_MI | (0x24 << 23))
 # define MI_STORE_REGISTER_MEM_USE_GGTT(1 << 22)
-- 
2.13.5

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] svga: issue debug warning for unsupported two-sided stencil state

[Neha Bhende]

Looks good to me.


Reviewed-by: Neha Bhende 


Regards,

Neha


From: mesa-dev  on behalf of Brian Paul 

Sent: Friday, November 10, 2017 6:40:26 PM
To: mesa-dev@lists.freedesktop.org
Subject: [Mesa-dev] [PATCH] svga: issue debug warning for unsupported two-sided 
stencil state

We only have a single stencil read mask and write mask.  Issue a
warning if different front/back values are used.  The Piglit
gl-2.0-two-sided-stencil test hits this.
---
 src/gallium/drivers/svga/svga_pipe_depthstencil.c | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/src/gallium/drivers/svga/svga_pipe_depthstencil.c 
b/src/gallium/drivers/svga/svga_pipe_depthstencil.c
index 1b62290..e5caa4b 100644
--- a/src/gallium/drivers/svga/svga_pipe_depthstencil.c
+++ b/src/gallium/drivers/svga/svga_pipe_depthstencil.c
@@ -172,6 +172,21 @@ svga_create_depth_stencil_state(struct pipe_context *pipe,

   ds->stencil_mask  = templ->stencil[1].valuemask & 0xff;
   ds->stencil_writemask = templ->stencil[1].writemask & 0xff;
+
+  if (templ->stencil[1].valuemask != templ->stencil[0].valuemask) {
+ pipe_debug_message(>debug.callback, CONFORMANCE,
+"two-sided stencil mask not supported "
+"(front=0x%x, back=0x%x)",
+templ->stencil[0].valuemask,
+templ->stencil[1].valuemask);
+  }
+  if (templ->stencil[1].writemask != templ->stencil[0].writemask) {
+ pipe_debug_message(>debug.callback, CONFORMANCE,
+"two-sided stencil writemask not supported "
+"(front=0x%x, back=0x%x)",
+templ->stencil[0].writemask,
+templ->stencil[1].writemask);
+  }
}
else {
   /* back face state is same as front-face state */
--
1.9.1

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://urldefense.proofpoint.com/v2/url?u=https-3A__lists.freedesktop.org_mailman_listinfo_mesa-2Ddev=DwIGaQ=uilaK90D4TOVoH58JNXRgQ=U9C05uEFArICiTQ6FqFIgVCB-YGE5G2JTThVEccv_Ec=G0jOYq_LoVonAPIAMBNujnLcGheNLWedG3WtYO3mbn0=QluX83Fb70cz1E8pS8V7mR4zpiIvPP-mO6XYaN-D7bU=
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 1/3] i965: Program DWord Length in MI_FLUSH_DW

[Anuj Phogat]

Signed-off-by: Anuj Phogat 
Cc: 
---
This series has already been pushed upstream. Nanley and Ken has
taken a look at the patches. I'll send out a separate patch for
a small change suggested by them.

 src/mesa/drivers/dri/i965/brw_pipe_control.c | 2 +-
 src/mesa/drivers/dri/i965/intel_blit.c   | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c 
b/src/mesa/drivers/dri/i965/brw_pipe_control.c
index bae4ba7c00..35f326a5c5 100644
--- a/src/mesa/drivers/dri/i965/brw_pipe_control.c
+++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c
@@ -462,7 +462,7 @@ brw_emit_mi_flush(struct brw_context *brw)
 
if (brw->batch.ring == BLT_RING && devinfo->gen >= 6) {
   BEGIN_BATCH_BLT(4);
-  OUT_BATCH(MI_FLUSH_DW);
+  OUT_BATCH(MI_FLUSH_DW | (4 - 2));
   OUT_BATCH(0);
   OUT_BATCH(0);
   OUT_BATCH(0);
diff --git a/src/mesa/drivers/dri/i965/intel_blit.c 
b/src/mesa/drivers/dri/i965/intel_blit.c
index 13431a7bd2..3d7bc92d13 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -104,7 +104,7 @@ set_blitter_tiling(struct brw_context *brw,
assert(brw->screen->devinfo.gen >= 6);
 
/* Idle the blitter before we update how tiling is interpreted. */
-   OUT_BATCH(MI_FLUSH_DW);
+   OUT_BATCH(MI_FLUSH_DW | (4 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
-- 
2.13.5

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 1/2] r600/shader: reserve first register of vertex shader.

[Dave Airlie]

On 15 November 2017 at 01:12, Andres Gomez  wrote:
> Dave, this nominated patch landed without mentioning any specific
> stable queue.
>
> From what I'm seeing, they depend on ea1b97714d9b which didn't make it
> for 17.2 so I'm dropping it for that queue.
>
> Let me know what you think.

Oh interesting, yes it's a actually fixing a regression since that
commit, I hadn't spotted the
regression what there at all.

So fine to drop.

Dave.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 2/3] i965/gen8+: Fix the number of dwords programmed in MI_FLUSH_DW

[Anuj Phogat]

Number of dwords in MI_FLUSH_DW changed from 4 to 5 in gen8+.

Signed-off-by: Anuj Phogat 
Cc: 
---
 src/mesa/drivers/dri/i965/brw_pipe_control.c |  7 +--
 src/mesa/drivers/dri/i965/intel_blit.c   | 17 ++---
 2 files changed, 19 insertions(+), 5 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c 
b/src/mesa/drivers/dri/i965/brw_pipe_control.c
index 35f326a5c5..39e8bff730 100644
--- a/src/mesa/drivers/dri/i965/brw_pipe_control.c
+++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c
@@ -461,11 +461,14 @@ brw_emit_mi_flush(struct brw_context *brw)
const struct gen_device_info *devinfo = >screen->devinfo;
 
if (brw->batch.ring == BLT_RING && devinfo->gen >= 6) {
-  BEGIN_BATCH_BLT(4);
-  OUT_BATCH(MI_FLUSH_DW | (4 - 2));
+  const unsigned n_dwords = devinfo->gen >= 8 ? 5 : 4;
+  BEGIN_BATCH_BLT(n_dwords);
+  OUT_BATCH(MI_FLUSH_DW | (n_dwords - 2));
   OUT_BATCH(0);
   OUT_BATCH(0);
   OUT_BATCH(0);
+  if (n_dwords == 5)
+ OUT_BATCH(0);
   ADVANCE_BATCH();
} else {
   int flags = PIPE_CONTROL_NO_WRITE | PIPE_CONTROL_RENDER_TARGET_FLUSH;
diff --git a/src/mesa/drivers/dri/i965/intel_blit.c 
b/src/mesa/drivers/dri/i965/intel_blit.c
index 3d7bc92d13..5f25bfaf61 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -101,13 +101,17 @@ set_blitter_tiling(struct brw_context *brw,
bool dst_y_tiled, bool src_y_tiled,
uint32_t *__map)
 {
-   assert(brw->screen->devinfo.gen >= 6);
+   const struct gen_device_info *devinfo = >screen->devinfo;
+   const unsigned n_dwords = devinfo->gen >= 8 ? 5 : 4;
+   assert(devinfo->gen >= 6);
 
/* Idle the blitter before we update how tiling is interpreted. */
-   OUT_BATCH(MI_FLUSH_DW | (4 - 2));
+   OUT_BATCH(MI_FLUSH_DW | (n_dwords - 2));
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
+   if (n_dwords == 5)
+  OUT_BATCH(0);
 
OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
OUT_BATCH(BCS_SWCTRL);
@@ -119,7 +123,14 @@ set_blitter_tiling(struct brw_context *brw,
 #define SET_BLITTER_TILING(...) __map = set_blitter_tiling(__VA_ARGS__, __map)
 
 #define BEGIN_BATCH_BLT_TILED(n, dst_y_tiled, src_y_tiled)  \
-  BEGIN_BATCH_BLT(n + ((dst_y_tiled || src_y_tiled) ? 14 : 0)); \
+  unsigned set_tiling_batch_size = 0;   \
+  if (dst_y_tiled || src_y_tiled) { \
+ if (devinfo->gen >= 8) \
+set_tiling_batch_size = 16; \
+ else   \
+set_tiling_batch_size = 14; \
+  } \
+  BEGIN_BATCH_BLT(n + set_tiling_batch_size);   \
   if (dst_y_tiled || src_y_tiled)   \
  SET_BLITTER_TILING(brw, dst_y_tiled, src_y_tiled)
 
-- 
2.13.5

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 3/3] i965: Make use of brw_load_register_imm32() helper function

[Anuj Phogat]

Signed-off-by: Anuj Phogat 
Cc: Nanley Chery 
---
 src/mesa/drivers/dri/i965/brw_draw.c |  6 +-
 src/mesa/drivers/dri/i965/brw_state_upload.c | 22 --
 src/mesa/drivers/dri/i965/gen7_l3_state.c| 17 ++---
 src/mesa/drivers/dri/i965/gen7_sol_state.c   |  6 +-
 src/mesa/drivers/dri/i965/gen8_depth_state.c |  8 +++-
 5 files changed, 19 insertions(+), 40 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_draw.c 
b/src/mesa/drivers/dri/i965/brw_draw.c
index 8920b0031b..7e29dcfd4e 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -242,11 +242,7 @@ brw_emit_prim(struct brw_context *brw,
   } else {
  brw_load_register_mem(brw, GEN7_3DPRIM_START_INSTANCE, bo,
prim->indirect_offset + 12);
- BEGIN_BATCH(3);
- OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
- OUT_BATCH(GEN7_3DPRIM_BASE_VERTEX);
- OUT_BATCH(0);
- ADVANCE_BATCH();
+ brw_load_register_imm32(brw, GEN7_3DPRIM_BASE_VERTEX, 0);
   }
} else {
   indirect_flag = 0;
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c 
b/src/mesa/drivers/dri/i965/brw_state_upload.c
index f54e15e92b..da464ef7b1 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -86,22 +86,16 @@ brw_upload_initial_gpu_state(struct brw_context *brw)
   /* Recommended optimizations for Victim Cache eviction and floating
* point blending.
*/
-  BEGIN_BATCH(3);
-  OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
-  OUT_BATCH(GEN7_CACHE_MODE_1);
-  OUT_BATCH(REG_MASK(GEN9_FLOAT_BLEND_OPTIMIZATION_ENABLE) |
-REG_MASK(GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC) |
-GEN9_FLOAT_BLEND_OPTIMIZATION_ENABLE |
-GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC);
-  ADVANCE_BATCH();
+  brw_load_register_imm32(brw, GEN7_CACHE_MODE_1,
+  REG_MASK(GEN9_FLOAT_BLEND_OPTIMIZATION_ENABLE) |
+  REG_MASK(GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC) |
+  GEN9_FLOAT_BLEND_OPTIMIZATION_ENABLE |
+  GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC);
 
   if (gen_device_info_is_9lp(devinfo)) {
- BEGIN_BATCH(3);
- OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
- OUT_BATCH(GEN7_GT_MODE);
- OUT_BATCH(GEN9_SUBSLICE_HASHING_MASK_BITS |
-   GEN9_SUBSLICE_HASHING_16x16);
- ADVANCE_BATCH();
+ brw_load_register_imm32(brw, GEN7_GT_MODE,
+ GEN9_SUBSLICE_HASHING_MASK_BITS |
+ GEN9_SUBSLICE_HASHING_16x16);
   }
}
 
diff --git a/src/mesa/drivers/dri/i965/gen7_l3_state.c 
b/src/mesa/drivers/dri/i965/gen7_l3_state.c
index 06559f5db7..8c8f4169e7 100644
--- a/src/mesa/drivers/dri/i965/gen7_l3_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_l3_state.c
@@ -121,19 +121,14 @@ setup_l3_config(struct brw_context *brw, const struct 
gen_l3_config *cfg)
if (devinfo->gen >= 8) {
   assert(!cfg->n[GEN_L3P_IS] && !cfg->n[GEN_L3P_C] && !cfg->n[GEN_L3P_T]);
 
-  BEGIN_BATCH(3);
-  OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
+  const unsigned imm_data = ((has_slm ? GEN8_L3CNTLREG_SLM_ENABLE : 0) |
+ SET_FIELD(cfg->n[GEN_L3P_URB], GEN8_L3CNTLREG_URB_ALLOC) |
+ SET_FIELD(cfg->n[GEN_L3P_RO], GEN8_L3CNTLREG_RO_ALLOC) |
+ SET_FIELD(cfg->n[GEN_L3P_DC], GEN8_L3CNTLREG_DC_ALLOC) |
+ SET_FIELD(cfg->n[GEN_L3P_ALL], GEN8_L3CNTLREG_ALL_ALLOC));
 
   /* Set up the L3 partitioning. */
-  OUT_BATCH(GEN8_L3CNTLREG);
-  OUT_BATCH((has_slm ? GEN8_L3CNTLREG_SLM_ENABLE : 0) |
-SET_FIELD(cfg->n[GEN_L3P_URB], GEN8_L3CNTLREG_URB_ALLOC) |
-SET_FIELD(cfg->n[GEN_L3P_RO], GEN8_L3CNTLREG_RO_ALLOC) |
-SET_FIELD(cfg->n[GEN_L3P_DC], GEN8_L3CNTLREG_DC_ALLOC) |
-SET_FIELD(cfg->n[GEN_L3P_ALL], GEN8_L3CNTLREG_ALL_ALLOC));
-
-  ADVANCE_BATCH();
-
+  brw_load_register_imm32(brw, GEN8_L3CNTLREG, imm_data);
} else {
   assert(!cfg->n[GEN_L3P_ALL]);
 
diff --git a/src/mesa/drivers/dri/i965/gen7_sol_state.c 
b/src/mesa/drivers/dri/i965/gen7_sol_state.c
index 299e650731..2189ed1b74 100644
--- a/src/mesa/drivers/dri/i965/gen7_sol_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_sol_state.c
@@ -65,11 +65,7 @@ gen7_begin_transform_feedback(struct gl_context *ctx, GLenum 
mode,
   brw->batch.needs_sol_reset = true;
} else {
   for (int i = 0; i < 4; i++) {
- BEGIN_BATCH(3);
- OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
- OUT_BATCH(GEN7_SO_WRITE_OFFSET(i));
- OUT_BATCH(0);
- ADVANCE_BATCH();
+ brw_load_register_imm32(brw, GEN7_SO_WRITE_OFFSET(i), 0);
   }
}
 
diff --git 

Re: [Mesa-dev] [PATCH 4/6] glx: Lift sending the MakeCurrent request to top-level code

[Ian Romanick]

On 11/14/2017 02:18 PM, Adam Jackson wrote:
> On Tue, 2017-11-14 at 14:03 -0800, Ian Romanick wrote:
> 
>>>  static void
>>>  indirect_unbind_context(struct glx_context *gc, struct glx_context *new)
>>>  {
>>
>> Mark the parameters UNUSED so that I don't get extra warnings. :)
> 
> How do I provoke these warnings in my own build?

I use -Wall -Wextra -Wunsafe-loop-optimizations -Werror=format-security
-Wno-sign-compare, but I think -Wunused (set by -Wall) is sufficient to
provoke this particular warning.

> - ajax

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] i965: disable BLORP color clears for gen 4-5

[Jason Ekstrand]

On Tue, Nov 14, 2017 at 11:11 AM, Matt Turner  wrote:

> On Thu, Nov 9, 2017 at 9:23 AM, Jason Ekstrand 
> wrote:
> > This is a really rubbish solution.  Yes, it fixes a crash in MPV but
> unless
> > we disable all blorp on gen4-5 (which I don't think is possible
> anymore), we
> > haven't actually fixed it for real.
>
> Are you planning to look into it? It's one week until 17.3.0 is
> scheduled to be released.
>

I think Ken is going to try and look at it.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH] r600: fix cubemap arrays

[Dave Airlie]

From: Dave Airlie 

A lot of cubemap array piglits fail, port the texture type
picking code from radeonsi which seems to fix most of them.

For images I will port the rest of the code.

Fixes:
getteximage-depth gl_texture_cube_map_array-*
fbo-generatemipmap-cubemap array
getteximage-targets cube_array
amongst others.

Signed-off-by: Dave Airlie 
---
 src/gallium/drivers/r600/evergreen_state.c | 26 +-
 1 file changed, 17 insertions(+), 9 deletions(-)

diff --git a/src/gallium/drivers/r600/evergreen_state.c 
b/src/gallium/drivers/r600/evergreen_state.c
index 68977bb..b02d7ee 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -169,9 +169,20 @@ static uint32_t r600_translate_blend_factor(int blend_fact)
return 0;
 }
 
-static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
+static unsigned r600_tex_dim(struct r600_texture *rtex,
+unsigned view_target, unsigned nr_samples)
 {
-   switch (dim) {
+   unsigned res_target = rtex->resource.b.b.target;
+
+   if (view_target == PIPE_TEXTURE_CUBE ||
+   view_target == PIPE_TEXTURE_CUBE_ARRAY)
+   res_target = view_target;
+   /* If interpreting cubemaps as something else, set 2D_ARRAY. */
+   else if (res_target == PIPE_TEXTURE_CUBE ||
+res_target == PIPE_TEXTURE_CUBE_ARRAY)
+   res_target = PIPE_TEXTURE_2D_ARRAY;
+
+   switch (res_target) {
default:
case PIPE_TEXTURE_1D:
return V_03_SQ_TEX_DIM_1D;
@@ -805,13 +816,10 @@ static int evergreen_fill_tex_resource_words(struct 
r600_context *rctx,
va = tmp->resource.gpu_address;
 
/* array type views and views into array types need to use layer offset 
*/
-   dim = params->target;
-   if (params->target != PIPE_TEXTURE_CUBE)
-   dim = MAX2(params->target, texture->target);
-
-   tex_resource_words[0] = (S_03_DIM(r600_tex_dim(dim, 
texture->nr_samples)) |
-  S_03_PITCH((pitch / 8) - 1) |
-  S_03_TEX_WIDTH(width - 1));
+   dim = r600_tex_dim(tmp, params->target, texture->nr_samples);
+   tex_resource_words[0] = (S_03_DIM(dim) |
+S_03_PITCH((pitch / 8) - 1) |
+S_03_TEX_WIDTH(width - 1));
if (rscreen->b.chip_class == CAYMAN)
tex_resource_words[0] |= 
CM_S_03_NON_DISP_TILING_ORDER(non_disp_tiling);
else
-- 
2.9.5

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 10/14] intel/blorp: Drop blorp_resolve_ccs_attachment

[Lionel Landwerlin]

Reviewed-by: Lionel Landwerlin 

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH] nir/clone: Free clone_state after use

[Eduardo Lima Mitev]

In nir_cf_list_clone(), a state_clone object is initialized but never
freed, causing a memory leak. If the remap_table argument is NULL,
init_state will create a hash table for it, and that's what
free_clone_state is supposed to free.
---
 src/compiler/nir/nir_clone.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/compiler/nir/nir_clone.c b/src/compiler/nir/nir_clone.c
index bcfdaa7594..c823acb6ee 100644
--- a/src/compiler/nir/nir_clone.c
+++ b/src/compiler/nir/nir_clone.c
@@ -660,6 +660,9 @@ nir_cf_list_clone(nir_cf_list *dst, nir_cf_list *src, 
nir_cf_node *parent,
clone_cf_list(, >list, >list);
 
fixup_phi_srcs();
+
+   if (!remap_table)
+  free_clone_state();
 }
 
 static nir_function_impl *
-- 
2.11.0

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 4/6] glx: Lift sending the MakeCurrent request to top-level code

[Adam Jackson]

On Tue, 2017-11-14 at 14:03 -0800, Ian Romanick wrote:

> >  static void
> >  indirect_unbind_context(struct glx_context *gc, struct glx_context *new)
> >  {
> 
> Mark the parameters UNUSED so that I don't get extra warnings. :)

How do I provoke these warnings in my own build?

- ajax
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] svga: issue debug warning for unsupported two-sided stencil state

[Charmaine Lee]

Reviewed-by: Charmaine Lee 


From: Brian Paul 
Sent: Friday, November 10, 2017 6:40:26 PM
To: mesa-dev@lists.freedesktop.org
Cc: Charmaine Lee
Subject: [PATCH] svga: issue debug warning for unsupported two-sided stencil 
state

We only have a single stencil read mask and write mask.  Issue a
warning if different front/back values are used.  The Piglit
gl-2.0-two-sided-stencil test hits this.
---
 src/gallium/drivers/svga/svga_pipe_depthstencil.c | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/src/gallium/drivers/svga/svga_pipe_depthstencil.c 
b/src/gallium/drivers/svga/svga_pipe_depthstencil.c
index 1b62290..e5caa4b 100644
--- a/src/gallium/drivers/svga/svga_pipe_depthstencil.c
+++ b/src/gallium/drivers/svga/svga_pipe_depthstencil.c
@@ -172,6 +172,21 @@ svga_create_depth_stencil_state(struct pipe_context *pipe,

   ds->stencil_mask  = templ->stencil[1].valuemask & 0xff;
   ds->stencil_writemask = templ->stencil[1].writemask & 0xff;
+
+  if (templ->stencil[1].valuemask != templ->stencil[0].valuemask) {
+ pipe_debug_message(>debug.callback, CONFORMANCE,
+"two-sided stencil mask not supported "
+"(front=0x%x, back=0x%x)",
+templ->stencil[0].valuemask,
+templ->stencil[1].valuemask);
+  }
+  if (templ->stencil[1].writemask != templ->stencil[0].writemask) {
+ pipe_debug_message(>debug.callback, CONFORMANCE,
+"two-sided stencil writemask not supported "
+"(front=0x%x, back=0x%x)",
+templ->stencil[0].writemask,
+templ->stencil[1].writemask);
+  }
}
else {
   /* back face state is same as front-face state */
--
1.9.1

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH v3 15/15] meson: build gallium xa state tracker

[Dylan Baker]

Quoting Marc Dietrich (2017-11-14 02:51:38)
> Hi Dylan,
> 
> Am Dienstag, 14. November 2017, 02:09:19 CET schrieb Dylan Baker:
> > v2: - set with_gallium_xa when -Dgallium-xa=true
> > - install pkg config file
> > ---
> >  meson.build   | 22 
> >  meson_options.txt |  7 +++
> >  src/gallium/meson.build   |  7 ++-
> >  src/gallium/state_trackers/xa/meson.build | 45 +
> >  src/gallium/targets/xa/meson.build| 84
> > +++ 5 files changed, 164 insertions(+), 1
> > deletion(-)
> >  create mode 100644 src/gallium/state_trackers/xa/meson.build
> >  create mode 100644 src/gallium/targets/xa/meson.build
> > 
> > diff --git a/meson.build b/meson.build
> > index 8c20523aab0..1d29eb67bfe 100644
> > --- a/meson.build
> > +++ b/meson.build
> > @@ -525,6 +525,28 @@ if va_drivers_path == ''
> >va_drivers_path = join_paths(get_option('libdir'), 'dri')
> >  endif
> > 
> > +_xa = get_option('gallium-xa')
> > +if _xa == 'auto'
> > +  if not ['linux', 'bsd'].contains(host_machine.system())
> > +with_gallium_xa = false
> > +  elif not (with_gallium_nouveau or with_gallium_freedreno or 
> with_gallium_i915 
> > +or with_gallium_svga)
> 
> autotools don't not have such limitation. At least it gets build with gallium-
> drivers=r600,swrast. However, not sure if it is useful.
> 
> Marc

autotools does the wrong thing in this case. For XA it checks that softpipe
(gallium swrast) + one non-swrast gallium driver is built. XA only works with
SVGA, freedreno, nouveau, and i915g though, so I've set the requirement to match
what the state_tracker actually does.

You can look at src/gallium/targets/xa/Makefile.am and see that it only works
with these drivers.

Dylan


signature.asc
Description: signature
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 6/6] glx: Implement GLX_EXT_no_config_context (v3)

[Ian Romanick]

On 11/14/2017 12:13 PM, Adam Jackson wrote:
> This more or less ports EGL_KHR_no_config_context to GLX.
> 
> v2: Enable the extension only for those backends that support it.
> v3: Fix glvnd path and dri2_convert_glx_attribs()
> 
> Khronos: https://github.com/KhronosGroup/OpenGL-Registry/pull/102
> Reviewed-by: Kenneth Graunke 
> Signed-off-by: Adam Jackson 
> ---
>  src/glx/create_context.c  | 41 
> ++-
>  src/glx/dri2_glx.c|  1 +
>  src/glx/dri3_glx.c|  1 +
>  src/glx/dri_common.c  |  4 
>  src/glx/drisw_glx.c   |  1 +
>  src/glx/g_glxglvnddispatchfuncs.c | 14 -
>  src/glx/glxcmds.c |  2 +-
>  src/glx/glxextensions.c   |  1 +
>  src/glx/glxextensions.h   |  1 +
>  9 files changed, 50 insertions(+), 16 deletions(-)
> 
> diff --git a/src/glx/create_context.c b/src/glx/create_context.c
> index 38e949ab4c..eab6511ad8 100644
> --- a/src/glx/create_context.c
> +++ b/src/glx/create_context.c
> @@ -47,21 +47,11 @@ glXCreateContextAttribsARB(Display *dpy, GLXFBConfig 
> config,
> xcb_generic_error_t *err;
> xcb_void_cookie_t cookie;
> unsigned dummy_err = 0;
> +   int screen = -1;
>  
> -
> -   if (dpy == NULL || cfg == NULL)
> -  return NULL;
> -
> -   /* This means that either the caller passed the wrong display pointer or
> -* one of the internal GLX data structures (probably the fbconfig) has an
> -* error.  There is nothing sensible to do, so return an error.
> -*/
> -   psc = GetGLXScreenConfigs(dpy, cfg->screen);
> -   if (psc == NULL)
> +   if (dpy == NULL)
>return NULL;
>  
> -   assert(cfg->screen == psc->scr);
> -
> /* Count the number of attributes specified by the application.  All
>  * attributes appear in pairs, except the terminating None.
>  */
> @@ -70,6 +60,29 @@ glXCreateContextAttribsARB(Display *dpy, GLXFBConfig 
> config,
>/* empty */ ;
> }
>  
> +   if (cfg) {
> +  screen = cfg->screen;
> +   } else {
> +  int i;

unsigned to prevent dumb GCC warnings.  Also, I'm pretty sure this code
can use C99 declarations in the for-loop.

Aside from that, this patch is

Reviewed-by: Ian Romanick 

> +  for (i = 0; i < num_attribs; i++) {
> + if (attrib_list[i * 2] == GLX_SCREEN)
> +screen = attrib_list[i * 2 + 1];
> +  }
> +   }
> +
> +   /* This means that either the caller passed the wrong display pointer or
> +* one of the internal GLX data structures (probably the fbconfig) has an
> +* error.  There is nothing sensible to do, so return an error.
> +*/
> +   psc = GetGLXScreenConfigs(dpy, screen);
> +   if (psc == NULL)
> +  return NULL;
> +
> +   assert(screen == psc->scr);
> +
> +   if (!cfg && !__glXExtensionBitIsEnabled(psc, EXT_no_config_context_bit))
> +  return NULL;
> +
> if (direct && psc->vtable->create_context_attribs) {
>/* GLX drops the error returned by the driver.  The expectation is that
> * an error will also be returned by the server.  The server's error
> @@ -104,8 +117,8 @@ glXCreateContextAttribsARB(Display *dpy, GLXFBConfig 
> config,
> cookie =
>xcb_glx_create_context_attribs_arb_checked(c,
>gc->xid,
> -  cfg->fbconfigID,
> -  cfg->screen,
> +  cfg ? cfg->fbconfigID : 0,
> +  screen,
>gc->share_xid,
>gc->isDirect,
>num_attribs,
> diff --git a/src/glx/dri2_glx.c b/src/glx/dri2_glx.c
> index 0f44635725..eeec4f0d60 100644
> --- a/src/glx/dri2_glx.c
> +++ b/src/glx/dri2_glx.c
> @@ -1129,6 +1129,7 @@ dri2BindExtensions(struct dri2_screen *psc, struct 
> glx_display * priv,
>  
>__glXEnableDirectExtension(>base, "GLX_ARB_create_context");
>__glXEnableDirectExtension(>base, 
> "GLX_ARB_create_context_profile");
> +  __glXEnableDirectExtension(>base, "GLX_EXT_no_config_context");
>  
>if ((mask & ((1 << __DRI_API_GLES) |
> (1 << __DRI_API_GLES2) |
> diff --git a/src/glx/dri3_glx.c b/src/glx/dri3_glx.c
> index a10306fe32..ac2e106a7e 100644
> --- a/src/glx/dri3_glx.c
> +++ b/src/glx/dri3_glx.c
> @@ -720,6 +720,7 @@ dri3_bind_extensions(struct dri3_screen *psc, struct 
> glx_display * priv,
>  
> __glXEnableDirectExtension(>base, "GLX_ARB_create_context");
> __glXEnableDirectExtension(>base, "GLX_ARB_create_context_profile");
> +   __glXEnableDirectExtension(>base, "GLX_EXT_no_config_context");
>  
> if ((mask & ((1 << __DRI_API_GLES) |
>  (1 << __DRI_API_GLES2) |
> diff --git 

Re: [Mesa-dev] [PATCH v3 14/15] meson: build gallium va state tracker

[Dylan Baker]

Quoting Marc Dietrich (2017-11-14 01:49:42)
> Hi Dylan,
> 
> Am Dienstag, 14. November 2017, 02:09:18 CET schrieb Dylan Baker:
> > v2: - set with_gallium_va when -Dgallium-va=true
> > - Fix megadrivers install
> > - only use cflags from pkg-config, don't add linker flags.
> > - Don't get version from pkg-config, it's not tracking the same
> >   version information.
> > ---
> >  meson.build   | 41 +-
> >  meson_options.txt | 13 +
> >  src/gallium/meson.build   |  7 ++-
> >  src/gallium/state_trackers/va/meson.build | 39 ++
> >  src/gallium/targets/va/meson.build| 89
> > +++ 5 files changed, 187 insertions(+), 2
> > deletions(-)
> >  create mode 100644 src/gallium/state_trackers/va/meson.build
> >  create mode 100644 src/gallium/targets/va/meson.build
> > 
> 
> snip
> 
> > diff --git a/src/gallium/state_trackers/va/meson.build
> > b/src/gallium/state_trackers/va/meson.build new file mode 100644
> > index 000..dd0d03b629a
> > --- /dev/null
> > +++ b/src/gallium/state_trackers/va/meson.build
> > @@ -0,0 +1,39 @@
> > +# Copyright © 2017 Intel Corporation
> > +
> > +# Permission is hereby granted, free of charge, to any person obtaining a
> > copy +# of this software and associated documentation files (the
> > "Software"), to deal +# in the Software without restriction, including
> > without limitation the rights +# to use, copy, modify, merge, publish,
> > distribute, sublicense, and/or sell +# copies of the Software, and to
> > permit persons to whom the Software is +# furnished to do so, subject to
> > the following conditions:
> > +
> > +# The above copyright notice and this permission notice shall be included
> > in +# all copies or substantial portions of the Software.
> > +
> > +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
> > OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> > MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
> > IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
> > CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
> > TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE
> > SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE.
> > +
> > +libva_version = va_version = ['2', '3', '0']
> 
> this gives an illegal assignment here.
> 
> Marc

Yup, I don't know why that was working for me before I sent it. Fixed locally.


signature.asc
Description: signature
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH v3 09/15] meson: extend install_megadrivers script to handle symmlinking

[Dylan Baker]

Quoting Eric Engestrom (2017-11-14 06:47:33)
> On Monday, 2017-11-13 17:09:13 -0800, Dylan Baker wrote:
> > which is required for the gallium media state trackers.
> > ---
> >  bin/install_megadrivers.py | 6 ++
> >  1 file changed, 6 insertions(+)
> > 
> > diff --git a/bin/install_megadrivers.py b/bin/install_megadrivers.py
> > index a98d7dd177b..581ff9791e5 100755
> > --- a/bin/install_megadrivers.py
> > +++ b/bin/install_megadrivers.py
> > @@ -33,6 +33,7 @@ def main():
> >  parser.add_argument('megadriver')
> >  parser.add_argument('libdir')
> >  parser.add_argument('drivers', nargs='+')
> > +parser.add_argument('--so-version', action='append', default=[])
> >  args = parser.parse_args()
> >  
> >  to = os.path.join(os.environ.get('MESON_INSTALL_DESTDIR_PREFIX'), 
> > args.libdir)
> > @@ -48,6 +49,11 @@ def main():
> >  os.unlink(driver)
> >  print('installing {} to {}'.format(args.megadriver, driver))
> >  os.link(master, driver)
> > +for v in args.so_version:
> > +name = '{}.{}'.format(driver, v)
> > +if os.path.exists(name):
> > +os.unlink(name)
> > +os.symlink(driver, name)
> 
> My understanding is that it should be the other way around: everything
> should point to the versioned file.
> 
> Taking libEGL.so for instance, autotools currently install it that way:
> /usr/lib/libEGL.so   -> libEGL.so.1.0.0
> /usr/lib/libEGL.so.1 -> libEGL.so.1.0.0
> /usr/lib/libEGL.so.1.0.0
> 
> I think this is so that one can hot-swap libs, for instance creating
> .so.1.0.1, then move the symlink to that, and then remove the old
> .so.1.0.0 file. Not sure how much it matters, but for consistency
> I would keep that scheme.
> 
> By the way, the so-version array should only ever contain
> $major.$minor.$patch and $major for the same value of $major, so what
> about simply taking that full version as an input and creating the file
> with it as the name, then symlink the so_version.split('.')[0] file and
> the version-less .so?

I talked with Matt about this yesterday, he was just confused as to why the
media drivers create version so's anyway, we don't do that for other driver
modules (dri, for example). But I haven't been able to dig back through the git
history yet and figure out if it was a mistake to version these in the first
place or not.

The nvidia blob driver installs (for vdpau):
libvdpau_nvidia.so.387.126
libvdpau_nvidia.so.1
libvdpau_nvidia.so

I wonder who the expert on these subsystems is?

Dylan


signature.asc
Description: signature
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 4/6] glx: Lift sending the MakeCurrent request to top-level code

[Ian Romanick]

A couple style nits below.  At least some of this patch will have to
change pending possible changes to patch 3.  Aside from that, I think
this is ok.

On 11/14/2017 12:13 PM, Adam Jackson wrote:
> Somewhat terrifyingly, we never sent this for direct contexts, which
> means the server never knew the context/drawable bindings.
> 
> To handle this sanely, pull the request code up out of the indirect
> backend, and rewrite the context switch path to call it as appropriate.
> This attempts to preserve the existing behavior of not calling unbind()
> on the context if its refcount would not drop to zero, which is why the
> diff is a little uglier than I'd like.
> 
> Signed-off-by: Adam Jackson 
> ---
>  src/glx/glxcurrent.c   | 181 
> +
>  src/glx/indirect_glx.c | 125 --
>  2 files changed, 151 insertions(+), 155 deletions(-)
> 
> diff --git a/src/glx/glxcurrent.c b/src/glx/glxcurrent.c
> index 9f8bf7cee1..7ee8a04a60 100644
> --- a/src/glx/glxcurrent.c
> +++ b/src/glx/glxcurrent.c
> @@ -165,17 +165,85 @@ glXGetCurrentDrawable(void)
> return gc->currentDrawable;
>  }
>  
> -/**
> - * Make a particular context current.
> - *
> - * \note This is in this file so that it can access dummyContext.
> - */
> +static Bool
> +SendMakeCurrentRequest(Display * dpy, GLXContextID gc_id,
> +   GLXContextTag gc_tag, GLXDrawable draw,
> +   GLXDrawable read, GLXContextTag *out_tag)
> +{
> +   xGLXMakeCurrentReply reply;
> +   Bool ret;
> +   int opcode = __glXSetupForCommand(dpy);
> +
> +   LockDisplay(dpy);
> +
> +   if (draw == read) {
> +  xGLXMakeCurrentReq *req;
> +
> +  GetReq(GLXMakeCurrent, req);
> +  req->reqType = opcode;
> +  req->glxCode = X_GLXMakeCurrent;
> +  req->drawable = draw;
> +  req->context = gc_id;
> +  req->oldContextTag = gc_tag;
> +   }
> +   else {
> +  struct glx_display *priv = __glXInitialize(dpy);
> +
> +  if ((priv->majorVersion > 1) || (priv->minorVersion >= 3)) {
> + xGLXMakeContextCurrentReq *req;
> +
> + GetReq(GLXMakeContextCurrent, req);
> + req->reqType = opcode;
> + req->glxCode = X_GLXMakeContextCurrent;
> + req->drawable = draw;
> + req->readdrawable = read;
> + req->context = gc_id;
> + req->oldContextTag = gc_tag;
> +  }
> +  else {
> + xGLXVendorPrivateWithReplyReq *vpreq;
> + xGLXMakeCurrentReadSGIReq *req;
> +
> + GetReqExtra(GLXVendorPrivateWithReply,
> + sz_xGLXMakeCurrentReadSGIReq -
> + sz_xGLXVendorPrivateWithReplyReq, vpreq);
> + req = (xGLXMakeCurrentReadSGIReq *) vpreq;
> + req->reqType = opcode;
> + req->glxCode = X_GLXVendorPrivateWithReply;
> + req->vendorCode = X_GLXvop_MakeCurrentReadSGI;
> + req->drawable = draw;
> + req->readable = read;
> + req->context = gc_id;
> + req->oldContextTag = gc_tag;
> +  }
> +   }
> +
> +   ret = _XReply(dpy, (xReply *) , 0, False);
> +
> +   if (out_tag)
> +  *out_tag = reply.contextTag;
> +
> +   UnlockDisplay(dpy);
> +   SyncHandle();
> +
> +   return ret;
> +}
> +
> +static void
> +SetGC(struct glx_context *gc, Display *dpy, GLXDrawable draw, GLXDrawable 
> read)
> +{
> +   gc->currentDpy = dpy;
> +   gc->currentDrawable = draw;
> +   gc->currentReadable = read;
> +}
> +
>  static Bool
>  MakeContextCurrent(Display * dpy, GLXDrawable draw,
> GLXDrawable read, GLXContext gc_user)
>  {
> struct glx_context *gc = (struct glx_context *) gc_user;
> struct glx_context *oldGC = __glXGetCurrentContext();
> +   Bool ret = GL_FALSE;
>  
> /* Make sure that the new context has a nonzero ID.  In the request,
>  * a zero context ID is used only to mean that we bind to no current
> @@ -186,59 +254,86 @@ MakeContextCurrent(Display * dpy, GLXDrawable draw,
> }
>  
> _glapi_check_multithread();
> -
> __glXLock();
> +
> +   /* Same context and drawables: no op, just return */
> if (oldGC == gc &&
> -   gc->currentDrawable == draw && gc->currentReadable == read) {
> -  __glXUnlock();
> -  return True;
> +   gc->currentDrawable == draw &&
> +   gc->currentReadable == read) {
> +  ret = GL_TRUE;
> }
>  
> -   if (oldGC != ) {
> -  if (--oldGC->thread_refcount == 0) {
> -  oldGC->vtable->unbind(oldGC, gc);
> -  oldGC->currentDpy = 0;
> +   /* Same context and new drawbles: update drawable bindings */
> +   else if (oldGC == gc) {

I'm not a fan of

   if () {
  ...
   }

   /* comment */
   else if () {
  ...
   }

I think the comment should move inside the else and the else should go
back with the }.

> +  if (!SendMakeCurrentRequest(dpy, gc->xid, gc->currentContextTag,
> +  draw, read, >currentContextTag)) {
> + goto out;
>}
> 

Re: [Mesa-dev] [PATCH 5/6] glx: Prepare driFetchDrawable for no-config contexts

[Ian Romanick]

On 11/14/2017 12:13 PM, Adam Jackson wrote:
> When we look up the DRI drawable state we need to associate an fbconfig
> with the drawable. With GLX_EXT_no_config_context we can no longer infer
> that from the context and must instead query the server.
> 
> Signed-off-by: Adam Jackson 
> ---
>  src/glx/dri_common.c  | 22 --
>  src/glx/glx_pbuffer.c |  2 +-
>  src/glx/glxclient.h   |  4 
>  3 files changed, 25 insertions(+), 3 deletions(-)
> 
> diff --git a/src/glx/dri_common.c b/src/glx/dri_common.c
> index 3b82309fa2..0d0b2d997b 100644
> --- a/src/glx/dri_common.c
> +++ b/src/glx/dri_common.c
> @@ -396,12 +396,25 @@ driDestroyConfigs(const __DRIconfig **configs)
> free(configs);
>  }
>  
> +static struct glx_config *
> +driInferDrawableConfig(struct glx_screen *psc, GLXDrawable draw)
> +{
> +   unsigned int fbconfig = 0;
> +
> +   if (GetDrawableAttribute(psc->dpy, draw, GLX_FBCONFIG_ID, )) {
> +  return glx_config_find_fbconfig(psc->configs, fbconfig);
> +   }
> +
> +   return NULL;
> +}
> +
>  _X_HIDDEN __GLXDRIdrawable *
>  driFetchDrawable(struct glx_context *gc, GLXDrawable glxDrawable)
>  {
> struct glx_display *const priv = __glXInitialize(gc->psc->dpy);
> __GLXDRIdrawable *pdraw;
> struct glx_screen *psc;
> +   struct glx_config *config = gc->config;
>  
> if (priv == NULL)
>return NULL;
> @@ -418,8 +431,13 @@ driFetchDrawable(struct glx_context *gc, GLXDrawable 
> glxDrawable)
>return pdraw;
> }
>  
> -   pdraw = psc->driScreen->createDrawable(psc, glxDrawable,
> -  glxDrawable, gc->config);
> +   if (config == NULL)
> +  config = driInferDrawableConfig(gc->psc, glxDrawable);
> +   if (config == NULL)
> +  return NULL;
> +
> +   pdraw = psc->driScreen->createDrawable(psc, glxDrawable, glxDrawable,
> +  config);
>  
> if (pdraw == NULL) {
>ErrorMessageF("failed to create drawable\n");
> diff --git a/src/glx/glx_pbuffer.c b/src/glx/glx_pbuffer.c
> index 933b5d9ecd..42e7996e37 100644
> --- a/src/glx/glx_pbuffer.c
> +++ b/src/glx/glx_pbuffer.c
> @@ -272,7 +272,7 @@ DestroyDRIDrawable(Display *dpy, GLXDrawable drawable, 
> int destroy_xdrawable)
>   * 10.  Given that, this routine should try to use an array on the stack to
>   * capture the reply rather than always calling Xmalloc.
>   */
> -static int
> +int
>  GetDrawableAttribute(Display * dpy, GLXDrawable drawable,

I'm trying to decide whether or not this needs a __glX prefix now.  Yes?

Other than that, this patch is

Reviewed-by: Ian Romanick 

>   int attribute, unsigned int *value)
>  {
> diff --git a/src/glx/glxclient.h b/src/glx/glxclient.h
> index 0d29e5635e..a448c4c000 100644
> --- a/src/glx/glxclient.h
> +++ b/src/glx/glxclient.h
> @@ -841,6 +841,10 @@ indirect_create_context_attribs(struct glx_screen *base,
>  const uint32_t *attribs,
>  unsigned *error);
>  
> +
> +extern int GetDrawableAttribute(Display * dpy, GLXDrawable drawable,
> +int attribute, unsigned int *value);
> +
>  #ifdef __cplusplus
>  }
>  #endif
> 

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH v3 04/15] meson: build r600 driver

[Dylan Baker]

Quoting Marc Dietrich (2017-11-14 01:45:43)
> Hi Dylan,
> 
> Am Dienstag, 14. November 2017, 02:09:08 CET schrieb Dylan Baker:
> > Signed-off-by: Dylan Baker 
> > Tested-by: Aaron Watry 
> > ---
> >  meson.build  |  22 --
> >  src/gallium/drivers/r600/meson.build | 128
> > +++ src/gallium/meson.build  | 
> >  6 +-
> >  src/gallium/targets/dri/meson.build  |   7 +-
> >  4 files changed, 154 insertions(+), 9 deletions(-)
> >  create mode 100644 src/gallium/drivers/r600/meson.build
> > 
> 
> snip
> 
> > diff --git a/src/gallium/drivers/r600/meson.build
> > b/src/gallium/drivers/r600/meson.build new file mode 100644
> > index 000..411b550331d
> > --- /dev/null
> > +++ b/src/gallium/drivers/r600/meson.build
> > @@ -0,0 +1,128 @@
> > +# Copyright © 2017 Intel Corporation
> > +
> > +# Permission is hereby granted, free of charge, to any person obtaining a
> > copy +# of this software and associated documentation files (the
> > "Software"), to deal +# in the Software without restriction, including
> > without limitation the rights +# to use, copy, modify, merge, publish,
> > distribute, sublicense, and/or sell +# copies of the Software, and to
> > permit persons to whom the Software is +# furnished to do so, subject to
> > the following conditions:
> > +
> > +# The above copyright notice and this permission notice shall be included
> > in +# all copies or substantial portions of the Software.
> > +
> > +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
> > OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> > MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
> > IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
> > CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
> > TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE
> > SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE.
> > +
> > +files_r600 = files(
> > +  'r600d_common.h',
> > +  'compute_memory_pool.c',
> > +  'compute_memory_pool.h',
> > +  'eg_asm.c',
> > +  'eg_debug.c',
> > +  'eg_sq.h',
> > +  'evergreen_compute.c',
> > +  'evergreen_compute.h',
> > +  'evergreen_compute_internal.h',
> > +  'evergreend.h',
> > +  'evergreen_hw_context.c',
> > +  'evergreen_state.c',
> > +  'r600_asm.c',
> > +  'r600_asm.h',
> > +  'r600_blit.c',
> > +  'r600d.h',
> > +  'r600_formats.h',
> > +  'r600_hw_context.c',
> > +  'r600_isa.c',
> > +  'r600_isa.h',
> > +  'r600_opcodes.h',
> > +  'r600_pipe.c',
> > +  'r600_pipe.h',
> > +  'r600_public.h',
> > +  'r600_shader.c',
> > +  'r600_shader.h',
> > +  'r600_sq.h',
> > +  'r600_state.c',
> > +  'r600_state_common.c',
> > +  'r600_uvd.c',
> > +  'r700_asm.c',
> > +  'r700_sq.h',
> > +  'cayman_msaa.c',
> > +  'r600_buffer_common.c',
> > +  'r600_cs.h',
> > +  'r600_gpu_load.c',
> > +  'r600_perfcounter.c',
> > +  'r600_pipe_common.c',
> > +  'r600_pipe_common.h',
> > +  'r600_query.c',
> > +  'r600_query.h',
> > +  'r600_streamout.c',
> > +  'r600_test_dma.c',
> > +  'r600_texture.c',
> > +  'r600_viewport.c',
> > +  'radeon_uvd.c',
> > +  'radeon_uvd.h',
> > +  'radeon_vce.c',
> > +  'radeon_vce.h',
> > +  'radeon_video.c',
> > +  'radeon_video.h',
> > +  'sb/sb_bc_builder.cpp',
> > +  'sb/sb_bc_decoder.cpp',
> > +  'sb/sb_bc_dump.cpp',
> > +  'sb/sb_bc_finalize.cpp',
> > +  'sb/sb_bc.h',
> > +  'sb/sb_bc_parser.cpp',
> > +  'sb/sb_context.cpp',
> > +  'sb/sb_core.cpp',
> > +  'sb/sb_dce_cleanup.cpp',
> > +  'sb/sb_def_use.cpp',
> > +  'sb/sb_dump.cpp',
> > +  'sb/sb_expr.cpp',
> > +  'sb/sb_expr.h',
> > +  'sb/sb_gcm.cpp',
> > +  'sb/sb_gvn.cpp',
> > +  'sb/sb_if_conversion.cpp',
> > +  'sb/sb_ir.cpp',
> > +  'sb/sb_ir.h',
> > +  'sb/sb_liveness.cpp',
> > +  'sb/sb_pass.cpp',
> > +  'sb/sb_pass.h',
> > +  'sb/sb_peephole.cpp',
> > +  'sb/sb_psi_ops.cpp',
> > +  'sb/sb_public.h',
> > +  'sb/sb_ra_checker.cpp',
> > +  'sb/sb_ra_coalesce.cpp',
> > +  'sb/sb_ra_init.cpp',
> > +  'sb/sb_sched.cpp',
> > +  'sb/sb_sched.h',
> > +  'sb/sb_shader.cpp',
> > +  'sb/sb_shader.h',
> > +  'sb/sb_ssa_builder.cpp',
> > +  'sb/sb_valtable.cpp',
> > +)
> > +
> > +egd_tables_h = custom_target(
> > +  'egd_tables.h',
> > +  input : ['egd_tables.py', 'evergreend.h'],
> > +  output : 'egd_tables.h',
> > +  command : [prog_python2, '@INPUT@'],
> > +  capture : true,
> > +)
> > +
> > +# TODO: compute defines
> > +
> > +libr600 = static_library(
> > +  'r600',
> > +  [files_r600, egd_tables_h],
> > +  c_args : [c_vis_args],
> > +  cpp_args : [cpp_vis_args],
> > +  include_directories : [
> > +inc_src, inc_include, inc_gallium, inc_gallium_aux, inc_amd_common,
> 
> inc_amd_common is not defined if radeonsi is not enabled.
> 
> Marc

Oops, that's a rebasing error. Fixed locally.


signature.asc
Description: signature
___
mesa-dev mailing list

Re: [Mesa-dev] [PATCH] meson: if dep_dl is an empty list, it's not a dependency object

[Dylan Baker]

Quoting Jon Turney (2017-11-14 04:05:21)
> On 13/11/2017 17:41, Dylan Baker wrote:
> > I thought I'd fixed this already,
> > Reviewed-by: Dylan Baker 
> 
> This workaround is already in place for dep_xxf86vm.
> 
> I took a brief look, and didn't see anywhere the same problem could 
> occur with any of the other uses of [] for a dependency.
> 
> > Quoting Jon Turney (2017-11-13 02:28:27)
> >> It's ok to use an empty list for dependencies:, but it's not ok to try to
> >> use the found() method of it.

Ah that makes sense. Once we bump our minimum version so that the empty
dependency() doesn't generate console noise (I think you did that work?) I'd
like to switch to that.

You have commit access, correct?

Dylan


signature.asc
Description: signature
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [Bug 103658] addrlib/gfx9/gfx9addrlib.cpp:727:50: error: expected expression

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=103658

Vinson Lee  changed:

   What|Removed |Added

   Keywords||bisected

--- Comment #2 from Vinson Lee  ---
commit 7f33e94e43a647d71a9f930cf3180e5abb529edd
Author: Marek Olšák 
Date:   Tue Nov 7 00:56:13 2017 +0100

amd/addrlib: update to latest version

This uses C++11 initializer lists.

I just overwrote all Mesa files with internal addrlib and discarded
hunks that we should probably keep, but I might have missed something.

The code depending on ADDR_AM_BUILD is removed. We can add it back next
time if needed.

Acked-by: Nicolai Hähnle 

:04 04 c055da298572eb64e857a1907496ccf7e92c2920
06079de7e3cf90c76f245612b96c12e6a369a42d M  src
bisect run success

-- 
You are receiving this mail because:
You are the QA Contact for the bug.
You are the assignee for the bug.___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 11/14] intel/blorp: Add a helper for filling out VERTEX_BUFFER_STATE

[Jason Ekstrand]

On Tue, Nov 14, 2017 at 10:05 AM, Lionel Landwerlin <
lionel.g.landwer...@intel.com> wrote:

> On 13/11/17 16:12, Jason Ekstrand wrote:
>
>> There are enough #ifs in there that it's kind-of pointless to duplicate
>> it for each buffer.
>> ---
>>   src/intel/blorp/blorp_genX_exec.h | 69 +++---
>> -
>>   1 file changed, 33 insertions(+), 36 deletions(-)
>>
>> diff --git a/src/intel/blorp/blorp_genX_exec.h
>> b/src/intel/blorp/blorp_genX_exec.h
>> index 4f88650..7548392 100644
>> --- a/src/intel/blorp/blorp_genX_exec.h
>> +++ b/src/intel/blorp/blorp_genX_exec.h
>> @@ -263,53 +263,50 @@ blorp_emit_input_varying_data(struct blorp_batch
>> *batch,
>>   }
>> static void
>> -blorp_emit_vertex_buffers(struct blorp_batch *batch,
>> -  const struct blorp_params *params)
>> +blorp_fill_vertex_buffer_state(struct blorp_batch *batch,
>> +   struct GENX(VERTEX_BUFFER_STATE) *vb,
>> +   unsigned idx,
>> +   struct blorp_address addr, uint32_t size,
>> +   uint32_t stride)
>>   {
>> -   struct GENX(VERTEX_BUFFER_STATE) vb[2];
>> -   memset(vb, 0, sizeof(vb));
>> +   vb[idx].VertexBufferIndex = idx;
>> +   vb[idx].BufferStartingAddress = addr;
>> +   vb[idx].BufferPitch = stride;
>>   -   uint32_t size;
>> -   blorp_emit_vertex_data(batch, params, [0].BufferStartingAddress,
>> );
>> -   vb[0].VertexBufferIndex = 0;
>> -   vb[0].BufferPitch = 3 * sizeof(float);
>>   #if GEN_GEN >= 6
>> -   vb[0].VertexBufferMOCS = batch->blorp->mocs.vb;
>> -#endif
>> -#if GEN_GEN >= 7
>> -   vb[0].AddressModifyEnable = true;
>> -#endif
>> -#if GEN_GEN >= 8
>> -   vb[0].BufferSize = size;
>> -#elif GEN_GEN >= 5
>> -   vb[0].BufferAccessType = VERTEXDATA;
>> -   vb[0].EndAddress = vb[0].BufferStartingAddress;
>> -   vb[0].EndAddress.offset += size - 1;
>> -#elif GEN_GEN == 4
>> -   vb[0].BufferAccessType = VERTEXDATA;
>> -   vb[0].MaxIndex = 2;
>> +   vb[idx].VertexBufferMOCS = batch->blorp->mocs.vb;
>>   #endif
>>   -   blorp_emit_input_varying_data(batch, params,
>> - [1].BufferStartingAddress, );
>> -   vb[1].VertexBufferIndex = 1;
>> -   vb[1].BufferPitch = 0;
>> -#if GEN_GEN >= 6
>> -   vb[1].VertexBufferMOCS = batch->blorp->mocs.vb;
>> -#endif
>>   #if GEN_GEN >= 7
>> -   vb[1].AddressModifyEnable = true;
>> +   vb[idx].AddressModifyEnable = true;
>>   #endif
>> +
>>   #if GEN_GEN >= 8
>> -   vb[1].BufferSize = size;
>> +   vb[idx].BufferSize = size;
>>   #elif GEN_GEN >= 5
>> -   vb[1].BufferAccessType = INSTANCEDATA;
>> -   vb[1].EndAddress = vb[1].BufferStartingAddress;
>> -   vb[1].EndAddress.offset += size - 1;
>> +   vb[idx].BufferAccessType = stride > 0 ? VERTEXDATA : INSTANCEDATA;
>> +   vb[idx].EndAddress = vb[idx].BufferStartingAddress;
>> +   vb[idx].EndAddress.offset += size - 1;
>>   #elif GEN_GEN == 4
>> -   vb[1].BufferAccessType = INSTANCEDATA;
>> -   vb[1].MaxIndex = 0;
>> +   vb[idx].BufferAccessType = stride > 0 ? VERTEXDATA : INSTANCEDATA;
>> +   vb[idx].MaxIndex = 2;
>>
>
> This MaxIndex used to be 0 for vb[1], now it's always 2 on gen4.
> I can't really tell whether that's going to have an unintended effect :(
>

That exists for gen4's really awkward method of bounds checking.  It may be
better to just set this to "stride > 0 ? size / stride : 0".  I'll do that
and see if it works.  Also, I don't think it really maters so long as it's
large enough since blorp is never going to go OOB.


>   #endif
>> +}
>> +
>> +static void
>> +blorp_emit_vertex_buffers(struct blorp_batch *batch,
>> +  const struct blorp_params *params)
>> +{
>> +   struct GENX(VERTEX_BUFFER_STATE) vb[2];
>> +   memset(vb, 0, sizeof(vb));
>> +
>> +   struct blorp_address addr;
>> +   uint32_t size;
>> +   blorp_emit_vertex_data(batch, params, , );
>> +   blorp_fill_vertex_buffer_state(batch, vb, 0, addr, size, 3 *
>> sizeof(float));
>> +
>> +   blorp_emit_input_varying_data(batch, params, , );
>> +   blorp_fill_vertex_buffer_state(batch, vb, 1, addr, size, 0);
>>const unsigned num_dwords = 1 + GENX(VERTEX_BUFFER_STATE_length)
>> * 2;
>>  uint32_t *dw = blorp_emitn(batch, GENX(3DSTATE_VERTEX_BUFFERS),
>> num_dwords);
>>
>
>
>
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 07/14] intel/blorp: Take a range of layers in blorp_ccs_resolve

[Jason Ekstrand]

On Tue, Nov 14, 2017 at 9:34 AM, Lionel Landwerlin <
lionel.g.landwer...@intel.com> wrote:

> On 13/11/17 16:12, Jason Ekstrand wrote:
>
>> ---
>>   src/intel/blorp/blorp.h   | 3 ++-
>>   src/intel/blorp/blorp_clear.c | 7 +--
>>   src/mesa/drivers/dri/i965/brw_blorp.c | 2 +-
>>   3 files changed, 8 insertions(+), 4 deletions(-)
>>
>> diff --git a/src/intel/blorp/blorp.h b/src/intel/blorp/blorp.h
>> index c3077aa..690e65f 100644
>> --- a/src/intel/blorp/blorp.h
>> +++ b/src/intel/blorp/blorp.h
>> @@ -202,7 +202,8 @@ enum blorp_fast_clear_op {
>> void
>>   blorp_ccs_resolve(struct blorp_batch *batch,
>> -  struct blorp_surf *surf, uint32_t level, uint32_t
>> layer,
>> +  struct blorp_surf *surf, uint32_t level,
>> +  uint32_t start_layer, uint32_t num_layers,
>> enum isl_format format,
>> enum blorp_fast_clear_op resolve_op);
>>   diff --git a/src/intel/blorp/blorp_clear.c
>> b/src/intel/blorp/blorp_clear.c
>> index 8d758df..56cc3dd 100644
>> --- a/src/intel/blorp/blorp_clear.c
>> +++ b/src/intel/blorp/blorp_clear.c
>> @@ -778,13 +778,16 @@ prepare_ccs_resolve(struct blorp_batch * const
>> batch,
>> void
>>   blorp_ccs_resolve(struct blorp_batch *batch,
>> -  struct blorp_surf *surf, uint32_t level, uint32_t
>> layer,
>> +  struct blorp_surf *surf, uint32_t level,
>> +  uint32_t start_layer, uint32_t num_layers,
>> enum isl_format format,
>> enum blorp_fast_clear_op resolve_op)
>>   {
>>  struct blorp_params params;
>>   -   prepare_ccs_resolve(batch, , surf, level, layer, format,
>> resolve_op);
>> +   prepare_ccs_resolve(batch, , surf, level, start_layer,
>> +   format, resolve_op);
>> +   params.num_layers = num_layers;
>>
>
> Ohoh... Was num_layers uninitialized before this patch?
>

No, prepare_ccs_resolve calls blorp_params_init() which sets it to 1.


> Otherwise looks good :
>
> Reviewed-by: Lionel Landwerlin 


Thanks!

   batch->blorp->exec(batch, );
>   }
> diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
> b/src/mesa/drivers/dri/i965/brw_blorp.c
> index eae8aaa..0736583 100644
> --- a/src/mesa/drivers/dri/i965/brw_blorp.c
> +++ b/src/mesa/drivers/dri/i965/brw_blorp.c
> @@ -1486,7 +1486,7 @@ brw_blorp_resolve_color(struct brw_context *brw,
> struct intel_mipmap_tree *mt,
>struct blorp_batch batch;
>  blorp_batch_init(>blorp, , brw, 0);
> -   blorp_ccs_resolve(, , level, layer,
> +   blorp_ccs_resolve(, , level, layer, 1,
>brw_blorp_to_isl_format(brw, format, true),
>resolve_op);
>  blorp_batch_finish();
>
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 3/6] glx: Move vertex array protocol state into the indirect backend

[Adam Jackson]

On Tue, 2017-11-14 at 13:15 -0800, Ian Romanick wrote:
> On 11/14/2017 12:13 PM, Adam Jackson wrote:
> > diff --git a/src/glx/indirect_glx.c b/src/glx/indirect_glx.c
> > index cfae12f6c0..b552b5768a 100644
> > --- a/src/glx/indirect_glx.c
> > +++ b/src/glx/indirect_glx.c
> > @@ -148,9 +148,21 @@ indirect_bind_context(struct glx_context *gc, struct 
> > glx_context *old,
> > sent = SendMakeCurrentRequest(dpy, gc->xid, tag, draw, read,
> >  >currentContextTag);
> >  
> > -   if (!IndirectAPI)
> > -  IndirectAPI = __glXNewIndirectAPI();
> > -   _glapi_set_dispatch(IndirectAPI);
> > +   if (sent) {
> > +  if (!IndirectAPI)
> > + IndirectAPI = __glXNewIndirectAPI();
> > +  _glapi_set_dispatch(IndirectAPI);
> > +
> > +  /* The indirect vertex array state must to be initialised after we
> > +   * have setup the context, as it needs to query server attributes.
> > +   */
> > +  __GLXattribute *state = gc->client_state_private;
> > +  if (state && state->array_state == NULL) {
> > + glGetString(GL_EXTENSIONS);
> > + glGetString(GL_VERSION);
> > + __glXInitVertexArrayState(gc);
> > +  }
> > +   }
> 
> This is where this code used to be, but commit d57c85c1 moved it.  Does
> this not re-regress things?  I guess wrapping it in 'if (sent)' seems
> like it ought to be enough to prevent the original problem.

Eep, good catch. I think this would indeed re-regress things. We're
calling ::bind before __glXSetCurrentContext - in fact with the dummy
context bound - which means those glGetStrings would probably fizzle.

I'll dig into this a bit further, hopefully a real piglit run will
shake out this and anything else remaining.

- ajax
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 01/18] radeon/vcn: add vcn encode interface

[Zhang, Boyuan]

If there is no objection, the patches will be pushed by the end of the week.

Thanks,
Boyuan

-Original Message-
From: Zhang, Boyuan 
Sent: November-08-17 1:08 PM
To: mesa-dev@lists.freedesktop.org
Cc: alexdeuc...@gmail.com; dy...@pnwbakers.com; mar...@gmail.com; 
ckoenig.leichtzumer...@gmail.com; Zhang, Boyuan
Subject: [PATCH 01/18] radeon/vcn: add vcn encode interface

From: Boyuan Zhang 

Add a new header file for vcn encode interface

Signed-off-by: Boyuan Zhang 
---
 src/gallium/drivers/radeon/radeon_vcn_enc.h | 325 
 1 file changed, 325 insertions(+)
 create mode 100644 src/gallium/drivers/radeon/radeon_vcn_enc.h

diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc.h 
b/src/gallium/drivers/radeon/radeon_vcn_enc.h
new file mode 100644
index 000..f9fa168
--- /dev/null
+++ b/src/gallium/drivers/radeon/radeon_vcn_enc.h
@@ -0,0 +1,325 @@
+/**
+
+ *
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person 
+obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject 
+to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial 
+portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 
+EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF 
+CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ 
+***
+***/
+
+#ifndef _RADEON_VCN_ENC_H
+#define _RADEON_VCN_ENC_H
+
+#define RENCODE_FW_INTERFACE_MAJOR_VERSION 1
+#define RENCODE_FW_INTERFACE_MINOR_VERSION 2
+
+#define RENCODE_IB_PARAM_SESSION_INFO  0x0001
+#define RENCODE_IB_PARAM_TASK_INFO 0x0002
+#define RENCODE_IB_PARAM_SESSION_INIT  0x0003
+#define RENCODE_IB_PARAM_LAYER_CONTROL 0x0004
+#define RENCODE_IB_PARAM_LAYER_SELECT  0x0005
+#define RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT 0x0006
+#define RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT   0x0007
+#define RENCODE_IB_PARAM_RATE_CONTROL_PER_PICTURE  0x0008
+#define RENCODE_IB_PARAM_QUALITY_PARAMS0x0009
+#define RENCODE_IB_PARAM_SLICE_HEADER  0x000a
+#define RENCODE_IB_PARAM_ENCODE_PARAMS 0x000b
+#define RENCODE_IB_PARAM_INTRA_REFRESH 0x000c
+#define RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER 0x000d
+#define RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER0x000e
+#define RENCODE_IB_PARAM_FEEDBACK_BUFFER   0x0010
+#define RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU0x0020
+
+#define RENCODE_H264_IB_PARAM_SLICE_CONTROL0x0021
+#define RENCODE_H264_IB_PARAM_SPEC_MISC0x0022
+#define RENCODE_H264_IB_PARAM_ENCODE_PARAMS0x0023
+#define RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER0x0024
+
+#define RENCODE_IB_OP_INITIALIZE   0x0101
+#define RENCODE_IB_OP_CLOSE_SESSION0x0102
+#define RENCODE_IB_OP_ENCODE   0x0103
+#define RENCODE_IB_OP_INIT_RC  0x0104
+#define RENCODE_IB_OP_INIT_RC_VBV_BUFFER_LEVEL 0x0105
+#define RENCODE_IB_OP_SET_SPEED_ENCODING_MODE  0x0106
+#define RENCODE_IB_OP_SET_BALANCE_ENCODING_MODE0x0107
+#define RENCODE_IB_OP_SET_QUALITY_ENCODING_MODE0x0108
+
+#define RENCODE_IF_MAJOR_VERSION_MASK  0x
+#define RENCODE_IF_MAJOR_VERSION_SHIFT 16
+#define RENCODE_IF_MINOR_VERSION_MASK  0x
+#define RENCODE_IF_MINOR_VERSION_SHIFT 0
+
+#define RENCODE_ENCODE_STANDARD_H264   1
+
+#define 

Re: [Mesa-dev] [PATCH 3/6] glx: Move vertex array protocol state into the indirect backend

[Ian Romanick]

On 11/14/2017 12:13 PM, Adam Jackson wrote:
> Only relevant for indirect contexts, so let's get that code out of the
> common path.
> 
> Signed-off-by: Adam Jackson 
> ---
>  src/glx/glxcurrent.c   | 12 
>  src/glx/indirect_glx.c | 18 +++---
>  2 files changed, 15 insertions(+), 15 deletions(-)
> 
> diff --git a/src/glx/glxcurrent.c b/src/glx/glxcurrent.c
> index fd04929b89..9f8bf7cee1 100644
> --- a/src/glx/glxcurrent.c
> +++ b/src/glx/glxcurrent.c
> @@ -238,18 +238,6 @@ MakeContextCurrent(Display * dpy, GLXDrawable draw,
>  
> __glXUnlock();
>  
> -   /* The indirect vertex array state must to be initialised after we
> -* have setup the context, as it needs to query server attributes.
> -*/
> -   if (gc && !gc->isDirect) {
> -  __GLXattribute *state = gc->client_state_private;
> -  if (state && state->array_state == NULL) {
> - glGetString(GL_EXTENSIONS);
> - glGetString(GL_VERSION);
> - __glXInitVertexArrayState(gc);
> -  }
> -   }
> -
> return GL_TRUE;
>  }
>  
> diff --git a/src/glx/indirect_glx.c b/src/glx/indirect_glx.c
> index cfae12f6c0..b552b5768a 100644
> --- a/src/glx/indirect_glx.c
> +++ b/src/glx/indirect_glx.c
> @@ -148,9 +148,21 @@ indirect_bind_context(struct glx_context *gc, struct 
> glx_context *old,
> sent = SendMakeCurrentRequest(dpy, gc->xid, tag, draw, read,
>>currentContextTag);
>  
> -   if (!IndirectAPI)
> -  IndirectAPI = __glXNewIndirectAPI();
> -   _glapi_set_dispatch(IndirectAPI);
> +   if (sent) {
> +  if (!IndirectAPI)
> + IndirectAPI = __glXNewIndirectAPI();
> +  _glapi_set_dispatch(IndirectAPI);
> +
> +  /* The indirect vertex array state must to be initialised after we
> +   * have setup the context, as it needs to query server attributes.
> +   */
> +  __GLXattribute *state = gc->client_state_private;
> +  if (state && state->array_state == NULL) {
> + glGetString(GL_EXTENSIONS);
> + glGetString(GL_VERSION);
> + __glXInitVertexArrayState(gc);
> +  }
> +   }

This is where this code used to be, but commit d57c85c1 moved it.  Does
this not re-regress things?  I guess wrapping it in 'if (sent)' seems
like it ought to be enough to prevent the original problem.

>  
> return !sent;
>  }
> 

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 2/6] glx: Use __glXSendError instead of open-coding it

[Ian Romanick]

This patch is

Reviewed-by: Ian Romanick 

On 11/14/2017 12:13 PM, Adam Jackson wrote:
> This also fixes a bug, the error path through MakeCurrent didn't
> translate the error code by the extension's error base.
> 
> Signed-off-by: Adam Jackson 
> ---
>  src/glx/glxcmds.c| 10 +-
>  src/glx/glxcurrent.c | 20 +++-
>  2 files changed, 4 insertions(+), 26 deletions(-)
> 
> diff --git a/src/glx/glxcmds.c b/src/glx/glxcmds.c
> index bc93d62510..eee45d962d 100644
> --- a/src/glx/glxcmds.c
> +++ b/src/glx/glxcmds.c
> @@ -392,15 +392,7 @@ glXCreateContext(Display * dpy, XVisualInfo * vis,
>config = glx_config_find_visual(psc->visuals, vis->visualid);
>  
> if (config == NULL) {
> -  xError error;
> -
> -  error.errorCode = BadValue;
> -  error.resourceID = vis->visualid;
> -  error.sequenceNumber = dpy->request;
> -  error.type = X_Error;
> -  error.majorCode = __glXSetupForCommand(dpy);
> -  error.minorCode = X_GLXCreateContext;
> -  _XError(dpy, );
> +  __glXSendError(dpy, BadValue, vis->visualid, X_GLXCreateContext, True);
>return None;
> }
>  
> diff --git a/src/glx/glxcurrent.c b/src/glx/glxcurrent.c
> index d1193265f9..fd04929b89 100644
> --- a/src/glx/glxcurrent.c
> +++ b/src/glx/glxcurrent.c
> @@ -36,8 +36,8 @@
>  #include 
>  
>  #include "glxclient.h"
> -
>  #include "glapi.h"
> +#include "glx_error.h"
>  
>  /*
>  ** We setup some dummy structures here so that the API can be used
> @@ -165,21 +165,6 @@ glXGetCurrentDrawable(void)
> return gc->currentDrawable;
>  }
>  
> -static void
> -__glXGenerateError(Display * dpy, XID resource,
> -   BYTE errorCode, CARD16 minorCode)
> -{
> -   xError error;
> -
> -   error.errorCode = errorCode;
> -   error.resourceID = resource;
> -   error.sequenceNumber = dpy->request;
> -   error.type = X_Error;
> -   error.majorCode = __glXSetupForCommand(dpy);
> -   error.minorCode = minorCode;
> -   _XError(dpy, );
> -}
> -
>  /**
>   * Make a particular context current.
>   *
> @@ -228,7 +213,8 @@ MakeContextCurrent(Display * dpy, GLXDrawable draw,
>if (gc->vtable->bind(gc, oldGC, draw, read) != Success) {
>   __glXSetCurrentContextNull();
>   __glXUnlock();
> - __glXGenerateError(dpy, None, GLXBadContext, 
> X_GLXMakeContextCurrent);
> + __glXSendError(dpy, GLXBadContext, None, X_GLXMakeContextCurrent,
> +False);
>   return GL_FALSE;
>}
>  
> 

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 10/18] radeon/vcn: add encode header implementations

[Andy Furniss]

Zhang, Boyuan wrote:

Zhang, Boyuan wrote:


On 14/11/17 10:53, Andy Furniss wrote:

Zhang, Boyuan wrote:



-Original Message-
From: Zhang, Boyuan
Sent: November-13-17 11:41 AM
To: Andy Furniss; Koenig, Christian; Mark Thompson;
mesa-dev@lists.freedesktop.org
Subject: RE: [Mesa-dev] [PATCH 10/18] radeon/vcn: add encode header
implementations

Zhang, Boyuan wrote:


diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
index 5170c67..c6dc420 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
@@ -362,6 +362,233 @@ static void radeon_enc_quality_params(struct 
radeon_encoder *enc)
  RADEON_ENC_END();
  }
  +static void radeon_enc_nalu_sps(struct radeon_encoder
*enc) {
+RADEON_ENC_BEGIN(RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU);
+RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_SPS);
+uint32_t *size_in_bytes = >cs->current.buf[enc->cs->current.cdw++];
+radeon_enc_reset(enc);
+radeon_enc_set_emulation_prevention(enc, false);
+radeon_enc_code_fixed_bits(enc, 0x0001, 32);
+radeon_enc_code_fixed_bits(enc, 0x67, 8);
+radeon_enc_byte_align(enc);
+radeon_enc_set_emulation_prevention(enc, true);
+radeon_enc_code_fixed_bits(enc, enc->enc_pic.spec_misc.profile_idc, 8);
+radeon_enc_code_fixed_bits(enc, 0x04, 8);

Please always set constraint_set1_flag when profile_idc is 66.  There are 
enough actually-constrained-baseline-but-not-marked-as-such streams in the 
world already to catch out decoders without full baseline support (that is, all 
of them).

Also, "constraint_set5_flag shall be equal to 0 when profile_idc is not equal to 77, 
88, 100, or 118".



[Boyuan] Thanks for pointing out. I modified the value to be 0x44 in the new 
patch (set1=1, and set5=1) since we only support constrained baseline for now.


It's not really with cabac though. I know there was a patch to turn it off - but 
that would have been wasteful and make linux < windows.

Why not use 77 if cabac is on + not set constrained bits, windows seems to set 
main.

Currently with vce trying to set main manually from ffmeg/gst in order to get something 
"correct" still sets flags = something that's not seen as main (but works).


Yes, but still the problem is cabac is not allowed for baseline profile and we 
only support baseline for now. I'm not quite sure about windows test you 
mentioned, I'm just guessing that we might have some main profile features 
support in some closed test environment on windows side, but definitely not all 
main profile features, no b frame support.
On linux side, we only support baseline profile for this vcn enc.
(fixed a typo)


   Yea, it's tricky, FWIW windows does not use b-frames for the test I've done 
(re-live turned up high = 50mbit 60fps).


I can get B-frames from AMF with a GCN 2 card on Windows.


Yes, we used to support b-frame for GCN2 (e.g. like Bonaire, Kabini, etc...) 
cards. But for later Asics, we dropped the b-frame support. Including this 
raven vcn encode, b-frame is still not supported according to our firmware team.
- Boyuan




It is flagged as main and uses cabac.
I guess main is the "correct" way to describe constrained baseline + cabac even 
if there are no other main features like b-frames.


Yes, I agree, that's the correct way in that case. However, we can't advertise 
main profile since we don't have b-frame support. It would cause serious 
problem if player tries to use b-frame when seeing that main profile is 
supported.


I guess you mean encoder rather than player - I don't think a player should 
care if there are no b-frames in main.

FWIW vainfo does currently advertise main/high support, IIRC it was mentioned 
in the past but lost in a long thread with many other issues in it.


I remember there was a discussion before about this, I will double check it and 
will probably make a patch to disable them if not yet disabled.



  So as explained before, we only support constrained baseline profile for this 
raven vcn encode now. And as a result, cabac is forced to be off in this 
bring-up patch.

Maybe advertise constrained baseline as encode + expose cabac switch that's in 
the vaapi spec and let the user/app decide to force that.

If cabac is on then flag the output as main.

Thanks for this idea, I could raise this in our meeting to discuss the possibility of doing this. Currently, 
"advertising constrained baseline only"  + "enabling cabac" at the same time doesn't sound like a 
"correct"/"perfect" way to me, I need more discussions with my team about this. Therefore, I will 
push the current patches, e.g. keep cabac disabled for now, to bring up this vcn encode if you are OK with it.
- Boyuan


Yea, fine, I am just discussing rather than trying to block - I don't 
even have a vcn card.



___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org

Re: [Mesa-dev] [PATCH v5 00/10] new series of Mesa for Tizen

[Mun, Gwan-gyeong]

Hi all,

I am sorry that I didn't have enough discussion about why new window
system code is needed for Tizen on mesa.

This is a brief architecture of Tizen Window System.

  
+--+
  | [Tizen Window System Architecture]
  |
  |
  |
  |
  |
  |
  |
  |  +---+
++  ++  |
  |  | Enlightenment Display |   |
   |  |   3D UI|  |
  |  |  Server for Tizen +-->|
EvasGL   |  |   Toolkit  |  |
  |  |   |   |
   |  ||  |
  |  |   |
+-+--+  +-+--+  |
  |  +--+-+--+
|   | |
  | | |
v   | |
  | | |
++| |
  | | |  | GPU
Vendor || |
  | | |  |
GL/EGL|<---+ |
  | | |  |
Driver|  |
  | | |
+-+--+  |
  | | |
| |
  | v v
v |
  |   +---++--+
++  |
  |   | TDM   ||TBM   |  |
   |  |
  |   |(Tizen Display Manager)+--->|(Tizen Buffer Manager)|<-|
TPL-EGL  |  |
  |   |   ||  |  |
   |  |
  |   +---++--+
++  |
  |
  |
  
+--+



< display server / wayland-egl client >

+-+
+---+
| |   |
   |
|  +---+  |   |
+---+   |
|  | Enlightenment Display +---+  |
|  wayland-egl client   |   |
|  |  Server for Tizen |  ||  |
+--+-+--+   |
|  +--++  ||  |
  | |  |
| |   ||  |
  | |  |
| v   ||  |
  | |  |
|  +---+  ||  |
  | |  |
|  | EVAS GL TBM   |  ||  |
  | |  |
|  ++-++  ||  |
  | |  |
|   | |   ||  |
  | |  |
|   | v   ||  |
  v v  |
|   |+-+  ||+--+  |
+-+   +-+   |
|   ||   EGL   +---|--->|  GPU Vendor
|<-+ EGL |   | wayland-egl |   |
|   |+++  |||  GL Driver   |  |
+--+--+   +---+-+   |
|   | |   ||+--+  |
  |  |  ^  |
|   v v   ||  |
  v  v  |  |
|  +-+   +-+  ||+--+  |
++--+   |
|  |   TBM   |<--+ TPL-EGL +---|--->| wayland-tbm
|<-+TPL-EGL|   |
|  +-+   +-+  ||+--+  |
+---+   |
| ||^ |
   |
| ||| |
   |
+-+++
+---+


* TBM:
   - Tizen Buffer Manager (TBM) provides the abstraction interface for
the graphic buffer manager
 in Tizen. [1]

   - Why does it needed?
 Because different vendors provides different user-level interface
for the memory manager,
  

[Mesa-dev] [PATCH 2/6] glx: Use __glXSendError instead of open-coding it

[Adam Jackson]

This also fixes a bug, the error path through MakeCurrent didn't
translate the error code by the extension's error base.

Signed-off-by: Adam Jackson 
---
 src/glx/glxcmds.c| 10 +-
 src/glx/glxcurrent.c | 20 +++-
 2 files changed, 4 insertions(+), 26 deletions(-)

diff --git a/src/glx/glxcmds.c b/src/glx/glxcmds.c
index bc93d62510..eee45d962d 100644
--- a/src/glx/glxcmds.c
+++ b/src/glx/glxcmds.c
@@ -392,15 +392,7 @@ glXCreateContext(Display * dpy, XVisualInfo * vis,
   config = glx_config_find_visual(psc->visuals, vis->visualid);
 
if (config == NULL) {
-  xError error;
-
-  error.errorCode = BadValue;
-  error.resourceID = vis->visualid;
-  error.sequenceNumber = dpy->request;
-  error.type = X_Error;
-  error.majorCode = __glXSetupForCommand(dpy);
-  error.minorCode = X_GLXCreateContext;
-  _XError(dpy, );
+  __glXSendError(dpy, BadValue, vis->visualid, X_GLXCreateContext, True);
   return None;
}
 
diff --git a/src/glx/glxcurrent.c b/src/glx/glxcurrent.c
index d1193265f9..fd04929b89 100644
--- a/src/glx/glxcurrent.c
+++ b/src/glx/glxcurrent.c
@@ -36,8 +36,8 @@
 #include 
 
 #include "glxclient.h"
-
 #include "glapi.h"
+#include "glx_error.h"
 
 /*
 ** We setup some dummy structures here so that the API can be used
@@ -165,21 +165,6 @@ glXGetCurrentDrawable(void)
return gc->currentDrawable;
 }
 
-static void
-__glXGenerateError(Display * dpy, XID resource,
-   BYTE errorCode, CARD16 minorCode)
-{
-   xError error;
-
-   error.errorCode = errorCode;
-   error.resourceID = resource;
-   error.sequenceNumber = dpy->request;
-   error.type = X_Error;
-   error.majorCode = __glXSetupForCommand(dpy);
-   error.minorCode = minorCode;
-   _XError(dpy, );
-}
-
 /**
  * Make a particular context current.
  *
@@ -228,7 +213,8 @@ MakeContextCurrent(Display * dpy, GLXDrawable draw,
   if (gc->vtable->bind(gc, oldGC, draw, read) != Success) {
  __glXSetCurrentContextNull();
  __glXUnlock();
- __glXGenerateError(dpy, None, GLXBadContext, X_GLXMakeContextCurrent);
+ __glXSendError(dpy, GLXBadContext, None, X_GLXMakeContextCurrent,
+False);
  return GL_FALSE;
   }
 
-- 
2.14.3

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 5/6] glx: Prepare driFetchDrawable for no-config contexts

[Adam Jackson]

When we look up the DRI drawable state we need to associate an fbconfig
with the drawable. With GLX_EXT_no_config_context we can no longer infer
that from the context and must instead query the server.

Signed-off-by: Adam Jackson 
---
 src/glx/dri_common.c  | 22 --
 src/glx/glx_pbuffer.c |  2 +-
 src/glx/glxclient.h   |  4 
 3 files changed, 25 insertions(+), 3 deletions(-)

diff --git a/src/glx/dri_common.c b/src/glx/dri_common.c
index 3b82309fa2..0d0b2d997b 100644
--- a/src/glx/dri_common.c
+++ b/src/glx/dri_common.c
@@ -396,12 +396,25 @@ driDestroyConfigs(const __DRIconfig **configs)
free(configs);
 }
 
+static struct glx_config *
+driInferDrawableConfig(struct glx_screen *psc, GLXDrawable draw)
+{
+   unsigned int fbconfig = 0;
+
+   if (GetDrawableAttribute(psc->dpy, draw, GLX_FBCONFIG_ID, )) {
+  return glx_config_find_fbconfig(psc->configs, fbconfig);
+   }
+
+   return NULL;
+}
+
 _X_HIDDEN __GLXDRIdrawable *
 driFetchDrawable(struct glx_context *gc, GLXDrawable glxDrawable)
 {
struct glx_display *const priv = __glXInitialize(gc->psc->dpy);
__GLXDRIdrawable *pdraw;
struct glx_screen *psc;
+   struct glx_config *config = gc->config;
 
if (priv == NULL)
   return NULL;
@@ -418,8 +431,13 @@ driFetchDrawable(struct glx_context *gc, GLXDrawable 
glxDrawable)
   return pdraw;
}
 
-   pdraw = psc->driScreen->createDrawable(psc, glxDrawable,
-  glxDrawable, gc->config);
+   if (config == NULL)
+  config = driInferDrawableConfig(gc->psc, glxDrawable);
+   if (config == NULL)
+  return NULL;
+
+   pdraw = psc->driScreen->createDrawable(psc, glxDrawable, glxDrawable,
+  config);
 
if (pdraw == NULL) {
   ErrorMessageF("failed to create drawable\n");
diff --git a/src/glx/glx_pbuffer.c b/src/glx/glx_pbuffer.c
index 933b5d9ecd..42e7996e37 100644
--- a/src/glx/glx_pbuffer.c
+++ b/src/glx/glx_pbuffer.c
@@ -272,7 +272,7 @@ DestroyDRIDrawable(Display *dpy, GLXDrawable drawable, int 
destroy_xdrawable)
  * 10.  Given that, this routine should try to use an array on the stack to
  * capture the reply rather than always calling Xmalloc.
  */
-static int
+int
 GetDrawableAttribute(Display * dpy, GLXDrawable drawable,
  int attribute, unsigned int *value)
 {
diff --git a/src/glx/glxclient.h b/src/glx/glxclient.h
index 0d29e5635e..a448c4c000 100644
--- a/src/glx/glxclient.h
+++ b/src/glx/glxclient.h
@@ -841,6 +841,10 @@ indirect_create_context_attribs(struct glx_screen *base,
 const uint32_t *attribs,
 unsigned *error);
 
+
+extern int GetDrawableAttribute(Display * dpy, GLXDrawable drawable,
+int attribute, unsigned int *value);
+
 #ifdef __cplusplus
 }
 #endif
-- 
2.14.3

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 3/6] glx: Move vertex array protocol state into the indirect backend

[Adam Jackson]

Only relevant for indirect contexts, so let's get that code out of the
common path.

Signed-off-by: Adam Jackson 
---
 src/glx/glxcurrent.c   | 12 
 src/glx/indirect_glx.c | 18 +++---
 2 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/src/glx/glxcurrent.c b/src/glx/glxcurrent.c
index fd04929b89..9f8bf7cee1 100644
--- a/src/glx/glxcurrent.c
+++ b/src/glx/glxcurrent.c
@@ -238,18 +238,6 @@ MakeContextCurrent(Display * dpy, GLXDrawable draw,
 
__glXUnlock();
 
-   /* The indirect vertex array state must to be initialised after we
-* have setup the context, as it needs to query server attributes.
-*/
-   if (gc && !gc->isDirect) {
-  __GLXattribute *state = gc->client_state_private;
-  if (state && state->array_state == NULL) {
- glGetString(GL_EXTENSIONS);
- glGetString(GL_VERSION);
- __glXInitVertexArrayState(gc);
-  }
-   }
-
return GL_TRUE;
 }
 
diff --git a/src/glx/indirect_glx.c b/src/glx/indirect_glx.c
index cfae12f6c0..b552b5768a 100644
--- a/src/glx/indirect_glx.c
+++ b/src/glx/indirect_glx.c
@@ -148,9 +148,21 @@ indirect_bind_context(struct glx_context *gc, struct 
glx_context *old,
sent = SendMakeCurrentRequest(dpy, gc->xid, tag, draw, read,
 >currentContextTag);
 
-   if (!IndirectAPI)
-  IndirectAPI = __glXNewIndirectAPI();
-   _glapi_set_dispatch(IndirectAPI);
+   if (sent) {
+  if (!IndirectAPI)
+ IndirectAPI = __glXNewIndirectAPI();
+  _glapi_set_dispatch(IndirectAPI);
+
+  /* The indirect vertex array state must to be initialised after we
+   * have setup the context, as it needs to query server attributes.
+   */
+  __GLXattribute *state = gc->client_state_private;
+  if (state && state->array_state == NULL) {
+ glGetString(GL_EXTENSIONS);
+ glGetString(GL_VERSION);
+ __glXInitVertexArrayState(gc);
+  }
+   }
 
return !sent;
 }
-- 
2.14.3

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 1/6] glx: Simplify some dummy vtable interactions

[Adam Jackson]

The dummy vtable has these slots as NULL already, no need to check for
the dummy context explicitly.

Signed-off-by: Adam Jackson 
---
 src/glx/glxcmds.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/glx/glxcmds.c b/src/glx/glxcmds.c
index c707d0cedf..bc93d62510 100644
--- a/src/glx/glxcmds.c
+++ b/src/glx/glxcmds.c
@@ -528,7 +528,7 @@ glXWaitGL(void)
 {
struct glx_context *gc = __glXGetCurrentContext();
 
-   if (gc !=  && gc->vtable->wait_gl)
+   if (gc->vtable->wait_gl)
   gc->vtable->wait_gl(gc);
 }
 
@@ -541,7 +541,7 @@ glXWaitX(void)
 {
struct glx_context *gc = __glXGetCurrentContext();
 
-   if (gc !=  && gc->vtable->wait_x)
+   if (gc->vtable->wait_x)
   gc->vtable->wait_x(gc);
 }
 
@@ -550,7 +550,7 @@ glXUseXFont(Font font, int first, int count, int listBase)
 {
struct glx_context *gc = __glXGetCurrentContext();
 
-   if (gc !=  && gc->vtable->use_x_font)
+   if (gc->vtable->use_x_font)
   gc->vtable->use_x_font(gc, font, first, count, listBase);
 }
 
@@ -2431,7 +2431,7 @@ __glXBindTexImageEXT(Display * dpy,
 {
struct glx_context *gc = __glXGetCurrentContext();
 
-   if (gc ==  || gc->vtable->bind_tex_image == NULL)
+   if (gc->vtable->bind_tex_image == NULL)
   return;
 
gc->vtable->bind_tex_image(dpy, drawable, buffer, attrib_list);
@@ -2442,7 +2442,7 @@ __glXReleaseTexImageEXT(Display * dpy, GLXDrawable 
drawable, int buffer)
 {
struct glx_context *gc = __glXGetCurrentContext();
 
-   if (gc ==  || gc->vtable->release_tex_image == NULL)
+   if (gc->vtable->release_tex_image == NULL)
   return;
 
gc->vtable->release_tex_image(dpy, drawable, buffer);
-- 
2.14.3

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 4/6] glx: Lift sending the MakeCurrent request to top-level code

[Adam Jackson]

Somewhat terrifyingly, we never sent this for direct contexts, which
means the server never knew the context/drawable bindings.

To handle this sanely, pull the request code up out of the indirect
backend, and rewrite the context switch path to call it as appropriate.
This attempts to preserve the existing behavior of not calling unbind()
on the context if its refcount would not drop to zero, which is why the
diff is a little uglier than I'd like.

Signed-off-by: Adam Jackson 
---
 src/glx/glxcurrent.c   | 181 +
 src/glx/indirect_glx.c | 125 --
 2 files changed, 151 insertions(+), 155 deletions(-)

diff --git a/src/glx/glxcurrent.c b/src/glx/glxcurrent.c
index 9f8bf7cee1..7ee8a04a60 100644
--- a/src/glx/glxcurrent.c
+++ b/src/glx/glxcurrent.c
@@ -165,17 +165,85 @@ glXGetCurrentDrawable(void)
return gc->currentDrawable;
 }
 
-/**
- * Make a particular context current.
- *
- * \note This is in this file so that it can access dummyContext.
- */
+static Bool
+SendMakeCurrentRequest(Display * dpy, GLXContextID gc_id,
+   GLXContextTag gc_tag, GLXDrawable draw,
+   GLXDrawable read, GLXContextTag *out_tag)
+{
+   xGLXMakeCurrentReply reply;
+   Bool ret;
+   int opcode = __glXSetupForCommand(dpy);
+
+   LockDisplay(dpy);
+
+   if (draw == read) {
+  xGLXMakeCurrentReq *req;
+
+  GetReq(GLXMakeCurrent, req);
+  req->reqType = opcode;
+  req->glxCode = X_GLXMakeCurrent;
+  req->drawable = draw;
+  req->context = gc_id;
+  req->oldContextTag = gc_tag;
+   }
+   else {
+  struct glx_display *priv = __glXInitialize(dpy);
+
+  if ((priv->majorVersion > 1) || (priv->minorVersion >= 3)) {
+ xGLXMakeContextCurrentReq *req;
+
+ GetReq(GLXMakeContextCurrent, req);
+ req->reqType = opcode;
+ req->glxCode = X_GLXMakeContextCurrent;
+ req->drawable = draw;
+ req->readdrawable = read;
+ req->context = gc_id;
+ req->oldContextTag = gc_tag;
+  }
+  else {
+ xGLXVendorPrivateWithReplyReq *vpreq;
+ xGLXMakeCurrentReadSGIReq *req;
+
+ GetReqExtra(GLXVendorPrivateWithReply,
+ sz_xGLXMakeCurrentReadSGIReq -
+ sz_xGLXVendorPrivateWithReplyReq, vpreq);
+ req = (xGLXMakeCurrentReadSGIReq *) vpreq;
+ req->reqType = opcode;
+ req->glxCode = X_GLXVendorPrivateWithReply;
+ req->vendorCode = X_GLXvop_MakeCurrentReadSGI;
+ req->drawable = draw;
+ req->readable = read;
+ req->context = gc_id;
+ req->oldContextTag = gc_tag;
+  }
+   }
+
+   ret = _XReply(dpy, (xReply *) , 0, False);
+
+   if (out_tag)
+  *out_tag = reply.contextTag;
+
+   UnlockDisplay(dpy);
+   SyncHandle();
+
+   return ret;
+}
+
+static void
+SetGC(struct glx_context *gc, Display *dpy, GLXDrawable draw, GLXDrawable read)
+{
+   gc->currentDpy = dpy;
+   gc->currentDrawable = draw;
+   gc->currentReadable = read;
+}
+
 static Bool
 MakeContextCurrent(Display * dpy, GLXDrawable draw,
GLXDrawable read, GLXContext gc_user)
 {
struct glx_context *gc = (struct glx_context *) gc_user;
struct glx_context *oldGC = __glXGetCurrentContext();
+   Bool ret = GL_FALSE;
 
/* Make sure that the new context has a nonzero ID.  In the request,
 * a zero context ID is used only to mean that we bind to no current
@@ -186,59 +254,86 @@ MakeContextCurrent(Display * dpy, GLXDrawable draw,
}
 
_glapi_check_multithread();
-
__glXLock();
+
+   /* Same context and drawables: no op, just return */
if (oldGC == gc &&
-   gc->currentDrawable == draw && gc->currentReadable == read) {
-  __glXUnlock();
-  return True;
+   gc->currentDrawable == draw &&
+   gc->currentReadable == read) {
+  ret = GL_TRUE;
}
 
-   if (oldGC != ) {
-  if (--oldGC->thread_refcount == 0) {
-oldGC->vtable->unbind(oldGC, gc);
-oldGC->currentDpy = 0;
+   /* Same context and new drawbles: update drawable bindings */
+   else if (oldGC == gc) {
+  if (!SendMakeCurrentRequest(dpy, gc->xid, gc->currentContextTag,
+  draw, read, >currentContextTag)) {
+ goto out;
   }
-   }
 
-   if (gc) {
-  /* Attempt to bind the context.  We do this before mucking with
-   * gc and __glXSetCurrentContext to properly handle our state in
-   * case of an error.
-   *
-   * If an error occurs, set the Null context since we've already
-   * blown away our old context.  The caller is responsible for
-   * figuring out how to handle setting a valid context.
-   */
-  if (gc->vtable->bind(gc, oldGC, draw, read) != Success) {
+  if (gc->vtable->bind(gc, gc, draw, read) != Success) {
  __glXSetCurrentContextNull();
- __glXUnlock();
- __glXSendError(dpy, GLXBadContext, 

[Mesa-dev] [PATCH 6/6] glx: Implement GLX_EXT_no_config_context (v3)

[Adam Jackson]

This more or less ports EGL_KHR_no_config_context to GLX.

v2: Enable the extension only for those backends that support it.
v3: Fix glvnd path and dri2_convert_glx_attribs()

Khronos: https://github.com/KhronosGroup/OpenGL-Registry/pull/102
Reviewed-by: Kenneth Graunke 
Signed-off-by: Adam Jackson 
---
 src/glx/create_context.c  | 41 ++-
 src/glx/dri2_glx.c|  1 +
 src/glx/dri3_glx.c|  1 +
 src/glx/dri_common.c  |  4 
 src/glx/drisw_glx.c   |  1 +
 src/glx/g_glxglvnddispatchfuncs.c | 14 -
 src/glx/glxcmds.c |  2 +-
 src/glx/glxextensions.c   |  1 +
 src/glx/glxextensions.h   |  1 +
 9 files changed, 50 insertions(+), 16 deletions(-)

diff --git a/src/glx/create_context.c b/src/glx/create_context.c
index 38e949ab4c..eab6511ad8 100644
--- a/src/glx/create_context.c
+++ b/src/glx/create_context.c
@@ -47,21 +47,11 @@ glXCreateContextAttribsARB(Display *dpy, GLXFBConfig config,
xcb_generic_error_t *err;
xcb_void_cookie_t cookie;
unsigned dummy_err = 0;
+   int screen = -1;
 
-
-   if (dpy == NULL || cfg == NULL)
-  return NULL;
-
-   /* This means that either the caller passed the wrong display pointer or
-* one of the internal GLX data structures (probably the fbconfig) has an
-* error.  There is nothing sensible to do, so return an error.
-*/
-   psc = GetGLXScreenConfigs(dpy, cfg->screen);
-   if (psc == NULL)
+   if (dpy == NULL)
   return NULL;
 
-   assert(cfg->screen == psc->scr);
-
/* Count the number of attributes specified by the application.  All
 * attributes appear in pairs, except the terminating None.
 */
@@ -70,6 +60,29 @@ glXCreateContextAttribsARB(Display *dpy, GLXFBConfig config,
 /* empty */ ;
}
 
+   if (cfg) {
+  screen = cfg->screen;
+   } else {
+  int i;
+  for (i = 0; i < num_attribs; i++) {
+ if (attrib_list[i * 2] == GLX_SCREEN)
+screen = attrib_list[i * 2 + 1];
+  }
+   }
+
+   /* This means that either the caller passed the wrong display pointer or
+* one of the internal GLX data structures (probably the fbconfig) has an
+* error.  There is nothing sensible to do, so return an error.
+*/
+   psc = GetGLXScreenConfigs(dpy, screen);
+   if (psc == NULL)
+  return NULL;
+
+   assert(screen == psc->scr);
+
+   if (!cfg && !__glXExtensionBitIsEnabled(psc, EXT_no_config_context_bit))
+  return NULL;
+
if (direct && psc->vtable->create_context_attribs) {
   /* GLX drops the error returned by the driver.  The expectation is that
* an error will also be returned by the server.  The server's error
@@ -104,8 +117,8 @@ glXCreateContextAttribsARB(Display *dpy, GLXFBConfig config,
cookie =
   xcb_glx_create_context_attribs_arb_checked(c,
 gc->xid,
-cfg->fbconfigID,
-cfg->screen,
+cfg ? cfg->fbconfigID : 0,
+screen,
 gc->share_xid,
 gc->isDirect,
 num_attribs,
diff --git a/src/glx/dri2_glx.c b/src/glx/dri2_glx.c
index 0f44635725..eeec4f0d60 100644
--- a/src/glx/dri2_glx.c
+++ b/src/glx/dri2_glx.c
@@ -1129,6 +1129,7 @@ dri2BindExtensions(struct dri2_screen *psc, struct 
glx_display * priv,
 
   __glXEnableDirectExtension(>base, "GLX_ARB_create_context");
   __glXEnableDirectExtension(>base, "GLX_ARB_create_context_profile");
+  __glXEnableDirectExtension(>base, "GLX_EXT_no_config_context");
 
   if ((mask & ((1 << __DRI_API_GLES) |
(1 << __DRI_API_GLES2) |
diff --git a/src/glx/dri3_glx.c b/src/glx/dri3_glx.c
index a10306fe32..ac2e106a7e 100644
--- a/src/glx/dri3_glx.c
+++ b/src/glx/dri3_glx.c
@@ -720,6 +720,7 @@ dri3_bind_extensions(struct dri3_screen *psc, struct 
glx_display * priv,
 
__glXEnableDirectExtension(>base, "GLX_ARB_create_context");
__glXEnableDirectExtension(>base, "GLX_ARB_create_context_profile");
+   __glXEnableDirectExtension(>base, "GLX_EXT_no_config_context");
 
if ((mask & ((1 << __DRI_API_GLES) |
 (1 << __DRI_API_GLES2) |
diff --git a/src/glx/dri_common.c b/src/glx/dri_common.c
index 0d0b2d997b..2e0ecaaf8d 100644
--- a/src/glx/dri_common.c
+++ b/src/glx/dri_common.c
@@ -562,6 +562,10 @@ dri2_convert_glx_attribs(unsigned num_attribs, const 
uint32_t *attribs,
 return false;
  }
  break;
+  case GLX_SCREEN:
+ /* Implies GLX_EXT_no_config_context */
+ *render_type = GLX_DONT_CARE;
+ break;
   default:
 /* If an unknown attribute is received, fail.
  

[Mesa-dev] [PATCH 0/6] glx: Implement GLX_EXT_no_config_context

[Adam Jackson]

The first three here are mostly cleanup, but after that it got
complicated. 4/6 addresses a longstanding bug in the GLX client code
where direct contexts would generate no protocol on MakeCurrent, which
means the server was unable to know what drawables were bound to a
context. We're not presently using that knowledge for anything, but a
DDX might want to react to it - perhaps to change the pixmap's tiling or
memory domain - so it seems worth adding on its own. I have not yet
tried a full piglit run with that change, in particular not with an
older X server.

5/6 depends on that change for the GLX 1.2 case of making a bare Window
current (and forgetting to do glXCreateWindow). Real GLX drawables will
have been created relative to an fbconfig, but for a bare Window we want
to query the server's idea of the config for the drawable. For that to
work, the server has to know that the window has been made current and
applied a config to it, thus the dependency on 4/6.

6/6 itself is unchanged from the last time it was sent.

- ajax

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 10/18] radeon/vcn: add encode header implementations

[Zhang, Boyuan]

Zhang, Boyuan wrote:
>> 
>> On 14/11/17 10:53, Andy Furniss wrote:
 Zhang, Boyuan wrote:
>
>
> -Original Message-
> From: Zhang, Boyuan
> Sent: November-13-17 11:41 AM
> To: Andy Furniss; Koenig, Christian; Mark Thompson; 
> mesa-dev@lists.freedesktop.org
> Subject: RE: [Mesa-dev] [PATCH 10/18] radeon/vcn: add encode header 
> implementations
>
> Zhang, Boyuan wrote:
>
>> diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
>> b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
>> index 5170c67..c6dc420 100644
>> --- a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
>> +++ b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
>> @@ -362,6 +362,233 @@ static void radeon_enc_quality_params(struct 
>> radeon_encoder *enc)
>>  RADEON_ENC_END();
>>  }
>>  +static void radeon_enc_nalu_sps(struct radeon_encoder 
>> *enc) {
>> +RADEON_ENC_BEGIN(RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU);
>> +RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_SPS);
>> +uint32_t *size_in_bytes = 
>> >cs->current.buf[enc->cs->current.cdw++];
>> +radeon_enc_reset(enc);
>> +radeon_enc_set_emulation_prevention(enc, false);
>> +radeon_enc_code_fixed_bits(enc, 0x0001, 32);
>> +radeon_enc_code_fixed_bits(enc, 0x67, 8);
>> +radeon_enc_byte_align(enc);
>> +radeon_enc_set_emulation_prevention(enc, true);
>> +radeon_enc_code_fixed_bits(enc, 
>> enc->enc_pic.spec_misc.profile_idc, 8);
>> +radeon_enc_code_fixed_bits(enc, 0x04, 8);
> Please always set constraint_set1_flag when profile_idc is 66.  There 
> are enough actually-constrained-baseline-but-not-marked-as-such 
> streams in the world already to catch out decoders without full 
> baseline support (that is, all of them).
>
> Also, "constraint_set5_flag shall be equal to 0 when profile_idc is 
> not equal to 77, 88, 100, or 118".

>>> [Boyuan] Thanks for pointing out. I modified the value to be 0x44 in 
>>> the new patch (set1=1, and set5=1) since we only support constrained 
>>> baseline for now.
>>
>> It's not really with cabac though. I know there was a patch to turn it 
>> off - but that would have been wasteful and make linux < windows.
>>
>> Why not use 77 if cabac is on + not set constrained bits, windows seems 
>> to set main.
>>
>> Currently with vce trying to set main manually from ffmeg/gst in order 
>> to get something "correct" still sets flags = something that's not seen 
>> as main (but works).
>
> Yes, but still the problem is cabac is not allowed for baseline profile 
> and we only support baseline for now. I'm not quite sure about windows 
> test you mentioned, I'm just guessing that we might have some main 
> profile features support in some closed test environment on windows side, 
> but definitely not all main profile features, no b frame support.
> On linux side, we only support baseline profile for this vcn enc.
> (fixed a typo)

   Yea, it's tricky, FWIW windows does not use b-frames for the test I've 
 done (re-live turned up high = 50mbit 60fps).
>>>
>>> I can get B-frames from AMF with a GCN 2 card on Windows.
>> 
>> Yes, we used to support b-frame for GCN2 (e.g. like Bonaire, Kabini, etc...) 
>> cards. But for later Asics, we dropped the b-frame support. Including this 
>> raven vcn encode, b-frame is still not supported according to our firmware 
>> team.
>> - Boyuan
>> 
>>>
 It is flagged as main and uses cabac.
 I guess main is the "correct" way to describe constrained baseline + cabac 
 even if there are no other main features like b-frames.
>> 
>> Yes, I agree, that's the correct way in that case. However, we can't 
>> advertise main profile since we don't have b-frame support. It would cause 
>> serious problem if player tries to use b-frame when seeing that main profile 
>> is supported.
>
> I guess you mean encoder rather than player - I don't think a player should 
> care if there are no b-frames in main.
>
> FWIW vainfo does currently advertise main/high support, IIRC it was mentioned 
> in the past but lost in a long thread with many other issues in it.

I remember there was a discussion before about this, I will double check it and 
will probably make a patch to disable them if not yet disabled.

>
>  So as explained before, we only support constrained baseline profile for 
> this raven vcn encode now. And as a result, cabac is forced to be off in this 
> bring-up patch.
>
> Maybe advertise constrained baseline as encode + expose cabac switch that's 
> in the vaapi spec and let the user/app decide to force that.
If cabac is on then flag the output as main.

Thanks for this idea, I 

Re: [Mesa-dev] [PATCH 1/3] broadcom/vc4: fix indentation in vc4_screen.c

[Eric Anholt]

Andres Rodriguez  writes:

> Stumbled into this when adding a new PIPE_CAP.
>
> Signed-off-by: Andres Rodriguez 

Reviewed this one, and pushed the series with nh's reviews added.


signature.asc
Description: PGP signature
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 10/18] radeon/vcn: add encode header implementations

[Andy Furniss]

Zhang, Boyuan wrote:


On 14/11/17 10:53, Andy Furniss wrote:

Zhang, Boyuan wrote:



-Original Message-
From: Zhang, Boyuan
Sent: November-13-17 11:41 AM
To: Andy Furniss; Koenig, Christian; Mark Thompson; 
mesa-dev@lists.freedesktop.org
Subject: RE: [Mesa-dev] [PATCH 10/18] radeon/vcn: add encode header 
implementations

Zhang, Boyuan wrote:


diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
index 5170c67..c6dc420 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
@@ -362,6 +362,233 @@ static void radeon_enc_quality_params(struct 
radeon_encoder *enc)
 RADEON_ENC_END();
 }
 +static void radeon_enc_nalu_sps(struct radeon_encoder *enc) {
+RADEON_ENC_BEGIN(RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU);
+RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_SPS);
+uint32_t *size_in_bytes = >cs->current.buf[enc->cs->current.cdw++];
+radeon_enc_reset(enc);
+radeon_enc_set_emulation_prevention(enc, false);
+radeon_enc_code_fixed_bits(enc, 0x0001, 32);
+radeon_enc_code_fixed_bits(enc, 0x67, 8);
+radeon_enc_byte_align(enc);
+radeon_enc_set_emulation_prevention(enc, true);
+radeon_enc_code_fixed_bits(enc, enc->enc_pic.spec_misc.profile_idc, 8);
+radeon_enc_code_fixed_bits(enc, 0x04, 8);

Please always set constraint_set1_flag when profile_idc is 66.  There are 
enough actually-constrained-baseline-but-not-marked-as-such streams in the 
world already to catch out decoders without full baseline support (that is, all 
of them).

Also, "constraint_set5_flag shall be equal to 0 when profile_idc is not equal to 77, 
88, 100, or 118".


[Boyuan] Thanks for pointing out. I modified the value to be 0x44 in the new 
patch (set1=1, and set5=1) since we only support constrained baseline for now.


It's not really with cabac though. I know there was a patch to turn it off - but 
that would have been wasteful and make linux < windows.

Why not use 77 if cabac is on + not set constrained bits, windows seems to set 
main.

Currently with vce trying to set main manually from ffmeg/gst in order to get something 
"correct" still sets flags = something that's not seen as main (but works).


Yes, but still the problem is cabac is not allowed for baseline profile and we 
only support baseline for now. I'm not quite sure about windows test you 
mentioned, I'm just guessing that we might have some main profile features 
support in some closed test environment on windows side, but definitely not all 
main profile features, no b frame support.
On linux side, we only support baseline profile for this vcn enc.
(fixed a typo)


  Yea, it's tricky, FWIW windows does not use b-frames for the test I've done 
(re-live turned up high = 50mbit 60fps).


I can get B-frames from AMF with a GCN 2 card on Windows.


Yes, we used to support b-frame for GCN2 (e.g. like Bonaire, Kabini, etc...) 
cards. But for later Asics, we dropped the b-frame support. Including this 
raven vcn encode, b-frame is still not supported according to our firmware team.
- Boyuan




It is flagged as main and uses cabac.
I guess main is the "correct" way to describe constrained baseline + cabac even 
if there are no other main features like b-frames.


Yes, I agree, that's the correct way in that case. However, we can't advertise 
main profile since we don't have b-frame support. It would cause serious 
problem if player tries to use b-frame when seeing that main profile is 
supported.


I guess you mean encoder rather than player - I don't think a player 
should care if there are no b-frames in main.


FWIW vainfo does currently advertise main/high support, IIRC it was 
mentioned in the past but lost in a long thread with many other issues 
in it.


 So as explained before, we only support constrained baseline profile 
for this raven vcn encode now. And as a result, cabac is forced to be 
off in this bring-up patch.


Maybe advertise constrained baseline as encode + expose cabac switch 
that's in the vaapi spec and let the user/app decide to force that.

If cabac is on then flag the output as main.

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [ANNOUNCE] mesa 17.3.0-rc4

[Matt Turner]

On Tue, Nov 14, 2017 at 6:37 AM, Emil Velikov  wrote:
> The fourth release candidate for Mesa 17.3.0 is now available.
>
> As per the issue tracker [1] we still have a number of outstanding bugs
> blocking the release.
>
> [1] https://bugs.freedesktop.org/show_bug.cgi?id=103491
>
> Andreas Boll (3):
>   broadcom/vc5: Add vc5_drm.h to the release tarball
>   broadcom/vc5: Remove unused v3d_compiler.c
>   glsl: Fix typo fragement -> fragment
>
> Dave Airlie (2):
>   radv: free attachments on end command buffer.
>   radv: add initial copy descriptor support. (v2)
>
> Dylan Baker (1):
>   autotools: Set C++ visibility flags on Intel
>
> Emil Velikov (5):
>   targets/opencl: don't hardcode the icd file install to /etc/...
>   automake: intel: correctly append to the LIBADD variable
>   configure.ac: loosen --enable-glvnd check to honour egl
>   configure.ac: require xcb* for the omx/va/... when using x11 platform
>   Update version to 17.3.0-rc4
>
> Jason Ekstrand (15):
>   intel/fs: Use a pure vertical stride for large register strides

I've reverted this on master and sent an email to mesa-stable@ to
cherry-pick two other commits instead. Please revert this from 17.3.

Andres, you probably should do the same for 17.2.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] i965: disable BLORP color clears for gen 4-5

[Matt Turner]

On Thu, Nov 9, 2017 at 9:23 AM, Jason Ekstrand  wrote:
> This is a really rubbish solution.  Yes, it fixes a crash in MPV but unless
> we disable all blorp on gen4-5 (which I don't think is possible anymore), we
> haven't actually fixed it for real.

Are you planning to look into it? It's one week until 17.3.0 is
scheduled to be released.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH] r600: shader CF_OP_VTX also doesn't use the EOP bit.

[Gert Wollny]

Although the EOP bit is documented for the vertex fetch clause, it is not
properly interpreted. As a result the piglit
  spec/arb_tessellation_shader/execution/trivial-tess-gs_no-gs-inputs
creates a TESS_EVAL shader that does not have an EOP clause, which might
result in a GPU lockup.

This patch forces an additional CF_OP_NOP group like it is already done for
other final CF_OP groups.

Signed-off-by: Gert Wollny 
---
 src/gallium/drivers/r600/r600_shader.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/r600/r600_shader.c 
b/src/gallium/drivers/r600/r600_shader.c
index 0fa2a1f0d1..625537b48b 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -3720,7 +3720,9 @@ static int r600_shader_from_tgsi(struct r600_context 
*rctx,
last = r600_isa_cf(ctx.bc->cf_last->op);
 
/* alu clause instructions don't have EOP bit, so add NOP */
-   if (!last || last->flags & CF_ALU || ctx.bc->cf_last->op == 
CF_OP_LOOP_END || ctx.bc->cf_last->op == CF_OP_CALL_FS || ctx.bc->cf_last->op 
== CF_OP_POP || ctx.bc->cf_last->op == CF_OP_GDS)
+   if (!last || last->flags & CF_ALU || ctx.bc->cf_last->op == 
CF_OP_LOOP_END ||
+   ctx.bc->cf_last->op == CF_OP_CALL_FS || ctx.bc->cf_last->op 
== CF_OP_POP ||
+   ctx.bc->cf_last->op == CF_OP_GDS || ctx.bc->cf_last->op == 
CF_OP_VTX)
r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
 
ctx.bc->cf_last->end_of_program = 1;
-- 
2.13.6

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 1/3] vulkan/wsi: Add a wsi_image structure

[Jason Ekstrand]

From: Daniel Stone 

This is used to hold information about the allocated image, rather than
an ever-growing function argument list.

v2 (Jason Ekstrand):
 - Rename wsi_image_base to wsi_image

Signed-off-by: Daniel Stone 
Reviewed-by: Jason Ekstrand 
---
 src/amd/vulkan/radv_wsi.c   | 31 ++
 src/intel/vulkan/anv_wsi.c  | 25 +++---
 src/vulkan/wsi/wsi_common.h | 19 --
 src/vulkan/wsi/wsi_common_wayland.c | 31 +++---
 src/vulkan/wsi/wsi_common_x11.c | 52 ++---
 5 files changed, 65 insertions(+), 93 deletions(-)

diff --git a/src/amd/vulkan/radv_wsi.c b/src/amd/vulkan/radv_wsi.c
index 64f5b0d..248c1ee 100644
--- a/src/amd/vulkan/radv_wsi.c
+++ b/src/amd/vulkan/radv_wsi.c
@@ -144,11 +144,7 @@ radv_wsi_image_create(VkDevice device_h,
  const VkAllocationCallbacks* pAllocator,
  bool needs_linear_copy,
  bool linear,
- VkImage *image_p,
- VkDeviceMemory *memory_p,
- uint32_t *size,
- uint32_t *offset,
- uint32_t *row_pitch, int *fd_p)
+ struct wsi_image *wsi_image)
 {
VkResult result = VK_SUCCESS;
struct radeon_surf *surface;
@@ -231,20 +227,22 @@ radv_wsi_image_create(VkDevice device_h,
RADV_FROM_HANDLE(radv_device_memory, memory, memory_h);
if (!radv_get_memory_fd(device, memory, ))
goto fail_alloc_memory;
-   *fd_p = fd;
+   wsi_image->fd = fd;
}
 
surface = >surface;
 
-   *image_p = image_h;
-   *memory_p = memory_h;
-   *size = image->size;
-   *offset = image->offset;
-
+   wsi_image->image = image_h;
+   wsi_image->memory = memory_h;
+   wsi_image->size = image->size;
+   wsi_image->offset = image->offset;
if (device->physical_device->rad_info.chip_class >= GFX9)
-   *row_pitch = surface->u.gfx9.surf_pitch * surface->bpe;
+   wsi_image->row_pitch =
+   surface->u.gfx9.surf_pitch * surface->bpe;
else
-   *row_pitch = surface->u.legacy.level[0].nblk_x * surface->bpe;
+   wsi_image->row_pitch =
+   surface->u.legacy.level[0].nblk_x * surface->bpe;
+
return VK_SUCCESS;
  fail_alloc_memory:
radv_FreeMemory(device_h, memory_h, pAllocator);
@@ -258,12 +256,11 @@ fail_create_image:
 static void
 radv_wsi_image_free(VkDevice device,
const VkAllocationCallbacks* pAllocator,
-   VkImage image_h,
-   VkDeviceMemory memory_h)
+   struct wsi_image *wsi_image)
 {
-   radv_DestroyImage(device, image_h, pAllocator);
+   radv_DestroyImage(device, wsi_image->image, pAllocator);
 
-   radv_FreeMemory(device, memory_h, pAllocator);
+   radv_FreeMemory(device, wsi_image->memory, pAllocator);
 }
 
 static const struct wsi_image_fns radv_wsi_image_fns = {
diff --git a/src/intel/vulkan/anv_wsi.c b/src/intel/vulkan/anv_wsi.c
index 08d83cd..b7aacd8 100644
--- a/src/intel/vulkan/anv_wsi.c
+++ b/src/intel/vulkan/anv_wsi.c
@@ -174,11 +174,7 @@ anv_wsi_image_create(VkDevice device_h,
  const VkAllocationCallbacks* pAllocator,
  bool different_gpu,
  bool linear,
- VkImage *image_p,
- VkDeviceMemory *memory_p,
- uint32_t *size,
- uint32_t *offset,
- uint32_t *row_pitch, int *fd_p)
+ struct wsi_image *wsi_image)
 {
struct anv_device *device = anv_device_from_handle(device_h);
VkImage image_h;
@@ -244,7 +240,6 @@ anv_wsi_image_create(VkDevice device_h,
struct anv_surface *surface = >planes[0].surface;
assert(surface->isl.tiling == ISL_TILING_X);
 
-   *row_pitch = surface->isl.row_pitch;
int ret = anv_gem_set_tiling(device, memory->bo->gem_handle,
 surface->isl.row_pitch, I915_TILING_X);
if (ret) {
@@ -264,11 +259,12 @@ anv_wsi_image_create(VkDevice device_h,
   goto fail_alloc_memory;
}
 
-   *image_p = image_h;
-   *memory_p = memory_h;
-   *fd_p = fd;
-   *size = image->size;
-   *offset = 0;
+   wsi_image->image = image_h;
+   wsi_image->memory = memory_h;
+   wsi_image->fd = fd;
+   wsi_image->size = image->size;
+   wsi_image->offset = 0;
+   wsi_image->row_pitch = surface->isl.row_pitch;
return VK_SUCCESS;
 fail_alloc_memory:
anv_FreeMemory(device_h, memory_h, pAllocator);
@@ -281,12 +277,11 @@ fail_create_image:
 static void
 anv_wsi_image_free(VkDevice device,
const VkAllocationCallbacks* pAllocator,
-   VkImage image_h,
-