Re: [PEDA] Revision problems
Dennis The reason you want to use update afterwards is because you want to update relative to the latest netlist. Mike - Original Message - From: Dennis Saputelli [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Sunday, August 25, 2002 11:52 AM Subject: Re: [PEDA] Revision problems shouldn't you load the netlist AFTER the update? else stray tracks could pick up connectivity? i haven't found clearing nets necessary, although i do it sometime Dennis Saputelli Michael Reagan (EDSI) wrote: Robert, Update free primitives is a very good command to use. I use flawlessly on every design. If you are getting drc errors when invoking the command then you must have traces shorted from one pad to another. The exact process I use is different than most others recommended practice, here is what I do 1 clear all nets from the design 2. load a new netlist 3 update free primitives 4 run drcs The reason I follow this procedure is because it can save hours of Protel crunching the netlist over and over again. If the pcb still has drc errors then there is a problem in the pcb file. I have used this process for hundreds of designs, and hundreds of thousands connections. It has never failed me Mike Reagan EDSI Frederick MD - Original Message - From: Robert M. Wolfe [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Sunday, August 25, 2002 9:04 AM Subject: Re: [PEDA] Revision problems To All on this one, I have also been in this situation with a board I had to use the update free primitive to connected copper. IMHO this is a VERY VERY dangerous command unless you are ABSOLUTELY sure there is nothing touching any pads that it should not be. I have used fottprints of pads touching to tie A D GND's etc together and if that has been done it will pick one of those nets and make that one net. NOT just the fact that trace touched this was clearly only pads touching but it made both ends one net. Also if there were footprint changes and traces just happen to be touching things that really don't want to be you are also in trouble. Yes DRC should flag all of these but IMHO this is a very dangerous and time consuming way to deal with this. I had to use this function because I did a board with contact patterns for switches I built into the footprint, and this is the only way Protel deals with making those tracks in the footprint become proper net. Again don't like it at all this way. It also seems to me that Protel is not consistant with respect to update, I have seen in some cases what is described in this thread, and also times where it actually updated the nets properly to new connections. Also it does not seem consistant with update footprints either, sometimes it does it and sometimes I have had to update them manually as I knew I changed one and it was not updated during PCB update with that option checked. Also on this board I did see that Online DRC did not actually update in real time, only after moving aound the board, and if I remember correctly, and maybe closing and going back in did I in fact see the green come up to inform me I had the shorts. I have not dealt with that phone board in awhile and my changes to boards has been pretty minimal so I have not seen this in awhile, but I would say Protels PCB update is a little flaky, and a word of caution be very careful with the update free primitives command Bob Wolfe - Original Message - From: Dennis Saputelli [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Friday, August 23, 2002 9:25 PM Subject: Re: [PEDA] Revision problems i am on the same page as you about this and yes almost all of our bds have polygon pours, so that is probably at the root of the 'false DRCs' i always reload the netlist after a copper update, just a sanity check and now for a confession i STILL don't use the synchronizer i have been told i am missing something there and i don't doubt it i just never seem to have the time to learn anything and a lot of our netlists are from orcad with all the wrong footprints Dennis Saputelli Brad Velander wrote: I get those not really a DRC problem highlighing all the time. Drives me nuts. I can change the size of a pad that is connected to a pour (legally) and the whole pour lights up as a DRC. I usually repour the polygon because it is faster than running the DRC and the highlight goes away. When I see it, it is usually on a polygon pour. Yeah, I would expect that your check would work with the reloading of the netlist as well. I don't think that you mentioned the reload of the netlist in the first reply so he might have had a real
Re: [PEDA] Revision problems
Thanks Guys, I see all of your points, I agree with you that once you understand how it works you can use it safely. (it can be a time issue if you get out of wack) I was trying to point out that if you are not careful and like you said understand what it will do it can take a bit of time to get things back on track. A lesson I learned the hard way on that early design when I was struggling. I have also used it since but was surprised recently (like I said earlier) with the fact that it looked at pads touching and changed nets, but now that I know what to look for I can prepare better. It was only in one place on that design so it was quick to fix. It really comes down to the extra steps (time) to deal with these things, other systems I've used did deal with this a bit more gracefully. Sorry if a scared the original poster on this one. Bob Wolfe - Original Message - From: Dennis Saputelli [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Sunday, August 25, 2002 2:52 PM Subject: Re: [PEDA] Revision problems shouldn't you load the netlist AFTER the update? else stray tracks could pick up connectivity? i haven't found clearing nets necessary, although i do it sometime Dennis Saputelli Michael Reagan (EDSI) wrote: Robert, Update free primitives is a very good command to use. I use flawlessly on every design. If you are getting drc errors when invoking the command then you must have traces shorted from one pad to another. The exact process I use is different than most others recommended practice, here is what I do 1 clear all nets from the design 2. load a new netlist 3 update free primitives 4 run drcs The reason I follow this procedure is because it can save hours of Protel crunching the netlist over and over again. If the pcb still has drc errors then there is a problem in the pcb file. I have used this process for hundreds of designs, and hundreds of thousands connections. It has never failed me Mike Reagan EDSI Frederick MD - Original Message - From: Robert M. Wolfe [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Sunday, August 25, 2002 9:04 AM Subject: Re: [PEDA] Revision problems To All on this one, I have also been in this situation with a board I had to use the update free primitive to connected copper. IMHO this is a VERY VERY dangerous command unless you are ABSOLUTELY sure there is nothing touching any pads that it should not be. I have used fottprints of pads touching to tie A D GND's etc together and if that has been done it will pick one of those nets and make that one net. NOT just the fact that trace touched this was clearly only pads touching but it made both ends one net. Also if there were footprint changes and traces just happen to be touching things that really don't want to be you are also in trouble. Yes DRC should flag all of these but IMHO this is a very dangerous and time consuming way to deal with this. I had to use this function because I did a board with contact patterns for switches I built into the footprint, and this is the only way Protel deals with making those tracks in the footprint become proper net. Again don't like it at all this way. It also seems to me that Protel is not consistant with respect to update, I have seen in some cases what is described in this thread, and also times where it actually updated the nets properly to new connections. Also it does not seem consistant with update footprints either, sometimes it does it and sometimes I have had to update them manually as I knew I changed one and it was not updated during PCB update with that option checked. Also on this board I did see that Online DRC did not actually update in real time, only after moving aound the board, and if I remember correctly, and maybe closing and going back in did I in fact see the green come up to inform me I had the shorts. I have not dealt with that phone board in awhile and my changes to boards has been pretty minimal so I have not seen this in awhile, but I would say Protels PCB update is a little flaky, and a word of caution be very careful with the update free primitives command Bob Wolfe - Original Message - From: Dennis Saputelli [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Friday, August 23, 2002 9:25 PM Subject: Re: [PEDA] Revision problems i am on the same page as you about this and yes almost all of our bds have polygon pours, so that is probably at the root of the 'false DRCs' i always reload the netlist after a copper update, just a sanity check and now for a confession i STILL don't use the synchronizer i have been told i am missing something there and i don't doubt it i just never seem to have the time to learn anything and
[PEDA] Tearing my hair out with DXP
All, For those that might be trying the multichannel feature of DXP: I just learned the hard way (hours of fiddling) about a few confusing things with the method. The little bit of documentation in the manual, Introducing Protel DXP, creates a couple of misunderstandings that I could only resolve by taking the 8-channel Mixer example apart. So here are some lasting impressions from the experience, in the order of points presented in the manual. First, when you place a Sheet Symbol and add the Repeat(CIN,1,8) style Designator, DXP DOES NOT create a Sheet Symbol that looks like the one in the Mixer example with multiple overlapping sheets. These appear to be just artwork added to the mixer schematic as rectangles for dramatic effect and the example would better without them. I know it is a minor point, but when other things don't work as they probably will not, it left me thinking that I hadn't declared something correctly to invoke the full power of the repeat. True, it is shown correctly in the manual diagram on page 6-2 but I was hard to convince (for about an hour or so, much later, when trying to get all to work by generating a netlist without error). Second, the technique of representing the bus coming out of a Sheet Entry symbol that has a Repeat as a single wire which then connects directly to a bus, (so that individual signals can be picked out), is so crucial but not obvious looking at the example diagram on page 6-2. There is only a small stub of bus wire connected to the Headphone wire in the picture and I overlooked that for quite a while. Third, it is possible to have the designators in the sheets incremented sequentially as _1, _2, ..._n, by simply leaving out the first parameter of the Designator Repeat() statement. I think this will mean that the technique of repeating channels on the circuit layout (assuming you route by hand) by simply copying the first one multiple times should still produce the same orderly incrementation of the designator in each channel. But I haven't verified this yet. .end - of - rant. regards, Tim Hutcheson Research Associate Institute for Human and Machine Cognition University of West Florida 40 S. Alcaniz St. Pensacola, FL 32501 USA 805-202-4461 * Tracking #: 471375E444F874419B41CCFBFC51A3346C4D8132 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Protel 99SE license
Hello all, I have a client that is looking for a Protel 99SE license. Does anyone have one for sale. Please email me off-line at [EMAIL PROTECTED] Thanks, Lloyd Good Circuit Creations 92 Holly Street NW Calgary AB Canada T2K 2C8 ph: (403)282-6445 cell:(403)710-5077 * Tracking #: 1BA43D22D71ECD4592452DA407EE6CC24BCB6244 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] DXP Variants / version control
[PEDA] (No Subject)
Hi all, I am currently designing a printed circuit board in which the main part is a XILINX FPGA. What I want to know is: (please read on) Upon completion of the schematics of the board design do PCB designers do anything to verify the correctness of the board schematics like simulation ? Especially where something complex like a XILINX FPGA is involved. ---OR do PCB designers simply trust the correctness of the schematic and proceed with PCB placement and routing ? In short ,is any board-level simulation (involving SPICE models or something similar) done before fabrication of the board ? please do reply, thanks and regards, Anand Kulkarni ___ Communicate with others using Lycos Mail for FREE! http://mail.lycos.com * Tracking #: F6DD7356D13FD44894E20B0C64260132B0F040F4 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] (No Subject)
Yes, you trust the schematic and its netlist. If it is wrong, then the person that did the schematic screwed up. Now of course you can tell them you spotted something, like a power pin that was floating because they were using hidden pins and forgot to connect the right name, but don't fix it for them. Alert them and have them drive the fix. -Original Message- From: Anand Kulkarni [mailto:[EMAIL PROTECTED]] Sent: Monday, August 26, 2002 1:22 PM To: PROTEL USER Group Subject: [PEDA] (No Subject) Hi all, I am currently designing a printed circuit board in which the main part is a XILINX FPGA. What I want to know is: (please read on) Upon completion of the schematics of the board design do PCB designers do anything to verify the correctness of the board schematics like simulation ? Especially where something complex like a XILINX FPGA is involved. ---OR do PCB designers simply trust the correctness of the schematic and proceed with PCB placement and routing ? In short ,is any board-level simulation (involving SPICE models or something similar) done before fabrication of the board ? please do reply, thanks and regards, Anand Kulkarni ___ Communicate with others using Lycos Mail for FREE! http://mail.lycos.com * Tracking #: F6DD7356D13FD44894E20B0C64260132B0F040F4 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Fw: Protel 99SE license
LLoyd, I tried posting direct to you at your [EMAIL PROTECTED] , twice, and it bombed both tomes with the following fatal error message: The original message was received at Mon, 26 Aug 2002 16:18:03 -0400 from xxx.xxx.xxx.xxx pacbell.net [xxx.xxx.xxx.xxx] - The following addresses had permanent fatal errors - [EMAIL PROTECTED] - Transcript of session follows - 550 5.1.2 [EMAIL PROTECTED]... Host unknown (Name server: hansel.ugly-duckling.net.: host not found) I am replying here in the hope that you get this. JaMi PS. I xed out my direct dsl address in the above message. * * * * * * * * * * - Original Message - From: JaMi Smith [EMAIL PROTECTED] To: [EMAIL PROTECTED] Cc: JaMi Smith [EMAIL PROTECTED] Sent: Monday, August 26, 2002 1:18 PM Subject: Re: [PEDA] Protel 99SE license Lloyd, Considering the reception (or lack thereof) of DXP, It is entirely possible that your friend could get P99SE direct from Altium at a substantial discount if he was willing to purchase it and forego an ATS License and free Upgrade to DXP. Actually, I wouldn't be supprised to find that Altium may continue to sell Protel 99 SE, simply because many people do not want to buy into the DXP Product since it appears to actually be unproven as a product and have a number of unresolved problems, etc., etc., and also appears to require a substantial adaption / learning curve. I would check with Altium first, and if you strike out there, I would suggest checking with Mr. Lomax, as he may have a license or two for sale. JaMi Smith -- -- - - - - - - -- -- -- - - - -- - -- -- - -- -- - - - - -- - -- - - - -- - Original Message - From: Lloyd Good [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Monday, August 26, 2002 9:30 AM Subject: [PEDA] Protel 99SE license Hello all, I have a client that is looking for a Protel 99SE license. Does anyone have one for sale. Please email me off-line at [EMAIL PROTECTED] Thanks, Lloyd Good Circuit Creations 92 Holly Street NW Calgary AB Canada T2K 2C8 ph: (403)282-6445 cell:(403)710-5077 * Tracking #: 1BA43D22D71ECD4592452DA407EE6CC24BCB6244 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] (No Subject)
Anand, you are asking questions to which the answers shall be as varied as the number of respondents. The answers will of course be based upon the environments where the designers work. Some designers are actually EEs and they do all the design including PCBs, some are EEs but only do the circuit design and turn the PCB over to the PCB layout person, some are only PCB designers that don't touch schematics at all. See the problem with an answer to your question. There is no one answer. The responsibility will be as equally diverse as the particular environments. In our shop, I am the PCB designer. I am also responsible for CAD library generation/maintenance, schematic entry, BOM generation and PCB design. However I do not design the circuits. The Engineers are responsible for the overall design. Our circuits are microwave circuits so Protel is useless for simulation or other integrity verification. Sincerely, Brad Velander. Lead PCB Designer Norsat International Inc. Microwave Products Tel (604) 292-9089 (direct line) Fax (604) 292-9010 email: [EMAIL PROTECTED] http://www.norsat.com Norsat's Microwave Products Division has now achieved ISO 9001:2000 certification -Original Message- From: Anand Kulkarni [mailto:[EMAIL PROTECTED]] Sent: Monday, August 26, 2002 1:22 PM To: PROTEL USER Group Subject: [PEDA] (No Subject) Hi all, I am currently designing a printed circuit board in which the main part is a XILINX FPGA. What I want to know is: (please read on) Upon completion of the schematics of the board design do PCB designers do anything to verify the correctness of the board schematics like simulation ? Especially where something complex like a XILINX FPGA is involved. ---OR do PCB designers simply trust the correctness of the schematic and proceed with PCB placement and routing ? In short ,is any board-level simulation (involving SPICE models or something similar) done before fabrication of the board ? please do reply, thanks and regards, Anand Kulkarni * Tracking #: AF1C1D938208214FBB19C969E099D53FCF4343EC * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] (No Subject)
Anand asked: I am currently designing a printed circuit board in which the main part is a XILINX FPGA. What I want to know is: (please read on) Upon completion of the schematics of the board design do PCB designers do anything to verify the correctness of the board schematics like simulation ? Especially where something complex like a XILINX FPGA is involved. do PCB designers simply trust the correctness of the schematic and proceed with PCB placement and routing ? In short ,is any board-level simulation (involving SPICE models or something similar) done before fabrication of the board ? *** Hi Anand, Although we do perform simulation on occasions, its not really to verify copper path connections noted in a schematic, but to ascertain that component parameters perform as advertised, or, on the PCB. to examine parasitic or distributed-circuit charac- teristics. And I'll be honest with you... I do NOT do simulations for the physical layout of our boards. I follow good design rules when laying the board out, such as keeping traces far enough apart to prevent too great of crosstalk, using controlled im- pedances when necessary, and keeping ground and power planes close together. I am not saying that you should not perform this sort of simulation. We do very small limited runs. This allows me to add another couple layers if I want to spread things out. In a big production run this would arbitrarily introduce unacceptable added costs, and the price for an effective simulation would probably be worthwhile. good luck, miker * Tracking #: 06D2151CAADF5C48870F208E48FFABC7CDE708BE * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Tearing my hair out with DXP
Hi Tim, The drawing routines for this were overlooked in the first release but will be updated to correctly draw the overlapping style in SP1. My apologies for the confusion. Best Regards, Nick Martin Joint CEO, Altium - Original Message - From: Tim Hutcheson [EMAIL PROTECTED] To: peda [EMAIL PROTECTED] Sent: Tuesday, August 27, 2002 1:03 AM Subject: [PEDA] Tearing my hair out with DXP All, For those that might be trying the multichannel feature of DXP: I just learned the hard way (hours of fiddling) about a few confusing things with the method. The little bit of documentation in the manual, Introducing Protel DXP, creates a couple of misunderstandings that I could only resolve by taking the 8-channel Mixer example apart. So here are some lasting impressions from the experience, in the order of points presented in the manual. First, when you place a Sheet Symbol and add the Repeat(CIN,1,8) style Designator, DXP DOES NOT create a Sheet Symbol that looks like the one in the Mixer example with multiple overlapping sheets. These appear to be just artwork added to the mixer schematic as rectangles for dramatic effect and the example would better without them. I know it is a minor point, but when other things don't work as they probably will not, it left me thinking that I hadn't declared something correctly to invoke the full power of the repeat. True, it is shown correctly in the manual diagram on page 6-2 but I was hard to convince (for about an hour or so, much later, when trying to get all to work by generating a netlist without error). Second, the technique of representing the bus coming out of a Sheet Entry symbol that has a Repeat as a single wire which then connects directly to a bus, (so that individual signals can be picked out), is so crucial but not obvious looking at the example diagram on page 6-2. There is only a small stub of bus wire connected to the Headphone wire in the picture and I overlooked that for quite a while. Third, it is possible to have the designators in the sheets incremented sequentially as _1, _2, ..._n, by simply leaving out the first parameter of the Designator Repeat() statement. I think this will mean that the technique of repeating channels on the circuit layout (assuming you route by hand) by simply copying the first one multiple times should still produce the same orderly incrementation of the designator in each channel. But I haven't verified this yet. .end - of - rant. regards, Tim Hutcheson Research Associate Institute for Human and Machine Cognition University of West Florida 40 S. Alcaniz St. Pensacola, FL 32501 USA 805-202-4461 * Tracking #: 471375E444F874419B41CCFBFC51A3346C4D8132 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] (No Subject)
Anand Kulkarni wrote: Hi all, I am currently designing a printed circuit board in which the main part is a XILINX FPGA. What I want to know is: (please read on) Upon completion of the schematics of the board design do PCB designers do anything to verify the correctness of the board schematics like simulation ? Especially where something complex like a XILINX FPGA is involved. ---OR do PCB designers simply trust the correctness of the schematic and proceed with PCB placement and routing ? In short ,is any board-level simulation (involving SPICE models or something similar) done before fabrication of the board ? Generally, I think the answer is no. There may be some need to simulate critical traces, such as high-speed clocks, to evaluate need for termination, and similar things. A complete analog simulation of a complex digital circuit including the FPGA is beyond the capacity of todays computers, unless you have a HUGE budget, and a few months of real supercomputer time available. PCB designers generally are not involved in the verification of the circuitry, especially what is programmed into an FPGA. My personal approach to this is to possibly simulate a generalized case of a single signal, like one bit of a data bus, or possibly 2 bits to check cross-talk. Once you know the signal quality of a representative signal, and have varied some of the parameters to see over what range of trace lengths, for instance, proper operation is obtained, you can then apply this as a 'rule' against all the signals of the same character. Some of the people designing Pentium motherboards are supposed to be using lots of simulation, but I have no idea what tools they are using. I think it is pretty clear they are NOT using Protel99 for this. Jon * Tracking #: 5BBAE86F2A670642A7A4D94DB8F0729E3A643CF8 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
