Re: [time-nuts] 5 MHZ PIC PPS Divider?
Thank you for your ideas, It will be good for me to go thou the process of improvement one step at a time, I have several steps to try that should keep me busy, I expect to make several prototypes and with some luck try several methods. I do need to bootstrap my self up as I have to develop my tools as I go. Using one prototype to debug the next. My first goal will be to produce a crude counter and see how far I can push it. I have the freedom to fail as this is a hobby for me. A few of my replies to the list went to the individual and not the group, this was a pilot error, sorry. Thanks again to all who help, Stanley - Original Message From: Pete [EMAIL PROTECTED] To: Discussion of precise time and frequency measurement time-nuts@febo.com Sent: Wednesday, April 16, 2008 11:30:38 AM Subject: Re: [time-nuts] 5 MHZ PIC PPS Divider? Stanley, Sometimes I get tunnel vision by looking for easy answers in big box solutions. Your 1GHz clock solution may be a simpler approach for 1ns resolution provide a straightforward result. The ECL part you've selected seems to simplify interfacing with its synchronous enables. Perhaps interpolation could be used to enhance resolution if 1ns isn't adequate. Pete Rawson ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. Be a better friend, newshound, and know-it-all with Yahoo! Mobile. Try it now. http://mobile.yahoo.com/;_ylt=Ahu06i62sR8HDtDypao8Wcj9tAcJ ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 5 MHZ PIC PPS Divider?
The ECL part you've selected seems to simplify interfacing with its synchronous enables. I think you are missing the decimal point. A synchronous enable will have setup/hold times. They will (generally) be less than the cycle time (1 ns). You aren't going to get that level of timing accuracy out of a PIC. You will have to include a (small?) cloud of high speed logic around the basic counter chip to make it work right. If you want to use ECL counters, my straw man would be a free running counter a register to grab a copy of the counter logic to load the register on the rising edge of the PPS and generate a data-ready signal for the PIC That lets you grab the counter once each second. Subtract the previous value to get the number of ticks in this second. Make the counter wide enough so you can figure out the high bits. Or feed the top bit to a counter/timer in the PIC. Or use it for the PIC's clock. If you like ECL, here is another approach: Start with a shift register runing at 1 GHz Add a holding register that grabs a copy of the shift register every N clocks. The holding register goes into an FPGA that runs at 1/N GHz You have to make 2 clocks, and you have to make sure that the holding register meets setup time at the FPGA. That determines how big you have to make N. The FPGA would look for rising edges. If not, it bumps a counter by N. If it finds one (maybe by table lookup), it adds N-x to the counter, copies the counter to a holding register, and reloads the counter to x. Pipeline as necessary. Some FPGAs have high speed serial links. The contain a PLL and a big shift register and lots of logic to do 8B/10B decoding and recognize sync patterns and ... There is usually an option to disable that logic. So you could do everything in the FPGA. Unfortunately, they tend to be the (very) expensive chips. -- These are my opinions, not necessarily my employer's. I hate spam. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 5 MHZ PIC PPS Divider?
The two ways I hoped to get around the counter ripple was to measure every other set of PPS with the counter stopped in between. Or two counters running in opposite seconds, one running while the other is stopped. Due to my error not everyone received all the discussion, my email reply puts the list address or the person who wrote the reply on a random basis. Stanley - Original Message From: Hal Murray [EMAIL PROTECTED] To: Discussion of precise time and frequency measurement time-nuts@febo.com Sent: Wednesday, April 16, 2008 1:15:53 PM Subject: Re: [time-nuts] 5 MHZ PIC PPS Divider? The ECL part you've selected seems to simplify interfacing with its synchronous enables. I think you are missing the decimal point. A synchronous enable will have setup/hold times. They will (generally) be less than the cycle time (1 ns). You aren't going to get that level of timing accuracy out of a PIC. You will have to include a (small?) cloud of high speed logic around the basic counter chip to make it work right. If you want to use ECL counters, my straw man would be a free running counter a register to grab a copy of the counter logic to load the register on the rising edge of the PPS and generate a data-ready signal for the PIC That lets you grab the counter once each second. Subtract the previous value to get the number of ticks in this second. Make the counter wide enough so you can figure out the high bits. Or feed the top bit to a counter/timer in the PIC. Or use it for the PIC's clock. If you like ECL, here is another approach: Start with a shift register runing at 1 GHz Add a holding register that grabs a copy of the shift register every N clocks. The holding register goes into an FPGA that runs at 1/N GHz You have to make 2 clocks, and you have to make sure that the holding register meets setup time at the FPGA. That determines how big you have to make N. The FPGA would look for rising edges. If not, it bumps a counter by N. If it finds one (maybe by table lookup), it adds N-x to the counter, copies the counter to a holding register, and reloads the counter to x. Pipeline as necessary. Some FPGAs have high speed serial links. The contain a PLL and a big shift register and lots of logic to do 8B/10B decoding and recognize sync patterns and ... There is usually an option to disable that logic. So you could do everything in the FPGA. Unfortunately, they tend to be the (very) expensive chips. -- These are my opinions, not necessarily my employer's. I hate spam. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. Be a better friend, newshound, and know-it-all with Yahoo! Mobile. Try it now. http://mobile.yahoo.com/;_ylt=Ahu06i62sR8HDtDypao8Wcj9tAcJ ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 5 MHZ PIC PPS Divider?
Hi Bruce, did you or anyone every build this LTC application? I wonder about the tempco matching of the reference 1N457 diodes compensating the 2N5771 etc... bye, Said In a message dated 4/15/2008 21:32:14 Pacific Daylight Time, [EMAIL PROTECTED] writes: For one version of a classical time to amplitude converter (TAC) with an ADC connected across the ramp capacitor see: http://www.linear.com/pc/downloadDocument.do?navId=H0,C1,C1155,C1001,C1158,P14 37,D **Need a new ride? Check out the largest site for U.S. used car listings at AOL Autos. (http://autos.aol.com/used?NCID=aolcmp0030002851) ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 5 MHZ PIC PPS Divider?
[EMAIL PROTECTED] wrote: Hi Bruce, did you or anyone every build this LTC application? I wonder about the tempco matching of the reference 1N457 diodes compensating the 2N5771 etc... bye, Said Said Not this particular implementation but have built similar circuits decades ago. Tempco isnt an issue. There's plenty of time to interleave calibration cycles of say 100ns, 200ns, 300ns, 400ns duration between PPS measurements. It should even be possible to correct residual low order non linearity. With some elaboration is easy to construct a BJT current source with a residual tempco of around 100 ppm or so due to the BJT's hfe tempco. Replacing the polystyrene cap with a C0G/NP0 cap is probably worthwhile especially if one wishes to avoid hand soldering the polystyrene cap using heat sinks on the cap leads. This technique and variants thereof have been in use for decades in nuclear instrumentation. Another widely used technique is the Wilkinson converter wher the capacitor is charges by a large current during the time interval to be measured and the discharge time with a current perhps 1/1000 of this is measured using a comparator and a counter clocked at 10 or even a 100 MHz. Bruce ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 5 MHZ PIC PPS Divider?
Bruce Griffiths Correction added: Said Not this particular implementation but have built similar circuits decades ago. Tempco isnt an issue. There's plenty of time to interleave calibration cycles of say 100ns, 200ns, 300ns, 400ns duration between PPS measurements. It should even be possible to correct residual low order non linearity. With some elaboration is easy to construct a BJT current source with a residual tempco of around _100 ppm/C_ or so due to the BJT's hfe (~100) tempco. Replacing the polystyrene cap with a C0G/NP0 cap is probably worthwhile especially if one wishes to avoid hand soldering the polystyrene cap using heat sinks on the cap leads. This technique and variants thereof have been in use for decades in nuclear instrumentation. Another widely used technique is the Wilkinson converter wher the capacitor is charges by a large current during the time interval to be measured and the discharge time with a current perhps 1/1000 of this is measured using a comparator and a counter clocked at 10 or even a 100 MHz. Bruce ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 5 MHZ PIC PPS Divider?
Hi Bruce: The A/D used is only 12 bits @ 300 kHz and Linear now has very similar 12 bit A/D at 600 kHz and 24 bit much slower. Since a s/h is used to capture the ramp value the key spec seems to be that the hold time exceeds the conversion time. Are there s/h circuits that hold for more than 130 ms? Hard to say what hold means when talking about 24 bit conversions. I'm not sure of how droop would effect the result. I'm asking because the LTC2400 is about $8 compared to the LTC1273A for $25. Have Fun, Brooke Clarke http://www.prc68.com/P/Prod.html Products I make and sell http://www.prc68.com/Alpha.shtml All my web pages listed based on html name http://www.PRC68.com http://www.precisionclock.com http://www.prc68.com/I/WebCam2.shtml 24/7 Sky-Weather-Astronomy Web Cam Bruce Griffiths wrote: [EMAIL PROTECTED] wrote: Hi Bruce, did you or anyone every build this LTC application? I wonder about the tempco matching of the reference 1N457 diodes compensating the 2N5771 etc... bye, Said Said Not this particular implementation but have built similar circuits decades ago. Tempco isnt an issue. There's plenty of time to interleave calibration cycles of say 100ns, 200ns, 300ns, 400ns duration between PPS measurements. It should even be possible to correct residual low order non linearity. With some elaboration is easy to construct a BJT current source with a residual tempco of around 100 ppm or so due to the BJT's hfe tempco. Replacing the polystyrene cap with a C0G/NP0 cap is probably worthwhile especially if one wishes to avoid hand soldering the polystyrene cap using heat sinks on the cap leads. This technique and variants thereof have been in use for decades in nuclear instrumentation. Another widely used technique is the Wilkinson converter wher the capacitor is charges by a large current during the time interval to be measured and the discharge time with a current perhps 1/1000 of this is measured using a comparator and a counter clocked at 10 or even a 100 MHz. Bruce ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 5 MHZ PIC PPS Divider?
Brooke Clarke wrote: Hi Bruce: The A/D used is only 12 bits @ 300 kHz and Linear now has very similar 12 bit A/D at 600 kHz and 24 bit much slower. Since a s/h is used to capture the ramp value the key spec seems to be that the hold time exceeds the conversion time. Are there s/h circuits that hold for more than 130 ms? Hard to say what hold means when talking about 24 bit conversions. I'm not sure of how droop would effect the result. I'm asking because the LTC2400 is about $8 compared to the LTC1273A for $25. Have Fun, Brooke Clarke Brooke You would need a separate buffered sample and hold when using an LTC2400 or similar sigma delta ADC as opposed to a capacitive charge redistribuiton ADC like the LTC1273 and its successors. Perhaps the best way to extend the hold time is to resample the analog voltage with a slower acquisition time low leakage sample and hold circuit. Since the output is unipolar one could just ramp up an integrator until its output is equal to the voltage across the TAC capacitor. The LTC2400 has a periodic switched capacitor input so that it approximates a resistive load, thus the TAC output needs to be buffered. If you use guard rings etc the TAC leakage/discharge current may be around 100pA or so with a runup current of say 5mA. Thus discharge time for a 400ns full scale input will be around 20secs. Droop as long as its linear wont affect conversion linearity however it will affect the TAC gain. You would need to use a very low bias current buffer to drive the LTC2400, however its settling time can be quite slow. It would also be possible to use an modified integrator with a large shunt input cap for temporary charge storage whilst the integrator settles. I suspect it would be better to use a cheaper more modern charge redistribution ADC like an LTC1415 or similar. Bruce ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 5 MHZ PIC PPS Divider?
Hi Bruce, got it, I also like the pulse stretcher dual-slope interpolator technique you mention. bye, Said In a message dated 4/16/2008 17:36:44 Pacific Daylight Time, [EMAIL PROTECTED] writes: Another widely used technique is the Wilkinson converter wher the capacitor is charges by a large current during the time interval to be measured and the discharge time with a current perhps 1/1000 of this is measured using a comparator and a counter clocked at 10 or even a 100 MHz. **Need a new ride? Check out the largest site for U.S. used car listings at AOL Autos. (http://autos.aol.com/used?NCID=aolcmp0030002851) ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 5 MHZ PIC PPS Divider?
Web articles on jitter: http://www.maxim-ic.com/appnotes.cfm/an_pk/2744 http://www.pericom.com/pdf/applications/AB036.pdf http://www.vectron.com/products/appnotes/jitter.htm The last reference appears to have practical method to measure jitter in fig 5. This is very detailed method but beyond my means: http://www.cardinalxtal.com/docs/notes/jitter_paper.pdf This may be closer but still expensive : http://www.aubraux.com/dsp/jitter-software.php Thinking out loud the adjustments of the GPS disciplined clocks such as Brooks Shera's has much of the same hardware, perhaps some modifications would allow jitter measurements from the ASCII status output ? Using the same device a PIC, to measure errors in PICs may not work. But perhaps a low cost way to measure the difference between the 10Mhz standard input and the PPS output and transferring this to a PC spreadsheet for analysis without the expensive test equipment ? I'm not thinking of using the exact same PIC to output the data of it's own, but a separate PIC to move the data to the PC. Also just the measurements needed not enough data to reproduce the whole waveform. The measuring PIC may need to buffer the Data to reduce the effects of slow speed transfer and any interaction of the transfer on the timing of the measurement. What bothers me is actual measurment, quote from the cardinalxtal reference above : JITTER TESTING SET UP AND METHOD Several factors must be considered when making jitter measurements. • Use of a high performance, wide bandwidth oscilloscope with high-speed clock jitter analysis software. • Maximize the number of measured values (greater than 25,000) for a peak-to-peak measured sigma at or near +/-4. • Use an oscilloscope sampling rate of 8 GS/Second to capture multiple samples on the leading edge. • Use a well-designed test fixture with proper clock load to preserve the cleanliness of the signal edges. • The oscillator under test must use a low noise power source. It is recommended to use a 4.7 uF capacitor in parallel with a 0.01 uF capacitor on the power line next to the oscillator. In patricular the 25,000 samples and the 8GS/Second data rate, how to reduce this and still record useful data ? - Original Message From: Bruce Griffiths [EMAIL PROTECTED] To: Tom Van Baak [EMAIL PROTECTED]; Discussion of precise time and frequency measurement time-nuts@febo.com Sent: Sunday, April 13, 2008 8:42:55 PM Subject: Re: [time-nuts] 5 MHZ PIC PPS Divider? Tom Tom Van Baak wrote: If minimising the PPS jitter, is important adding a single D flipflop to resynchronise the output PPS signal to the 5MHz input will be worthwhile. A relatively complex chip like a PIC is likely to produce a PPS output signal with a jitter much greater than that produced by a single flipflop. Bruce, double check the PIC data sheet and see if this is really true. They are not complex chips; they run DC to 10 MHz, and all outputs are synchronous with the clock. The trouble is there is no jitter specification, I was rather hoping that someone had actually measured the jitter. Timing modulation will depend on simultaneous switching effects and the occurrence of asynchronous events as well as the impedance of the chips internal ground and power wiring as well as bond wire inductances etc. Some of the more complex PICs have internal PLLs which will inevitably increase the internal noise and consequently the output jitter. The less complex chips may have similar jitter to HCMOS parts although its hard to be certain given the poor propagation delay characterisation data in the PIC datsheets I have seen. Your implementation using a PIC without an internal PLL and having a fixed instruction execution and periodic sequence should help minimise random jitter. snip Be a better friend, newshound, and know-it-all with Yahoo! Mobile. Try it now. http://mobile.yahoo.com/;_ylt=Ahu06i62sR8HDtDypao8Wcj9tAcJ ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 5 MHZ PIC PPS Divider?
What I would want would be a count that measures the zero crossing of the PPS signal and the next zero crossing of the 10 Mhz input ? This would be one number every second as the output data. Is looking at the zero crossing of the two signals OK? Simple/low cost hardware to produce this number? DIY device vs generalized Lab equipment. Be a better friend, newshound, and know-it-all with Yahoo! Mobile. Try it now. http://mobile.yahoo.com/;_ylt=Ahu06i62sR8HDtDypao8Wcj9tAcJ ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 5 MHZ PIC PPS Divider?
Stanley, Jitter measurements of moderately high frequency sources can be made directly with relatively cheap used instruments. Older sampling 'scopes from H-P and TEK appear on *Bay frequently. The H-P 54120 family boxes are down to US$500 to 800 with sampling heads capable of 12.4GHz measurements. These show up about once per month. If you're trying to buy one, wait for a complete system (mainframe+sampling head) which is listed as operational you have confidence it's actually working. These things are HEAVY having to return a junker is painful; even if you get your money back. These mainframes have jitter capture analysis built in. The internal trigger jitter floor is about 1ps, good enough for most measurements. The internal timebase delay feature allows measuring multi- cycle jitter out to many screens width of data. Obviously, long delays will introduce added jitter floor contribution, but it's still quite good. Regards, Pete Rawson ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 5 MHZ PIC PPS Divider?
Thanks Pete not sure my wife will let another big box in the door. I was thinking of some thing like this : http://www.onsemi.com/PowerSolutions/product.do?id=MC100E137FN a ECL 8-Bit Ripple Counter. And a 1Ghz oscillator make the measurement of differences. This should get me to the 1ns level ? But looking at the sampling heads may be close to what I want, I will look for some manuals on the web. I would want to transfer the data to a PC, would I need a GPIB Interface and some software ? I'm trying to eliminate the extra stuff like the scope tube and it's power supply and end up with a small box to interface to the computer. - Original Message From: Pete [EMAIL PROTECTED] To: Discussion of precise time and frequency measurement time-nuts@febo.com Sent: Tuesday, April 15, 2008 3:13:02 PM Subject: Re: [time-nuts] 5 MHZ PIC PPS Divider? Stanley, Jitter measurements of moderately high frequency sources can be made directly with relatively cheap used instruments. Older sampling 'scopes from H-P and TEK appear on *Bay frequently. The H-P 54120 family boxes are down to US$500 to 800 with sampling heads capable of 12.4GHz measurements. These show up about once per month. If you're trying to buy one, wait for a complete system (mainframe+sampling head) which is listed as operational you have confidence it's actually working. These things are HEAVY having to return a junker is painful; even if you get your money back. These mainframes have jitter capture analysis built in. The internal trigger jitter floor is about 1ps, good enough for most measurements. The internal timebase delay feature allows measuring multi- cycle jitter out to many screens width of data. Obviously, long delays will introduce added jitter floor contribution, but it's still quite good. Regards, Pete Rawson ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. Be a better friend, newshound, and know-it-all with Yahoo! Mobile. Try it now. http://mobile.yahoo.com/;_ylt=Ahu06i62sR8HDtDypao8Wcj9tAcJ ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 5 MHZ PIC PPS Divider?
a ECL 8-Bit Ripple Counter. And a 1Ghz oscillator make the measurement of differences. This should get me to the 1ns level ? Or try a FPGA... They run at 250 MHz so all you need is 4 clock phases. The other approach would be to make a delay line that's longer than a single clock and has many FFs along the way. I'm not sure how to calibrate that and keep it calibrated as power/temp change. -- These are my opinions, not necessarily my employer's. I hate spam. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 5 MHZ PIC PPS Divider?
Not sure any calibration is needed as the measurement is + or - one count at 1Ghz and if we measure only the time to the next 10 Mhz pulse we have the rest of the 1/2 or whole second to transfer data and reset the counter if we don't allow for overflow. We could skip every other pulse if more time is needed for things to settle or the PIC to dump data. The output of the ring counter (1Ghz/256=38.4Mhz) could feed a counter in the PIC for more resolution if we wanted to count several PPS cycles, that is if the jitter was not huge. - Original Message From: Hal Murray [EMAIL PROTECTED] To: Discussion of precise time and frequency measurement time-nuts@febo.com Sent: Tuesday, April 15, 2008 4:42:53 PM Subject: Re: [time-nuts] 5 MHZ PIC PPS Divider? a ECL 8-Bit Ripple Counter. And a 1Ghz oscillator make the measurement of differences. This should get me to the 1ns level ? Or try a FPGA... They run at 250 MHz so all you need is 4 clock phases. The other approach would be to make a delay line that's longer than a single clock and has many FFs along the way. I'm not sure how to calibrate that and keep it calibrated as power/temp change. -- These are my opinions, not necessarily my employer's. I hate spam. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. Be a better friend, newshound, and know-it-all with Yahoo! Mobile. Try it now. http://mobile.yahoo.com/;_ylt=Ahu06i62sR8HDtDypao8Wcj9tAcJ ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 5 MHZ PIC PPS Divider?
More thinking out loud ... if the 1Ghz-2 Ghz oscillator is phase locked too the 10 Mhz signal then we reduce the error ? - Original Message From: Stanley Reynolds [EMAIL PROTECTED] To: Discussion of precise time and frequency measurement time-nuts@febo.com Sent: Tuesday, April 15, 2008 6:11:35 PM Subject: Re: [time-nuts] 5 MHZ PIC PPS Divider? Not sure any calibration is needed as the measurement is + or - one count at 1Ghz and if we measure only the time to the next 10 Mhz pulse we have the rest of the 1/2 or whole second to transfer data and reset the counter if we don't allow for overflow. We could skip every other pulse if more time is needed for things to settle or the PIC to dump data. The output of the ring counter (1Ghz/256=38.4Mhz) could feed a counter in the PIC for more resolution if we wanted to count several PPS cycles, that is if the jitter was not huge. - Original Message From: Hal Murray [EMAIL PROTECTED] To: Discussion of precise time and frequency measurement time-nuts@febo.com Sent: Tuesday, April 15, 2008 4:42:53 PM Subject: Re: [time-nuts] 5 MHZ PIC PPS Divider? a ECL 8-Bit Ripple Counter. And a 1Ghz oscillator make the measurement of differences. This should get me to the 1ns level ? Or try a FPGA... They run at 250 MHz so all you need is 4 clock phases. The other approach would be to make a delay line that's longer than a single clock and has many FFs along the way. I'm not sure how to calibrate that and keep it calibrated as power/temp change. -- These are my opinions, not necessarily my employer's. I hate spam. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. Be a better friend, newshound, and know-it-all with Yahoo! Mobile. Try it now. http://mobile.yahoo.com/;_ylt=Ahu06i62sR8HDtDypao8Wcj9tAcJ ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. Be a better friend, newshound, and know-it-all with Yahoo! Mobile. Try it now. http://mobile.yahoo.com/;_ylt=Ahu06i62sR8HDtDypao8Wcj9tAcJ ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 5 MHZ PIC PPS Divider?
Bruce Griffiths wrote: Stanley Reynolds wrote: Thanks Pete not sure my wife will let another big box in the door. I was thinking of some thing like this : http://www.onsemi.com/PowerSolutions/product.do?id=MC100E137FN a ECL 8-Bit Ripple Counter. And a 1Ghz oscillator make the measurement of differences. This should get me to the 1ns level ? But looking at the sampling heads may be close to what I want, I will look for some manuals on the web. I would want to transfer the data to a PC, would I need a GPIB Interface and some software ? I'm trying to eliminate the extra stuff like the scope tube and it's power supply and end up with a small box to interface to the computer. Stanley, Stanley Yet another technique is to low pass filter the PPS signal and sample it with a pipeline or similar high speed ADC clocked at say 100MHz (phase locked to the 10MHz standard). Then process the ADC output to determine the midpoint of the filtered PPS transition with subnanosecond (100ps should be easy to achieve) resolution. Only the conversions near the transition need be stored the others merely need to be counted. An FPGA makes this easy and since there is only one such transition per second a relatively slow processor should suffice. With the right FPGA you can build the processor right into the FPGA simplifying wiring. The Xilinx Spartan II starter kit, for example allows this, all you need do is connect it to the ADC board and use the built in LAN or serial port connection to connect to a PC. Bruce ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 5 MHZ PIC PPS Divider?
snip Using a ripple counter is a particularly bad idea, guaranteeing reliable sampling is likely to be difficult to impossible unless the counter is capable of reliable operation at several GHz. The problem being the ripple clock propagation delay from one flipflop to the next. For this counter the input clock to output transition delay is typically over 4nsec whilst the clock to Q0 delay is about 1.7ns a difference of 2.3 cycles at 1 GHz. Bruce Yes but if the PIC controls the counter Hold control you should have more than enough time for the counter to settle on the order of .5sec 1 sec when measuring a PPS signal. The chip cost is abt 8 USD . I was looking at this device because of it's speed and low cost the ripple delay was just a trade off, just as the low speed interface to the PC and limited data collected is a trade off. Be a better friend, newshound, and know-it-all with Yahoo! Mobile. Try it now. http://mobile.yahoo.com/;_ylt=Ahu06i62sR8HDtDypao8Wcj9tAcJ ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 5 MHZ PIC PPS Divider?
Stanley Reynolds wrote: snip Using a ripple counter is a particularly bad idea, guaranteeing reliable sampling is likely to be difficult to impossible unless the counter is capable of reliable operation at several GHz. The problem being the ripple clock propagation delay from one flipflop to the next. For this counter the input clock to output transition delay is typically over 4nsec whilst the clock to Q0 delay is about 1.7ns a difference of 2.3 cycles at 1 GHz. Bruce Yes but if the PIC controls the counter Hold control you should have more than enough time for the counter to settle on the order of .5sec 1 sec when measuring a PPS signal. The chip cost is abt 8 USD . I was looking at this device because of it's speed and low cost the ripple delay was just a trade off, just as the low speed interface to the PC and limited data collected is a trade off. Stanley You still need a 1GHz synchroniser (ECL dual D flipflop or shift register) for reliable operation when using the synchronous hold input (dont try using the asynchronous hold function as it is much more difficult to get this to work reliably). Range is only 256 ns so that when testing an oscillator with a relatively large instability or frequency offset count wrapping will be a problem. Bruce ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 5 MHZ PIC PPS Divider?
- Original Message From: Bruce Griffiths [EMAIL PROTECTED] To: Discussion of precise time and frequency measurement time-nuts@febo.com Sent: Tuesday, April 15, 2008 7:54:21 PM Subject: Re: [time-nuts] 5 MHZ PIC PPS Divider? Stanley Reynolds wrote: snip Using a ripple counter is a particularly bad idea, guaranteeing reliable sampling is likely to be difficult to impossible unless the counter is capable of reliable operation at several GHz. The problem being the ripple clock propagation delay from one flipflop to the next. For this counter the input clock to output transition delay is typically over 4nsec whilst the clock to Q0 delay is about 1.7ns a difference of 2.3 cycles at 1 GHz. Bruce Yes but if the PIC controls the counter Hold control you should have more than enough time for the counter to settle on the order of .5sec 1 sec when measuring a PPS signal. The chip cost is abt 8 USD . I was looking at this device because of it's speed and low cost the ripple delay was just a trade off, just as the low speed interface to the PC and limited data collected is a trade off. Stanley You still need a 1GHz synchroniser (ECL dual D flipflop or shift register) for reliable operation when using the synchronous hold input (dont try using the asynchronous hold function as it is much more difficult to get this to work reliably). Range is only 256 ns so that when testing an oscillator with a relatively large instability or frequency offset count wrapping will be a problem. Bruce I was thinking of using a counter in the PIC for extending the range, could also cut the clock rate if needed, but a 16 bit counter in the PIC if it would work at 38 Mhz. I notice that the chip has a number of controls, the asynch start and synch start as well as the low to high transition on the clock input: http://www.onsemi.com/pub_link/Collateral/MC10E137-D.PDF Table 2 the sequential truth table list the functions When you say reliable what is the error you mean ? A missed count of 1 out of a 100 should be acceptable. Page 7 lists several application notes AN1504/D − Metastability and the ECLinPS Family http://www.onsemi.com/pub_link/Collateral/AN1504-D.PDF I think this is what you are trying to tell me, if so I will study it. Or any reference you could recommend ? On-line references appeal to my cheap nature, and I want it now conditioning. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. Be a better friend, newshound, and know-it-all with Yahoo! Mobile. Try it now. http://mobile.yahoo.com/;_ylt=Ahu06i62sR8HDtDypao8Wcj9tAcJ ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 5 MHZ PIC PPS Divider?
Stanley Reynolds wrote: - Original Message From: Bruce Griffiths [EMAIL PROTECTED] To: Discussion of precise time and frequency measurement time-nuts@febo.com Sent: Tuesday, April 15, 2008 7:54:21 PM Subject: Re: [time-nuts] 5 MHZ PIC PPS Divider? Stanley Reynolds wrote: snip Using a ripple counter is a particularly bad idea, guaranteeing reliable sampling is likely to be difficult to impossible unless the counter is capable of reliable operation at several GHz. The problem being the ripple clock propagation delay from one flipflop to the next. For this counter the input clock to output transition delay is typically over 4nsec whilst the clock to Q0 delay is about 1.7ns a difference of 2.3 cycles at 1 GHz. Bruce Yes but if the PIC controls the counter Hold control you should have more than enough time for the counter to settle on the order of .5sec 1 sec when measuring a PPS signal. The chip cost is abt 8 USD . I was looking at this device because of it's speed and low cost the ripple delay was just a trade off, just as the low speed interface to the PC and limited data collected is a trade off. Stanley You still need a 1GHz synchroniser (ECL dual D flipflop or shift register) for reliable operation when using the synchronous hold input (dont try using the asynchronous hold function as it is much more difficult to get this to work reliably). Range is only 256 ns so that when testing an oscillator with a relatively large instability or frequency offset count wrapping will be a problem. Bruce I was thinking of using a counter in the PIC for extending the range, could also cut the clock rate if needed, but a 16 bit counter in the PIC if it would work at 38 Mhz. I notice that the chip has a number of controls, the asynch start and synch start as well as the low to high transition on the clock input: http://www.onsemi.com/pub_link/Collateral/MC10E137-D.PDF Table 2 the sequential truth table list the functions When you say reliable what is the error you mean ? A missed count of 1 out of a 100 should be acceptable. Page 7 lists several application notes AN1504/D − Metastability and the ECLinPS Family http://www.onsemi.com/pub_link/Collateral/AN1504-D.PDF I think this is what you are trying to tell me, if so I will study it. Or any reference you could recommend ? On-line references appeal to my cheap nature, and I want it now conditioning. ___ Stanley That application note will give you an introduction to metastability. A pair of multi GHz D flipflops should ensure that the probability of metastability is less than once in a hundred years or longer. Just make sure you wait long enough for both the ECL and the extension counters to settle. A better method is to read a very long counter on the fly (64 bits or more) at the (synchronised) PPS edge. However with ripple counters this gets tricky as one has to sample each bit at suitable times to ensure that the sampled count is actually valid. Software extension of the count chain (after the PIC counter) is also possible. I'd just interpolate a 10MHz clock: you can do this all with a PIC and ADC and some inexpensive analog hardware. Bruce ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 5 MHZ PIC PPS Divider?
snip Stanley That application note will give you an introduction to metastability. A pair of multi GHz D flipflops should ensure that the probability of metastability is less than once in a hundred years or longer. Just make sure you wait long enough for both the ECL and the extension counters to settle. A better method is to read a very long counter on the fly (64 bits or more) at the (synchronised) PPS edge. However with ripple counters this gets tricky as one has to sample each bit at suitable times to ensure that the sampled count is actually valid. Software extension of the count chain (after the PIC counter) is also possible. I'd just interpolate a 10MHz clock: you can do this all with a PIC and ADC and some inexpensive analog hardware. Bruce Thank you the pointers, I have found these explanations of interpolate : http://www.mwrf.com/Articles/ArticleID/12529/12529.html http://www.pendulum-instruments.com/Assets/download/timestamping_article.pdf As I understand it the trick is to measure the fractional parts of the wave at both the start and end or just the end if the start is synchronized, for a improvement in resolution at lower clock speeds. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. Be a better friend, newshound, and know-it-all with Yahoo! Mobile. Try it now. http://mobile.yahoo.com/;_ylt=Ahu06i62sR8HDtDypao8Wcj9tAcJ ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 5 MHZ PIC PPS Divider?
Stanley For one version of a classical time to amplitude converter (TAC) with an ADC connected across the ramp capacitor see: http://www.linear.com/pc/downloadDocument.do?navId=H0,C1,C1155,C1001,C1158,P1437,D - Datasheet for LTC1276 towards the end. With an increased power supply for the current sources a somewhat more linear version that doesnt require the non linearity correction is possible. Alternatively you can do the linearity correction in software. When sampling using a sinewave style interpolator one takes sine and cosine samples hence the phase angle is can be calculated from the samples. If the same sinewave clocks the counters then one can interpolate the count. A dual simultaneous sampling ADC is needed for each input. Expanding to multiple channels is easy particularly if they all sample the same continuously clocked counter. Bruce ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 5 MHZ PIC PPS Divider?
If minimising the PPS jitter, is important adding a single D flipflop to resynchronise the output PPS signal to the 5MHz input will be worthwhile. A relatively complex chip like a PIC is likely to produce a PPS output signal with a jitter much greater than that produced by a single flipflop. Bruce, double check the PIC data sheet and see if this is really true. They are not complex chips; they run DC to 10 MHz, and all outputs are synchronous with the clock. Measuring the PPS output jitter of the PIC will be somewhat challenging as It I would expect it to be somewhat less than 100ps. I think way less. I measured it with a 5370B when I designed the divider ten years ago. But I'll measure it again for you using better equipment. The corresponding output jitter at the resynchronising flipflop output should be significantly less than 10ps even for a 74HC74. In this case only the flipflop's random jitter is significant as the frequency and duty cycle of the PPS input to the flipflop are constant apart from the effects of jitter. Bruce This would be an interesting experiment. /tvb ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 5 MHZ PIC PPS Divider?
Tom, While the outputs change state synchronously with the clock, there may be many gates and latches inside the chip between the clock pin and the output, and the delay through those will be affected by temperature, supply voltage glitches and ground bounce, things that are not necessarily very well controlled inside the chip, so the jitter has to be more than a single external D-latch of J-K flip-flop with a decoupling cap across it will provide. Didier -Original Message- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On Behalf Of Tom Van Baak Sent: Sunday, April 13, 2008 9:55 AM To: Discussion of precise time and frequency measurement Subject: Re: [time-nuts] 5 MHZ PIC PPS Divider? If minimising the PPS jitter, is important adding a single D flipflop to resynchronise the output PPS signal to the 5MHz input will be worthwhile. A relatively complex chip like a PIC is likely to produce a PPS output signal with a jitter much greater than that produced by a single flipflop. Bruce, double check the PIC data sheet and see if this is really true. They are not complex chips; they run DC to 10 MHz, and all outputs are synchronous with the clock. Measuring the PPS output jitter of the PIC will be somewhat challenging as It I would expect it to be somewhat less than 100ps. I think way less. I measured it with a 5370B when I designed the divider ten years ago. But I'll measure it again for you using better equipment. The corresponding output jitter at the resynchronising flipflop output should be significantly less than 10ps even for a 74HC74. In this case only the flipflop's random jitter is significant as the frequency and duty cycle of the PPS input to the flipflop are constant apart from the effects of jitter. Bruce This would be an interesting experiment. /tvb ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. Internal Virus Database is out-of-date. Checked by AVG. Version: 7.5.519 / Virus Database: 269.22.5/1358 - Release Date: 4/3/2008 6:36 PM Internal Virus Database is out-of-date. Checked by AVG. Version: 7.5.519 / Virus Database: 269.22.5/1358 - Release Date: 4/3/2008 6:36 PM ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 5 MHZ PIC PPS Divider?
From some data sheets, if the Vcc to the external Flip Flop is regulated toward the high end of normal range the delay is reduced but not sure abt the jitter, my guess is they are inversely related but maybe a smaller delay means less jitter even if it increases in % of the delay. If you used a crystal oven on the FF then you could control the temperature but perhaps the higher temp would increase the jitter. Cooling with a Peltier effect CPU heat sink and thermostat instead of an oven to control the temp set below ambient ? Doesn't appear to conform to the KISS principal but does help me understand a little better. This reminds me of the laws of thermodynamics which are often abstract. - Original Message From: Didier Juges [EMAIL PROTECTED] To: Tom Van Baak [EMAIL PROTECTED]; Discussion of precise time and frequency measurement time-nuts@febo.com Sent: Sunday, April 13, 2008 10:09:47 AM Subject: Re: [time-nuts] 5 MHZ PIC PPS Divider? Tom, While the outputs change state synchronously with the clock, there may be many gates and latches inside the chip between the clock pin and the output, and the delay through those will be affected by temperature, supply voltage glitches and ground bounce, things that are not necessarily very well controlled inside the chip, so the jitter has to be more than a single external D-latch of J-K flip-flop with a decoupling cap across it will provide. Didier -Original Message- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On Behalf Of Tom Van Baak Sent: Sunday, April 13, 2008 9:55 AM To: Discussion of precise time and frequency measurement Subject: Re: [time-nuts] 5 MHZ PIC PPS Divider? If minimising the PPS jitter, is important adding a single D flipflop to resynchronise the output PPS signal to the 5MHz input will be worthwhile. A relatively complex chip like a PIC is likely to produce a PPS output signal with a jitter much greater than that produced by a single flipflop. Bruce, double check the PIC data sheet and see if this is really true. They are not complex chips; they run DC to 10 MHz, and all outputs are synchronous with the clock. Measuring the PPS output jitter of the PIC will be somewhat challenging as It I would expect it to be somewhat less than 100ps. I think way less. I measured it with a 5370B when I designed the divider ten years ago. But I'll measure it again for you using better equipment. The corresponding output jitter at the resynchronising flipflop output should be significantly less than 10ps even for a 74HC74. In this case only the flipflop's random jitter is significant as the frequency and duty cycle of the PPS input to the flipflop are constant apart from the effects of jitter. Bruce This would be an interesting experiment. /tvb ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. Internal Virus Database is out-of-date. Checked by AVG. Version: 7.5.519 / Virus Database: 269.22.5/1358 - Release Date: 4/3/2008 6:36 PM Internal Virus Database is out-of-date. Checked by AVG. Version: 7.5.519 / Virus Database: 269.22.5/1358 - Release Date: 4/3/2008 6:36 PM ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. __ Do You Yahoo!? Tired of spam? Yahoo! Mail has the best spam protection around http://mail.yahoo.com ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 5 MHZ PIC PPS Divider?
Tom Tom Van Baak wrote: If minimising the PPS jitter, is important adding a single D flipflop to resynchronise the output PPS signal to the 5MHz input will be worthwhile. A relatively complex chip like a PIC is likely to produce a PPS output signal with a jitter much greater than that produced by a single flipflop. Bruce, double check the PIC data sheet and see if this is really true. They are not complex chips; they run DC to 10 MHz, and all outputs are synchronous with the clock. The trouble is there is no jitter specification, I was rather hoping that someone had actually measured the jitter. Timing modulation will depend on simultaneous switching effects and the occurrence of asynchronous events as well as the impedance of the chips internal ground and power wiring as well as bond wire inductances etc. Some of the more complex PICs have internal PLLs which will inevitably increase the internal noise and consequently the output jitter. The less complex chips may have similar jitter to HCMOS parts although its hard to be certain given the poor propagation delay characterisation data in the PIC datsheets I have seen. Your implementation using a PIC without an internal PLL and having a fixed instruction execution and periodic sequence should help minimise random jitter. Measuring the PPS output jitter of the PIC will be somewhat challenging as It I would expect it to be somewhat less than 100ps. I think way less. I measured it with a 5370B when I designed the divider ten years ago. But I'll measure it again for you using better equipment. If its similar to the random jitter of an HCMOS gate (~5ps) then this measurement will be a little challenging. The corresponding output jitter at the resynchronising flipflop output should be significantly less than 10ps even for a 74HC74. In this case only the flipflop's random jitter is significant as the frequency and duty cycle of the PPS input to the flipflop are constant apart from the effects of jitter. Bruce This would be an interesting experiment. /tvb It is extremely difficult to characterise the propagation delay jitter with a 5370 unless one uses a large string of series connected gates. Using the same trick with a chain of flipflops is a little trickier. I suspect that the PIC clock to output pin transition delay tempco will be a limiting factor if the temperature varies too much. Similarly the propagation delay tempco of a 74HC74 will limt the long term delay stability. Bruce ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 5 MHZ PIC PPS Divider?
Thanks, Dave. I was under the impression from discussion long ago (and my memory may be wrong) that the change wasn't as trivial as it seemed. But if no other solution surfaces, I'll give this a try. By the way, I don't need 50% duty cycle, but I am trying to minimize jitter sources. See my reply to Bruce below for more on what I'm trying to accomplish. Thanks! John David Forbes said the following on 04/11/2008 04:12 PM: At 3:23 PM -0400 4/11/08, John Ackermann N8UR wrote: Has anyone come up with a 5 MHz input version of TVB's PIC divider? I could use one... Thanks, John John, I haven't done that, but it looks easy to do. Change the second stage to divide by 5 instead of 10. You will get 50 KHz instead of 100 KHz, but so what. This takes two changes in the constants for Digit1's tests: first... Loop1 BTFSC STATUS, Zero INCFDigit1 MOVLW BASE10 -- change BASE10 to 0x5 SUBWF Digit1, W BTFSC STATUS, Zero CLRFDigit1 later... MOVLW HALF10 -- change HALF10 to 0x2 SUBWF Digit1, W RRF OutByte, 1 ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 5 MHZ PIC PPS Divider?
Thanks, Bruce. I considered the idea of a multiplier but would like to use a software-only solution if I can. That's not only for simplicity, but also to eliminate additional sources of jitter; the experiment I have in mind is to test the second-to-second noise (and short term noise trends) of GPS and other PPS sources,* so I'm looking for as stable a reference as I can get. The additional noise from a mulitplier may be small, but I want to minimize the number of unknowns. Thanks! John * I realize that I'll also be limited by counter resolution. Bruce Griffiths said the following on 04/11/2008 05:56 PM: John Ackermann N8UR wrote: Has anyone come up with a 5 MHz input version of TVB's PIC divider? I could use one... Thanks, John John You could always cheat using a simple frequency doubler. Use a pair of diodes to create a fullwave rectified sinewave followed by a comparator for a sinewave input. A simple feedback loop can be used to ensure the comparator output duty cycle is 50%. Use a circuit that generates a pulse on every transition for a square wave input. Low pass filtering the square wave can be used to produce a waveform that the comparator above could work with. A feedback loop could be used to maintain the comparator output duty cycle at 50%. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 5 MHZ PIC PPS Divider?
Quoting John Ackermann N8UR [EMAIL PROTECTED], on Sat 12 Apr 2008 07:44:06 AM PDT: * I realize that I'll also be limited by counter resolution. Unless you use some sort of time to digital converter. There's some ASICs out there that do this, and I've seen CPLDs programmed to do it. The new fancy oscilloscopes from,e.g., Tektronix have this so that you can measure jitter to finer resolution than the 20Gs/s sample rate. Seems one could also do a similar Time-to-Digital thing by using the old vernier counter scheme.. take your 5MHz and create a slightly offset version (4.9,5.1, or 5.01, etc.) by dividing and mixing and hook it up to a second counter. Jim Lux ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 5 MHZ PIC PPS Divider?
At 10:34 AM -0400 4/12/08, John Ackermann N8UR wrote: Thanks, Dave. I was under the impression from discussion long ago (and my memory may be wrong) that the change wasn't as trivial as it seemed. But if no other solution surfaces, I'll give this a try. John, The change is indeed non-trivial if you want to make 100 KHz from 5 MHz. However, if you don't need the first stage to be the correct 100 KHz, it's a lot easier. -- --David Forbes, Tucson, AZ http://www.cathodecorner.com/ ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 5 MHZ PIC PPS Divider?
David Forbes said the following on 04/12/2008 12:16 PM: At 10:34 AM -0400 4/12/08, John Ackermann N8UR wrote: Thanks, Dave. I was under the impression from discussion long ago (and my memory may be wrong) that the change wasn't as trivial as it seemed. But if no other solution surfaces, I'll give this a try. John, The change is indeed non-trivial if you want to make 100 KHz from 5 MHz. However, if you don't need the first stage to be the correct 100 KHz, it's a lot easier. OK, I only need the PPS output, so losing 100kHz isn't a problem. Thanks! John ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 5 MHZ PIC PPS Divider?
John Ackermann N8UR wrote: Thanks, Bruce. I considered the idea of a multiplier but would like to use a software-only solution if I can. That's not only for simplicity, but also to eliminate additional sources of jitter; the experiment I have in mind is to test the second-to-second noise (and short term noise trends) of GPS and other PPS sources,* so I'm looking for as stable a reference as I can get. The additional noise from a mulitplier may be small, but I want to minimize the number of unknowns. Thanks! John * I realize that I'll also be limited by counter resolution. John If minimising the PPS jitter, is important adding a single D flipflop to resynchronise the output PPS signal to the 5MHz input will be worthwhile. A relatively complex chip like a PIC is likely to produce a PPS output signal with a jitter much greater than that produced by a single flipflop. Measuring the PPS output jitter of the PIC will be somewhat challenging as It I would expect it to be somewhat less than 100ps. The corresponding output jitter at the resynchronising flipflop output should be significantly less than 10ps even for a 74HC74. In this case only the flipflop's random jitter is significant as the frequency and duty cycle of the PPS input to the flipflop are constant apart from the effects of jitter. Bruce ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 5 MHZ PIC PPS Divider?
Bruce Griffiths wrote: John Ackermann N8UR wrote: Thanks, Bruce. I considered the idea of a multiplier but would like to use a software-only solution if I can. That's not only for simplicity, but also to eliminate additional sources of jitter; the experiment I have in mind is to test the second-to-second noise (and short term noise trends) of GPS and other PPS sources,* so I'm looking for as stable a reference as I can get. The additional noise from a mulitplier may be small, but I want to minimize the number of unknowns. Thanks! John * I realize that I'll also be limited by counter resolution. John If minimising the PPS jitter, is important adding a single D flipflop to resynchronise the output PPS signal to the 5MHz input will be worthwhile. A relatively complex chip like a PIC is likely to produce a PPS output signal with a jitter much greater than that produced by a single flipflop. Measuring the PPS output jitter of the PIC will be somewhat challenging as It I would expect it to be somewhat less than 100ps. The corresponding output jitter at the resynchronising flipflop output should be significantly less than 10ps even for a 74HC74. In this case only the flipflop's random jitter is significant as the frequency and duty cycle of the PPS input to the flipflop are constant apart from the effects of jitter. Bruce John It is also possible to use a frequency doubler to generate 10MHz from the 5MHz input to drive the PIC and resynchronise the resultant PPS output from the PIC to the 5MHz input using an external D flipflop. This will remove the jitter due to both the frequency divider and the PIC. Using a low phase shift filter (ie none ) at the doubler output will ensure a relatively stable delay between the 5MHz zero crossing and the 10MHz doubler output. Bruce ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 5 MHZ PIC PPS Divider?
John Since the PIC CLK input to output pin transition delay is relatively large (50ns or more on some datasheets) it is likely to have a relatively large tempco (several hundred ps/C) so this may be the primary limiting factor unless the thermal environment is very stable. A fast external resynchronising flipflop may have a clock to output delay and associated tempco at least 10X lower than this. Measuring the PIC clock input to PPS output delay tempco should be relatively easy if its tempco is indeed that large. Bruce ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 5 MHZ PIC PPS Divider?
Bruce Griffiths wrote: John Since the PIC CLK input to output pin transition delay is relatively large (50ns or more on some datasheets) it is likely to have a relatively large tempco (several hundred ps/C) so this may be the primary limiting factor unless the thermal environment is very stable. A fast external resynchronising flipflop may have a clock to output delay and associated tempco at least 10X lower than this. Measuring the PIC clock input to PPS output delay tempco should be relatively easy if its tempco is indeed that large. Bruce John If the temperature (of the output devices) were logged along with the PPS timing data then calibration of the clock to output transition delay should allow an effective improvement of at least a factor of 10 in effective delay tempco after correction for temperature fluctuations. Bruce ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 5 MHZ PIC PPS Divider?
At 3:23 PM -0400 4/11/08, John Ackermann N8UR wrote: Has anyone come up with a 5 MHz input version of TVB's PIC divider? I could use one... Thanks, John John, I haven't done that, but it looks easy to do. Change the second stage to divide by 5 instead of 10. You will get 50 KHz instead of 100 KHz, but so what. This takes two changes in the constants for Digit1's tests: first... Loop1 BTFSC STATUS, Zero INCFDigit1 MOVLW BASE10 -- change BASE10 to 0x5 SUBWF Digit1, W BTFSC STATUS, Zero CLRFDigit1 later... MOVLW HALF10 -- change HALF10 to 0x2 SUBWF Digit1, W RRF OutByte, 1 -- --David Forbes, Tucson, AZ http://www.cathodecorner.com/ ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 5 MHZ PIC PPS Divider?
John Ackermann N8UR wrote: Has anyone come up with a 5 MHz input version of TVB's PIC divider? I could use one... Thanks, John John You could always cheat using a simple frequency doubler. Use a pair of diodes to create a fullwave rectified sinewave followed by a comparator for a sinewave input. A simple feedback loop can be used to ensure the comparator output duty cycle is 50%. Use a circuit that generates a pulse on every transition for a square wave input. Low pass filtering the square wave can be used to produce a waveform that the comparator above could work with. A feedback loop could be used to maintain the comparator output duty cycle at 50%. Bruce ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
