[U-Boot] [PATCH 1/1] efi_loader: consistent naming of protocol GUIDs

[Heinrich Schuchardt]

We should consistently use the same name for protocol GUIDs as defined in
the UEFI specification. Not adhering to this rule has led to duplicate
definitions for the EFI_LOADED_IMAGE_PROTOCOL_GUID.

Adjust misnamed protocol GUIDs.

Adjust the text for the graphics output protocol in the output of the
`efidebug dh` command.

Signed-off-by: Heinrich Schuchardt 
---
 cmd/efidebug.c   | 10 +-
 include/efi_api.h| 18 +++---
 lib/efi/efi.c|  2 +-
 lib/efi/efi_stub.c   |  2 +-
 lib/efi_loader/efi_disk.c|  2 +-
 lib/efi_loader/efi_gop.c |  2 +-
 lib/efi_loader/efi_image_loader.c|  8 
 lib/efi_loader/efi_net.c |  4 ++--
 lib/efi_loader/helloworld.c  |  2 +-
 lib/efi_selftest/efi_selftest_bitblt.c   |  2 +-
 lib/efi_selftest/efi_selftest_block_device.c |  4 ++--
 lib/efi_selftest/efi_selftest_devicepath.c   |  2 +-
 lib/efi_selftest/efi_selftest_gop.c  |  2 +-
 lib/efi_selftest/efi_selftest_loadimage.c|  2 +-
 lib/efi_selftest/efi_selftest_miniapp_exit.c |  2 +-
 lib/efi_selftest/efi_selftest_snp.c  |  2 +-
 16 files changed, 31 insertions(+), 35 deletions(-)

diff --git a/cmd/efidebug.c b/cmd/efidebug.c
index db96682c5a..4bf91ed248 100644
--- a/cmd/efidebug.c
+++ b/cmd/efidebug.c
@@ -185,7 +185,7 @@ static const struct {
 } guid_list[] = {
{
"Device Path",
-   DEVICE_PATH_GUID,
+   EFI_DEVICE_PATH_PROTOCOL_GUID,
},
{
"Device Path To Text",
@@ -217,7 +217,7 @@ static const struct {
},
{
"Block IO",
-   BLOCK_IO_GUID,
+   EFI_BLOCK_IO_PROTOCOL_GUID,
},
{
"Simple File System",
@@ -225,11 +225,11 @@ static const struct {
},
{
"Loaded Image",
-   LOADED_IMAGE_PROTOCOL_GUID,
+   EFI_LOADED_IMAGE_PROTOCOL_GUID,
},
{
-   "GOP",
-   EFI_GOP_GUID,
+   "Graphics Output",
+   EFI_GRAPHICS_OUTPUT_PROTOCOL_GUID,
},
 };

diff --git a/include/efi_api.h b/include/efi_api.h
index 5b0a100635..472160cb30 100644
--- a/include/efi_api.h
+++ b/include/efi_api.h
@@ -290,10 +290,6 @@ struct efi_runtime_services {
EFI_GUID(0x8be4df61, 0x93ca, 0x11d2, 0xaa, 0x0d, \
 0x00, 0xe0, 0x98, 0x03, 0x2b, 0x8c)

-#define LOADED_IMAGE_PROTOCOL_GUID \
-   EFI_GUID(0x5b1b31a1, 0x9562, 0x11d2, 0x8e, 0x3f, \
-0x00, 0xa0, 0xc9, 0x69, 0x72, 0x3b)
-
 #define EFI_FDT_GUID \
EFI_GUID(0xb1b621d5, 0xf19c, 0x41a5, \
 0x83, 0x0b, 0xd9, 0x15, 0x2c, 0x69, 0xaa, 0xe0)
@@ -329,11 +325,11 @@ struct efi_system_table {
struct efi_configuration_table *tables;
 };

-#define LOADED_IMAGE_GUID \
+#define EFI_LOADED_IMAGE_PROTOCOL_GUID \
EFI_GUID(0x5b1b31a1, 0x9562, 0x11d2, \
 0x8e, 0x3f, 0x00, 0xa0, 0xc9, 0x69, 0x72, 0x3b)

-#define LOADED_IMAGE_DEVICE_PATH_GUID \
+#define EFI_LOADED_IMAGE_DEVICE_PATH_PROTOCOL_GUID \
EFI_GUID(0xbc62157e, 0x3e33, 0x4fec, \
 0x99, 0x20, 0x2d, 0x3b, 0x36, 0xd7, 0x50, 0xdf)

@@ -355,7 +351,7 @@ struct efi_loaded_image {
unsigned long unload;
 };

-#define DEVICE_PATH_GUID \
+#define EFI_DEVICE_PATH_PROTOCOL_GUID \
EFI_GUID(0x09576e91, 0x6d3f, 0x11d2, \
 0x8e, 0x39, 0x00, 0xa0, 0xc9, 0x69, 0x72, 0x3b)

@@ -478,7 +474,7 @@ struct efi_device_path_file_path {
u16 str[];
 } __packed;

-#define BLOCK_IO_GUID \
+#define EFI_BLOCK_IO_PROTOCOL_GUID \
EFI_GUID(0x964e5b21, 0x6459, 0x11d2, \
 0x8e, 0x39, 0x00, 0xa0, 0xc9, 0x69, 0x72, 0x3b)

@@ -1123,7 +1119,7 @@ struct efi_hii_config_access_protocol {
efi_browser_action_request_t *action_request);
 };

-#define EFI_GOP_GUID \
+#define EFI_GRAPHICS_OUTPUT_PROTOCOL_GUID \
EFI_GUID(0x9042a9de, 0x23dc, 0x4a38, \
 0x96, 0xfb, 0x7a, 0xde, 0xd0, 0x80, 0x51, 0x6a)

@@ -1175,7 +1171,7 @@ struct efi_gop {
struct efi_gop_mode *mode;
 };

-#define EFI_SIMPLE_NETWORK_GUID \
+#define EFI_SIMPLE_NETWORK_PROTOCOL_GUID \
EFI_GUID(0xa19832b9, 0xac25, 0x11d3, \
 0x9a, 0x2d, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d)

@@ -1268,7 +1264,7 @@ struct efi_simple_network {
struct efi_simple_network_mode *mode;
 };

-#define EFI_PXE_GUID \
+#define EFI_PXE_BASE_CODE_PROTOCOL_GUID \
EFI_GUID(0x03c4e603, 0xac28, 0x11d3, \
 0x9a, 0x2d, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d)

diff --git a/lib/efi/efi.c b/lib/efi/efi.c
index 2c6a50824f..7cba57b131 100644
--- a/lib/efi/efi.c
+++ b/lib/efi/efi.c
@@ -53,7 +53,7 @@ void efi_puts(struct efi_priv *priv, const char *str)
 int efi_init(struct efi_priv *priv, const char *banner, 

Re: [U-Boot] [PATCH v7 00/15] SiFive FU540 Support

[Atish Patra]

On 4/19/19 1:44 PM, Kevin Hilman wrote:

On Fri, Apr 19, 2019 at 1:38 PM Kevin Hilman  wrote:


Atish Patra  writes:


On 4/18/19 4:16 PM, Kevin Hilman wrote:

Atish Patra  writes:


On 4/18/19 12:15 PM, Kevin Hilman wrote:

Palmer, Anup,

On Tue, Mar 12, 2019 at 1:55 AM Palmer Dabbelt  wrote:


On Mon, 11 Mar 2019 07:33:25 PDT (-0700), bmeng...@gmail.com wrote:

On Thu, Feb 14, 2019 at 7:58 AM Kevin Hilman  wrote:


Kevin Hilman  writes:


Hi Anup,

Anup Patel  writes:


This patchset adds SiFive Freedom Unleashed (FU540) support
to RISC-V U-Boot.

The patches are based upon latest U-Boot source tree
(git://git.denx.de/u-boot.git) at commit id
dbe70c7d4e3d5c705a98d82952e05a591efd0683

All drivers namely: SiFive PRCI, SiFive Serial, and Cadance
MACB Ethernet work fine on actual SiFive Unleashed board and
QEMU sifive_u machine.


I tested u-boot networking (DHCP, TFTP) on my desk with a gigE switch
and it worked fine.  Then, I moved it to a lab with a 100Mb switch,
and DHCP doesn't work anymore.


And to be clear, neither does TFTP if setting static
ipaddr/netmask/gatewayip etc.


Sound to me a bug of the GEM driver on SiFive FU540 board.


It looks to me like u-boot is missing a driver for the GEM clockmux in the
FU540.  This is necessary to switch between the clock for 1G operation and 100M
operation.  Without this you'll just get whatever clock was set up by the
previous boot stage (or even worse, reset).


Anyone know if this is fixed in u-boot yet?  I've yet to try the
latest mainline u-boot, but will if if it's expected to work.



I have not seen a GEM driver for FU540 board. So I guess it is not fixed
it. Is it a blocker for setting up kernelCI for RISC-V ?


Not really, that's only one of the remaining issue. For now, I have
connected it to a gigE switch, so u-boot networking is working.

But, the bigger blocker for kernelCI right now is not having
out-of-the-box mainline support.  Mainline is still missing a serial
driver, and a handful of Kconfig options in the default defconfig to
make things boot[1].

If I use the 'v5.1-rc4_unleashed' from your github, along with my
kconfig fragment[1], things are working well.

But in order to automate this for kernelCI, we need all of that
upstream.


Yeah. I agree. We need upstream drivers sooner than later.
I believe SiFive Team (Paul & co) are working on this.

He recently sent updated version of driver patches to the linux-riscv
mailing list.


Yes, I'm trying to test all of those (hence our other discussion on the
DT thread)


[1] This is the config fragment I'm adding to the default defconfig in
mainline.  I'm not exactly sure which ones are absolutely need for basic
boot.

CONFIG_SERIAL_SIFIVE=y
CONFIG_SERIAL_SIFIVE_CONSOLE=y
CONFIG_SIFIVE_PLIC=y
CONFIG_SPI=y
CONFIG_SPI_SIFIVE=y
CONFIG_GPIOLIB=y
CONFIG_GPIO_SIFIVE=y
CONFIG_PWM_SIFIVE=y
CONFIG_CLK_U54_PRCI=y
CONFIG_CLK_GEMGXL_MGMT=y



My working config has enabled all of the above except CONFIG_PWM_SIFIVE.
I have not played around the config that much to find out absolute
minimum config. So this may not be the answer you are looking for :).


At least for kernelCI, we'll need to figure that out and get it upstream
if we want to boot test these.


Oh, and one other u-boot question.

Any reason you didn't enable `booti` support in riscv u-boot?  That
would allow you to boot the Image (or Image.gz) directly, instead of
the need to create a special image with u-boot header (uImage)

Yes. I am currently working on booti support. I should have a working 
patch by next week.


Regards,
Atish

Kevin



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Re: [U-Boot] [PATCH v2 1/2] warp7: Switch to DM Serial

[Fabio Estevam]

On Fri, Apr 19, 2019 at 3:35 PM Pierre-Jean Texier  wrote:
>
> This commit switches to DM SERIAL for warp7 and warp7_bl33 defconfigs.
>
> Signed-off-by: Pierre-Jean Texier 
> Signed-off-by: Joris Offouga 

Reviewed-by: Fabio Estevam 
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Re: [U-Boot] [PATCH v2 2/2] warp7: Switch to DM USB

[Fabio Estevam]

On Fri, Apr 19, 2019 at 3:35 PM Pierre-Jean Texier  wrote:
>
> This commit switches to DM USB for warp7 and warp7_bl33 defconfigs.
>
> Signed-off-by: Pierre-Jean Texier 
> Signed-off-by: Joris Offouga 

Reviewed-by: Fabio Estevam 
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Re: [U-Boot] Is mmc still being actively maintained?

[Lukasz Majewski]

Hi Peng,

> Hi All, Jaehoon
> 
> Is mmc still being actively maintained?

As fair as I can tell, it is "maintained" by Tom and Marek as last PR by
Jaehoon has been sent on:
Tue, 8 May 2018 16:22:14 +0900

> I would help if it is not
> being maintained.

It would be great if you could help with maintaining this code as a
dedicated Custodian.


> 
> Thanks,
> Peng.
> ___
> U-Boot mailing list
> U-Boot@lists.denx.de
> https://lists.denx.de/listinfo/u-boot




Best regards,

Lukasz Majewski

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Re: [U-Boot] [PATCH v2 00/10] clk: imx: Add i.MX6 CLK support

[Lukasz Majewski]

On Fri, 19 Apr 2019 08:52:28 +
Peng Fan  wrote:

> > On Fri, 19 Apr 2019 11:56:25 +0530
> > Jagan Teki  wrote:
> >   
> > > On Fri, Apr 5, 2019 at 2:20 AM Lukasz Majewski 
> > > wrote:  
> > > >
> > > > Hi Jagan,
> > > >  
> > > > > On Thu, Apr 4, 2019 at 3:31 PM Lukasz Majewski 
> > > > > wrote:  
> > > > > >
> > > > > > On Thu, 4 Apr 2019 14:56:36 +0530 Jagan Teki
> > > > > >  wrote:
> > > > > >  
> > > > > > > On Thu, Apr 4, 2019 at 2:31 PM Lukasz Majewski
> > > > > > >  wrote:  
> > > > > > > >
> > > > > > > > On Tue,  2 Apr 2019 16:58:33 +0530 Jagan Teki
> > > > > > > >  wrote:
> > > > > > > >  
> > > > > > > > > This is revised version of previous i.MX6 clock
> > > > > > > > > management [1].
> > > > > > > > >
> > > > > > > > > The main difference between previous version is
> > > > > > > > > - Group the i.MX6 ccm clocks into gates and tree
> > > > > > > > > instead of handling the clocks in simple way using
> > > > > > > > > case statement.
> > > > > > > > > - use gate clocks for enable/disable management.
> > > > > > > > > - use tree clocks for get/set rate or parent traverse
> > > > > > > > > management.
> > > > > > > > > - parent clock handling via clock type.
> > > > > > > > > - traverse the parent clock using recursive
> > > > > > > > > functionlaity.
> > > > > > > > >
> > > > > > > > > The main motive behind this tree framework is to make
> > > > > > > > > the clock tree management simple and useful for U-Boot
> > > > > > > > > requirements instead of garbing Linux clock management
> > > > > > > > > code.
> > > > > > > > >
> > > > > > > > > We are trying to manage the Allwinner clocks with
> > > > > > > > > similar kind, so having this would really help i.MX6
> > > > > > > > > as well.
> > > > > > > > >
> > > > > > > > > Added simple names for clock macros, but will update
> > > > > > > > > it in future version.
> > > > > > > > >
> > > > > > > > > I have skipped ENET clocks from previous series, will
> > > > > > > > > add it in future patches.
> > > > > > > > >
> > > > > > > > > Changes for v2:
> > > > > > > > > - changed framework patches.
> > > > > > > > > - add support for imx6qdl and imx6ul boards
> > > > > > > > > - add clock gates, tree.
> > > > > > > > >
> > > > > > > > > [1] https://patchwork.ozlabs.org/cover/950964/
> > > > > > > > >
> > > > > > > > > Any inputs?  
> > > > > > > >
> > > > > > > > Hmm It looks like we are doing some development in
> > > > > > > > parallel.
> > > > > > > >
> > > > > > > > Please look into following commit [1]:
> > > > > > > > https://patchwork.ozlabs.org/patch/1034051/
> > > > > > > >
> > > > > > > > It ports from Linux 5.0 the CCF framework for iMX6Q,
> > > > > > > > which IMHO in the long term is a better approach.
> > > > > > > > The code is kept simple and resembles the code from
> > > > > > > > Barebox.
> > > > > > > >
> > > > > > > > Please correct me if I'm wrong, but the code from your
> > > > > > > > work is not modeling muxes, gates and other components
> > > > > > > > from Linux CCF.  
> > > > > > >
> > > > > > > The U-Boot implementation of CLK would require as minimal
> > > > > > > and simple as possible due to requirement of U-Boot
> > > > > > > itself. Hope you agree this point?  
> > > > > >
> > > > > > Now i.MX6 is using clock.c CLK implementation. If we decide
> > > > > > to replace it - we shall do it in a way, which would allow
> > > > > > us to follow Linux kernel. (the barebox implementation is a
> > > > > > stripped CCF from Linux, the same is in patch [1]).
> > > > > >  
> > > > > > > if yes having CCF stack code to handle all clock with
> > > > > > > respective separate drivers management is may not require
> > > > > > > as of now, IMHO.  
> > > > > >
> > > > > > I do have a gut feeling, that we will end up with the need
> > > > > > to have the CCF framework ported anyway. As for example
> > > > > > imx7/8 can re-use muxes, gates code.  
> > > > >
> > > > > As per my experience the main the over-ahead to handle clocks
> > > > > in U-Boot if we go with separate clock drivers is for Video
> > > > > and Ethernet peripherals. these are key IP's which use more
> > > > > clocks from U-Boot point-of-view, others can be handle pretty
> > > > > straight-forward unless if they don't have too much tree
> > > > > chain.
> > > > >
> > > > > On this series, the tree management is already supported ENET
> > > > > in i.MX6, and Allwinner platforms.
> > > > >
> > > > > As of now, I'm thinking I can handle reset of the clocks with
> > > > > similar way.  
> > > >
> > > > But this code also supports ENET and ESDHCI clocks on i.MX6Q (as
> > > > supporting those was the motivator for this work).
> > > >
> > > > One important thing to be aware of - the problem with SPL's
> > > > footprint. The implementation with clock.c is small and simple,
> > > > but doesn't scale well.
> > > >  
> > > > >  
> > > > > >
> > > > > > However, those are only my "feelings" after a glimpse look
> > > > > > - I will look into your code more thoroughly and 

[U-Boot] [GIT] Pull request: u-boot-dfu v2 (14.04.2019)

[Lukasz Majewski]

Dear Marek,

The following changes since commit
1f4ae66eaab29bfb5d1eb44996f7826c9cd01ed1:

  Merge tag 'arc-for-2019.07' of git://git.denx.de/u-boot-arc
  (2019-04-18 12:12:16 -0400)

are available in the git repository at:

  git://git.denx.de/u-boot-dfu.git 

for you to fetch changes up to 5e24783e992e0b2749a0e39ba3cab9900cd0b759:

  usb: dwc2: fix gadget disconnect (2019-04-19 16:56:53 +0200)


Alex Kiernan (1):
  fastboot: Replace literal 32 with PART_NAME_LEN

Andy Shevchenko (1):
  dfu: Avoid declaring unused variables and absent parameters

Eugeniu Rosca (3):
  fastboot: getvar: correct/rename "has_slot" to "has-slot"
  fastboot: Improve error reporting on 'getvar partition-{size,
type}' fastboot: add support for 'getvar platform'

Fabrice Gasnier (1):
  usb: dwc2: fix gadget disconnect

Patrice Chotard (1):
  usb: dwc2_udc_otg: Add tx_fifo_sz array support

Patrick Delaunay (16):
  phy: usbphyc: remove unused variable index
  phy: usbphyc: update xlate with DT binding
  phy: usbphyc: Binding update of vdda supply
  phy: usbphyc: move vdda1v1 and vdda1v8 in phy_init
  phy: usbphyc: increase PLL wait timeout
  usb: dwc2: remove unused variable regs_otg
  usb: dwc2: convert driver to DM_USB_GADGET
  usb: dwc2: force reset assert before to probe the driver
  usb: dwc2: Add force-b-session-valid support
  usb: dwc2: Add function for session B check
  usb: dwc2_udc_otg: Read MAX_HW_ENDPOINT from HWCFG4 register
  usb: dwc2: add support for STM32MP1
  stm32mp1: remove CONFIG_USB_DWC2, HOST support for USBO
  stm32mp1: migrate USBOTG device to driver model
  stm32mp1: add stusb1600 support for DK1 and DK2 board
  usb: reload watchdog during ums command


 arch/arm/dts/stm32mp157-pinctrl.dtsi   |   7 ++
 arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi   |   3 +-
 arch/arm/dts/stm32mp157a-dk1.dts   |  34 +++-
 arch/arm/dts/stm32mp157c-ed1.dts   |   8 --
 arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi   |   1 +
 arch/arm/dts/stm32mp157c.dtsi  |   5 +-
 board/st/stm32mp1/stm32mp1.c   | 185
 +++--
 cmd/dfu.c  |   3 +
 cmd/usb_mass_storage.c |   3 +
 configs/stm32mp15_basic_defconfig  |   2 +-
 configs/stm32mp15_trusted_defconfig|   2 +-
 doc/device-tree-bindings/phy/phy-stm32-usbphyc.txt |   4 +-
 doc/device-tree-bindings/usb/dwc2.txt  |  58 +
 drivers/fastboot/fb_getvar.c   |  16 +++-
 drivers/fastboot/fb_mmc.c  |  10 +--
 drivers/phy/phy-stm32-usbphyc.c| 111
 +
 drivers/usb/gadget/dwc2_udc_otg.c  | 388
 
--
 drivers/usb/gadget/dwc2_udc_otg_priv.h |   1 -
 drivers/usb/gadget/dwc2_udc_otg_regs.h |  37 +++--
 drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c |  14 +++-
 include/usb/dwc2_udc.h |   7 ++ 21 files
 changed, 670 insertions(+), 229 deletions(-) create mode 100644
 doc/device-tree-bindings/usb/dwc2.txt

Travis-CI:
https://travis-ci.org/lmajewski/u-boot-dfu/builds/522181824

Best regards,

Lukasz Majewski

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Re: [U-Boot] [PATCH v3] arm: socfpga: mailbox: Fix off-by-one error on command length checking

[Simon Goldschmidt]

Marek Vasut  schrieb am Fr., 19. Apr. 2019, 11:29:

> On 4/19/19 8:17 AM, Ley Foon Tan wrote:
> > A mailbox command contains 1-DWORD header + arguments. The "len" variable
> > only contains the length of the arguments, but not the 1-DWORD header.
> > Include the length of header when checking the ring buffer space to
> > prevent off-by-one error.
>
> How long is a DWORD ? Windows API (which we have nothing to do with)
> defines that as 32bit type, "typedef unsigned long DWORD;", see [1].
> But the patch below fixes an off-by-one error , not off by four error ?
>

As all the macros for that mailbox seem to do u32 index access only, I'd be
ok with the commit message if it didn't use the term 'DWORD'...

Regards,
Simon


> [1]
> https://docs.microsoft.com/en-us/windows/desktop/winprog/windows-data-types
>
> > Signed-off-by: Ley Foon Tan 
> > Signed-off-by: Chee Hong Ang 
> > ---
> > v2->v3:
> > - Update commit description.
> > ---
> >  arch/arm/mach-socfpga/mailbox_s10.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/arch/arm/mach-socfpga/mailbox_s10.c
> b/arch/arm/mach-socfpga/mailbox_s10.c
> > index 3c33223936..8363c93e90 100644
> > --- a/arch/arm/mach-socfpga/mailbox_s10.c
> > +++ b/arch/arm/mach-socfpga/mailbox_s10.c
> > @@ -59,7 +59,7 @@ static __always_inline int
> mbox_fill_cmd_circular_buff(u32 header, u32 len,
> >*/
> >   if (((cin + 1) % MBOX_CMD_BUFFER_SIZE) == cout ||
> >   ((MBOX_CMD_BUFFER_SIZE - cin + cout - 1) %
> > -  MBOX_CMD_BUFFER_SIZE) < len)
> > +  MBOX_CMD_BUFFER_SIZE) < (len + 1))
> >   return -ENOMEM;
> >
> >   /* write header to circular buffer */
> >
>
>
> --
> Best regards,
> Marek Vasut
>
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Re: [U-Boot] [PULL] u-boot-socfpga/master

[Simon Goldschmidt]

Marek Vasut  schrieb am Di., 16. Apr. 2019, 23:14:

> On 4/16/19 10:08 PM, Simon Goldschmidt wrote:
> > Hi Marek,
> >
> > Am 12.04.2019 um 12:31 schrieb Marek Vasut:
> >> On 4/11/19 10:07 PM, Simon Goldschmidt wrote:
> >>>
> >>>
> >>> Marek Vasut mailto:ma...@denx.de>> schrieb am Do., 11.
> >>> Apr. 2019, 21:59:
> >>>
> >>>  On 4/11/19 9:30 PM, Simon Goldschmidt wrote:
> >>>  >
> >>>  >
> >>>  > On 11.04.19 21:03, Tom Rini wrote:
> >>>  >> On Thu, Apr 11, 2019 at 08:49:38PM +0200, Simon Goldschmidt
> >>> wrote:
> >>>  >>>
> >>>  >>>
> >>>  >>> On 11.04.19 20:20, Tom Rini wrote:
> >>>   On Thu, Apr 11, 2019 at 08:19:38PM +0200, Marek Vasut wrote:
> >>>  > On 4/11/19 8:17 PM, Tom Rini wrote:
> >>>  >> On Wed, Apr 10, 2019 at 04:46:28PM +0200, Marek Vasut
> wrote:
> >>>  >>
> >>>  >>> The following changes since commit
> >>>  >>> 3c99166441bf3ea325af2da83cfe65430b49c066:
> >>>  >>>
> >>>  >>>Prepare v2019.04 (2019-04-08 21:40:40 -0400)
> >>>  >>>
> >>>  >>> are available in the Git repository at:
> >>>  >>>
> >>>  >>>git://git.denx.de/u-boot-socfpga.git
> >>>   master
> >>>  >>>
> >>>  >>> for you to fetch changes up to
> >>>  >>> ef8679b24ec6226b7198e06747ff047a16030ca4:
> >>>  >>>
> >>>  >>>arm: dts: Stratix10: Add QSPI node (2019-04-09 13:11:06
> >>>  +0200)
> >>>  >>>
> >>>  >>
> >>>  >> Arg, sorry I didn't see this sooner:
> >>>  >> arm:  w+   socfpga_arria10
> >>>  >> +(socfpga_arria10)
> >>>  >> +(socfpga_arria10) WARNING: unmet direct dependencies
> >>>  detected for
> >>>  >> ALTERA_SDRAM
> >>>  >> +(socfpga_arria10)   Depends on [n]: RAM [=n] &&
> >>>  >> (TARGET_SOCFPGA_GEN5 [=n] || TARGET_SOCFPGA_ARRIA10 [=y])
> >>>  >> +(socfpga_arria10)   Selected by [y]:
> >>>  >> +(socfpga_arria10)   - TARGET_SOCFPGA_ARRIA10 [=y] && ARM
> >>> [=y] &&
> >>>  >> ARCH_SOCFPGA [=y]
> >>>  >
> >>>  > Is this coming from this PR or not ?
> >>>  
> >>>   Yes, this PR.  Top of tree + this PR only.
> >>>  >>>
> >>>  >>> It's not only top of tree + this PR, it also fails for pure
> >>>  >>> u-boot-socfpga/master.
> >>>  >>>
> >>>  >>> Seems like this bug has been introduced when I made the gen5
> >>> driver
> >>>  >>> depend
> >>>  >>> on RAM. Unfortunately, all the drivers use one Kconfig item
> >>>  (although
> >>>  >>> these
> >>>  >>> are totally different drivers) but now only gen5 depends on
> >>> RAM. Is
> >>>  >>> there
> >>>  >>> any Kconfig magic to fix this without duplicating the config
> >>> item
> >>>  >>> entries?
> >>>  >>
> >>>  >> I think you may want something more like:
> >>>  >> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> >>>  >> index 04a207c9403e..4a23e327dfb4 100644
> >>>  >> --- a/arch/arm/Kconfig
> >>>  >> +++ b/arch/arm/Kconfig
> >>>  >> @@ -821,14 +821,12 @@ config ARCH_SOCFPGA
> >>>  >>   select DM_SERIAL
> >>>  >>   select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5
> ||
> >>>  >> TARGET_SOCFPGA_ARRIA10
> >>>  >>   select OF_CONTROL
> >>>  >> -select RAM if TARGET_SOCFPGA_GEN5
> >>>  >>   select SPL_DM_RESET if DM_RESET
> >>>  >>   select SPL_DM_SERIAL
> >>>  >>   select SPL_LIBCOMMON_SUPPORT
> >>>  >>   select SPL_LIBGENERIC_SUPPORT
> >>>  >>   select SPL_NAND_SUPPORT if SPL_NAND_DENALI
> >>>  >>   select SPL_OF_CONTROL
> >>>  >> -select SPL_RAM if TARGET_SOCFPGA_GEN5
> >>>  >>   select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10
> >>>  >>   select SPL_SERIAL_SUPPORT
> >>>  >>   select SPL_WATCHDOG_SUPPORT
> >>>  >> diff --git a/drivers/ddr/altera/Kconfig
> >>> b/drivers/ddr/altera/Kconfig
> >>>  >> index 7370d4133a67..8f60b56eb848 100644
> >>>  >> --- a/drivers/ddr/altera/Kconfig
> >>>  >> +++ b/drivers/ddr/altera/Kconfig
> >>>  >> @@ -1,6 +1,7 @@
> >>>  >>   config ALTERA_SDRAM
> >>>  >>   bool "SoCFPGA DDR SDRAM driver"
> >>>  >> -depends on RAM
> >>>  >>   depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
> >>>  >> +select RAM if TARGET_SOCFPGA_GEN5
> >>>  >> +select SPL_RAM if TARGET_SOCFPGA_GEN5
> >>>  >>   help
> >>>  >> Enable DDR SDRAM controller for the SoCFPGA devices.
> >>>  >>
> >>>  >> But I didn't test anything other than socfpga_arria10/arria5 as
> >>>  >> building.
> >>>  >
> >>>  > Tom,
> >>>  > Thanks for the hint. I did just that and it works for me
> >>> (cyclone5).
> >>>  > As only this platform is affected by this patch, it should be
> >>> fine.
> >>>  >
> >>>  > Marek,
> >>>  

Re: [U-Boot] [PATCH v7 00/15] SiFive FU540 Support

[Kevin Hilman]

On Fri, Apr 19, 2019 at 1:38 PM Kevin Hilman  wrote:
>
> Atish Patra  writes:
>
> > On 4/18/19 4:16 PM, Kevin Hilman wrote:
> >> Atish Patra  writes:
> >>
> >>> On 4/18/19 12:15 PM, Kevin Hilman wrote:
>  Palmer, Anup,
> 
>  On Tue, Mar 12, 2019 at 1:55 AM Palmer Dabbelt  wrote:
> >
> > On Mon, 11 Mar 2019 07:33:25 PDT (-0700), bmeng...@gmail.com wrote:
> >> On Thu, Feb 14, 2019 at 7:58 AM Kevin Hilman  
> >> wrote:
> >>>
> >>> Kevin Hilman  writes:
> >>>
>  Hi Anup,
> 
>  Anup Patel  writes:
> 
> > This patchset adds SiFive Freedom Unleashed (FU540) support
> > to RISC-V U-Boot.
> >
> > The patches are based upon latest U-Boot source tree
> > (git://git.denx.de/u-boot.git) at commit id
> > dbe70c7d4e3d5c705a98d82952e05a591efd0683
> >
> > All drivers namely: SiFive PRCI, SiFive Serial, and Cadance
> > MACB Ethernet work fine on actual SiFive Unleashed board and
> > QEMU sifive_u machine.
> 
>  I tested u-boot networking (DHCP, TFTP) on my desk with a gigE switch
>  and it worked fine.  Then, I moved it to a lab with a 100Mb switch,
>  and DHCP doesn't work anymore.
> >>>
> >>> And to be clear, neither does TFTP if setting static
> >>> ipaddr/netmask/gatewayip etc.
> >>
> >> Sound to me a bug of the GEM driver on SiFive FU540 board.
> >
> > It looks to me like u-boot is missing a driver for the GEM clockmux in 
> > the
> > FU540.  This is necessary to switch between the clock for 1G operation 
> > and 100M
> > operation.  Without this you'll just get whatever clock was set up by 
> > the
> > previous boot stage (or even worse, reset).
> 
>  Anyone know if this is fixed in u-boot yet?  I've yet to try the
>  latest mainline u-boot, but will if if it's expected to work.
> 
> >>>
> >>> I have not seen a GEM driver for FU540 board. So I guess it is not fixed
> >>> it. Is it a blocker for setting up kernelCI for RISC-V ?
> >>
> >> Not really, that's only one of the remaining issue. For now, I have
> >> connected it to a gigE switch, so u-boot networking is working.
> >>
> >> But, the bigger blocker for kernelCI right now is not having
> >> out-of-the-box mainline support.  Mainline is still missing a serial
> >> driver, and a handful of Kconfig options in the default defconfig to
> >> make things boot[1].
> >>
> >> If I use the 'v5.1-rc4_unleashed' from your github, along with my
> >> kconfig fragment[1], things are working well.
> >>
> >> But in order to automate this for kernelCI, we need all of that
> >> upstream.
> >>
> > Yeah. I agree. We need upstream drivers sooner than later.
> > I believe SiFive Team (Paul & co) are working on this.
> >
> > He recently sent updated version of driver patches to the linux-riscv
> > mailing list.
>
> Yes, I'm trying to test all of those (hence our other discussion on the
> DT thread)
>
> >> [1] This is the config fragment I'm adding to the default defconfig in
> >> mainline.  I'm not exactly sure which ones are absolutely need for basic
> >> boot.
> >>
> >> CONFIG_SERIAL_SIFIVE=y
> >> CONFIG_SERIAL_SIFIVE_CONSOLE=y
> >> CONFIG_SIFIVE_PLIC=y
> >> CONFIG_SPI=y
> >> CONFIG_SPI_SIFIVE=y
> >> CONFIG_GPIOLIB=y
> >> CONFIG_GPIO_SIFIVE=y
> >> CONFIG_PWM_SIFIVE=y
> >> CONFIG_CLK_U54_PRCI=y
> >> CONFIG_CLK_GEMGXL_MGMT=y
> >>
> >
> > My working config has enabled all of the above except CONFIG_PWM_SIFIVE.
> > I have not played around the config that much to find out absolute
> > minimum config. So this may not be the answer you are looking for :).
>
> At least for kernelCI, we'll need to figure that out and get it upstream
> if we want to boot test these.

Oh, and one other u-boot question.

Any reason you didn't enable `booti` support in riscv u-boot?  That
would allow you to boot the Image (or Image.gz) directly, instead of
the need to create a special image with u-boot header (uImage)

Kevin
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Re: [U-Boot] [PATCH v7 00/15] SiFive FU540 Support

[Kevin Hilman]

Atish Patra  writes:

> On 4/18/19 4:16 PM, Kevin Hilman wrote:
>> Atish Patra  writes:
>> 
>>> On 4/18/19 12:15 PM, Kevin Hilman wrote:
 Palmer, Anup,

 On Tue, Mar 12, 2019 at 1:55 AM Palmer Dabbelt  wrote:
>
> On Mon, 11 Mar 2019 07:33:25 PDT (-0700), bmeng...@gmail.com wrote:
>> On Thu, Feb 14, 2019 at 7:58 AM Kevin Hilman  
>> wrote:
>>>
>>> Kevin Hilman  writes:
>>>
 Hi Anup,

 Anup Patel  writes:

> This patchset adds SiFive Freedom Unleashed (FU540) support
> to RISC-V U-Boot.
>
> The patches are based upon latest U-Boot source tree
> (git://git.denx.de/u-boot.git) at commit id
> dbe70c7d4e3d5c705a98d82952e05a591efd0683
>
> All drivers namely: SiFive PRCI, SiFive Serial, and Cadance
> MACB Ethernet work fine on actual SiFive Unleashed board and
> QEMU sifive_u machine.

 I tested u-boot networking (DHCP, TFTP) on my desk with a gigE switch
 and it worked fine.  Then, I moved it to a lab with a 100Mb switch,
 and DHCP doesn't work anymore.
>>>
>>> And to be clear, neither does TFTP if setting static
>>> ipaddr/netmask/gatewayip etc.
>>
>> Sound to me a bug of the GEM driver on SiFive FU540 board.
>
> It looks to me like u-boot is missing a driver for the GEM clockmux in the
> FU540.  This is necessary to switch between the clock for 1G operation 
> and 100M
> operation.  Without this you'll just get whatever clock was set up by the
> previous boot stage (or even worse, reset).

 Anyone know if this is fixed in u-boot yet?  I've yet to try the
 latest mainline u-boot, but will if if it's expected to work.

>>>
>>> I have not seen a GEM driver for FU540 board. So I guess it is not fixed
>>> it. Is it a blocker for setting up kernelCI for RISC-V ?
>> 
>> Not really, that's only one of the remaining issue. For now, I have
>> connected it to a gigE switch, so u-boot networking is working.
>> 
>> But, the bigger blocker for kernelCI right now is not having
>> out-of-the-box mainline support.  Mainline is still missing a serial
>> driver, and a handful of Kconfig options in the default defconfig to
>> make things boot[1].
>> 
>> If I use the 'v5.1-rc4_unleashed' from your github, along with my
>> kconfig fragment[1], things are working well.
>> 
>> But in order to automate this for kernelCI, we need all of that
>> upstream.
>> 
> Yeah. I agree. We need upstream drivers sooner than later.
> I believe SiFive Team (Paul & co) are working on this.
>
> He recently sent updated version of driver patches to the linux-riscv 
> mailing list.

Yes, I'm trying to test all of those (hence our other discussion on the
DT thread)

>> [1] This is the config fragment I'm adding to the default defconfig in
>> mainline.  I'm not exactly sure which ones are absolutely need for basic
>> boot.
>> 
>> CONFIG_SERIAL_SIFIVE=y
>> CONFIG_SERIAL_SIFIVE_CONSOLE=y
>> CONFIG_SIFIVE_PLIC=y
>> CONFIG_SPI=y
>> CONFIG_SPI_SIFIVE=y
>> CONFIG_GPIOLIB=y
>> CONFIG_GPIO_SIFIVE=y
>> CONFIG_PWM_SIFIVE=y
>> CONFIG_CLK_U54_PRCI=y
>> CONFIG_CLK_GEMGXL_MGMT=y
>> 
>
> My working config has enabled all of the above except CONFIG_PWM_SIFIVE.
> I have not played around the config that much to find out absolute 
> minimum config. So this may not be the answer you are looking for :).

At least for kernelCI, we'll need to figure that out and get it upstream
if we want to boot test these.

Kevin
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Re: [U-Boot] [PATCH 4/4] ARM: socfpga: Add support for selecting bridges in bridge command

[Simon Goldschmidt]

On 17.04.19 22:15, Marek Vasut wrote:

Add optional "mask" argument to the SoCFPGA bridge command, to select
which bridges should be enabled/disabled. This allows the user to avoid
enabling bridges which are not connected into the FPGA fabric. Default
behavior is to enable/disable all bridges.


So does this change the command? Seems like leaving away the new 'mask' 
argument would now lead to enabling all bridges by overwriting whatever 
the handoff values were before?


Regards,
Simon



Signed-off-by: Marek Vasut 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Simon Goldschmidt 
Cc: Tien Fong Chee 
---
  arch/arm/mach-socfpga/include/mach/misc.h |  2 +-
  arch/arm/mach-socfpga/misc.c  | 17 +++--
  arch/arm/mach-socfpga/misc_arria10.c  |  2 +-
  arch/arm/mach-socfpga/misc_gen5.c | 12 +++-
  arch/arm/mach-socfpga/misc_s10.c  |  2 +-
  5 files changed, 25 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/misc.h 
b/arch/arm/mach-socfpga/include/mach/misc.h
index 86d5d2b62b..c3ca8cdf3b 100644
--- a/arch/arm/mach-socfpga/include/mach/misc.h
+++ b/arch/arm/mach-socfpga/include/mach/misc.h
@@ -39,6 +39,6 @@ void socfpga_init_security_policies(void);
  void socfpga_sdram_remap_zero(void);
  #endif
  
-void do_bridge_reset(int enable);

+void do_bridge_reset(int enable, unsigned int mask);
  
  #endif /* _MISC_H_ */

diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index ec8339e045..e1ea8eb73e 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -126,17 +126,22 @@ int arch_cpu_init(void)
  #ifndef CONFIG_SPL_BUILD
  static int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const 
argv[])
  {
-   if (argc != 2)
+   unsigned int mask = ~0;
+
+   if (argc < 2 || argc > 3)
return CMD_RET_USAGE;
  
  	argv++;
  
+	if (argc == 3)

+   mask = simple_strtoul(argv[1], NULL, 16);
+
switch (*argv[0]) {
case 'e':   /* Enable */
-   do_bridge_reset(1);
+   do_bridge_reset(1, mask);
break;
case 'd':   /* Disable */
-   do_bridge_reset(0);
+   do_bridge_reset(0, mask);
break;
default:
return CMD_RET_USAGE;
@@ -145,10 +150,10 @@ static int do_bridge(cmd_tbl_t *cmdtp, int flag, int 
argc, char * const argv[])
return 0;
  }
  
-U_BOOT_CMD(bridge, 2, 1, do_bridge,

+U_BOOT_CMD(bridge, 3, 1, do_bridge,
   "SoCFPGA HPS FPGA bridge control",
-  "enable  - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
-  "bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA 
bridges\n"
+  "enable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA 
bridges\n"
+  "bridge disable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA 
bridges\n"
   ""
  );
  
diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c

index 63b8c75d31..2e2a40b65d 100644
--- a/arch/arm/mach-socfpga/misc_arria10.c
+++ b/arch/arm/mach-socfpga/misc_arria10.c
@@ -115,7 +115,7 @@ int print_cpuinfo(void)
  }
  #endif
  
-void do_bridge_reset(int enable)

+void do_bridge_reset(int enable, unsigned int mask)
  {
if (enable)
socfpga_reset_deassert_bridges_handoff();
diff --git a/arch/arm/mach-socfpga/misc_gen5.c 
b/arch/arm/mach-socfpga/misc_gen5.c
index 6e11ba6cb2..7876953595 100644
--- a/arch/arm/mach-socfpga/misc_gen5.c
+++ b/arch/arm/mach-socfpga/misc_gen5.c
@@ -249,9 +249,19 @@ static void socfpga_sdram_apply_static_cfg(void)
: : "r"(val), "r"(_ctrl->static_cfg) : "memory", "cc");
  }
  
-void do_bridge_reset(int enable)

+void do_bridge_reset(int enable, unsigned int mask)
  {
+   int i;
+
if (enable) {
+   socfpga_bridges_set_handoff_regs(!(mask & BIT(0)),
+!(mask & BIT(1)),
+!(mask & BIT(2)));
+   for (i = 0; i < 2; i++) {/* Reload SW setting cache */
+   iswgrp_handoff[i] =
+   readl(_regs->iswgrp_handoff[i]);
+   }
+
writel(iswgrp_handoff[2], _regs->fpgaintfgrp_module);
socfpga_sdram_apply_static_cfg();
writel(iswgrp_handoff[3], _ctrl->fpgaport_rst);
diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c
index 113eace650..60c96090ce 100644
--- a/arch/arm/mach-socfpga/misc_s10.c
+++ b/arch/arm/mach-socfpga/misc_s10.c
@@ -150,7 +150,7 @@ int arch_early_init_r(void)
return 0;
  }
  
-void do_bridge_reset(int enable)

+void do_bridge_reset(int enable, unsigned int mask)
  {
socfpga_bridges_reset(enable);
  }


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Re: [U-Boot] [PATCH 3/4] ARM: socfpga: Fully unmap the FPGA bridges from L3 space

[Simon Goldschmidt]

On 17.04.19 22:15, Marek Vasut wrote:

Instead of just putting the bridges into reset, fully remove the bridges
from the L3 main bridge space when disabling them by clearing bits in
NIC-301 remap register. Moreover, only touch the 3 LSbits in brgmodrst
register as the rest of the bits are undefined.

Signed-off-by: Marek Vasut 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Simon Goldschmidt 
Cc: Tien Fong Chee 


Reviewed-by: Simon Goldschmidt 


---
  arch/arm/mach-socfpga/reset_manager_gen5.c | 3 ++-
  1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-socfpga/reset_manager_gen5.c 
b/arch/arm/mach-socfpga/reset_manager_gen5.c
index 66af924485..89a384b59c 100644
--- a/arch/arm/mach-socfpga/reset_manager_gen5.c
+++ b/arch/arm/mach-socfpga/reset_manager_gen5.c
@@ -103,7 +103,8 @@ void socfpga_bridges_reset(int enable)
  
  	if (enable) {

/* brdmodrst */
-   writel(0x, _manager_base->brg_mod_reset);
+   writel(0x7, _manager_base->brg_mod_reset);
+   writel(L3REGS_REMAP_OCRAM_MASK, SOCFPGA_L3REGS_ADDRESS);
} else {
socfpga_bridges_set_handoff_regs(false, false, false);
  


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Re: [U-Boot] [PATCH 2/4] ARM: socfpga: Disable bridges in SPL unless booting from FPGA

[Simon Goldschmidt]

On 17.04.19 22:15, Marek Vasut wrote:

Disable bridges between L3 Main switch and FPGA unless booting
from FPGA and keep them disabled to prevent glitches and possible
hangs of the L3 Main switch.

The current version of the code could have enabled the bridges
between the L3 Main switch and FPGA for a short period of time
in board_init_f() in case the FPGA was programmed and then again
disable them at the end of board_init_f(). Replace this with a
code which only sets up the handoff registers and let the user
enable the bridges later on.

Signed-off-by: Marek Vasut 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Simon Goldschmidt 
Cc: Tien Fong Chee 


Reviewed-by: Simon Goldschmidt 


---
  arch/arm/mach-socfpga/spl_gen5.c | 5 +
  1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c
index 45382b549a..aa88f2cf3e 100644
--- a/arch/arm/mach-socfpga/spl_gen5.c
+++ b/arch/arm/mach-socfpga/spl_gen5.c
@@ -188,7 +188,7 @@ void board_init_f(ulong dummy)
  
  	/* De-assert reset for peripherals and bridges based on handoff */

reset_deassert_peripherals_handoff();
-   socfpga_bridges_reset(0);
+   socfpga_bridges_set_handoff_regs(true, true, true);
  
  	debug("Unfreezing/Thaw all I/O banks\n");

/* unfreeze / thaw all IO banks */
@@ -228,7 +228,4 @@ void board_init_f(ulong dummy)
puts("SDRAM size check failed!\n");
hang();
}
-
-   if (!socfpga_is_booting_from_fpga())
-   socfpga_bridges_reset(1);
  }


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Re: [U-Boot] [PATCH 1/4] ARM: socfpga: Factor out handoff register configuration

[Simon Goldschmidt]

On 17.04.19 22:15, Marek Vasut wrote:

Factor out the code for programming preloader handoff register values,
the ISWGRP Handoff 0 and 1. These registers later control which bridges
are enabled by the "bridge" command on Gen5 devices.

Signed-off-by: Marek Vasut 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Simon Goldschmidt 
Cc: Tien Fong Chee 
---
  .../include/mach/reset_manager_gen5.h |  1 +
  arch/arm/mach-socfpga/reset_manager_gen5.c| 25 +--
  2 files changed, 24 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h 
b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
index dd58922cec..5e490d182e 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
@@ -9,6 +9,7 @@
  #include 
  
  void reset_deassert_peripherals_handoff(void);

+void socfpga_bridges_set_handoff_regs(bool h2f, bool lwh2f, bool f2h);
  void socfpga_bridges_reset(int enable);
  
  struct socfpga_reset_manager {

diff --git a/arch/arm/mach-socfpga/reset_manager_gen5.c 
b/arch/arm/mach-socfpga/reset_manager_gen5.c
index 25baef79bc..66af924485 100644
--- a/arch/arm/mach-socfpga/reset_manager_gen5.c
+++ b/arch/arm/mach-socfpga/reset_manager_gen5.c
@@ -73,6 +73,28 @@ void reset_deassert_peripherals_handoff(void)
  #define L3REGS_REMAP_HPS2FPGA_MASK0x08
  #define L3REGS_REMAP_OCRAM_MASK   0x01
  
+void socfpga_bridges_set_handoff_regs(bool h2f, bool lwh2f, bool f2h)

+{
+   u32 brgmask = 0x0;
+   u32 l3rmask = L3REGS_REMAP_OCRAM_MASK;
+
+   if (h2f)
+   brgmask |= BIT(0);
+   else
+   l3rmask |= L3REGS_REMAP_HPS2FPGA_MASK;
+
+   if (lwh2f)
+   brgmask |= BIT(1);
+   else
+   l3rmask |= L3REGS_REMAP_LWHPS2FPGA_MASK;
+
+   if (f2h)
+   brgmask |= BIT(2);
+
+   writel(brgmask, _regs->iswgrp_handoff[0]);
+   writel(l3rmask, _regs->iswgrp_handoff[1]);
+}
+
  void socfpga_bridges_reset(int enable)
  {
const u32 l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK |


'l3mask' seems unused after this change, no?

Other than that:
Reviewed-by: Simon Goldschmidt 


@@ -83,8 +105,7 @@ void socfpga_bridges_reset(int enable)
/* brdmodrst */
writel(0x, _manager_base->brg_mod_reset);
} else {
-   writel(0, _regs->iswgrp_handoff[0]);
-   writel(l3mask, _regs->iswgrp_handoff[1]);
+   socfpga_bridges_set_handoff_regs(false, false, false);
  
  		/* Check signal from FPGA. */

if (!fpgamgr_test_fpga_ready()) {


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[U-Boot] [PATCH v2 2/2] warp7: Switch to DM USB

[Pierre-Jean Texier]

This commit switches to DM USB for warp7 and warp7_bl33 defconfigs.

Signed-off-by: Pierre-Jean Texier 
Signed-off-by: Joris Offouga 
---

Changes in v2:
- Split patch
- Removed unused header file 

 arch/arm/dts/imx7s-warp.dts  | 1 +
 board/warp7/warp7.c  | 6 --
 configs/warp7_bl33_defconfig | 1 +
 configs/warp7_defconfig  | 1 +
 4 files changed, 3 insertions(+), 6 deletions(-)

diff --git a/arch/arm/dts/imx7s-warp.dts b/arch/arm/dts/imx7s-warp.dts
index 4d87348..db5ef67 100644
--- a/arch/arm/dts/imx7s-warp.dts
+++ b/arch/arm/dts/imx7s-warp.dts
@@ -19,6 +19,7 @@
 
aliases {
mmc0 = 
+   usb0 = 
};
 
chosen {
diff --git a/board/warp7/warp7.c b/board/warp7/warp7.c
index 2882dc9..134a6c9 100644
--- a/board/warp7/warp7.c
+++ b/board/warp7/warp7.c
@@ -14,7 +14,6 @@
 #include 
 #include 
 #include 
-#include 
 #include 
 #include 
 #include 
@@ -128,11 +127,6 @@ int checkboard(void)
return 0;
 }
 
-int board_usb_phy_mode(int port)
-{
-   return USB_INIT_DEVICE;
-}
-
 int board_late_init(void)
 {
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
diff --git a/configs/warp7_bl33_defconfig b/configs/warp7_bl33_defconfig
index d34f76b..300dc38 100644
--- a/configs/warp7_bl33_defconfig
+++ b/configs/warp7_bl33_defconfig
@@ -41,6 +41,7 @@ CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_SPECIFY_CONSOLE_INDEX=y
 CONFIG_DM_SERIAL=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_MXC_USB_OTG_HACTIVE=y
 CONFIG_USB_GADGET=y
diff --git a/configs/warp7_defconfig b/configs/warp7_defconfig
index ae424ab..cabddad 100644
--- a/configs/warp7_defconfig
+++ b/configs/warp7_defconfig
@@ -51,6 +51,7 @@ CONFIG_SPECIFY_CONSOLE_INDEX=y
 CONFIG_DM_SERIAL=y
 CONFIG_OPTEE=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_MXC_USB_OTG_HACTIVE=y
 CONFIG_USB_GADGET=y
-- 
2.7.4

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[U-Boot] [PATCH v2 1/2] warp7: Switch to DM Serial

[Pierre-Jean Texier]

This commit switches to DM SERIAL for warp7 and warp7_bl33 defconfigs.

Signed-off-by: Pierre-Jean Texier 
Signed-off-by: Joris Offouga 
---

Changes in v2:
- Split patch
- Removed CONFIG_MXC_UART_BASE from config file

 arch/arm/dts/imx7s-warp.dts  | 4 
 configs/warp7_bl33_defconfig | 2 ++
 configs/warp7_defconfig  | 2 ++
 include/configs/warp7.h  | 2 --
 4 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/imx7s-warp.dts b/arch/arm/dts/imx7s-warp.dts
index d28b7ec..4d87348 100644
--- a/arch/arm/dts/imx7s-warp.dts
+++ b/arch/arm/dts/imx7s-warp.dts
@@ -21,6 +21,10 @@
mmc0 = 
};
 
+   chosen {
+   stdout-path = 
+   };
+
gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <_gpio>;
diff --git a/configs/warp7_bl33_defconfig b/configs/warp7_bl33_defconfig
index 6eaf152..d34f76b 100644
--- a/configs/warp7_bl33_defconfig
+++ b/configs/warp7_bl33_defconfig
@@ -38,6 +38,8 @@ CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_PFUZE100=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_DM_SERIAL=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_MXC_USB_OTG_HACTIVE=y
diff --git a/configs/warp7_defconfig b/configs/warp7_defconfig
index 28aa06f..ae424ab 100644
--- a/configs/warp7_defconfig
+++ b/configs/warp7_defconfig
@@ -47,6 +47,8 @@ CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_PFUZE100=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_DM_SERIAL=y
 CONFIG_OPTEE=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/include/configs/warp7.h b/include/configs/warp7.h
index 043f286..2bbf691 100644
--- a/include/configs/warp7.h
+++ b/include/configs/warp7.h
@@ -24,8 +24,6 @@
 #endif
 #endif
 
-#define CONFIG_MXC_UART_BASE   UART1_IPS_BASE_ADDR
-
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN  (35 * SZ_1M)
 
-- 
2.7.4

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[U-Boot] [PATCH v2 0/2] Convert WaRP7 to DM_USB and DM_SERIAL

[Pierre-Jean Texier]

This series convert the WaRP7 to the following DM:
-CONFIG_DM_USB
-CONFIG_DM_SERIAL

Change in v2: 
- Now split in two distinct patches (DM_USB & DM_SERIAL)
 
Pierre-Jean Texier (2):
  warp7: Switch to DM Serial
  warp7: Switch to DM USB

 arch/arm/dts/imx7s-warp.dts  | 5 +
 board/warp7/warp7.c  | 6 --
 configs/warp7_bl33_defconfig | 3 +++
 configs/warp7_defconfig  | 3 +++
 include/configs/warp7.h  | 2 --
 5 files changed, 11 insertions(+), 8 deletions(-)

-- 
2.7.4

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[U-Boot] [RFT PATCH v2 2/2] sunxi: Enable EMAC on the Bananapi M3

[Chen-Yu Tsai]

From: Chen-Yu Tsai 

The Bananapi M3 has an RTL8211E PHY connected to the EMAC using
RGMII. The PHY is powered by DCDC1 through SW @ 3.3V.

The board is designed to use 3.3V with RGMII, instead of the standard
reduced voltage of 2.5V we see everywhere. DLDO3, which provides the
I/O voltages, is raised to match.

This patch enables the EMAC and Realtek PHY drivers in the defconfig.
The device tree file already has the EMAC enabled.

Signed-off-by: Chen-Yu Tsai 

---

Changes in v2:
  - Dropped clk/reset related changes in favor of DM CLK / RESET support
  - Raised DLDO3 for RGMII I/O on Bananapi M3 to 3.3V per design

 configs/Sinovoip_BPI_M3_defconfig | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/configs/Sinovoip_BPI_M3_defconfig 
b/configs/Sinovoip_BPI_M3_defconfig
index 79743a9c9a51..b9ab00cb8a29 100644
--- a/configs/Sinovoip_BPI_M3_defconfig
+++ b/configs/Sinovoip_BPI_M3_defconfig
@@ -21,8 +21,10 @@ CONFIG_CONSOLE_MUX=y
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-bananapi-m3"
+CONFIG_PHY_REALTEK=y
+CONFIG_SUN8I_EMAC=y
 CONFIG_AXP_DCDC5_VOLT=1200
-CONFIG_AXP_DLDO3_VOLT=2500
+CONFIG_AXP_DLDO3_VOLT=3300
 CONFIG_AXP_SW_ON=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y
-- 
2.20.1

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[U-Boot] [RFT PATCH v2 0/2] sunxi: Enable EMAC on A83T boards using Realtek RTL8211E PHY

[Chen-Yu Tsai]

From: Chen-Yu Tsai 

Hi everyone,

This series enables EMAC (Ethernet controller) on two A83T boards,
the Cubietruck Plus and Bananapi M3.

This series is now based on sunxi/next, which has patches that convert
sun8i-emac to use the common CLK and DM_RESET framework.

The two patches enable the sun8i-emac and Realtek PHY driver in their
respective defconfigs. The device trees already have the EMAC enabled.
For the Bananapi M3, the regulator providing the I/O voltages is raised
to 3.3V.

As I currently do not have access to my boards, testing by others is
requested.

Regards
ChenYu

Changes in v2:
  - Dropped clk/reset related changes in favor of DM CLK / RESET support
  - Raised DLDO3 for RGMII I/O on Bananapi M3 to 3.3V per design

Chen-Yu Tsai (2):
  sunxi: Enable EMAC on the Cubietruck Plus
  sunxi: Enable EMAC on the Bananapi M3

 configs/Cubietruck_plus_defconfig | 2 ++
 configs/Sinovoip_BPI_M3_defconfig | 4 +++-
 2 files changed, 5 insertions(+), 1 deletion(-)

-- 
2.20.1

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[U-Boot] [RFT PATCH v2 1/2] sunxi: Enable EMAC on the Cubietruck Plus

[Chen-Yu Tsai]

From: Chen-Yu Tsai 

The Cubietruck Plus has an RTL8211E PHY connected to the EMAC using
RGMII. The PHY is powered by DLDO4 @ 3.3V, while the I/O pins are
powered by DLDO3 @ 2.5V.

This patch enables the EMAC and Realtek PHY drivers in the defconfig.
The device tree file already has the EMAC enabled.

Signed-off-by: Chen-Yu Tsai 
---

Changes in v2: None

 configs/Cubietruck_plus_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/configs/Cubietruck_plus_defconfig 
b/configs/Cubietruck_plus_defconfig
index 869bffcfca0c..044af12779c6 100644
--- a/configs/Cubietruck_plus_defconfig
+++ b/configs/Cubietruck_plus_defconfig
@@ -20,6 +20,8 @@ CONFIG_CONSOLE_MUX=y
 # CONFIG_SPL_DOS_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-cubietruck-plus"
+CONFIG_PHY_REALTEK=y
+CONFIG_SUN8I_EMAC=y
 CONFIG_AXP_DLDO3_VOLT=2500
 CONFIG_AXP_DLDO4_VOLT=3300
 CONFIG_AXP_FLDO1_VOLT=1200
-- 
2.20.1

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[U-Boot] [PULL] u-boot-stm32 for v2019.07-rc1​ (round 2)

[Patrice CHOTARD]

Hi Tom

Please find the pull request for STM32 round 2

The following changes since commit 1f4ae66eaab29bfb5d1eb44996f7826c9cd01ed1:

  Merge tag 'arc-for-2019.07' of git://git.denx.de/u-boot-arc
(2019-04-18 12:12:16 -0400)

are available in the git repository at:


  https://github.com/pchotard/u-boot.git tags/u-boot-stm32-mcu-20190419

for you to fetch changes up to 5b37873ff04f082efa0a74ba04185599ccec165b:

  mmc: stm32_sdmmc2: Fix r1b timeout issue (2019-04-19 17:19:32 +0200)


STM32 MCUs update:
_ DT rework and alignment with DT kernel v4.20
_ mmc: arm_pl180_mmci: Synchronize compatible with kernel v4.20
_ mmc: stm32_sdmmc2: Synchronize properties with kernel v4.20
_ configs: update for F746/769 boards


Christophe Kerello (1):
  mmc: stm32_sdmmc2: Fix r1b timeout issue

Patrice Chotard (15):
  ARM:dts: stm32: sort nodes by alphabetical order in f4 u-boot files
  ARM: dts: stm32: Sync DT files with v4.20 kernel for stm32f4
  ARM: dts: stm32: Migrate U-boot nodes to U-boot DT files for stm32f7
  ARM: dts: stm32: Sync DT with v4.20 kernel for stm32f7
  ARM: dts: Migrate U-boot nodes to U-boot DT files for stm32h7
  ARM: dts: stm32: Sync DT with v4.20 kernel for stm32h7
  ARM: dts: stm32: Restore old usart1 clock bindings for stm32f7
  pinctrl: stm32: Add st,stm32f769-pinctrl compatible string
  mmc: arm_pl180_mmci: Sync compatible with kernel
  configs: stm32f746-disco: update EXTRA_ENV_SETTINGS
  configs: stm32f746-disco: enable CONFIG_DISTRO_DEFAULTS
  configs: stm32f746-disco: Enable SPI_FLASH_MACRONIX
  board: stm32f746-disco: Get MII/RMII phy_mode from DT
  ARM: dts: stm32: Update sdmmc binding for stm32h743i-eval
  ARM: dts: stm32: Update sdmmc binding for stm32mp157c-ed1

Patrick Delaunay (1):
  mmc: stm32_sdmmc2: Update DT properties with v4.19 bindings

 arch/arm/dts/stm32746g-eval-u-boot.dtsi |  188 +++
 arch/arm/dts/stm32746g-eval.dts |  222 +---
 arch/arm/dts/stm32f4-pinctrl.dtsi   |   27 +-
 arch/arm/dts/stm32f429-disco-u-boot.dtsi|   18 +-
 arch/arm/dts/stm32f429-disco.dts|4 +-
 arch/arm/dts/stm32f429-pinctrl.dtsi |3 +-
 arch/arm/dts/stm32f429.dtsi |   33 +-
 arch/arm/dts/stm32f469-disco-u-boot.dtsi|   46 +-
 arch/arm/dts/stm32f469-disco.dts|   86 +-
 arch/arm/dts/stm32f469-pinctrl.dtsi |3 +-
 arch/arm/dts/stm32f469.dtsi |   19 +
 arch/arm/dts/stm32f7-pinctrl.dtsi   |  289 
 arch/arm/dts/stm32f7-u-boot.dtsi|  139 +-
 arch/arm/dts/stm32f746-disco-u-boot.dtsi|  251 
 arch/arm/dts/stm32f746-disco.dts|  279 +---
 arch/arm/dts/stm32f746-pinctrl.dtsi |   11 +
 arch/arm/dts/stm32f746.dtsi |  747 +++
 arch/arm/dts/stm32f769-disco-u-boot.dtsi|  165 +++
 arch/arm/dts/stm32f769-disco.dts|  236 +---
 arch/arm/dts/stm32f769-pinctrl.dtsi |   11 +
 arch/arm/dts/stm32h7-u-boot.dtsi|  197 ++-
 arch/arm/dts/stm32h743-pinctrl.dtsi |  160 +--
 arch/arm/dts/stm32h743.dtsi |  462 ++-
 arch/arm/dts/stm32h743i-disco-u-boot.dtsi   |   11 +
 arch/arm/dts/stm32h743i-disco.dts   |   44 +-
 arch/arm/dts/stm32h743i-eval-u-boot.dtsi|   12 +
 arch/arm/dts/stm32h743i-eval.dts|   79 +-
 arch/arm/dts/stm32mp157c-ed1.dts|   10 +-
 board/st/stm32f746-disco/stm32f746-disco.c  |   23 +-
 configs/stm32f746-disco_defconfig   |   14 +-
 drivers/mmc/arm_pl180_mmci.c|   14 +-
 drivers/mmc/arm_pl180_mmci.h|3 +-
 drivers/mmc/stm32_sdmmc2.c  |   67 +-
 drivers/pinctrl/pinctrl_stm32.c |1 +
 include/configs/stm32f746-disco.h   |   22 +-
 include/dt-bindings/clock/stm32fx-clock.h   |7 +-
 include/dt-bindings/pinctrl/stm32f746-pinfunc.h | 1341 ---
 include/dt-bindings/pinctrl/stm32h7-pinfunc.h   | 1612
---
 38 files changed, 2740 insertions(+), 4116 deletions(-)
 create mode 100644 arch/arm/dts/stm32746g-eval-u-boot.dtsi
 create mode 100644 arch/arm/dts/stm32f469.dtsi
 create mode 100644 arch/arm/dts/stm32f7-pinctrl.dtsi
 create mode 100644 arch/arm/dts/stm32f746-disco-u-boot.dtsi
 create mode 100644 arch/arm/dts/stm32f746-pinctrl.dtsi
 create mode 100644 arch/arm/dts/stm32f769-disco-u-boot.dtsi
 create mode 100644 arch/arm/dts/stm32f769-pinctrl.dtsi
 create mode 100644 arch/arm/dts/stm32h743i-disco-u-boot.dtsi
 create mode 100644 arch/arm/dts/stm32h743i-eval-u-boot.dtsi
 delete mode 100644 include/dt-bindings/pinctrl/stm32f746-pinfunc.h
 delete mode 100644 include/dt-bindings/pinctrl/stm32h7

Re: [U-Boot] [PATCH] phycore-pcl060: U-boot support for Phytec phyCORE PCL060

[Marek Vasut]

On 4/19/19 5:06 PM, Parthiban Nallathambi wrote:
> Hello Marek,
> 
> On 4/19/19 3:35 PM, Marek Vasut wrote:
>> On 4/19/19 3:18 PM, Parthiban Nallathambi wrote:
>>
>> Hi,
>>
>> [...]
>>
> diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
> index d29f1ca0b5..9336439340 100644
> --- a/arch/arm/mach-omap2/Kconfig
> +++ b/arch/arm/mach-omap2/Kconfig
> @@ -186,6 +186,7 @@ source "board/ti/am43xx/Kconfig"
>  source "board/ti/am335x/Kconfig"
>  source "board/compulab/cm_t335/Kconfig"
>  source "board/compulab/cm_t43/Kconfig"
> +source "board/phytec/phycore_pcl060/Kconfig"

 Here [1] it says the name of the SoM is PCM-060 , what is PCL-060 ?

 [1]
 https://www.phytec.eu/product-eu/system-on-modules/phycore-am335x-download/
  [...]
>>>
>>> This differs only by the connector. PCM variants are pluggable and PCL 
>>> variants
>>> are direct soliderable to the carrier board.
>>>
>>> Copied from [1]:
>>> The PCL-060 System On Module is a connector-less, BGA style variant of the
>>> PCM-060/phyCORE-AM335x R2 SOM. Unlike traditional Phytec SOM products that 
>>> support
>>> high density connectors, the PCL-060 SOM is directly soldered down to the
>>> phyBOARD-Wega AM335x using Phytec's Direct Solder Connect technology (DSC). 
>>> This
>>> solution offers an ultra-low cost Single Board Computer for the AM335x 
>>> processor, while
>>> maintaining most of the advantages of the SOM concept.
>>>
>>> [1] 
>>> https://www.phytec.de/fileadmin/user_upload/downloads/Manuals/L-845e_1.pdf
>>
>> Ah damn, this looks like a consistency problem is coming up. We have
>> multiple PCM* SoMs in U-Boot, one PCL* SoM and now another PCL/PCM SoM.
>> But the PCL063 isn't even manufactured in variant with connectors, so I
>> guess we can ignore that one.
>>
>> I wonder whether we should stick to PCM* for all of the Phytec SoMs for
>> consistency sake and document that PCL060 is also supported or maybe
>> there's a better way ?
> 
> Does PCX/PCx makes sense? But we have the same problem with variscite [1] 
> SoM's
> (either SODIMM or solderable).
> 
> [1] https://lists.denx.de/pipermail/u-boot/2019-April/365667.html

PCX would introduce another option, in addition to PCM/PCL, one which
cannot be easily found on the internet, so I'd like to avoid that. I
am banking toward the sticking with PCM where possible (simply because
that's what $searchengine spits out first when you look for that SoM,
and because we already have plenty of PCM-nnn SoMs), but maybe someone
has a better idea .

-- 
Best regards,
Marek Vasut
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Re: [U-Boot] [GIT] Pull request: u-boot-dfu (14.04.2019)

[Marek Vasut]

On 4/19/19 4:55 PM, Lukasz Majewski wrote:
> Hi Marek,
> 
>> On 4/19/19 1:23 PM, Lukasz Majewski wrote:
>>> Dear Marek,
>>>
>>> The following changes since commit
>>> 1f4ae66eaab29bfb5d1eb44996f7826c9cd01ed1:  
>>
>> [...]
>>
>>> Peng Fan (1):
>>>   MLK-12883 usb: limit USB_MAX_XFER_BLK to 256  
>>
>> NAK, this patch is not for gadget and is wrong, cfr. my comment on V3.
>> Please drop it and respin the PR.
>>
> 
> Interesting as I was not on the v3 CC
> 
> Anyway, I will prepare next PR.

Seems the CC was a bit random with each version.

Thanks

-- 
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 6/6] configs: stm32mp15: Enable Ethernet feature

[Patrick DELAUNAY]

Hi Christophe,

> 
> This allows to enable Ethernet and use driver for Synopsys Ethernet QoS device
> 
> Signed-off-by: Christophe Roullier 
> ---
> 
>  configs/stm32mp15_basic_defconfig | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/configs/stm32mp15_basic_defconfig
> b/configs/stm32mp15_basic_defconfig
> index d20b2ab..38a2a0a 100644
> --- a/configs/stm32mp15_basic_defconfig
> +++ b/configs/stm32mp15_basic_defconfig
> @@ -41,6 +41,8 @@ CONFIG_LED=y
>  CONFIG_LED_GPIO=y
>  CONFIG_DM_MMC=y
>  CONFIG_STM32_SDMMC2=y
> +CONFIG_DM_ETH=y
> +CONFIG_DWC_ETH_QOS=y
>  CONFIG_PHY=y
>  CONFIG_PHY_STM32_USBPHYC=y
>  # CONFIG_PINCTRL_FULL is not set
> --
> 2.7.4

For stm32mp1 boards EV1 and DK2
Test done with master (SHA1 = 75ce8c938d39bd22460be66e6bf318bd2410c17b)

Tested-by: Patrick Delaunay 
Acked-by: Patrick Delaunay 

Regards
Patrick

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Re: [U-Boot] [PATCH 5/6] stm32mp1: Add Ethernet support for stm32mp1 board

[Patrick DELAUNAY]

Hi Christophe,

 
> Add default SERVERIP address
> Enable noncached memory region required by ethernet driver Add PXE support
> 
> Signed-off-by: Christophe Roullier 
> ---
> 
>  include/configs/stm32mp1.h | 11 ++-
>  1 file changed, 10 insertions(+), 1 deletion(-)
> 
> diff --git a/include/configs/stm32mp1.h b/include/configs/stm32mp1.h index
> 701298c..8469529 100644
> --- a/include/configs/stm32mp1.h
> +++ b/include/configs/stm32mp1.h
> @@ -73,12 +73,21 @@
>  #define CONFIG_SYS_MMC_MAX_DEVICE3
>  #define CONFIG_SUPPORT_EMMC_BOOT
> 
> +/* Ethernet need */
> +#ifdef CONFIG_DWC_ETH_QOS
> +#define CONFIG_SYS_NONCACHED_MEMORY  (1 * SZ_1M) /* 1M */
> +#define CONFIG_SERVERIP 192.168.1.1
> +#define CONFIG_BOOTP_SERVERIP
> +#define CONFIG_SYS_AUTOLOAD  "no"
> +#endif
> +
>  #if !defined(CONFIG_SPL) || !defined(CONFIG_SPL_BUILD)
> 
>  #define BOOT_TARGET_DEVICES(func) \
>   func(MMC, mmc, 1) \
>   func(MMC, mmc, 0) \
> - func(MMC, mmc, 2)
> + func(MMC, mmc, 2) \
> + func(PXE, pxe, na)
> 
>  #include 
> 
> --
> 2.7.4

For stm32mp1 boards EV1 and DK2
Test done with master (SHA1 = 75ce8c938d39bd22460be66e6bf318bd2410c17b)

Tested-by: Patrick Delaunay 
Acked-by: Patrick Delaunay 

One minor remark: you can add "boot_net_usb_start=true" in 
CONFIG_EXTRA_ENV_SETTINGS to avoid unnecessary usb start  when ethernet is 
started.

I will push a patch when the serie will be accepted.


Regards
Patrick
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Re: [U-Boot] [PATCH 3/6] net: dwc_eth_qos: add Ethernet stm32mp1 support

[Patrick DELAUNAY]

Hi Christophe,

> 
> Synopsys GMAC 4.20 is used. And Phy mode for eval and disco is RMII with PHY
> Realtek RTL8211 (RGMII) We also support some other PHY config on
> stm32mp157c
> PHY_MODE  (MII,GMII, RMII, RGMII) and in normal,
> PHY wo crystal (25Mhz and 50Mhz), No 125Mhz from PHY config
> 
> Signed-off-by: Christophe Roullier 
> ---
> 
>  drivers/net/dwc_eth_qos.c | 435
> --
>  1 file changed, 383 insertions(+), 52 deletions(-)
> 
> diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index
> 9f1c5af..a6546d5 100644
> --- a/drivers/net/dwc_eth_qos.c
> +++ b/drivers/net/dwc_eth_qos.c
> @@ -26,7 +26,6 @@
>   *supports a single RGMII PHY. This configuration also has SW control 
> over
>   *all clock and reset signals to the HW block.
>   */
> -
>  #include 
>  #include 
>  #include 
> @@ -95,6 +94,7 @@ struct eqos_mac_regs {
>  #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK   3
>  #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED0
>  #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB2
> +#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV 1
> 
>  #define EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT   0
>  #define EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK0xff
> @@ -108,6 +108,7 @@ struct eqos_mac_regs {
>  #define EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT  16
>  #define EQOS_MAC_MDIO_ADDRESS_CR_SHIFT   8
>  #define EQOS_MAC_MDIO_ADDRESS_CR_20_35   2
> +#define EQOS_MAC_MDIO_ADDRESS_CR_250_300 5
>  #define EQOS_MAC_MDIO_ADDRESS_SKAP   BIT(4)
>  #define EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT  2
>  #define EQOS_MAC_MDIO_ADDRESS_GOC_READ   3
> @@ -260,6 +261,29 @@ struct eqos_desc {
> 
>  struct eqos_config {
>   bool reg_access_always_ok;
> + int mdio_wait;
> + int swr_wait;
> + int config_mac;
> + int config_mac_mdio;
> + int (*interface)(struct udevice *dev);
> + struct eqos_ops *ops;
> +};
> +
> +struct eqos_ops {
> + void (*eqos_inval_desc)(void *desc);
> + void (*eqos_flush_desc)(void *desc);
> + void (*eqos_inval_buffer)(void *buf, size_t size);
> + void (*eqos_flush_buffer)(void *buf, size_t size);
> + int (*eqos_probe_resources)(struct udevice *dev);
> + int (*eqos_remove_resources)(struct udevice *dev);
> + int (*eqos_stop_resets)(struct udevice *dev);
> + int (*eqos_start_resets)(struct udevice *dev);
> + void (*eqos_stop_clks)(struct udevice *dev);
> + int (*eqos_start_clks)(struct udevice *dev);
> + int (*eqos_calibrate_pads)(struct udevice *dev);
> + int (*eqos_disable_calibration)(struct udevice *dev);
> + int (*eqos_set_tx_clk_speed)(struct udevice *dev);
> + ulong (*eqos_get_tick_clk_rate)(struct udevice *dev);
>  };
> 
>  struct eqos_priv {
> @@ -276,6 +300,7 @@ struct eqos_priv {
>   struct clk clk_rx;
>   struct clk clk_ptp_ref;
>   struct clk clk_tx;
> + struct clk clk_ck;
>   struct clk clk_slave_bus;
>   struct mii_dev *mii;
>   struct phy_device *phy;
> @@ -327,7 +352,7 @@ static void eqos_free_descs(void *descs)  #endif  }
> 
> -static void eqos_inval_desc(void *desc)
> +static void eqos_inval_desc_tegra186(void *desc)
>  {
>  #ifndef CONFIG_SYS_NONCACHED_MEMORY
>   unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN -
> 1); @@ -338,14 +363,36 @@ static void eqos_inval_desc(void *desc)  #endif  }
> 
> -static void eqos_flush_desc(void *desc)
> +static void eqos_inval_desc_stm32(void *desc) { #ifndef
> +CONFIG_SYS_NONCACHED_MEMORY
> + unsigned long start = rounddown((unsigned long)desc,
> ARCH_DMA_MINALIGN);
> + unsigned long end = roundup((unsigned long)desc +
> EQOS_DESCRIPTOR_SIZE,
> + ARCH_DMA_MINALIGN);
> +
> + invalidate_dcache_range(start, end);
> +#endif
> +}
> +
> +static void eqos_flush_desc_tegra186(void *desc)
>  {
>  #ifndef CONFIG_SYS_NONCACHED_MEMORY
>   flush_cache((unsigned long)desc, EQOS_DESCRIPTOR_SIZE);  #endif  }
> 
> -static void eqos_inval_buffer(void *buf, size_t size)
> +static void eqos_flush_desc_stm32(void *desc) { #ifndef
> +CONFIG_SYS_NONCACHED_MEMORY
> + unsigned long start = rounddown((unsigned long)desc,
> ARCH_DMA_MINALIGN);
> + unsigned long end = roundup((unsigned long)desc +
> EQOS_DESCRIPTOR_SIZE,
> + ARCH_DMA_MINALIGN);
> +
> + flush_dcache_range(start, end);
> +#endif
> +}
> +
> +static void eqos_inval_buffer_tegra186(void *buf, size_t size)
>  {
>   unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN -
> 1);
>   unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN); @@ -
> 353,11 +400,29 @@ static void eqos_inval_buffer(void *buf, size_t size)
>   invalidate_dcache_range(start, end);
>  }
> 
> -static void eqos_flush_buffer(void *buf, size_t size)
> +static void 

Re: [U-Boot] [PATCH 4/6] ARM: dts: stm32: Add Ethernet support on stm32mp1

[Patrick DELAUNAY]

Hi Christophe,

> 
> This patch add Ethernet support on stm32mp157 eval board
> 
> Signed-off-by: Christophe Roullier 
> ---
> 
>  arch/arm/dts/stm32mp157-pinctrl.dtsi | 31
> +++
>  arch/arm/dts/stm32mp157c-ev1.dts | 21 +
>  arch/arm/dts/stm32mp157c.dtsi| 35
> +++
>  3 files changed, 87 insertions(+)
> 
> diff --git a/arch/arm/dts/stm32mp157-pinctrl.dtsi b/arch/arm/dts/stm32mp157-
> pinctrl.dtsi
> index 85da592..66723b0 100644
> --- a/arch/arm/dts/stm32mp157-pinctrl.dtsi
> +++ b/arch/arm/dts/stm32mp157-pinctrl.dtsi
> @@ -157,6 +157,37 @@
>   };
>   };
> 
> + ethernet0_rgmii_pins_a: rgmii-0 {
> + pins1 {
> + pinmux =  AF11)>, /* ETH_RGMII_CLK125 */
> +  ,
> /* ETH_RGMII_GTX_CLK */
> +   AF11)>, /* ETH_RGMII_TXD0 */
> +   AF11)>, /* ETH_RGMII_TXD1 */
> +  ,
> /* ETH_RGMII_TXD2 */
> +  ,
> /* ETH_RGMII_TXD3 */
> +   AF11)>, /* ETH_RGMII_TX_CTL */
> +  ;
> /* ETH_MDC */
> + bias-disable;
> + drive-push-pull;
> + slew-rate = <2>;
> + };
> + pins2 {
> + pinmux =  AF11)>; /* ETH_MDIO */
> + bias-disable;
> + drive-push-pull;
> + slew-rate = <0>;
> + };
> + pins3 {
> + pinmux =  AF11)>, /* ETH_RGMII_RXD0 */
> +  ,
> /* ETH_RGMII_RXD1 */
> +  ,
> /* ETH_RGMII_RXD2 */
> +  ,
> /* ETH_RGMII_RXD3 */
> +  ,
> /* ETH_RGMII_RX_CLK */
> +  ;
> /* ETH_RGMII_RX_CTL */
> + bias-disable;
> + };
> + };
> +
>   i2c1_pins_a: i2c1-0 {
>   pins {
>   pinmux =  AF5)>, /* I2C1_SCL */ diff --git a/arch/arm/dts/stm32mp157c-ev1.dts
> b/arch/arm/dts/stm32mp157c-ev1.dts
> index 902a42b..bdbf7fb 100644
> --- a/arch/arm/dts/stm32mp157c-ev1.dts
> +++ b/arch/arm/dts/stm32mp157c-ev1.dts
> @@ -11,6 +11,9 @@
>   model = "STMicroelectronics STM32MP157C eval daughter on eval
> mother";
>   compatible = "st,stm32mp157c-ev1", "st,stm32mp157c-ed1",
> "st,stm32mp157";
> 
> + aliases {
> + ethernet0 = 
> + };
>  };
> 
>   {
> @@ -19,6 +22,24 @@
>   status = "okay";
>  };
> 
> + {
> + status = "okay";
> + pinctrl-0 = <_rgmii_pins_a>;
> + pinctrl-names = "default";
> + phy-mode = "rgmii-id";
> + max-speed = <1000>;
> + phy-handle = <>;
> +
> + mdio0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "snps,dwmac-mdio";
> + phy0: ethernet-phy@0 {
> + reg = <0>;
> + };
> + };
> +};
> +
>   {
>   pinctrl-names = "default";
>   pinctrl-0 = <_pins_a>;
> diff --git a/arch/arm/dts/stm32mp157c.dtsi b/arch/arm/dts/stm32mp157c.dtsi 
> index
> 37cadfa..1271abf 100644
> --- a/arch/arm/dts/stm32mp157c.dtsi
> +++ b/arch/arm/dts/stm32mp157c.dtsi
> @@ -915,6 +915,41 @@
>   status = "disabled";
>   };
> 
> + stmmac_axi_config_0: stmmac-axi-config {
> + snps,wr_osr_lmt = <0x7>;
> + snps,rd_osr_lmt = <0x7>;
> + snps,blen = <0 0 0 0 16 8 4>;
> + };
> +
> + ethernet0: ethernet@5800a000 {
> + compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
> + reg = <0x5800a000 0x2000>;
> + reg-names = "stmmaceth";
> + interrupts-extended =
> + < GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
> + < GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
> + < 70 1>;
> + interrupt-names = "macirq",
> +   "eth_wake_irq",
> +   "stm32_pwr_wakeup";
> + clock-names = "stmmaceth",
> +   "mac-clk-tx",
> +   

Re: [U-Boot] [PATCH 2/6] board: stm32mp1: Add board_interface_eth_init

[Patrick DELAUNAY]

Hi Christophe,

> 
> Called to configure Ethernet PHY interface selection and configure clock 
> selection
> in RCC Ethernet clock tree.
> 
> Signed-off-by: Christophe Roullier 
> ---
> 
>  board/st/stm32mp1/stm32mp1.c | 77
> 
>  1 file changed, 77 insertions(+)
> 
> diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c
> index 54feca0..7c37018 100644
> --- a/board/st/stm32mp1/stm32mp1.c
> +++ b/board/st/stm32mp1/stm32mp1.c
> @@ -10,12 +10,27 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
>  #include 
>  #include 
> 
> +/* SYSCFG registers */
> +#define SYSCFG_PMCSETR   0x04
> +#define SYSCFG_PMCCLRR   0x44
> +
> +#define SYSCFG_PMCSETR_ETH_CLK_SEL   BIT(16)
> +#define SYSCFG_PMCSETR_ETH_REF_CLK_SEL   BIT(17)
> +
> +#define SYSCFG_PMCSETR_ETH_SELMIIBIT(20)
> +
> +#define SYSCFG_PMCSETR_ETH_SEL_MASK  GENMASK(23, 21)
> +#define SYSCFG_PMCSETR_ETH_SEL_GMII_MII  0
> +#define SYSCFG_PMCSETR_ETH_SEL_RGMII BIT(21)
> +#define SYSCFG_PMCSETR_ETH_SEL_RMII  BIT(23)
> +
>  /*
>   * Get a global data pointer
>   */
> @@ -196,3 +211,65 @@ int board_init(void)
> 
>   return 0;
>  }
> +
> +/* board interface eth init */
> +/* this is a weak define that we are overriding */ int
> +board_interface_eth_init(int interface_type, bool eth_clk_sel_reg,
> +  bool eth_ref_clk_sel_reg)
> +{
> + u8 *syscfg;
> + u32 value;
> +
> + syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
> +
> + if (!syscfg)
> + return -ENODEV;
> +
> + switch (interface_type) {
> + case PHY_INTERFACE_MODE_MII:
> + value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
> + SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
> + debug("%s: PHY_INTERFACE_MODE_MII\n", __func__);
> + break;
> + case PHY_INTERFACE_MODE_GMII:
> + if (eth_clk_sel_reg)
> + value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
> + SYSCFG_PMCSETR_ETH_CLK_SEL;
> + else
> + value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII;
> + debug("%s: PHY_INTERFACE_MODE_GMII\n", __func__);
> + break;
> + case PHY_INTERFACE_MODE_RMII:
> + if (eth_ref_clk_sel_reg)
> + value = SYSCFG_PMCSETR_ETH_SEL_RMII |
> + SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
> + else
> + value = SYSCFG_PMCSETR_ETH_SEL_RMII;
> + debug("%s: PHY_INTERFACE_MODE_RMII\n", __func__);
> + break;
> + case PHY_INTERFACE_MODE_RGMII:
> + case PHY_INTERFACE_MODE_RGMII_ID:
> + case PHY_INTERFACE_MODE_RGMII_RXID:
> + case PHY_INTERFACE_MODE_RGMII_TXID:
> + if (eth_clk_sel_reg)
> + value = SYSCFG_PMCSETR_ETH_SEL_RGMII |
> + SYSCFG_PMCSETR_ETH_CLK_SEL;
> + else
> + value = SYSCFG_PMCSETR_ETH_SEL_RGMII;
> + debug("%s: PHY_INTERFACE_MODE_RGMII\n", __func__);
> + break;
> + default:
> + debug("%s: Do not manage %d interface\n",
> +   __func__, interface_type);
> + /* Do not manage others interfaces */
> + return -EINVAL;
> + }
> +
> + /* clear and set ETH configuration bits */
> + writel(SYSCFG_PMCSETR_ETH_SEL_MASK |
> SYSCFG_PMCSETR_ETH_SELMII |
> +SYSCFG_PMCSETR_ETH_REF_CLK_SEL |
> SYSCFG_PMCSETR_ETH_CLK_SEL,
> +syscfg + SYSCFG_PMCCLRR);
> + writel(value, syscfg + SYSCFG_PMCSETR);
> +
> + return 0;
> +}
> --
> 2.7.4

For stm32mp1 boards EV1 and DK2
Test done with master (SHA1 = 75ce8c938d39bd22460be66e6bf318bd2410c17b)

Tested-by: Patrick Delaunay 
Acked-by: Patrick Delaunay 

Regards
Patrick
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Re: [U-Boot] [PATCH] phycore-pcl060: U-boot support for Phytec phyCORE PCL060

[Parthiban Nallathambi]

Hello Marek,

On 4/19/19 3:35 PM, Marek Vasut wrote:
> On 4/19/19 3:18 PM, Parthiban Nallathambi wrote:
> 
> Hi,
> 
> [...]
> 
 diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
 index d29f1ca0b5..9336439340 100644
 --- a/arch/arm/mach-omap2/Kconfig
 +++ b/arch/arm/mach-omap2/Kconfig
 @@ -186,6 +186,7 @@ source "board/ti/am43xx/Kconfig"
  source "board/ti/am335x/Kconfig"
  source "board/compulab/cm_t335/Kconfig"
  source "board/compulab/cm_t43/Kconfig"
 +source "board/phytec/phycore_pcl060/Kconfig"
>>>
>>> Here [1] it says the name of the SoM is PCM-060 , what is PCL-060 ?
>>>
>>> [1]
>>> https://www.phytec.eu/product-eu/system-on-modules/phycore-am335x-download/
>>>  [...]
>>
>> This differs only by the connector. PCM variants are pluggable and PCL 
>> variants
>> are direct soliderable to the carrier board.
>>
>> Copied from [1]:
>> The PCL-060 System On Module is a connector-less, BGA style variant of the
>> PCM-060/phyCORE-AM335x R2 SOM. Unlike traditional Phytec SOM products that 
>> support
>> high density connectors, the PCL-060 SOM is directly soldered down to the
>> phyBOARD-Wega AM335x using Phytec's Direct Solder Connect technology (DSC). 
>> This
>> solution offers an ultra-low cost Single Board Computer for the AM335x 
>> processor, while
>> maintaining most of the advantages of the SOM concept.
>>
>> [1] 
>> https://www.phytec.de/fileadmin/user_upload/downloads/Manuals/L-845e_1.pdf
> 
> Ah damn, this looks like a consistency problem is coming up. We have
> multiple PCM* SoMs in U-Boot, one PCL* SoM and now another PCL/PCM SoM.
> But the PCL063 isn't even manufactured in variant with connectors, so I
> guess we can ignore that one.
> 
> I wonder whether we should stick to PCM* for all of the Phytec SoMs for
> consistency sake and document that PCL060 is also supported or maybe
> there's a better way ?

Does PCX/PCx makes sense? But we have the same problem with variscite [1] SoM's
(either SODIMM or solderable).

[1] https://lists.denx.de/pipermail/u-boot/2019-April/365667.html

> 
> [...]
> 

-- 
Thanks,
Parthiban N

DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-22 Fax: (+49)-8142-66989-80 Email: p...@denx.de
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Re: [U-Boot] [PATCH 1/6] stm32mp1: clk: use the correct identifier for ethck

[Patrick DELAUNAY]

Hi Christophe,

> 
> From: Patrick Delaunay 
> 
> ETHCK_K is the identifier the kernel clock for ETH in kernel binding, 
> selected by
> ETHKSELR / gated by ETHCKEN = BIT(7).
> U-Boot driver need to use the same identifier, so change ETHCK to ETHCK_K.
> 
> Signed-off-by: Patrick Delaunay 
> Signed-off-by: Christophe Roullier 
> ---
> 
>  drivers/clk/clk_stm32mp1.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c index
> aebc6f0..d70e039 100644
> --- a/drivers/clk/clk_stm32mp1.c
> +++ b/drivers/clk/clk_stm32mp1.c
> @@ -553,7 +553,7 @@ static const struct stm32mp1_clk_gate
> stm32mp1_clk_gate[] = {
> 
>   STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 0, GPIOZ,
> _UNKNOWN_SEL),
> 
> - STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 7, ETHCK,
> _ETH_SEL),
> + STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 7, ETHCK_K,
> _ETH_SEL),
>   STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 8, ETHTX,
> _UNKNOWN_SEL),
>   STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 9, ETHRX,
> _UNKNOWN_SEL),
>   STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB6ENSETR, 10, ETHMAC,
> _ACLK),
> --
> 2.7.4

For stm32mp1 boards EV1 and DK2
Test done with master (SHA1 = 75ce8c938d39bd22460be66e6bf318bd2410c17b)

Tested-by: Patrick Delaunay 

Regards
Patrick
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Re: [U-Boot] [GIT] Pull request: u-boot-dfu (14.04.2019)

[Lukasz Majewski]

Hi Marek,

> On 4/19/19 1:23 PM, Lukasz Majewski wrote:
> > Dear Marek,
> > 
> > The following changes since commit
> > 1f4ae66eaab29bfb5d1eb44996f7826c9cd01ed1:  
> 
> [...]
> 
> > Peng Fan (1):
> >   MLK-12883 usb: limit USB_MAX_XFER_BLK to 256  
> 
> NAK, this patch is not for gadget and is wrong, cfr. my comment on V3.
> Please drop it and respin the PR.
> 

Interesting as I was not on the v3 CC

Anyway, I will prepare next PR.

Best regards,

Lukasz Majewski

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Re: [U-Boot] [rockchip/rk3399-rockpro64] Upstream doesn't have support for SD card/USB3.0?

[Qu Wenruo]

On 2019/4/19 下午2:08, Qu Wenruo wrote:
> Hi,
> 
> Sorry if the problem is too newbie, but I tried to build upstream U-boot
> for RockPro64 (which uses RK3399 SoC) using the evb-rk3399 defconfig.
> 
> My adventure starts good, it boots properly. However SDMMC doesn't work
> ("Card did not respond to voltage select!").
> 
> USB only detects two USB2.0 hubs, no USB storage detected either.
> 
> The missing storage looks like can be solved by adding USB storage
> support, but I'm wondering how to make Uboot to recognize the SDMMC.
> 
> Not familiar enough with device tree, but v5.1-rc kernel seems to have
> the dst file needed for rockpro64.
> 
> Any idea on what to do next? Copying the file and try to make U-boot to
> add a new board?

Well, found the existing patch for that, and after applying, everything
works fine.

The original error report is for eMMC module which is fine as I haven't
installed eMMC module to that board, and no driver for SDcard.

Thanks,
Qu

> 
> Thanks,
> Qu
> 
> 
> 
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Re: [U-Boot] [RESEND PATCH v3] sun50i: a64: Add Olimex A64-Teres-I board initial support

[Jonas Smedegaard]

Quoting Jagan Teki (2019-04-19 08:21:27)
> On Fri, Apr 19, 2019 at 1:14 AM Jonas Smedegaard  wrote:
> >
> > [resent only to list, to avoid blocking due to too many recipients]
> 
> Better to CC maintainers at least.

I agree, but...

a) above email was no progression but a simple re-posting to list what 
was already sent to to you and others but had been blocked from entering 
the list due to too many recipients (although the earlier held-back 
email was then accepted to the list about same time as I resend it), and

b) I am uncertain which maintainers are appropriate to cc - patman 
script adds 11 recipients which th list considers too many and holds 
back.  Should I simply ignore those mailinglist warnings and wait days 
for my posts to get accepted?

[snip repeated remarks: Agreed, will include in next revision]


> > --- /dev/null
> > +++ b/configs/teres_i_defconfig
> > @@ -0,0 +1,21 @@
> > +CONFIG_ARM=y
> > +CONFIG_ARCH_SUNXI=y
> > +CONFIG_SPL=y
> > +CONFIG_MACH_SUN50I=y
> > +CONFIG_DRAM_CLK=552
> > +CONFIG_DRAM_ZQ=3881949
> > +CONFIG_MMC_SUNXI_SLOT_EXTRA=2
> > +CONFIG_I2C0_ENABLE=y
> > +# CONFIG_CMD_FLASH is not set
> > +# CONFIG_SPL_DOS_PARTITION is not set
> > +# CONFIG_SPL_EFI_PARTITION is not set
> > +CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-teres-i"
> > +CONFIG_DM_REGULATOR=y
> > +CONFIG_DM_REGULATOR_FIXED=y
> > +CONFIG_DM_PWM=y
> > +CONFIG_PWM_SUNXI=y
> > +CONFIG_USB_EHCI_HCD=y
> 
> Enable CONFIG_USB_OHCI_HCD since you have ohci node. I this this would 
> fix your usb issue.

No, solution is _not_ to simply add CONFIG_USB_OHCI_HCD as that will 
cause the board to hang.

If solution to USB issue is simple then I certainly agree that should be 
done as part of this initial patch, but even without USB support I find 
the patch quite useful: It makes the board bootable with mainline linux!

I therefore suggest to include the patch as-is and work on the USB issue 
separately.


 - Jonas

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Re: [U-Boot] [PATCH v3] spi: Zap mxs_spi driver-related code

[Marek Vasut]

On 4/19/19 3:29 PM, Marek Vasut wrote:
> On 4/19/19 2:42 PM, Tom Rini wrote:
>> On Fri, Apr 19, 2019 at 11:25:47AM +0200, Marek Vasut wrote:
>>> On 4/19/19 8:55 AM, Jagan Teki wrote:
 Dropped
 - mxs_spi driver
 - CONFIG_MXS_SPI

 Dropped due to:
 - no active updates
 - no dm conversion
 - multiple pings for asking dm-conversion
>>>
>>> This is the first information I received ... sigh.
>>
>> Sigh, I thought you had seen this before and noted at the time that you
>> hadn't heard anything before then.
>>
>> So, are the mx28 family boards something we still want to support?  I
>> assume there's going to be other things that need converting there too.
> 
> I didn't see much MX28 activity recently myself, except for the thing
> Mans was playing with.

Oh and regarding the conversion, yes, a lot of MXS stuff will need
conversion.

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Re: [U-Boot] [PATCH] phycore-pcl060: U-boot support for Phytec phyCORE PCL060

[Marek Vasut]

On 4/19/19 3:18 PM, Parthiban Nallathambi wrote:

Hi,

[...]

>>> diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
>>> index d29f1ca0b5..9336439340 100644
>>> --- a/arch/arm/mach-omap2/Kconfig
>>> +++ b/arch/arm/mach-omap2/Kconfig
>>> @@ -186,6 +186,7 @@ source "board/ti/am43xx/Kconfig"
>>>  source "board/ti/am335x/Kconfig"
>>>  source "board/compulab/cm_t335/Kconfig"
>>>  source "board/compulab/cm_t43/Kconfig"
>>> +source "board/phytec/phycore_pcl060/Kconfig"
>>
>> Here [1] it says the name of the SoM is PCM-060 , what is PCL-060 ?
>>
>> [1]
>> https://www.phytec.eu/product-eu/system-on-modules/phycore-am335x-download/
>>  [...]
> 
> This differs only by the connector. PCM variants are pluggable and PCL 
> variants
> are direct soliderable to the carrier board.
> 
> Copied from [1]:
> The PCL-060 System On Module is a connector-less, BGA style variant of the
> PCM-060/phyCORE-AM335x R2 SOM. Unlike traditional Phytec SOM products that 
> support
> high density connectors, the PCL-060 SOM is directly soldered down to the
> phyBOARD-Wega AM335x using Phytec's Direct Solder Connect technology (DSC). 
> This
> solution offers an ultra-low cost Single Board Computer for the AM335x 
> processor, while
> maintaining most of the advantages of the SOM concept.
> 
> [1] https://www.phytec.de/fileadmin/user_upload/downloads/Manuals/L-845e_1.pdf

Ah damn, this looks like a consistency problem is coming up. We have
multiple PCM* SoMs in U-Boot, one PCL* SoM and now another PCL/PCM SoM.
But the PCL063 isn't even manufactured in variant with connectors, so I
guess we can ignore that one.

I wonder whether we should stick to PCM* for all of the Phytec SoMs for
consistency sake and document that PCL060 is also supported or maybe
there's a better way ?

[...]

-- 
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Re: [U-Boot] [PATCH v3] spi: Zap mxs_spi driver-related code

[Michael Nazzareno Trimarchi]

Hi Tom

On Fri, Apr 19, 2019 at 2:42 PM Tom Rini  wrote:
>
> On Fri, Apr 19, 2019 at 11:25:47AM +0200, Marek Vasut wrote:
> > On 4/19/19 8:55 AM, Jagan Teki wrote:
> > > Dropped
> > > - mxs_spi driver
> > > - CONFIG_MXS_SPI
> > >
> > > Dropped due to:
> > > - no active updates
> > > - no dm conversion
> > > - multiple pings for asking dm-conversion
> >
> > This is the first information I received ... sigh.
>
> Sigh, I thought you had seen this before and noted at the time that you
> hadn't heard anything before then.
>
> So, are the mx28 family boards something we still want to support?  I
> assume there's going to be other things that need converting there too.

I have one mx28 long term support. We have added spl support and
booting. Can you please
wait to drop it?

Michael
>
> --
> Tom
>


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Re: [U-Boot] [GIT] Pull request: u-boot-dfu (14.04.2019)

[Marek Vasut]

On 4/19/19 1:23 PM, Lukasz Majewski wrote:
> Dear Marek,
> 
> The following changes since commit
> 1f4ae66eaab29bfb5d1eb44996f7826c9cd01ed1:

[...]

> Peng Fan (1):
>   MLK-12883 usb: limit USB_MAX_XFER_BLK to 256

NAK, this patch is not for gadget and is wrong, cfr. my comment on V3.
Please drop it and respin the PR.

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Re: [U-Boot] [PATCH v3] spi: Zap mxs_spi driver-related code

[Marek Vasut]

On 4/19/19 2:42 PM, Tom Rini wrote:
> On Fri, Apr 19, 2019 at 11:25:47AM +0200, Marek Vasut wrote:
>> On 4/19/19 8:55 AM, Jagan Teki wrote:
>>> Dropped
>>> - mxs_spi driver
>>> - CONFIG_MXS_SPI
>>>
>>> Dropped due to:
>>> - no active updates
>>> - no dm conversion
>>> - multiple pings for asking dm-conversion
>>
>> This is the first information I received ... sigh.
> 
> Sigh, I thought you had seen this before and noted at the time that you
> hadn't heard anything before then.
> 
> So, are the mx28 family boards something we still want to support?  I
> assume there's going to be other things that need converting there too.

I didn't see much MX28 activity recently myself, except for the thing
Mans was playing with.

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Re: [U-Boot] [PATCH] phycore-pcl060: U-boot support for Phytec phyCORE PCL060

[Parthiban Nallathambi]

Hello Marek,

On 4/19/19 11:47 AM, Marek Vasut wrote:
> On 4/18/19 5:01 PM, Niel Fourie wrote:
>> Support for Phytech phyCORE AM335x R2 SOM (PCL060) on the Phytec
>> phyBOARD-Wega AM335x.
>>
>> CPU  : AM335X-GP rev 2.1
>> Model: Phytec AM335x phyBOARD-WEGA
>> DRAM:  256 MiB
>> NAND:  256 MiB
>> MMC:   OMAP SD/MMC: 0
>> eth0: ethernet@4a10
>>
>> Working:
>>  - Eth0
>>  - i2C
>>  - MMC/SD
>>  - NAND
>>  - UART
>>  - USB (host)
>>
>> Signed-off-by: Niel Fourie 
>> ---
>>  arch/arm/dts/Makefile|   3 +-
>>  arch/arm/dts/am335x-phycore-som.dtsi | 327 ++
>>  arch/arm/dts/am335x-wega-rdk-u-boot.dtsi |  35 +++
>>  arch/arm/dts/am335x-wega-rdk.dts |  23 ++
>>  arch/arm/dts/am335x-wega.dtsi| 231 +++
> 
> The DTs come from Linux kernel, but which version of Linux ?
> Which exact commit ? Did you modify them in any way ?
> 
> [...]
> 
>> diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
>> index d29f1ca0b5..9336439340 100644
>> --- a/arch/arm/mach-omap2/Kconfig
>> +++ b/arch/arm/mach-omap2/Kconfig
>> @@ -186,6 +186,7 @@ source "board/ti/am43xx/Kconfig"
>>  source "board/ti/am335x/Kconfig"
>>  source "board/compulab/cm_t335/Kconfig"
>>  source "board/compulab/cm_t43/Kconfig"
>> +source "board/phytec/phycore_pcl060/Kconfig"
> 
> Here [1] it says the name of the SoM is PCM-060 , what is PCL-060 ?
> 
> [1]
> https://www.phytec.eu/product-eu/system-on-modules/phycore-am335x-download/
>  [...]

This differs only by the connector. PCM variants are pluggable and PCL variants
are direct soliderable to the carrier board.

Copied from [1]:
The PCL-060 System On Module is a connector-less, BGA style variant of the
PCM-060/phyCORE-AM335x R2 SOM. Unlike traditional Phytec SOM products that 
support
high density connectors, the PCL-060 SOM is directly soldered down to the
phyBOARD-Wega AM335x using Phytec's Direct Solder Connect technology (DSC). This
solution offers an ultra-low cost Single Board Computer for the AM335x 
processor, while
maintaining most of the advantages of the SOM concept.

[1] https://www.phytec.de/fileadmin/user_upload/downloads/Manuals/L-845e_1.pdf

Thanks,
Parthiban N

> 
>> diff --git a/board/phytec/phycore_pcl060/Kconfig 
>> b/board/phytec/phycore_pcl060/Kconfig
>> new file mode 100644
>> index 00..bdd1a9b6e0
>> --- /dev/null
>> +++ b/board/phytec/phycore_pcl060/Kconfig
>> @@ -0,0 +1,19 @@
>> +if TARGET_PCL060
>> +
>> +config SYS_BOARD
>> +default "phycore_pcl060"
>> +
>> +config SYS_VENDOR
>> +default "phytec"
>> +
>> +config SYS_SOC
>> +default "am33xx"
>> +
>> +config SYS_CONFIG_NAME
>> +default "phycore_pcl060"
>> +
>> +config PCL060_DDR_SIZE
>> +int "DDR size (in MiB) of Phycore PCL060 module"
>> +default 256
> 
> DRAM size should come from DT, we don't need another custom config
> option. Look at fdtdec_setup_mem_size_base() and
> fdtdec_setup_memory_banksize().
> 
> [...]
> 
>> diff --git a/board/phytec/phycore_pcl060/board.c 
>> b/board/phytec/phycore_pcl060/board.c
>> new file mode 100644
>> index 00..01fe13e959
>> --- /dev/null
>> +++ b/board/phytec/phycore_pcl060/board.c
>> @@ -0,0 +1,340 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * board.c
>> + *
>> + * Board functions for Phytec phyCORE-AM335x R2 (pcl060) based boards
>> + *
>> + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
>> + * Copyright (C) 2013 Lars Poeschel, Lemonage Software GmbH
>> + * Copyright (C) 2015 Wadim Egorov, PHYTEC Messtechnik GmbH
>> + * Copyright (C) 2019 DENX Software Engineering GmbH
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include "board.h"
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
>> +
>> +#ifdef CONFIG_SPL_BUILD
>> +
>> +#ifdef CONFIG_SPL_OS_BOOT
> 
> #if CONFIG_IS_ENABLED(OS_BOOT)
> 
>> +int spl_start_uboot(void)
>> +{
>> +return 1;
>> +}
>> +#endif
>> +/* DDR RAM defines */
>> +#define DDR_CLK_MHZ 400 /* DDR_DPLL_MULT value */
>> +
>> +#define OSC (V_OSCK / 100)
>> +const struct dpll_params dpll_ddr = {
>> +DDR_CLK_MHZ, OSC - 1, 1, -1, -1, -1, -1};
>> +
>> +const struct dpll_params *get_dpll_ddr_params(void)
>> +{
>> +return _ddr;
>> +}
>> +
>> +const struct ctrl_ioregs ioregs = {
>> +.cm0ioctl   = 0x18B,
>> +.cm1ioctl   = 0x18B,
>> +.cm2ioctl   = 0x18B,
>> +.dt0ioctl   = 0x18B,
>> +.dt1ioctl   = 0x18B,
>> +};
>> +
>> +static const struct cmd_control ddr3_cmd_ctrl_data = {
>> +.cmd0csratio = 0x80,
>> +.cmd0iclkout = 0x0,
>> +
>> +.cmd1csratio = 0x80,
>> +

Re: [U-Boot] [PATCH v3] spi: Zap mxs_spi driver-related code

[Tom Rini]

On Fri, Apr 19, 2019 at 11:25:47AM +0200, Marek Vasut wrote:
> On 4/19/19 8:55 AM, Jagan Teki wrote:
> > Dropped
> > - mxs_spi driver
> > - CONFIG_MXS_SPI
> > 
> > Dropped due to:
> > - no active updates
> > - no dm conversion
> > - multiple pings for asking dm-conversion
> 
> This is the first information I received ... sigh.

Sigh, I thought you had seen this before and noted at the time that you
hadn't heard anything before then.

So, are the mx28 family boards something we still want to support?  I
assume there's going to be other things that need converting there too.

-- 
Tom


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Re: [U-Boot] [PATCH] Convert CONFIG_SUPPORT_EMMC_BOOT to Kconfig

[Patrick DELAUNAY]

Hi Alex,

> 
> This converts the following to Kconfig:
>CONFIG_SUPPORT_EMMC_BOOT
> 
> Signed-off-by: Alex Kiernan 
> ---
> Green travis build:
> 
> https://travis-ci.org/akiernan/u-boot/builds/521906850
> 
> Testing affected boards for configuration changes:
> 
>   boards.cfg is up to date. Nothing to do.
>   Summary of 3 commits for 95 boards (4 threads, 1 job per thread)
>   01: Merge tag 'u-boot-imx-20190415' of git://git.denx.de/u-boot-imx
>  aarch64:  w+   xilinx_zynqmp_mini_emmc1 xilinx_zynqmp_mini_emmc0
> xilinx_zynqmp_mini_qspi clearfog_gt_8k imx8qxp_mek xilinx_zynqmp_mini
> xilinx_zynqmp_mini_nand imx8mq_evk
>  arm:  w+   cm_t54 cl-som-imx7 marsboard clearfog apalis_imx6 warp7 
> pico-
> hobbit-imx7d pico-pi-imx6ul dms-ba16 arndale riotboard pico-hobbit-imx6ul
> colibri_imx7 pico-imx7d xpress_spl opos6uldev warp7_bl33 imx6dl_mamoj
> ge_bx50v3 display5 mx7dsabresd_qspi display5_factory colibri_imx7_emmc
> gwventana_nand mx7dsabresd gwventana_gw5904 gwventana_emmc
> am57xx_hs_evm_usb omap5_uevm brppt1_spi xilinx_zynqmp_r5 vinco
> mx6sabresd warp riotboard_spl vining_2000 zc5601 zc5202 xpress pico-imx6ul
> dms-ba16-1g pico-pi-imx7d
>   02: configs: Resync with savedefconfig
>   03: Convert CONFIG_SUPPORT_EMMC_BOOT to Kconfig

Acked-by: Patrick Delaunay 

>  README   | 3 ---
>  configs/am57xx_evm_defconfig | 1 +
>  configs/am57xx_hs_evm_defconfig  | 1 +
>  configs/am57xx_hs_evm_usb_defconfig  | 1 +
>  configs/apalis-tk1_defconfig | 1 +
>  configs/apalis_imx6_defconfig| 1 +
>  configs/arndale_defconfig| 1 +
>  configs/avnet_ultra96_rev1_defconfig | 1 +
>  configs/cl-som-imx7_defconfig| 1 +
>  configs/clearfog_defconfig   | 1 +
>  configs/cm_t54_defconfig | 1 +
>  configs/colibri_imx6_defconfig   | 1 +
>  configs/colibri_imx7_emmc_defconfig  | 1 +
>  configs/display5_defconfig   | 1 +
>  configs/display5_factory_defconfig   | 1 +
>  configs/dms-ba16-1g_defconfig| 1 +
>  configs/dms-ba16_defconfig   | 1 +
>  configs/dra7xx_evm_defconfig | 1 +
>  configs/dra7xx_hs_evm_defconfig  | 1 +
>  configs/dra7xx_hs_evm_usb_defconfig  | 1 +
>  configs/edison_defconfig | 1 +
>  configs/ge_bx50v3_defconfig  | 1 +
>  configs/gwventana_emmc_defconfig | 1 +
>  configs/gwventana_gw5904_defconfig   | 1 +
>  configs/gwventana_nand_defconfig | 1 +
>  configs/imx6dl_mamoj_defconfig   | 1 +
>  configs/imx8mq_evk_defconfig | 1 +
>  configs/imx8qxp_mek_defconfig| 1 +
>  configs/liteboard_defconfig  | 1 +
>  configs/mt7623n_bpir2_defconfig  | 1 +
>  configs/mx6sabresd_defconfig | 1 +
>  configs/mx7dsabresd_defconfig| 1 +
>  configs/mx7dsabresd_qspi_defconfig   | 1 +
>  configs/mx7ulp_evk_defconfig | 1 +
>  configs/mx7ulp_evk_plugin_defconfig  | 1 +
>  configs/odroid-xu3_defconfig | 1 +
>  configs/omap5_uevm_defconfig | 1 +
>  configs/opos6uldev_defconfig | 1 +
>  configs/peach-pi_defconfig   | 1 +
>  configs/peach-pit_defconfig  | 1 +
>  configs/pico-hobbit-imx6ul_defconfig | 1 +
>  configs/pico-hobbit-imx7d_defconfig  | 1 +
>  configs/pico-imx6ul_defconfig| 1 +
>  configs/pico-imx7d_defconfig | 1 +
>  configs/pico-pi-imx6ul_defconfig | 1 +
>  configs/pico-pi-imx7d_defconfig  | 1 +
>  configs/riotboard_defconfig  | 1 +
>  configs/riotboard_spl_defconfig  | 1 +
>  configs/smdk5250_defconfig   | 1 +
>  configs/smdk5420_defconfig   | 1 +
>  configs/snow_defconfig   | 1 +
>  configs/spring_defconfig | 1 +
>  configs/stm32mp15_basic_defconfig| 1 +
>  configs/stm32mp15_trusted_defconfig  | 1 +
>  configs/uniphier_ld4_sld8_defconfig  | 1 +
>  configs/uniphier_v7_defconfig| 1 +
>  configs/uniphier_v8_defconfig| 1 +
>  configs/vinco_defconfig  | 1 +
>  configs/vining_2000_defconfig| 1 +
>  configs/warp7_bl33_defconfig | 1 +
>  configs/warp7_defconfig  | 1 +
>  configs/warp_defconfig   | 1 +
>  configs/xilinx_zynqmp_mini_emmc0_defconfig   | 1 +
>  configs/xilinx_zynqmp_mini_emmc1_defconfig 

[U-Boot] [rockchip/rk3399-rockpro64] Upstream doesn't have support for SD card/USB3.0?

[Qu Wenruo]

Hi,

Sorry if the problem is too newbie, but I tried to build upstream U-boot
for RockPro64 (which uses RK3399 SoC) using the evb-rk3399 defconfig.

My adventure starts good, it boots properly. However SDMMC doesn't work
("Card did not respond to voltage select!").

USB only detects two USB2.0 hubs, no USB storage detected either.

The missing storage looks like can be solved by adding USB storage
support, but I'm wondering how to make Uboot to recognize the SDMMC.

Not familiar enough with device tree, but v5.1-rc kernel seems to have
the dst file needed for rockpro64.

Any idea on what to do next? Copying the file and try to make U-boot to
add a new board?

Thanks,
Qu




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Re: [U-Boot] [PATCH] Convert CONFIG_SUPPORT_EMMC_BOOT to Kconfig

[Lukasz Majewski]

Hi Alex,

> This converts the following to Kconfig:
>CONFIG_SUPPORT_EMMC_BOOT
> 
> Signed-off-by: Alex Kiernan 
> ---
> Green travis build:
> 
> https://travis-ci.org/akiernan/u-boot/builds/521906850
> 
> Testing affected boards for configuration changes:
> 
>   boards.cfg is up to date. Nothing to do.
>   Summary of 3 commits for 95 boards (4 threads, 1 job per thread)
>   01: Merge tag 'u-boot-imx-20190415' of git://git.denx.de/u-boot-imx
>  aarch64:  w+   xilinx_zynqmp_mini_emmc1 xilinx_zynqmp_mini_emmc0
> xilinx_zynqmp_mini_qspi clearfog_gt_8k imx8qxp_mek xilinx_zynqmp_mini
> xilinx_zynqmp_mini_nand imx8mq_evk arm:  w+   cm_t54 cl-som-imx7
> marsboard clearfog apalis_imx6 warp7 pico-hobbit-imx7d pico-pi-imx6ul
> dms-ba16 arndale riotboard pico-hobbit-imx6ul colibri_imx7 pico-imx7d
> xpress_spl opos6uldev warp7_bl33 imx6dl_mamoj ge_bx50v3 display5
> mx7dsabresd_qspi display5_factory colibri_imx7_emmc gwventana_nand
> mx7dsabresd gwventana_gw5904 gwventana_emmc am57xx_hs_evm_usb
> omap5_uevm brppt1_spi xilinx_zynqmp_r5 vinco mx6sabresd warp
> riotboard_spl vining_2000 zc5601 zc5202 xpress pico-imx6ul
> dms-ba16-1g pico-pi-imx7d 02: configs: Resync with savedefconfig 03:
> Convert CONFIG_SUPPORT_EMMC_BOOT to Kconfig

Acked-by: Lukasz Majewski 

> 
>  README   | 3 ---
>  configs/am57xx_evm_defconfig | 1 +
>  configs/am57xx_hs_evm_defconfig  | 1 +
>  configs/am57xx_hs_evm_usb_defconfig  | 1 +
>  configs/apalis-tk1_defconfig | 1 +
>  configs/apalis_imx6_defconfig| 1 +
>  configs/arndale_defconfig| 1 +
>  configs/avnet_ultra96_rev1_defconfig | 1 +
>  configs/cl-som-imx7_defconfig| 1 +
>  configs/clearfog_defconfig   | 1 +
>  configs/cm_t54_defconfig | 1 +
>  configs/colibri_imx6_defconfig   | 1 +
>  configs/colibri_imx7_emmc_defconfig  | 1 +
>  configs/display5_defconfig   | 1 +
>  configs/display5_factory_defconfig   | 1 +
>  configs/dms-ba16-1g_defconfig| 1 +
>  configs/dms-ba16_defconfig   | 1 +
>  configs/dra7xx_evm_defconfig | 1 +
>  configs/dra7xx_hs_evm_defconfig  | 1 +
>  configs/dra7xx_hs_evm_usb_defconfig  | 1 +
>  configs/edison_defconfig | 1 +
>  configs/ge_bx50v3_defconfig  | 1 +
>  configs/gwventana_emmc_defconfig | 1 +
>  configs/gwventana_gw5904_defconfig   | 1 +
>  configs/gwventana_nand_defconfig | 1 +
>  configs/imx6dl_mamoj_defconfig   | 1 +
>  configs/imx8mq_evk_defconfig | 1 +
>  configs/imx8qxp_mek_defconfig| 1 +
>  configs/liteboard_defconfig  | 1 +
>  configs/mt7623n_bpir2_defconfig  | 1 +
>  configs/mx6sabresd_defconfig | 1 +
>  configs/mx7dsabresd_defconfig| 1 +
>  configs/mx7dsabresd_qspi_defconfig   | 1 +
>  configs/mx7ulp_evk_defconfig | 1 +
>  configs/mx7ulp_evk_plugin_defconfig  | 1 +
>  configs/odroid-xu3_defconfig | 1 +
>  configs/omap5_uevm_defconfig | 1 +
>  configs/opos6uldev_defconfig | 1 +
>  configs/peach-pi_defconfig   | 1 +
>  configs/peach-pit_defconfig  | 1 +
>  configs/pico-hobbit-imx6ul_defconfig | 1 +
>  configs/pico-hobbit-imx7d_defconfig  | 1 +
>  configs/pico-imx6ul_defconfig| 1 +
>  configs/pico-imx7d_defconfig | 1 +
>  configs/pico-pi-imx6ul_defconfig | 1 +
>  configs/pico-pi-imx7d_defconfig  | 1 +
>  configs/riotboard_defconfig  | 1 +
>  configs/riotboard_spl_defconfig  | 1 +
>  configs/smdk5250_defconfig   | 1 +
>  configs/smdk5420_defconfig   | 1 +
>  configs/snow_defconfig   | 1 +
>  configs/spring_defconfig | 1 +
>  configs/stm32mp15_basic_defconfig| 1 +
>  configs/stm32mp15_trusted_defconfig  | 1 +
>  configs/uniphier_ld4_sld8_defconfig  | 1 +
>  configs/uniphier_v7_defconfig| 1 +
>  configs/uniphier_v8_defconfig| 1 +
>  configs/vinco_defconfig  | 1 +
>  configs/vining_2000_defconfig| 1 +
>  configs/warp7_bl33_defconfig | 1 +
>  configs/warp7_defconfig  | 1 +
>  configs/warp_defconfig   | 1 +
>  configs/xilinx_zynqmp_mini_emmc0_defconfig   | 1 +
>  configs/xilinx_zynqmp_mini_emmc1_defconfig   | 1 +
>  

[U-Boot] [PATCH] Convert CONFIG_SUPPORT_EMMC_BOOT to Kconfig

[Alex Kiernan]

This converts the following to Kconfig:
   CONFIG_SUPPORT_EMMC_BOOT

Signed-off-by: Alex Kiernan 
---
Green travis build:

https://travis-ci.org/akiernan/u-boot/builds/521906850

Testing affected boards for configuration changes:

  boards.cfg is up to date. Nothing to do.
  Summary of 3 commits for 95 boards (4 threads, 1 job per thread)
  01: Merge tag 'u-boot-imx-20190415' of git://git.denx.de/u-boot-imx
 aarch64:  w+   xilinx_zynqmp_mini_emmc1 xilinx_zynqmp_mini_emmc0 
xilinx_zynqmp_mini_qspi clearfog_gt_8k imx8qxp_mek xilinx_zynqmp_mini 
xilinx_zynqmp_mini_nand imx8mq_evk
 arm:  w+   cm_t54 cl-som-imx7 marsboard clearfog apalis_imx6 warp7 
pico-hobbit-imx7d pico-pi-imx6ul dms-ba16 arndale riotboard pico-hobbit-imx6ul 
colibri_imx7 pico-imx7d xpress_spl opos6uldev warp7_bl33 imx6dl_mamoj ge_bx50v3 
display5 mx7dsabresd_qspi display5_factory colibri_imx7_emmc gwventana_nand 
mx7dsabresd gwventana_gw5904 gwventana_emmc am57xx_hs_evm_usb omap5_uevm 
brppt1_spi xilinx_zynqmp_r5 vinco mx6sabresd warp riotboard_spl vining_2000 
zc5601 zc5202 xpress pico-imx6ul dms-ba16-1g pico-pi-imx7d
  02: configs: Resync with savedefconfig
  03: Convert CONFIG_SUPPORT_EMMC_BOOT to Kconfig

 README   | 3 ---
 configs/am57xx_evm_defconfig | 1 +
 configs/am57xx_hs_evm_defconfig  | 1 +
 configs/am57xx_hs_evm_usb_defconfig  | 1 +
 configs/apalis-tk1_defconfig | 1 +
 configs/apalis_imx6_defconfig| 1 +
 configs/arndale_defconfig| 1 +
 configs/avnet_ultra96_rev1_defconfig | 1 +
 configs/cl-som-imx7_defconfig| 1 +
 configs/clearfog_defconfig   | 1 +
 configs/cm_t54_defconfig | 1 +
 configs/colibri_imx6_defconfig   | 1 +
 configs/colibri_imx7_emmc_defconfig  | 1 +
 configs/display5_defconfig   | 1 +
 configs/display5_factory_defconfig   | 1 +
 configs/dms-ba16-1g_defconfig| 1 +
 configs/dms-ba16_defconfig   | 1 +
 configs/dra7xx_evm_defconfig | 1 +
 configs/dra7xx_hs_evm_defconfig  | 1 +
 configs/dra7xx_hs_evm_usb_defconfig  | 1 +
 configs/edison_defconfig | 1 +
 configs/ge_bx50v3_defconfig  | 1 +
 configs/gwventana_emmc_defconfig | 1 +
 configs/gwventana_gw5904_defconfig   | 1 +
 configs/gwventana_nand_defconfig | 1 +
 configs/imx6dl_mamoj_defconfig   | 1 +
 configs/imx8mq_evk_defconfig | 1 +
 configs/imx8qxp_mek_defconfig| 1 +
 configs/liteboard_defconfig  | 1 +
 configs/mt7623n_bpir2_defconfig  | 1 +
 configs/mx6sabresd_defconfig | 1 +
 configs/mx7dsabresd_defconfig| 1 +
 configs/mx7dsabresd_qspi_defconfig   | 1 +
 configs/mx7ulp_evk_defconfig | 1 +
 configs/mx7ulp_evk_plugin_defconfig  | 1 +
 configs/odroid-xu3_defconfig | 1 +
 configs/omap5_uevm_defconfig | 1 +
 configs/opos6uldev_defconfig | 1 +
 configs/peach-pi_defconfig   | 1 +
 configs/peach-pit_defconfig  | 1 +
 configs/pico-hobbit-imx6ul_defconfig | 1 +
 configs/pico-hobbit-imx7d_defconfig  | 1 +
 configs/pico-imx6ul_defconfig| 1 +
 configs/pico-imx7d_defconfig | 1 +
 configs/pico-pi-imx6ul_defconfig | 1 +
 configs/pico-pi-imx7d_defconfig  | 1 +
 configs/riotboard_defconfig  | 1 +
 configs/riotboard_spl_defconfig  | 1 +
 configs/smdk5250_defconfig   | 1 +
 configs/smdk5420_defconfig   | 1 +
 configs/snow_defconfig   | 1 +
 configs/spring_defconfig | 1 +
 configs/stm32mp15_basic_defconfig| 1 +
 configs/stm32mp15_trusted_defconfig  | 1 +
 configs/uniphier_ld4_sld8_defconfig  | 1 +
 configs/uniphier_v7_defconfig| 1 +
 configs/uniphier_v8_defconfig| 1 +
 configs/vinco_defconfig  | 1 +
 configs/vining_2000_defconfig| 1 +
 configs/warp7_bl33_defconfig | 1 +
 configs/warp7_defconfig  | 1 +
 configs/warp_defconfig   | 1 +
 configs/xilinx_zynqmp_mini_emmc0_defconfig   | 1 +
 configs/xilinx_zynqmp_mini_emmc1_defconfig   | 1 +
 configs/xilinx_zynqmp_zc1275_revB_defconfig  | 1 +
 configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 1 +
 configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig | 1 +
 

[U-Boot] relationship between "ARM_DCC" and "DEBUG_UART_ARM_DCC"?

[Robert P. J. Day]

  just noticed the oddness regarding those two Kbuild symbols:

$ git grep ARM_DCC
arch/x86/include/asm/acpi_table.h:#define ACPI_DBG2_ARM_DCC   0x000F
configs/zynq_cse_qspi_defconfig:CONFIG_DEBUG_UART_ARM_DCC=y
drivers/serial/Kconfig:config DEBUG_UART_ARM_DCC
drivers/serial/Makefile:obj-$(CONFIG_ARM_DCC) += arm_dcc.o
drivers/serial/arm_dcc.c:#ifdef CONFIG_DEBUG_UART_ARM_DCC
include/configs/xilinx_versal.h:#define CONFIG_ARM_DCC
include/configs/xilinx_zynqmp.h:#define CONFIG_ARM_DCC
include/configs/zynq-common.h:#define CONFIG_ARM_DCC
scripts/config_whitelist.txt:CONFIG_ARM_DCC
$

  strangely(?), there is a Kbuild config directive for the latter:

  drivers/serial/Kconfig:config DEBUG_UART_ARM_DCC

but not the former, which is just hardcoded in some xilinx-associated
header files. is this deliberate? it just seems ... weird.

rday

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 http://crashcourse.ca

Twitter:   http://twitter.com/rpjday
LinkedIn:   http://ca.linkedin.com/in/rpjday

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[U-Boot] [GIT] Pull request: u-boot-dfu (14.04.2019)

[Lukasz Majewski]

Dear Marek,

The following changes since commit
1f4ae66eaab29bfb5d1eb44996f7826c9cd01ed1:

  Merge tag 'arc-for-2019.07' of git://git.denx.de/u-boot-arc
  (2019-04-18 12:12:16 -0400)

are available in the git repository at:

  git://git.denx.de/u-boot-dfu.git 

for you to fetch changes up to 5e6288f7b5a0863b09b9d375267d29d3545cd3b3:

  usb: dwc2: fix gadget disconnect (2019-04-19 08:29:23 +0200)


Alex Kiernan (1):
  fastboot: Replace literal 32 with PART_NAME_LEN

Andy Shevchenko (1):
  dfu: Avoid declaring unused variables and absent parameters

Eugeniu Rosca (3):
  fastboot: getvar: correct/rename "has_slot" to "has-slot"
  fastboot: Improve error reporting on 'getvar partition-{size,
type}' fastboot: add support for 'getvar platform'

Fabrice Gasnier (1):
  usb: dwc2: fix gadget disconnect

Patrice Chotard (1):
  usb: dwc2_udc_otg: Add tx_fifo_sz array support

Patrick Delaunay (16):
  phy: usbphyc: remove unused variable index
  phy: usbphyc: update xlate with DT binding
  phy: usbphyc: Binding update of vdda supply
  phy: usbphyc: move vdda1v1 and vdda1v8 in phy_init
  phy: usbphyc: increase PLL wait timeout
  usb: dwc2: remove unused variable regs_otg
  usb: dwc2: convert driver to DM_USB_GADGET
  usb: dwc2: force reset assert before to probe the driver
  usb: dwc2: Add force-b-session-valid support
  usb: dwc2: Add function for session B check
  usb: dwc2_udc_otg: Read MAX_HW_ENDPOINT from HWCFG4 register
  usb: dwc2: add support for STM32MP1
  stm32mp1: remove CONFIG_USB_DWC2, HOST support for USBO
  stm32mp1: migrate USBOTG device to driver model
  stm32mp1: add stusb1600 support for DK1 and DK2 board
  usb: reload watchdog during ums command

Peng Fan (1):
  MLK-12883 usb: limit USB_MAX_XFER_BLK to 256

 arch/arm/dts/stm32mp157-pinctrl.dtsi   |   7 ++
 arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi   |   3 +-
 arch/arm/dts/stm32mp157a-dk1.dts   |  34 +++-
 arch/arm/dts/stm32mp157c-ed1.dts   |   8 --
 arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi   |   1 +
 arch/arm/dts/stm32mp157c.dtsi  |   5 +-
 board/st/stm32mp1/stm32mp1.c   | 185
 +++--
 cmd/dfu.c  |   3 +
 cmd/usb_mass_storage.c |   3 +
 common/usb_storage.c   |   6 +-
 configs/stm32mp15_basic_defconfig  |   2 +-
 configs/stm32mp15_trusted_defconfig|   2 +-
 doc/device-tree-bindings/phy/phy-stm32-usbphyc.txt |   4 +-
 doc/device-tree-bindings/usb/dwc2.txt  |  58 +
 drivers/fastboot/fb_getvar.c   |  16 +++-
 drivers/fastboot/fb_mmc.c  |  10 +--
 drivers/phy/phy-stm32-usbphyc.c| 111
 +
 drivers/usb/gadget/dwc2_udc_otg.c  | 388
 
--
 drivers/usb/gadget/dwc2_udc_otg_priv.h |   1 -
 drivers/usb/gadget/dwc2_udc_otg_regs.h |  37 +++--
 drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c |  14 +++-
 include/usb/dwc2_udc.h |   7 ++ 22 files
 changed, 675 insertions(+), 230 deletions(-) create mode 100644
 doc/device-tree-bindings/usb/dwc2.txt


Travis-CI:
https://travis-ci.org/lmajewski/u-boot-dfu/builds/522040767


Best regards,

Lukasz Majewski

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Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lu...@denx.de


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Re: [U-Boot] [RFC PATCH v3] usb: limit USB_MAX_XFER_BLK to 256

[Marek Vasut]

On 4/18/19 1:45 AM, Marcel Ziswiler wrote:
> From: Peng Fan 
> 
> For Some USB mass storage devices, such as:
> "
>  - Kingston DataTraveler 2.0 001D7D06CF09B04199C7B3EA
>  - Class: (from Interface) Mass Storage
>  - PacketSize: 64  Configurations: 1
>  - Vendor: 0x0930  Product 0x6545 Version 1.16
> "
> When `usb read 0x8000 0 0x2000`, we met
> "EHCI timed out on TD - token=0x80008d80".
> 
> The devices does not support scsi VPD page, we are not able
> to get the maximum transfer length for READ(10)/WRITE(10).
> 
> So we limit this to 256 blocks as READ(6).
> 
> Signed-off-by: Peng Fan 
> Acked-by: Marcel Ziswiler 
> (cherry picked from commit df0052575b2bc9d66ae73584768e1a457ed5d914)
> 
> Signed-off-by: Marcel Ziswiler 
> 
> ---
> This comes from NXP's downstream and has proven to tremendously improve
> the situation with those odd USB mass storage aka memory sticks. This is
> why I post it here asking whether or not this may be something
> benefiting more people. Any feedback and suggestions are welcome.
> 
> Changes in v3:
> - Drop the reference to the NXP internal MLK-xxx tracking number as
>   suggested by Peng.
> 
> Changes in v2:
> - Fixed spelling in comment as suggested by Igor.
> 
>  common/usb_storage.c | 6 +-
>  1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/common/usb_storage.c b/common/usb_storage.c
> index 8c889bb1a6..4e284645f5 100644
> --- a/common/usb_storage.c
> +++ b/common/usb_storage.c
> @@ -949,7 +949,11 @@ static void usb_stor_set_max_xfer_blk(struct usb_device 
> *udev,
>* there is enough free heap space left, but the SCSI READ(10) and
>* WRITE(10) commands are limited to 65535 blocks.
>*/
> - blk = USHRT_MAX;
> + /*
> +  * Some USB mass storage devices have issues, limiting this to 256
> +  * fixes this.
> +  */
> + blk = 256;

Seems like the previous comment, right above this new one, contradicts
this claim. Please update the original comment.

That said, there was an attempt to fix this properly by using adaptive
block length implementation, which would not impact devices that are not
broken. This hack above will degrade performance of such good devices.
Maybe you can resuscitate that adaptive approach instead ?

>  #else
>   blk = 20;
>  #endif
> 


-- 
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH] phycore-pcl060: U-boot support for Phytec phyCORE PCL060

[Marek Vasut]

On 4/18/19 5:01 PM, Niel Fourie wrote:
> Support for Phytech phyCORE AM335x R2 SOM (PCL060) on the Phytec
> phyBOARD-Wega AM335x.
> 
> CPU  : AM335X-GP rev 2.1
> Model: Phytec AM335x phyBOARD-WEGA
> DRAM:  256 MiB
> NAND:  256 MiB
> MMC:   OMAP SD/MMC: 0
> eth0: ethernet@4a10
> 
> Working:
>  - Eth0
>  - i2C
>  - MMC/SD
>  - NAND
>  - UART
>  - USB (host)
> 
> Signed-off-by: Niel Fourie 
> ---
>  arch/arm/dts/Makefile|   3 +-
>  arch/arm/dts/am335x-phycore-som.dtsi | 327 ++
>  arch/arm/dts/am335x-wega-rdk-u-boot.dtsi |  35 +++
>  arch/arm/dts/am335x-wega-rdk.dts |  23 ++
>  arch/arm/dts/am335x-wega.dtsi| 231 +++

The DTs come from Linux kernel, but which version of Linux ?
Which exact commit ? Did you modify them in any way ?

[...]

> diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
> index d29f1ca0b5..9336439340 100644
> --- a/arch/arm/mach-omap2/Kconfig
> +++ b/arch/arm/mach-omap2/Kconfig
> @@ -186,6 +186,7 @@ source "board/ti/am43xx/Kconfig"
>  source "board/ti/am335x/Kconfig"
>  source "board/compulab/cm_t335/Kconfig"
>  source "board/compulab/cm_t43/Kconfig"
> +source "board/phytec/phycore_pcl060/Kconfig"

Here [1] it says the name of the SoM is PCM-060 , what is PCL-060 ?

[1]
https://www.phytec.eu/product-eu/system-on-modules/phycore-am335x-download/
 [...]

> diff --git a/board/phytec/phycore_pcl060/Kconfig 
> b/board/phytec/phycore_pcl060/Kconfig
> new file mode 100644
> index 00..bdd1a9b6e0
> --- /dev/null
> +++ b/board/phytec/phycore_pcl060/Kconfig
> @@ -0,0 +1,19 @@
> +if TARGET_PCL060
> +
> +config SYS_BOARD
> + default "phycore_pcl060"
> +
> +config SYS_VENDOR
> + default "phytec"
> +
> +config SYS_SOC
> + default "am33xx"
> +
> +config SYS_CONFIG_NAME
> + default "phycore_pcl060"
> +
> +config PCL060_DDR_SIZE
> + int "DDR size (in MiB) of Phycore PCL060 module"
> + default 256

DRAM size should come from DT, we don't need another custom config
option. Look at fdtdec_setup_mem_size_base() and
fdtdec_setup_memory_banksize().

[...]

> diff --git a/board/phytec/phycore_pcl060/board.c 
> b/board/phytec/phycore_pcl060/board.c
> new file mode 100644
> index 00..01fe13e959
> --- /dev/null
> +++ b/board/phytec/phycore_pcl060/board.c
> @@ -0,0 +1,340 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * board.c
> + *
> + * Board functions for Phytec phyCORE-AM335x R2 (pcl060) based boards
> + *
> + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
> + * Copyright (C) 2013 Lars Poeschel, Lemonage Software GmbH
> + * Copyright (C) 2015 Wadim Egorov, PHYTEC Messtechnik GmbH
> + * Copyright (C) 2019 DENX Software Engineering GmbH
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include "board.h"
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
> +
> +#ifdef CONFIG_SPL_BUILD
> +
> +#ifdef CONFIG_SPL_OS_BOOT

#if CONFIG_IS_ENABLED(OS_BOOT)

> +int spl_start_uboot(void)
> +{
> + return 1;
> +}
> +#endif
> +/* DDR RAM defines */
> +#define DDR_CLK_MHZ  400 /* DDR_DPLL_MULT value */
> +
> +#define OSC  (V_OSCK / 100)
> +const struct dpll_params dpll_ddr = {
> + DDR_CLK_MHZ, OSC - 1, 1, -1, -1, -1, -1};
> +
> +const struct dpll_params *get_dpll_ddr_params(void)
> +{
> + return _ddr;
> +}
> +
> +const struct ctrl_ioregs ioregs = {
> + .cm0ioctl   = 0x18B,
> + .cm1ioctl   = 0x18B,
> + .cm2ioctl   = 0x18B,
> + .dt0ioctl   = 0x18B,
> + .dt1ioctl   = 0x18B,
> +};
> +
> +static const struct cmd_control ddr3_cmd_ctrl_data = {
> + .cmd0csratio = 0x80,
> + .cmd0iclkout = 0x0,
> +
> + .cmd1csratio = 0x80,
> + .cmd1iclkout = 0x0,
> +
> + .cmd2csratio = 0x80,
> + .cmd2iclkout = 0x0,
> +};
> +
> +#if CONFIG_PCL060_DDR_SIZE == 256

Get the DRAM layout from DT and apply EMIF settings accordingly.

[...]

> diff --git a/include/configs/phycore_pcl060.h 
> b/include/configs/phycore_pcl060.h
> new file mode 100644
> index 00..982c96b267
> --- /dev/null
> +++ b/include/configs/phycore_pcl060.h
> @@ -0,0 +1,141 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * phycore_pcl060.h
> + *
> + * Phytec phyCORE-AM335x (pcl060) boards information header
> + *
> + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
> + * Copyright (C) 2013 Lars Poeschel, Lemonage Software GmbH
> + * Copyright (C) 2019 DENX Software Engineering GmbH
> + */
> +
> +#ifndef __CONFIG_PCL060_H
> +#define __CONFIG_PCL060_H
> +
> +#include 
> +
> +#define CONFIG_ENV_SIZE  (128 << 10) /* 128 KiB */

Re: [U-Boot] [PATCH 0/2] Add Kconfig to disable cache ops

[Vignesh Raghavendra]

Hi,

On 08/04/19 10:32 PM, Vignesh Raghavendra wrote:
> This series adds a Kconfig to disable cache maintenance operations on
> a coherent architectures. And disable cache flush/invalidate ops for
> SPL/U-Boot code running on A53 core of AM654 SoC(which is IO coherent)
> 
> Vignesh Raghavendra (2):
>   arch: armv8: Provide a way to disable cache maintenance ops
>   board: ti: am654: select SYS_DISABLE_DCACHE_OPS for arm64 build

Please ignore this patches. I found an issue with the patches. Will post
a v2.

> 
>  arch/Kconfig  |  9 +
>  arch/arm/cpu/armv8/cache_v8.c | 18 ++
>  board/ti/am65x/Kconfig|  1 +
>  3 files changed, 28 insertions(+)
> 

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Re: [U-Boot] [RESEND PATCH] usb: Select USB_MUSB_DSPS with USB_MUSB_TI

[Marek Vasut]

On 4/18/19 1:10 PM, Alex Kiernan wrote:
> USB_MUSB_TI requires USB_MUSB_DSPS, failing at link time if it's not
> selected:
> 
>   drivers/usb/musb-new/built-in.o: In function 
> `ti_musb_host_ofdata_to_platdata':
>   drivers/usb/musb-new/ti-musb.c:193: undefined reference to `musb_dsps_ops'
> 
> or if OF_CONTROL is not selected:
> 
>   arch/arm/mach-omap2/built-in.o:(.data.usb0+0x24): undefined reference to 
> `musb_dsps_ops'
> 
> Reviewed-by: Hannes Schmelzer 
> Tested-by: Hannes Schmelzer 
> Signed-off-by: Alex Kiernan 

Applied, thanks.

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Re: [U-Boot] [PATCH v3] spi: Zap mxs_spi driver-related code

[Marek Vasut]

On 4/19/19 8:55 AM, Jagan Teki wrote:
> Dropped
> - mxs_spi driver
> - CONFIG_MXS_SPI
> 
> Dropped due to:
> - no active updates
> - no dm conversion
> - multiple pings for asking dm-conversion

This is the first information I received ... sigh.
+CC Mans, he was working on this platform before.

> - no response for dm converted patch
> - driver-model migration expiry
> 
> Cc: Marek Vasut 
> Cc: Fabio Estevam 
> Signed-off-by: Jagan Teki 
> ---
> Changes for v3:
> - rebase on master
> 
>  configs/bg0900_defconfig|   1 -
>  configs/mx28evk_auart_console_defconfig |   1 -
>  configs/mx28evk_defconfig   |   1 -
>  configs/mx28evk_nand_defconfig  |   1 -
>  configs/mx28evk_spi_defconfig   |   1 -
>  drivers/spi/Kconfig |   6 -
>  drivers/spi/Makefile|   1 -
>  drivers/spi/mxs_spi.c   | 358 
>  8 files changed, 370 deletions(-)
>  delete mode 100644 drivers/spi/mxs_spi.c
> 
> diff --git a/configs/bg0900_defconfig b/configs/bg0900_defconfig
> index 2c4d3e3d54..f8421ef304 100644
> --- a/configs/bg0900_defconfig
> +++ b/configs/bg0900_defconfig
> @@ -40,5 +40,4 @@ CONFIG_SPI_FLASH_STMICRO=y
>  CONFIG_MII=y
>  CONFIG_CONS_INDEX=0
>  CONFIG_SPI=y
> -CONFIG_MXS_SPI=y
>  CONFIG_OF_LIBFDT=y
> diff --git a/configs/mx28evk_auart_console_defconfig 
> b/configs/mx28evk_auart_console_defconfig
> index c54b933e53..d976ea584c 100644
> --- a/configs/mx28evk_auart_console_defconfig
> +++ b/configs/mx28evk_auart_console_defconfig
> @@ -51,7 +51,6 @@ CONFIG_SPI_FLASH_SST=y
>  CONFIG_MII=y
>  CONFIG_CONS_INDEX=0
>  CONFIG_SPI=y
> -CONFIG_MXS_SPI=y
>  CONFIG_USB=y
>  CONFIG_USB_EHCI_HCD=y
>  CONFIG_USB_STORAGE=y
> diff --git a/configs/mx28evk_defconfig b/configs/mx28evk_defconfig
> index 187467d3db..40ab39ccf1 100644
> --- a/configs/mx28evk_defconfig
> +++ b/configs/mx28evk_defconfig
> @@ -51,7 +51,6 @@ CONFIG_SPI_FLASH_SST=y
>  CONFIG_MII=y
>  CONFIG_CONS_INDEX=0
>  CONFIG_SPI=y
> -CONFIG_MXS_SPI=y
>  CONFIG_USB=y
>  CONFIG_USB_EHCI_HCD=y
>  CONFIG_USB_STORAGE=y
> diff --git a/configs/mx28evk_nand_defconfig b/configs/mx28evk_nand_defconfig
> index 7d891e7934..0d2afbbdb0 100644
> --- a/configs/mx28evk_nand_defconfig
> +++ b/configs/mx28evk_nand_defconfig
> @@ -50,7 +50,6 @@ CONFIG_SPI_FLASH_SST=y
>  CONFIG_MII=y
>  CONFIG_CONS_INDEX=0
>  CONFIG_SPI=y
> -CONFIG_MXS_SPI=y
>  CONFIG_USB=y
>  CONFIG_USB_EHCI_HCD=y
>  CONFIG_USB_STORAGE=y
> diff --git a/configs/mx28evk_spi_defconfig b/configs/mx28evk_spi_defconfig
> index cb5b1b3b75..b9ea4934bb 100644
> --- a/configs/mx28evk_spi_defconfig
> +++ b/configs/mx28evk_spi_defconfig
> @@ -50,7 +50,6 @@ CONFIG_SPI_FLASH_SST=y
>  CONFIG_MII=y
>  CONFIG_CONS_INDEX=0
>  CONFIG_SPI=y
> -CONFIG_MXS_SPI=y
>  CONFIG_USB=y
>  CONFIG_USB_EHCI_HCD=y
>  CONFIG_USB_STORAGE=y
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> index 7043b5c0f6..955da8db64 100644
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -370,12 +370,6 @@ config MXC_SPI
> Enable the MXC SPI controller driver. This driver can be used
> on various i.MX SoCs such as i.MX31/35/51/6/7.
>  
> -config MXS_SPI
> - bool "MXS SPI Driver"
> - help
> -   Enable the MXS SPI controller driver. This driver can be used
> -   on the i.MX23 and i.MX28 SoCs.
> -
>  config OMAP3_SPI
>   bool "McSPI driver for OMAP"
>   help
> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
> index 25add2812d..055ef99dc9 100644
> --- a/drivers/spi/Makefile
> +++ b/drivers/spi/Makefile
> @@ -40,7 +40,6 @@ obj-$(CONFIG_MT7621_SPI) += mt7621_spi.o
>  obj-$(CONFIG_MSCC_BB_SPI) += mscc_bb_spi.o
>  obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o
>  obj-$(CONFIG_MXC_SPI) += mxc_spi.o
> -obj-$(CONFIG_MXS_SPI) += mxs_spi.o
>  obj-$(CONFIG_ATCSPI200_SPI) += atcspi200_spi.o
>  obj-$(CONFIG_OMAP3_SPI) += omap3_spi.o
>  obj-$(CONFIG_PIC32_SPI) += pic32_spi.o
> diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c
> deleted file mode 100644
> index 5065e407f8..00
> --- a/drivers/spi/mxs_spi.c
> +++ /dev/null
> @@ -1,358 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * Freescale i.MX28 SPI driver
> - *
> - * Copyright (C) 2011 Marek Vasut 
> - * on behalf of DENX Software Engineering GmbH
> - *
> - * NOTE: This driver only supports the SPI-controller chipselects,
> - *   GPIO driven chipselects are not supported.
> - */
> -
> -#include 
> -#include 
> -#include 
> -#include 
> -#include 
> -#include 
> -#include 
> -#include 
> -#include 
> -#include 
> -
> -#define  MXS_SPI_MAX_TIMEOUT 100
> -#define  MXS_SPI_PORT_OFFSET 0x2000
> -#define MXS_SSP_CHIPSELECT_MASK  0x0030
> -#define MXS_SSP_CHIPSELECT_SHIFT 20
> -
> -#define MXSSSP_SMALL_TRANSFER512
> -
> -struct mxs_spi_slave {
> - struct spi_slaveslave;
> - uint32_tmax_khz;
> - uint32_tmode;
> - struct mxs_ssp_regs 

Re: [U-Boot] [U-Boot-DM] [PATCH] drivers: serial: lpuart: Enable Little Endian Support

[Marek Vasut]

On 4/18/19 2:30 PM, Vabhav Sharma wrote:
> Hello Maintainers,
> A gentle reminder to merge the changes.

Next time, use
$ ./scripts/get_maintainer.pl -f drivers/serial/serial_lpuart.c
and actually CC the maintainers.

> Regards,
> Vabhav
> 
>> -Original Message-
>> From: Vabhav Sharma
>> Sent: Thursday, January 31, 2019 5:38 PM
>> To: u-boot@lists.denx.de; u-boot...@lists.denx.de
>> Cc: Vabhav Sharma 
>> Subject: [PATCH] drivers: serial: lpuart: Enable Little Endian Support
>>
>> By default LPUART driver with compatible string "fsl,ls1021a-lpuart"
>> support big-endian mode.On NXP SoC like LS1028A LPUART IP is little-
>> endian,Added support to Fetch LPUART IP Endianness from lpuart device-
>> tree node.
>>
>> Signed-off-by: Vabhav Sharma 
>> ---
>>  drivers/serial/serial_lpuart.c | 4 
>>  1 file changed, 4 insertions(+)
>>
>> diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c 
>> index
>> a357b00..57dd4a7 100644
>> --- a/drivers/serial/serial_lpuart.c
>> +++ b/drivers/serial/serial_lpuart.c
>> @@ -1,5 +1,6 @@
>>  // SPDX-License-Identifier: GPL-2.0+
>>  /*
>> + * Copyright 2019 NXP
>>   * Copyright 2013 Freescale Semiconductor, Inc.
>>   */
>>
>> @@ -502,6 +503,9 @@ static int lpuart_serial_ofdata_to_platdata(struct
>> udevice *dev)
>>  plat->reg = (void *)addr;
>>  plat->flags = dev_get_driver_data(dev);
>>
>> +if (fdtdec_get_bool(blob, node, "little-endian"))
>> +plat->flags &= ~LPUART_FLAG_REGMAP_ENDIAN_BIG;
>> +
>>  if (!fdt_node_check_compatible(blob, node, "fsl,ls1021a-lpuart"))
>>  plat->devtype = DEV_LS1021A;
>>  else if (!fdt_node_check_compatible(blob, node, "fsl,imx7ulp-
>> lpuart"))
>> --
>> 2.7.4
> 
> ___
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> https://lists.denx.de/listinfo/u-boot-dm
> 


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Re: [U-Boot] [PATCH v3] arm: socfpga: mailbox: Fix off-by-one error on command length checking

[Marek Vasut]

On 4/19/19 8:17 AM, Ley Foon Tan wrote:
> A mailbox command contains 1-DWORD header + arguments. The "len" variable
> only contains the length of the arguments, but not the 1-DWORD header.
> Include the length of header when checking the ring buffer space to
> prevent off-by-one error.

How long is a DWORD ? Windows API (which we have nothing to do with)
defines that as 32bit type, "typedef unsigned long DWORD;", see [1].
But the patch below fixes an off-by-one error , not off by four error ?

[1]
https://docs.microsoft.com/en-us/windows/desktop/winprog/windows-data-types

> Signed-off-by: Ley Foon Tan 
> Signed-off-by: Chee Hong Ang 
> ---
> v2->v3:
> - Update commit description.
> ---
>  arch/arm/mach-socfpga/mailbox_s10.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/mach-socfpga/mailbox_s10.c 
> b/arch/arm/mach-socfpga/mailbox_s10.c
> index 3c33223936..8363c93e90 100644
> --- a/arch/arm/mach-socfpga/mailbox_s10.c
> +++ b/arch/arm/mach-socfpga/mailbox_s10.c
> @@ -59,7 +59,7 @@ static __always_inline int mbox_fill_cmd_circular_buff(u32 
> header, u32 len,
>*/
>   if (((cin + 1) % MBOX_CMD_BUFFER_SIZE) == cout ||
>   ((MBOX_CMD_BUFFER_SIZE - cin + cout - 1) %
> -  MBOX_CMD_BUFFER_SIZE) < len)
> +  MBOX_CMD_BUFFER_SIZE) < (len + 1))
>   return -ENOMEM;
>  
>   /* write header to circular buffer */
> 


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Re: [U-Boot] [PATCH v3 3/3] arm: sunxi: h6: fix reset using r_wdog

[Clément Péron]

Hi,

On Fri, 19 Apr 2019 at 10:24, Jagan Teki  wrote:
>
> On Fri, Apr 19, 2019 at 1:23 PM Clément Péron  wrote:
> >
> > Hi,
> >
> > +Chen-Yu Tsai for test and +Icenowy because she try to contact AW
> > about this issue.
> >
> > On Wed, 17 Apr 2019 at 19:41, Clément Péron  wrote:
> > >
> > > WDOG is broken for some H6 rev. The board is not
> > > reseted correctly.
> > >
> > > Use the R_WDOG instead.
> >
> > The issue is real except on Pine H64 and Rongpin RP-H6B which seems to
> > be NOT affected.
> > Lot of users on OrangePi boards (Lite2 / One Plus and 3) are
> > complaining about this issue.
> >
> > We perform a simple watchdog test on different board :
> >
> > Chen-Yu Tsai :
> > Pine h64 = H6 V200-AWIN H6448BA 7782 => OK
> > OrangePi Lite 2 = H6 V200-AWIN H8068BA 61C2 => KO
> >
> > Martin Ayotte :
> > PineH64 = H8069BA 6892 => OK
> > Orange Pi 3 = HA047BA 69W2 => KO
> > OPiOnePlus = H7310BA 6842 => KO
> > OPiLite2 = H6448BA 6662 => KO
> >
> > Clément Péron:
> > Beelink GS1 = H6 V200-AWIN H7309BA 6842 => KO
> >
> > After the series of result, Icenowy try to reach Allwinner about this
> > issue but they seems not interested to investigate it.
> >
> > I'm not sure if it's an HW errata or if there something misconfigured
> > but the result is here WDOG doesn't make these boards reboot.
> > And this should not happens !
>
> How about Linux? same issue.
Yes, Linux use PSCI, call ATF and we have the same issue as ATF use
the watchdog to reboot.

Clement
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Re: [U-Boot] [PATCH v2 00/10] clk: imx: Add i.MX6 CLK support

[Peng Fan]

> On Fri, 19 Apr 2019 11:56:25 +0530
> Jagan Teki  wrote:
> 
> > On Fri, Apr 5, 2019 at 2:20 AM Lukasz Majewski  wrote:
> > >
> > > Hi Jagan,
> > >
> > > > On Thu, Apr 4, 2019 at 3:31 PM Lukasz Majewski 
> > > > wrote:
> > > > >
> > > > > On Thu, 4 Apr 2019 14:56:36 +0530 Jagan Teki
> > > > >  wrote:
> > > > >
> > > > > > On Thu, Apr 4, 2019 at 2:31 PM Lukasz Majewski 
> > > > > > wrote:
> > > > > > >
> > > > > > > On Tue,  2 Apr 2019 16:58:33 +0530 Jagan Teki
> > > > > > >  wrote:
> > > > > > >
> > > > > > > > This is revised version of previous i.MX6 clock management
> > > > > > > > [1].
> > > > > > > >
> > > > > > > > The main difference between previous version is
> > > > > > > > - Group the i.MX6 ccm clocks into gates and tree instead
> > > > > > > > of handling the clocks in simple way using case statement.
> > > > > > > > - use gate clocks for enable/disable management.
> > > > > > > > - use tree clocks for get/set rate or parent traverse
> > > > > > > > management.
> > > > > > > > - parent clock handling via clock type.
> > > > > > > > - traverse the parent clock using recursive functionlaity.
> > > > > > > >
> > > > > > > > The main motive behind this tree framework is to make the
> > > > > > > > clock tree management simple and useful for U-Boot
> > > > > > > > requirements instead of garbing Linux clock management
> > > > > > > > code.
> > > > > > > >
> > > > > > > > We are trying to manage the Allwinner clocks with similar
> > > > > > > > kind, so having this would really help i.MX6 as well.
> > > > > > > >
> > > > > > > > Added simple names for clock macros, but will update it in
> > > > > > > > future version.
> > > > > > > >
> > > > > > > > I have skipped ENET clocks from previous series, will add
> > > > > > > > it in future patches.
> > > > > > > >
> > > > > > > > Changes for v2:
> > > > > > > > - changed framework patches.
> > > > > > > > - add support for imx6qdl and imx6ul boards
> > > > > > > > - add clock gates, tree.
> > > > > > > >
> > > > > > > > [1] https://patchwork.ozlabs.org/cover/950964/
> > > > > > > >
> > > > > > > > Any inputs?
> > > > > > >
> > > > > > > Hmm It looks like we are doing some development in
> > > > > > > parallel.
> > > > > > >
> > > > > > > Please look into following commit [1]:
> > > > > > > https://patchwork.ozlabs.org/patch/1034051/
> > > > > > >
> > > > > > > It ports from Linux 5.0 the CCF framework for iMX6Q, which
> > > > > > > IMHO in the long term is a better approach.
> > > > > > > The code is kept simple and resembles the code from Barebox.
> > > > > > >
> > > > > > > Please correct me if I'm wrong, but the code from your work
> > > > > > > is not modeling muxes, gates and other components from Linux
> > > > > > > CCF.
> > > > > >
> > > > > > The U-Boot implementation of CLK would require as minimal and
> > > > > > simple as possible due to requirement of U-Boot itself. Hope
> > > > > > you agree this point?
> > > > >
> > > > > Now i.MX6 is using clock.c CLK implementation. If we decide to
> > > > > replace it - we shall do it in a way, which would allow us to
> > > > > follow Linux kernel. (the barebox implementation is a stripped
> > > > > CCF from Linux, the same is in patch [1]).
> > > > >
> > > > > > if yes having CCF stack code to handle all clock with
> > > > > > respective separate drivers management is may not require as
> > > > > > of now, IMHO.
> > > > >
> > > > > I do have a gut feeling, that we will end up with the need to
> > > > > have the CCF framework ported anyway. As for example imx7/8 can
> > > > > re-use muxes, gates code.
> > > >
> > > > As per my experience the main the over-ahead to handle clocks in
> > > > U-Boot if we go with separate clock drivers is for Video and
> > > > Ethernet peripherals. these are key IP's which use more clocks
> > > > from U-Boot point-of-view, others can be handle pretty
> > > > straight-forward unless if they don't have too much tree chain.
> > > >
> > > > On this series, the tree management is already supported ENET in
> > > > i.MX6, and Allwinner platforms.
> > > >
> > > > As of now, I'm thinking I can handle reset of the clocks with
> > > > similar way.
> > >
> > > But this code also supports ENET and ESDHCI clocks on i.MX6Q (as
> > > supporting those was the motivator for this work).
> > >
> > > One important thing to be aware of - the problem with SPL's
> > > footprint. The implementation with clock.c is small and simple, but
> > > doesn't scale well.
> > >
> > > >
> > > > >
> > > > > However, those are only my "feelings" after a glimpse look - I
> > > > > will look into your code more thoroughly and provide feedback.
> > > >
> > > > Please have a look, if possible check even the code size by adding
> > > > USDHC clocks.
> > >
> > > Yes, code size (especially in SPL) is an _important_ factor here.
> > >
> > > >
> > > > >
> > > > > >
> > > > > > This series is using recursive calls for handling parenting
> > > > > > stuff to handle get or set rates, which is fine for handling
> > > > > 

[U-Boot] [PATCH RFC] watchdog: Add Allwinner watchdog driver

[Jagan Teki]

This patch add watchdog driver for Allwinner SoCs.

Initial non-dm driver has send by 'Chris Blake' So I keep his
author on the driver itself.

Signed-off-by: Chris Blake 
Signed-off-by: Jagan Teki 
---
 drivers/watchdog/Kconfig |   7 ++
 drivers/watchdog/Makefile|   1 +
 drivers/watchdog/sunxi_wdt.c | 207 +++
 3 files changed, 215 insertions(+)
 create mode 100644 drivers/watchdog/sunxi_wdt.c

diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 115fc4551f..79fd58048e 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -117,6 +117,13 @@ config WDT_MTK
  The watchdog timer is stopped when initialized.
  It performs full SoC reset.
 
+config WDT_SUNXI
+   bool "Allwinner SoC watchdog support"
+   depends on WDT
+   default y if ARCH_SUNXI
+   help
+ Select this to enable watchdog timer for Allwinner SoCs.
+
 config XILINX_TB_WATCHDOG
bool "Xilinx Axi watchdog timer support"
depends on WDT
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index d901240ad1..16003a8fc6 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -27,3 +27,4 @@ obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o
 obj-$(CONFIG_MPC8xx_WATCHDOG) += mpc8xx_wdt.o
 obj-$(CONFIG_WDT_MT7621) += mt7621_wdt.o
 obj-$(CONFIG_WDT_MTK) += mtk_wdt.o
+obj-$(CONFIG_WDT_SUNXI) += sunxi_wdt.o
diff --git a/drivers/watchdog/sunxi_wdt.c b/drivers/watchdog/sunxi_wdt.c
new file mode 100644
index 00..2e7364b7bb
--- /dev/null
+++ b/drivers/watchdog/sunxi_wdt.c
@@ -0,0 +1,207 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Watchdog driver for Allwinner SoCs
+ *
+ * Copyright (C) 2019 Chris Blake 
+ * Copyright (C) 2019 Jagan Teki 
+ *
+ * Based on the linux/drivers/watchdog/sunxi_wdt.c
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#define WDT_TIMEOUT_MASK   0x0F
+#define WDT_CTRL_RELOAD((1 << 0) | (0x0a57 << 1))
+#define WDT_MODE_ENBIT(0)
+
+/*
+ * This structure stores the register offsets for different variants
+ * of Allwinner's watchdog hardware.
+ */
+struct sunxi_wdt_reg {
+   u8 wdt_ctrl;
+   u8 wdt_cfg;
+   u8 wdt_mode;
+   u8 wdt_timeout_shift;
+   u8 wdt_reset_mask;
+   u8 wdt_reset_val;
+};
+
+struct sunxi_wdt_priv {
+   void __iomem *base;
+   const struct sunxi_wdt_reg *wdt_regs;
+};
+
+/*
+ * wdt_timeout_map maps the watchdog timer interval value in seconds to
+ * the value of the register WDT_MODE at bits .wdt_timeout_shift ~ +3
+ *
+ * [timeout seconds] = register value
+ *
+ */
+static const int wdt_timeout_map[] = {
+   [1] = 0x1,  /* 1s  */
+   [2] = 0x2,  /* 2s  */
+   [3] = 0x3,  /* 3s  */
+   [4] = 0x4,  /* 4s  */
+   [5] = 0x5,  /* 5s  */
+   [6] = 0x6,  /* 6s  */
+   [8] = 0x7,  /* 8s  */
+   [10] = 0x8, /* 10s */
+   [12] = 0x9, /* 12s */
+   [14] = 0xA, /* 14s */
+   [16] = 0xB, /* 16s */
+};
+
+static int sunxi_wdt_reset(struct udevice *dev)
+{
+   struct sunxi_wdt_priv *priv = dev_get_priv(dev);
+
+   writel(WDT_CTRL_RELOAD, priv->base + priv->wdt_regs->wdt_ctrl);
+
+   return 0;
+}
+
+static int sunxi_wdt_stop(struct udevice *dev)
+{
+   struct sunxi_wdt_priv *priv = dev_get_priv(dev);
+
+   writel(0, priv->base + priv->wdt_regs->wdt_mode);
+
+   return 0;
+}
+
+static int sunxi_wdt_expire_now(struct udevice *dev, ulong flags)
+{
+   struct sunxi_wdt_priv *priv = dev_get_priv(dev);
+   u32 val;
+
+   /* Set system reset function */
+   val = readl(priv->base + priv->wdt_regs->wdt_cfg);
+   val &= ~(priv->wdt_regs->wdt_reset_mask);
+   val |= priv->wdt_regs->wdt_reset_val;
+   writel(val, priv->base + priv->wdt_regs->wdt_cfg);
+
+   /* Set lowest timeout and enable watchdog */
+   val = readl(priv->base + priv->wdt_regs->wdt_mode);
+   val &= (WDT_TIMEOUT_MASK << priv->wdt_regs->wdt_timeout_shift);
+   val |= WDT_MODE_EN;
+   writel(val, priv->base + priv->wdt_regs->wdt_mode);
+
+   /*
+* Restart the watchdog. The default (and lowest) interval
+* value for the watchdog is 0.5s.
+*/
+   writel(WDT_CTRL_RELOAD, priv->base + priv->wdt_regs->wdt_ctrl);
+
+   while (1) {
+   mdelay(5);
+   val = readl(priv->base + priv->wdt_regs->wdt_mode);
+   val |= WDT_MODE_EN;
+   writel(val, priv->base + priv->wdt_regs->wdt_mode);
+   }
+
+   return 0;
+}
+
+static void sunxi_wdt_set_timeout(struct udevice *dev, unsigned int timeout)
+{
+   struct sunxi_wdt_priv *priv = dev_get_priv(dev);
+   u32 reg;
+
+   if (wdt_timeout_map[timeout] == 0)
+   timeout++;
+
+   reg = readl(priv->base + priv->wdt_regs->wdt_mode);
+   reg &= (WDT_TIMEOUT_MASK << priv->wdt_regs->wdt_timeout_shift);
+   reg |= wdt_timeout_map[timeout] << priv->wdt_regs->wdt_timeout_shift;
+   writel(reg, 

Re: [U-Boot] [PATCH v3 3/3] arm: sunxi: h6: fix reset using r_wdog

[Jagan Teki]

On Fri, Apr 19, 2019 at 1:23 PM Clément Péron  wrote:
>
> Hi,
>
> +Chen-Yu Tsai for test and +Icenowy because she try to contact AW
> about this issue.
>
> On Wed, 17 Apr 2019 at 19:41, Clément Péron  wrote:
> >
> > WDOG is broken for some H6 rev. The board is not
> > reseted correctly.
> >
> > Use the R_WDOG instead.
>
> The issue is real except on Pine H64 and Rongpin RP-H6B which seems to
> be NOT affected.
> Lot of users on OrangePi boards (Lite2 / One Plus and 3) are
> complaining about this issue.
>
> We perform a simple watchdog test on different board :
>
> Chen-Yu Tsai :
> Pine h64 = H6 V200-AWIN H6448BA 7782 => OK
> OrangePi Lite 2 = H6 V200-AWIN H8068BA 61C2 => KO
>
> Martin Ayotte :
> PineH64 = H8069BA 6892 => OK
> Orange Pi 3 = HA047BA 69W2 => KO
> OPiOnePlus = H7310BA 6842 => KO
> OPiLite2 = H6448BA 6662 => KO
>
> Clément Péron:
> Beelink GS1 = H6 V200-AWIN H7309BA 6842 => KO
>
> After the series of result, Icenowy try to reach Allwinner about this
> issue but they seems not interested to investigate it.
>
> I'm not sure if it's an HW errata or if there something misconfigured
> but the result is here WDOG doesn't make these boards reboot.
> And this should not happens !

How about Linux? same issue.
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Re: [U-Boot] [PATCH v2 00/10] clk: imx: Add i.MX6 CLK support

[Lukasz Majewski]

On Fri, 19 Apr 2019 11:56:25 +0530
Jagan Teki  wrote:

> On Fri, Apr 5, 2019 at 2:20 AM Lukasz Majewski  wrote:
> >
> > Hi Jagan,
> >  
> > > On Thu, Apr 4, 2019 at 3:31 PM Lukasz Majewski 
> > > wrote:  
> > > >
> > > > On Thu, 4 Apr 2019 14:56:36 +0530
> > > > Jagan Teki  wrote:
> > > >  
> > > > > On Thu, Apr 4, 2019 at 2:31 PM Lukasz Majewski 
> > > > > wrote:  
> > > > > >
> > > > > > On Tue,  2 Apr 2019 16:58:33 +0530
> > > > > > Jagan Teki  wrote:
> > > > > >  
> > > > > > > This is revised version of previous i.MX6 clock management
> > > > > > > [1].
> > > > > > >
> > > > > > > The main difference between previous version is
> > > > > > > - Group the i.MX6 ccm clocks into gates and tree instead
> > > > > > > of handling the clocks in simple way using case statement.
> > > > > > > - use gate clocks for enable/disable management.
> > > > > > > - use tree clocks for get/set rate or parent traverse
> > > > > > > management.
> > > > > > > - parent clock handling via clock type.
> > > > > > > - traverse the parent clock using recursive functionlaity.
> > > > > > >
> > > > > > > The main motive behind this tree framework is to make the
> > > > > > > clock tree management simple and useful for U-Boot
> > > > > > > requirements instead of garbing Linux clock management
> > > > > > > code.
> > > > > > >
> > > > > > > We are trying to manage the Allwinner clocks with similar
> > > > > > > kind, so having this would really help i.MX6 as well.
> > > > > > >
> > > > > > > Added simple names for clock macros, but will update it in
> > > > > > > future version.
> > > > > > >
> > > > > > > I have skipped ENET clocks from previous series, will add
> > > > > > > it in future patches.
> > > > > > >
> > > > > > > Changes for v2:
> > > > > > > - changed framework patches.
> > > > > > > - add support for imx6qdl and imx6ul boards
> > > > > > > - add clock gates, tree.
> > > > > > >
> > > > > > > [1] https://patchwork.ozlabs.org/cover/950964/
> > > > > > >
> > > > > > > Any inputs?  
> > > > > >
> > > > > > Hmm It looks like we are doing some development in
> > > > > > parallel.
> > > > > >
> > > > > > Please look into following commit [1]:
> > > > > > https://patchwork.ozlabs.org/patch/1034051/
> > > > > >
> > > > > > It ports from Linux 5.0 the CCF framework for iMX6Q, which
> > > > > > IMHO in the long term is a better approach.
> > > > > > The code is kept simple and resembles the code from Barebox.
> > > > > >
> > > > > > Please correct me if I'm wrong, but the code from your work
> > > > > > is not modeling muxes, gates and other components from
> > > > > > Linux CCF.  
> > > > >
> > > > > The U-Boot implementation of CLK would require as minimal and
> > > > > simple as possible due to requirement of U-Boot itself. Hope
> > > > > you agree this point?  
> > > >
> > > > Now i.MX6 is using clock.c CLK implementation. If we decide to
> > > > replace it - we shall do it in a way, which would allow us to
> > > > follow Linux kernel. (the barebox implementation is a stripped
> > > > CCF from Linux, the same is in patch [1]).
> > > >  
> > > > > if yes having CCF stack code to handle all clock with
> > > > > respective separate drivers management is may not require as
> > > > > of now, IMHO.  
> > > >
> > > > I do have a gut feeling, that we will end up with the need to
> > > > have the CCF framework ported anyway. As for example imx7/8 can
> > > > re-use muxes, gates code.  
> > >
> > > As per my experience the main the over-ahead to handle clocks in
> > > U-Boot if we go with separate clock drivers is for Video and
> > > Ethernet peripherals. these are key IP's which use more clocks
> > > from U-Boot point-of-view, others can be handle pretty
> > > straight-forward unless if they don't have too much tree chain.
> > >
> > > On this series, the tree management is already supported ENET in
> > > i.MX6, and Allwinner platforms.
> > >
> > > As of now, I'm thinking I can handle reset of the clocks with
> > > similar way.  
> >
> > But this code also supports ENET and ESDHCI clocks on i.MX6Q (as
> > supporting those was the motivator for this work).
> >
> > One important thing to be aware of - the problem with SPL's
> > footprint. The implementation with clock.c is small and simple, but
> > doesn't scale well.
> >  
> > >  
> > > >
> > > > However, those are only my "feelings" after a glimpse look - I
> > > > will look into your code more thoroughly and provide feedback.  
> > >
> > > Please have a look, if possible check even the code size by adding
> > > USDHC clocks.  
> >
> > Yes, code size (especially in SPL) is an _important_ factor here.
> >  
> > >  
> > > >  
> > > > >
> > > > > This series is using recursive calls for handling parenting
> > > > > stuff to handle get or set rates, which is fine for handling
> > > > > clock tree management as far as U-Boot point-of-view. We have
> > > > > faced similar situation as I explained in commit message
> > > > > about Allwinner clocks [2] and we ended up going this way.  

Re: [U-Boot] [PATCH v2 05/10] clk: imx: Add imx6q clock tree support

[Lukasz Majewski]

Hi Jagan,

> i.MX6 clock control module comprise of parent clocks, gates,
> multiplexers, dividers, PODF, PLL, fixed rate and etc.
> 
> So, the U-Boot implementation of ccm has divided into gates and tree.
> 
> 1) gate clocks are generic clock configuration of enable/disable bit
> management which can be handle via imx6_clock_gate.
> 2) tree clocks are handle via tree clock management where it link the
> clocks based on the parent clock which usually required to get and
> set the clock rates.

If I understood the patch series:

The clock hierarchy has been flattened to only two kinds of elements:
gates and "tree".

I'm not sure if we will not find this not enough in the future when one
wants to implement/use video/USB/other clocks.

For example only pllv3 type has several variants:

+enum imx_pllv3_type {
+   IMX_PLLV3_GENERIC,
+   IMX_PLLV3_SYS,
+   IMX_PLLV3_USB,
+   IMX_PLLV3_USB_VF610,
+   IMX_PLLV3_AV,
+   IMX_PLLV3_ENET,
+   IMX_PLLV3_ENET_IMX7,
+   IMX_PLLV3_SYS_VF610,
+   IMX_PLLV3_DDR_IMX7,

USB, USB_VF610 (vybrid), Generic, ENET (which is not implemented by
this series).

With porting Linux approach I'm pretty sure that I can add support for
vybrid in the future when e.g. gadget is converted to DM.

Is this also so predictable with your approach ?

> 
> This patch add tree clock management for imx6q USDHC clocks, so the
> mmc driver from imx6 can eventually use this so getting the USDHC
> clock rates.

But for USDHC you only need gate and read the clock value (which is not
so deepen hidden in the hierarchy).

> 
> Unlike Linux, U-Boot implementation may not require to maintain exact
> clock tree due to various constrains and use cases.

Another use case - ECSPI / ENET.

> So here is how
> the clock tree differs between them.
> 
> usdhc clock tree in Linux:
> -
> USDHC1 => USDHC1_PODF => USDHC1_SEL => PLL2_PFD2 => PLL2_BUS =>
> PLL2_BYPASS => PLL2 => OSC
> 
> usdhc clock tree in U-Boot:
> ---
> USDHC1 => USDHC1_PODF => USDHC1_SEL => PLL2_PFD2 => PLL2_BUS => OSC
> 
> Signed-off-by: Jagan Teki 
> ---
>  arch/arm/include/asm/arch-mx6/clock.h |  65 
>  drivers/clk/imx/clk-imx6-common.c | 103
> ++ drivers/clk/imx/clk-imx6q.c   |
> 70 + 3 files changed, 238 insertions(+)
> 
> diff --git a/arch/arm/include/asm/arch-mx6/clock.h
> b/arch/arm/include/asm/arch-mx6/clock.h index fa921a9f08..424231c691
> 100644 --- a/arch/arm/include/asm/arch-mx6/clock.h
> +++ b/arch/arm/include/asm/arch-mx6/clock.h
> @@ -21,6 +21,67 @@
>  #define MXC_CLK3232768
>  #endif
>  
> +#define OSC_24M_ULL  2400ULL
> +
> +enum imx6_clk_type {
> + IMX6_CLK_TYPE_SIMPLE= 0,
> + IMX6_CLK_TYPE_FIXED,
> + IMX6_CLK_TYPE_DIV,
> + IMX6_CLK_TYPE_MUX,
> + IMX6_CLK_TYPE_PLL_PFD,
> + IMX6_CLK_TYPE_PLL_DIV,
> +};
> +
> +/**
> + * struct imx6_clk_tree - imx6 ccm clock tree
> + *
> + * @parent:  parent clock tree
> + * @type:clock type
> + * @off: register offset of the specified clock
> + * @shift:   number of bits to shift the bitfield
> + * @width:   width of the bitfield
> + * @idx: index of the specified clock
> + * @fixed_rate:  fixed clock rate
> + */
> +struct imx6_clk_tree {
> + const unsigned long *parent;
> + enum imx6_clk_type type;
> + u16 off;
> +
> + u8 shift;
> + u8 width;
> + u8 idx;
> + ulong fixed_rate;
> +};
> +
> +#define TREE(_parent, _type, _off, _shift, _width, _idx,
> _fixed_rate) {\
> + .parent =
> _parent,  \
> + .type =
> _type,\
> + .off =
> _off, \
> + .shift =
> _shift,   \
> + .width =
> _width,   \
> + .idx =
> _idx, \
> + .fixed_rate =
> _fixed_rate,  \ +}
> +
> +#define
> SIMPLE(_parent)
> \
> + TREE(_parent, IMX6_CLK_TYPE_SIMPLE, 0, 0, 0, 0, 0)
> +
> +#define
> FIXED(_fixed_rate)\
> + TREE(NULL, IMX6_CLK_TYPE_FIXED, 0, 0, 0, 0, _fixed_rate)
> +
> +#define DIV(_parent, _off, _shift,
> _width)   \
> + TREE(_parent, IMX6_CLK_TYPE_DIV, _off, _shift, _width, 0, 0)
> +
> +#define MUX(_parent, _off, _shift,
> _width)   \
> + TREE(_parent, IMX6_CLK_TYPE_MUX, _off, _shift, _width, 0, 0)
> +
> +#define PLL_PFD(_parent, _off, _width,
> _idx) \
> + TREE(_parent, IMX6_CLK_TYPE_PLL_PFD, _off, 0, _width, _idx,
> 0) +
> +#define PLL_DIV(_parent, _off, _shift,
> _width)   \
> + TREE(_parent, IMX6_CLK_TYPE_PLL_DIV, _off, _shift, 

Re: [U-Boot] [PATCH v3 3/3] arm: sunxi: h6: fix reset using r_wdog

[Clément Péron]

Hi,

+Chen-Yu Tsai for test and +Icenowy because she try to contact AW
about this issue.

On Wed, 17 Apr 2019 at 19:41, Clément Péron  wrote:
>
> WDOG is broken for some H6 rev. The board is not
> reseted correctly.
>
> Use the R_WDOG instead.

The issue is real except on Pine H64 and Rongpin RP-H6B which seems to
be NOT affected.
Lot of users on OrangePi boards (Lite2 / One Plus and 3) are
complaining about this issue.

We perform a simple watchdog test on different board :

Chen-Yu Tsai :
Pine h64 = H6 V200-AWIN H6448BA 7782 => OK
OrangePi Lite 2 = H6 V200-AWIN H8068BA 61C2 => KO

Martin Ayotte :
PineH64 = H8069BA 6892 => OK
Orange Pi 3 = HA047BA 69W2 => KO
OPiOnePlus = H7310BA 6842 => KO
OPiLite2 = H6448BA 6662 => KO

Clément Péron:
Beelink GS1 = H6 V200-AWIN H7309BA 6842 => KO

After the series of result, Icenowy try to reach Allwinner about this
issue but they seems not interested to investigate it.

I'm not sure if it's an HW errata or if there something misconfigured
but the result is here WDOG doesn't make these boards reboot.
And this should not happens !

As we don't have the ARIS co proc to do power management and watchdog
is the only solution to reset the board for now.
A really simple change from Watchdog to R_Watchdog fix the issue and
has been tested on several boards.
Patch is already applied on Armbian.

Thanks,
Clément

>
> Signed-off-by: Clément Péron 
> ---
>  arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h | 1 +
>  arch/arm/mach-sunxi/board.c | 9 +++--
>  2 files changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h 
> b/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h
> index 41a9b0fc47..6392cb07b4 100644
> --- a/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h
> +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h
> @@ -60,6 +60,7 @@
>  #define SUNXI_RTC_BASE 0x0700
>  #define SUNXI_R_CPUCFG_BASE0x07000400
>  #define SUNXI_PRCM_BASE0x0701
> +#define SUNXI_R_WDOG_BASE  0x07020400
>  #define SUNXI_R_PIO_BASE   0x07022000
>  #define SUNXI_R_UART_BASE  0x0708
>  #define SUNXI_R_TWI_BASE   0x07081400
> diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
> index c6dd7b8e54..921e4c5175 100644
> --- a/arch/arm/mach-sunxi/board.c
> +++ b/arch/arm/mach-sunxi/board.c
> @@ -289,9 +289,14 @@ void reset_cpu(ulong addr)
> writel(WDT_MODE_RESET_EN | WDT_MODE_EN, >mode);
> }
>  #elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_MACH_SUN50I_H6)
> +#if defined(CONFIG_MACH_SUN50I_H6)
> +   /* WDOG is broken for some H6 rev. use the R_WDOG instead */
> static const struct sunxi_wdog *wdog =
> -((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
> -
> +   (struct sunxi_wdog *)SUNXI_R_WDOG_BASE;
> +#else
> +   static const struct sunxi_wdog *wdog =
> +   ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
> +#endif
> /* Set the watchdog for its shortest interval (.5s) and wait */
> writel(WDT_CFG_RESET, >cfg);
> writel(WDT_MODE_EN, >mode);
> --
> 2.17.1
>
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[U-Boot] [PATCH v3] spi: Zap fsl_espi driver-related code

[Jagan Teki]

Dropped
- fsl_espi driver

Dropped due to:
- no active updates
- no dm conversion
- multiple pings for asking dm-conversion
- driver-model migration expiry

Cc: Oleksandr Zhadan and Michael Durrant 
Signed-off-by: Jagan Teki 
---
Change for v3:
- rebase on master

 board/Arcturus/ucp1020/ucp1020.c |   6 +
 drivers/spi/Kconfig  |   7 -
 drivers/spi/Makefile |   1 -
 drivers/spi/fsl_espi.c   | 383 ---
 4 files changed, 6 insertions(+), 391 deletions(-)
 delete mode 100644 drivers/spi/fsl_espi.c

diff --git a/board/Arcturus/ucp1020/ucp1020.c b/board/Arcturus/ucp1020/ucp1020.c
index 1a1fcb9be9..b07ba60671 100644
--- a/board/Arcturus/ucp1020/ucp1020.c
+++ b/board/Arcturus/ucp1020/ucp1020.c
@@ -43,6 +43,12 @@ void spi_set_speed(struct spi_slave *slave, uint hz)
/* TO DO: It's actially have to be in spi/ */
 }
 
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+   /* do nothing, there is no spi driver */
+   return 0;
+}
+
 /*
  * To be compatible with cmd_gpio
  */
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 8a86878fee..23b089b0e5 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -320,13 +320,6 @@ config CF_SPI
  Enable the ColdFire SPI driver. This driver can be used on
  some m68k SoCs.
 
-config FSL_ESPI
-   bool "Freescale eSPI driver"
-   help
- Enable the Freescale eSPI driver. This driver can be used to
- access the SPI interface and SPI NOR flash on platforms embedding
- this Freescale eSPI IP core.
-
 config FSL_QSPI
bool "Freescale QSPI driver"
imply SPI_FLASH_BAR
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index be4b4c140d..88bdf66dbd 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -27,7 +27,6 @@ obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
 obj-$(CONFIG_DESIGNWARE_SPI) += designware_spi.o
 obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
 obj-$(CONFIG_FSL_DSPI) += fsl_dspi.o
-obj-$(CONFIG_FSL_ESPI) += fsl_espi.o
 obj-$(CONFIG_FSL_QSPI) += fsl_qspi.o
 obj-$(CONFIG_ICH_SPI) +=  ich.o
 obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c
deleted file mode 100644
index 7444ae1a06..00
--- a/drivers/spi/fsl_espi.c
+++ /dev/null
@@ -1,383 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * eSPI controller driver.
- *
- * Copyright 2010-2011 Freescale Semiconductor, Inc.
- * Author: Mingkai Hu (mingkai...@freescale.com)
- */
-
-#include 
-
-#include 
-#include 
-#include 
-
-struct fsl_spi_slave {
-   struct spi_slave slave;
-   ccsr_espi_t *espi;
-   unsigned intdiv16;
-   unsigned intpm;
-   int tx_timeout;
-   unsigned intmode;
-   size_t  cmd_len;
-   u8  cmd_buf[16];
-   size_t  data_len;
-   unsigned intmax_transfer_length;
-};
-
-#define to_fsl_spi_slave(s) container_of(s, struct fsl_spi_slave, slave)
-#define US_PER_SECOND  100UL
-
-#define ESPI_MAX_CS_NUM4
-#define ESPI_FIFO_WIDTH_BIT32
-
-#define ESPI_EV_RNEBIT(9)
-#define ESPI_EV_TNFBIT(8)
-#define ESPI_EV_DONBIT(14)
-#define ESPI_EV_TXEBIT(15)
-#define ESPI_EV_RFCNT_SHIFT24
-#define ESPI_EV_RFCNT_MASK (0x3f << ESPI_EV_RFCNT_SHIFT)
-
-#define ESPI_MODE_EN   BIT(31) /* Enable interface */
-#define ESPI_MODE_TXTHR(x) ((x) << 8)  /* Tx FIFO threshold */
-#define ESPI_MODE_RXTHR(x) ((x) << 0)  /* Rx FIFO threshold */
-
-#define ESPI_COM_CS(x) ((x) << 30)
-#define ESPI_COM_TRANLEN(x)((x) << 0)
-
-#define ESPI_CSMODE_CI_INACTIVEHIGHBIT(31)
-#define ESPI_CSMODE_CP_BEGIN_EDGCLKBIT(30)
-#define ESPI_CSMODE_REV_MSB_FIRST  BIT(29)
-#define ESPI_CSMODE_DIV16  BIT(28)
-#define ESPI_CSMODE_PM(x)  ((x) << 24)
-#define ESPI_CSMODE_POL_ASSERTED_LOW   BIT(20)
-#define ESPI_CSMODE_LEN(x) ((x) << 16)
-#define ESPI_CSMODE_CSBEF(x)   ((x) << 12)
-#define ESPI_CSMODE_CSAFT(x)   ((x) << 8)
-#define ESPI_CSMODE_CSCG(x)((x) << 3)
-
-#define ESPI_CSMODE_INIT_VAL (ESPI_CSMODE_POL_ASSERTED_LOW | \
-   ESPI_CSMODE_CSBEF(0) | ESPI_CSMODE_CSAFT(0) | \
-   ESPI_CSMODE_CSCG(1))
-
-#define ESPI_MAX_DATA_TRANSFER_LEN 0xFFF0
-
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
-   unsigned int max_hz, unsigned int mode)
-{
-   struct fsl_spi_slave *fsl;
-   sys_info_t sysinfo;
-   unsigned long spibrg = 0;
-   unsigned long spi_freq = 0;
-   unsigned char pm = 0;
-
-   if (!spi_cs_is_valid(bus, cs))
-   return NULL;
-
-   fsl = spi_alloc_slave(struct fsl_spi_slave, bus, cs);
-   if (!fsl)
-   return NULL;
-
-   fsl->espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR);
-   fsl->mode = mode;
-   fsl->max_transfer_length 

[U-Boot] [PATCH v3] spi: Zap soft_spi_legacy driver-related code

[Jagan Teki]

Dropped
- soft_spi_legacy driver
- CONFIG_SOFT_SPI

Dropped due to:
- no active updates
- no dm conversion
- multiple pings for asking dm-conversion
- driver-model migration expiry

Cc: Vasily Khoruzhick 
Signed-off-by: Jagan Teki 
---
Changes for v3:
- rebase on master

 drivers/spi/Kconfig   |  12 +--
 drivers/spi/Makefile  |   1 -
 drivers/spi/soft_spi_legacy.c | 168 --
 include/configs/MPC8349EMDS.h |   3 -
 include/configs/zipitz2.h |   1 -
 5 files changed, 6 insertions(+), 179 deletions(-)
 delete mode 100644 drivers/spi/soft_spi_legacy.c

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 4095bf5950..8a86878fee 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -213,6 +213,12 @@ config SANDBOX_SPI
};
  };
 
+config SOFT_SPI
+   bool "Soft SPI driver"
+   help
+Enable Soft SPI driver. This driver is to use GPIO simulate
+the SPI protocol.
+
 config SPI_SUNXI
bool "Allwinner SoC SPI controllers"
help
@@ -301,12 +307,6 @@ config ZYNQMP_GQSPI
 
 endif # if DM_SPI
 
-config SOFT_SPI
-   bool "Soft SPI driver"
-   help
-Enable Soft SPI driver. This driver is to use GPIO simulate
-the SPI protocol.
-
 config MSCC_BB_SPI
bool "MSCC bitbang SPI driver"
depends on SOC_VCOREIII
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index fd147447fe..be4b4c140d 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -13,7 +13,6 @@ obj-$(CONFIG_TI_QSPI) += ti_qspi.o
 else
 obj-y += spi.o
 obj-$(CONFIG_SPI_MEM) += spi-mem-nodm.o
-obj-$(CONFIG_SOFT_SPI) += soft_spi_legacy.o
 endif
 
 obj-$(CONFIG_ALTERA_SPI) += altera_spi.o
diff --git a/drivers/spi/soft_spi_legacy.c b/drivers/spi/soft_spi_legacy.c
deleted file mode 100644
index cc5ab5f991..00
--- a/drivers/spi/soft_spi_legacy.c
+++ /dev/null
@@ -1,168 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2002
- * Gerald Van Baren, Custom IDEAS, vanba...@cideas.com.
- *
- * Influenced by code from:
- * Wolfgang Denk, DENX Software Engineering, w...@denx.de.
- */
-
-#include 
-#include 
-
-#include 
-
-/*---
- * Definitions
- */
-
-#ifdef DEBUG_SPI
-#define PRINTD(fmt,args...)printf (fmt ,##args)
-#else
-#define PRINTD(fmt,args...)
-#endif
-
-struct soft_spi_slave {
-   struct spi_slave slave;
-   unsigned int mode;
-};
-
-static inline struct soft_spi_slave *to_soft_spi(struct spi_slave *slave)
-{
-   return container_of(slave, struct soft_spi_slave, slave);
-}
-
-/*=*/
-/* Public Functions*/
-/*=*/
-
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
-   unsigned int max_hz, unsigned int mode)
-{
-   struct soft_spi_slave *ss;
-
-   if (!spi_cs_is_valid(bus, cs))
-   return NULL;
-
-   ss = spi_alloc_slave(struct soft_spi_slave, bus, cs);
-   if (!ss)
-   return NULL;
-
-   ss->mode = mode;
-
-   /* TODO: Use max_hz to limit the SCK rate */
-
-   return >slave;
-}
-
-void spi_free_slave(struct spi_slave *slave)
-{
-   struct soft_spi_slave *ss = to_soft_spi(slave);
-
-   free(ss);
-}
-
-int spi_claim_bus(struct spi_slave *slave)
-{
-#ifdef CONFIG_SYS_IMMR
-   volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-#endif
-   struct soft_spi_slave *ss = to_soft_spi(slave);
-
-   /*
-* Make sure the SPI clock is in idle state as defined for
-* this slave.
-*/
-   if (ss->mode & SPI_CPOL)
-   SPI_SCL(1);
-   else
-   SPI_SCL(0);
-
-   return 0;
-}
-
-void spi_release_bus(struct spi_slave *slave)
-{
-   /* Nothing to do */
-}
-
-/*---
- * SPI transfer
- *
- * This writes "bitlen" bits out the SPI MOSI port and simultaneously clocks
- * "bitlen" bits in the SPI MISO port.  That's just the way SPI works.
- *
- * The source of the outgoing bits is the "dout" parameter and the
- * destination of the input bits is the "din" parameter.  Note that "dout"
- * and "din" can point to the same memory location, in which case the
- * input data overwrites the output data (since both are buffered by
- * temporary variables, this is OK).
- */
-int  spi_xfer(struct spi_slave *slave, unsigned int bitlen,
-   const void *dout, void *din, unsigned long flags)
-{
-#ifdef CONFIG_SYS_IMMR
-   volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-#endif
-   struct soft_spi_slave *ss = to_soft_spi(slave);
-   uchar   tmpdin  = 0;
-   uchar   tmpdout = 0;
-   const u8*txd = dout;
-   u8  *rxd = din;
-   int  

[U-Boot] [PATCH v3] spi: Zap sh_spi driver-related code

[Jagan Teki]

Dropped
- sh_spi driver
- CONFIG_SH_SPI,SH_SPI_BASE

Dropped due to:
- no active updates
- no dm conversion
- multiple pings for asking dm-conversion
- no response for dm converted patch
- driver-model migration expiry

Signed-off-by: Jagan Teki 
---
Changes for v3:
- rebase on master

 configs/sh7752evb_defconfig  |   1 -
 configs/sh7753evb_defconfig  |   1 -
 configs/sh7757lcr_defconfig  |   1 -
 drivers/spi/Kconfig  |   6 -
 drivers/spi/Makefile |   1 -
 drivers/spi/sh_spi.c | 249 ---
 drivers/spi/sh_spi.h |  67 --
 include/configs/sh7752evb.h  |   3 -
 include/configs/sh7753evb.h  |   3 -
 include/configs/sh7757lcr.h  |   3 -
 scripts/config_whitelist.txt |   1 -
 11 files changed, 336 deletions(-)
 delete mode 100644 drivers/spi/sh_spi.c
 delete mode 100644 drivers/spi/sh_spi.h

diff --git a/configs/sh7752evb_defconfig b/configs/sh7752evb_defconfig
index b34709d1ea..425f194c95 100644
--- a/configs/sh7752evb_defconfig
+++ b/configs/sh7752evb_defconfig
@@ -38,5 +38,4 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SH_ETHER=y
 CONFIG_SCIF_CONSOLE=y
 CONFIG_SPI=y
-CONFIG_SH_SPI=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/sh7753evb_defconfig b/configs/sh7753evb_defconfig
index 857e90b86a..3904e1b39d 100644
--- a/configs/sh7753evb_defconfig
+++ b/configs/sh7753evb_defconfig
@@ -37,5 +37,4 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SH_ETHER=y
 CONFIG_SCIF_CONSOLE=y
 CONFIG_SPI=y
-CONFIG_SH_SPI=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/sh7757lcr_defconfig b/configs/sh7757lcr_defconfig
index 8314435b93..d4a132f50b 100644
--- a/configs/sh7757lcr_defconfig
+++ b/configs/sh7757lcr_defconfig
@@ -39,5 +39,4 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SH_ETHER=y
 CONFIG_SCIF_CONSOLE=y
 CONFIG_SPI=y
-CONFIG_SH_SPI=y
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 955da8db64..4095bf5950 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -341,12 +341,6 @@ config DAVINCI_SPI
help
  Enable the Davinci SPI driver
 
-config SH_SPI
-   bool "SuperH SPI driver"
-   help
- Enable the SuperH SPI controller driver. This driver can be used
- on various SuperH SoCs, such as SH7757.
-
 config SH_QSPI
bool "Renesas Quad SPI driver"
help
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 055ef99dc9..fd147447fe 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -48,7 +48,6 @@ obj-$(CONFIG_RENESAS_RPC_SPI) += renesas_rpc_spi.o
 obj-$(CONFIG_ROCKCHIP_SPI) += rk_spi.o
 obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o
 obj-$(CONFIG_SPI_SUNXI) += spi-sunxi.o
-obj-$(CONFIG_SH_SPI) += sh_spi.o
 obj-$(CONFIG_SH_QSPI) += sh_qspi.o
 obj-$(CONFIG_STM32_QSPI) += stm32_qspi.o
 obj-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
diff --git a/drivers/spi/sh_spi.c b/drivers/spi/sh_spi.c
deleted file mode 100644
index c58fd0ebc4..00
--- a/drivers/spi/sh_spi.c
+++ /dev/null
@@ -1,249 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * SH SPI driver
- *
- * Copyright (C) 2011-2012 Renesas Solutions Corp.
- */
-
-#include 
-#include 
-#include 
-#include 
-#include 
-#include "sh_spi.h"
-
-static void sh_spi_write(unsigned long data, unsigned long *reg)
-{
-   writel(data, reg);
-}
-
-static unsigned long sh_spi_read(unsigned long *reg)
-{
-   return readl(reg);
-}
-
-static void sh_spi_set_bit(unsigned long val, unsigned long *reg)
-{
-   unsigned long tmp;
-
-   tmp = sh_spi_read(reg);
-   tmp |= val;
-   sh_spi_write(tmp, reg);
-}
-
-static void sh_spi_clear_bit(unsigned long val, unsigned long *reg)
-{
-   unsigned long tmp;
-
-   tmp = sh_spi_read(reg);
-   tmp &= ~val;
-   sh_spi_write(tmp, reg);
-}
-
-static void clear_fifo(struct sh_spi *ss)
-{
-   sh_spi_set_bit(SH_SPI_RSTF, >regs->cr2);
-   sh_spi_clear_bit(SH_SPI_RSTF, >regs->cr2);
-}
-
-static int recvbuf_wait(struct sh_spi *ss)
-{
-   while (sh_spi_read(>regs->cr1) & SH_SPI_RBE) {
-   if (ctrlc())
-   return 1;
-   udelay(10);
-   }
-   return 0;
-}
-
-static int write_fifo_empty_wait(struct sh_spi *ss)
-{
-   while (!(sh_spi_read(>regs->cr1) & SH_SPI_TBE)) {
-   if (ctrlc())
-   return 1;
-   udelay(10);
-   }
-   return 0;
-}
-
-static void sh_spi_set_cs(struct sh_spi *ss, unsigned int cs)
-{
-   unsigned long val = 0;
-
-   if (cs & 0x01)
-   val |= SH_SPI_SSS0;
-   if (cs & 0x02)
-   val |= SH_SPI_SSS1;
-
-   sh_spi_clear_bit(SH_SPI_SSS0 | SH_SPI_SSS1, >regs->cr4);
-   sh_spi_set_bit(val, >regs->cr4);
-}
-
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
-   unsigned int max_hz, unsigned int mode)
-{
-   struct sh_spi *ss;
-
-   if (!spi_cs_is_valid(bus, cs))
-   return NULL;
-
-   ss = spi_alloc_slave(struct sh_spi, bus, cs);
-   

[U-Boot] [PATCH v3] spi: Zap mxs_spi driver-related code

[Jagan Teki]

Dropped
- mxs_spi driver
- CONFIG_MXS_SPI

Dropped due to:
- no active updates
- no dm conversion
- multiple pings for asking dm-conversion
- no response for dm converted patch
- driver-model migration expiry

Cc: Marek Vasut 
Cc: Fabio Estevam 
Signed-off-by: Jagan Teki 
---
Changes for v3:
- rebase on master

 configs/bg0900_defconfig|   1 -
 configs/mx28evk_auart_console_defconfig |   1 -
 configs/mx28evk_defconfig   |   1 -
 configs/mx28evk_nand_defconfig  |   1 -
 configs/mx28evk_spi_defconfig   |   1 -
 drivers/spi/Kconfig |   6 -
 drivers/spi/Makefile|   1 -
 drivers/spi/mxs_spi.c   | 358 
 8 files changed, 370 deletions(-)
 delete mode 100644 drivers/spi/mxs_spi.c

diff --git a/configs/bg0900_defconfig b/configs/bg0900_defconfig
index 2c4d3e3d54..f8421ef304 100644
--- a/configs/bg0900_defconfig
+++ b/configs/bg0900_defconfig
@@ -40,5 +40,4 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_MII=y
 CONFIG_CONS_INDEX=0
 CONFIG_SPI=y
-CONFIG_MXS_SPI=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx28evk_auart_console_defconfig 
b/configs/mx28evk_auart_console_defconfig
index c54b933e53..d976ea584c 100644
--- a/configs/mx28evk_auart_console_defconfig
+++ b/configs/mx28evk_auart_console_defconfig
@@ -51,7 +51,6 @@ CONFIG_SPI_FLASH_SST=y
 CONFIG_MII=y
 CONFIG_CONS_INDEX=0
 CONFIG_SPI=y
-CONFIG_MXS_SPI=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_STORAGE=y
diff --git a/configs/mx28evk_defconfig b/configs/mx28evk_defconfig
index 187467d3db..40ab39ccf1 100644
--- a/configs/mx28evk_defconfig
+++ b/configs/mx28evk_defconfig
@@ -51,7 +51,6 @@ CONFIG_SPI_FLASH_SST=y
 CONFIG_MII=y
 CONFIG_CONS_INDEX=0
 CONFIG_SPI=y
-CONFIG_MXS_SPI=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_STORAGE=y
diff --git a/configs/mx28evk_nand_defconfig b/configs/mx28evk_nand_defconfig
index 7d891e7934..0d2afbbdb0 100644
--- a/configs/mx28evk_nand_defconfig
+++ b/configs/mx28evk_nand_defconfig
@@ -50,7 +50,6 @@ CONFIG_SPI_FLASH_SST=y
 CONFIG_MII=y
 CONFIG_CONS_INDEX=0
 CONFIG_SPI=y
-CONFIG_MXS_SPI=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_STORAGE=y
diff --git a/configs/mx28evk_spi_defconfig b/configs/mx28evk_spi_defconfig
index cb5b1b3b75..b9ea4934bb 100644
--- a/configs/mx28evk_spi_defconfig
+++ b/configs/mx28evk_spi_defconfig
@@ -50,7 +50,6 @@ CONFIG_SPI_FLASH_SST=y
 CONFIG_MII=y
 CONFIG_CONS_INDEX=0
 CONFIG_SPI=y
-CONFIG_MXS_SPI=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_STORAGE=y
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 7043b5c0f6..955da8db64 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -370,12 +370,6 @@ config MXC_SPI
  Enable the MXC SPI controller driver. This driver can be used
  on various i.MX SoCs such as i.MX31/35/51/6/7.
 
-config MXS_SPI
-   bool "MXS SPI Driver"
-   help
- Enable the MXS SPI controller driver. This driver can be used
- on the i.MX23 and i.MX28 SoCs.
-
 config OMAP3_SPI
bool "McSPI driver for OMAP"
help
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 25add2812d..055ef99dc9 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -40,7 +40,6 @@ obj-$(CONFIG_MT7621_SPI) += mt7621_spi.o
 obj-$(CONFIG_MSCC_BB_SPI) += mscc_bb_spi.o
 obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o
 obj-$(CONFIG_MXC_SPI) += mxc_spi.o
-obj-$(CONFIG_MXS_SPI) += mxs_spi.o
 obj-$(CONFIG_ATCSPI200_SPI) += atcspi200_spi.o
 obj-$(CONFIG_OMAP3_SPI) += omap3_spi.o
 obj-$(CONFIG_PIC32_SPI) += pic32_spi.o
diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c
deleted file mode 100644
index 5065e407f8..00
--- a/drivers/spi/mxs_spi.c
+++ /dev/null
@@ -1,358 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Freescale i.MX28 SPI driver
- *
- * Copyright (C) 2011 Marek Vasut 
- * on behalf of DENX Software Engineering GmbH
- *
- * NOTE: This driver only supports the SPI-controller chipselects,
- *   GPIO driven chipselects are not supported.
- */
-
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-
-#defineMXS_SPI_MAX_TIMEOUT 100
-#defineMXS_SPI_PORT_OFFSET 0x2000
-#define MXS_SSP_CHIPSELECT_MASK0x0030
-#define MXS_SSP_CHIPSELECT_SHIFT   20
-
-#define MXSSSP_SMALL_TRANSFER  512
-
-struct mxs_spi_slave {
-   struct spi_slaveslave;
-   uint32_tmax_khz;
-   uint32_tmode;
-   struct mxs_ssp_regs *regs;
-};
-
-static inline struct mxs_spi_slave *to_mxs_slave(struct spi_slave *slave)
-{
-   return container_of(slave, struct mxs_spi_slave, slave);
-}
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
-   /* MXS SPI: 4 ports and 3 chip selects maximum */
-   if (!mxs_ssp_bus_id_valid(bus) || cs > 2)
-   return 0;
-   else
-   return 1;
-}
-
-struct spi_slave 

[U-Boot] [PATCH] spi: Zap mxs_spi driver-related code

[Jagan Teki]

Dropped
- mxs_spi driver
- CONFIG_MXS_SPI

Dropped due to:
- no active updates
- no dm conversion
- multiple pings for asking dm-conversion
- no response for dm converted patch
- driver-model migration expiry

Cc: Marek Vasut 
Cc: Fabio Estevam 
Signed-off-by: Jagan Teki 
---
 configs/bg0900_defconfig|   1 -
 configs/mx28evk_auart_console_defconfig |   1 -
 configs/mx28evk_defconfig   |   1 -
 configs/mx28evk_nand_defconfig  |   1 -
 configs/mx28evk_spi_defconfig   |   1 -
 drivers/spi/Kconfig |   6 -
 drivers/spi/Makefile|   1 -
 drivers/spi/mxs_spi.c   | 358 
 8 files changed, 370 deletions(-)
 delete mode 100644 drivers/spi/mxs_spi.c

diff --git a/configs/bg0900_defconfig b/configs/bg0900_defconfig
index 2c4d3e3d54..f8421ef304 100644
--- a/configs/bg0900_defconfig
+++ b/configs/bg0900_defconfig
@@ -40,5 +40,4 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_MII=y
 CONFIG_CONS_INDEX=0
 CONFIG_SPI=y
-CONFIG_MXS_SPI=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx28evk_auart_console_defconfig 
b/configs/mx28evk_auart_console_defconfig
index c54b933e53..d976ea584c 100644
--- a/configs/mx28evk_auart_console_defconfig
+++ b/configs/mx28evk_auart_console_defconfig
@@ -51,7 +51,6 @@ CONFIG_SPI_FLASH_SST=y
 CONFIG_MII=y
 CONFIG_CONS_INDEX=0
 CONFIG_SPI=y
-CONFIG_MXS_SPI=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_STORAGE=y
diff --git a/configs/mx28evk_defconfig b/configs/mx28evk_defconfig
index 187467d3db..40ab39ccf1 100644
--- a/configs/mx28evk_defconfig
+++ b/configs/mx28evk_defconfig
@@ -51,7 +51,6 @@ CONFIG_SPI_FLASH_SST=y
 CONFIG_MII=y
 CONFIG_CONS_INDEX=0
 CONFIG_SPI=y
-CONFIG_MXS_SPI=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_STORAGE=y
diff --git a/configs/mx28evk_nand_defconfig b/configs/mx28evk_nand_defconfig
index 7d891e7934..0d2afbbdb0 100644
--- a/configs/mx28evk_nand_defconfig
+++ b/configs/mx28evk_nand_defconfig
@@ -50,7 +50,6 @@ CONFIG_SPI_FLASH_SST=y
 CONFIG_MII=y
 CONFIG_CONS_INDEX=0
 CONFIG_SPI=y
-CONFIG_MXS_SPI=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_STORAGE=y
diff --git a/configs/mx28evk_spi_defconfig b/configs/mx28evk_spi_defconfig
index cb5b1b3b75..b9ea4934bb 100644
--- a/configs/mx28evk_spi_defconfig
+++ b/configs/mx28evk_spi_defconfig
@@ -50,7 +50,6 @@ CONFIG_SPI_FLASH_SST=y
 CONFIG_MII=y
 CONFIG_CONS_INDEX=0
 CONFIG_SPI=y
-CONFIG_MXS_SPI=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_STORAGE=y
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 7043b5c0f6..955da8db64 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -370,12 +370,6 @@ config MXC_SPI
  Enable the MXC SPI controller driver. This driver can be used
  on various i.MX SoCs such as i.MX31/35/51/6/7.
 
-config MXS_SPI
-   bool "MXS SPI Driver"
-   help
- Enable the MXS SPI controller driver. This driver can be used
- on the i.MX23 and i.MX28 SoCs.
-
 config OMAP3_SPI
bool "McSPI driver for OMAP"
help
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 25add2812d..055ef99dc9 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -40,7 +40,6 @@ obj-$(CONFIG_MT7621_SPI) += mt7621_spi.o
 obj-$(CONFIG_MSCC_BB_SPI) += mscc_bb_spi.o
 obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o
 obj-$(CONFIG_MXC_SPI) += mxc_spi.o
-obj-$(CONFIG_MXS_SPI) += mxs_spi.o
 obj-$(CONFIG_ATCSPI200_SPI) += atcspi200_spi.o
 obj-$(CONFIG_OMAP3_SPI) += omap3_spi.o
 obj-$(CONFIG_PIC32_SPI) += pic32_spi.o
diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c
deleted file mode 100644
index 5065e407f8..00
--- a/drivers/spi/mxs_spi.c
+++ /dev/null
@@ -1,358 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Freescale i.MX28 SPI driver
- *
- * Copyright (C) 2011 Marek Vasut 
- * on behalf of DENX Software Engineering GmbH
- *
- * NOTE: This driver only supports the SPI-controller chipselects,
- *   GPIO driven chipselects are not supported.
- */
-
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-
-#defineMXS_SPI_MAX_TIMEOUT 100
-#defineMXS_SPI_PORT_OFFSET 0x2000
-#define MXS_SSP_CHIPSELECT_MASK0x0030
-#define MXS_SSP_CHIPSELECT_SHIFT   20
-
-#define MXSSSP_SMALL_TRANSFER  512
-
-struct mxs_spi_slave {
-   struct spi_slaveslave;
-   uint32_tmax_khz;
-   uint32_tmode;
-   struct mxs_ssp_regs *regs;
-};
-
-static inline struct mxs_spi_slave *to_mxs_slave(struct spi_slave *slave)
-{
-   return container_of(slave, struct mxs_spi_slave, slave);
-}
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
-   /* MXS SPI: 4 ports and 3 chip selects maximum */
-   if (!mxs_ssp_bus_id_valid(bus) || cs > 2)
-   return 0;
-   else
-   return 1;
-}
-
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned 

[U-Boot] [PATCH] spi: Zap lpc32xx_ssp driver-related code

[Jagan Teki]

Dropped
- lpc32xx_ssp driver
- CONFIG_LPC32XX_SSP, LPC32XX_SSP_TIMEOUT items

Dropped due to:
- no active updates
- no dm conversion
- multiple pings for asking dm-conversion
- no response for dm converted patch
- driver-model migration expiry

Cc: Vladimir Zapolskiy 
Cc: Albert ARIBAUD 
Signed-off-by: Jagan Teki 
---
 configs/devkit3250_defconfig |   1 -
 configs/work_92105_defconfig |   1 -
 drivers/spi/Kconfig  |   5 --
 drivers/spi/Makefile |   1 -
 drivers/spi/lpc32xx_ssp.c| 134 ---
 include/configs/devkit3250.h |   5 --
 include/configs/work_92105.h |   5 --
 scripts/config_whitelist.txt |   1 -
 8 files changed, 153 deletions(-)
 delete mode 100644 drivers/spi/lpc32xx_ssp.c

diff --git a/configs/devkit3250_defconfig b/configs/devkit3250_defconfig
index b739f27803..8fc7763c3a 100644
--- a/configs/devkit3250_defconfig
+++ b/configs/devkit3250_defconfig
@@ -42,7 +42,6 @@ CONFIG_PHY_ADDR_ENABLE=y
 CONFIG_PHY_ADDR=31
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
-CONFIG_LPC32XX_SSP=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/work_92105_defconfig b/configs/work_92105_defconfig
index 105e51a400..61863abeb7 100644
--- a/configs/work_92105_defconfig
+++ b/configs/work_92105_defconfig
@@ -38,4 +38,3 @@ CONFIG_PHYLIB=y
 CONFIG_PHY_ADDR_ENABLE=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
-CONFIG_LPC32XX_SSP=y
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index fb794adae7..7043b5c0f6 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -359,11 +359,6 @@ config KIRKWOOD_SPI
  Enable support for SPI on various Marvell SoCs, such as
  Kirkwood and Armada 375.
 
-config LPC32XX_SSP
-   bool "LPC32XX SPI Driver"
-   help
- Enable support for SPI on LPC32xx
-
 config MPC8XXX_SPI
bool "MPC8XXX SPI Driver"
help
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 8be9a4baa2..25add2812d 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -32,7 +32,6 @@ obj-$(CONFIG_FSL_ESPI) += fsl_espi.o
 obj-$(CONFIG_FSL_QSPI) += fsl_qspi.o
 obj-$(CONFIG_ICH_SPI) +=  ich.o
 obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
-obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o
 obj-$(CONFIG_MESON_SPIFC) += meson_spifc.o
 obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o
 obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
diff --git a/drivers/spi/lpc32xx_ssp.c b/drivers/spi/lpc32xx_ssp.c
deleted file mode 100644
index 4b09366317..00
--- a/drivers/spi/lpc32xx_ssp.c
+++ /dev/null
@@ -1,134 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * LPC32xx SSP interface (SPI mode)
- *
- * (C) Copyright 2014  DENX Software Engineering GmbH
- * Written-by: Albert ARIBAUD 
- */
-
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-
-/* SSP chip registers */
-struct ssp_regs {
-   u32 cr0;
-   u32 cr1;
-   u32 data;
-   u32 sr;
-   u32 cpsr;
-   u32 imsc;
-   u32 ris;
-   u32 mis;
-   u32 icr;
-   u32 dmacr;
-};
-
-/* CR1 register defines  */
-#define SSP_CR1_SSP_ENABLE 0x0002
-
-/* SR register defines  */
-#define SSP_SR_TNF 0x0002
-/* SSP status RX FIFO not empty bit */
-#define SSP_SR_RNE 0x0004
-
-/* lpc32xx spi slave */
-struct lpc32xx_spi_slave {
-   struct spi_slave slave;
-   struct ssp_regs *regs;
-};
-
-static inline struct lpc32xx_spi_slave *to_lpc32xx_spi_slave(
-   struct spi_slave *slave)
-{
-   return container_of(slave, struct lpc32xx_spi_slave, slave);
-}
-
-/* the following is called in sequence by do_spi_xfer() */
-
-struct spi_slave *spi_setup_slave(uint bus, uint cs, uint max_hz, uint mode)
-{
-   struct lpc32xx_spi_slave *lslave;
-
-   /* we only set up SSP0 for now, so ignore bus */
-
-   if (mode & SPI_3WIRE) {
-   pr_err("3-wire mode not supported");
-   return NULL;
-   }
-
-   if (mode & SPI_SLAVE) {
-   pr_err("slave mode not supported\n");
-   return NULL;
-   }
-
-   if (mode & SPI_PREAMBLE) {
-   pr_err("preamble byte skipping not supported\n");
-   return NULL;
-   }
-
-   lslave = spi_alloc_slave(struct lpc32xx_spi_slave, bus, cs);
-   if (!lslave) {
-   printf("SPI_error: Fail to allocate lpc32xx_spi_slave\n");
-   return NULL;
-   }
-
-   lslave->regs = (struct ssp_regs *)SSP0_BASE;
-
-   /*
-* 8 bit frame, SPI fmt, 500kbps -> clock divider is 26.
-* Set SCR to 0 and CPSDVSR to 26.
-*/
-
-   writel(0x7, >regs->cr0); /* 8-bit chunks, SPI, 1 clk/bit */
-   writel(26, >regs->cpsr); /* SSP clock = HCLK/26 = 500kbps */
-   writel(0, >regs->imsc); /* do not raise any interrupts */
-   writel(0, >regs->icr); /* clear any pending interrupt */
-   writel(0, >regs->dmacr); /* do not do DMAs */
-   writel(SSP_CR1_SSP_ENABLE, >regs->cr1); /* enable SSP0 */
-   return >slave;
-}
-
-void spi_free_slave(struct spi_slave *slave)
-{

Re: [U-Boot] [PATCH v5 01/13] m68k: add basic set of devicetrees

[Jagan Teki]

Hi Angelo,

On Thu, Mar 14, 2019 at 2:17 AM Angelo Dureghello  wrote:
>
> This patch adds a basic group of devicetrees, one for each
> cpu family, including actually just uart and dspi devices,
> since these are the drivers supporting devicetree (support
> added in this patch-set).
>
> Acked-by: Jagan Teki 
> Signed-off-by: Angelo Dureghello 
> ---

Any chance to apply this series? I fine with spi dm conversion. merge
it asap, before MW.

Reviewed-by: Jagan Teki 
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Re: [U-Boot] [PATCH] usb: dwc2: fix gadget disconnect

[Lukasz Majewski]

On Wed, 17 Apr 2019 16:46:13 +0200
Fabrice Gasnier  wrote:

> This fixes a disconnect issue detected with fastboot command, when
> using dwc2 driver.
> - On u-boot side:
> uboot>$ fastboot 0  
> - On USB host PC side, few seconds after
> PC>$ fastboot reboot # Get stuck, uboot target never reboots  
> 
> By enabling DEBUG_ISR logs, the bus suspend interrupt is seen before
> the PC command has been issued. When the USB bus suspend occurs,
> there's a HACK that disables the fastboot (composite driver). Here is
> the call stack upon USB bus suspend:
> - dwc2_handle_usb_suspend_intr()
>   - dev->driver->disconnect()
> - composite_disconnect()
>   - reset_config()
> - f->disable()
>   - fastboot_disable()
> - usb_ep_disable(f_fb->out_ep);
> - usb_ep_disable(f_fb->in_ep);
> .. other disable calls.
> 
> When the resume interrupt happens, everything has been disabled, then
> nothing happens. fastboot command gets stuck on HOST side.
> 
> Remove original HACK, that disconnects the composite driver upon
> USB bus suspend. Implement disconnect detection instead:
> - check GINTSTS OTG interrupt
> - read GOTGINT register
> - check GOTGINT, SesEndDet bit (e.g. session end)
> This is inspired by what is implemented currently in Linux dwc2
> driver.
> 
> Signed-off-by: Fabrice Gasnier 
> ---
> 
>  drivers/usb/gadget/dwc2_udc_otg_regs.h |  6 +-
>  drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c | 14 --
>  2 files changed, 17 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/usb/gadget/dwc2_udc_otg_regs.h
> b/drivers/usb/gadget/dwc2_udc_otg_regs.h index a1829b3..b685256 100644
> --- a/drivers/usb/gadget/dwc2_udc_otg_regs.h
> +++ b/drivers/usb/gadget/dwc2_udc_otg_regs.h
> @@ -86,6 +86,9 @@ struct dwc2_usbotg_reg {
>  #define B_SESSION_VALID  (0x1<<19)
>  #define A_SESSION_VALID  (0x1<<18)
>  
> +/* DWC2_UDC_OTG_GOTINT */
> +#define GOTGINT_SES_END_DET  (1<<2)
> +
>  /* DWC2_UDC_OTG_GAHBCFG */
>  #define PTXFE_HALF   (0<<8)
>  #define PTXFE_ZERO   (1<<8)
> @@ -118,6 +121,7 @@ struct dwc2_usbotg_reg {
>  #define INT_NP_TX_FIFO_EMPTY (0x1<<5)
>  #define INT_RX_FIFO_NOT_EMPTY(0x1<<4)
>  #define INT_SOF  (0x1<<3)
> +#define INT_OTG  (0x1<<2)
>  #define INT_DEV_MODE (0x0<<0)
>  #define INT_HOST_MODE(0x1<<1)
>  #define INT_GOUTNakEff   (0x01<<7)
> @@ -246,7 +250,7 @@ struct dwc2_usbotg_reg {
>  
>  /* Masks definitions */
>  #define GINTMSK_INIT (INT_OUT_EP | INT_IN_EP | INT_RESUME |
> INT_ENUMDONE\
> - | INT_RESET | INT_SUSPEND)
> + | INT_RESET | INT_SUSPEND | INT_OTG)
>  #define DOEPMSK_INIT (CTRL_OUT_EP_SETUP_PHASE_DONE |
> AHB_ERROR|TRANSFER_DONE) #define DIEPMSK_INIT
> (NON_ISO_IN_EP_TIMEOUT|AHB_ERROR|TRANSFER_DONE) #define
> GAHBCFG_INIT  (PTXFE_HALF | NPTXFE_HALF | MODE_DMA |
> BURST_INCR4\ diff --git a/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c
> b/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c index a75af49..7eb632d
> 100644 --- a/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c +++
> b/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c @@ -467,7 +467,7 @@
> static void process_ep_out_intr(struct dwc2_udc *dev) static int
> dwc2_udc_irq(int irq, void *_dev) {
>   struct dwc2_udc *dev = _dev;
> - u32 intr_status;
> + u32 intr_status, gotgint;
>   u32 usb_status, gintmsk;
>   unsigned long flags = 0;
>  
> @@ -521,14 +521,24 @@ static int dwc2_udc_irq(int irq, void *_dev)
>   && dev->driver) {
>   if (dev->driver->suspend)
>   dev->driver->suspend(>gadget);
> + }
> + }
> +
> + if (intr_status & INT_OTG) {
> + gotgint = readl(>gotgint);
> + debug_cond(DEBUG_ISR,
> +"\tOTG interrupt: (GOTGINT):0x%x\n",
> gotgint); 
> - /* HACK to let gadget detect disconnected
> state */
> + if (gotgint & GOTGINT_SES_END_DET) {
> + debug_cond(DEBUG_ISR, "\t\tSession End
> Detected\n");
> + /* Let gadget detect disconnected state */
>   if (dev->driver->disconnect) {
>   spin_unlock_irqrestore(>lock,
> flags); dev->driver->disconnect(>gadget);
>   spin_lock_irqsave(>lock, flags);
>   }
>   }
> + writel(gotgint, >gotgint);
>   }
>  
>   if (intr_status & INT_RESUME) {

Acked-by: Lukasz Majewski 

Best regards,

Lukasz Majewski

--

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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lu...@denx.de


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Description: OpenPGP digital signature

Re: [U-Boot] [PATCH] usb: reload watchdog during ums command

[Lukasz Majewski]

Hi Patrick,

> Reload the watchdog in the mass storage command ums
> to avoid reboot during the usb waiting loop
> when the host doesn't send any request.
> 
> Signed-off-by: Patrick Delaunay 
> ---
> 
>  cmd/usb_mass_storage.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/cmd/usb_mass_storage.c b/cmd/usb_mass_storage.c
> index 753ae4f..570cf3a 100644
> --- a/cmd/usb_mass_storage.c
> +++ b/cmd/usb_mass_storage.c
> @@ -14,6 +14,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  
>  static int ums_read_sector(struct ums *ums_dev,
>  ulong start, lbaint_t blkcnt, void *buf)
> @@ -226,6 +227,8 @@ static int do_usb_mass_storage(cmd_tbl_t *cmdtp,
> int flag, rc = CMD_RET_SUCCESS;
>   goto cleanup_register;
>   }
> +
> + WATCHDOG_RESET();
>   }
>  
>  cleanup_register:

Acked-by: Lukasz Majewski 


Best regards,

Lukasz Majewski

--

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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lu...@denx.de


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Re: [U-Boot] [PATCH v2 00/10] clk: imx: Add i.MX6 CLK support

[Jagan Teki]

On Fri, Apr 5, 2019 at 2:20 AM Lukasz Majewski  wrote:
>
> Hi Jagan,
>
> > On Thu, Apr 4, 2019 at 3:31 PM Lukasz Majewski  wrote:
> > >
> > > On Thu, 4 Apr 2019 14:56:36 +0530
> > > Jagan Teki  wrote:
> > >
> > > > On Thu, Apr 4, 2019 at 2:31 PM Lukasz Majewski 
> > > > wrote:
> > > > >
> > > > > On Tue,  2 Apr 2019 16:58:33 +0530
> > > > > Jagan Teki  wrote:
> > > > >
> > > > > > This is revised version of previous i.MX6 clock management
> > > > > > [1].
> > > > > >
> > > > > > The main difference between previous version is
> > > > > > - Group the i.MX6 ccm clocks into gates and tree instead of
> > > > > > handling the clocks in simple way using case statement.
> > > > > > - use gate clocks for enable/disable management.
> > > > > > - use tree clocks for get/set rate or parent traverse
> > > > > > management.
> > > > > > - parent clock handling via clock type.
> > > > > > - traverse the parent clock using recursive functionlaity.
> > > > > >
> > > > > > The main motive behind this tree framework is to make the
> > > > > > clock tree management simple and useful for U-Boot
> > > > > > requirements instead of garbing Linux clock management code.
> > > > > >
> > > > > > We are trying to manage the Allwinner clocks with similar
> > > > > > kind, so having this would really help i.MX6 as well.
> > > > > >
> > > > > > Added simple names for clock macros, but will update it in
> > > > > > future version.
> > > > > >
> > > > > > I have skipped ENET clocks from previous series, will add it
> > > > > > in future patches.
> > > > > >
> > > > > > Changes for v2:
> > > > > > - changed framework patches.
> > > > > > - add support for imx6qdl and imx6ul boards
> > > > > > - add clock gates, tree.
> > > > > >
> > > > > > [1] https://patchwork.ozlabs.org/cover/950964/
> > > > > >
> > > > > > Any inputs?
> > > > >
> > > > > Hmm It looks like we are doing some development in parallel.
> > > > >
> > > > > Please look into following commit [1]:
> > > > > https://patchwork.ozlabs.org/patch/1034051/
> > > > >
> > > > > It ports from Linux 5.0 the CCF framework for iMX6Q, which IMHO
> > > > > in the long term is a better approach.
> > > > > The code is kept simple and resembles the code from Barebox.
> > > > >
> > > > > Please correct me if I'm wrong, but the code from your work is
> > > > > not modeling muxes, gates and other components from Linux CCF.
> > > >
> > > > The U-Boot implementation of CLK would require as minimal and
> > > > simple as possible due to requirement of U-Boot itself. Hope you
> > > > agree this point?
> > >
> > > Now i.MX6 is using clock.c CLK implementation. If we decide to
> > > replace it - we shall do it in a way, which would allow us to follow
> > > Linux kernel. (the barebox implementation is a stripped CCF from
> > > Linux, the same is in patch [1]).
> > >
> > > > if yes having CCF stack code to handle all clock with
> > > > respective separate drivers management is may not require as of
> > > > now, IMHO.
> > >
> > > I do have a gut feeling, that we will end up with the need to have
> > > the CCF framework ported anyway. As for example imx7/8 can re-use
> > > muxes, gates code.
> >
> > As per my experience the main the over-ahead to handle clocks in
> > U-Boot if we go with separate clock drivers is for Video and Ethernet
> > peripherals. these are key IP's which use more clocks from U-Boot
> > point-of-view, others can be handle pretty straight-forward unless if
> > they don't have too much tree chain.
> >
> > On this series, the tree management is already supported ENET in
> > i.MX6, and Allwinner platforms.
> >
> > As of now, I'm thinking I can handle reset of the clocks with similar
> > way.
>
> But this code also supports ENET and ESDHCI clocks on i.MX6Q (as
> supporting those was the motivator for this work).
>
> One important thing to be aware of - the problem with SPL's footprint.
> The implementation with clock.c is small and simple, but doesn't scale
> well.
>
> >
> > >
> > > However, those are only my "feelings" after a glimpse look - I will
> > > look into your code more thoroughly and provide feedback.
> >
> > Please have a look, if possible check even the code size by adding
> > USDHC clocks.
>
> Yes, code size (especially in SPL) is an _important_ factor here.
>
> >
> > >
> > > >
> > > > This series is using recursive calls for handling parenting stuff
> > > > to handle get or set rates, which is fine for handling clock tree
> > > > management as far as U-Boot point-of-view. We have faced similar
> > > > situation as I explained in commit message about Allwinner clocks
> > > > [2] and we ended up going this way.
> > >
> > > I'm not Allwinner expert - but if I may ask - how far away is this
> > > implementation from mainline Linux kernel?
> > >
> > > How difficult is it to port the new code (or update it)?
> >
> > Allwinner clocks also has similar gates, muxs, and with other platform
> > stuff which has too much scope in Linux to use CCM.
>
> For example the barebox managed 

Re: [U-Boot] [RESEND PATCH v3] sun50i: a64: Add Olimex A64-Teres-I board initial support

[Jagan Teki]

On Fri, Apr 19, 2019 at 1:14 AM Jonas Smedegaard  wrote:
>
> [resent only to list, to avoid blocking due to too many recipients]

Better to CC maintainers at least.

>
> Olimex A64-Teres-I board is a mainboard (the only one so far)
> for Olimex Teres-I DIY laptop kit.
>
> Key features:
> - Allwinner A64 Cortex-A53
> - Mali-400MP2 GPU
> - AXP803 PMIC
> - 2GB DDR3 RAM
> - MicroSD Slot
> - 16GB eMMC Flash
> - eDP LCD display
> - HDMI
> - USB Host
> - Battery management
> - 5V DC power supply
> - Certified Open Source Hardware (OSHW)
>
> Works:
> - i2C
> - MMC/SD
> - PWM backlight
>
> Known broken:
> - USB
>
> Company page: https://linux-sunxi.org/Olimex_Teres-A64
> Community page: https://linux-sunxi.org/Olimex_Teres-A64
> hardware sources:
> https://github.com/OLIMEX/DIY-LAPTOP/tree/master/HARDWARE/A64-TERES/TERES-PCB1-A64-MAIN

We discussed to remove these.

>
> This patch enables support for the A64-Teres-I board to u-boot,
> including enabling screen backlight (lacking from Linux device-tree).
>
> Linux commit details about the sun50i-a64-teres-i.dts sync:
> "arm64: dts: allwinner: a64: Rename uart0_pins_a label to uart0_pb_pins"
> (sha1: d91ebb95b96c8840932dc3a10c9f243712555467)
>
> Cosmetic warnings regarding whitespace and placement of SPDX notice for
> dts file was ignored.
>
> config and .dtsi file are adapted from pinebook files.
>
> Tested-by: Jonas Smedegaard 
> Signed-off-by: Jonas Smedegaard 
> ---
>
>
> Changes for v2:
>   * List Icenowy and Jonas as MAINTAINERS
>   * Add commit hash in linux tree for sun50i-a64-teres-i.dts
>   * Drop superfluous and unsupported Author: tag
>
> Changes for v3:
>   * Use tags sun50i a64 (not sunxi)
>   * List key, working, and known broken features
>   * Reference upstream pages.
>   * Reference linux commit
>
> ---
>  MAINTAINERS |   8 +
>  arch/arm/dts/Makefile   |   3 +-
>  arch/arm/dts/sun50i-a64-teres-i-u-boot.dtsi |  41 +++
>  arch/arm/dts/sun50i-a64-teres-i.dts | 270 
>  configs/teres_i_defconfig   |  21 ++
>  5 files changed, 342 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/dts/sun50i-a64-teres-i-u-boot.dtsi
>  create mode 100644 arch/arm/dts/sun50i-a64-teres-i.dts
>  create mode 100644 configs/teres_i_defconfig
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index c77abba1e5..d6ba87a0ba 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -319,6 +319,14 @@ F: arch/arm/include/asm/arch-sunxi/
>  F: arch/arm/mach-sunxi/
>  F: board/sunxi/
>
> +ARM SUNXI OLIMEX TERES-I
> +M: Jonas Smedegaard 
> +M: Icenowy Zheng 
> +S: Maintained
> +T: git https://salsa.debian.org/js/u-boot

Same here

and you have to add this entry in board/sunxi/MAINTAINERS

> +F: arch/arm/dts/sun50i-a64-teres-i*
> +F: configs/teres_i_defconfig
> +
>  ARM TEGRA
>  M: Tom Warren 
>  S: Maintained
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 0aee8dfde0..eabe9e1ae3 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -483,7 +483,8 @@ dtb-$(CONFIG_MACH_SUN50I) += \
> sun50i-a64-pine64-plus.dtb \
> sun50i-a64-pine64.dtb \
> sun50i-a64-pinebook.dtb \
> -   sun50i-a64-sopine-baseboard.dtb
> +   sun50i-a64-sopine-baseboard.dtb \
> +   sun50i-a64-teres-i.dtb
>  dtb-$(CONFIG_MACH_SUN9I) += \
> sun9i-a80-optimus.dtb \
> sun9i-a80-cubieboard4.dtb \
> diff --git a/arch/arm/dts/sun50i-a64-teres-i-u-boot.dtsi 
> b/arch/arm/dts/sun50i-a64-teres-i-u-boot.dtsi
> new file mode 100644
> index 00..1a64b7d09c
> --- /dev/null
> +++ b/arch/arm/dts/sun50i-a64-teres-i-u-boot.dtsi
> @@ -0,0 +1,41 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2019 Vasily Khoruzhick 
> + *
> + */
> +
> +#include "sunxi-u-boot.dtsi"
> +
> +/ {
> +   vdd_bl: regulator@0 {
> +   compatible = "regulator-fixed";
> +   regulator-name = "bl-3v3";
> +   regulator-min-microvolt = <330>;
> +   regulator-max-microvolt = <330>;
> +   gpio = < 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
> +   enable-active-high;
> +   };
> +
> +   backlight: backlight {
> +   compatible = "pwm-backlight";
> +   pwms = < 0 5 0>;
> +   brightness-levels = <0 5 10 15 20 30 40 55 70 85 100>;
> +   default-brightness-level = <2>;
> +   enable-gpios = < 3 23 GPIO_ACTIVE_HIGH>; /* PD23 */
> +   power-supply = <_bl>;
> +   };
> +};
> +
> +/* The ANX6345 eDP-bridge is on i2c */
> + {
> +   anx6345: edp-bridge@38 {
> +   compatible = "analogix,anx6345";
> +   reg = <0x38>;
> +   reset-gpios = < 3 24 GPIO_ACTIVE_LOW>; /* PD24 */
> +   status = "okay";
> +   };
> +};
> +
> + {
> +   status = "okay";
> +};
> diff --git a/arch/arm/dts/sun50i-a64-teres-i.dts 
> 

[U-Boot] [PATCH v3] arm: socfpga: mailbox: Fix off-by-one error on command length checking

[Ley Foon Tan]

A mailbox command contains 1-DWORD header + arguments. The "len" variable
only contains the length of the arguments, but not the 1-DWORD header.
Include the length of header when checking the ring buffer space to
prevent off-by-one error.

Signed-off-by: Ley Foon Tan 
Signed-off-by: Chee Hong Ang 
---
v2->v3:
- Update commit description.
---
 arch/arm/mach-socfpga/mailbox_s10.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-socfpga/mailbox_s10.c 
b/arch/arm/mach-socfpga/mailbox_s10.c
index 3c33223936..8363c93e90 100644
--- a/arch/arm/mach-socfpga/mailbox_s10.c
+++ b/arch/arm/mach-socfpga/mailbox_s10.c
@@ -59,7 +59,7 @@ static __always_inline int mbox_fill_cmd_circular_buff(u32 
header, u32 len,
 */
if (((cin + 1) % MBOX_CMD_BUFFER_SIZE) == cout ||
((MBOX_CMD_BUFFER_SIZE - cin + cout - 1) %
-MBOX_CMD_BUFFER_SIZE) < len)
+MBOX_CMD_BUFFER_SIZE) < (len + 1))
return -ENOMEM;
 
/* write header to circular buffer */
-- 
2.19.0

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Re: [U-Boot] [PATCH v2 3/3] mach-meson: g12a: add DWC2 peripheral mode support

[Lukasz Majewski]

Hi Neil,

> Adds support for Amlogic G12A USB Device mode.
> 
> The DWC2 Controller behind the Glue can be connected to an OTG
> capable PHY. The Glue setups the PHY mode.
> 
> This patch implements Device mode support by adding a
> board_usb_init/cleanup setting up the DWC2 controller and switch the
> OTG capable port to Device before starting the DWC2 controller in
> Device mode.
> 
> Signed-off-by: Neil Armstrong 

I wanted to apply this series, but it turned out that it depends on:
[U-Boot] [PATCH v2 0/6] ARM: meson: Add support for G12A based U200
board

Let's wait till the above one is pulled to master.

> ---
>  arch/arm/include/asm/arch-meson/usb.h |  12 +++
>  arch/arm/mach-meson/board-g12a.c  | 126
> ++ 2 files changed, 138 insertions(+)
>  create mode 100644 arch/arm/include/asm/arch-meson/usb.h
> 
> diff --git a/arch/arm/include/asm/arch-meson/usb.h
> b/arch/arm/include/asm/arch-meson/usb.h new file mode 100644
> index 00..b794b5ce77
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-meson/usb.h
> @@ -0,0 +1,12 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (C) 2019 BayLibre, SAS
> + * Author: Neil Armstrong 
> + */
> +
> +#ifndef __MESON_USB_H__
> +#define __MESON_USB_H__
> +
> +int dwc3_meson_g12a_force_mode(struct udevice *dev, enum usb_dr_mode
> mode); +
> +#endif /* __MESON_USB_H__ */
> diff --git a/arch/arm/mach-meson/board-g12a.c
> b/arch/arm/mach-meson/board-g12a.c index fc3764b960..1652970fbd 100644
> --- a/arch/arm/mach-meson/board-g12a.c
> +++ b/arch/arm/mach-meson/board-g12a.c
> @@ -12,7 +12,12 @@
>  #include 
>  #include 
>  #include 
> +#include 
> +#include 
> +#include 
> +#include 
>  #include 
> +#include 
>  
>  DECLARE_GLOBAL_DATA_PTR;
>  
> @@ -148,3 +153,124 @@ void meson_eth_init(phy_interface_t mode,
> unsigned int flags) /* Enable power gate */
>   clrbits_le32(G12A_MEM_PD_REG_0, G12A_MEM_PD_REG_0_ETH_MASK);
>  }
> +
> +#if CONFIG_IS_ENABLED(USB_DWC3_MESON_G12A) && \
> + CONFIG_IS_ENABLED(USB_GADGET_DWC2_OTG)
> +static struct dwc2_plat_otg_data meson_g12a_dwc2_data;
> +
> +int board_usb_init(int index, enum usb_init_type init)
> +{
> + struct fdtdec_phandle_args args;
> + const void *blob = gd->fdt_blob;
> + int node, dwc2_node;
> + struct udevice *dev, *clk_dev;
> + struct clk clk;
> + int ret;
> +
> + /* find the usb glue node */
> + node = fdt_node_offset_by_compatible(blob, -1,
> +
> "amlogic,meson-g12a-usb-ctrl");
> + if (node < 0) {
> + debug("Not found usb-control node\n");
> + return -ENODEV;
> + }
> +
> + if (!fdtdec_get_is_enabled(blob, node)) {
> + debug("usb is disabled in the device tree\n");
> + return -ENODEV;
> + }
> +
> + ret = uclass_get_device_by_of_offset(UCLASS_SIMPLE_BUS,
> node, );
> + if (ret) {
> + debug("Not found usb-control device\n");
> + return ret;
> + }
> +
> + /* find the dwc2 node */
> + dwc2_node = fdt_node_offset_by_compatible(blob, node,
> +
> "amlogic,meson-g12a-usb");
> + if (dwc2_node < 0) {
> + debug("Not found dwc2 node\n");
> + return -ENODEV;
> + }
> +
> + if (!fdtdec_get_is_enabled(blob, dwc2_node)) {
> + debug("dwc2 is disabled in the device tree\n");
> + return -ENODEV;
> + }
> +
> + meson_g12a_dwc2_data.regs_otg = fdtdec_get_addr(blob,
> dwc2_node, "reg");
> + if (meson_g12a_dwc2_data.regs_otg == FDT_ADDR_T_NONE) {
> + debug("usbotg: can't get base address\n");
> + return -ENODATA;
> + }
> +
> + /* Enable clock */
> + ret = fdtdec_parse_phandle_with_args(blob, dwc2_node,
> "clocks",
> +  "#clock-cells", 0, 0,
> );
> + if (ret) {
> + debug("usbotg has no clocks defined in the device
> tree\n");
> + return ret;
> + }
> +
> + ret = uclass_get_device_by_of_offset(UCLASS_CLK, args.node,
> _dev);
> + if (ret)
> + return ret;
> +
> + if (args.args_count != 1) {
> + debug("Can't find clock ID in the device tree\n");
> + return -ENODATA;
> + }
> +
> + clk.dev = clk_dev;
> + clk.id = args.args[0];
> +
> + ret = clk_enable();
> + if (ret) {
> + debug("Failed to enable usbotg clock\n");
> + return ret;
> + }
> +
> + meson_g12a_dwc2_data.rx_fifo_sz = fdtdec_get_int(blob,
> dwc2_node,
> +
> "g-rx-fifo-size", 0);
> + meson_g12a_dwc2_data.np_tx_fifo_sz = fdtdec_get_int(blob,
> dwc2_node,
> + "g-np-tx-fifo-size",
> 0);
> + meson_g12a_dwc2_data.tx_fifo_sz = fdtdec_get_int(blob,
> dwc2_node,
> +
> "g-tx-fifo-size", 0); +
> + /* Switch to peripheral mode */
> + ret = dwc3_meson_g12a_force_mode(dev,
> USB_DR_MODE_PERIPHERAL);
> + if (ret)
> + return ret;
> +
> + return