Re: [ARTIQ] FW: initial specification of the project

, March 30, 2016 1:50 PM To: Grzegorz Kasprowicz <kaspr...@gmail.com> Cc: 'Slichter, Daniel H. (Fed)' <daniel.slich...@nist.gov>; 'Grzegorz Kasprowicz' <gkasp...@elka.pw.edu.pl>; artiq@lists.m-labs.hk Subject: Re: [ARTIQ] FW: initial specification of the project On Tuesday, 29 March 20

Re: [ARTIQ] FW: initial specification of the project

h=X=0ahUKEwj19L7younLAhUKvXIKHQVBCg8Q_AUIBigB#tbm=isch=castellated+RF+modules> On 30 March 2016 at 22:40, Grzegorz Kasprowicz <kaspr...@gmail.com> wrote: > One more thing - we can fit 5 SMA connectors on FMC panel, in case of 6 > ones, we won't be able to screw them. > But we can install MMCX ones for clocks

Re: [ARTIQ] FW: initial specification of the project

Actually HPC with LPC IO assignment and 8 x GTP links is popular configuration So you have 34 LVDS pairs and 8 GTP links. On 30 March 2016 at 23:00, Slichter, Daniel H. (Fed) < daniel.slich...@nist.gov> wrote: > > On Wed, Mar 30, 2016 at 10:25 PM, Slichter, Daniel H. (Fed) > >

Re: [ARTIQ] FW: initial specification of the project

On Tuesday, 29 March 2016 11:14:14 PM HKT Grzegorz Kasprowicz wrote: > [GK] If you don't use ARM, you still get hardened SDRAM controller and > GBE MACs. Yes, that's what I was saying: you cannot get rid of them (i.e. use their pins like other IOs). So you need to use the Zynq-sp

Re: [ARTIQ] FW: initial specification of the project

ucq <s...@m-labs.hk>; Grzegorz Kasprowicz <kaspr...@gmail.com> Cc: 'Grzegorz Kasprowicz' <gkasp...@elka.pw.edu.pl>; artiq@lists.m-labs.hk Subject: RE: [ARTIQ] FW: initial specification of the project > I like this plan. I think 4 + 4 channels will also make the front >

Re: [ARTIQ] FW: initial specification of the project

to be verified. On 30 March 2016 at 23:02, Slichter, Daniel H. (Fed) < daniel.slich...@nist.gov> wrote: > This is an interesting potential solution although I am not sure how the > signal integrity is at ~3 GHz, for example. > > > > *From:* Grzegorz Kasprowicz [mailto:kaspr...@gmail.

Re: [ARTIQ] FW: initial specification of the project

Are we talking about double width AMCs? Two DAC channels and 2 RF modules should fit. Greg -Original Message- From: Sébastien Bourdeauducq [mailto:s...@m-labs.hk] Sent: Wednesday, March 30, 2016 5:46 PM To: Leibrandt, David R. (Fed) <david.leibra...@nist.gov> Cc: Grzegorz Kasp

Re: [ARTIQ] FW: initial specification of the project

FMC > daughtercard itself, as close to the amplifiers etc as possible. > > > > Using the alternating grounds a la CERN seems like a suitable solution to > me for sending in these additional analog rails. > > > > *From:* Grzegorz Kasprowicz [mailto:kaspr...@gmail.com] > *Sent

Re: [ARTIQ] FW: initial specification of the project

Well, we can do another crazy thing - solder small module with RF stuff on the FMC board, under same shield. In this way we keep 3 simple FMCs with expensive ADCs/DACs and define the functionality by soldering (automatic or manual) of just RF modules. WE can even design such modules to hold the

Re: [ARTIQ] Fwd: FW: initial specification of the project

of the project On Wed, Mar 30, 2016 at 9:53 PM, Grzegorz Kasprowicz <gkasp...@elka.pw.edu.pl> wrote: > Maybe we should come back to the roots:) What if we use standard FMCs > (LPC) with DAC/ADC channels and RF stuff _on_ them. > JESD204B and some pins would go to the FPGA while DAC and

Re: [ARTIQ] FW: initial specification of the project

On 31 March 2016 at 04:58, Sébastien Bourdeauducq <s...@m-labs.hk> wrote: > On Wednesday, 30 March 2016 9:37:51 PM HKT Grzegorz Kasprowicz wrote: > > Well, you don't have to write it. > > It is already available for RTOS and linux. > > We are not using RTOS or Li

Re: [ARTIQ] FW: initial specification of the project

this architecture. > > > > *From:* Grzegorz Kasprowicz [mailto:kaspr...@gmail.com] > *Sent:* Wednesday, March 30, 2016 3:36 PM > > *To:* Slichter, Daniel H. (Fed) <daniel.slich...@nist.gov> > *Cc:* Robert Jördens <r...@m-labs.hk>; Grzegorz Kasprowicz

Re: [ARTIQ] DSP gateware

Yes, but for such speed you don't need to match better than several mm. Greg On 31 March 2016 at 13:51, Robert Jördens wrote: > On Thu, Mar 31, 2016 at 8:51 AM, Florent Kermarrec > wrote: > > When choosing between Artix7 or Kintex7 you also have to

Re: [ARTIQ] FW: initial specification of the project

One more thing In case of ZynQ, instead of ZU11, we have smaller GTX count version - ZU7 in the same package. Its cost is about 700-750$. So we can install ZU7 by default, and when necessary, upgrade it to ZU11. Greg -Original Message- From: Grzegorz Kasprowicz [mailto:gkasp

Re: [ARTIQ] FW: initial specification of the project

are dedicated to the clock distribution. Greg On 8 April 2016 at 12:25, Sébastien Bourdeauducq <s...@m-labs.hk> wrote: > On Friday, 8 April 2016 12:02:43 PM HKT Grzegorz Kasprowicz wrote: > > The MTCA backplane is not designed to distribute RF or analog clocks. > > > > Definitely t

Re: [ARTIQ] FW: initial specification of the project

Anyway, we have already plenty of things to do so I'd relay on existing backplane at the moment:) On 8 April 2016 at 12:51, Grzegorz Kasprowicz <kaspr...@gmail.com> wrote: > Well, I don't have such template so all must be done from scratch. > It's really big piece of PCB, we need a

Re: [ARTIQ] FW: initial specification of the project

> > Why do you think that CPUs have negative value? You don't have to use > them > > at all. > > I already explained that the MPSoC has to be dealt with and cannot be > completely ignored. If we have two SDRAM systems, maybe we can to a > reasonable > extent, but then it does complicate the board.

Re: [ARTIQ] FW: initial specification of the project

lane communication... Indeed, in this way we could move the noise spectrum much higher, where it’s easier to filter it out. Greg From: kaspr...@gmail.com <mailto:kaspr...@gmail.com> [mailto:kaspr...@gmail.com] On Behalf Of Grzegorz Kasprowicz Sent: 08 April 2016 11:34 To: Thomas Hart

Re: [ARTIQ] FW: initial specification of the project

synchronously apply reset pulse to all AMCs, exactly in the same ways as in case of clock distribution over the backplane . Best regards, Greg From: Thomas Harty [mailto:thomas.ha...@physics.ox.ac.uk] Sent: Friday, April 08, 2016 8:04 PM To: Grzegorz Kasprowicz <g.kasprow...@elka.pw.edu

Re: [ARTIQ] TTL + slow DACs

:48, Grzegorz Kasprowicz <kaspr...@gmail.com> wrote: > Well, yes, providing that you find charger that won't fail after 500 hours > :) > > > -Original Message- > From: Sébastien Bourdeauducq [mailto:s...@m-labs.hk] > Sent: Thursday, March 31, 2016 12:42 PM >

Re: [ARTIQ] FW: initial specification of the project

: ARTIQ [mailto:artiq-boun...@lists.m-labs.hk] On Behalf Of Slichter, Daniel H. (Fed) Sent: Monday, March 28, 2016 5:25 PM To: Sébastien Bourdeauducq <s...@m-labs.hk> Cc: Grzegorz Kasprowicz <gkasp...@elka.pw.edu.pl>; artiq@lists.m-labs.hk Subject: Re: [ARTIQ] FW: initial specification of

Re: [ARTIQ] analog extension cards

I can agree that FMC is not the best idea in case of RF stuff. There are multipin RF board 2 board coaxial connectors which can be used for plugin modules. And such modules can be easily shielded using i.e. Wurth shields or EZ-Shields from Harwin that can be easily customized. Greg

Re: [ARTIQ] FW: initial specification of the project

On Friday, 25 March 2016 12:24:02 PM HKT you wrote: > * whether or not we use Zynq remains to be decided. > **The price difference is not that high (a few tens of $) and we get > plenty of CPU power Yes, but Zynq chips are annoying to program (even if we do not use the ARM cores) and more

Re: [ARTIQ] TTL + slow DACs

Well, yes, providing that you find charger that won't fail after 500 hours :) -Original Message- From: Sébastien Bourdeauducq [mailto:s...@m-labs.hk] Sent: Thursday, March 31, 2016 12:42 PM To: Grzegorz Kasprowicz <kaspr...@gmail.com> Cc: Slichter, Daniel H. (Fed) <dan

Re: [ARTIQ] TTL + slow DACs

Well, we can use in this case the AMC board plugged into dual AMC box which has 4 SFPs. In some cases this could be an overkill, but it is working solution. http://www.ohwr.org/projects/amc-ubackplane-sfp/wiki On 31 March 2016 at 12:05, Sébastien Bourdeauducq wrote: > On

Re: [ARTIQ] White Rabbit: SFP vs SFP+

On 19 July 2016 at 17:47, j arl wrote: > Greg, Others, Thinking about using SFP+ on new hardware (Sayma, > Metlino). If SFP+ is backward compatible with SFP, m-labs could > attempt DRTIO using SFP+ transceivers and fall back to > WhiteRabbit-approved SFP as backup [1].

Re: [ARTIQ] sayma gateware updates

On 24 July 2016 at 14:19, Sébastien Bourdeauducq <s...@m-labs.hk> wrote: > Hi, > > On Sunday, July 24, 2016 07:33 PM, Grzegorz Kasprowicz wrote: > >> > When receiving a bitfile, a board (Metlino/Sayma) writes it to its >> > flash memory (via a SPI master co

Re: [ARTIQ] uTCA backplane driver choices

at 18:17, Sébastien Bourdeauducq <s...@m-labs.hk> wrote: > On Tuesday, June 28, 2016 04:00 PM, Grzegorz Kasprowicz wrote: > >> For Sayma board to not waste precious GTX we will add PHY with >> 1000Base-X. We can also route it to SATA connector and provide dedicated

Re: [ARTIQ] clock recovery on Metlino and Kasli

OK On 30 June 2016 at 10:50, Sébastien Bourdeauducq <s...@m-labs.hk> wrote: > On Thursday, June 30, 2016 04:49 PM, Grzegorz Kasprowicz wrote: > >> In case of WR it already worked quite well 6 years ago but later on this >> circuit was modified several times:) >> All

Re: [ARTIQ] clock recovery on Metlino and Kasli

-labs.hk] Sent: Thursday, June 30, 2016 5:57 AM To: Grzegorz Kasprowicz <kaspr...@gmail.com>; j arl <joe.britton@gmail.com> Cc: Robert Jördens <r...@m-labs.hk>; artiq@lists.m-labs.hk Subject: Re: clock recovery on Metlino and Kasli Hi, my question was whether one can get rid of

Re: [ARTIQ] clock recovery on Metlino and Kasli

've moved to this > conversation to a new thread. > > On Tuesday, June 28, 2016 04:02 PM, Grzegorz Kasprowicz wrote: > > For synchronisation over fibre we can use existing White Rabbit core. > > The card requires only 2 VCXO oscillators and FPGA logic. The WR core > > consumes 50% of smal

Re: [ARTIQ] uTCA backplane driver choices

we can use Si instead of CDCM61004RHBT Greg On 29 June 2016 at 04:56, Sébastien Bourdeauducq <s...@m-labs.hk> wrote: > On Tuesday, June 28, 2016 04:02 PM, Grzegorz Kasprowicz wrote: > >> For synchronisation over fibre we can use existing White Rabbit core. >> The c

Re: [ARTIQ] Sinara clocking

Which FPGA - on AMC or on RTM should generate SYSREF clock? I mean connection of HMC7043 RFSYNCIN pins. ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq

Re: [ARTIQ] Sinara multi-crate / DRTIO switches

We can use multiple 10Gbit links in parallel between Metlinos but the latency would be the same. ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq

Re: [ARTIQ] shared SPI clock

on Sayma RTM FPGA we have enough pins to do p2p connections for all SPI chips, and so I did. ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq

Re: [ARTIQ] plans for clock chip, JESD and DAC initialization/configuration

Just use Aurora IP core or something with similar functionality. You have 2 bidir links, one can be used for DRTIO, second for simple control protocol. >From one side you have some inputs that are repeated on the other side. You can run UART, SPI or whatever you want since it is transparent. I

Re: [ARTIQ] ARTIQ Digest, Vol 34, Issue 3

You don’t have to do combined order. Just drop an email that you want to order 10 pieces with each board shipped to certain place. Only transportation cost will apply. Greg From: Neal Pisenti [mailto:npise...@gmail.com] Sent: Wednesday, March 15, 2017 9:37 PM To: Grzegorz Kasprowicz

[ARTIQ] [SINARA] hardware arrived!

look here https://cloud.githubusercontent.com/assets/4325054/24015076/98f7653a-0a87-11e7-93d2-7df1831b2422.jpg ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq

Re: [ARTIQ] ARTIQ Digest, Vol 34, Issue 3

I already received assembled 3U boards including VHDCI carrier and BNC IO. So we can test whole setup in the lab quickly. You can help us with simple HDL design for KC705 that i.e. toggles IOs or makes loopback: ttl->lvds->VHDCI-> FPGA-> VHDCI->lvds->TTL. At the moment we are so occupied with

Re: [ARTIQ] ARTIQ Digest, Vol 34, Issue 3

It is compatible with VHDCI carrier - I used the same pinout. I have 2 pieces in lab to do tests. Moreover, to do quick tests I designed another simple adapter that converts TTL to LVDS. Sources are here: https://github.com/m-labs/sinara/tree/master/ARTIQ_ALTIUM/Kasli/3U/PCB_3U_Tester. Can be

Re: [ARTIQ] ARTIQ Digest, Vol 37, Issue 6

Usually one can expect half of octopart prices. So the difference would be about 30$ On 29 June 2017 at 21:43, Joe Britton via ARTIQ wrote: > Octopart Avnet costs for 1 unit > > XC7A100T-2CSG324C $131.22 > XC7A50T-2CSG324C $74.98 > > Greg, What is the cost differential

Re: [ARTIQ] ARTIQ Digest, Vol 37, Issue 7

gt; >> > >> Today's Topics: > >> > >> 1. Re: ARTIQ Digest, Vol 37, Issue 6 (Thomas Harty) > >> 2. Re: ARTIQ Digest, Vol 37, Issue 6 (Slichter, Daniel H. (Fed)) > >> 3. Re: ARTIQ Digest, Vol 37, Issue 6 (Sébastien Bourdeauducq) > >

Re: [ARTIQ] SFP/SATA cables for connecting Ethernet on Sayma

PM To: Grzegorz Kasprowicz <kaspr...@gmail.com> Cc: artiq@lists.m-labs.hk Subject: SFP/SATA cables for connecting Ethernet on Sayma Hi Greg, just a quick note about the SFP/SATA cable that is necessary to connect Ethernet on a Sayma directly. I suggest building them from a passive SFP