Re: OPCODE tables

This solution is a bit tedious, but you could first check Appendix J in Principles of Operation to see if the instruction is an extended mnemonic, and if it is then obtain the base mnemonic. Then you could look up the base mnemonic using the OPTABLE(LIST) approach described elsewhere. There

Re: Inner macro and PRINT NOGEN

eddelelse- > Fra: IBM Mainframe Assembler List På > vegne af Mark Boonie > Sendt: 1. december 2023 18:48 > Til: ASSEMBLER-LIST@LISTSERV.UGA.EDU > Emne: Re: Inner macro and PRINT NOGEN > > Does your assembly have the LIBMAC option in effect? Look at the first >

Re: Inner macro and PRINT NOGEN

Does your assembly have the LIBMAC option in effect? Look at the first page or two to see the list of options in effect. If it is in effect, though, you should see the same behavior for all other library macros as well (if any). Is this the case? - mb > -Original Message- > From:

Re: BAKR/PR and Linkage Convention

Since isn't a system variable, that behavior would depend on what you set to. If you use then the generated alignment should be based on the start of the CSECT. - mb > -Original Message- > From: IBM Mainframe Assembler List On > Behalf Of Bill Hitefield > Sent: Thursday, November

Re: BAKR/PR and Linkage Convenction

I'm not sure what update to HLASM provided this capability, but you can use: ORG *,256 If you don't have the requisite update to the ORG statement, you can use a macro, of which many are in circulation. Here's one with a slightly different syntax -- the first parameter is the

Re: ASMA057E Undefined operation code SR 15,15

The latest System Processor Optimization Primer has this to say (hopefully the indentation will be retained, or at least be self-evident if it isn't): For most cases (in real life code), the differences between SR/XR vs. LHI or SGR/XGR vs. LGHI will not be noticeable Obtaining the ultimate

Re: EXCP CCB Status Code Error

The x'40' is an incorrect-length indication. If you're using format-0 CCWs then the count field is required to be non-zero. As a result, a NOP, which doesn't transfer any data, will always end with the CCW count \= 0. If the ORB does not have the incorrect-length-suppression (L) bit set and

Re: Generating a TR field

meters, using N', then the macro may treat an empty parameter > as an invalid parameter. ... > > > ________ > > From: Mark Boonie [???@US.IBM.COM] > > Sent: Sunday, May 29, 2022 1:58 PM > > ... > > One of the reasons it's import

Re: Generating a TR field

Fortunately I've never seen a macro coded like that, although it certainly seems possible. However, I would consider that to be a demented flaw in the macro design rather than the language. I do see your point, though, about wanting some construct that would always indicate the start of the

Re: Generating a TR field

I didn't quite understand your point about one of the two macros being valid, so I apologize if I'm stating the obvious. I think the problem you're describing stems from the fact that in HLASM, the remarks for a given line begin after the operand entry for that line ends. If you have an

Re: Next instruction needed

> Conceptually,the MVCL instruction could treat cases that specified the > same register pair for source and target operands as a request to clean or > fill the designated storage area. You'd have to change the current behavior of MVCL -- when the same register is specified for both operands, it

Re: Long Displacement Facility (was: Fun with RXSBG)

> What is the macro to generate facility bit EQUs? In TPF, it's IZARCH.  For the z/OS macro, I'd have to phone a friend. Actually I just did a Google search and found IHAPSAE, which itself points you to IHAFACL. - mb

Re: Long Displacement Facility (was: Fun with RXSBG)

> I went back and checked: > > > o Long-displacement facility was first documented in SA22-7832-02 > > o STFLE was first documented in SA22-7832-04 If you need to test a facility bit in the range of 0-31 then use the list of bits stored by the STORE FACILITY LIST instruction, which should

Re: Branch-and-Link nomenclature question

Oh, good, it must be Friday, (Wait, what's that? It's not? Drat.) I'd probably call the set of instructions "linkage" instructions, or "program linkage" instructions. When describing the logic flow to someone, I tend to say "call a subroutine" or "link to a subroutine", but I sometimes

Re: Saving Caller's 64-bit Registers

> * The fact that is so confusing implies that the Assembler Services > Guide is not doing a good job of explaining it. It is hard to > understand because it defies expectations. What you *expect* is that > you have a value that describes the format of a structure, and by > implication, its

Re: Saving Caller's 64-bit Registers (was "...Regsiters")

> This provides the cornerstone of a GREAT SHARE presentation you oughtta > give wunna these days! Funny, I'm looking at a SHARE presentation, from August 2012, that I refer to when I have questions about how this stuff works. It's by some guy named -- well, what do you know -- Tom Marchant.

Re: Base-less macros

> In that scenario, offset 4 of Xs save area will no longer contain > FnSA, and can thus be identified as the forward pointer of a 72-bytesave area. The point that several recent posts have been trying to make is that the contents of word 1 indicate how the registers were saved in the

Re: Base-less macros

> The one case where there could be an issue is if the > routine calls both code expecting a 72-byte save area and code > calling a 144-byte area. > > If the linkage conventions are followed, under what circumstances > would you be unable to follow the forward chain with a little bit of work?

Re: MNOTE imbedded apostrophes / ASMA163W

> I guess, to show the content of a SETC variable symbol in MNOTE, > you will have to double the apostrophes. That is: copy the symbol to > another one, call a macro which doubles the apostrophes and then > show this other symbol. The built-in function DOUBLE might come in handy. From the

Re: Base-less macros

So Jonathan doesn't have to respond: > And LA R1,-CL128'x' on a 128 byte boundary? >From the Language Reference: Each literal pool has five segments into which the literals are stored (a) in the order that the literals are specified, and (b) according to their assembled lengths, which, for

*-*

I've probably been writing assembler for too long to be asking this question now, but what is the purpose of coding '*-*' in some assembler expressions? I've seen it in parameter lists (usually as an adcon), operands of executed instruction (e.g., MVC 0(*-*,5),0(6)), etc. As far as I can tell

Re: Determing the Presence of an Instruction

> > What happens on an older model where a field is "reserved, must be zero" > if the programmer supplies a non-zero value which would be valid on a > newer model? > > Perhaps, architecturally, the answer is: the behavior is undefined or > machine-dependent. > I would guess that in most cases

Re: Multi CPU interlock question

> Does CS tell the right story, or does CS itself require alignment? The updated storage area is required to be fullword aligned, which is why you could/should just skip the CS. - mb

Re: Multi CPU interlock question

Speaking for myself, I would consider it "proper" to align the operands and skip the CS -- the architecture guarantees the behavior, so doing the update with CS seems like overkill. (I'd probably also add a comment in the code for each operand pointing out the reason for the alignment

Re: Multi CPU interlock question

On all z/Architecture CPUs, MVC will appear fullword-concurrent provided both the source and target operands are fullword-aligned. - mb IBM Mainframe Assembler List wrote on 01/09/2019 06:17:29 AM: > MVC might on some CPUs appear to do it 4 byte wise (or other multiples > thereof) -

Re: Getting the Last Condition code

There's also EPSW, which gives you a lot more than just the condition code and program mask. - mb IBM Mainframe Assembler List wrote on 12/06/2018 10:03:39 PM: > BALR should also lead the OP to other similar instructions to do what > he wants.

Re: An idea I got when researching a bug - warnings when a specific register is changed

I like the idea -- in fact it was on my Christmas Wish List that I sent to John E. every once in a while. How desirable would it be to not tie it to a USING? There's no reason a register other than a USING base shouldn't be able to be declared Constant. Making it part of a USING would make

Re: FIND or INDEX builtin function

If you want the position of the first non-blank character then use WordIndex(string, 1). If you want the character itself then use Left(Word(string, 1), 1). Obviously you should include checks to handle the lack of any non-blank characters. - mb IBM Mainframe Assembler List

OPTABLE error

I spent an hour or so fighting with my build environment because I thought it was ignoring my options, but now I think I have an HLASM bug. I'm specifying OPTABLE(ZS6,LIST) as a *PROCESS option. The "Options for this Assembly" page shows that the option has been processed correctly ("3

Re: Any real need for sequence numbers in 73-80 any more?

I grew leery of CMS UPDATE when I found it couldn't handle updating files that contain lines that look like update control cards. I know it's not very likely that anyone would ever maintain an UPDATE file by using UPDATE, but stuff like that always makes me wonder what else isn't being handled

Re: random quest

Perhaps there's something about the question I don't understand, but if you want 99,999 unique 5-digit numbers then you'll end up with the numbers 0 to 9. Or do you just want the *order* of the numbers to be random? - mb

Re: HLASM "Anomaly"

One reason to implement the messages as warnings instead of errors is that warnings can be suppressed, using options like SUPRWARN, TYPECHECK, FLAG, ALIGN, USING(WARN()), and maybe others. Some of these warnings can also be suppressed "locally" using ACONTROL. I'm not aware of any errors that

Re: Transactional Execution - anybody used it?

> So. Has anyone on this forum actually used the TBEGIN and TEND instructions > in their code? I would appreciate knowing what / why they chose to do so. > I'm just trying to understand the real purpose of these instructions on a > PRACTICAL level. Yes, I've read up on "Transactional Memory" on

Re: HLASM anomaly

> Were I to rebut each of your hypothetical objections you could of course > rebut my rebuttals. I will only point out that often the coder does not have > control over how flags are defined: they are defined in some system or > "external" DSECT or similar. I concede that readily. My thinking

Re: HLASM anomaly

> It is perhaps a silly example. But suppose R1 was to contain a pair > of flag byte values. Suppose the flags were equated. Now it might > make sense to code > > LHI R1,2AL1(MYFLAG1) > > Or something like that. Yes you can code the following but it is no > great exemplar of coding clarity:

New HLASM RFE

This afternoon I submitted an RFE requesting new capabilities for HLASM. My intent was to make it easier to deal with DSECTs whose size needs to be an integral power of 2. This is perhaps not interesting to most of you. However, the requested capabilities -- exponentiation, base-2 logs, etc.

Re: Csect - Dsect Question

z/TPF has supported RMODE64 code for over 10 years. But we're a little different than most other OSes. :-) - mb IBM Mainframe Assembler List wrote on 04/01/2016 02:17:06 PM: > is RMODE64 supported yet on any op-sys (and don't forget > Scott; he wants it for

Re: Generating warning for AL2 expression truncation?

The maximum length of a hexadecimal constant is 256 for a DC statement; for a DS statement it's 64K-1. For fixed-point constants (H or F, but not Y), you can use Uddd for an unsigned value. For example, DC H'U4' will generate 9C40. - mb IBM Mainframe Assembler List

Re: load logical halfword immediate

Perhaps the OP wanted to have HLASM diagnose when a value is used that is too large; IILF would be silent instead of generating ASMA320W. Just speculating - mb Tony Harminc wrote on 01/21/2016 01:56:48 PM: > On 20 January 2016 at 14:21, Swarbrick, Frank >

Reltive branches to outside a control section

Is it possible to branch to a location in low storage (say, location x'1234') using a relative-branch instruction where the target is a symbol defined in a DSECT for which a USING is established at location 0? If so, I can't seem to discover the proper incantation. Any ideas? Thanks. - mb

Re: Reltive branches to outside a control section

The code will run on TPF, but a platform-independent answer is probably the best option. - mb Mark Boonie z/TPF Development 845-433-4918 (t/l 293-4918) From: Gary Weinhold <weinh...@dkl.com> To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Date: 12/16/2015 12:03 PM Subject:Re: R

Re: Reltive branches to outside a control section

ntrol section > Sent by: IBM Mainframe Assembler List <ASSEMBLER-LIST@LISTSERV.UGA.EDU> > > On 16 December 2015 at 11:55, Mark Boonie <boo...@us.ibm.com> wrote: > > Is it possible to branch to a location in low storage (say, > location x'1234') using a relative-branch inst

Re: Fw: Rounding to a 2G-byte boundary

Actually I may end up defining a new macro after all. I can use the RISBG instruction instead: RISBGZ reg,reg,0,63-power This avoids all of the extra instructions and also avoids using a second register. - mb Mark Boonie z/TPF Development 845-433-4918 (t/l 293-4918) From: Steve Smith

Re: Rounding to a 2G-byte boundary

-LIST@LISTSERV.UGA.EDU On 2015-06-25 16:00, Mark Boonie wrote: However, I can't specify the boundary as a symbol equated to 2G (e.g., SEGTBLRANGE EQU X'8000') without getting an assembler error due to an overflow in an intermediate value. Does anyone have any alternative ways

Rounding to a 2G-byte boundary

I have macro that currently looks like this: MACRO , RNDUP REG,BOUND AGHI REG,BOUND-1 RNDDOWN REG,BOUND MEND , I was trying to update it to use the newer ALGFI instruction like this: MACRO , RNDUP REG,BOUND ALGFI

Re: Redesigning the Principles of Operation Manual

What ADD instructions do I have? What exactly does TROT do? What instructions does this particular facility contain? What does the opcode 0FE0 do? The first question isn't readily addressed by the current form of Principles of Operation, but the last three are. - To see exactly what TROT

Re: Redesigning the Principles of Operation Manual

A page eject before each instruction doesn't matter to me one way or another. I rarely print instruction write-ups so the extra paper isn't an issue. In PDF form, the size is almost irrelevant. I wouldn't like single-column format, though. I'm not a usability expert, but I find that on

Re: Redesigning the Principles of Operation Manual

I'm not sure how much drilling down you'd like to do once you're at the instruction level, but FYI, Appendix B contains three tables of instructions just as you asked for, arranged by name, mnemonic, and operation code. Each table entry has a link to the instruction description. Hopefully

What does the 'end' address on a USING statement mean?

I recently started looking at the 'end' specification for the USING statement, something I've neglected for a long time. I *thought* it indicated the last location that could be assembled with that USING, but I'm not so sure any more. I have the following source file: dummycsect ,

Re: What does the 'end' address on a USING statement mean?

This may not clarify the issue, but isn't the offset in the LG instruction 20-bit? That would mean that it can address 0 to F, or 0 to 1,048,575, right? Actually, Chuck, it's a signed displacement, so it can address -512K - 512K-1 from the address in the base and index registers.

Re: ML and Architecture Level Set

In chapter 7 of ESA/390 Principles of Operation, section Instructions, Programming Note 11 says The following additional general instructions are available in the ESA/390 architectural mode when the z/Architecture architectural mode is installed, after which follows the list of N3

Re: Carmine Cannatello's book

I *think* FORMAC was an IBM product. If it's the same thing I'm thinking of, I discovered in college that it was installed on our system and I played with it once in a while. It would also evaluate formulas symbolically and print equations in a format roughly similar to a hand-written style.

Re: macros to implement opcodes

Like John Gilmore, I (strongly) dislike hard-coded 3's and 4's, especially when a macro generates several instructions that must be ORG'ed into and around. Labels are our friends. If I were writing this macro and found that the user-supplied label was optional, I would probably write code to

Re: macros to implement opcodes

reason, hopefully someone will let me know. - mb IBM Mainframe Assembler List ASSEMBLER-LIST@listserv.uga.edu wrote on 12/21/2013 03:11:29 PM: From: Mark Boonie/Poughkeepsie/IBM@IBMUS To: ASSEMBLER-LIST@listserv.uga.edu, Date: 12/21/2013 03:14 PM Subject: Re: macros to implement opcodes Sent

Re: macros to implement opcodes

One that comes to mind is the DIAG macro in VM's DMSOM maclib. I'm sure z/OS has its version, too. - mb IBM Mainframe Assembler List ASSEMBLER-LIST@listserv.uga.edu wrote on 12/20/2013 04:21:28 PM: From: Ian S. Worthington ianworthing...@usa.net To: ASSEMBLER-LIST@listserv.uga.edu, Date:

Re: Which instructions available on which machine table?

(I apologize in advance for not answering your question.) I always get uneasy when I see questions about when an instruction was *first* available. There's no assumption in Principles of Operation that once an instruction is introduced then it will be on all following machine. I know that in

Re: Which instructions available on which machine table?

, code to my best guest as to my current 'lowest denominator' customer. Tony Thigpen -Original Message - From: Mark Boonie Sent: 12/11/2013 03:28 PM (I apologize in advance for not answering your question.) I always get uneasy when I see questions about when an instruction

Re: TRE has no modifier bit

Given a recent enough machine (z9 or later), you could use TROO instead. - mb IBM Mainframe Assembler List ASSEMBLER-LIST@listserv.uga.edu wrote on 11/17/2013 08:23:59 AM: From: Martin Truebner mar...@pi-sysprog.de To: ASSEMBLER-LIST@listserv.uga.edu, Date: 11/17/2013 08:21 AM Subject: TRE

Re: how to: document usage of bit(s) of a register.

Hmm, what about RISBG R0,R13,0,31,32 - since someone brought up these instructions? Assuming it's on the CPU of course. Should impress other programmers no end. I missed the start of the thread so I'm not sure what the original issue was. The original append was only looking for a

Re: how to: document usage of bit(s) of a register.

The convention for control registers in Principles of Operation is CR1.0-51, for bits 0-51 of CR1, so I'd go with R13.32-63, etc. - mb

Re: Generated macro code

Thanks for the explanation, Jonathan. I think the behavior is fine. A documentation update would be sufficient, in my opinion. - mb

Generated macro code

I have a macro that generates other macros as well as DSECTs, equates, etc. If I issue PRINT NOGEN and then invoke the macro in order to define the new macros, the lines that comprise the new macros appear in the listing, even though the DSECT and equate definitions are suppressed. Is this the

Re: Generated macro code

Look to see if PCONTROL(GEN,ON) is in effect.. No, it's not in effect, according to the Options for this Assembly page. Note that the DSECT and equates definitions do not appear, as expected. - mb

Re: TRTE and new instructions

I don't question the value of using macro-driven machinery for generating the code to emulate instructions. However, in OCO code, coping with the unavailability of machine instructions must be done at run time, not at assembly time. Only sort of. Depending on the code, you could have an

Re: Load and Add

I suspect it's a misunderstanding of operand nomenclature. For LAA, LAAG, LAAL, and LAALG, the operands are listed after the mnemonic as R1,R3,D2 (B2), where the digits are rendered as subscripts. The second operand is the operand whose parts have a subscript of 2(i.e., D2(B2)), *not* the

Another you-see-what-you-want-to-see moment

not involve macros or OPSYN.) - mb Mark Boonie

Re: Curosity Question

, or is there another condition that has been implied (or stated explicitly) that I overlooked? Thank you for any information you can give me. - mb Mark Boonie z/TPF Development 845-433-4918 (t/l 293-4918) From: John Gilmore jwgli...@gmail.com To: ASSEMBLER-LIST@listserv.uga.edu, Date: 11/01

Re: Help needed: Machine types for certain z/Architecture PoOP manuals?

When did this doc change happen? It appears it was part of SA22-7832-05, published in April 2007. - mb

Re: Equate for conditions

Yes, there are extended suffixes for COMPARE AND BRANCH and COMPARE AND TRAP. The defined suffixes are -H, -L, -E, -NH, -NL, and -NE. - mb Mark Boonie z/TPF Development Martin Trübner wrote on 12/20/2010 05:57:18 AM: ... Or am I in the wrong book and there are extended mnemonics for CIT

Re: z/OS IARV64

of any real storage; ... They do, however, entail the overhead of segment or page table entries. -- gil Why wouldn't the region-third-table entry simply be marked invalid? (I'm not saying you're wrong -- I have no idea how z/OS does it.) - mb Mark Boonie z/TPF Development

Re: z/OS IARV64

addresses from 2GB to 4GB-1 are invalid. - mb Mark Boonie z/TPF Development