SV: Conditional MVCL macro?

. oktober 2020 15:58 Til: ASSEMBLER-LIST@LISTSERV.UGA.EDU Emne: RES: Conditional MVCL macro? MVC moves up to 256 bytes, not 255 -Mensagem original- De: IBM Mainframe Assembler List Em nome de Robin Vowels Enviada em: quinta-feira, 22 de outubro de 2020 05:03 Para: ASSEMBLER-LIST

RES: Conditional MVCL macro?

MVC moves up to 256 bytes, not 255 -Mensagem original- De: IBM Mainframe Assembler List Em nome de Robin Vowels Enviada em: quinta-feira, 22 de outubro de 2020 05:03 Para: ASSEMBLER-LIST@LISTSERV.UGA.EDU Assunto: Re: Conditional MVCL macro? - Original Message - From: "

Re: Conditional MVCL macro?

On 2020-10-22, at 02:02:56, Robin Vowels wrote: > > You need to test R15 being zero. Subtracting 1 and then doing an EX > is potentially dangerous. > I wonder whether avoiding this hazard was motivation for CMS MDFS and SFS and early MVS RECFM=V prohibiting empty records. -- gil

Re: Conditional MVCL macro?

j mvc 0(*-*,r1),0(r14) short copy lrr1,r15 copy length mvcl r0,r14 long copy ds0h Willy --- Thi

Re: Conditional MVCL macro?

On Tue, 20 Oct 2020 16:58:52 -0400 Steve Smith said:   And for something completely different... sometimes I use MVCK for   a variable-length move instead of EX/MVC or MVCL.  I haven't done   any performance tests, because I haven't used it in   performance-critical code (and it does have

Re: Conditional MVCL macro?

smetz3 From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on behalf of Ed Jaffe [edja...@phoenixsoftware.com] Sent: Wednesday, October 21, 2020 1:46 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Conditional MVCL macro? On 10/21/2020 10:36 AM, Seymour

Re: Conditional MVCL macro?

On 10/21/2020 10:36 AM, Seymour J Metz wrote: Which? Either is subject to an access violation crossing page boundaries. For MVCL, I don't know of any special significance to 256KiB. For MVCOS, assuming no page fault, 256 < 4096, but I don't know of any significance of 256 rather than,

Re: Conditional MVCL macro?

] Sent: Wednesday, October 21, 2020 12:07 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Conditional MVCL macro? On 2020-10-21, at 09:20:31, Seymour J Metz wrote: > > Unless performance is an issue, I generally opt for simplicity. If > performance is an issue I encapsulate it i

Re: Conditional MVCL macro?

Which? Either is subject to an access violation crossing page boundaries. For MVCL, I don't know of any special significance to 256KiB. For MVCOS, assuming no page fault, 256 < 4096, but I don't know of any significance of 256 rather than, e.g., 128, 512; you don't need the loop for any len

Re: Conditional MVCL macro?

On 10/21/2020 8:22 AM, Seymour J Metz wrote: 4K is indeed an architected limit for MVCOS, but for MVCLE it's "CPU-determined number of bytes". But nicely it will always complete the move if it is <=256 bytes. So you don't need the loop for short moves. -- Phoenix Software International

Re: Conditional MVCL macro?

On 2020-10-21, at 09:20:31, Seymour J Metz wrote: > > Unless performance is an issue, I generally opt for simplicity. If > performance is an issue I encapsulate it in a macro that generates different > code for different processors. > It's harder for an EQUated symbolic length; worse yet for

Re: Conditional MVCL macro?

r Wiid [pw...@mweb.co.za] Sent: Wednesday, October 21, 2020 2:22 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Conditional MVCL macro? MVCOS? Also needs to be re-driven after 4K

Re: Conditional MVCL macro?

Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on behalf of Dan Greiner [dan_grei...@att.net] Sent: Tuesday, October 20, 2020 11:42 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Conditional MVCL macro? One of the questions that I always ask in response to concerns about whether one

Re: Conditional MVCL macro?

MVCOS? Also needs to be re-driven after 4K -Original Message- From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On Behalf Of Steve Smith Sent: 20 October 2020 22:59 To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Conditional MVCL macro? There's actually a big

Re: Conditional MVCL macro?

Can you share your $MVC macro? Brian On Tue, 20 Oct 2020 17:42:55 +, Christopher Y. Blaicher wrote: >We just got a z15 and I have not tested MVCL vs MVC loop, but on all prior >machines a MVC loop beat a MVCL up to about 32K. Over 32K MVCL is the way to >go. In our envir

Re: Conditional MVCL macro?

nstruction completes (which may or may not be what you intended) ... so the answer implicitly looks more like (b). To assert control over whether MVCL wipes out the cache, check out the discussion of the special pad characters X'B0' and X'B8' used by the instruction on page 7-291 (RHC) of the "

Re: Conditional MVCL macro?

@LISTSERV.UGA.EDU Subject: Re: Conditional MVCL macro? Unless I am thinking fuzzily, an interrupted MVCL leaves the PSW pointing to the MVCL (not past it) and the relevant registers incremented and decremented appropriately, so the supervisor may dispatch other tasks on the affected CPU, let them run

Re: Conditional MVCL macro?

I'm pretty sure that testing for pending interrupts didn't slow down CLCL or MVCL on the 370/165 or 370/168. But the microinstruction was 108 bits; longer if you had an emulator feature. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 From

Re: Conditional MVCL macro?

So it was written, and it is so done. sas On Tue, Oct 20, 2020 at 6:35 PM Charles Mills wrote: > Unless I am thinking fuzzily, an interrupted MVCL leaves the PSW pointing > to > the MVCL (not past it) and the relevant registers incremented and > decremented appropriately, so the su

Re: Conditional MVCL macro?

Interrupts can only be handled between instructions (don't ask me how pipelining figures) except, MVCL has the potential to delay that too long, so it (and a handful of others) were made to be interruptible. Probably, that just means the micro/milli-code program gets interrupted between micro

Re: Conditional MVCL macro?

Unless I am thinking fuzzily, an interrupted MVCL leaves the PSW pointing to the MVCL (not past it) and the relevant registers incremented and decremented appropriately, so the supervisor may dispatch other tasks on the affected CPU, let them run as they will, and then resume the interrupted task

Re: Conditional MVCL macro?

There's actually a big difference between MVCL being interruptible, and > MVCLE stopping periodically before it's finished. The latter is not > interruptible, it just stops before completion periodically for the program > to do something else if it wants to. ... > I thought it was

Re: Conditional MVCL macro?

On 2020-10-20, at 14:58:52, Steve Smith wrote: > > There's actually a big difference between MVCL being interruptible, and > MVCLE stopping periodically before it's finished. The latter is not > interruptible, it just stops before completion periodically for the program > to do

Re: Conditional MVCL macro?

' BAL R14,TIMEOUT The second case was just a move of 1K using four MVC instructions in a row, which is the fastest. All the others are just $MVC macro vs MVCL instruction. Chris Blaicher Technical Architect

Re: Conditional MVCL macro?

There's actually a big difference between MVCL being interruptible, and MVCLE stopping periodically before it's finished. The latter is not interruptible, it just stops before completion periodically for the program to do something else if it wants to. Checking a flag is a possibility

Re: Conditional MVCL macro?

Thanks for sharing your test results, although I had trouble explaining the results of the first two tests, and maybe this is related to how the $MVC macro does its thing. Anyway, If you throw out the first two tests, the $MVC technique appears to be 250-300% more efficient than the MVCL

Re: Conditional MVCL macro?

long operations." If a similar process happens with MVCL at the 2K boundary, that could be the explanation. I'm not a hardware guy, so just guessing. Chris Blaicher Technical Architect Precisely.com -Original Message- From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSE

Re: Conditional MVCL macro?

I just re-ran a test on our z15 machine and got interesting numbers. The $MVC was reasonably linear from start to finish. The MVCL has a big jump from 2K to 4K, but was also reasonably linear outside of that jump. It never caught up to the $MVC implementation. TEST TYPE = BASE CODE

Re: Conditional MVCL macro?

2020 10:52 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Conditional MVCL macro? MVCL is, and always has been, interruptible.

Re: Conditional MVCL macro?

COBOL version was 6.3 using ARCH(13) OPT(2) -Original Message- From: IBM Mainframe Assembler List On Behalf Of John Melcher Sent: Tuesday, October 20, 2020 12:09 To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Conditional MVCL macro? JES2 has had a $MVCL macro since SP2.2.0. What

Re: Conditional MVCL macro?

:09 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Conditional MVCL macro? JES2 has had a $MVCL macro since SP2.2.0. What version of COBOL, I wonder? The COBOL compiler for a 4000 byte move, from to the same with OPT(2) generates LAY R10,5072(,R9) FROM LA R7,1072(,R9) TO ...

Re: Conditional MVCL macro?

MVCL is, and always has been, interruptible. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on behalf of Charles Mills [charl...@mcn.org] Sent: Tuesday, October 20, 2020 11

Re: Conditional MVCL macro?

We just got a z15 and I have not tested MVCL vs MVC loop, but on all prior machines a MVC loop beat a MVCL up to about 32K. Over 32K MVCL is the way to go. In our environment we rarely are moving more than 32K. We built a $MVC macro with 3 parameters, destination, source and length and use

Re: Conditional MVCL macro?

Our testing on a Z14 (MVS under VM), MVCL was considerably slower than a 256-byte MVC loop plus an executed MVC for various unaligned data lengths from 40 bytes to 32K. For zeroing memory up to 1G, XC in a loop was about the same as MVCL up to 256 bytes, then MVCL was faster (MVCLE was slightly

Re: Conditional MVCL macro?

On 10/20/2020 8:54 AM, Charles Mills wrote: @Ed, can you elaborate a little on your reasoning? (Not doubting it; just curious.) Is it that the interruptibility provides a significant improvement over MVCL? Or the support for lengths greater than 16M? Or ... ? MVCL with anything other than zero

Re: Conditional MVCL macro?

JES2 has had a $MVCL macro since SP2.2.0. What version of COBOL, I wonder? -Original Message- From: IBM Mainframe Assembler List On Behalf Of Charles Mills Sent: Tuesday, October 20, 2020 12:05 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Conditional MVCL macro? *** External

Re: Conditional MVCL macro?

Note that in neither case does it use MVCL or MVCLE! The 4097 boundary may simply be a reasonableness thing, not a performance thing. For a 150K move, 600-or-so MVC's in-line might be faster than a loop, but does it really seem reasonable? Slightly OT to 'move' but I find it interesting

Re: Conditional MVCL macro?

to both be aligned on a page boundary, then the opportunity exists for the async data mover to kick in if a move long is being used. I think this applied to both MVCL and MVCLE, but not sure. So ideally a macro would want to utilize both MVCs and MVCL/E. More grist for the mill! -Original

Re: Conditional MVCL macro?

at 4097 bytes. -Original Message- From: IBM Mainframe Assembler List On Behalf Of Charles Mills Sent: Tuesday, October 20, 2020 10:54 To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Conditional MVCL macro? @Ed, can you elaborate a little on your reasoning? (Not doubting it; just

Re: Conditional MVCL macro?

I don't know how today's machines (z13 and up) perform, but back when I had access to Strobe it regularly pointed out long MVCL / CLCL instructions generated by COBOL 4.2 (in the specific application case I was working on these were usually around 8K bytes) as relatively large "hot

Re: Conditional MVCL macro?

@Ed, can you elaborate a little on your reasoning? (Not doubting it; just curious.) Is it that the interruptibility provides a significant improvement over MVCL? Or the support for lengths greater than 16M? Or ... ? When I asked Dr. Shum about move strategies he seemed to indicate that for data

Re: Conditional MVCL macro?

We've switched almost exclusively to MVCLE except for short, fixed-length moves. On 10/20/2020 5:42 AM, Tony Thigpen wrote: I have several programs that work with buffers and moving random length data around using MVCLs. I am considering writing a 'conditional MVCL' macro that, at runtime

SV: Conditional MVCL macro?

lrr1,r0copy target address exr15, j mvc 0(*-*,r1),0(r14) short copy lrr1,r15 copy length mv

Re: Conditional MVCL macro?

> > What is the effect of the conditional branch and the EX on the pipeline? Are > the performance tradeoffs the same on all supported processors? Also, tuning > code for a current processor may slow it down on a new one. > > > -- > Shmuel (Seymour J.) Metz > http://mason.gmu.edu/~smetz3 In

Re: Conditional MVCL macro?

From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on behalf of Tony Thigpen [t...@vse2pdf.com] Sent: Tuesday, October 20, 2020 8:42 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Conditional MVCL macro? I have several programs that work with buffers

Conditional MVCL macro?

I have several programs that work with buffers and moving random length data around using MVCLs. I am considering writing a 'conditional MVCL' macro that, at runtime, looks at the lengths and either executes the MVCL or bypasses it and uses a MVC via EX. I know this would generate a longer

Re: Source address significance for clearing MVCL

From: "Steve Smith" Sent: Friday, August 18, 2017 2:04 AM HLASM doesn't do "obviously I meant" (aka DWIM). So, you are an HLASM, not a real person. --- This email has been checked for viruses by Avast antivirus software. https://www.avast.com/antivirus

Re: Source address significance for clearing MVCL

Second 4K *page* Charles -Original Message- From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On Behalf Of Wayne Driscoll Sent: Thursday, August 17, 2017 12:59 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Source address significance for clearing MVCL

Re: Source address significance for clearing MVCL

used. -Original Message- From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On Behalf Of Steve Smith Sent: Thursday, August 17, 2017 12:15 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Source address significance for clearing MVCL Your wiki note is incorrect

Re: Source address significance for clearing MVCL

To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Source address significance for clearing MVCL HLASM doesn't do "obviously I meant" (aka DWIM). The source address register is ignored, doesn't have to be cleared, and will not be changed, when the source length is 0. btw, the cool modern

Re: Source address significance for clearing MVCL

On 2017-08-17, at 09:27, Robin Vowels wrote: > From: "Charles Mills" > Sent: Friday, August 18, 2017 1:04 AM > > >> I'd need a whole lot more than two SR R2,0's. > (Sometimes it works.) > Obviously I meant SR R2,R2. > Or, to make it always work, you could: LR

Re: Source address significance for clearing MVCL

Your wiki note is incorrect. MVCL doesn't use the high-word for its length registers. And 'O' instructions do not insert, they OR (duh). OILH is useful when a length has already been loaded, and you know the high byte is zero. OILF is overkill, but some say you can never have too much overkill

Re: Source address significance for clearing MVCL

To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Source address significance for clearing MVCL HLASM doesn't do "obviously I meant" (aka DWIM). The source address register is ignored, doesn't have to be cleared, and will not be changed, when the source length is 0. btw, the cool

Re: Source address significance for clearing MVCL

HLASM doesn't do "obviously I meant" (aka DWIM). The source address register is ignored, doesn't have to be cleared, and will not be changed, when the source length is 0. btw, the cool modern way to set that with one instruction is LLILH Rx,x'4000' (e.g.). Fair warning, this clears the

Re: Source address significance for clearing MVCL

From: "Charles Mills" Sent: Friday, August 18, 2017 1:04 AM I'd need a whole lot more than two SR R2,0's. Obviously I meant SR R2,R2. --- This email has been checked for viruses by Avast antivirus software. https://www.avast.com/antivirus

Re: Source address significance for clearing MVCL

From: "Charles Mills" Sent: Friday, August 18, 2017 12:33 AM Address 0 is a legal fetch address. The question is can I get away with not worrying about what is in the source address register? What, for example, if it points to a non-address or to something that happens to

Re: Source address significance for clearing MVCL

significance for clearing MVCL From: "Charles Mills" <charl...@mcn.org> Sent: Friday, August 18, 2017 12:33 AM > Address 0 is a legal fetch address. > > The question is can I get away with not worrying about what is in the > source address register? What, for example, if i

Re: Source address significance for clearing MVCL

From: "Charles Mills" Sent: Friday, August 18, 2017 12:33 AM Address 0 is a legal fetch address. The question is can I get away with not worrying about what is in the source address register? What, for example, if it points to a non-address or to something that happens to

Re: Source address significance for clearing MVCL

Perfect! Thanks, Charles -Original Message- From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On Behalf Of Jonathan Scott Sent: Thursday, August 17, 2017 10:15 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Source address significance for clearing MVCL

Re: Source address significance for clearing MVCL

On 2017-08-17, at 08:33, Charles Mills wrote: > Address 0 is a legal fetch address. > Is there, for testing, an address that's guaranteed to be fetch-protected? > The question is can I get away with not worrying about what is in the source > address register? What, for example, if it points to

Re: Source address significance for clearing MVCL

Sent: Thursday, August 17, 2017 10:07 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Source address significance for clearing MVCL Yes, I do believe you are correct. Checked a bit of old code for clearing an area and both source addr and length are 0 Regards, Gary Freestone

Re: Source address significance for clearing MVCL

; I don't see this explicitly in the PoOp. Is my recollection correct? That > for a "pure clearing" MVCL (source length zero, destination length non-zero) > the contents of source address register R2 are not significant, and a > specification or access exception on the source a

Re: Source address significance for clearing MVCL

From: "Charles Mills" <charl...@mcn.org> Sent: Thursday, August 17, 2017 11:00 PM I don't see this explicitly in the PoOp. Is my recollection correct? That for a "pure clearing" MVCL (source length zero, destination length non-zero) the contents of

Re: Source address significance for clearing MVCL

August 2017 11:01 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Source address significance for clearing MVCL I don't see this explicitly in the PoOp. Is my recollection correct? That for a "pure clearing" MVCL (source length zero, destination length non-zero) the contents of sour

Source address significance for clearing MVCL

I don't see this explicitly in the PoOp. Is my recollection correct? That for a "pure clearing" MVCL (source length zero, destination length non-zero) the contents of source address register R2 are not significant, and a specification or access exception on the source address is no

Automatic reply: MVCL

I will be on vacation between Jun 16 and Jul 15 (both days included). If you need to open an issue with me, please open it via (11)55036100 or via support.ca.com, and someone will contact you.

Re: MVCL

On Mon, 16 Jun 2014 11:34:50 +1000, Robin Vowels wrote: From: Duffy Nightingale du...@soundsoftware.us Sent: Monday, June 16, 2014 5:27 AM I've always done the ex of mvc thusly: EXR1,TEXT8000 MOVE IN ASCII NUMBERS Down where it will not be executed TEXT8000 DS0H

Re: MVCL

On 2014-06-16, at 10:30, Tom Marchant wrote: You didn't show the MVC, but when you said you prefer it to be close by, perhaps you meant that you would put it immediately before or after the EX. Some like to keep it close without an additional execution by coding: EXR1,TEXT8000

Re: MVCL

[mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On Behalf Of Steve Comstock Sent: Wednesday, May 21, 2014 7:19 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: MVCL On 5/21/2014 8:14 AM, Robin Vowels wrote: From: Steve Hobson steve_hob...@uk.ibm.com Sent: Wednesday, May 21, 2014 9:38 PM For many years I've

Automatic reply: MVCL

I am out of the office and will be returning Monday Jun 23. If you need immediate assistance please contact Robert H Lewis. Otherwise, I will reply to messages when I return. Thank you, Greg Bowers

Re: MVCL

, 2014 7:19 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: MVCL On 5/21/2014 8:14 AM, Robin Vowels wrote: From: Steve Hobson steve_hob...@uk.ibm.com Sent: Wednesday, May 21, 2014 9:38 PM For many years I've used this style which I was taught be the legendary Pete Roberts: MVC

Automatyczna odpowiedź: MVCL

Dzień dobry, do 15 czerwca przebywam poza biurem. Poczta nie jest przekierowywana. W sprawach pilnych proszę o kontakt z Krzysztofem Szubą lub Jakubem Teską. Pozdrawiam, Arkadiusz Wojtczak

Re: Baseless? (Was: MVCL)

I think of - Code (base) register: generally old style, when relative addressing is not available - Static Area (base) register: address of your static data (such as literals) Some modules actually have no such data but most do. z/OS macros may assume that you have addressability to such an

Re: MVCL

Well thank you, Mr G. But better not to be drawn in further. -Ursprüngliche Nachricht- Von: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] Im Auftrag von John Gilmore Gesendet: Montag, 26. Mai 2014 21:50 An: ASSEMBLER-LIST@LISTSERV.UGA.EDU Betreff: Re: MVCL David

Baseless? (Was: MVCL)

On 5/26/2014 6:57 PM, Scott Ford wrote: No such animal as a code base register unless this is some slang …There are BASE and BASELESS HLASM code. In this context, baseless must be some sort of slang. There are based branches and there are relative branches. Use of relative branches in a

Re: MVCL

that, for most of its life was neither contentious nor : really ambiguous. : :My apologies. I was not intending to obfuscate but rather to clarify. It :seems I was not successful. : :I posted a couple of code fragments in the context of EX+MVC vs MVCL. Two :people pointed out that MVC (and EX

Re: MVCL

' storage using a DSECT as a template. In any case a register is [usually] required, and David is free to call it a base register if he wishes. Steve Hobson's second-time-around distinction: begin extract Both MVC and MVCL use registers to locate their operands. I am aware that S-type operands

Re: MVCL

register, if it is a code base when addressing constants. Is the base needed by EX a cbr, because its target is an instruction? Or is that just a, hmm, non-cbr (non?)br? Fragen über Fragen. Of course, MVCL does not use a base, of whatever sort. Um, how do you get addresses into the relevant

Re: MVCL

On 2014-05-26, at 07:59, Robin Vowels wrote: Um, how do you get addresses into the relevant registers required by MVCL? ADCONs? -- gil

Re: MVCL

LOAD, LOAD ADDRESS, LOAD ADDRESS RELATIVE LONG come to mind off hand. On May 26, 2014 9:09 AM, Paul Gilmartin paulgboul...@aim.com wrote: On 2014-05-26, at 07:59, Robin Vowels wrote: Um, how do you get addresses into the relevant registers required by MVCL? ADCONs? -- gil

Re: MVCL

I suspect that Robin's question was rhetorical/tongue-in-cheek, not a request for information. He is a very old hand at this game. John Gilmore, Ashland, MA 01721 - USA

Re: MVCL

List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] Im Auftrag von John Gilmore Gesendet: Montag, 26. Mai 2014 14:16 An: ASSEMBLER-LIST@LISTSERV.UGA.EDU Betreff: Re: MVCL It is now clear that we are dealing here with neither confusion nor disagreement alone but with an unholy admixture of both. It cannot

AW: MVCL

2014 15:59 An: ASSEMBLER-LIST@LISTSERV.UGA.EDU Betreff: Re: MVCL From: David Stokes sto...@interchip.de Sent: Monday, May 26, 2014 5:47 PM Binyamin Dissen wrote: When it requires a base register is stated, it obviously means a CODE base register. One wonders how that can be confused. Why? (It's

Re: MVCL

David Stokes saw calumny---a lie spoken or written to damage someone else's reputation---where none was intended. I suspect that he did not know quite what this word means. Now he does. John Gilmore, Ashland, MA 01721 - USA

Re: MVCL

On 5/26/14, John Gilmore jwgli...@gmail.com wrote: David Stokes saw calumny---a lie spoken or written to damage someone else's reputation---where none was intended. I suspect that he did not know quite what this word means. Now he does. John Gilmore, Ashland, MA 01721 - USA -- John

Re: MVCL

From: Binyamin Dissen bdis...@dissensoftware.com Sent: Monday, May 26, 2014 3:51 PM When it requires a base register is stated, it obviously means a CODE base register. No it doesn't. A base register is a base register. --- This email is free from viruses and malware because avast!

Re: MVCL

of time removing code base registers from existing code. If you mean that the registers in the base+displacement SS MVC operands are called base registers then yes, the MVC uses base registers. However they are not extra registers required over and above what MVCL needs. For this type of move

Re: MVCL

that the registers in the base+displacement SS MVC operands are called base registers then yes, the MVC uses base registers. However they are not extra registers required over and above what MVCL needs. For this type of move, MVCL uses a register to contain the address of the target and a register

Re: MVCL

I am not sure what purpose is served by obfuscating an ancient piece of terminology that, for most of its life was neither contentious nor really ambiguous. Terms do, of course, acquire new meanings that cannot be ignored, and in the future I shall call what I have called a base register since

Re: MVCL

fragments in the context of EX+MVC vs MVCL. Two people pointed out that MVC (and EX for that matter) require a base register. My ish response was not intended to say you are mistaken, it was intended to say that is not really relevant to a discussion of the relative merits of EX+MVC and MVCL. Both MVC

Re: MVCL

From: Steve Hobson steve_hob...@uk.ibm.com Sent: Wednesday, May 21, 2014 11:31 PM : MVC TARGET(0),SOURCE : EX Rx,*-6 : Requires a code base register. Well, ish: LARL Ry,*+6 MVC TARGET(0),SOURCE EX Rx,0(,Ry) This (MVC)

Automatic reply: MVCL

I am away on vacation. I will be returning Monday June 2, 2014. If this is an emergency please call Susan Kincaid at (713) 745-9311. Or you can page me at (713) 404-9779.

Re: MVCL

From: Binyamin Dissen bdis...@dissensoftware.com Sent: Wednesday, May 21, 2014 10:03 PM On Wed, 21 May 2014 12:38:09 +0100 Steve Hobson steve_hob...@uk.ibm.com wrote: : I tend to use MVCL like Tony does. The reason that I tend to not like :doing : a EX of an MVC is because the MVC needs

Re: MVCL

@LISTSERV.UGA.EDU] Im Auftrag von Robin Vowels Gesendet: Samstag, 24. Mai 2014 13:35 An: ASSEMBLER-LIST@LISTSERV.UGA.EDU Betreff: Re: MVCL From: Binyamin Dissen bdis...@dissensoftware.com Sent: Wednesday, May 21, 2014 10:03 PM On Wed, 21 May 2014 12:38:09 +0100 Steve Hobson steve_hob

Re: MVCL

(not a loop, saving then loading 14 registers with zeros, storing several times) MVCL MVC (from zeros) ... (I think there was one or two more which I forget) overlapping MVC XC Yes, the new machine recognized that the XC arguments were the same and just stored zeros apparently without fetching anything

Re: MVCL

On 21 May 2014 07:34, Robin Vowels robi...@dodo.com.au wrote: From: Ed Jaffe edja...@phoenixsoftware.com Sent: Wednesday, May 21, 2014 2:52 PM On 5/20/2014 8:44 PM, Robin Vowels wrote: I use MVCL a lot even for very small moves where the length is not known at assembly time. But I

Re: MVCL

On 5/20/2014 11:44 PM, Robin Vowels wrote: Sounds like overkill. MVC with EX would be simpler. It depends very much on the requirement. For example, building a longer string from several different sources; MVCL sets the destination address and residual length after completion, allowing

Re: MVCL

; MVCL sets the destination address and residual length after completion, allowing for simple chaining of multiple moves. While EX/MVC can accomplish the same thing, they require a little more arithmetic. Only a BCTR. It all can be handled trivially by a macro. However, for multiple moves

Re: MVCL (was: Right Justification Subroutine)

I tend to use MVCL like Tony does. The reason that I tend to not like doing a EX of an MVC is because the MVC needs to be out-of-line. (and is the MVC in the i-cache or the d-cache?) Also, this requires a base register to address the area containing the MVC. Which is generally not a problem

Re: MVCL (was: Right Justification Subroutine)

I tend to use MVCL like Tony does. The reason that I tend to not like doing a EX of an MVC is because the MVC needs to be out-of-line. (and is the MVC in the i-cache or the d-cache?) Also, this requires a base register to address the area containing the MVC. Which is generally not a problem

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