All,
for literals where the assembler refuses to do the calculus for you,
you can use a SETA statement to determine the value,
then use the SETA symbol to promote the calculated value into the DC value.
The upper limit of 2G of results, including any intermediate values,
still applies.
To get
If you have more than an academic interest, there's always RFE, also not
new. In my limited world, the need for writing constants > 2G has not
really come up much.
The famous =FDS12E6'1' is about it, and already works (one second in TOD
format; multiples, up to a few hours at least, also work).
> On May 19, 2022, at 14:39:49, Steve Smith wrote:
>
> AD
>
> This isn't new.
>
DCAD(100*100)
???
> On Thu, May 19, 2022 at 3:49 PM Paul Gilmartin wrote:
>> On May 19, 2022, at 12:16:45, Ngan, Robert (DXC Luxoft) wrote:
>>>
>>> FD is a fixed point doubleword.
>>>
>>
AD
This isn't new.
sas
On Thu, May 19, 2022 at 3:49 PM Paul Gilmartin <
0014e0e4a59b-dmarc-requ...@listserv.uga.edu> wrote:
> On May 19, 2022, at 12:16:45, Ngan, Robert (DXC Luxoft) wrote:
> >
> > FD is a fixed point doubleword.
> >
> Alas, there's no way to define a doubleword constant
Of Paul Gilmartin
Sent: Thursday, May 19, 2022 14:49
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Quadword constant
On May 19, 2022, at 12:16:45, Ngan, Robert (DXC Luxoft) wrote:
>
> FD is a fixed point doubleword.
>
Alas, there's no way to define a doubleword constant containing
On May 19, 2022, at 12:16:45, Ngan, Robert (DXC Luxoft) wrote:
>
> FD is a fixed point doubleword.
>
Alas, there's no way to define a doubleword constant containing the
value of an arithmetic expression AL8(2+2)?
Having only a 32-bit assembler for a 64-bit architecture is
increasingly becoming
FD is a fixed point doubleword.
Robert Ngan
DXC Luxoft
-Original Message-
From: IBM Mainframe Assembler List On Behalf
Of Schmitt, Michael
Sent: Thursday, May 19, 2022 13:09
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Quadword constant
Today I learned that there isn't a fixed
@LISTSERV.UGA.EDU
Subject: Quadword constant
HLASM has fixed decimal constants for Halfwords, Fullwords, Doublewords, with
appropriate alignment. Why is there none for Quadwords?
The closest I see is LQ, but that appears to be intended for floating point.
Since APAR PH40885 you can simply suppress warning ASMA500W if
you don't want to be nagged about item alignment exceeding
SECTALGN, as the alignment warning no longer prevents the
expected code from being generated.
The section alignment for purposes of code generation is now
always assumed to be
- begin snippet (from Steve Smith)
That's the old-fashioned way. This is the new way:
ORG *,16
- end snippet
The assembler still cares about SECTALGN. The "old fashioned way"
works fine, independent of SECTALGN. Also, note that I explicitly
stated mapping quad word
On Wed, 20 Apr 2022 at 13:03, Charles Mills wrote:
> > USING *,16
> I was wondering about R16. Would come in handy.
Maybe on the z16...?
[There was an old PL/I Optimizer APAR (1980ish?) complaining that a
new compiler release could not generate code for certain large source
modules that had
I was wondering about R16. Would come in handy.
Charles
-Original Message-
From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On
Behalf Of Steve Smith
Sent: Wednesday, April 20, 2022 9:31 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Quadword constant
Sheesh. Sorry, I meant ORG *,16.
On Wed, Apr 20, 2022 at 12:30 PM Steve Smith wrote:
> That's the old-fashioned way. This is the new way:
>
> USING *,16
>
> There are some caveats. For CSECTs, HLASM will complain if SECALGN is
> insufficient. For DSECTs, it's your responsibility to ensure
That's the old-fashioned way. This is the new way:
USING *,16
There are some caveats. For CSECTs, HLASM will complain if SECALGN is
insufficient. For DSECTs, it's your responsibility to ensure the alignment
matches (if it's real important). Fortunately, STORAGE has a corresponding
alignment
Ed;
Of course, what you said about the LQ type of DC is true, and I too
have used LQ data types in some of my code too. However, the
SECTALGN requirement is a bit of an issue when assembling code with
2**3 (double word) section alignment and which also contains DSECTs
which map quad word
[edja...@phoenixsoftware.com]
Sent: Tuesday, April 19, 2022 10:22 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Quadword constant
On 4/19/2022 7:13 PM, Bob Raicer wrote:
>
> Having the ability to assemble quadword aligned 128-bit items for
> use with these instructions would be hel
On 4/19/2022 7:13 PM, Bob Raicer wrote:
Having the ability to assemble quadword aligned 128-bit items for
use with these instructions would be helpful.
We define quadword-aligned storage areas all the time. For example:
Field1 DC LQ'0'
Field2 DC LQ'0'
Of course, you need to specify the
A couple of more general instructions which require quadword aligned
storage operands and 128-bit values in even-odd pairs of 64-bit
GPRs:
Compare Double and Swap (CDSG)
Compare and Swap and Store (CSST)
Having the ability to assemble quadword aligned 128-bit items for
use with these
List on behalf
of Paul Gilmartin <0014e0e4a59b-dmarc-requ...@listserv.uga.edu>
Sent: Monday, April 18, 2022 8:48 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Quadword constant
On Apr 18, 2022, at 16:48:23, Seymour J Metz wrote:
>
> VA foo,bar,baz,4
>
Please show how to
On Apr 18, 2022, at 16:48:23, Seymour J Metz wrote:
>
> VA foo,bar,baz,4
>
Please show how to define foo, bar, and baz with HLASM to specify
A dividend of fixed point 1E15.
Did you use a calculator?
>
> From: Steve Smith
> Sent: Monday, April 18, 2022
-dmarc-requ...@listserv.uga.edu]
Sent: Monday, April 18, 2022 11:40 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Quadword constant
On Apr 18, 2022, at 09:02:41, Schmitt, Michael wrote:
>
> HLASM has fixed decimal constants for Halfwords, Fullwords, Doublewords, with
> appropriate
@LISTSERV.UGA.EDU
Subject: Re: Quadword constant
HLASM has fixed BINARY constant type specifiers for H, F, FD. The
architecture has no support that I know of for 16-byte fixed binary, so why
should the assembler?
sas
On Mon, Apr 18, 2022 at 11:06 AM Schmitt, Michael
wrote:
> HLASM has fixed deci
@LISTSERV.UGA.EDU
Subject: Re: Quadword constant
On Apr 18, 2022, at 09:02:41, Schmitt, Michael wrote:
HLASM has fixed decimal constants for Halfwords, Fullwords,
Doublewords,
with appropriate alignment. Why is there none for Quadwords?
The closest I see is LQ, but that appears to be intended
On Apr 18, 2022, at 10:03:05, Don Higgins wrote:
>
>> What instructions take fixed quadword operas? I imagine some variant of
>> Divide.
>
> Yes, DLG and DLGR operate on 128 bit dividend in 64 bit r1 and r1+1. But
> since the dividend is in registers, there is no requirement for quad word
>
:03 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Quadword constant
>What instructions take fixed quadword operas? I imagine some variant of
Divide.
Yes, DLG and DLGR operate on 128 bit dividend in 64 bit r1 and r1+1. But
since the dividend is in registers, there is no requirement for q
net
-Original Message-
From: IBM Mainframe Assembler List On
Behalf Of Paul Gilmartin
Sent: Monday, April 18, 2022 11:40 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Quadword constant
On Apr 18, 2022, at 09:02:41, Schmitt, Michael wrote:
>
> HLASM has fixed decimal constants for
HLASM has fixed BINARY constant type specifiers for H, F, FD. The
architecture has no support that I know of for 16-byte fixed binary, so why
should the assembler?
sas
On Mon, Apr 18, 2022 at 11:06 AM Schmitt, Michael
wrote:
> HLASM has fixed decimal constants for Halfwords, Fullwords,
On Apr 18, 2022, at 09:02:41, Schmitt, Michael wrote:
>
> HLASM has fixed decimal constants for Halfwords, Fullwords, Doublewords, with
> appropriate alignment. Why is there none for Quadwords?
>
> The closest I see is LQ, but that appears to be intended for floating point.
>
What
HLASM has fixed decimal constants for Halfwords, Fullwords, Doublewords, with
appropriate alignment. Why is there none for Quadwords?
The closest I see is LQ, but that appears to be intended for floating point.
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