[casper] katADC

Hello, Does anyone have any spare katADCs they might be prepared to donate, or sell for some notional fee? We're in need of at least one, after our spare was found to be damaged, but a handful would be good. Thanks Michael -- You received this message because you are subscribed to the Google

Re: [casper] katadc

Hello Heystek, It's conventional to use the sync0..3 outputs of the KatADC (through an OR gate) into the Sync input of your PFB. This should be a PPS signal. Do you have a PPS signal and clock reference going into your katadc? What speed (i.e. FPGA clock frequency) are you running at? Try doing

Re: [casper] katadc

Hi James Physically I have connected the signal generator to the katadc's "i" input connector with a square wave at 50MHz with amplitude of 2Vpp. The simulink model is connected as follows: [image: Inline image 2] If I program the ROACH and pull a spectrum of It I get nothing (only a straight

Re: [casper] katadc

Hello Heystek, If you're not getting a spectrum, what are you getting? How have you connected your katadc? (Both physically and with the yellow block)? Regards, James On Wed, May 17, 2017 at 9:46 AM, Heystek Grobler wrote: > Good day everyone > > I am trying to

[casper] katadc

Good day everyone I am trying to implement tutorial 3 on a ROACH1 with a katadc. I have previously done it on a ROACH2 with the iadc. For some reason I am struggling to get the katadc to work. I am using the katadc yellow block but I cant generate a spectrum. I hooked up an signal generator to

Re: [casper] katadc help in simulink

Hello Heystek, It's probably better practice to use software registers (or you could just use one register for all four inputs and slice it out), but you should also have been able to use Xilinx constants, that should have compiled. Regards, James On Mon, May 8, 2017 at 3:33 PM, Heystek

Re: [casper] katadc help in simulink

Hi James Thanks for the help!! I had to add software registers to en0 and en1 as well but know it compiles. Thanks for the help!! I really apreciate it Heystek On Mon, May 8, 2017 at 2:23 PM, James Smith wrote: > Hello Heystek, > > The KatADC is described here: >

Re: [casper] katadc help in simulink

Hello Heystek, The KatADC is described here: https://casper.berkeley.edu/wiki/KatADC It's got two channels which you need to enable if you want to use them, and 31.5 dB variable attenuators which you need to set. So if you want them to be on all the time, just hard-wire some 1s into en0 and

[casper] katadc help in simulink

Good day everyone I have a ROACH1 board with a katadc. I have located the katadc under the CAPER XPS Blockset (I am trying to do tut3). I have swapped the iadc for the katadc. The problem is, the katadc has the following inputs: en0 atten0 en1 atten1 I need to connect something to those inputs

Re: [casper] KatADC impedance values

hi james, as far as I know, all the casper adc board inputs are 50 ohms, except for the differential input version of the adc16 board, which has 100 ohm differential inputs. several of the adc boards are not well terminated (they aren't 50 ohms at all frequencies...), especially the earlier

[casper] KatADC impedance values

Hi all, Is there any reason to believe that the input on the KatADC board (or any ADC board which we might end up using) is not a 50-ohm? How would one go about determining that? The wiki says nothing about its VSWR or related information. Any thoughts would be appreciated. Regards, James

Re: [casper] KatADC vs ASIAA ADC

Hi Dan Thanks for your input. For 800 MHz BW, I am looking for 2048 spectral channels. If that is a tall order, we could settle for 1024. I am hoping to double the number of channels for halving the BW. For eg. BW NumChannels 8002048 4004096 2008192 I see why you are suggesting

Re: [casper] KatADC vs ASIAA ADC

John We do have switchable analog filters that define the 200, 400 and 800 MHz bandpasses in our IF processors. So decimation in sample domain should still work. Yes, that's true. In our case we want to avoid the complexity of switching in various bandpass filters for the narrowband case.

Re: [casper] KatADC vs ASIAA ADC

Hi John If you can sample 800 MHz bandwidth, then can't you use a digitial bandpass filter to get to the lower bandwidths? Gerry On 3/21/2014 11:43 AM, John Ford wrote: John We do have switchable analog filters that define the 200, 400 and 800 MHz bandpasses in our IF processors. So

Re: [casper] KatADC vs ASIAA ADC

hi gopal, how many spectral channels do you need? for 800 MHz bandwidth, you can use a pair of asiaa dual adc's at 2Gsps, and get four signal inputs per roach2, and clock the fgpa at 250 MHz. . for 400 MHz bandwidth, i suggest you use a pair of adc16 boards in quad input mode (sample at 960

[casper] KatADC est_brd_clk

Hi All, We are bringing multiple ROACH2 boards online, each equipped with two KatADC boards. To my surprise, 3 of our 8 ROACH2s show a 401 MHz FPGA clock rate, as returned from the Python KATCP est_brd_clk() function, when supplying an 800 MHz clock to the ADCs. The others show the correct

Re: [casper] KATADC attenuators

Hi Tom, Not sure if you have resolved this, but there is no jumper setting to override the attenuation on the KatADC. There are jumpers (J2, 3) that force the input switches (U30, 31) on for test purposes. -F On Thu, Dec 20, 2012 at 10:57 PM, Tom Kuiper kui...@jpl.nasa.gov wrote: I have two

Re: [casper] KATADC gain control

On 12/28/2012 08:24 PM, Ryan Monroe wrote: Hey Tom, remember that the gain setting on the katadc block was not enabled on that design. You'll probably need that to control adc gain I'd forgotten that you told me that, Ryan, but now that you remind me I also recall thinking that since the

Re: [casper] KATADC gain control

On 12/29/2012 09:19 AM, Tom Kuiper wrote: I guess, pending a resolution of this issue, I can try a work-around in which I first load KAT_rfi_sys and then replace it with kurtspec. Not elegant but ... Yup! That works. Thanks for the explanation, Jason. Tom

[casper] KATADC gain control

I have two designs I'm playing with. I find that if I run the KAT_rfi_sys 16K spectrometer, then after that I can control the RF attenuators with corr.katadc.rf_fe_set(). However, if I load another design developed here (kurtspec) into a cold ROACH (i.e. after power cycling)

Re: [casper] KATADC gain control

If you take a look at the KATADC yellow block, you'll see there's an input port for configuring it from the simulink gateware. In this spectrometer design, that port is tied to a software register called adc_ctrl0. It has 6 bits (lsbs) to set the attenuator in half-db steps and the msb toggles

[casper] KATADC self-calibration

Can someone point me to the documentation about the KATADCs self-calibration function? Is there a discussion somewhere about the optimum r.m.s. voltage for the sampler input? Thanks, Tom

[casper] KATADC attenuators

I have two KATADCs, one each in ZDOC0 of two ROACH-1 boards (named roach1 and roach2). It appears that the attenuator for input 0 of the KATADC in roach2 is at 0 dB for whatever attenuation setting command is sent to it. The other three inputs respond as I expect. I assume that this is some

Re: [casper] KATADC attenuators (Tom Kuiper)

Tom, I suggest that you swap the KATADC boards between roach1 and roach2. Does the problem stay with roach2 or does it move with the KATADC board? Are you running exactly the same .bof file on both ROACHes? --Larry -- === Larry R.

Re: [casper] KATADC attenuators (Tom Kuiper)

On 12/20/2012 01:33 PM, Larry D'Addario wrote: I suggest that you swap the KATADC boards between roach1 and roach2. Does the problem stay with roach2 or does it move with the KATADC board? I'm pretty sure that I know how that would turn out. Unfortunately, I'm at home in West LA, 30 min with

Re: [casper] KatADC counts to volts

something seems strange. isn't the input range of the ADC IC : Vin FSR pin14 low .590 to .730 Vpp Vin FSR pin15 high .800 to .940 Vpp page 11 of 46 of http://www.ti.com/lit/gpn/adc08d1520 I see +/-50 mV but thats for the common mode input. On Thu, 9 Aug 2012, Tom Kuiper wrote: The KatADC is

Re: [casper] KatADC documentation and questions

Thanks Andrew and Francois! This is a very useful information. Nimish On Mon, Mar 19, 2012 at 2:36 AM, Francois Kapp francois.k...@ska.ac.zawrote: I just looked through the attenuator data sheet - there are no settling time specifications, but I'm sure whatever it is, it will be dominated by

Re: [casper] KatADC documentation and questions

Hi Andrew, Thanks for this information. To be more specific, we would like to change the attenuation in the KatADC RF front end every 20 ms and we can allow up to 1 ms of dead time/settling time. Do you think this can work? A related question is how to change this attenuation. I tried using a

[casper] KatADC documentation and questions

Hi all, Is there any documentation/memo on how to use the KatADC yellow block. In particular, I need to know how to use the variable attenuation feature (inputs atten*, en*). The documentation here — https://casper.berkeley.edu/wiki/KatADC — mentions about a 20dB Gain Block (50.0MHz - 850.0MHz),

Re: [casper] KatADC documentation and questions

Hi Andrew, Thanks for the detailed information. Assuming we have a software register connected to the KatADC atten0 input, how often/fast can we change the attenuation? Thanks, Nimish On Thu, Mar 8, 2012 at 1:03 PM, Andrew Martens and...@ska.ac.za wrote: Hi Nimish The katADC is a bit

Re: [casper] KatADC documentation and questions

Hi Nimish Assuming we have a software register connected to the KatADC atten0 input, how often/fast can we change the attenuation? The change in value triggers an IIC operation using a controller in the katADC yellow block. The rate at which you can change the attenuatation/enable is thus

Re: [casper] KatADC

Thanks Etienne. On Wed, 29 Feb 2012, Etienne Bauermeister wrote: Hi Matt, The 2/4 Gsps version of the KatADC is based on an engineering sample they gave us of a future 2/4 Gsps ADC that is based on the current 1.5/3 Gsps ADC - I think it is just an up-sampled version of the latter. The

Re: [casper] KatADC

Hi Matt (and maybe Tom who started this thread last June), Further to Kim's note, we are also using the ASIAA e2v based board on ROACH 2, and we have already demonstrated 8 bit 5 GS/s quad interleaved operation on ROACH 2. It has two IF inputs, and can run in a dual channel 2.5 GS/s mode. The

Re: [casper] KatADC

Thanks Kim. On Tue, 28 Feb 2012, Kim Guzzino wrote: Matt, ASIAA and I have the 8bit 5Gsps E2v board made by ASIAA running at 4Gsps into a ZDOK on a ROACH1. Our ROACH1 has the SX95 chip and uses the ddr iserdes inputs. the chip is spec'd to run the io's up at 1Gsps and seems to work fine at

Re: [casper] KatADC

Thanks Francois. bummer. Avnet says no stock; need to quote, 60 unit min order. I haven't tried to contact Avnet for a quote. Matt On Wed, 29 Feb 2012, Francois Kapp wrote: Hi Matt, As far as we know the part has not been released commercially.  I suspect if it has not happened by now, it is

Re: [casper] KatADC

Hi Matt, The 2/4 Gsps version of the KatADC is based on an engineering sample they gave us of a future 2/4 Gsps ADC that is based on the current 1.5/3 Gsps ADC - I think it is just an up-sampled version of the latter. The indication from them was that this will be a future product that would

[casper] KatADC question

Dear CASPERites, I have used interleaved ADC1-3000-8 boards with great success, but have a future application which does not require the input bandwidth of this ADC, and which would also benefit from reduced cost. My future bandwidth requirement is 2 GHz, and the KatADC appears to be a

Re: [casper] KatADC

I'd like to know more about this ADC on the hardware wiki page under KatADC: Dual 8-bit 2.0GSPS (or Single 8-bit 4.0GSPS), National Semiconductor ADC08D1520/S7002396 ADC, RF Front-End However, the KatADC page doesn't seem to have any information about it. Can someone direct me to or send

Re: [casper] KatADC

On 06/01/2011 11:19 AM, John Ford wrote: I'd like to know more about this ADC on the hardware wiki page under KatADC: Dual 8-bit 2.0GSPS (or Single 8-bit 4.0GSPS), National Semiconductor ADC08D1520/S7002396 ADC, RF Front-End However, the KatADC page doesn't seem to have any information about

Re: [casper] KatADC

Hi Tom, The 4GSPS version of KatADC is based on an up-tested version of the ADC08D1520, which is designated S7002396. It is unclear whether this will be released as a commercial product by National - a few inquiries to them couldn't hurt the cause. So far we have only received the one. The

Re: [casper] KatADC

hi tom, regarding pushing the KatADC from 2*1.5 Gsps to 4 Gsps: it will be difficult, perhaps impossible, to move 4 Gsps 8 bit ADC data through a single zdoc connector into roach I. each of the 32 bit lvds lanes would have to operate at 1 Gbit/sec, and we've never tried that on Roach I.

Re: [casper] katADC, ISE/SysGen10.1 compatible?

Hi LuisDavid George (as the author of the "yellow block" and underlying controller) is probably the correct person to respond to this question but if you areplanning on switching to the Xilinx 11.x suite, then I would encourage you to do so. We are using 11.5 at KAT and have no problems using the

Re: [casper] katADC, ISE/SysGen10.1 compatible?

Hi Luis. I created new netlists and verilog files of {fab,cpu}_op_fifo and rx_fifo, using FIFO Generator v4.3 and selecting the options according to the original XCO files. As you have worked out, the FIFO netlists were generated using ISE 11 tools, making them incompatible with 10.1.

Re: [casper] katADC, ISE/SysGen10.1 compatible?

Hey Jason (and CASPER) FWIW, it looks like ROACH2 will start using 12.x tools so it might be a good idea not to fall too far behind the development versions. ROACH-2 will start out using the 11 toolflow. A whole lot of work is required to get things moved over to the 12 and 13 tools. We will

[casper] katADC, ISE/SysGen10.1 compatible?

Dear katADC users, I am trying to synthesize a simple design using the katadc block (see screen capture in the attachments). This is my tool set in a Windows XP machine: ISE 10.1, SysGen v.10.1.1134, MATLAB R2007b, v7.5.0.342, latest CASPER libs (today's git clone

Re: [casper] katADC, ISE/SysGen10.1 compatible?

UPDATE: I created new netlists and verilog files of {fab,cpu}_op_fifo and rx_fifo, using FIFO Generator v4.3 and selecting the options according to the original XCO files. The only thing that I did not copy exactly is the reset_type option of the rx_fifo in v5.3: