[PATCH] D158763: [flang][driver] Mark -L as visible in Flang

[Bryan Chan via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG1561495cd128: [flang][driver] Mark -L as visible in Flang 
(authored by erjin, committed by bryanpkc).

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Files:
  clang/include/clang/Driver/Options.td
  flang/test/Driver/driver-help-hidden.f90
  flang/test/Driver/driver-help.f90
  flang/test/Driver/misc-flags.f90


Index: flang/test/Driver/misc-flags.f90
===
--- flang/test/Driver/misc-flags.f90
+++ flang/test/Driver/misc-flags.f90
@@ -7,6 +7,9 @@
 ! Make sure that `-fuse-ld' is "visible" to Flang's driver
 ! RUN: %flang -fuse-ld= -### %s
 
+! Make sure that `-L' is "visible" to Flang's driver
+! RUN: %flang -L/ -### %s
+
 program hello
   write(*,*), "Hello world!"
 end program hello
Index: flang/test/Driver/driver-help.f90
===
--- flang/test/Driver/driver-help.f90
+++ flang/test/Driver/driver-help.f90
@@ -90,6 +90,7 @@
 ! HELP-NEXT: --help-hidden   Display help for hidden options
 ! HELP-NEXT: -help   Display available options
 ! HELP-NEXT: -I Add directory to the end of the list of 
include search paths
+! HELP-NEXT: -L Add directory to library search path
 ! HELP-NEXT: -march=  For a list of available architectures for 
the target use '-mcpu=help'
 ! HELP-NEXT: -mcpu=   For a list of available CPUs for the 
target use '-mcpu=help'
 ! HELP-NEXT: -mllvm=Alias for -mllvm
Index: flang/test/Driver/driver-help-hidden.f90
===
--- flang/test/Driver/driver-help-hidden.f90
+++ flang/test/Driver/driver-help-hidden.f90
@@ -102,6 +102,7 @@
 ! CHECK-NEXT: --help-hidden   Display help for hidden options
 ! CHECK-NEXT: -help   Display available options
 ! CHECK-NEXT: -I Add directory to the end of the list of 
include search paths
+! CHECK-NEXT: -L Add directory to library search path
 ! CHECK-NEXT: -march=  For a list of available architectures 
for the target use '-mcpu=help'
 ! CHECK-NEXT: -mcpu=   For a list of available CPUs for the 
target use '-mcpu=help'
 ! CHECK-NEXT: -mllvm=Alias for -mllvm
Index: clang/include/clang/Driver/Options.td
===
--- clang/include/clang/Driver/Options.td
+++ clang/include/clang/Driver/Options.td
@@ -818,6 +818,7 @@
 paths, for example if also specified with -isystem, the -I option
 will be ignored}]>;
 def L : JoinedOrSeparate<["-"], "L">, Flags<[RenderJoined]>, Group,
+Visibility<[ClangOption, FlangOption]>,
 MetaVarName<"">, HelpText<"Add directory to library search path">;
 def MD : Flag<["-"], "MD">, Group,
 HelpText<"Write a depfile containing user and system headers">;


Index: flang/test/Driver/misc-flags.f90
===
--- flang/test/Driver/misc-flags.f90
+++ flang/test/Driver/misc-flags.f90
@@ -7,6 +7,9 @@
 ! Make sure that `-fuse-ld' is "visible" to Flang's driver
 ! RUN: %flang -fuse-ld= -### %s
 
+! Make sure that `-L' is "visible" to Flang's driver
+! RUN: %flang -L/ -### %s
+
 program hello
   write(*,*), "Hello world!"
 end program hello
Index: flang/test/Driver/driver-help.f90
===
--- flang/test/Driver/driver-help.f90
+++ flang/test/Driver/driver-help.f90
@@ -90,6 +90,7 @@
 ! HELP-NEXT: --help-hidden   Display help for hidden options
 ! HELP-NEXT: -help   Display available options
 ! HELP-NEXT: -I Add directory to the end of the list of include search paths
+! HELP-NEXT: -L Add directory to library search path
 ! HELP-NEXT: -march=  For a list of available architectures for the target use '-mcpu=help'
 ! HELP-NEXT: -mcpu=   For a list of available CPUs for the target use '-mcpu=help'
 ! HELP-NEXT: -mllvm=Alias for -mllvm
Index: flang/test/Driver/driver-help-hidden.f90
===
--- flang/test/Driver/driver-help-hidden.f90
+++ flang/test/Driver/driver-help-hidden.f90
@@ -102,6 +102,7 @@
 ! CHECK-NEXT: --help-hidden   Display help for hidden options
 ! CHECK-NEXT: -help   Display available options
 ! CHECK-NEXT: -I Add directory to the end of the list of include search paths
+! CHECK-NEXT: -L Add directory to library search path
 ! CHECK-NEXT: -march=  For a list of available architectures for the target use '-mcpu=help'
 ! CHECK-NEXT: -mcpu=   For a list of available CPUs for the target use '-mcpu=help'
 ! CHECK-NEXT: -mllvm=

[PATCH] D158763: [flang][driver] Mark -L as visible in Flang

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc added inline comments.



Comment at: clang/include/clang/Driver/Options.td:821
 def L : JoinedOrSeparate<["-"], "L">, Flags<[RenderJoined]>, Group,
+Visibility<[ClangOption, FlangOption]>,
 MetaVarName<"">, HelpText<"Add directory to library search path">;

erjin wrote:
> bryanpkc wrote:
> > Question: How does Clang not give an error for `-L` if this wasn't visible 
> > to Clang?
> If there is no Visibility specified, the default Visibility is the 
> ClangOption. If we want to add an extra option, the visibility needs both.
Thanks for the explanation!


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[PATCH] D158763: [flang][driver] Mark -L as visible in Flang

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc added inline comments.



Comment at: clang/include/clang/Driver/Options.td:821
 def L : JoinedOrSeparate<["-"], "L">, Flags<[RenderJoined]>, Group,
+Visibility<[ClangOption, FlangOption]>,
 MetaVarName<"">, HelpText<"Add directory to library search path">;

Question: How does Clang not give an error for `-L` if this wasn't visible to 
Clang?


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[PATCH] D158430: [flang][driver] Mark -fuse-ld as visible in Flang

[Bryan Chan via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGdc8e46c7e5ea: [flang][driver] Mark -fuse-ld as visible in 
Flang (authored by erjin, committed by bryanpkc).

Repository:
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Files:
  clang/include/clang/Driver/Options.td
  flang/test/Driver/misc-flags.f90


Index: flang/test/Driver/misc-flags.f90
===
--- flang/test/Driver/misc-flags.f90
+++ flang/test/Driver/misc-flags.f90
@@ -4,6 +4,9 @@
 ! Make sure that `-Wl` is "visible" to Flang's driver
 ! RUN: %flang -Wl,abs -### %s
 
+! Make sure that `-fuse-ld' is "visible" to Flang's driver
+! RUN: %flang -fuse-ld= -### %s
+
 program hello
   write(*,*), "Hello world!"
 end program hello
Index: clang/include/clang/Driver/Options.td
===
--- clang/include/clang/Driver/Options.td
+++ clang/include/clang/Driver/Options.td
@@ -5887,7 +5887,7 @@
   "generated assembly will consider GNU as support. 'none' means that all ELF "
   "features can be used, regardless of binutils support. Defaults to 2.26.">;
 def fuse_ld_EQ : Joined<["-"], "fuse-ld=">, Group,
-  Flags<[LinkOption]>, Visibility<[ClangOption, CLOption]>;
+  Flags<[LinkOption]>, Visibility<[ClangOption, FlangOption, CLOption]>;
 def ld_path_EQ : Joined<["--"], "ld-path=">, Group;
 
 defm align_labels : BooleanFFlag<"align-labels">, 
Group;


Index: flang/test/Driver/misc-flags.f90
===
--- flang/test/Driver/misc-flags.f90
+++ flang/test/Driver/misc-flags.f90
@@ -4,6 +4,9 @@
 ! Make sure that `-Wl` is "visible" to Flang's driver
 ! RUN: %flang -Wl,abs -### %s
 
+! Make sure that `-fuse-ld' is "visible" to Flang's driver
+! RUN: %flang -fuse-ld= -### %s
+
 program hello
   write(*,*), "Hello world!"
 end program hello
Index: clang/include/clang/Driver/Options.td
===
--- clang/include/clang/Driver/Options.td
+++ clang/include/clang/Driver/Options.td
@@ -5887,7 +5887,7 @@
   "generated assembly will consider GNU as support. 'none' means that all ELF "
   "features can be used, regardless of binutils support. Defaults to 2.26.">;
 def fuse_ld_EQ : Joined<["-"], "fuse-ld=">, Group,
-  Flags<[LinkOption]>, Visibility<[ClangOption, CLOption]>;
+  Flags<[LinkOption]>, Visibility<[ClangOption, FlangOption, CLOption]>;
 def ld_path_EQ : Joined<["--"], "ld-path=">, Group;
 
 defm align_labels : BooleanFFlag<"align-labels">, Group;
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[PATCH] D156128: [Clang][AArch64] Fix up immediate range of f64f64 mopa/mops intrinsics

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc accepted this revision.
bryanpkc added a comment.
This revision is now accepted and ready to land.

Thanks for the catch!


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[PATCH] D156128: [Clang][AArch64] Fix up immediate range of f64f64 mopa/mops intrinsics

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc added inline comments.



Comment at: clang/include/clang/Basic/arm_sme.td:254
   [IsStreaming, IsSharedZA],
-  [ImmCheck<0, ImmCheck0_3>]>;
+  [ImmCheck<0, ImmCheck0_0>]>;
   }

Shouldn't this say `ImmCheck0_7` instead?


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[PATCH] D156121: [Clang][AArch64] svldr_vnum/svstr_vnum should use cntsb iso vscale for the offset

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc accepted this revision.
bryanpkc added a comment.
This revision is now accepted and ready to land.

LGTM. Sorry for not catching this earlier.


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[PATCH] D142702: [Clang][AArch64][SME] Generate target features from +(no)sme.* options

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc added inline comments.



Comment at: clang/test/Driver/aarch64-implied-sme-features.c:49
+// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+nosme+sme-i16i64 %s 
-### 2>&1 | FileCheck %s --check-prefix=SME-SUBFEATURE-CONFLICT-REV
+// SME-SUBFEATURE-CONFLICT-REV: "-target-feature" "-sme-f64f64" 
"-target-feature" "+sme-i16i64" "-target-feature" "+sme" "-target-feature" 
"+bf16"

MaskRay wrote:
> michaelplatings wrote:
> > Hi Bryan, this test fails in our downstream toolchain because it has 
> > additional features that show up in between these features. Breaking the 
> > line up as shown would fix this. Another option could be to add `{{.*}}` 
> > between the features. Doing likewise for other checks in this file would 
> > make them less brittle as well.
> First: `-target ` has been deprecated since Clang 3.4, Use `--target=` for 
> new tests.
> 
> Do you know why you have additional features? I think placing 
> `"-target-feature"` on the same line is generally a good practice. It 
> strengthens the test to ensure the feature set is compressive is not 
> interleaved by other stuff.
@michaelplatings @MaskRay  I can submit a patch quickly to fix `-target`. I am 
curious what features show up between those ones in my test, because the 
options to toggle dependent features should be added immediately after one 
another. When I placed the `"-target-feature"` strings on the same line, I was 
following the example in `aarch64-implied-sve-features.c`.


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[PATCH] D142702: [Clang][AArch64][SME] Generate target features from +(no)sme.* options

[Bryan Chan via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG2c38740ca661: [Clang][AArch64][SME] Generate target features 
from +(no)sme.* options (authored by bryanpkc).

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Files:
  clang/lib/Driver/ToolChains/Arch/AArch64.cpp
  clang/test/Driver/aarch64-implied-sme-features.c


Index: clang/test/Driver/aarch64-implied-sme-features.c
===
--- /dev/null
+++ clang/test/Driver/aarch64-implied-sme-features.c
@@ -0,0 +1,49 @@
+// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sme %s -### 2>&1 | 
FileCheck %s --check-prefix=SME-IMPLY
+// SME-IMPLY: "-target-feature" "+sme" "-target-feature" "+bf16"
+
+// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+nosme %s -### 2>&1 | 
FileCheck %s --check-prefix=NOSME
+// NOSME: "-target-feature" "-sme"
+
+// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sme+nosme %s -### 2>&1 
| FileCheck %s --check-prefix=SME-REVERT
+// SME-REVERT-NOT: "-target-feature" "+sme"
+// SME-REVERT: "-target-feature" "+bf16" "-target-feature" "-sme" 
"-target-feature" "-sme-f64f64" "-target-feature" "-sme-i16i64"
+
+// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sme+nobf16 %s -### 
2>&1 | FileCheck %s --check-prefix=SME-CONFLICT
+// SME-CONFLICT-NOT: "-target-feature" "+sme"
+// SME-CONFLICT-NOT: "-target-feature" "+bf16"
+// SME-CONFLICT: "-target-feature" "-bf16" "-target-feature" "-sme" 
"-target-feature" "-sme-f64f64" "-target-feature" "-sme-i16i64"
+
+// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sme-i16i64 %s -### 
2>&1 | FileCheck %s --check-prefix=SME-I16I64
+// SME-I16I64: "-target-feature" "+sme-i16i64" "-target-feature" "+sme" 
"-target-feature" "+bf16"
+
+// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+nosme-i16i64 %s -### 
2>&1 | FileCheck %s --check-prefix=NOSME-I16I64
+// NOSME-I16I64-NOT: "-target-feature" "+sme-i16i64"
+// NOSME-I16I64-NOT: "-target-feature" "+sme"
+// NOSME-I16I64-NOT: "-target-feature" "+bf16"
+// NOSME-I16I64: "-target-feature" "-sme-i16i64"
+
+// RUN: %clang -target aarch64-linux-gnu 
-march=armv8-a+sme-i16i64+nosme-i16i64 %s -### 2>&1 | FileCheck %s 
--check-prefix=SME-I16I64-REVERT
+// SME-I16I64-REVERT: "-target-feature" "+sme" "-target-feature" "+bf16" 
"-target-feature" "-sme-i16i64"
+
+// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+nosme-f64f64 %s -### 
2>&1 | FileCheck %s --check-prefix=NOSME-F64F64
+// NOSME-F64F64-NOT: "-target-feature" "+sme-f64f64"
+// NOSME-F64F64-NOT: "-target-feature" "+sme"
+// NOSME-F64F64-NOT: "-target-feature" "+bf16"
+// NOSME-F64F64: "-target-feature" "-sme-f64f64"
+
+// RUN: %clang -target aarch64-linux-gnu 
-march=armv8-a+sme-f64f64+nosme-f64f64 %s -### 2>&1 | FileCheck %s 
--check-prefix=SME-F64F64-REVERT
+// SME-F64F64-REVERT: "-target-feature" "+sme" "-target-feature" "+bf16" 
"-target-feature" "-sme-f64f64"
+
+// RUN: %clang -target aarch64-linux-gnu 
-march=armv8-a+sme-f64f64+nosme-i16i64 %s -### 2>&1 | FileCheck %s 
--check-prefix=SME-SUBFEATURE-MIX
+// SME-SUBFEATURE-MIX: "-target-feature" "+sme-f64f64" "-target-feature" 
"+sme" "-target-feature" "+bf16" "-target-feature" "-sme-i16i64"
+
+// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sme-i16i64+nosme %s 
-### 2>&1 | FileCheck %s --check-prefix=SME-SUBFEATURE-CONFLICT1
+// SME-SUBFEATURE-CONFLICT1: "-target-feature" "+bf16" "-target-feature" 
"-sme" "-target-feature" "-sme-f64f64" "-target-feature" "-sme-i16i64"
+
+// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sme-f64f64+nobf16 %s 
-### 2>&1 | FileCheck %s --check-prefix=SME-SUBFEATURE-CONFLICT2
+// SME-SUBFEATURE-CONFLICT2-NOT: "-target-feature" "+bf16"
+// SME-SUBFEATURE-CONFLICT2-NOT: "-target-feature" "+sme"
+// SME-SUBFEATURE-CONFLICT2-NOT: "-target-feature" "+sme-f64f64"
+
+// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+nosme+sme-i16i64 %s 
-### 2>&1 | FileCheck %s --check-prefix=SME-SUBFEATURE-CONFLICT-REV
+// SME-SUBFEATURE-CONFLICT-REV: "-target-feature" "-sme-f64f64" 
"-target-feature" "+sme-i16i64" "-target-feature" "+sme" "-target-feature" 
"+bf16"
Index: clang/lib/Driver/ToolChains/Arch/AArch64.cpp
===
--- clang/lib/Driver/ToolChains/Arch/AArch64.cpp
+++ clang/lib/Driver/ToolChains/Arch/AArch64.cpp
@@ -82,6 +82,25 @@
 else
   return false;
 
+// +sme implies +bf16.
+// +sme-f64f64 and +sme-i16i64 both imply +sme.
+if (Feature == "sme") {
+  Features.push_back("+bf16");
+} else if (Feature == "nosme") {
+  Features.push_back("-sme-f64f64");
+  Features.push_back("-sme-i16i64");
+} else if (Feature == "sme-f64f64") {
+  Features.push_back("+sme");
+  Features.push_back("+bf16");
+} else if (Feature == "sme-i16i64") 

[PATCH] D134681: [Clang][AArch64][SME] Add outer product intrinsics

[Bryan Chan via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGaebde82b29a8: [Clang][AArch64][SME] Add outer product 
intrinsics (authored by bryanpkc).

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Files:
  clang/include/clang/Basic/arm_sme.td
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mopa-za32.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mopa-za64.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mops-za32.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mops-za64.c
  clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp

Index: clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
===
--- clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
+++ clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
@@ -123,6 +123,19 @@
   SVE_ACLE_FUNC(svaddha_za32, _s32, _m,)(4, pg, pg, svundef_s32());
   // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 3]}}
   SVE_ACLE_FUNC(svaddva_za32, _s32, _m,)(-1, pg, pg, svundef_s32());
+
+  // expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
+  SVE_ACLE_FUNC(svmopa_za32, _s8, _m,)(4, pg, pg, svundef_s8(), svundef_s8());
+  // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 3]}}
+  SVE_ACLE_FUNC(svmops_za32, _s8, _m,)(-1, pg, pg, svundef_s8(), svundef_s8());
+  // expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
+  SVE_ACLE_FUNC(svsumopa_za32, _s8, _m,)(4, pg, pg, svundef_s8(), svundef_u8());
+  // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 3]}}
+  SVE_ACLE_FUNC(svsumops_za32, _s8, _m,)(-1, pg, pg, svundef_s8(), svundef_u8());
+  // expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
+  SVE_ACLE_FUNC(svusmopa_za32, _u8, _m,)(4, pg, pg, svundef_u8(), svundef_s8());
+  // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 3]}}
+  SVE_ACLE_FUNC(svusmops_za32, _u8, _m,)(-1, pg, pg, svundef_u8(), svundef_s8());
 }
 
 void test_range_0_7(svbool_t pg, void *ptr) {
@@ -164,6 +177,19 @@
   SVE_ACLE_FUNC(svaddha_za64, _s64, _m,)(8, pg, pg, svundef_s64());
   // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 7]}}
   SVE_ACLE_FUNC(svaddva_za64, _s64, _m,)(-1, pg, pg, svundef_s64());
+
+  // expected-error@+1 {{argument value 8 is outside the valid range [0, 7]}}
+  SVE_ACLE_FUNC(svmopa_za64, _s16, _m,)(8, pg, pg, svundef_s16(), svundef_s16());
+  // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 7]}}
+  SVE_ACLE_FUNC(svmops_za64, _s16, _m,)(-1, pg, pg, svundef_s16(), svundef_s16());
+  // expected-error@+1 {{argument value 8 is outside the valid range [0, 7]}}
+  SVE_ACLE_FUNC(svsumopa_za64, _s16, _m,)(8, pg, pg, svundef_s16(), svundef_u16());
+  // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 7]}}
+  SVE_ACLE_FUNC(svsumops_za64, _s16, _m,)(-1, pg, pg, svundef_s16(), svundef_u16());
+  // expected-error@+1 {{argument value 8 is outside the valid range [0, 7]}}
+  SVE_ACLE_FUNC(svusmopa_za64, _u16, _m,)(8, pg, pg, svundef_u16(), svundef_s16());
+  // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 7]}}
+  SVE_ACLE_FUNC(svusmops_za64, _u16, _m,)(-1, pg, pg, svundef_u16(), svundef_s16());
 }
 
 void test_range_0_15(svbool_t pg, void *ptr) {
Index: clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mops-za64.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mops-za64.c
@@ -0,0 +1,74 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme-f64f64 -target-feature +sme-i16i64 -target-feature +sve -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme-f64f64 -target-feature +sme-i16i64 -target-feature +sve -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX
+// RUN: %clang_cc1 -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme-f64f64 -target-feature +sme-i16i64 -target-feature +sve -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C
+// RUN: %clang_cc1 -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme-f64f64 -target-feature +sme-i16i64 -target-feature +sve -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu 

[PATCH] D134680: [Clang][AArch64][SME] Add intrinsics for adding vector elements to ZA tile

[Bryan Chan via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG4ae900c06363: [Clang][AArch64][SME] Add intrinsics for 
adding vector elements to ZA tile (authored by bryanpkc).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134680/new/

https://reviews.llvm.org/D134680

Files:
  clang/include/clang/Basic/arm_sme.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i32.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i64.c
  clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp

Index: clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
===
--- clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
+++ clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
@@ -118,6 +118,11 @@
   SVE_ACLE_FUNC(svwrite_hor_za32, _s32, _m,)(0, -1, -1, pg, svundef_s32());
   // expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
   SVE_ACLE_FUNC(svwrite_ver_za32, _s32, _m,)(3, -1, 4, pg, svundef_s32());
+
+  // expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
+  SVE_ACLE_FUNC(svaddha_za32, _s32, _m,)(4, pg, pg, svundef_s32());
+  // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 3]}}
+  SVE_ACLE_FUNC(svaddva_za32, _s32, _m,)(-1, pg, pg, svundef_s32());
 }
 
 void test_range_0_7(svbool_t pg, void *ptr) {
@@ -154,6 +159,11 @@
   SVE_ACLE_FUNC(svwrite_hor_za16, _s16, _m,)(0, -1, -1, pg, svundef_s16());
   // expected-error@+1 {{argument value 8 is outside the valid range [0, 7]}}
   SVE_ACLE_FUNC(svwrite_ver_za16, _s16, _m,)(1, -1, 8, pg, svundef_s16());
+
+  // expected-error@+1 {{argument value 8 is outside the valid range [0, 7]}}
+  SVE_ACLE_FUNC(svaddha_za64, _s64, _m,)(8, pg, pg, svundef_s64());
+  // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 7]}}
+  SVE_ACLE_FUNC(svaddva_za64, _s64, _m,)(-1, pg, pg, svundef_s64());
 }
 
 void test_range_0_15(svbool_t pg, void *ptr) {
Index: clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i64.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i64.c
@@ -0,0 +1,110 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme-i16i64 -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme-i16i64 -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX
+// RUN: %clang_cc1 -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme-i16i64 -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C
+// RUN: %clang_cc1 -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme-i16i64 -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme-i16i64 -target-feature +sve -S -O1 -Werror -o /dev/null %s
+
+#include 
+
+#ifdef SME_OVERLOADED_FORMS
+#define SME_ACLE_FUNC(A1,A2_UNUSED,A3) A1##A3
+#else
+#define SME_ACLE_FUNC(A1,A2,A3) A1##A2##A3
+#endif
+
+// CHECK-C-LABEL: @test_svaddha_za64_u64(
+// CHECK-CXX-LABEL: @_Z21test_svaddha_za64_u64u10__SVBool_tu10__SVBool_tu12__SVUint64_t(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PN:%.*]])
+// CHECK-NEXT:[[TMP1:%.*]] = tail call  @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PM:%.*]])
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.addha.nxv2i64(i32 0,  [[TMP0]],  [[TMP1]],  [[ZN:%.*]])
+// CHECK-NEXT:ret void
+//
+void test_svaddha_za64_u64(svbool_t pn, svbool_t pm, svuint64_t zn) {
+  SME_ACLE_FUNC(svaddha_za64, _u64, _m)(0, pn, pm, zn);
+}
+
+// CHECK-C-LABEL: @test_svaddha_za64_u64_1(
+// CHECK-CXX-LABEL: @_Z23test_svaddha_za64_u64_1u10__SVBool_tu10__SVBool_tu12__SVUint64_t(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PN:%.*]])
+// CHECK-NEXT:[[TMP1:%.*]] = tail call  @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PM:%.*]])
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.addha.nxv2i64(i32 7,  [[TMP0]],  [[TMP1]],  [[ZN:%.*]])
+// CHECK-NEXT:ret void
+//
+void test_svaddha_za64_u64_1(svbool_t pn, svbool_t pm, svuint64_t zn) {
+  SME_ACLE_FUNC(svaddha_za64, _u64, _m)(7, pn, pm, zn);
+}
+
+// CHECK-C-LABEL: @test_svaddha_za64_s64(
+// CHECK-CXX-LABEL: @_Z21test_svaddha_za64_s64u10__SVBool_tu10__SVBool_tu11__SVInt64_t(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  

[PATCH] D134679: [Clang][AArch64][SME] Add intrinsics for reading streaming vector length

[Bryan Chan via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG15d16a79a01f: [Clang][AArch64][SME] Add intrinsics for 
reading streaming vector length (authored by bryanpkc).

Changed prior to commit:
  https://reviews.llvm.org/D134679?vs=526379=542396#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134679/new/

https://reviews.llvm.org/D134679

Files:
  clang/include/clang/Basic/arm_sme.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_cnt.c


Index: clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_cnt.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_cnt.c
@@ -0,0 +1,46 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme 
-target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s 
-check-prefixes=CHECK,CHECK-C
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme 
-target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s 
-check-prefixes=CHECK,CHECK-CXX
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme 
-target-feature +sve -S -O1 -Werror -o /dev/null %s
+
+#include 
+
+// CHECK-C-LABEL: @test_svcntsb(
+// CHECK-CXX-LABEL: @_Z12test_svcntsbv(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 @llvm.aarch64.sme.cntsb()
+// CHECK-NEXT:ret i64 [[TMP0]]
+//
+uint64_t test_svcntsb() {
+  return svcntsb();
+}
+
+// CHECK-C-LABEL: @test_svcntsh(
+// CHECK-CXX-LABEL: @_Z12test_svcntshv(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 @llvm.aarch64.sme.cntsh()
+// CHECK-NEXT:ret i64 [[TMP0]]
+//
+uint64_t test_svcntsh() {
+  return svcntsh();
+}
+
+// CHECK-C-LABEL: @test_svcntsw(
+// CHECK-CXX-LABEL: @_Z12test_svcntswv(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 @llvm.aarch64.sme.cntsw()
+// CHECK-NEXT:ret i64 [[TMP0]]
+//
+uint64_t test_svcntsw() {
+  return svcntsw();
+}
+
+// CHECK-C-LABEL: @test_svcntsd(
+// CHECK-CXX-LABEL: @_Z12test_svcntsdv(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 @llvm.aarch64.sme.cntsd()
+// CHECK-NEXT:ret i64 [[TMP0]]
+//
+uint64_t test_svcntsd() {
+  return svcntsd();
+}
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -9955,6 +9955,7 @@
   getContext().GetBuiltinType(BuiltinID, Error, );
   assert(Error == ASTContext::GE_None && "Should not codegen an error");
 
+  llvm::Type *Ty = ConvertType(E->getType());
   llvm::SmallVector Ops;
   for (unsigned i = 0, e = E->getNumArgs(); i != e; i++) {
 if ((ICEArguments & (1 << i)) == 0)
@@ -9987,6 +9988,12 @@
   else if (BuiltinID == SME::BI__builtin_sme_svldr_vnum_za ||
BuiltinID == SME::BI__builtin_sme_svstr_vnum_za)
 return EmitSMELdrStr(TypeFlags, Ops, Builtin->LLVMIntrinsic);
+  else if (Builtin->LLVMIntrinsic != 0) {
+Function *F = CGM.getIntrinsic(Builtin->LLVMIntrinsic,
+   getSVEOverloadTypes(TypeFlags, Ty, Ops));
+Value *Call = Builder.CreateCall(F, Ops);
+return Call;
+  }
 
   /// Should not happen
   return nullptr;
Index: clang/include/clang/Basic/arm_sme.td
===
--- clang/include/clang/Basic/arm_sme.td
+++ clang/include/clang/Basic/arm_sme.td
@@ -135,3 +135,19 @@
   def SVZERO_ZA  : SInst<"svzero_za", "v", "", MergeNone, 
"aarch64_sme_zero",
  [IsOverloadNone, IsStreamingCompatible, 
IsSharedZA]>;
 }
+
+
+// SME - Counting elements in a streaming vector
+
+multiclass ZACount {
+  let TargetGuard = "sme" in {
+def NAME : SInst<"sv" # n_suffix, "nv", "", MergeNone,
+  "aarch64_sme_" # n_suffix,
+  [IsOverloadNone, IsStreamingCompatible, IsPreservesZA]>;
+  }
+}
+
+defm SVCNTSB : ZACount<"cntsb">;
+defm SVCNTSH : ZACount<"cntsh">;
+defm SVCNTSW : ZACount<"cntsw">;
+defm SVCNTSD : ZACount<"cntsd">;


Index: clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_cnt.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_cnt.c
@@ -0,0 +1,46 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX
+// 

[PATCH] D134678: [Clang][AArch64][SME] Add intrinsics for ZA array load/store (LDR/STR)

[Bryan Chan via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGf225898a7c61: [Clang][AArch64][SME] Add intrinsics for ZA 
array load/store (LDR/STR) (authored by bryanpkc).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134678/new/

https://reviews.llvm.org/D134678

Files:
  clang/include/clang/Basic/arm_sme.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ldr.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_str.c
  clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp

Index: clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
===
--- clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
+++ clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
@@ -174,6 +174,11 @@
   // expected-error@+1 {{argument value 16 is outside the valid range [0, 15]}}
   SVE_ACLE_FUNC(svst1_ver_vnum_za8,,,)(0, -1, 16, pg, ptr, 1);
 
+  // expected-error@+1 {{argument value 16 is outside the valid range [0, 15]}}
+  SVE_ACLE_FUNC(svldr_vnum_za,,,)(-1, 16, ptr);
+  // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 15]}}
+  SVE_ACLE_FUNC(svstr_vnum_za,,,)(-1, -1, ptr);
+
   // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 15]}}
   SVE_ACLE_FUNC(svread_hor_za128, _s8, _m,)(svundef_s8(), pg, -1, -1, 0);
   // expected-error@+1 {{argument value 16 is outside the valid range [0, 15]}}
@@ -209,6 +214,9 @@
   SVE_ACLE_FUNC(svst1_hor_vnum_za32,,,)(u64, u64, 0, pg, ptr, u64); // expected-error {{argument to 'svst1_hor_vnum_za32' must be a constant integer}}
   SVE_ACLE_FUNC(svst1_ver_vnum_za64,,,)(0, u64, u64, pg, ptr, u64); // expected-error {{argument to 'svst1_ver_vnum_za64' must be a constant integer}}
 
+  SVE_ACLE_FUNC(svldr_vnum_za,,,)(u64, u64, ptr); // expected-error {{argument to 'svldr_vnum_za' must be a constant integer}}
+  SVE_ACLE_FUNC(svstr_vnum_za,,,)(u64, u64, ptr); // expected-error {{argument to 'svstr_vnum_za' must be a constant integer}}
+
   SVE_ACLE_FUNC(svread_hor_za8, _s8, _m,)(svundef_s8(), pg, 0, u64, u64); // expected-error-re {{argument to 'svread_hor_za8{{.*}}_m' must be a constant integer}}
   SVE_ACLE_FUNC(svread_ver_za16, _s16, _m,)(svundef_s16(), pg, u64, u64, 0);  // expected-error-re {{argument to 'svread_ver_za16{{.*}}_m' must be a constant integer}}
   SVE_ACLE_FUNC(svwrite_hor_za32, _s32, _m,)(0, u64, u64, pg, svundef_s32()); // expected-error-re {{argument to 'svwrite_hor_za32{{.*}}_m' must be a constant integer}}
Index: clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_str.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_str.c
@@ -0,0 +1,30 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -o /dev/null %s
+
+#include 
+
+// CHECK-C-LABEL: @test_svstr_vnum_za(
+// CHECK-CXX-LABEL: @_Z18test_svstr_vnum_zajPv(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.str(i32 [[SLICE_BASE:%.*]], ptr [[PTR:%.*]])
+// CHECK-NEXT:ret void
+//
+void test_svstr_vnum_za(uint32_t slice_base, void *ptr) {
+  svstr_vnum_za(slice_base, 0, ptr);
+}
+
+// CHECK-C-LABEL: @test_svstr_vnum_za_1(
+// CHECK-CXX-LABEL: @_Z20test_svstr_vnum_za_1jPv(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[VSCALE:%.*]] = tail call i64 @llvm.vscale.i64()
+// CHECK-NEXT:[[MULVL:%.*]] = mul nuw nsw i64 [[VSCALE]], 240
+// CHECK-NEXT:[[TMP0:%.*]] = getelementptr i8, ptr [[PTR:%.*]], i64 [[MULVL]]
+// CHECK-NEXT:[[TILESLICE:%.*]] = add i32 [[SLICE_BASE:%.*]], 15
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.str(i32 [[TILESLICE]], ptr [[TMP0]])
+// CHECK-NEXT:ret void
+//
+void test_svstr_vnum_za_1(uint32_t slice_base, void *ptr) {
+  svstr_vnum_za(slice_base, 15, ptr);
+}
Index: clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ldr.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ldr.c
@@ -0,0 +1,30 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve 

[PATCH] D134677: [Clang][AArch64][SME] Add ZA zeroing intrinsics

[Bryan Chan via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG578b0bd4e621: [Clang][AArch64][SME] Add ZA zeroing 
intrinsics (authored by bryanpkc).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134677/new/

https://reviews.llvm.org/D134677

Files:
  clang/include/clang/Basic/arm_sme.td
  clang/include/clang/Basic/arm_sve_sme_incl.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_zero.c
  clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp

Index: clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
===
--- clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
+++ clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
@@ -192,6 +192,13 @@
   SVE_ACLE_FUNC(svwrite_ver_za8, _s8, _m,)(0, -1, 16, pg, svundef_s8());
 }
 
+void test_range_0_255(svbool_t pg, void *ptr) {
+  // expected-error@+1 {{argument value 256 is outside the valid range [0, 255]}}
+  SVE_ACLE_FUNC(svzero_mask_za,,,)(256);
+  // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 255]}}
+  SVE_ACLE_FUNC(svzero_mask_za,,,)(-1);
+}
+
 void test_constant(uint64_t u64, svbool_t pg, void *ptr) {
   SVE_ACLE_FUNC(svld1_hor_za8,,,)(u64, u64, 0, pg, ptr);  // expected-error {{argument to 'svld1_hor_za8' must be a constant integer}}
   SVE_ACLE_FUNC(svld1_ver_za16,,,)(0, u64, u64, pg, ptr); // expected-error {{argument to 'svld1_ver_za16' must be a constant integer}}
Index: clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_zero.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_zero.c
@@ -0,0 +1,46 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -o /dev/null %s
+
+#include 
+
+// CHECK-C-LABEL: @test_svzero_mask_za(
+// CHECK-CXX-LABEL: @_Z19test_svzero_mask_zav(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.zero(i32 0)
+// CHECK-NEXT:ret void
+//
+void test_svzero_mask_za() {
+  svzero_mask_za(0);
+}
+
+// CHECK-C-LABEL: @test_svzero_mask_za_1(
+// CHECK-CXX-LABEL: @_Z21test_svzero_mask_za_1v(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.zero(i32 176)
+// CHECK-NEXT:ret void
+//
+void test_svzero_mask_za_1() {
+  svzero_mask_za(176);
+}
+
+// CHECK-C-LABEL: @test_svzero_mask_za_2(
+// CHECK-CXX-LABEL: @_Z21test_svzero_mask_za_2v(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.zero(i32 255)
+// CHECK-NEXT:ret void
+//
+void test_svzero_mask_za_2() {
+  svzero_mask_za(255);
+}
+
+// CHECK-C-LABEL: @test_svzero_za(
+// CHECK-CXX-LABEL: @_Z14test_svzero_zav(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.zero(i32 255)
+// CHECK-NEXT:ret void
+//
+void test_svzero_za() {
+  svzero_za();
+}
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3003,6 +3003,10 @@
   if (SemaBuiltinConstantArgRange(TheCall, ArgNum, 0, 15))
 HasError = true;
   break;
+case SVETypeFlags::ImmCheck0_255:
+  if (SemaBuiltinConstantArgRange(TheCall, ArgNum, 0, 255))
+HasError = true;
+  break;
 }
   }
 
Index: clang/lib/CodeGen/CodeGenFunction.h
===
--- clang/lib/CodeGen/CodeGenFunction.h
+++ clang/lib/CodeGen/CodeGenFunction.h
@@ -4283,6 +4283,9 @@
   llvm::Value *EmitSMEReadWrite(SVETypeFlags TypeFlags,
 llvm::SmallVectorImpl ,
 unsigned IntID);
+  llvm::Value *EmitSMEZero(SVETypeFlags TypeFlags,
+   llvm::SmallVectorImpl ,
+   unsigned IntID);
   llvm::Value *EmitAArch64SMEBuiltinExpr(unsigned BuiltinID, const CallExpr *E);
 
   llvm::Value *EmitAArch64BuiltinExpr(unsigned BuiltinID, const CallExpr *E,
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -9495,6 +9495,16 @@
   return Builder.CreateCall(F, Ops);
 }
 
+Value *CodeGenFunction::EmitSMEZero(SVETypeFlags TypeFlags,
+   

[PATCH] D134678: [Clang][AArch64][SME] Add intrinsics for ZA array load/store (LDR/STR)

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc updated this revision to Diff 541132.
bryanpkc marked an inline comment as done.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134678/new/

https://reviews.llvm.org/D134678

Files:
  clang/include/clang/Basic/arm_sme.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ldr.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_str.c
  clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp

Index: clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
===
--- clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
+++ clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
@@ -174,6 +174,11 @@
   // expected-error@+1 {{argument value 16 is outside the valid range [0, 15]}}
   SVE_ACLE_FUNC(svst1_ver_vnum_za8,,,)(0, -1, 16, pg, ptr, 1);
 
+  // expected-error@+1 {{argument value 16 is outside the valid range [0, 15]}}
+  SVE_ACLE_FUNC(svldr_vnum_za,,,)(-1, 16, ptr);
+  // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 15]}}
+  SVE_ACLE_FUNC(svstr_vnum_za,,,)(-1, -1, ptr);
+
   // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 15]}}
   SVE_ACLE_FUNC(svread_hor_za128, _s8, _m,)(svundef_s8(), pg, -1, -1, 0);
   // expected-error@+1 {{argument value 16 is outside the valid range [0, 15]}}
@@ -209,6 +214,9 @@
   SVE_ACLE_FUNC(svst1_hor_vnum_za32,,,)(u64, u64, 0, pg, ptr, u64); // expected-error {{argument to 'svst1_hor_vnum_za32' must be a constant integer}}
   SVE_ACLE_FUNC(svst1_ver_vnum_za64,,,)(0, u64, u64, pg, ptr, u64); // expected-error {{argument to 'svst1_ver_vnum_za64' must be a constant integer}}
 
+  SVE_ACLE_FUNC(svldr_vnum_za,,,)(u64, u64, ptr); // expected-error {{argument to 'svldr_vnum_za' must be a constant integer}}
+  SVE_ACLE_FUNC(svstr_vnum_za,,,)(u64, u64, ptr); // expected-error {{argument to 'svstr_vnum_za' must be a constant integer}}
+
   SVE_ACLE_FUNC(svread_hor_za8, _s8, _m,)(svundef_s8(), pg, 0, u64, u64); // expected-error-re {{argument to 'svread_hor_za8{{.*}}_m' must be a constant integer}}
   SVE_ACLE_FUNC(svread_ver_za16, _s16, _m,)(svundef_s16(), pg, u64, u64, 0);  // expected-error-re {{argument to 'svread_ver_za16{{.*}}_m' must be a constant integer}}
   SVE_ACLE_FUNC(svwrite_hor_za32, _s32, _m,)(0, u64, u64, pg, svundef_s32()); // expected-error-re {{argument to 'svwrite_hor_za32{{.*}}_m' must be a constant integer}}
Index: clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_str.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_str.c
@@ -0,0 +1,30 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -o /dev/null %s
+
+#include 
+
+// CHECK-C-LABEL: @test_svstr_vnum_za(
+// CHECK-CXX-LABEL: @_Z18test_svstr_vnum_zajPv(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.str(i32 [[SLICE_BASE:%.*]], ptr [[PTR:%.*]])
+// CHECK-NEXT:ret void
+//
+void test_svstr_vnum_za(uint32_t slice_base, void *ptr) {
+  svstr_vnum_za(slice_base, 0, ptr);
+}
+
+// CHECK-C-LABEL: @test_svstr_vnum_za_1(
+// CHECK-CXX-LABEL: @_Z20test_svstr_vnum_za_1jPv(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[VSCALE:%.*]] = tail call i64 @llvm.vscale.i64()
+// CHECK-NEXT:[[MULVL:%.*]] = mul nuw nsw i64 [[VSCALE]], 240
+// CHECK-NEXT:[[TMP0:%.*]] = getelementptr i8, ptr [[PTR:%.*]], i64 [[MULVL]]
+// CHECK-NEXT:[[TILESLICE:%.*]] = add i32 [[SLICE_BASE:%.*]], 15
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.str(i32 [[TILESLICE]], ptr [[TMP0]])
+// CHECK-NEXT:ret void
+//
+void test_svstr_vnum_za_1(uint32_t slice_base, void *ptr) {
+  svstr_vnum_za(slice_base, 15, ptr);
+}
Index: clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ldr.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ldr.c
@@ -0,0 +1,30 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme 

[PATCH] D134678: [Clang][AArch64][SME] Add intrinsics for ZA array load/store (LDR/STR)

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc marked an inline comment as done.
bryanpkc added inline comments.



Comment at: clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_str.c:24
+// CHECK-NEXT:[[TMP0:%.*]] = getelementptr i8, ptr [[PTR:%.*]], i64 
[[MULVL]]
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.str(i32 [[SLICE_BASE:%.*]], 
ptr [[TMP0]])
+// CHECK-NEXT:ret void

sdesmalen wrote:
> This is missing an `add` of `15` to `%slice_base`.
Thanks for catching that. Fixed.


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[PATCH] D128648: [Clang][AArch64][SME] Add vector read/write (mova) intrinsics

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc marked an inline comment as done.
bryanpkc added inline comments.



Comment at: clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_read.c:22
+//
+svint8_t test_svread_hor_za8_s8(svint8_t zd, svbool_t pg, uint32_t slice_base) 
__arm_streaming {
+return SME_ACLE_FUNC(svread_hor_za8, _s8, _m)(zd, pg, 0, slice_base, 0);

sdesmalen wrote:
> I think you've missed removing these?
You are right, my bad. Fixed.


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[PATCH] D142702: [Clang][AArch64][SME] Generate target features from +(no)sme.* options

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc updated this revision to Diff 540842.
bryanpkc marked an inline comment as done.
bryanpkc added a comment.

Removed dependency on SVE and SVE2 as per @sdesmalen's suggestion. Also made 
`nobf16` imply `nosme` to be consistent with the handling of other feature 
dependencies.


Repository:
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Files:
  clang/lib/Driver/ToolChains/Arch/AArch64.cpp
  clang/test/Driver/aarch64-implied-sme-features.c


Index: clang/test/Driver/aarch64-implied-sme-features.c
===
--- /dev/null
+++ clang/test/Driver/aarch64-implied-sme-features.c
@@ -0,0 +1,49 @@
+// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sme %s -### 2>&1 | 
FileCheck %s --check-prefix=SME-IMPLY
+// SME-IMPLY: "-target-feature" "+sme" "-target-feature" "+bf16"
+
+// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+nosme %s -### 2>&1 | 
FileCheck %s --check-prefix=NOSME
+// NOSME: "-target-feature" "-sme"
+
+// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sme+nosme %s -### 2>&1 
| FileCheck %s --check-prefix=SME-REVERT
+// SME-REVERT-NOT: "-target-feature" "+sme"
+// SME-REVERT: "-target-feature" "+bf16" "-target-feature" "-sme" 
"-target-feature" "-sme-f64f64" "-target-feature" "-sme-i16i64"
+
+// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sme+nobf16 %s -### 
2>&1 | FileCheck %s --check-prefix=SME-CONFLICT
+// SME-CONFLICT-NOT: "-target-feature" "+sme"
+// SME-CONFLICT-NOT: "-target-feature" "+bf16"
+// SME-CONFLICT: "-target-feature" "-bf16" "-target-feature" "-sme" 
"-target-feature" "-sme-f64f64" "-target-feature" "-sme-i16i64"
+
+// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sme-i16i64 %s -### 
2>&1 | FileCheck %s --check-prefix=SME-I16I64
+// SME-I16I64: "-target-feature" "+sme-i16i64" "-target-feature" "+sme" 
"-target-feature" "+bf16"
+
+// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+nosme-i16i64 %s -### 
2>&1 | FileCheck %s --check-prefix=NOSME-I16I64
+// NOSME-I16I64-NOT: "-target-feature" "+sme-i16i64"
+// NOSME-I16I64-NOT: "-target-feature" "+sme"
+// NOSME-I16I64-NOT: "-target-feature" "+bf16"
+// NOSME-I16I64: "-target-feature" "-sme-i16i64"
+
+// RUN: %clang -target aarch64-linux-gnu 
-march=armv8-a+sme-i16i64+nosme-i16i64 %s -### 2>&1 | FileCheck %s 
--check-prefix=SME-I16I64-REVERT
+// SME-I16I64-REVERT: "-target-feature" "+sme" "-target-feature" "+bf16" 
"-target-feature" "-sme-i16i64"
+
+// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+nosme-f64f64 %s -### 
2>&1 | FileCheck %s --check-prefix=NOSME-F64F64
+// NOSME-F64F64-NOT: "-target-feature" "+sme-f64f64"
+// NOSME-F64F64-NOT: "-target-feature" "+sme"
+// NOSME-F64F64-NOT: "-target-feature" "+bf16"
+// NOSME-F64F64: "-target-feature" "-sme-f64f64"
+
+// RUN: %clang -target aarch64-linux-gnu 
-march=armv8-a+sme-f64f64+nosme-f64f64 %s -### 2>&1 | FileCheck %s 
--check-prefix=SME-F64F64-REVERT
+// SME-F64F64-REVERT: "-target-feature" "+sme" "-target-feature" "+bf16" 
"-target-feature" "-sme-f64f64"
+
+// RUN: %clang -target aarch64-linux-gnu 
-march=armv8-a+sme-f64f64+nosme-i16i64 %s -### 2>&1 | FileCheck %s 
--check-prefix=SME-SUBFEATURE-MIX
+// SME-SUBFEATURE-MIX: "-target-feature" "+sme-f64f64" "-target-feature" 
"+sme" "-target-feature" "+bf16" "-target-feature" "-sme-i16i64"
+
+// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sme-i16i64+nosme %s 
-### 2>&1 | FileCheck %s --check-prefix=SME-SUBFEATURE-CONFLICT1
+// SME-SUBFEATURE-CONFLICT1: "-target-feature" "+bf16" "-target-feature" 
"-sme" "-target-feature" "-sme-f64f64" "-target-feature" "-sme-i16i64"
+
+// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sme-f64f64+nobf16 %s 
-### 2>&1 | FileCheck %s --check-prefix=SME-SUBFEATURE-CONFLICT2
+// SME-SUBFEATURE-CONFLICT2-NOT: "-target-feature" "+bf16"
+// SME-SUBFEATURE-CONFLICT2-NOT: "-target-feature" "+sme"
+// SME-SUBFEATURE-CONFLICT2-NOT: "-target-feature" "+sme-f64f64"
+
+// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+nosme+sme-i16i64 %s 
-### 2>&1 | FileCheck %s --check-prefix=SME-SUBFEATURE-CONFLICT-REV
+// SME-SUBFEATURE-CONFLICT-REV: "-target-feature" "-sme-f64f64" 
"-target-feature" "+sme-i16i64" "-target-feature" "+sme" "-target-feature" 
"+bf16"
Index: clang/lib/Driver/ToolChains/Arch/AArch64.cpp
===
--- clang/lib/Driver/ToolChains/Arch/AArch64.cpp
+++ clang/lib/Driver/ToolChains/Arch/AArch64.cpp
@@ -82,6 +82,25 @@
 else
   return false;
 
+// +sme implies +bf16.
+// +sme-f64f64 and +sme-i16i64 both imply +sme.
+if (Feature == "sme") {
+  Features.push_back("+bf16");
+} else if (Feature == "nosme") {
+  Features.push_back("-sme-f64f64");
+  Features.push_back("-sme-i16i64");
+} else if (Feature == "sme-f64f64") {
+  Features.push_back("+sme");
+  Features.push_back("+bf16");
+} else 

[PATCH] D134681: [Clang][AArch64][SME] Add outer product intrinsics

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc updated this revision to Diff 540841.
bryanpkc added a comment.

Removed the attribute macro from tests, as @sdesmalen suggested.


Repository:
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Files:
  clang/include/clang/Basic/arm_sme.td
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mopa-za32.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mopa-za64.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mops-za32.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mops-za64.c
  clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp

Index: clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
===
--- clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
+++ clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
@@ -123,6 +123,19 @@
   SVE_ACLE_FUNC(svaddha_za32, _s32, _m,)(4, pg, pg, svundef_s32());
   // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 3]}}
   SVE_ACLE_FUNC(svaddva_za32, _s32, _m,)(-1, pg, pg, svundef_s32());
+
+  // expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
+  SVE_ACLE_FUNC(svmopa_za32, _s8, _m,)(4, pg, pg, svundef_s8(), svundef_s8());
+  // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 3]}}
+  SVE_ACLE_FUNC(svmops_za32, _s8, _m,)(-1, pg, pg, svundef_s8(), svundef_s8());
+  // expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
+  SVE_ACLE_FUNC(svsumopa_za32, _s8, _m,)(4, pg, pg, svundef_s8(), svundef_u8());
+  // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 3]}}
+  SVE_ACLE_FUNC(svsumops_za32, _s8, _m,)(-1, pg, pg, svundef_s8(), svundef_u8());
+  // expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
+  SVE_ACLE_FUNC(svusmopa_za32, _u8, _m,)(4, pg, pg, svundef_u8(), svundef_s8());
+  // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 3]}}
+  SVE_ACLE_FUNC(svusmops_za32, _u8, _m,)(-1, pg, pg, svundef_u8(), svundef_s8());
 }
 
 void test_range_0_7(svbool_t pg, void *ptr) {
@@ -164,6 +177,19 @@
   SVE_ACLE_FUNC(svaddha_za64, _s64, _m,)(8, pg, pg, svundef_s64());
   // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 7]}}
   SVE_ACLE_FUNC(svaddva_za64, _s64, _m,)(-1, pg, pg, svundef_s64());
+
+  // expected-error@+1 {{argument value 8 is outside the valid range [0, 7]}}
+  SVE_ACLE_FUNC(svmopa_za64, _s16, _m,)(8, pg, pg, svundef_s16(), svundef_s16());
+  // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 7]}}
+  SVE_ACLE_FUNC(svmops_za64, _s16, _m,)(-1, pg, pg, svundef_s16(), svundef_s16());
+  // expected-error@+1 {{argument value 8 is outside the valid range [0, 7]}}
+  SVE_ACLE_FUNC(svsumopa_za64, _s16, _m,)(8, pg, pg, svundef_s16(), svundef_u16());
+  // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 7]}}
+  SVE_ACLE_FUNC(svsumops_za64, _s16, _m,)(-1, pg, pg, svundef_s16(), svundef_u16());
+  // expected-error@+1 {{argument value 8 is outside the valid range [0, 7]}}
+  SVE_ACLE_FUNC(svusmopa_za64, _u16, _m,)(8, pg, pg, svundef_u16(), svundef_s16());
+  // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 7]}}
+  SVE_ACLE_FUNC(svusmops_za64, _u16, _m,)(-1, pg, pg, svundef_u16(), svundef_s16());
 }
 
 void test_range_0_15(svbool_t pg, void *ptr) {
Index: clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mops-za64.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mops-za64.c
@@ -0,0 +1,74 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme-f64f64 -target-feature +sme-i16i64 -target-feature +sve -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme-f64f64 -target-feature +sme-i16i64 -target-feature +sve -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX
+// RUN: %clang_cc1 -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme-f64f64 -target-feature +sme-i16i64 -target-feature +sve -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C
+// RUN: %clang_cc1 -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme-f64f64 -target-feature +sme-i16i64 -target-feature +sve -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme-f64f64 -target-feature +sme-i16i64 -target-feature +sve -target-feature +bf16 -S -O1 

[PATCH] D134680: [Clang][AArch64][SME] Add intrinsics for adding vector elements to ZA tile

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc updated this revision to Diff 540840.
bryanpkc added a comment.

Removed the attribute macro from tests, as @sdesmalen suggested.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134680/new/

https://reviews.llvm.org/D134680

Files:
  clang/include/clang/Basic/arm_sme.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i32.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i64.c
  clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp

Index: clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
===
--- clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
+++ clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
@@ -118,6 +118,11 @@
   SVE_ACLE_FUNC(svwrite_hor_za32, _s32, _m,)(0, -1, -1, pg, svundef_s32());
   // expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
   SVE_ACLE_FUNC(svwrite_ver_za32, _s32, _m,)(3, -1, 4, pg, svundef_s32());
+
+  // expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
+  SVE_ACLE_FUNC(svaddha_za32, _s32, _m,)(4, pg, pg, svundef_s32());
+  // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 3]}}
+  SVE_ACLE_FUNC(svaddva_za32, _s32, _m,)(-1, pg, pg, svundef_s32());
 }
 
 void test_range_0_7(svbool_t pg, void *ptr) {
@@ -154,6 +159,11 @@
   SVE_ACLE_FUNC(svwrite_hor_za16, _s16, _m,)(0, -1, -1, pg, svundef_s16());
   // expected-error@+1 {{argument value 8 is outside the valid range [0, 7]}}
   SVE_ACLE_FUNC(svwrite_ver_za16, _s16, _m,)(1, -1, 8, pg, svundef_s16());
+
+  // expected-error@+1 {{argument value 8 is outside the valid range [0, 7]}}
+  SVE_ACLE_FUNC(svaddha_za64, _s64, _m,)(8, pg, pg, svundef_s64());
+  // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 7]}}
+  SVE_ACLE_FUNC(svaddva_za64, _s64, _m,)(-1, pg, pg, svundef_s64());
 }
 
 void test_range_0_15(svbool_t pg, void *ptr) {
Index: clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i64.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i64.c
@@ -0,0 +1,110 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme-i16i64 -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme-i16i64 -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX
+// RUN: %clang_cc1 -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme-i16i64 -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C
+// RUN: %clang_cc1 -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme-i16i64 -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme-i16i64 -target-feature +sve -S -O1 -Werror -o /dev/null %s
+
+#include 
+
+#ifdef SME_OVERLOADED_FORMS
+#define SME_ACLE_FUNC(A1,A2_UNUSED,A3) A1##A3
+#else
+#define SME_ACLE_FUNC(A1,A2,A3) A1##A2##A3
+#endif
+
+// CHECK-C-LABEL: @test_svaddha_za64_u64(
+// CHECK-CXX-LABEL: @_Z21test_svaddha_za64_u64u10__SVBool_tu10__SVBool_tu12__SVUint64_t(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PN:%.*]])
+// CHECK-NEXT:[[TMP1:%.*]] = tail call  @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PM:%.*]])
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.addha.nxv2i64(i32 0,  [[TMP0]],  [[TMP1]],  [[ZN:%.*]])
+// CHECK-NEXT:ret void
+//
+void test_svaddha_za64_u64(svbool_t pn, svbool_t pm, svuint64_t zn) {
+  SME_ACLE_FUNC(svaddha_za64, _u64, _m)(0, pn, pm, zn);
+}
+
+// CHECK-C-LABEL: @test_svaddha_za64_u64_1(
+// CHECK-CXX-LABEL: @_Z23test_svaddha_za64_u64_1u10__SVBool_tu10__SVBool_tu12__SVUint64_t(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PN:%.*]])
+// CHECK-NEXT:[[TMP1:%.*]] = tail call  @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PM:%.*]])
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.addha.nxv2i64(i32 7,  [[TMP0]],  [[TMP1]],  [[ZN:%.*]])
+// CHECK-NEXT:ret void
+//
+void test_svaddha_za64_u64_1(svbool_t pn, svbool_t pm, svuint64_t zn) {
+  SME_ACLE_FUNC(svaddha_za64, _u64, _m)(7, pn, pm, zn);
+}
+
+// CHECK-C-LABEL: @test_svaddha_za64_s64(
+// CHECK-CXX-LABEL: @_Z21test_svaddha_za64_s64u10__SVBool_tu10__SVBool_tu11__SVInt64_t(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PN:%.*]])
+// CHECK-NEXT:[[TMP1:%.*]] = tail call  

[PATCH] D134678: [Clang][AArch64][SME] Add intrinsics for ZA array load/store (LDR/STR)

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc updated this revision to Diff 540839.
bryanpkc added a comment.

Removed the attribute macro from tests, as @sdesmalen suggested.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134678/new/

https://reviews.llvm.org/D134678

Files:
  clang/include/clang/Basic/arm_sme.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ldr.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_str.c
  clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp

Index: clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
===
--- clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
+++ clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
@@ -174,6 +174,11 @@
   // expected-error@+1 {{argument value 16 is outside the valid range [0, 15]}}
   SVE_ACLE_FUNC(svst1_ver_vnum_za8,,,)(0, -1, 16, pg, ptr, 1);
 
+  // expected-error@+1 {{argument value 16 is outside the valid range [0, 15]}}
+  SVE_ACLE_FUNC(svldr_vnum_za,,,)(-1, 16, ptr);
+  // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 15]}}
+  SVE_ACLE_FUNC(svstr_vnum_za,,,)(-1, -1, ptr);
+
   // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 15]}}
   SVE_ACLE_FUNC(svread_hor_za128, _s8, _m,)(svundef_s8(), pg, -1, -1, 0);
   // expected-error@+1 {{argument value 16 is outside the valid range [0, 15]}}
@@ -209,6 +214,9 @@
   SVE_ACLE_FUNC(svst1_hor_vnum_za32,,,)(u64, u64, 0, pg, ptr, u64); // expected-error {{argument to 'svst1_hor_vnum_za32' must be a constant integer}}
   SVE_ACLE_FUNC(svst1_ver_vnum_za64,,,)(0, u64, u64, pg, ptr, u64); // expected-error {{argument to 'svst1_ver_vnum_za64' must be a constant integer}}
 
+  SVE_ACLE_FUNC(svldr_vnum_za,,,)(u64, u64, ptr); // expected-error {{argument to 'svldr_vnum_za' must be a constant integer}}
+  SVE_ACLE_FUNC(svstr_vnum_za,,,)(u64, u64, ptr); // expected-error {{argument to 'svstr_vnum_za' must be a constant integer}}
+
   SVE_ACLE_FUNC(svread_hor_za8, _s8, _m,)(svundef_s8(), pg, 0, u64, u64); // expected-error-re {{argument to 'svread_hor_za8{{.*}}_m' must be a constant integer}}
   SVE_ACLE_FUNC(svread_ver_za16, _s16, _m,)(svundef_s16(), pg, u64, u64, 0);  // expected-error-re {{argument to 'svread_ver_za16{{.*}}_m' must be a constant integer}}
   SVE_ACLE_FUNC(svwrite_hor_za32, _s32, _m,)(0, u64, u64, pg, svundef_s32()); // expected-error-re {{argument to 'svwrite_hor_za32{{.*}}_m' must be a constant integer}}
Index: clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_str.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_str.c
@@ -0,0 +1,29 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -o /dev/null %s
+
+#include 
+
+// CHECK-C-LABEL: @test_svstr_vnum_za(
+// CHECK-CXX-LABEL: @_Z18test_svstr_vnum_zajPv(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.str(i32 [[SLICE_BASE:%.*]], ptr [[PTR:%.*]])
+// CHECK-NEXT:ret void
+//
+void test_svstr_vnum_za(uint32_t slice_base, void *ptr) {
+  svstr_vnum_za(slice_base, 0, ptr);
+}
+
+// CHECK-C-LABEL: @test_svstr_vnum_za_1(
+// CHECK-CXX-LABEL: @_Z20test_svstr_vnum_za_1jPv(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[VSCALE:%.*]] = tail call i64 @llvm.vscale.i64()
+// CHECK-NEXT:[[MULVL:%.*]] = mul nuw nsw i64 [[VSCALE]], 240
+// CHECK-NEXT:[[TMP0:%.*]] = getelementptr i8, ptr [[PTR:%.*]], i64 [[MULVL]]
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.str(i32 [[SLICE_BASE:%.*]], ptr [[TMP0]])
+// CHECK-NEXT:ret void
+//
+void test_svstr_vnum_za_1(uint32_t slice_base, void *ptr) {
+  svstr_vnum_za(slice_base, 15, ptr);
+}
Index: clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ldr.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ldr.c
@@ -0,0 +1,29 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S 

[PATCH] D134677: [Clang][AArch64][SME] Add ZA zeroing intrinsics

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc updated this revision to Diff 540838.
bryanpkc added a comment.

Removed the attribute macro as suggested.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134677/new/

https://reviews.llvm.org/D134677

Files:
  clang/include/clang/Basic/arm_sme.td
  clang/include/clang/Basic/arm_sve_sme_incl.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_zero.c
  clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp

Index: clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
===
--- clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
+++ clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
@@ -192,6 +192,13 @@
   SVE_ACLE_FUNC(svwrite_ver_za8, _s8, _m,)(0, -1, 16, pg, svundef_s8());
 }
 
+void test_range_0_255(svbool_t pg, void *ptr) {
+  // expected-error@+1 {{argument value 256 is outside the valid range [0, 255]}}
+  SVE_ACLE_FUNC(svzero_mask_za,,,)(256);
+  // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 255]}}
+  SVE_ACLE_FUNC(svzero_mask_za,,,)(-1);
+}
+
 void test_constant(uint64_t u64, svbool_t pg, void *ptr) {
   SVE_ACLE_FUNC(svld1_hor_za8,,,)(u64, u64, 0, pg, ptr);  // expected-error {{argument to 'svld1_hor_za8' must be a constant integer}}
   SVE_ACLE_FUNC(svld1_ver_za16,,,)(0, u64, u64, pg, ptr); // expected-error {{argument to 'svld1_ver_za16' must be a constant integer}}
Index: clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_zero.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_zero.c
@@ -0,0 +1,46 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -o /dev/null %s
+
+#include 
+
+// CHECK-C-LABEL: @test_svzero_mask_za(
+// CHECK-CXX-LABEL: @_Z19test_svzero_mask_zav(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.zero(i32 0)
+// CHECK-NEXT:ret void
+//
+void test_svzero_mask_za() {
+  svzero_mask_za(0);
+}
+
+// CHECK-C-LABEL: @test_svzero_mask_za_1(
+// CHECK-CXX-LABEL: @_Z21test_svzero_mask_za_1v(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.zero(i32 176)
+// CHECK-NEXT:ret void
+//
+void test_svzero_mask_za_1() {
+  svzero_mask_za(176);
+}
+
+// CHECK-C-LABEL: @test_svzero_mask_za_2(
+// CHECK-CXX-LABEL: @_Z21test_svzero_mask_za_2v(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.zero(i32 255)
+// CHECK-NEXT:ret void
+//
+void test_svzero_mask_za_2() {
+  svzero_mask_za(255);
+}
+
+// CHECK-C-LABEL: @test_svzero_za(
+// CHECK-CXX-LABEL: @_Z14test_svzero_zav(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.zero(i32 255)
+// CHECK-NEXT:ret void
+//
+void test_svzero_za() {
+  svzero_za();
+}
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3003,6 +3003,10 @@
   if (SemaBuiltinConstantArgRange(TheCall, ArgNum, 0, 15))
 HasError = true;
   break;
+case SVETypeFlags::ImmCheck0_255:
+  if (SemaBuiltinConstantArgRange(TheCall, ArgNum, 0, 255))
+HasError = true;
+  break;
 }
   }
 
Index: clang/lib/CodeGen/CodeGenFunction.h
===
--- clang/lib/CodeGen/CodeGenFunction.h
+++ clang/lib/CodeGen/CodeGenFunction.h
@@ -4283,6 +4283,9 @@
   llvm::Value *EmitSMEReadWrite(SVETypeFlags TypeFlags,
 llvm::SmallVectorImpl ,
 unsigned IntID);
+  llvm::Value *EmitSMEZero(SVETypeFlags TypeFlags,
+   llvm::SmallVectorImpl ,
+   unsigned IntID);
   llvm::Value *EmitAArch64SMEBuiltinExpr(unsigned BuiltinID, const CallExpr *E);
 
   llvm::Value *EmitAArch64BuiltinExpr(unsigned BuiltinID, const CallExpr *E,
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -9495,6 +9495,16 @@
   return Builder.CreateCall(F, Ops);
 }
 
+Value *CodeGenFunction::EmitSMEZero(SVETypeFlags TypeFlags,
+SmallVectorImpl ,
+unsigned IntID) {
+  // svzero_za() intrinsic zeros the entire za tile and has no 

[PATCH] D128648: [Clang][AArch64][SME] Add vector read/write (mova) intrinsics

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc marked an inline comment as done.
bryanpkc added inline comments.



Comment at: clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_read.c:13
+#else
+#define ARM_STREAMING_ATTR __attribute__((arm_streaming))
+#endif

sdesmalen wrote:
> The spelling has recently changed to the `__arm_streaming`. Also with the new 
> attribute keywords, the position of the attributes is more strict and need 
> sto be after the function arguments (e.g. `svint8_t test_svread_..(...) 
> ARM_STREAMING_ATTR {`)
> 
> Sorry if I previously gave you the wrong steer here to add these macros, but 
> I've changed my mind and think it's better to remove them for now. That means 
> we won't have any streaming attributes on the functions in the tests, but we 
> can (and will need to) add those when we add diagnostics for missing 
> attributes, for example when using a `shared ZA` intrinsic  when the function 
> misses `__arm_shared_za/__arm_new_za`, or when using a streaming intrinsic 
> when the function is not `__arm_streaming`. Writing this also made me realise 
> the functions below would be missing `__arm_shared_za` attributes.
> 
> Can you remove these macros from the patches? Again, my apologies for the 
> wrong steer!
@sdesmalen Thanks for the clarification and sorry for the late reply as I was 
on vacation. I have updated the patch as you suggested. I can also look into 
adding support for more attributes and corresponding semantic checks, if you 
guys haven't started already.


Repository:
  rG LLVM Github Monorepo

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[PATCH] D128648: [Clang][AArch64][SME] Add vector read/write (mova) intrinsics

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc added a comment.

@sdesmalen Could you take a look at the patch stack again?


Repository:
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[PATCH] D134677: [Clang][AArch64][SME] Add ZA zeroing intrinsics

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc updated this revision to Diff 532431.
bryanpkc marked 3 inline comments as done.
bryanpkc added a comment.

Rebased. NFC.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134677/new/

https://reviews.llvm.org/D134677

Files:
  clang/include/clang/Basic/arm_sme.td
  clang/include/clang/Basic/arm_sve_sme_incl.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_zero.c
  clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp

Index: clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
===
--- clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
+++ clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
@@ -14,8 +14,10 @@
 
 #ifdef DISABLE_SME_ATTRIBUTES
 #define ARM_STREAMING_ATTR
+#define ARM_SHARED_ZA_ATTR
 #else
 #define ARM_STREAMING_ATTR __attribute__((arm_streaming))
+#define ARM_SHARED_ZA_ATTR __attribute__((arm_shared_za))
 #endif
 
 ARM_STREAMING_ATTR
@@ -203,6 +205,14 @@
   SVE_ACLE_FUNC(svwrite_ver_za8, _s8, _m,)(0, -1, 16, pg, svundef_s8());
 }
 
+ARM_SHARED_ZA_ATTR
+void test_range_0_255(svbool_t pg, void *ptr) {
+  // expected-error@+1 {{argument value 256 is outside the valid range [0, 255]}}
+  SVE_ACLE_FUNC(svzero_mask_za,,,)(256);
+  // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 255]}}
+  SVE_ACLE_FUNC(svzero_mask_za,,,)(-1);
+}
+
 ARM_STREAMING_ATTR
 void test_constant(uint64_t u64, svbool_t pg, void *ptr) {
   SVE_ACLE_FUNC(svld1_hor_za8,,,)(u64, u64, 0, pg, ptr);  // expected-error {{argument to 'svld1_hor_za8' must be a constant integer}}
Index: clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_zero.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_zero.c
@@ -0,0 +1,52 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -DDISABLE_SME_ATTRIBUTES -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C
+// RUN: %clang_cc1 -DDISABLE_SME_ATTRIBUTES -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX
+// RUN: %clang_cc1 -DDISABLE_SME_ATTRIBUTES -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -o /dev/null %s
+
+#include 
+
+#ifdef DISABLE_SME_ATTRIBUTES
+#define ARM_SHARED_ZA_ATTR
+#else
+#define ARM_SHARED_ZA_ATTR __attribute__((arm_shared_za))
+#endif
+
+// CHECK-C-LABEL: @test_svzero_mask_za(
+// CHECK-CXX-LABEL: @_Z19test_svzero_mask_zav(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.zero(i32 0)
+// CHECK-NEXT:ret void
+//
+ARM_SHARED_ZA_ATTR void test_svzero_mask_za() {
+  svzero_mask_za(0);
+}
+
+// CHECK-C-LABEL: @test_svzero_mask_za_1(
+// CHECK-CXX-LABEL: @_Z21test_svzero_mask_za_1v(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.zero(i32 176)
+// CHECK-NEXT:ret void
+//
+ARM_SHARED_ZA_ATTR void test_svzero_mask_za_1() {
+  svzero_mask_za(176);
+}
+
+// CHECK-C-LABEL: @test_svzero_mask_za_2(
+// CHECK-CXX-LABEL: @_Z21test_svzero_mask_za_2v(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.zero(i32 255)
+// CHECK-NEXT:ret void
+//
+ARM_SHARED_ZA_ATTR void test_svzero_mask_za_2() {
+  svzero_mask_za(255);
+}
+
+// CHECK-C-LABEL: @test_svzero_za(
+// CHECK-CXX-LABEL: @_Z14test_svzero_zav(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.zero(i32 255)
+// CHECK-NEXT:ret void
+//
+ARM_SHARED_ZA_ATTR void test_svzero_za() {
+  svzero_za();
+}
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -2995,6 +2995,10 @@
   if (SemaBuiltinConstantArgRange(TheCall, ArgNum, 0, 15))
 HasError = true;
   break;
+case SVETypeFlags::ImmCheck0_255:
+  if (SemaBuiltinConstantArgRange(TheCall, ArgNum, 0, 255))
+HasError = true;
+  break;
 }
   }
 
Index: clang/lib/CodeGen/CodeGenFunction.h
===
--- clang/lib/CodeGen/CodeGenFunction.h
+++ clang/lib/CodeGen/CodeGenFunction.h
@@ -4266,6 +4266,9 @@
   llvm::Value *EmitSMEReadWrite(SVETypeFlags TypeFlags,
 llvm::SmallVectorImpl ,
 unsigned IntID);
+  llvm::Value *EmitSMEZero(SVETypeFlags TypeFlags,
+   llvm::SmallVectorImpl ,
+   unsigned IntID);
   llvm::Value *EmitAArch64SMEBuiltinExpr(unsigned BuiltinID, const CallExpr *E);
 
   llvm::Value *EmitAArch64BuiltinExpr(unsigned 

[PATCH] D134678: [Clang][AArch64][SME] Add intrinsics for ZA array load/store (LDR/STR)

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc updated this revision to Diff 531953.
bryanpkc added a comment.

Also added SME attributes to the tests.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134678/new/

https://reviews.llvm.org/D134678

Files:
  clang/include/clang/Basic/arm_sme.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ldr.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_str.c
  clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp

Index: clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
===
--- clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
+++ clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
@@ -187,6 +187,11 @@
   // expected-error@+1 {{argument value 16 is outside the valid range [0, 15]}}
   SVE_ACLE_FUNC(svst1_ver_vnum_za8,,,)(0, -1, 16, pg, ptr, 1);
 
+  // expected-error@+1 {{argument value 16 is outside the valid range [0, 15]}}
+  SVE_ACLE_FUNC(svldr_vnum_za,,,)(-1, 16, ptr);
+  // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 15]}}
+  SVE_ACLE_FUNC(svstr_vnum_za,,,)(-1, -1, ptr);
+
   // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 15]}}
   SVE_ACLE_FUNC(svread_hor_za128, _s8, _m,)(svundef_s8(), pg, -1, -1, 0);
   // expected-error@+1 {{argument value 16 is outside the valid range [0, 15]}}
@@ -224,6 +229,9 @@
   SVE_ACLE_FUNC(svst1_hor_vnum_za32,,,)(u64, u64, 0, pg, ptr, u64); // expected-error {{argument to 'svst1_hor_vnum_za32' must be a constant integer}}
   SVE_ACLE_FUNC(svst1_ver_vnum_za64,,,)(0, u64, u64, pg, ptr, u64); // expected-error {{argument to 'svst1_ver_vnum_za64' must be a constant integer}}
 
+  SVE_ACLE_FUNC(svldr_vnum_za,,,)(u64, u64, ptr); // expected-error {{argument to 'svldr_vnum_za' must be a constant integer}}
+  SVE_ACLE_FUNC(svstr_vnum_za,,,)(u64, u64, ptr); // expected-error {{argument to 'svstr_vnum_za' must be a constant integer}}
+
   SVE_ACLE_FUNC(svread_hor_za8, _s8, _m,)(svundef_s8(), pg, 0, u64, u64); // expected-error-re {{argument to 'svread_hor_za8{{.*}}_m' must be a constant integer}}
   SVE_ACLE_FUNC(svread_ver_za16, _s16, _m,)(svundef_s16(), pg, u64, u64, 0);  // expected-error-re {{argument to 'svread_ver_za16{{.*}}_m' must be a constant integer}}
   SVE_ACLE_FUNC(svwrite_hor_za32, _s32, _m,)(0, u64, u64, pg, svundef_s32()); // expected-error-re {{argument to 'svwrite_hor_za32{{.*}}_m' must be a constant integer}}
Index: clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_str.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_str.c
@@ -0,0 +1,35 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -DDISABLE_SME_ATTRIBUTES -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C
+// RUN: %clang_cc1 -DDISABLE_SME_ATTRIBUTES -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX
+// RUN: %clang_cc1 -DDISABLE_SME_ATTRIBUTES -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -o /dev/null %s
+
+#include 
+
+#ifdef DISABLE_SME_ATTRIBUTES
+#define ARM_SHARED_ZA_ATTR
+#else
+#define ARM_SHARED_ZA_ATTR __attribute__((arm_shared_za))
+#endif
+
+// CHECK-C-LABEL: @test_svstr_vnum_za(
+// CHECK-CXX-LABEL: @_Z18test_svstr_vnum_zajPv(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.str(i32 [[SLICE_BASE:%.*]], ptr [[PTR:%.*]])
+// CHECK-NEXT:ret void
+//
+ARM_SHARED_ZA_ATTR void test_svstr_vnum_za(uint32_t slice_base, void *ptr) {
+  svstr_vnum_za(slice_base, 0, ptr);
+}
+
+// CHECK-C-LABEL: @test_svstr_vnum_za_1(
+// CHECK-CXX-LABEL: @_Z20test_svstr_vnum_za_1jPv(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[VSCALE:%.*]] = tail call i64 @llvm.vscale.i64()
+// CHECK-NEXT:[[MULVL:%.*]] = mul nuw nsw i64 [[VSCALE]], 240
+// CHECK-NEXT:[[TMP0:%.*]] = getelementptr i8, ptr [[PTR:%.*]], i64 [[MULVL]]
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.str(i32 [[SLICE_BASE:%.*]], ptr [[TMP0]])
+// CHECK-NEXT:ret void
+//
+ARM_SHARED_ZA_ATTR void test_svstr_vnum_za_1(uint32_t slice_base, void *ptr) {
+  svstr_vnum_za(slice_base, 15, ptr);
+}
Index: clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ldr.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ldr.c
@@ -0,0 +1,35 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -DDISABLE_SME_ATTRIBUTES -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C
+// RUN: %clang_cc1 

[PATCH] D134678: [Clang][AArch64][SME] Add intrinsics for ZA array load/store (LDR/STR)

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc updated this revision to Diff 531949.
bryanpkc added a comment.

Instead of defining new type flags, `EmitAArch64SMEBuiltinExpr` is updated to 
switch on `BuiltinID`, as suggested by @sdesmalen.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134678/new/

https://reviews.llvm.org/D134678

Files:
  clang/include/clang/Basic/arm_sme.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ldr.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_str.c
  clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp

Index: clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
===
--- clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
+++ clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
@@ -187,6 +187,11 @@
   // expected-error@+1 {{argument value 16 is outside the valid range [0, 15]}}
   SVE_ACLE_FUNC(svst1_ver_vnum_za8,,,)(0, -1, 16, pg, ptr, 1);
 
+  // expected-error@+1 {{argument value 16 is outside the valid range [0, 15]}}
+  SVE_ACLE_FUNC(svldr_vnum_za,,,)(-1, 16, ptr);
+  // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 15]}}
+  SVE_ACLE_FUNC(svstr_vnum_za,,,)(-1, -1, ptr);
+
   // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 15]}}
   SVE_ACLE_FUNC(svread_hor_za128, _s8, _m,)(svundef_s8(), pg, -1, -1, 0);
   // expected-error@+1 {{argument value 16 is outside the valid range [0, 15]}}
@@ -224,6 +229,9 @@
   SVE_ACLE_FUNC(svst1_hor_vnum_za32,,,)(u64, u64, 0, pg, ptr, u64); // expected-error {{argument to 'svst1_hor_vnum_za32' must be a constant integer}}
   SVE_ACLE_FUNC(svst1_ver_vnum_za64,,,)(0, u64, u64, pg, ptr, u64); // expected-error {{argument to 'svst1_ver_vnum_za64' must be a constant integer}}
 
+  SVE_ACLE_FUNC(svldr_vnum_za,,,)(u64, u64, ptr); // expected-error {{argument to 'svldr_vnum_za' must be a constant integer}}
+  SVE_ACLE_FUNC(svstr_vnum_za,,,)(u64, u64, ptr); // expected-error {{argument to 'svstr_vnum_za' must be a constant integer}}
+
   SVE_ACLE_FUNC(svread_hor_za8, _s8, _m,)(svundef_s8(), pg, 0, u64, u64); // expected-error-re {{argument to 'svread_hor_za8{{.*}}_m' must be a constant integer}}
   SVE_ACLE_FUNC(svread_ver_za16, _s16, _m,)(svundef_s16(), pg, u64, u64, 0);  // expected-error-re {{argument to 'svread_ver_za16{{.*}}_m' must be a constant integer}}
   SVE_ACLE_FUNC(svwrite_hor_za32, _s32, _m,)(0, u64, u64, pg, svundef_s32()); // expected-error-re {{argument to 'svwrite_hor_za32{{.*}}_m' must be a constant integer}}
Index: clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_str.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_str.c
@@ -0,0 +1,29 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -o /dev/null %s
+
+#include 
+
+// CHECK-C-LABEL: @test_svstr_vnum_za(
+// CHECK-CXX-LABEL: @_Z18test_svstr_vnum_zajPv(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.str(i32 [[SLICE_BASE:%.*]], ptr [[PTR:%.*]])
+// CHECK-NEXT:ret void
+//
+void test_svstr_vnum_za(uint32_t slice_base, void *ptr) {
+  svstr_vnum_za(slice_base, 0, ptr);
+}
+
+// CHECK-C-LABEL: @test_svstr_vnum_za_1(
+// CHECK-CXX-LABEL: @_Z20test_svstr_vnum_za_1jPv(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[VSCALE:%.*]] = tail call i64 @llvm.vscale.i64()
+// CHECK-NEXT:[[MULVL:%.*]] = mul nuw nsw i64 [[VSCALE]], 240
+// CHECK-NEXT:[[TMP0:%.*]] = getelementptr i8, ptr [[PTR:%.*]], i64 [[MULVL]]
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.str(i32 [[SLICE_BASE:%.*]], ptr [[TMP0]])
+// CHECK-NEXT:ret void
+//
+void test_svstr_vnum_za_1(uint32_t slice_base, void *ptr) {
+  svstr_vnum_za(slice_base, 15, ptr);
+}
Index: clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ldr.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ldr.c
@@ -0,0 +1,29 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX
+// RUN: %clang_cc1 -triple 

[PATCH] D134677: [Clang][AArch64][SME] Add ZA zeroing intrinsics

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc updated this revision to Diff 531330.
bryanpkc added a comment.

Addressed @sdesmalen's comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134677/new/

https://reviews.llvm.org/D134677

Files:
  clang/include/clang/Basic/arm_sme.td
  clang/include/clang/Basic/arm_sve_sme_incl.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_zero.c
  clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp

Index: clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
===
--- clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
+++ clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
@@ -14,8 +14,10 @@
 
 #ifdef DISABLE_SME_ATTRIBUTES
 #define ARM_STREAMING_ATTR
+#define ARM_SHARED_ZA_ATTR
 #else
 #define ARM_STREAMING_ATTR __attribute__((arm_streaming))
+#define ARM_SHARED_ZA_ATTR __attribute__((arm_shared_za))
 #endif
 
 ARM_STREAMING_ATTR
@@ -203,6 +205,14 @@
   SVE_ACLE_FUNC(svwrite_ver_za8, _s8, _m,)(0, -1, 16, pg, svundef_s8());
 }
 
+ARM_SHARED_ZA_ATTR
+void test_range_0_255(svbool_t pg, void *ptr) {
+  // expected-error@+1 {{argument value 256 is outside the valid range [0, 255]}}
+  SVE_ACLE_FUNC(svzero_mask_za,,,)(256);
+  // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 255]}}
+  SVE_ACLE_FUNC(svzero_mask_za,,,)(-1);
+}
+
 ARM_STREAMING_ATTR
 void test_constant(uint64_t u64, svbool_t pg, void *ptr) {
   SVE_ACLE_FUNC(svld1_hor_za8,,,)(u64, u64, 0, pg, ptr);  // expected-error {{argument to 'svld1_hor_za8' must be a constant integer}}
Index: clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_zero.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_zero.c
@@ -0,0 +1,52 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -DDISABLE_SME_ATTRIBUTES -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C
+// RUN: %clang_cc1 -DDISABLE_SME_ATTRIBUTES -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX
+// RUN: %clang_cc1 -DDISABLE_SME_ATTRIBUTES -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -o /dev/null %s
+
+#include 
+
+#ifdef DISABLE_SME_ATTRIBUTES
+#define ARM_SHARED_ZA_ATTR
+#else
+#define ARM_SHARED_ZA_ATTR __attribute__((arm_shared_za))
+#endif
+
+// CHECK-C-LABEL: @test_svzero_mask_za(
+// CHECK-CXX-LABEL: @_Z19test_svzero_mask_zav(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.zero(i32 0)
+// CHECK-NEXT:ret void
+//
+ARM_SHARED_ZA_ATTR void test_svzero_mask_za() {
+  svzero_mask_za(0);
+}
+
+// CHECK-C-LABEL: @test_svzero_mask_za_1(
+// CHECK-CXX-LABEL: @_Z21test_svzero_mask_za_1v(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.zero(i32 176)
+// CHECK-NEXT:ret void
+//
+ARM_SHARED_ZA_ATTR void test_svzero_mask_za_1() {
+  svzero_mask_za(176);
+}
+
+// CHECK-C-LABEL: @test_svzero_mask_za_2(
+// CHECK-CXX-LABEL: @_Z21test_svzero_mask_za_2v(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.zero(i32 255)
+// CHECK-NEXT:ret void
+//
+ARM_SHARED_ZA_ATTR void test_svzero_mask_za_2() {
+  svzero_mask_za(255);
+}
+
+// CHECK-C-LABEL: @test_svzero_za(
+// CHECK-CXX-LABEL: @_Z14test_svzero_zav(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.zero(i32 255)
+// CHECK-NEXT:ret void
+//
+ARM_SHARED_ZA_ATTR void test_svzero_za() {
+  svzero_za();
+}
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -2995,6 +2995,10 @@
   if (SemaBuiltinConstantArgRange(TheCall, ArgNum, 0, 15))
 HasError = true;
   break;
+case SVETypeFlags::ImmCheck0_255:
+  if (SemaBuiltinConstantArgRange(TheCall, ArgNum, 0, 255))
+HasError = true;
+  break;
 }
   }
 
Index: clang/lib/CodeGen/CodeGenFunction.h
===
--- clang/lib/CodeGen/CodeGenFunction.h
+++ clang/lib/CodeGen/CodeGenFunction.h
@@ -4266,6 +4266,9 @@
   llvm::Value *EmitSMEReadWrite(SVETypeFlags TypeFlags,
 llvm::SmallVectorImpl ,
 unsigned IntID);
+  llvm::Value *EmitSMEZero(SVETypeFlags TypeFlags,
+   llvm::SmallVectorImpl ,
+   unsigned IntID);
   llvm::Value *EmitAArch64SMEBuiltinExpr(unsigned BuiltinID, const CallExpr *E);
 
   llvm::Value *EmitAArch64BuiltinExpr(unsigned BuiltinID, const CallExpr *E,

[PATCH] D128648: [Clang][AArch64][SME] Add vector read/write (mova) intrinsics

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc added a comment.

@sdesmalen Could you review this and the rest of the patch stack?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128648/new/

https://reviews.llvm.org/D128648

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[PATCH] D142702: [Clang][AArch64][SME] Generate target features from +(no)sme.* options

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc updated this revision to Diff 528293.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D142702/new/

https://reviews.llvm.org/D142702

Files:
  clang/lib/Driver/ToolChains/Arch/AArch64.cpp
  clang/test/Driver/aarch64-implied-sme-features.c
  clang/test/Driver/aarch64-implied-sve-features.c

Index: clang/test/Driver/aarch64-implied-sve-features.c
===
--- clang/test/Driver/aarch64-implied-sve-features.c
+++ clang/test/Driver/aarch64-implied-sve-features.c
@@ -57,7 +57,7 @@
 // SVE2-SUBFEATURE-MIX: "-target-feature" "+sve2-bitperm" "-target-feature" "+sve" "-target-feature" "+sve2" "-target-feature" "-sve2-aes"
 
 // RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+sve2-sm4+nosve2 %s -### 2>&1 | FileCheck %s --check-prefix=SVE2-SUBFEATURE-CONFLICT
-// SVE2-SUBFEATURE-CONFLICT: "-target-feature" "+sve" "-target-feature" "-sve2" "-target-feature" "-sve2-bitperm" "-target-feature" "-sve2-sha3" "-target-feature" "-sve2-aes" "-target-feature" "-sve2-sm4"
+// SVE2-SUBFEATURE-CONFLICT: "-target-feature" "+sve" "-target-feature" "-sve2" "-target-feature" "-sve2-bitperm" "-target-feature" "-sve2-sha3" "-target-feature" "-sve2-aes" "-target-feature" "-sve2-sm4" "-target-feature" "-sme" "-target-feature" "-sme-f64f64" "-target-feature" "-sme-i16i64"
 
 // RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+sve2-aes+nosve %s -### 2>&1 | FileCheck %s --check-prefix=SVE-SUBFEATURE-CONFLICT
 // SVE-SUBFEATURE-CONFLICT-NOT: "-target-feature" "+sve2-aes"
@@ -65,7 +65,7 @@
 // SVE-SUBFEATURE-CONFLICT-NOT: "-target-feature" "+sve"
 
 // RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+nosve+sve2-aes %s -### 2>&1 | FileCheck %s --check-prefix=SVE-SUBFEATURE-CONFLICT-REV
-// SVE-SUBFEATURE-CONFLICT-REV: "-target-feature" "-sve2-bitperm" "-target-feature" "-sve2-sha3" "-target-feature" "-sve2-sm4" "-target-feature" "+sve2-aes" "-target-feature" "+sve" "-target-feature" "+sve2"
+// SVE-SUBFEATURE-CONFLICT-REV: "-target-feature" "-sve2-bitperm" "-target-feature" "-sve2-sha3" "-target-feature" "-sve2-sm4" "-target-feature" "-sme" "-target-feature" "-sme-f64f64" "-target-feature" "-sme-i16i64" "-target-feature" "+sve2-aes" "-target-feature" "+sve" "-target-feature" "+sve2"
 
 // RUN: %clang --target=aarch64-linux-gnu -mcpu=neoverse-n2+nosve2 %s -### 2>&1 | FileCheck %s --check-prefix=SVE-MCPU-FEATURES
 // SVE-MCPU-FEATURES-NOT: "-target-feature" "+sve2-bitperm"
Index: clang/test/Driver/aarch64-implied-sme-features.c
===
--- /dev/null
+++ clang/test/Driver/aarch64-implied-sme-features.c
@@ -0,0 +1,55 @@
+// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sme %s -### 2>&1 | FileCheck %s --check-prefix=SME-IMPLY
+// SME-IMPLY: "-target-feature" "+sme" "-target-feature" "+sve" "-target-feature" "+sve2" "-target-feature" "+bf16"
+
+// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+nosme %s -### 2>&1 | FileCheck %s --check-prefix=NOSME
+// NOSME: "-target-feature" "-sme"
+
+// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sme+nosme %s -### 2>&1 | FileCheck %s --check-prefix=SME-REVERT
+// SME-REVERT-NOT: "-target-feature" "+sme"
+// SME-REVERT: "-target-feature" "+sve" "-target-feature" "+sve2" "-target-feature" "+bf16" "-target-feature" "-sme" "-target-feature" "-sme-f64f64" "-target-feature" "-sme-i16i64"
+
+// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sme+nosve %s -### 2>&1 | FileCheck %s --check-prefix=SME-CONFLICT
+// SME-CONFLICT: "-target-feature" "-sve" "-target-feature" "-sve2" "-target-feature" "-sve2-bitperm" "-target-feature" "-sve2-sha3" "-target-feature" "-sve2-aes" "-target-feature" "-sve2-sm4" "-target-feature" "-sme"
+
+// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sme+sve %s -### 2>&1 | FileCheck %s --check-prefix=SME-SVE
+// SME-SVE: "-target-feature" "+sme" "-target-feature" "+sve2" "-target-feature" "+bf16" "-target-feature" "+sve"
+
+// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sme-i16i64 %s -### 2>&1 | FileCheck %s --check-prefix=SME-I16I64
+// SME-I16I64: "-target-feature" "+sme-i16i64" "-target-feature" "+sme" "-target-feature" "+sve" "-target-feature" "+sve2" "-target-feature" "+bf16"
+
+// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+nosme-i16i64 %s -### 2>&1 | FileCheck %s --check-prefix=NOSME-I16I64
+// NOSME-I16I64-NOT: "-target-feature" "+sme-i16i64"
+// NOSME-I16I64-NOT: "-target-feature" "+sme"
+// NOSME-I16I64-NOT: "-target-feature" "+sve"
+// NOSME-I16I64-NOT: "-target-feature" "+sve2"
+// NOSME-I16I64-NOT: "-target-feature" "+bf16"
+// NOSME-I16I64: "-target-feature" "-sme-i16i64"
+
+// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sme-i16i64+nosme-i16i64 %s -### 2>&1 | FileCheck %s --check-prefix=SME-I16I64-REVERT
+// SME-I16I64-REVERT: "-target-feature" "+sme" "-target-feature" "+sve" "-target-feature" "+sve2" "-target-feature" "+bf16" 

[PATCH] D134681: [Clang][AArch64][SME] Add outer product intrinsics

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc updated this revision to Diff 528291.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134681/new/

https://reviews.llvm.org/D134681

Files:
  clang/include/clang/Basic/arm_sme.td
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mopa-za32.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mopa-za64.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mops-za32.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mops-za64.c
  clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp

Index: clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
===
--- clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
+++ clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
@@ -132,6 +132,19 @@
   SVE_ACLE_FUNC(svaddha_za32, _s32, _m,)(4, pg, pg, svundef_s32());
   // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 3]}}
   SVE_ACLE_FUNC(svaddva_za32, _s32, _m,)(-1, pg, pg, svundef_s32());
+
+  // expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
+  SVE_ACLE_FUNC(svmopa_za32, _s8, _m,)(4, pg, pg, svundef_s8(), svundef_s8());
+  // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 3]}}
+  SVE_ACLE_FUNC(svmops_za32, _s8, _m,)(-1, pg, pg, svundef_s8(), svundef_s8());
+  // expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
+  SVE_ACLE_FUNC(svsumopa_za32, _s8, _m,)(4, pg, pg, svundef_s8(), svundef_u8());
+  // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 3]}}
+  SVE_ACLE_FUNC(svsumops_za32, _s8, _m,)(-1, pg, pg, svundef_s8(), svundef_u8());
+  // expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
+  SVE_ACLE_FUNC(svusmopa_za32, _u8, _m,)(4, pg, pg, svundef_u8(), svundef_s8());
+  // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 3]}}
+  SVE_ACLE_FUNC(svusmops_za32, _u8, _m,)(-1, pg, pg, svundef_u8(), svundef_s8());
 }
 
 ARM_STREAMING_ATTR
@@ -174,6 +187,19 @@
   SVE_ACLE_FUNC(svaddha_za64, _s64, _m,)(8, pg, pg, svundef_s64());
   // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 7]}}
   SVE_ACLE_FUNC(svaddva_za64, _s64, _m,)(-1, pg, pg, svundef_s64());
+
+  // expected-error@+1 {{argument value 8 is outside the valid range [0, 7]}}
+  SVE_ACLE_FUNC(svmopa_za64, _s16, _m,)(8, pg, pg, svundef_s16(), svundef_s16());
+  // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 7]}}
+  SVE_ACLE_FUNC(svmops_za64, _s16, _m,)(-1, pg, pg, svundef_s16(), svundef_s16());
+  // expected-error@+1 {{argument value 8 is outside the valid range [0, 7]}}
+  SVE_ACLE_FUNC(svsumopa_za64, _s16, _m,)(8, pg, pg, svundef_s16(), svundef_u16());
+  // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 7]}}
+  SVE_ACLE_FUNC(svsumops_za64, _s16, _m,)(-1, pg, pg, svundef_s16(), svundef_u16());
+  // expected-error@+1 {{argument value 8 is outside the valid range [0, 7]}}
+  SVE_ACLE_FUNC(svusmopa_za64, _u16, _m,)(8, pg, pg, svundef_u16(), svundef_s16());
+  // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 7]}}
+  SVE_ACLE_FUNC(svusmops_za64, _u16, _m,)(-1, pg, pg, svundef_u16(), svundef_s16());
 }
 
 ARM_STREAMING_ATTR
Index: clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mops-za64.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mops-za64.c
@@ -0,0 +1,80 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -DDISABLE_SME_ATTRIBUTES -triple aarch64-none-linux-gnu -target-feature +sme-f64f64 -target-feature +sme-i16i64 -target-feature +sve -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C
+// RUN: %clang_cc1 -DDISABLE_SME_ATTRIBUTES -triple aarch64-none-linux-gnu -target-feature +sme-f64f64 -target-feature +sme-i16i64 -target-feature +sve -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX
+// RUN: %clang_cc1 -DDISABLE_SME_ATTRIBUTES -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme-f64f64 -target-feature +sme-i16i64 -target-feature +sve -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C
+// RUN: %clang_cc1 -DDISABLE_SME_ATTRIBUTES -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme-f64f64 -target-feature +sme-i16i64 -target-feature +sve -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX
+// RUN: %clang_cc1 -DDISABLE_SME_ATTRIBUTES -triple aarch64-none-linux-gnu -target-feature +sme-f64f64 -target-feature +sme-i16i64 -target-feature +sve -target-feature +bf16 -S -O1 -Werror -o /dev/null %s

[PATCH] D134680: [Clang][AArch64][SME] Add intrinsics for adding vector elements to ZA tile

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc updated this revision to Diff 526683.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134680/new/

https://reviews.llvm.org/D134680

Files:
  clang/include/clang/Basic/arm_sme.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i32.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i64.c
  clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp

Index: clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
===
--- clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
+++ clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
@@ -127,6 +127,11 @@
   SVE_ACLE_FUNC(svwrite_hor_za32, _s32, _m,)(0, -1, -1, pg, svundef_s32());
   // expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
   SVE_ACLE_FUNC(svwrite_ver_za32, _s32, _m,)(3, -1, 4, pg, svundef_s32());
+
+  // expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
+  SVE_ACLE_FUNC(svaddha_za32, _s32, _m,)(4, pg, pg, svundef_s32());
+  // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 3]}}
+  SVE_ACLE_FUNC(svaddva_za32, _s32, _m,)(-1, pg, pg, svundef_s32());
 }
 
 ARM_STREAMING_ATTR
@@ -164,6 +169,11 @@
   SVE_ACLE_FUNC(svwrite_hor_za16, _s16, _m,)(0, -1, -1, pg, svundef_s16());
   // expected-error@+1 {{argument value 8 is outside the valid range [0, 7]}}
   SVE_ACLE_FUNC(svwrite_ver_za16, _s16, _m,)(1, -1, 8, pg, svundef_s16());
+
+  // expected-error@+1 {{argument value 8 is outside the valid range [0, 7]}}
+  SVE_ACLE_FUNC(svaddha_za64, _s64, _m,)(8, pg, pg, svundef_s64());
+  // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 7]}}
+  SVE_ACLE_FUNC(svaddva_za64, _s64, _m,)(-1, pg, pg, svundef_s64());
 }
 
 ARM_STREAMING_ATTR
Index: clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i64.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i64.c
@@ -0,0 +1,116 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -DDISABLE_SME_ATTRIBUTES -triple aarch64-none-linux-gnu -target-feature +sme-i16i64 -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C
+// RUN: %clang_cc1 -DDISABLE_SME_ATTRIBUTES -triple aarch64-none-linux-gnu -target-feature +sme-i16i64 -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX
+// RUN: %clang_cc1 -DDISABLE_SME_ATTRIBUTES -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme-i16i64 -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C
+// RUN: %clang_cc1 -DDISABLE_SME_ATTRIBUTES -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme-i16i64 -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX
+// RUN: %clang_cc1 -DDISABLE_SME_ATTRIBUTES -triple aarch64-none-linux-gnu -target-feature +sme-i16i64 -target-feature +sve -S -O1 -Werror -o /dev/null %s
+
+#include 
+
+#ifdef DISABLE_SME_ATTRIBUTES
+#define ARM_STREAMING_ATTR
+#else
+#define ARM_STREAMING_ATTR __attribute__((arm_streaming))
+#endif
+
+#ifdef SME_OVERLOADED_FORMS
+#define SME_ACLE_FUNC(A1,A2_UNUSED,A3) A1##A3
+#else
+#define SME_ACLE_FUNC(A1,A2,A3) A1##A2##A3
+#endif
+
+// CHECK-C-LABEL: @test_svaddha_za64_u64(
+// CHECK-CXX-LABEL: @_Z21test_svaddha_za64_u64u10__SVBool_tu10__SVBool_tu12__SVUint64_t(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PN:%.*]])
+// CHECK-NEXT:[[TMP1:%.*]] = tail call  @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PM:%.*]])
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.addha.nxv2i64(i32 0,  [[TMP0]],  [[TMP1]],  [[ZN:%.*]])
+// CHECK-NEXT:ret void
+//
+ARM_STREAMING_ATTR void test_svaddha_za64_u64(svbool_t pn, svbool_t pm, svuint64_t zn) {
+  SME_ACLE_FUNC(svaddha_za64, _u64, _m)(0, pn, pm, zn);
+}
+
+// CHECK-C-LABEL: @test_svaddha_za64_u64_1(
+// CHECK-CXX-LABEL: @_Z23test_svaddha_za64_u64_1u10__SVBool_tu10__SVBool_tu12__SVUint64_t(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PN:%.*]])
+// CHECK-NEXT:[[TMP1:%.*]] = tail call  @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PM:%.*]])
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.addha.nxv2i64(i32 7,  [[TMP0]],  [[TMP1]],  [[ZN:%.*]])
+// CHECK-NEXT:ret void
+//
+ARM_STREAMING_ATTR void test_svaddha_za64_u64_1(svbool_t pn, svbool_t pm, svuint64_t zn) {
+  SME_ACLE_FUNC(svaddha_za64, _u64, _m)(7, pn, pm, zn);
+}
+
+// CHECK-C-LABEL: @test_svaddha_za64_s64(
+// CHECK-CXX-LABEL: @_Z21test_svaddha_za64_s64u10__SVBool_tu10__SVBool_tu11__SVInt64_t(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = 

[PATCH] D134680: [Clang][AArch64][SME] Add intrinsics for adding vector elements to ZA tile

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc updated this revision to Diff 526621.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134680/new/

https://reviews.llvm.org/D134680

Files:
  clang/include/clang/Basic/arm_sme.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i32.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i64.c

Index: clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i64.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i64.c
@@ -0,0 +1,116 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -DDISABLE_SME_ATTRIBUTES -triple aarch64-none-linux-gnu -target-feature +sme-i16i64 -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C
+// RUN: %clang_cc1 -DDISABLE_SME_ATTRIBUTES -triple aarch64-none-linux-gnu -target-feature +sme-i16i64 -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX
+// RUN: %clang_cc1 -DDISABLE_SME_ATTRIBUTES -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme-i16i64 -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C
+// RUN: %clang_cc1 -DDISABLE_SME_ATTRIBUTES -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme-i16i64 -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX
+// RUN: %clang_cc1 -DDISABLE_SME_ATTRIBUTES -triple aarch64-none-linux-gnu -target-feature +sme-i16i64 -target-feature +sve -S -O1 -Werror -o /dev/null %s
+
+#include 
+
+#ifdef DISABLE_SME_ATTRIBUTES
+#define ARM_STREAMING_ATTR
+#else
+#define ARM_STREAMING_ATTR __attribute__((arm_streaming))
+#endif
+
+#ifdef SME_OVERLOADED_FORMS
+#define SME_ACLE_FUNC(A1,A2_UNUSED,A3) A1##A3
+#else
+#define SME_ACLE_FUNC(A1,A2,A3) A1##A2##A3
+#endif
+
+// CHECK-C-LABEL: @test_svaddha_za64_u64(
+// CHECK-CXX-LABEL: @_Z21test_svaddha_za64_u64u10__SVBool_tu10__SVBool_tu12__SVUint64_t(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PN:%.*]])
+// CHECK-NEXT:[[TMP1:%.*]] = tail call  @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PM:%.*]])
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.addha.nxv2i64(i32 0,  [[TMP0]],  [[TMP1]],  [[ZN:%.*]])
+// CHECK-NEXT:ret void
+//
+ARM_STREAMING_ATTR void test_svaddha_za64_u64(svbool_t pn, svbool_t pm, svuint64_t zn) {
+  SME_ACLE_FUNC(svaddha_za64, _u64, _m)(0, pn, pm, zn);
+}
+
+// CHECK-C-LABEL: @test_svaddha_za64_u64_1(
+// CHECK-CXX-LABEL: @_Z23test_svaddha_za64_u64_1u10__SVBool_tu10__SVBool_tu12__SVUint64_t(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PN:%.*]])
+// CHECK-NEXT:[[TMP1:%.*]] = tail call  @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PM:%.*]])
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.addha.nxv2i64(i32 7,  [[TMP0]],  [[TMP1]],  [[ZN:%.*]])
+// CHECK-NEXT:ret void
+//
+ARM_STREAMING_ATTR void test_svaddha_za64_u64_1(svbool_t pn, svbool_t pm, svuint64_t zn) {
+  SME_ACLE_FUNC(svaddha_za64, _u64, _m)(7, pn, pm, zn);
+}
+
+// CHECK-C-LABEL: @test_svaddha_za64_s64(
+// CHECK-CXX-LABEL: @_Z21test_svaddha_za64_s64u10__SVBool_tu10__SVBool_tu11__SVInt64_t(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PN:%.*]])
+// CHECK-NEXT:[[TMP1:%.*]] = tail call  @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PM:%.*]])
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.addha.nxv2i64(i32 0,  [[TMP0]],  [[TMP1]],  [[ZN:%.*]])
+// CHECK-NEXT:ret void
+//
+ARM_STREAMING_ATTR void test_svaddha_za64_s64(svbool_t pn, svbool_t pm, svint64_t zn) {
+  SME_ACLE_FUNC(svaddha_za64, _s64, _m)(0, pn, pm, zn);
+}
+
+// CHECK-C-LABEL: @test_svaddha_za64_s64_1(
+// CHECK-CXX-LABEL: @_Z23test_svaddha_za64_s64_1u10__SVBool_tu10__SVBool_tu11__SVInt64_t(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PN:%.*]])
+// CHECK-NEXT:[[TMP1:%.*]] = tail call  @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PM:%.*]])
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.addha.nxv2i64(i32 7,  [[TMP0]],  [[TMP1]],  [[ZN:%.*]])
+// CHECK-NEXT:ret void
+//
+ARM_STREAMING_ATTR void test_svaddha_za64_s64_1(svbool_t pn, svbool_t pm, svint64_t zn) {
+  SME_ACLE_FUNC(svaddha_za64, _s64, _m)(7, pn, pm, zn);
+}
+
+// CHECK-C-LABEL: @test_svaddva_za64_u64(
+// CHECK-CXX-LABEL: @_Z21test_svaddva_za64_u64u10__SVBool_tu10__SVBool_tu12__SVUint64_t(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PN:%.*]])
+// CHECK-NEXT:[[TMP1:%.*]] = tail call  @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PM:%.*]])
+// CHECK-NEXT:  

[PATCH] D134679: [Clang][AArch64][SME] Add intrinsics for reading streaming vector length

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc updated this revision to Diff 526379.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134679/new/

https://reviews.llvm.org/D134679

Files:
  clang/include/clang/Basic/arm_sme.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_cnt.c


Index: clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_cnt.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_cnt.c
@@ -0,0 +1,46 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme 
-target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s 
-check-prefixes=CHECK,CHECK-C
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme 
-target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s 
-check-prefixes=CHECK,CHECK-CXX
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme 
-target-feature +sve -S -O1 -Werror -o /dev/null %s
+
+#include 
+
+// CHECK-C-LABEL: @test_svcntsb(
+// CHECK-CXX-LABEL: @_Z12test_svcntsbv(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 @llvm.aarch64.sme.cntsb()
+// CHECK-NEXT:ret i64 [[TMP0]]
+//
+uint64_t test_svcntsb() {
+  return svcntsb();
+}
+
+// CHECK-C-LABEL: @test_svcntsh(
+// CHECK-CXX-LABEL: @_Z12test_svcntshv(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 @llvm.aarch64.sme.cntsh()
+// CHECK-NEXT:ret i64 [[TMP0]]
+//
+uint64_t test_svcntsh() {
+  return svcntsh();
+}
+
+// CHECK-C-LABEL: @test_svcntsw(
+// CHECK-CXX-LABEL: @_Z12test_svcntswv(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 @llvm.aarch64.sme.cntsw()
+// CHECK-NEXT:ret i64 [[TMP0]]
+//
+uint64_t test_svcntsw() {
+  return svcntsw();
+}
+
+// CHECK-C-LABEL: @test_svcntsd(
+// CHECK-CXX-LABEL: @_Z12test_svcntsdv(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 @llvm.aarch64.sme.cntsd()
+// CHECK-NEXT:ret i64 [[TMP0]]
+//
+uint64_t test_svcntsd() {
+  return svcntsd();
+}
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -9923,6 +9923,7 @@
   getContext().GetBuiltinType(BuiltinID, Error, );
   assert(Error == ASTContext::GE_None && "Should not codegen an error");
 
+  llvm::Type *Ty = ConvertType(E->getType());
   llvm::SmallVector Ops;
   for (unsigned i = 0, e = E->getNumArgs(); i != e; i++) {
 if ((ICEArguments & (1 << i)) == 0)
@@ -9953,6 +9954,12 @@
 return EmitSMEZero(TypeFlags, Ops, Builtin->LLVMIntrinsic);
   else if (TypeFlags.isLoadReg() || TypeFlags.isStoreReg())
 return EmitSMELdrStr(TypeFlags, Ops, Builtin->LLVMIntrinsic);
+  else if (Builtin->LLVMIntrinsic != 0) {
+Function *F = CGM.getIntrinsic(Builtin->LLVMIntrinsic,
+   getSVEOverloadTypes(TypeFlags, Ty, Ops));
+Value *Call = Builder.CreateCall(F, Ops);
+return Call;
+  }
 
   /// Should not happen
   return nullptr;
Index: clang/include/clang/Basic/arm_sme.td
===
--- clang/include/clang/Basic/arm_sme.td
+++ clang/include/clang/Basic/arm_sme.td
@@ -135,3 +135,19 @@
   def SVZERO_ZA  : SInst<"svzero_za", "v", "", MergeNone, 
"aarch64_sme_zero",
  [IsZero, IsOverloadNone, IsStreamingCompatible, 
IsSharedZA]>;
 }
+
+
+// SME - Counting elements in a streaming vector
+
+multiclass ZACount {
+  let TargetGuard = "sme" in {
+def NAME : SInst<"sv" # n_suffix, "nv", "", MergeNone,
+  "aarch64_sme_" # n_suffix,
+  [IsOverloadNone, IsStreamingCompatible, IsPreservesZA]>;
+  }
+}
+
+defm SVCNTSB : ZACount<"cntsb">;
+defm SVCNTSH : ZACount<"cntsh">;
+defm SVCNTSW : ZACount<"cntsw">;
+defm SVCNTSD : ZACount<"cntsd">;


Index: clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_cnt.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_cnt.c
@@ -0,0 +1,46 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -o /dev/null %s
+
+#include 
+
+// CHECK-C-LABEL: @test_svcntsb(
+// CHECK-CXX-LABEL: @_Z12test_svcntsbv(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 

[PATCH] D134678: [Clang][AArch64][SME] Add intrinsics for ZA array load/store (LDR/STR)

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc updated this revision to Diff 526361.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134678/new/

https://reviews.llvm.org/D134678

Files:
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/Basic/arm_sme.td
  clang/include/clang/Basic/arm_sve_sme_incl.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ldr.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_str.c
  clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp

Index: clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
===
--- clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
+++ clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
@@ -185,6 +185,11 @@
   // expected-error@+1 {{argument value 16 is outside the valid range [0, 15]}}
   SVE_ACLE_FUNC(svst1_ver_vnum_za8,,,)(0, -1, 16, pg, ptr, 1);
 
+  // expected-error@+1 {{argument value 16 is outside the valid range [0, 15]}}
+  SVE_ACLE_FUNC(svldr_vnum_za,,,)(-1, 16, ptr);
+  // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 15]}}
+  SVE_ACLE_FUNC(svstr_vnum_za,,,)(-1, -1, ptr);
+
   // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 15]}}
   SVE_ACLE_FUNC(svread_hor_za128, _s8, _m,)(svundef_s8(), pg, -1, -1, 0);
   // expected-error@+1 {{argument value 16 is outside the valid range [0, 15]}}
@@ -222,6 +227,9 @@
   SVE_ACLE_FUNC(svst1_hor_vnum_za32,,,)(u64, u64, 0, pg, ptr, u64); // expected-error {{argument to 'svst1_hor_vnum_za32' must be a constant integer}}
   SVE_ACLE_FUNC(svst1_ver_vnum_za64,,,)(0, u64, u64, pg, ptr, u64); // expected-error {{argument to 'svst1_ver_vnum_za64' must be a constant integer}}
 
+  SVE_ACLE_FUNC(svldr_vnum_za,,,)(u64, u64, ptr); // expected-error {{argument to 'svldr_vnum_za' must be a constant integer}}
+  SVE_ACLE_FUNC(svstr_vnum_za,,,)(u64, u64, ptr); // expected-error {{argument to 'svstr_vnum_za' must be a constant integer}}
+
   SVE_ACLE_FUNC(svread_hor_za8, _s8, _m,)(svundef_s8(), pg, 0, u64, u64); // expected-error-re {{argument to 'svread_hor_za8{{.*}}_m' must be a constant integer}}
   SVE_ACLE_FUNC(svread_ver_za16, _s16, _m,)(svundef_s16(), pg, u64, u64, 0);  // expected-error-re {{argument to 'svread_ver_za16{{.*}}_m' must be a constant integer}}
   SVE_ACLE_FUNC(svwrite_hor_za32, _s32, _m,)(0, u64, u64, pg, svundef_s32()); // expected-error-re {{argument to 'svwrite_hor_za32{{.*}}_m' must be a constant integer}}
Index: clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_str.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_str.c
@@ -0,0 +1,29 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -o /dev/null %s
+
+#include 
+
+// CHECK-C-LABEL: @test_svstr_vnum_za(
+// CHECK-CXX-LABEL: @_Z18test_svstr_vnum_zajPv(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.str(i32 [[SLICE_BASE:%.*]], ptr [[PTR:%.*]])
+// CHECK-NEXT:ret void
+//
+void test_svstr_vnum_za(uint32_t slice_base, void *ptr) {
+  svstr_vnum_za(slice_base, 0, ptr);
+}
+
+// CHECK-C-LABEL: @test_svstr_vnum_za_1(
+// CHECK-CXX-LABEL: @_Z20test_svstr_vnum_za_1jPv(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[VSCALE:%.*]] = tail call i64 @llvm.vscale.i64()
+// CHECK-NEXT:[[MULVL:%.*]] = mul nuw nsw i64 [[VSCALE]], 240
+// CHECK-NEXT:[[TMP0:%.*]] = getelementptr i8, ptr [[PTR:%.*]], i64 [[MULVL]]
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.str(i32 [[SLICE_BASE:%.*]], ptr [[TMP0]])
+// CHECK-NEXT:ret void
+//
+void test_svstr_vnum_za_1(uint32_t slice_base, void *ptr) {
+  svstr_vnum_za(slice_base, 15, ptr);
+}
Index: clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ldr.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ldr.c
@@ -0,0 +1,29 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S 

[PATCH] D134677: [Clang][AArch64][SME] Add ZA zeroing intrinsics

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc updated this revision to Diff 526351.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134677/new/

https://reviews.llvm.org/D134677

Files:
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/Basic/arm_sme.td
  clang/include/clang/Basic/arm_sve_sme_incl.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_zero.c
  clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp

Index: clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
===
--- clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
+++ clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
@@ -203,6 +203,14 @@
   SVE_ACLE_FUNC(svwrite_ver_za8, _s8, _m,)(0, -1, 16, pg, svundef_s8());
 }
 
+ARM_STREAMING_ATTR
+void test_range_0_255(svbool_t pg, void *ptr) {
+  // expected-error@+1 {{argument value 256 is outside the valid range [0, 255]}}
+  SVE_ACLE_FUNC(svzero_mask_za,,,)(256);
+  // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 255]}}
+  SVE_ACLE_FUNC(svzero_mask_za,,,)(-1);
+}
+
 ARM_STREAMING_ATTR
 void test_constant(uint64_t u64, svbool_t pg, void *ptr) {
   SVE_ACLE_FUNC(svld1_hor_za8,,,)(u64, u64, 0, pg, ptr);  // expected-error {{argument to 'svld1_hor_za8' must be a constant integer}}
Index: clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_zero.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_zero.c
@@ -0,0 +1,46 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -o /dev/null %s
+
+#include 
+
+// CHECK-C-LABEL: @test_svzero_mask_za(
+// CHECK-CXX-LABEL: @_Z19test_svzero_mask_zav(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.zero(i32 0)
+// CHECK-NEXT:ret void
+//
+void test_svzero_mask_za() {
+  svzero_mask_za(0);
+}
+
+// CHECK-C-LABEL: @test_svzero_mask_za_1(
+// CHECK-CXX-LABEL: @_Z21test_svzero_mask_za_1v(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.zero(i32 176)
+// CHECK-NEXT:ret void
+//
+void test_svzero_mask_za_1() {
+  svzero_mask_za(176);
+}
+
+// CHECK-C-LABEL: @test_svzero_mask_za_2(
+// CHECK-CXX-LABEL: @_Z21test_svzero_mask_za_2v(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.zero(i32 255)
+// CHECK-NEXT:ret void
+//
+void test_svzero_mask_za_2() {
+  svzero_mask_za(255);
+}
+
+// CHECK-C-LABEL: @test_svzero_za(
+// CHECK-CXX-LABEL: @_Z14test_svzero_zav(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.zero(i32 255)
+// CHECK-NEXT:ret void
+//
+void test_svzero_za() {
+  svzero_za();
+}
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -2992,6 +2992,10 @@
   if (SemaBuiltinConstantArgRange(TheCall, ArgNum, 0, 15))
 HasError = true;
   break;
+case SVETypeFlags::ImmCheck0_255:
+  if (SemaBuiltinConstantArgRange(TheCall, ArgNum, 0, 255))
+HasError = true;
+  break;
 }
   }
 
Index: clang/lib/CodeGen/CodeGenFunction.h
===
--- clang/lib/CodeGen/CodeGenFunction.h
+++ clang/lib/CodeGen/CodeGenFunction.h
@@ -4267,6 +4267,9 @@
   llvm::Value *EmitSMEReadWrite(SVETypeFlags TypeFlags,
 llvm::SmallVectorImpl ,
 unsigned IntID);
+  llvm::Value *EmitSMEZero(SVETypeFlags TypeFlags,
+   llvm::SmallVectorImpl ,
+   unsigned IntID);
   llvm::Value *EmitAArch64SMEBuiltinExpr(unsigned BuiltinID, const CallExpr *E);
 
   llvm::Value *EmitAArch64BuiltinExpr(unsigned BuiltinID, const CallExpr *E,
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -9448,6 +9448,16 @@
   return Builder.CreateCall(F, Ops);
 }
 
+Value *CodeGenFunction::EmitSMEZero(SVETypeFlags TypeFlags,
+SmallVectorImpl ,
+unsigned IntID) {
+  // svzero_za() intrinsic zeros the entire za tile and has no paramters.
+  if (Ops.size() == 0)
+Ops.push_back(llvm::ConstantInt::get(Int32Ty, 255));
+  Function *F = 

[PATCH] D127910: [Clang][AArch64][SME] Add vector load/store (ld1/st1) intrinsics

[Bryan Chan via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG9f6250f59105: [Clang][AArch64][SME] Add vector load/store 
(ld1/st1) intrinsics (authored by bryanpkc).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D127910/new/

https://reviews.llvm.org/D127910

Files:
  clang/include/clang/Basic/BuiltinsAArch64.def
  clang/include/clang/Basic/BuiltinsARM.def
  clang/include/clang/Basic/BuiltinsNEON.def
  clang/include/clang/Basic/BuiltinsSME.def
  clang/include/clang/Basic/CMakeLists.txt
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/Basic/arm_sme.td
  clang/include/clang/Basic/arm_sve.td
  clang/include/clang/Basic/arm_sve_sme_incl.td
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Sema/SemaChecking.cpp
  clang/lib/Sema/SemaDeclAttr.cpp
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1_vnum.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1_vnum.c
  clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
  clang/test/Sema/aarch64-sme-intrinsics/acle_sme_target.c
  clang/utils/TableGen/SveEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h

Index: clang/utils/TableGen/TableGenBackends.h
===
--- clang/utils/TableGen/TableGenBackends.h
+++ clang/utils/TableGen/TableGenBackends.h
@@ -101,6 +101,11 @@
 void EmitSveTypeFlags(llvm::RecordKeeper , llvm::raw_ostream );
 void EmitSveRangeChecks(llvm::RecordKeeper , llvm::raw_ostream );
 
+void EmitSmeHeader(llvm::RecordKeeper , llvm::raw_ostream );
+void EmitSmeBuiltins(llvm::RecordKeeper , llvm::raw_ostream );
+void EmitSmeBuiltinCG(llvm::RecordKeeper , llvm::raw_ostream );
+void EmitSmeRangeChecks(llvm::RecordKeeper , llvm::raw_ostream );
+
 void EmitMveHeader(llvm::RecordKeeper , llvm::raw_ostream );
 void EmitMveBuiltinDef(llvm::RecordKeeper , llvm::raw_ostream );
 void EmitMveBuiltinSema(llvm::RecordKeeper , llvm::raw_ostream );
Index: clang/utils/TableGen/TableGen.cpp
===
--- clang/utils/TableGen/TableGen.cpp
+++ clang/utils/TableGen/TableGen.cpp
@@ -82,6 +82,10 @@
   GenArmSveBuiltinCG,
   GenArmSveTypeFlags,
   GenArmSveRangeChecks,
+  GenArmSmeHeader,
+  GenArmSmeBuiltins,
+  GenArmSmeBuiltinCG,
+  GenArmSmeRangeChecks,
   GenArmCdeHeader,
   GenArmCdeBuiltinDef,
   GenArmCdeBuiltinSema,
@@ -226,6 +230,14 @@
"Generate arm_sve_typeflags.inc for clang"),
 clEnumValN(GenArmSveRangeChecks, "gen-arm-sve-sema-rangechecks",
"Generate arm_sve_sema_rangechecks.inc for clang"),
+clEnumValN(GenArmSmeHeader, "gen-arm-sme-header",
+   "Generate arm_sme.h for clang"),
+clEnumValN(GenArmSmeBuiltins, "gen-arm-sme-builtins",
+   "Generate arm_sme_builtins.inc for clang"),
+clEnumValN(GenArmSmeBuiltinCG, "gen-arm-sme-builtin-codegen",
+   "Generate arm_sme_builtin_cg_map.inc for clang"),
+clEnumValN(GenArmSmeRangeChecks, "gen-arm-sme-sema-rangechecks",
+   "Generate arm_sme_sema_rangechecks.inc for clang"),
 clEnumValN(GenArmMveHeader, "gen-arm-mve-header",
"Generate arm_mve.h for clang"),
 clEnumValN(GenArmMveBuiltinDef, "gen-arm-mve-builtin-def",
@@ -454,6 +466,18 @@
   case GenArmSveRangeChecks:
 EmitSveRangeChecks(Records, OS);
 break;
+  case GenArmSmeHeader:
+EmitSmeHeader(Records, OS);
+break;
+  case GenArmSmeBuiltins:
+EmitSmeBuiltins(Records, OS);
+break;
+  case GenArmSmeBuiltinCG:
+EmitSmeBuiltinCG(Records, OS);
+break;
+  case GenArmSmeRangeChecks:
+EmitSmeRangeChecks(Records, OS);
+break;
   case GenArmCdeHeader:
 EmitCdeHeader(Records, OS);
 break;
Index: clang/utils/TableGen/SveEmitter.cpp
===
--- clang/utils/TableGen/SveEmitter.cpp
+++ clang/utils/TableGen/SveEmitter.cpp
@@ -228,7 +228,7 @@
   }
 
   /// Emits the intrinsic declaration to the ostream.
-  void emitIntrinsic(raw_ostream ) const;
+  void emitIntrinsic(raw_ostream , SVEEmitter ) const;
 
 private:
   std::string getMergeSuffix() const { return MergeSuffix; }
@@ -347,8 +347,21 @@
   /// Create the SVETypeFlags used in CGBuiltins
   void createTypeFlags(raw_ostream );
 
+  /// Emit arm_sme.h.
+  void createSMEHeader(raw_ostream );
+
+  /// Emit all the SME __builtin prototypes and code needed by Sema.
+  void createSMEBuiltins(raw_ostream );
+
+  /// Emit all the information needed to map builtin -> LLVM IR intrinsic.
+  void createSMECodeGenMap(raw_ostream );

[PATCH] D127910: [Clang][AArch64][SME] Add vector load/store (ld1/st1) intrinsics

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc added a comment.

@sdesmalen How does the latest version look to you? If you approve, I will land 
this and finish updating the rest of the patch series. One of the pre-merge 
builds failed for an unrelated reason, but other jobs were successful.


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[PATCH] D128648: [Clang][AArch64][SME] Add vector read/write (mova) intrinsics

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc added a comment.

Rebased on main, and removed dependence on the SME attributes patch as per 
https://reviews.llvm.org/D127910?vs=522039=522064#inline-1451681.


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[PATCH] D127910: [Clang][AArch64][SME] Add vector load/store (ld1/st1) intrinsics

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc updated this revision to Diff 522064.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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Files:
  clang/include/clang/Basic/BuiltinsAArch64.def
  clang/include/clang/Basic/BuiltinsARM.def
  clang/include/clang/Basic/BuiltinsNEON.def
  clang/include/clang/Basic/BuiltinsSME.def
  clang/include/clang/Basic/CMakeLists.txt
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/Basic/arm_sme.td
  clang/include/clang/Basic/arm_sve.td
  clang/include/clang/Basic/arm_sve_sme_incl.td
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Sema/SemaChecking.cpp
  clang/lib/Sema/SemaDeclAttr.cpp
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1_vnum.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1_vnum.c
  clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
  clang/test/Sema/aarch64-sme-intrinsics/acle_sme_target.c
  clang/utils/TableGen/SveEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h

Index: clang/utils/TableGen/TableGenBackends.h
===
--- clang/utils/TableGen/TableGenBackends.h
+++ clang/utils/TableGen/TableGenBackends.h
@@ -101,6 +101,11 @@
 void EmitSveTypeFlags(llvm::RecordKeeper , llvm::raw_ostream );
 void EmitSveRangeChecks(llvm::RecordKeeper , llvm::raw_ostream );
 
+void EmitSmeHeader(llvm::RecordKeeper , llvm::raw_ostream );
+void EmitSmeBuiltins(llvm::RecordKeeper , llvm::raw_ostream );
+void EmitSmeBuiltinCG(llvm::RecordKeeper , llvm::raw_ostream );
+void EmitSmeRangeChecks(llvm::RecordKeeper , llvm::raw_ostream );
+
 void EmitMveHeader(llvm::RecordKeeper , llvm::raw_ostream );
 void EmitMveBuiltinDef(llvm::RecordKeeper , llvm::raw_ostream );
 void EmitMveBuiltinSema(llvm::RecordKeeper , llvm::raw_ostream );
Index: clang/utils/TableGen/TableGen.cpp
===
--- clang/utils/TableGen/TableGen.cpp
+++ clang/utils/TableGen/TableGen.cpp
@@ -82,6 +82,10 @@
   GenArmSveBuiltinCG,
   GenArmSveTypeFlags,
   GenArmSveRangeChecks,
+  GenArmSmeHeader,
+  GenArmSmeBuiltins,
+  GenArmSmeBuiltinCG,
+  GenArmSmeRangeChecks,
   GenArmCdeHeader,
   GenArmCdeBuiltinDef,
   GenArmCdeBuiltinSema,
@@ -226,6 +230,14 @@
"Generate arm_sve_typeflags.inc for clang"),
 clEnumValN(GenArmSveRangeChecks, "gen-arm-sve-sema-rangechecks",
"Generate arm_sve_sema_rangechecks.inc for clang"),
+clEnumValN(GenArmSmeHeader, "gen-arm-sme-header",
+   "Generate arm_sme.h for clang"),
+clEnumValN(GenArmSmeBuiltins, "gen-arm-sme-builtins",
+   "Generate arm_sme_builtins.inc for clang"),
+clEnumValN(GenArmSmeBuiltinCG, "gen-arm-sme-builtin-codegen",
+   "Generate arm_sme_builtin_cg_map.inc for clang"),
+clEnumValN(GenArmSmeRangeChecks, "gen-arm-sme-sema-rangechecks",
+   "Generate arm_sme_sema_rangechecks.inc for clang"),
 clEnumValN(GenArmMveHeader, "gen-arm-mve-header",
"Generate arm_mve.h for clang"),
 clEnumValN(GenArmMveBuiltinDef, "gen-arm-mve-builtin-def",
@@ -454,6 +466,18 @@
   case GenArmSveRangeChecks:
 EmitSveRangeChecks(Records, OS);
 break;
+  case GenArmSmeHeader:
+EmitSmeHeader(Records, OS);
+break;
+  case GenArmSmeBuiltins:
+EmitSmeBuiltins(Records, OS);
+break;
+  case GenArmSmeBuiltinCG:
+EmitSmeBuiltinCG(Records, OS);
+break;
+  case GenArmSmeRangeChecks:
+EmitSmeRangeChecks(Records, OS);
+break;
   case GenArmCdeHeader:
 EmitCdeHeader(Records, OS);
 break;
Index: clang/utils/TableGen/SveEmitter.cpp
===
--- clang/utils/TableGen/SveEmitter.cpp
+++ clang/utils/TableGen/SveEmitter.cpp
@@ -228,7 +228,7 @@
   }
 
   /// Emits the intrinsic declaration to the ostream.
-  void emitIntrinsic(raw_ostream ) const;
+  void emitIntrinsic(raw_ostream , SVEEmitter ) const;
 
 private:
   std::string getMergeSuffix() const { return MergeSuffix; }
@@ -346,8 +346,21 @@
   /// Create the SVETypeFlags used in CGBuiltins
   void createTypeFlags(raw_ostream );
 
+  /// Emit arm_sme.h.
+  void createSMEHeader(raw_ostream );
+
+  /// Emit all the SME __builtin prototypes and code needed by Sema.
+  void createSMEBuiltins(raw_ostream );
+
+  /// Emit all the information needed to map builtin -> LLVM IR intrinsic.
+  void createSMECodeGenMap(raw_ostream );
+
+  /// Emit all the range checks for the immediates.
+  void createSMERangeChecks(raw_ostream );
+
   /// Create intrinsic and add it to \p Out
-  void createIntrinsic(Record *R, SmallVectorImpl> );
+  

[PATCH] D127910: [Clang][AArch64][SME] Add vector load/store (ld1/st1) intrinsics

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc updated this revision to Diff 522039.
bryanpkc edited the summary of this revision.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D127910/new/

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Files:
  clang/include/clang/Basic/BuiltinsNEON.def
  clang/include/clang/Basic/BuiltinsSME.def
  clang/include/clang/Basic/CMakeLists.txt
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/Basic/arm_sme.td
  clang/include/clang/Basic/arm_sve.td
  clang/include/clang/Basic/arm_sve_sme_incl.td
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Sema/SemaChecking.cpp
  clang/lib/Sema/SemaDeclAttr.cpp
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1_vnum.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1_vnum.c
  clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
  clang/test/Sema/aarch64-sme-intrinsics/acle_sme_target.c
  clang/utils/TableGen/SveEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h

Index: clang/utils/TableGen/TableGenBackends.h
===
--- clang/utils/TableGen/TableGenBackends.h
+++ clang/utils/TableGen/TableGenBackends.h
@@ -101,6 +101,11 @@
 void EmitSveTypeFlags(llvm::RecordKeeper , llvm::raw_ostream );
 void EmitSveRangeChecks(llvm::RecordKeeper , llvm::raw_ostream );
 
+void EmitSmeHeader(llvm::RecordKeeper , llvm::raw_ostream );
+void EmitSmeBuiltins(llvm::RecordKeeper , llvm::raw_ostream );
+void EmitSmeBuiltinCG(llvm::RecordKeeper , llvm::raw_ostream );
+void EmitSmeRangeChecks(llvm::RecordKeeper , llvm::raw_ostream );
+
 void EmitMveHeader(llvm::RecordKeeper , llvm::raw_ostream );
 void EmitMveBuiltinDef(llvm::RecordKeeper , llvm::raw_ostream );
 void EmitMveBuiltinSema(llvm::RecordKeeper , llvm::raw_ostream );
Index: clang/utils/TableGen/TableGen.cpp
===
--- clang/utils/TableGen/TableGen.cpp
+++ clang/utils/TableGen/TableGen.cpp
@@ -82,6 +82,10 @@
   GenArmSveBuiltinCG,
   GenArmSveTypeFlags,
   GenArmSveRangeChecks,
+  GenArmSmeHeader,
+  GenArmSmeBuiltins,
+  GenArmSmeBuiltinCG,
+  GenArmSmeRangeChecks,
   GenArmCdeHeader,
   GenArmCdeBuiltinDef,
   GenArmCdeBuiltinSema,
@@ -226,6 +230,14 @@
"Generate arm_sve_typeflags.inc for clang"),
 clEnumValN(GenArmSveRangeChecks, "gen-arm-sve-sema-rangechecks",
"Generate arm_sve_sema_rangechecks.inc for clang"),
+clEnumValN(GenArmSmeHeader, "gen-arm-sme-header",
+   "Generate arm_sme.h for clang"),
+clEnumValN(GenArmSmeBuiltins, "gen-arm-sme-builtins",
+   "Generate arm_sme_builtins.inc for clang"),
+clEnumValN(GenArmSmeBuiltinCG, "gen-arm-sme-builtin-codegen",
+   "Generate arm_sme_builtin_cg_map.inc for clang"),
+clEnumValN(GenArmSmeRangeChecks, "gen-arm-sme-sema-rangechecks",
+   "Generate arm_sme_sema_rangechecks.inc for clang"),
 clEnumValN(GenArmMveHeader, "gen-arm-mve-header",
"Generate arm_mve.h for clang"),
 clEnumValN(GenArmMveBuiltinDef, "gen-arm-mve-builtin-def",
@@ -454,6 +466,18 @@
   case GenArmSveRangeChecks:
 EmitSveRangeChecks(Records, OS);
 break;
+  case GenArmSmeHeader:
+EmitSmeHeader(Records, OS);
+break;
+  case GenArmSmeBuiltins:
+EmitSmeBuiltins(Records, OS);
+break;
+  case GenArmSmeBuiltinCG:
+EmitSmeBuiltinCG(Records, OS);
+break;
+  case GenArmSmeRangeChecks:
+EmitSmeRangeChecks(Records, OS);
+break;
   case GenArmCdeHeader:
 EmitCdeHeader(Records, OS);
 break;
Index: clang/utils/TableGen/SveEmitter.cpp
===
--- clang/utils/TableGen/SveEmitter.cpp
+++ clang/utils/TableGen/SveEmitter.cpp
@@ -228,7 +228,7 @@
   }
 
   /// Emits the intrinsic declaration to the ostream.
-  void emitIntrinsic(raw_ostream ) const;
+  void emitIntrinsic(raw_ostream , SVEEmitter ) const;
 
 private:
   std::string getMergeSuffix() const { return MergeSuffix; }
@@ -346,8 +346,21 @@
   /// Create the SVETypeFlags used in CGBuiltins
   void createTypeFlags(raw_ostream );
 
+  /// Emit arm_sme.h.
+  void createSMEHeader(raw_ostream );
+
+  /// Emit all the SME __builtin prototypes and code needed by Sema.
+  void createSMEBuiltins(raw_ostream );
+
+  /// Emit all the information needed to map builtin -> LLVM IR intrinsic.
+  void createSMECodeGenMap(raw_ostream );
+
+  /// Emit all the range checks for the immediates.
+  void createSMERangeChecks(raw_ostream );
+
   /// Create intrinsic and add it to \p Out
-  void createIntrinsic(Record *R, SmallVectorImpl> );
+  void createIntrinsic(Record *R,
+   

[PATCH] D127910: [Clang][AArch64][SME] Add vector load/store (ld1/st1) intrinsics

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc added inline comments.



Comment at: clang/lib/Basic/Targets/AArch64.cpp:726
 
-if (Feature == "+sme") {
-  HasSME = true;

sdesmalen wrote:
> Why did you remove this?
The `Feature == "+sme"` case is also handled below on line 782. Perhaps we 
should delete this block and add `HasFullFP16` below.



Comment at: clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1.c:16
+//
+__attribute__((arm_streaming)) void test_svld1_hor_za8(uint32_t slice_base, 
svbool_t pg, const void *ptr) {
+  svld1_hor_za8(0, slice_base, 0, pg, ptr);

sdesmalen wrote:
> Hi @bryanpkc, would you be happy to remove the dependence on the attributes 
> patch for now, so that we can move forward to review/land this patch series?
> 
> I'm thinking of doing something like:
> 
>   // RUN: %clang_cc1 -DDISABLE_SME_ATTRIBUTES 
>   ...
>   
>   #ifdef DISABLE_SME_ATTRIBUTES
>   #define ARM_STREAMING_ATTR
>   #else
>   #define ARM_STREAMING_ATTR __attribute__((arm_streaming))
>   #endif
>   
>   ...
>   
>   ARM_STREAMING_ATTR void test_svld1_hor_za16(uint32_t slice_base, svbool_t 
> pg, const void *ptr) {
> svld1_hor_za16(0, slice_base, 0, pg, ptr);
> svld1_hor_za16(1, slice_base, 7, pg, ptr);
>   }
> 
> With that the tests all pass, and when the attribute patches have landed we 
> can just remove the `-DDISABLE_SME_ATTRIBUTES` from the RUN lines.
Sounds good, I will give that a shot. If we can unblock this patch, I will also 
rebase and update the rest of the patch series. Thanks!


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[PATCH] D148211: [clang][tests] Fix Flang driver tests for Windows

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc added a comment.

> May I ask you to commit the change? I do not have commit access.

Done.


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[PATCH] D148211: [clang][tests] Fix Flang driver tests for Windows

[Bryan Chan via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG7b85bfffc486: [clang][tests] Fix Flang driver tests for 
Windows (authored by kaadam, committed by bryanpkc).

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Files:
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  clang/test/Driver/flang/flang_ucase.F90
  clang/test/Driver/flang/multiple-inputs.f90


Index: clang/test/Driver/flang/multiple-inputs.f90
===
--- clang/test/Driver/flang/multiple-inputs.f90
+++ clang/test/Driver/flang/multiple-inputs.f90
@@ -1,7 +1,7 @@
 ! Check that flang driver can handle multiple inputs at once.
 
 ! RUN: %clang --driver-mode=flang -### -fsyntax-only %S/Inputs/one.f90 
%S/Inputs/two.f90 2>&1 | FileCheck --check-prefixes=CHECK-SYNTAX-ONLY %s
-! CHECK-SYNTAX-ONLY-LABEL: "{{[^"]*}}flang-new" "-fc1"
+! CHECK-SYNTAX-ONLY-LABEL: "{{[^"]*}}flang-new{{[^"/]*}}" "-fc1"
 ! CHECK-SYNTAX-ONLY: "{{[^"]*}}/Inputs/one.f90"
-! CHECK-SYNTAX-ONLY-LABEL: "{{[^"]*}}flang-new" "-fc1"
+! CHECK-SYNTAX-ONLY-LABEL: "{{[^"]*}}flang-new{{[^"/]*}}" "-fc1"
 ! CHECK-SYNTAX-ONLY: "{{[^"]*}}/Inputs/two.f90"
Index: clang/test/Driver/flang/flang_ucase.F90
===
--- clang/test/Driver/flang/flang_ucase.F90
+++ clang/test/Driver/flang/flang_ucase.F90
@@ -13,7 +13,7 @@
 ! * (no type specified, resulting in an object file)
 
 ! All invocations should begin with flang -fc1, consume up to here.
-! ALL-LABEL: "{{[^"]*}}flang-new" "-fc1"
+! ALL-LABEL: "{{[^"]*}}flang-new{{[^"/]*}}" "-fc1"
 
 ! Check that f90 files are not treated as "previously preprocessed"
 ! ... in --driver-mode=flang.
Index: clang/test/Driver/flang/flang.f90
===
--- clang/test/Driver/flang/flang.f90
+++ clang/test/Driver/flang/flang.f90
@@ -13,7 +13,7 @@
 ! * (no type specified, resulting in an object file)
 
 ! All invocations should begin with flang -fc1, consume up to here.
-! ALL-LABEL: "{{[^"]*}}flang-new" "-fc1"
+! ALL-LABEL: "{{[^"]*}}flang-new{{[^"/]*}}" "-fc1"
 
 ! Check that f90 files are not treated as "previously preprocessed"
 ! ... in --driver-mode=flang.


Index: clang/test/Driver/flang/multiple-inputs.f90
===
--- clang/test/Driver/flang/multiple-inputs.f90
+++ clang/test/Driver/flang/multiple-inputs.f90
@@ -1,7 +1,7 @@
 ! Check that flang driver can handle multiple inputs at once.
 
 ! RUN: %clang --driver-mode=flang -### -fsyntax-only %S/Inputs/one.f90 %S/Inputs/two.f90 2>&1 | FileCheck --check-prefixes=CHECK-SYNTAX-ONLY %s
-! CHECK-SYNTAX-ONLY-LABEL: "{{[^"]*}}flang-new" "-fc1"
+! CHECK-SYNTAX-ONLY-LABEL: "{{[^"]*}}flang-new{{[^"/]*}}" "-fc1"
 ! CHECK-SYNTAX-ONLY: "{{[^"]*}}/Inputs/one.f90"
-! CHECK-SYNTAX-ONLY-LABEL: "{{[^"]*}}flang-new" "-fc1"
+! CHECK-SYNTAX-ONLY-LABEL: "{{[^"]*}}flang-new{{[^"/]*}}" "-fc1"
 ! CHECK-SYNTAX-ONLY: "{{[^"]*}}/Inputs/two.f90"
Index: clang/test/Driver/flang/flang_ucase.F90
===
--- clang/test/Driver/flang/flang_ucase.F90
+++ clang/test/Driver/flang/flang_ucase.F90
@@ -13,7 +13,7 @@
 ! * (no type specified, resulting in an object file)
 
 ! All invocations should begin with flang -fc1, consume up to here.
-! ALL-LABEL: "{{[^"]*}}flang-new" "-fc1"
+! ALL-LABEL: "{{[^"]*}}flang-new{{[^"/]*}}" "-fc1"
 
 ! Check that f90 files are not treated as "previously preprocessed"
 ! ... in --driver-mode=flang.
Index: clang/test/Driver/flang/flang.f90
===
--- clang/test/Driver/flang/flang.f90
+++ clang/test/Driver/flang/flang.f90
@@ -13,7 +13,7 @@
 ! * (no type specified, resulting in an object file)
 
 ! All invocations should begin with flang -fc1, consume up to here.
-! ALL-LABEL: "{{[^"]*}}flang-new" "-fc1"
+! ALL-LABEL: "{{[^"]*}}flang-new{{[^"/]*}}" "-fc1"
 
 ! Check that f90 files are not treated as "previously preprocessed"
 ! ... in --driver-mode=flang.
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[PATCH] D148211: [clang][tests] Fix Flang driver tests for Windows

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc accepted this revision.
bryanpkc added a comment.
This revision is now accepted and ready to land.

LGTM


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[PATCH] D148211: [clang][tests] Fix Flang driver tests for Windows

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc added a comment.

`clang/test/Driver/flang/multiple-inputs-mixed.f90` uses a more general 
FileCheck pattern:

  ! CHECK-SYNTAX-ONLY-LABEL: "{{[^"]*}}flang-new{{[^"/]*}}" "-fc1"

Perhaps these files should use the same regexp?


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[PATCH] D128648: [Clang][AArch64][SME] Add vector read/write (mova) intrinsics

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc added inline comments.



Comment at: clang/include/clang/Basic/arm_sme.td:103
+def NAME # _H : SInst<"svwrite_hor_" # n_suffix # "[_{d}]", "vimiPd", t, 
MergeOp1,
+  "aarch64_sme_write" # !cond(!eq(n_suffix, "za128") : 
"q", true: "") # "_horiz",
+  [IsWrite, IsStreaming, IsSharedZA], ch>;

kmclaughlin wrote:
> This is only a suggestion, but would it make the multiclasses simpler to just 
> pass in either `"q"` or `""` depending on the instruction, and append this to 
> `aarch64_sme_read/write`?
Thanks for the suggestion, but simplifying the definition at the cost of 
complicating the interface does not seem worthwhile. I think the current 
implementation is more self-documenting and clearer about the intent, and 
reduces the cognitive burden for a future reader, to whom the uses of `""` and 
`"q"` may not be obvious.



Comment at: clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_read.c:2
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme 
-target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s 
-check-prefixes=CHECK,CHECK-C
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme 
-target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s 
-check-prefixes=CHECK,CHECK-CXX

kmclaughlin wrote:
> I think `-target-feature +sve` can be removed from this test and 
> `acle_sme_write.c`
Doing that will cause errors like these:
```
error: SVE vector type 'svbool_t' (aka '__SVBool_t') cannot be used in a target 
without sve
```
As I have explained in [D127910](https://reviews.llvm.org/D127910#4137844), 
`-target-feature +sme` does not imply `-target-feature +sve`. But `-march=` 
processing will work as expected when D142702 lands.


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[PATCH] D127910: [Clang][AArch64][SME] Add vector load/store (ld1/st1) intrinsics

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc updated this revision to Diff 500638.
bryanpkc edited the summary of this revision.
bryanpkc added a comment.

Fix some bugs in the range checks of immediate operands.


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Files:
  clang/include/clang/Basic/BuiltinsNEON.def
  clang/include/clang/Basic/BuiltinsSME.def
  clang/include/clang/Basic/CMakeLists.txt
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/Basic/arm_sme.td
  clang/include/clang/Basic/arm_sve.td
  clang/include/clang/Basic/arm_sve_sme_incl.td
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Sema/SemaChecking.cpp
  clang/lib/Sema/SemaDeclAttr.cpp
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1_vnum.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1_vnum.c
  clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
  clang/test/Sema/aarch64-sme-intrinsics/acle_sme_target.c
  clang/utils/TableGen/SveEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h

Index: clang/utils/TableGen/TableGenBackends.h
===
--- clang/utils/TableGen/TableGenBackends.h
+++ clang/utils/TableGen/TableGenBackends.h
@@ -101,6 +101,11 @@
 void EmitSveTypeFlags(llvm::RecordKeeper , llvm::raw_ostream );
 void EmitSveRangeChecks(llvm::RecordKeeper , llvm::raw_ostream );
 
+void EmitSmeHeader(llvm::RecordKeeper , llvm::raw_ostream );
+void EmitSmeBuiltins(llvm::RecordKeeper , llvm::raw_ostream );
+void EmitSmeBuiltinCG(llvm::RecordKeeper , llvm::raw_ostream );
+void EmitSmeRangeChecks(llvm::RecordKeeper , llvm::raw_ostream );
+
 void EmitMveHeader(llvm::RecordKeeper , llvm::raw_ostream );
 void EmitMveBuiltinDef(llvm::RecordKeeper , llvm::raw_ostream );
 void EmitMveBuiltinSema(llvm::RecordKeeper , llvm::raw_ostream );
Index: clang/utils/TableGen/TableGen.cpp
===
--- clang/utils/TableGen/TableGen.cpp
+++ clang/utils/TableGen/TableGen.cpp
@@ -81,6 +81,10 @@
   GenArmSveBuiltinCG,
   GenArmSveTypeFlags,
   GenArmSveRangeChecks,
+  GenArmSmeHeader,
+  GenArmSmeBuiltins,
+  GenArmSmeBuiltinCG,
+  GenArmSmeRangeChecks,
   GenArmCdeHeader,
   GenArmCdeBuiltinDef,
   GenArmCdeBuiltinSema,
@@ -219,6 +223,14 @@
"Generate arm_sve_typeflags.inc for clang"),
 clEnumValN(GenArmSveRangeChecks, "gen-arm-sve-sema-rangechecks",
"Generate arm_sve_sema_rangechecks.inc for clang"),
+clEnumValN(GenArmSmeHeader, "gen-arm-sme-header",
+   "Generate arm_sme.h for clang"),
+clEnumValN(GenArmSmeBuiltins, "gen-arm-sme-builtins",
+   "Generate arm_sme_builtins.inc for clang"),
+clEnumValN(GenArmSmeBuiltinCG, "gen-arm-sme-builtin-codegen",
+   "Generate arm_sme_builtin_cg_map.inc for clang"),
+clEnumValN(GenArmSmeRangeChecks, "gen-arm-sme-sema-rangechecks",
+   "Generate arm_sme_sema_rangechecks.inc for clang"),
 clEnumValN(GenArmMveHeader, "gen-arm-mve-header",
"Generate arm_mve.h for clang"),
 clEnumValN(GenArmMveBuiltinDef, "gen-arm-mve-builtin-def",
@@ -438,6 +450,18 @@
   case GenArmSveRangeChecks:
 EmitSveRangeChecks(Records, OS);
 break;
+  case GenArmSmeHeader:
+EmitSmeHeader(Records, OS);
+break;
+  case GenArmSmeBuiltins:
+EmitSmeBuiltins(Records, OS);
+break;
+  case GenArmSmeBuiltinCG:
+EmitSmeBuiltinCG(Records, OS);
+break;
+  case GenArmSmeRangeChecks:
+EmitSmeRangeChecks(Records, OS);
+break;
   case GenArmCdeHeader:
 EmitCdeHeader(Records, OS);
 break;
Index: clang/utils/TableGen/SveEmitter.cpp
===
--- clang/utils/TableGen/SveEmitter.cpp
+++ clang/utils/TableGen/SveEmitter.cpp
@@ -228,7 +228,7 @@
   }
 
   /// Emits the intrinsic declaration to the ostream.
-  void emitIntrinsic(raw_ostream ) const;
+  void emitIntrinsic(raw_ostream , SVEEmitter ) const;
 
 private:
   std::string getMergeSuffix() const { return MergeSuffix; }
@@ -346,8 +346,21 @@
   /// Create the SVETypeFlags used in CGBuiltins
   void createTypeFlags(raw_ostream );
 
+  /// Emit arm_sme.h.
+  void createSMEHeader(raw_ostream );
+
+  /// Emit all the SME __builtin prototypes and code needed by Sema.
+  void createSMEBuiltins(raw_ostream );
+
+  /// Emit all the information needed to map builtin -> LLVM IR intrinsic.
+  void createSMECodeGenMap(raw_ostream );
+
+  /// Emit all the range checks for the immediates.
+  void createSMERangeChecks(raw_ostream );
+
   /// Create intrinsic and add it to \p Out
-  void 

[PATCH] D127910: [Clang][AArch64][SME] Add vector load/store (ld1/st1) intrinsics

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc updated this revision to Diff 500630.
bryanpkc added a comment.

Moved test case `acle_target_sme.c` into 
`clang/test/Sema/aarch64-sme-intrinsics/`.


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Files:
  clang/include/clang/Basic/BuiltinsNEON.def
  clang/include/clang/Basic/BuiltinsSME.def
  clang/include/clang/Basic/CMakeLists.txt
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/Basic/arm_sme.td
  clang/include/clang/Basic/arm_sve.td
  clang/include/clang/Basic/arm_sve_sme_incl.td
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Sema/SemaChecking.cpp
  clang/lib/Sema/SemaDeclAttr.cpp
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1_vnum.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1_vnum.c
  clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
  clang/test/Sema/aarch64-sme-intrinsics/acle_sme_target.c
  clang/utils/TableGen/SveEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h

Index: clang/utils/TableGen/TableGenBackends.h
===
--- clang/utils/TableGen/TableGenBackends.h
+++ clang/utils/TableGen/TableGenBackends.h
@@ -101,6 +101,11 @@
 void EmitSveTypeFlags(llvm::RecordKeeper , llvm::raw_ostream );
 void EmitSveRangeChecks(llvm::RecordKeeper , llvm::raw_ostream );
 
+void EmitSmeHeader(llvm::RecordKeeper , llvm::raw_ostream );
+void EmitSmeBuiltins(llvm::RecordKeeper , llvm::raw_ostream );
+void EmitSmeBuiltinCG(llvm::RecordKeeper , llvm::raw_ostream );
+void EmitSmeRangeChecks(llvm::RecordKeeper , llvm::raw_ostream );
+
 void EmitMveHeader(llvm::RecordKeeper , llvm::raw_ostream );
 void EmitMveBuiltinDef(llvm::RecordKeeper , llvm::raw_ostream );
 void EmitMveBuiltinSema(llvm::RecordKeeper , llvm::raw_ostream );
Index: clang/utils/TableGen/TableGen.cpp
===
--- clang/utils/TableGen/TableGen.cpp
+++ clang/utils/TableGen/TableGen.cpp
@@ -81,6 +81,10 @@
   GenArmSveBuiltinCG,
   GenArmSveTypeFlags,
   GenArmSveRangeChecks,
+  GenArmSmeHeader,
+  GenArmSmeBuiltins,
+  GenArmSmeBuiltinCG,
+  GenArmSmeRangeChecks,
   GenArmCdeHeader,
   GenArmCdeBuiltinDef,
   GenArmCdeBuiltinSema,
@@ -219,6 +223,14 @@
"Generate arm_sve_typeflags.inc for clang"),
 clEnumValN(GenArmSveRangeChecks, "gen-arm-sve-sema-rangechecks",
"Generate arm_sve_sema_rangechecks.inc for clang"),
+clEnumValN(GenArmSmeHeader, "gen-arm-sme-header",
+   "Generate arm_sme.h for clang"),
+clEnumValN(GenArmSmeBuiltins, "gen-arm-sme-builtins",
+   "Generate arm_sme_builtins.inc for clang"),
+clEnumValN(GenArmSmeBuiltinCG, "gen-arm-sme-builtin-codegen",
+   "Generate arm_sme_builtin_cg_map.inc for clang"),
+clEnumValN(GenArmSmeRangeChecks, "gen-arm-sme-sema-rangechecks",
+   "Generate arm_sme_sema_rangechecks.inc for clang"),
 clEnumValN(GenArmMveHeader, "gen-arm-mve-header",
"Generate arm_mve.h for clang"),
 clEnumValN(GenArmMveBuiltinDef, "gen-arm-mve-builtin-def",
@@ -438,6 +450,18 @@
   case GenArmSveRangeChecks:
 EmitSveRangeChecks(Records, OS);
 break;
+  case GenArmSmeHeader:
+EmitSmeHeader(Records, OS);
+break;
+  case GenArmSmeBuiltins:
+EmitSmeBuiltins(Records, OS);
+break;
+  case GenArmSmeBuiltinCG:
+EmitSmeBuiltinCG(Records, OS);
+break;
+  case GenArmSmeRangeChecks:
+EmitSmeRangeChecks(Records, OS);
+break;
   case GenArmCdeHeader:
 EmitCdeHeader(Records, OS);
 break;
Index: clang/utils/TableGen/SveEmitter.cpp
===
--- clang/utils/TableGen/SveEmitter.cpp
+++ clang/utils/TableGen/SveEmitter.cpp
@@ -228,7 +228,7 @@
   }
 
   /// Emits the intrinsic declaration to the ostream.
-  void emitIntrinsic(raw_ostream ) const;
+  void emitIntrinsic(raw_ostream , SVEEmitter ) const;
 
 private:
   std::string getMergeSuffix() const { return MergeSuffix; }
@@ -346,8 +346,21 @@
   /// Create the SVETypeFlags used in CGBuiltins
   void createTypeFlags(raw_ostream );
 
+  /// Emit arm_sme.h.
+  void createSMEHeader(raw_ostream );
+
+  /// Emit all the SME __builtin prototypes and code needed by Sema.
+  void createSMEBuiltins(raw_ostream );
+
+  /// Emit all the information needed to map builtin -> LLVM IR intrinsic.
+  void createSMECodeGenMap(raw_ostream );
+
+  /// Emit all the range checks for the immediates.
+  void createSMERangeChecks(raw_ostream );
+
   /// Create intrinsic and add it to \p Out
-  void createIntrinsic(Record *R, SmallVectorImpl> );
+  void 

[PATCH] D127762: [Clang][AArch64] Add ACLE attributes for SME.

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc added a comment.

@sdesmalen @rsandifo-arm @aaron.ballman @erichkeane What is the plan for this 
patch? Is it going to be abandoned in favor of D139028 
, or can it be landed in its current form 
after addressing all outstanding review comments?


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[PATCH] D127910: [Clang][AArch64][SME] Add vector load/store (ld1/st1) intrinsics

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc updated this revision to Diff 500578.
bryanpkc added a comment.

Removed `EltTypeBool128` as suggested.


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Files:
  clang/include/clang/Basic/BuiltinsNEON.def
  clang/include/clang/Basic/BuiltinsSME.def
  clang/include/clang/Basic/CMakeLists.txt
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/Basic/arm_sme.td
  clang/include/clang/Basic/arm_sve.td
  clang/include/clang/Basic/arm_sve_sme_incl.td
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Sema/SemaChecking.cpp
  clang/lib/Sema/SemaDeclAttr.cpp
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1_vnum.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1_vnum.c
  clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
  clang/test/Sema/aarch64-sme-target.c
  clang/utils/TableGen/SveEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h

Index: clang/utils/TableGen/TableGenBackends.h
===
--- clang/utils/TableGen/TableGenBackends.h
+++ clang/utils/TableGen/TableGenBackends.h
@@ -101,6 +101,11 @@
 void EmitSveTypeFlags(llvm::RecordKeeper , llvm::raw_ostream );
 void EmitSveRangeChecks(llvm::RecordKeeper , llvm::raw_ostream );
 
+void EmitSmeHeader(llvm::RecordKeeper , llvm::raw_ostream );
+void EmitSmeBuiltins(llvm::RecordKeeper , llvm::raw_ostream );
+void EmitSmeBuiltinCG(llvm::RecordKeeper , llvm::raw_ostream );
+void EmitSmeRangeChecks(llvm::RecordKeeper , llvm::raw_ostream );
+
 void EmitMveHeader(llvm::RecordKeeper , llvm::raw_ostream );
 void EmitMveBuiltinDef(llvm::RecordKeeper , llvm::raw_ostream );
 void EmitMveBuiltinSema(llvm::RecordKeeper , llvm::raw_ostream );
Index: clang/utils/TableGen/TableGen.cpp
===
--- clang/utils/TableGen/TableGen.cpp
+++ clang/utils/TableGen/TableGen.cpp
@@ -81,6 +81,10 @@
   GenArmSveBuiltinCG,
   GenArmSveTypeFlags,
   GenArmSveRangeChecks,
+  GenArmSmeHeader,
+  GenArmSmeBuiltins,
+  GenArmSmeBuiltinCG,
+  GenArmSmeRangeChecks,
   GenArmCdeHeader,
   GenArmCdeBuiltinDef,
   GenArmCdeBuiltinSema,
@@ -219,6 +223,14 @@
"Generate arm_sve_typeflags.inc for clang"),
 clEnumValN(GenArmSveRangeChecks, "gen-arm-sve-sema-rangechecks",
"Generate arm_sve_sema_rangechecks.inc for clang"),
+clEnumValN(GenArmSmeHeader, "gen-arm-sme-header",
+   "Generate arm_sme.h for clang"),
+clEnumValN(GenArmSmeBuiltins, "gen-arm-sme-builtins",
+   "Generate arm_sme_builtins.inc for clang"),
+clEnumValN(GenArmSmeBuiltinCG, "gen-arm-sme-builtin-codegen",
+   "Generate arm_sme_builtin_cg_map.inc for clang"),
+clEnumValN(GenArmSmeRangeChecks, "gen-arm-sme-sema-rangechecks",
+   "Generate arm_sme_sema_rangechecks.inc for clang"),
 clEnumValN(GenArmMveHeader, "gen-arm-mve-header",
"Generate arm_mve.h for clang"),
 clEnumValN(GenArmMveBuiltinDef, "gen-arm-mve-builtin-def",
@@ -438,6 +450,18 @@
   case GenArmSveRangeChecks:
 EmitSveRangeChecks(Records, OS);
 break;
+  case GenArmSmeHeader:
+EmitSmeHeader(Records, OS);
+break;
+  case GenArmSmeBuiltins:
+EmitSmeBuiltins(Records, OS);
+break;
+  case GenArmSmeBuiltinCG:
+EmitSmeBuiltinCG(Records, OS);
+break;
+  case GenArmSmeRangeChecks:
+EmitSmeRangeChecks(Records, OS);
+break;
   case GenArmCdeHeader:
 EmitCdeHeader(Records, OS);
 break;
Index: clang/utils/TableGen/SveEmitter.cpp
===
--- clang/utils/TableGen/SveEmitter.cpp
+++ clang/utils/TableGen/SveEmitter.cpp
@@ -228,7 +228,7 @@
   }
 
   /// Emits the intrinsic declaration to the ostream.
-  void emitIntrinsic(raw_ostream ) const;
+  void emitIntrinsic(raw_ostream , SVEEmitter ) const;
 
 private:
   std::string getMergeSuffix() const { return MergeSuffix; }
@@ -346,8 +346,21 @@
   /// Create the SVETypeFlags used in CGBuiltins
   void createTypeFlags(raw_ostream );
 
+  /// Emit arm_sme.h.
+  void createSMEHeader(raw_ostream );
+
+  /// Emit all the SME __builtin prototypes and code needed by Sema.
+  void createSMEBuiltins(raw_ostream );
+
+  /// Emit all the information needed to map builtin -> LLVM IR intrinsic.
+  void createSMECodeGenMap(raw_ostream );
+
+  /// Emit all the range checks for the immediates.
+  void createSMERangeChecks(raw_ostream );
+
   /// Create intrinsic and add it to \p Out
-  void createIntrinsic(Record *R, SmallVectorImpl> );
+  void createIntrinsic(Record *R,
+  

[PATCH] D127910: [Clang][AArch64][SME] Add vector load/store (ld1/st1) intrinsics

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc marked an inline comment as done.
bryanpkc added inline comments.



Comment at: clang/lib/CodeGen/CGBuiltin.cpp:8874
   case SVETypeFlags::EltTyBool64:
+  case SVETypeFlags::EltTyBool128:
 return Builder.getInt1Ty();

kmclaughlin wrote:
> Is it necessary to add an `EltTypeBool128`? I think the EmitSVEPredicateCast 
> call in EmitSMELd1St1 is creating a vector based on the memory element type 
> and not the predicate type?
You are right, `EltTypeBool128` is not used right now; I can remove it. When we 
started working on the pre-ACLE intrinsics in our downstream compiler, we were 
planning to add something like `svptrue_b128`, even though the hardware `PTRUE` 
instruction doesn't support the Q size specifier. It is still not clear to me 
how the ACLE wants users to create a predicate vector for a call to a `_za128` 
intrinsic.


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[PATCH] D127910: [Clang][AArch64][SME] Add vector load/store (ld1/st1) intrinsics

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc marked an inline comment as done.
bryanpkc added inline comments.



Comment at: clang/lib/Headers/CMakeLists.txt:332
+  # Generate arm_sme.h
+  clang_generate_header(-gen-arm-sme-header arm_sme.td arm_sme.h)
   # Generate arm_bf16.h

sdesmalen wrote:
> bryanpkc wrote:
> > bryanpkc wrote:
> > > sdesmalen wrote:
> > > > The ACLE specification is still in a draft (ALP) state, which means 
> > > > there may still be subject to significant changes. To avoid users from 
> > > > using this implementation with the expectation that their code is 
> > > > compliant going forward, it would be good to rename the header file to 
> > > > something that makes it very clear this feature is not yet ready to 
> > > > use. I'm thinking of something like 
> > > > `arm_sme_draft_spec_subject_to_change.h`. When the specification goes 
> > > > out of draft, we can rename it to `arm_sme.h`. Could you rename the 
> > > > file for now?
> > > Would something shorter like `arm_sme_draft.h` or 
> > > `arm_sme_experimental.h` suffice?
> > Renamed to `arm_sme_experimental.h`.
> While `arm_sme_experimental.h` is indeed shorter, it should be unequivocally 
> clear to the user that they shouldn't rely on the function prototypes defined 
> in this header file yet because the specification itself is not finalised. I 
> think that adding the `draft_spec_subject_to_change` to the name makes that 
> more clear than `experimental`, as the latter might suggest that the support 
> is not yet entirely stable or complete. There probably isn't that much to 
> gain from making the user experience better by using a shorter name, if the 
> whole point is to prevent people from using it for any production code. So 
> from that perspective, I still have a slight preference for 
> `arm_sme_draft_spec_subject_to_change.h`.
Renamed as suggested.



Comment at: clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp:3
+
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -triple aarch64-none-linux-gnu 
-target-feature +sve -target-feature +sme -fsyntax-only -verify 
-verify-ignore-unexpected=error %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -DSVE_OVERLOADED_FORMS -triple 
aarch64-none-linux-gnu -target-feature +sve -target-feature +sme -fsyntax-only 
-verify -verify-ignore-unexpected=error %s

david-arm wrote:
> I think you can remove the `-target-feature +sve` flags from the RUN lines 
> because `+sme` should imply that.
If I understand `llvm/lib/Target/AArch64/AArch64.td` and 
`clang/lib/Basic/Targets/AArch64.cpp` correctly, `-target-feature +sme` does 
not imply `-target-feature +sve`. I can remove the `-D__ARM_FEATURE_SME` though.

On the other hand, `-march=armv8+sme` will imply `-target-feature +sve`, which 
I have implemented in D142702.



Comment at: clang/utils/TableGen/SveEmitter.cpp:1477
+
+  OS << "#if !defined(__ARM_FEATURE_SME)\n";
+  OS << "#error \"SME support not enabled\"\n";

dmgreen wrote:
> bryanpkc wrote:
> > dmgreen wrote:
> > > We have been changing how the existing SVE and NEON instrinsics work a 
> > > little. There are some details in https://reviews.llvm.org/D131064. The 
> > > short version is it is best to not rely upon preprocessor macros, and 
> > > instead define the intrinsics so that they can be used if the right 
> > > target features are available. This allows us to do things like this 
> > > below, even without a -march that supports sme, and have them callable at 
> > > runtime under the right situations. We should be doing the same for SME.
> > > ```
> > > __attribute__((target("+sme")))
> > > void sme_func() {
> > >   somesmeintrinsics();
> > > }
> > > ```
> > I have refactored the SME intrinsics in a similar fashion. Could you 
> > confirm if I did it correctly?
> It looks OK - as far as I can see. It might be worth adding a test for it? 
> But otherwise it looks good. Thanks.
Added a test case.


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[PATCH] D127910: [Clang][AArch64][SME] Add vector load/store (ld1/st1) intrinsics

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc updated this revision to Diff 498700.
bryanpkc marked 2 inline comments as done and an inline comment as not done.
bryanpkc added a comment.

Addressed review comments.


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Files:
  clang/include/clang/Basic/BuiltinsNEON.def
  clang/include/clang/Basic/BuiltinsSME.def
  clang/include/clang/Basic/CMakeLists.txt
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/Basic/arm_sme.td
  clang/include/clang/Basic/arm_sve.td
  clang/include/clang/Basic/arm_sve_sme_incl.td
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Sema/SemaChecking.cpp
  clang/lib/Sema/SemaDeclAttr.cpp
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1_vnum.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1_vnum.c
  clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
  clang/test/Sema/aarch64-sme-target.c
  clang/utils/TableGen/SveEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h

Index: clang/utils/TableGen/TableGenBackends.h
===
--- clang/utils/TableGen/TableGenBackends.h
+++ clang/utils/TableGen/TableGenBackends.h
@@ -101,6 +101,11 @@
 void EmitSveTypeFlags(llvm::RecordKeeper , llvm::raw_ostream );
 void EmitSveRangeChecks(llvm::RecordKeeper , llvm::raw_ostream );
 
+void EmitSmeHeader(llvm::RecordKeeper , llvm::raw_ostream );
+void EmitSmeBuiltins(llvm::RecordKeeper , llvm::raw_ostream );
+void EmitSmeBuiltinCG(llvm::RecordKeeper , llvm::raw_ostream );
+void EmitSmeRangeChecks(llvm::RecordKeeper , llvm::raw_ostream );
+
 void EmitMveHeader(llvm::RecordKeeper , llvm::raw_ostream );
 void EmitMveBuiltinDef(llvm::RecordKeeper , llvm::raw_ostream );
 void EmitMveBuiltinSema(llvm::RecordKeeper , llvm::raw_ostream );
Index: clang/utils/TableGen/TableGen.cpp
===
--- clang/utils/TableGen/TableGen.cpp
+++ clang/utils/TableGen/TableGen.cpp
@@ -81,6 +81,10 @@
   GenArmSveBuiltinCG,
   GenArmSveTypeFlags,
   GenArmSveRangeChecks,
+  GenArmSmeHeader,
+  GenArmSmeBuiltins,
+  GenArmSmeBuiltinCG,
+  GenArmSmeRangeChecks,
   GenArmCdeHeader,
   GenArmCdeBuiltinDef,
   GenArmCdeBuiltinSema,
@@ -219,6 +223,14 @@
"Generate arm_sve_typeflags.inc for clang"),
 clEnumValN(GenArmSveRangeChecks, "gen-arm-sve-sema-rangechecks",
"Generate arm_sve_sema_rangechecks.inc for clang"),
+clEnumValN(GenArmSmeHeader, "gen-arm-sme-header",
+   "Generate arm_sme.h for clang"),
+clEnumValN(GenArmSmeBuiltins, "gen-arm-sme-builtins",
+   "Generate arm_sme_builtins.inc for clang"),
+clEnumValN(GenArmSmeBuiltinCG, "gen-arm-sme-builtin-codegen",
+   "Generate arm_sme_builtin_cg_map.inc for clang"),
+clEnumValN(GenArmSmeRangeChecks, "gen-arm-sme-sema-rangechecks",
+   "Generate arm_sme_sema_rangechecks.inc for clang"),
 clEnumValN(GenArmMveHeader, "gen-arm-mve-header",
"Generate arm_mve.h for clang"),
 clEnumValN(GenArmMveBuiltinDef, "gen-arm-mve-builtin-def",
@@ -438,6 +450,18 @@
   case GenArmSveRangeChecks:
 EmitSveRangeChecks(Records, OS);
 break;
+  case GenArmSmeHeader:
+EmitSmeHeader(Records, OS);
+break;
+  case GenArmSmeBuiltins:
+EmitSmeBuiltins(Records, OS);
+break;
+  case GenArmSmeBuiltinCG:
+EmitSmeBuiltinCG(Records, OS);
+break;
+  case GenArmSmeRangeChecks:
+EmitSmeRangeChecks(Records, OS);
+break;
   case GenArmCdeHeader:
 EmitCdeHeader(Records, OS);
 break;
Index: clang/utils/TableGen/SveEmitter.cpp
===
--- clang/utils/TableGen/SveEmitter.cpp
+++ clang/utils/TableGen/SveEmitter.cpp
@@ -228,7 +228,7 @@
   }
 
   /// Emits the intrinsic declaration to the ostream.
-  void emitIntrinsic(raw_ostream ) const;
+  void emitIntrinsic(raw_ostream , SVEEmitter ) const;
 
 private:
   std::string getMergeSuffix() const { return MergeSuffix; }
@@ -346,8 +346,21 @@
   /// Create the SVETypeFlags used in CGBuiltins
   void createTypeFlags(raw_ostream );
 
+  /// Emit arm_sme.h.
+  void createSMEHeader(raw_ostream );
+
+  /// Emit all the SME __builtin prototypes and code needed by Sema.
+  void createSMEBuiltins(raw_ostream );
+
+  /// Emit all the information needed to map builtin -> LLVM IR intrinsic.
+  void createSMECodeGenMap(raw_ostream );
+
+  /// Emit all the range checks for the immediates.
+  void createSMERangeChecks(raw_ostream );
+
   /// Create intrinsic and add it to \p Out
-  void createIntrinsic(Record *R, 

[PATCH] D127910: [Clang][AArch64][SME] Add vector load/store (ld1/st1) intrinsics

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc updated this revision to Diff 496976.
bryanpkc marked an inline comment as done.
bryanpkc added a comment.

Fixed minor bugs in the previous upload.


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Files:
  clang/include/clang/Basic/BuiltinsSME.def
  clang/include/clang/Basic/CMakeLists.txt
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/Basic/arm_sme.td
  clang/include/clang/Basic/arm_sve.td
  clang/include/clang/Basic/arm_sve_sme_incl.td
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Sema/SemaChecking.cpp
  clang/lib/Sema/SemaDeclAttr.cpp
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1_vnum.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1_vnum.c
  clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
  clang/utils/TableGen/SveEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h

Index: clang/utils/TableGen/TableGenBackends.h
===
--- clang/utils/TableGen/TableGenBackends.h
+++ clang/utils/TableGen/TableGenBackends.h
@@ -101,6 +101,11 @@
 void EmitSveTypeFlags(llvm::RecordKeeper , llvm::raw_ostream );
 void EmitSveRangeChecks(llvm::RecordKeeper , llvm::raw_ostream );
 
+void EmitSmeHeader(llvm::RecordKeeper , llvm::raw_ostream );
+void EmitSmeBuiltins(llvm::RecordKeeper , llvm::raw_ostream );
+void EmitSmeBuiltinCG(llvm::RecordKeeper , llvm::raw_ostream );
+void EmitSmeRangeChecks(llvm::RecordKeeper , llvm::raw_ostream );
+
 void EmitMveHeader(llvm::RecordKeeper , llvm::raw_ostream );
 void EmitMveBuiltinDef(llvm::RecordKeeper , llvm::raw_ostream );
 void EmitMveBuiltinSema(llvm::RecordKeeper , llvm::raw_ostream );
Index: clang/utils/TableGen/TableGen.cpp
===
--- clang/utils/TableGen/TableGen.cpp
+++ clang/utils/TableGen/TableGen.cpp
@@ -81,6 +81,10 @@
   GenArmSveBuiltinCG,
   GenArmSveTypeFlags,
   GenArmSveRangeChecks,
+  GenArmSmeHeader,
+  GenArmSmeBuiltins,
+  GenArmSmeBuiltinCG,
+  GenArmSmeRangeChecks,
   GenArmCdeHeader,
   GenArmCdeBuiltinDef,
   GenArmCdeBuiltinSema,
@@ -219,6 +223,14 @@
"Generate arm_sve_typeflags.inc for clang"),
 clEnumValN(GenArmSveRangeChecks, "gen-arm-sve-sema-rangechecks",
"Generate arm_sve_sema_rangechecks.inc for clang"),
+clEnumValN(GenArmSmeHeader, "gen-arm-sme-header",
+   "Generate arm_sme.h for clang"),
+clEnumValN(GenArmSmeBuiltins, "gen-arm-sme-builtins",
+   "Generate arm_sme_builtins.inc for clang"),
+clEnumValN(GenArmSmeBuiltinCG, "gen-arm-sme-builtin-codegen",
+   "Generate arm_sme_builtin_cg_map.inc for clang"),
+clEnumValN(GenArmSmeRangeChecks, "gen-arm-sme-sema-rangechecks",
+   "Generate arm_sme_sema_rangechecks.inc for clang"),
 clEnumValN(GenArmMveHeader, "gen-arm-mve-header",
"Generate arm_mve.h for clang"),
 clEnumValN(GenArmMveBuiltinDef, "gen-arm-mve-builtin-def",
@@ -438,6 +450,18 @@
   case GenArmSveRangeChecks:
 EmitSveRangeChecks(Records, OS);
 break;
+  case GenArmSmeHeader:
+EmitSmeHeader(Records, OS);
+break;
+  case GenArmSmeBuiltins:
+EmitSmeBuiltins(Records, OS);
+break;
+  case GenArmSmeBuiltinCG:
+EmitSmeBuiltinCG(Records, OS);
+break;
+  case GenArmSmeRangeChecks:
+EmitSmeRangeChecks(Records, OS);
+break;
   case GenArmCdeHeader:
 EmitCdeHeader(Records, OS);
 break;
Index: clang/utils/TableGen/SveEmitter.cpp
===
--- clang/utils/TableGen/SveEmitter.cpp
+++ clang/utils/TableGen/SveEmitter.cpp
@@ -228,7 +228,7 @@
   }
 
   /// Emits the intrinsic declaration to the ostream.
-  void emitIntrinsic(raw_ostream ) const;
+  void emitIntrinsic(raw_ostream , SVEEmitter ) const;
 
 private:
   std::string getMergeSuffix() const { return MergeSuffix; }
@@ -346,8 +346,21 @@
   /// Create the SVETypeFlags used in CGBuiltins
   void createTypeFlags(raw_ostream );
 
+  /// Emit arm_sme.h.
+  void createSMEHeader(raw_ostream );
+
+  /// Emit all the SME __builtin prototypes and code needed by Sema.
+  void createSMEBuiltins(raw_ostream );
+
+  /// Emit all the information needed to map builtin -> LLVM IR intrinsic.
+  void createSMECodeGenMap(raw_ostream );
+
+  /// Emit all the range checks for the immediates.
+  void createSMERangeChecks(raw_ostream );
+
   /// Create intrinsic and add it to \p Out
-  void createIntrinsic(Record *R, SmallVectorImpl> );
+  void createIntrinsic(Record *R,
+   SmallVectorImpl> );
 };
 
 } 

[PATCH] D127910: [Clang][AArch64][SME] Add vector load/store (ld1/st1) intrinsics

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc marked 5 inline comments as done.
bryanpkc added inline comments.



Comment at: clang/include/clang/Basic/arm_sme.td:22
+let TargetGuard = "sme" in {
+  def SVLD1_HOR_ZA8 : MInst<"svld1_hor_za8", "vimiPQ", "c", [IsLoad, 
IsOverloadNone, IsStreaming, IsSharedZA], MemEltTyDefault, 
"aarch64_sme_ld1b_horiz", [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, 
ImmCheck0_15>]>;
+  def SVLD1_HOR_ZA16 : MInst<"svld1_hor_za16", "vimiPQ", "s", [IsLoad, 
IsOverloadNone, IsStreaming, IsSharedZA], MemEltTyDefault, 
"aarch64_sme_ld1h_horiz", [ImmCheck<0, ImmCheck0_1>, ImmCheck<2, ImmCheck0_7>]>;

david-arm wrote:
> This is just a suggestion, but you could reduce the lines of code here if you 
> want by creating a multiclass that creates both the horizontal and vertical 
> variants for each size, i.e. something like
> 
>   multiclass MyMultiClass<..> {
> def NAME # _H : MInst<...>
> def NAME # _V : MInst<...>
>   }
> 
>   defm SVLD1_ZA8 : MyMultiClass<...>;
> 
> or whatever naming scheme you prefer, and same for the stores. Feel free to 
> ignore this suggestion though if it doesn't help you!
Thanks for the suggestion. Refactored.



Comment at: clang/lib/Headers/CMakeLists.txt:332
+  # Generate arm_sme.h
+  clang_generate_header(-gen-arm-sme-header arm_sme.td arm_sme.h)
   # Generate arm_bf16.h

bryanpkc wrote:
> sdesmalen wrote:
> > The ACLE specification is still in a draft (ALP) state, which means there 
> > may still be subject to significant changes. To avoid users from using this 
> > implementation with the expectation that their code is compliant going 
> > forward, it would be good to rename the header file to something that makes 
> > it very clear this feature is not yet ready to use. I'm thinking of 
> > something like `arm_sme_draft_spec_subject_to_change.h`. When the 
> > specification goes out of draft, we can rename it to `arm_sme.h`. Could you 
> > rename the file for now?
> Would something shorter like `arm_sme_draft.h` or `arm_sme_experimental.h` 
> suffice?
Renamed to `arm_sme_experimental.h`.


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[PATCH] D127910: [Clang][AArch64][SME] Add vector load/store (ld1/st1) intrinsics

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc updated this revision to Diff 496964.
bryanpkc edited the summary of this revision.
bryanpkc added a comment.

Addressed review comments.


Repository:
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Files:
  clang/include/clang/Basic/BuiltinsSME.def
  clang/include/clang/Basic/CMakeLists.txt
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/Basic/arm_sme.td
  clang/include/clang/Basic/arm_sve.td
  clang/include/clang/Basic/arm_sve_sme_incl.td
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Sema/SemaChecking.cpp
  clang/lib/Sema/SemaDeclAttr.cpp
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1_vnum.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1_vnum.c
  clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
  clang/utils/TableGen/SveEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h

Index: clang/utils/TableGen/TableGenBackends.h
===
--- clang/utils/TableGen/TableGenBackends.h
+++ clang/utils/TableGen/TableGenBackends.h
@@ -101,6 +101,11 @@
 void EmitSveTypeFlags(llvm::RecordKeeper , llvm::raw_ostream );
 void EmitSveRangeChecks(llvm::RecordKeeper , llvm::raw_ostream );
 
+void EmitSmeHeader(llvm::RecordKeeper , llvm::raw_ostream );
+void EmitSmeBuiltins(llvm::RecordKeeper , llvm::raw_ostream );
+void EmitSmeBuiltinCG(llvm::RecordKeeper , llvm::raw_ostream );
+void EmitSmeRangeChecks(llvm::RecordKeeper , llvm::raw_ostream );
+
 void EmitMveHeader(llvm::RecordKeeper , llvm::raw_ostream );
 void EmitMveBuiltinDef(llvm::RecordKeeper , llvm::raw_ostream );
 void EmitMveBuiltinSema(llvm::RecordKeeper , llvm::raw_ostream );
Index: clang/utils/TableGen/TableGen.cpp
===
--- clang/utils/TableGen/TableGen.cpp
+++ clang/utils/TableGen/TableGen.cpp
@@ -81,6 +81,10 @@
   GenArmSveBuiltinCG,
   GenArmSveTypeFlags,
   GenArmSveRangeChecks,
+  GenArmSmeHeader,
+  GenArmSmeBuiltins,
+  GenArmSmeBuiltinCG,
+  GenArmSmeRangeChecks,
   GenArmCdeHeader,
   GenArmCdeBuiltinDef,
   GenArmCdeBuiltinSema,
@@ -219,6 +223,14 @@
"Generate arm_sve_typeflags.inc for clang"),
 clEnumValN(GenArmSveRangeChecks, "gen-arm-sve-sema-rangechecks",
"Generate arm_sve_sema_rangechecks.inc for clang"),
+clEnumValN(GenArmSmeHeader, "gen-arm-sme-header",
+   "Generate arm_sme.h for clang"),
+clEnumValN(GenArmSmeBuiltins, "gen-arm-sme-builtins",
+   "Generate arm_sme_builtins.inc for clang"),
+clEnumValN(GenArmSmeBuiltinCG, "gen-arm-sme-builtin-codegen",
+   "Generate arm_sme_builtin_cg_map.inc for clang"),
+clEnumValN(GenArmSmeRangeChecks, "gen-arm-sme-sema-rangechecks",
+   "Generate arm_sme_sema_rangechecks.inc for clang"),
 clEnumValN(GenArmMveHeader, "gen-arm-mve-header",
"Generate arm_mve.h for clang"),
 clEnumValN(GenArmMveBuiltinDef, "gen-arm-mve-builtin-def",
@@ -438,6 +450,18 @@
   case GenArmSveRangeChecks:
 EmitSveRangeChecks(Records, OS);
 break;
+  case GenArmSmeHeader:
+EmitSmeHeader(Records, OS);
+break;
+  case GenArmSmeBuiltins:
+EmitSmeBuiltins(Records, OS);
+break;
+  case GenArmSmeBuiltinCG:
+EmitSmeBuiltinCG(Records, OS);
+break;
+  case GenArmSmeRangeChecks:
+EmitSmeRangeChecks(Records, OS);
+break;
   case GenArmCdeHeader:
 EmitCdeHeader(Records, OS);
 break;
Index: clang/utils/TableGen/SveEmitter.cpp
===
--- clang/utils/TableGen/SveEmitter.cpp
+++ clang/utils/TableGen/SveEmitter.cpp
@@ -228,7 +228,7 @@
   }
 
   /// Emits the intrinsic declaration to the ostream.
-  void emitIntrinsic(raw_ostream ) const;
+  void emitIntrinsic(raw_ostream , SVEEmitter ) const;
 
 private:
   std::string getMergeSuffix() const { return MergeSuffix; }
@@ -346,8 +346,21 @@
   /// Create the SVETypeFlags used in CGBuiltins
   void createTypeFlags(raw_ostream );
 
+  /// Emit arm_sme.h.
+  void createSMEHeader(raw_ostream );
+
+  /// Emit all the SME __builtin prototypes and code needed by Sema.
+  void createSMEBuiltins(raw_ostream );
+
+  /// Emit all the information needed to map builtin -> LLVM IR intrinsic.
+  void createSMECodeGenMap(raw_ostream );
+
+  /// Emit all the range checks for the immediates.
+  void createSMERangeChecks(raw_ostream );
+
   /// Create intrinsic and add it to \p Out
-  void createIntrinsic(Record *R, SmallVectorImpl> );
+  void createIntrinsic(Record *R,
+   SmallVectorImpl> );
 };
 
 } // end 

[PATCH] D127910: [Clang][AArch64][SME] Add vector load/store (ld1/st1) intrinsics

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc added inline comments.



Comment at: clang/lib/Headers/CMakeLists.txt:332
+  # Generate arm_sme.h
+  clang_generate_header(-gen-arm-sme-header arm_sme.td arm_sme.h)
   # Generate arm_bf16.h

sdesmalen wrote:
> The ACLE specification is still in a draft (ALP) state, which means there may 
> still be subject to significant changes. To avoid users from using this 
> implementation with the expectation that their code is compliant going 
> forward, it would be good to rename the header file to something that makes 
> it very clear this feature is not yet ready to use. I'm thinking of something 
> like `arm_sme_draft_spec_subject_to_change.h`. When the specification goes 
> out of draft, we can rename it to `arm_sme.h`. Could you rename the file for 
> now?
Would something shorter like `arm_sme_draft.h` or `arm_sme_experimental.h` 
suffice?


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[PATCH] D127910: [Clang][AArch64][SME] Add vector load/store (ld1/st1) intrinsics

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc updated this revision to Diff 495592.
bryanpkc marked 4 inline comments as done.
bryanpkc added a comment.

Rebased on trunk and addressed review comments.


Repository:
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Files:
  clang/include/clang/Basic/BuiltinsSME.def
  clang/include/clang/Basic/CMakeLists.txt
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/Basic/arm_sme.td
  clang/include/clang/Basic/arm_sve.td
  clang/include/clang/Basic/arm_sve_sme_incl.td
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Sema/SemaChecking.cpp
  clang/lib/Sema/SemaDeclAttr.cpp
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1_vnum.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1_vnum.c
  clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
  clang/utils/TableGen/SveEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h

Index: clang/utils/TableGen/TableGenBackends.h
===
--- clang/utils/TableGen/TableGenBackends.h
+++ clang/utils/TableGen/TableGenBackends.h
@@ -101,6 +101,11 @@
 void EmitSveTypeFlags(llvm::RecordKeeper , llvm::raw_ostream );
 void EmitSveRangeChecks(llvm::RecordKeeper , llvm::raw_ostream );
 
+void EmitSmeHeader(llvm::RecordKeeper , llvm::raw_ostream );
+void EmitSmeBuiltins(llvm::RecordKeeper , llvm::raw_ostream );
+void EmitSmeBuiltinCG(llvm::RecordKeeper , llvm::raw_ostream );
+void EmitSmeRangeChecks(llvm::RecordKeeper , llvm::raw_ostream );
+
 void EmitMveHeader(llvm::RecordKeeper , llvm::raw_ostream );
 void EmitMveBuiltinDef(llvm::RecordKeeper , llvm::raw_ostream );
 void EmitMveBuiltinSema(llvm::RecordKeeper , llvm::raw_ostream );
Index: clang/utils/TableGen/TableGen.cpp
===
--- clang/utils/TableGen/TableGen.cpp
+++ clang/utils/TableGen/TableGen.cpp
@@ -81,6 +81,10 @@
   GenArmSveBuiltinCG,
   GenArmSveTypeFlags,
   GenArmSveRangeChecks,
+  GenArmSmeHeader,
+  GenArmSmeBuiltins,
+  GenArmSmeBuiltinCG,
+  GenArmSmeRangeChecks,
   GenArmCdeHeader,
   GenArmCdeBuiltinDef,
   GenArmCdeBuiltinSema,
@@ -219,6 +223,14 @@
"Generate arm_sve_typeflags.inc for clang"),
 clEnumValN(GenArmSveRangeChecks, "gen-arm-sve-sema-rangechecks",
"Generate arm_sve_sema_rangechecks.inc for clang"),
+clEnumValN(GenArmSmeHeader, "gen-arm-sme-header",
+   "Generate arm_sme.h for clang"),
+clEnumValN(GenArmSmeBuiltins, "gen-arm-sme-builtins",
+   "Generate arm_sme_builtins.inc for clang"),
+clEnumValN(GenArmSmeBuiltinCG, "gen-arm-sme-builtin-codegen",
+   "Generate arm_sme_builtin_cg_map.inc for clang"),
+clEnumValN(GenArmSmeRangeChecks, "gen-arm-sme-sema-rangechecks",
+   "Generate arm_sme_sema_rangechecks.inc for clang"),
 clEnumValN(GenArmMveHeader, "gen-arm-mve-header",
"Generate arm_mve.h for clang"),
 clEnumValN(GenArmMveBuiltinDef, "gen-arm-mve-builtin-def",
@@ -438,6 +450,18 @@
   case GenArmSveRangeChecks:
 EmitSveRangeChecks(Records, OS);
 break;
+  case GenArmSmeHeader:
+EmitSmeHeader(Records, OS);
+break;
+  case GenArmSmeBuiltins:
+EmitSmeBuiltins(Records, OS);
+break;
+  case GenArmSmeBuiltinCG:
+EmitSmeBuiltinCG(Records, OS);
+break;
+  case GenArmSmeRangeChecks:
+EmitSmeRangeChecks(Records, OS);
+break;
   case GenArmCdeHeader:
 EmitCdeHeader(Records, OS);
 break;
Index: clang/utils/TableGen/SveEmitter.cpp
===
--- clang/utils/TableGen/SveEmitter.cpp
+++ clang/utils/TableGen/SveEmitter.cpp
@@ -228,7 +228,7 @@
   }
 
   /// Emits the intrinsic declaration to the ostream.
-  void emitIntrinsic(raw_ostream ) const;
+  void emitIntrinsic(raw_ostream , SVEEmitter ) const;
 
 private:
   std::string getMergeSuffix() const { return MergeSuffix; }
@@ -346,8 +346,21 @@
   /// Create the SVETypeFlags used in CGBuiltins
   void createTypeFlags(raw_ostream );
 
+  /// Emit arm_sme.h.
+  void createSMEHeader(raw_ostream );
+
+  /// Emit all the SME __builtin prototypes and code needed by Sema.
+  void createSMEBuiltins(raw_ostream );
+
+  /// Emit all the information needed to map builtin -> LLVM IR intrinsic.
+  void createSMECodeGenMap(raw_ostream );
+
+  /// Emit all the range checks for the immediates.
+  void createSMERangeChecks(raw_ostream );
+
   /// Create intrinsic and add it to \p Out
-  void createIntrinsic(Record *R, SmallVectorImpl> );
+  void createIntrinsic(Record *R,
+   SmallVectorImpl> );
 

[PATCH] D127910: [Clang][AArch64][SME] Add vector load/store (ld1/st1) intrinsics

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc marked 9 inline comments as done.
bryanpkc added inline comments.



Comment at: clang/include/clang/Basic/TargetBuiltins.h:312
+  /// Flags to identify the types for overloaded SME builtins.
+  class SMETypeFlags {
+uint64_t Flags;

david-arm wrote:
> I actually don't think you need to add this class - we should be able to just 
> reuse the existing SVETypeFlags structure. I think this is fine because 
> you've commonised the flags between SME and SVE.
Thanks for the suggestion. I have removed this class.



Comment at: clang/include/clang/Basic/arm_sme.td:21
+
+def SVLD1_HOR_ZA8 : MInst<"svld1_hor_za8", "vimiPQ", "c", [IsLoad, 
IsOverloadNone, IsStreaming, IsSharedZA], MemEltTyDefault, 
"aarch64_sme_ld1b_horiz">;
+def SVLD1_HOR_ZA16 : MInst<"svld1_hor_za16", "vimiPQ", "s", [IsLoad, 
IsOverloadNone, IsStreaming, IsSharedZA], MemEltTyDefault, 
"aarch64_sme_ld1h_horiz">;

david-arm wrote:
> I think all the load and store instructions need immediate checks for the 
> tile and slice_offset here such as:
> 
> [ImmCheck<0, ImmCheck0>, ImmCheck<2, ImmCheck0_15>]
> 
> for SVLD1_HOR_ZA8 and the others. It's mentioned in the ACLE - 
> https://arm-software.github.io/acle/main/acle.html#sme-language-extensions-and-intrinsics:
> 
>   15.4.3.1 Common Rules
> 
>   ...
>   Every argument named tile, slice_offset or tile_mask must be an integer 
> constant expression in the range of the underlying instruction.
> 
Done.



Comment at: clang/include/clang/Basic/arm_sve_sme_incl.td:126
+// Z: const pointer to uint64_t
+
+class MergeType {

david-arm wrote:
> Please can you add a comment here for the new Prototype modifier you added - 
> '%'?
A comment for '%' already exists on line 103.



Comment at: clang/lib/Basic/Targets/AArch64.cpp:438
 
+  if (HasSME)
+Builder.defineMacro("__ARM_FEATURE_SME", "1");

david-arm wrote:
> Can you remove this please? We can't really set this macro until the SME ABI 
> and ACLE is feature complete.
OK. Could you educate me what else is needed for SME ABI and ACLE to be 
feature-complete? How can I help?



Comment at: 
clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_int_const_expr_error.c:5
+
+__attribute__((arm_streaming)) void test_svld1_hor_za8(uint64_t tile, uint32_t 
slice_base, uint64_t slice_offset, svbool_t pg, void *ptr) {
+  svld1_hor_za8(tile, slice_base, 0, pg, ptr);  // expected-error 
{{argument to 'svld1_hor_za8' must be a constant integer}}

david-arm wrote:
> Once you've added the immediate range checks for the loads and stores it 
> would be good add checks here for immediates outside the range for each 
> instruction.
Done, thanks for the suggestion. I have also moved these tests into 
`clang/test/Sema/arm-sme-intrinsics/`.



Comment at: clang/utils/TableGen/SveEmitter.cpp:1477
+
+  OS << "#if !defined(__ARM_FEATURE_SME)\n";
+  OS << "#error \"SME support not enabled\"\n";

dmgreen wrote:
> We have been changing how the existing SVE and NEON instrinsics work a 
> little. There are some details in https://reviews.llvm.org/D131064. The short 
> version is it is best to not rely upon preprocessor macros, and instead 
> define the intrinsics so that they can be used if the right target features 
> are available. This allows us to do things like this below, even without a 
> -march that supports sme, and have them callable at runtime under the right 
> situations. We should be doing the same for SME.
> ```
> __attribute__((target("+sme")))
> void sme_func() {
>   somesmeintrinsics();
> }
> ```
I have refactored the SME intrinsics in a similar fashion. Could you confirm if 
I did it correctly?


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[PATCH] D142702: [Clang][AArch64][SME] Generate target features from +(no)sme.* options

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc created this revision.
bryanpkc added reviewers: sdesmalen, rsandifo-arm, david-arm.
Herald added a subscriber: kristof.beyls.
Herald added a project: All.
bryanpkc requested review of this revision.
Herald added subscribers: cfe-commits, MaskRay.
Herald added a project: clang.

Repository:
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https://reviews.llvm.org/D142702

Files:
  clang/lib/Driver/ToolChains/Arch/AArch64.cpp
  clang/test/Driver/aarch64-implied-sme-features.c

Index: clang/test/Driver/aarch64-implied-sme-features.c
===
--- /dev/null
+++ clang/test/Driver/aarch64-implied-sme-features.c
@@ -0,0 +1,55 @@
+// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sme %s -### 2>&1 | FileCheck %s --check-prefix=SME-IMPLY
+// SME-IMPLY: "-target-feature" "+sme" "-target-feature" "+sve" "-target-feature" "+sve2" "-target-feature" "+bf16"
+
+// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+nosme %s -### 2>&1 | FileCheck %s --check-prefix=NOSME
+// NOSME: "-target-feature" "-sme"
+
+// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sme+nosme %s -### 2>&1 | FileCheck %s --check-prefix=SME-REVERT
+// SME-REVERT-NOT: "-target-feature" "+sme"
+// SME-REVERT: "-target-feature" "+sve" "-target-feature" "+sve2" "-target-feature" "+bf16" "-target-feature" "-sme" "-target-feature" "-sme-f64f64" "-target-feature" "-sme-i16i64"
+
+// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sme+nosve %s -### 2>&1 | FileCheck %s --check-prefix=SME-CONFLICT
+// SME-CONFLICT: "-target-feature" "-sve" "-target-feature" "-sve2" "-target-feature" "-sve2-bitperm" "-target-feature" "-sve2-sha3" "-target-feature" "-sve2-aes" "-target-feature" "-sve2-sm4" "-target-feature" "-sme"
+
+// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sme+sve %s -### 2>&1 | FileCheck %s --check-prefix=SME-SVE
+// SME-SVE: "-target-feature" "+sme" "-target-feature" "+sve2" "-target-feature" "+bf16" "-target-feature" "+sve"
+
+// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sme-i16i64 %s -### 2>&1 | FileCheck %s --check-prefix=SME-I16I64
+// SME-I16I64: "-target-feature" "+sme-i16i64" "-target-feature" "+sme" "-target-feature" "+sve" "-target-feature" "+sve2" "-target-feature" "+bf16"
+
+// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+nosme-i16i64 %s -### 2>&1 | FileCheck %s --check-prefix=NOSME-I16I64
+// NOSME-I16I64-NOT: "-target-feature" "+sme-i16i64"
+// NOSME-I16I64-NOT: "-target-feature" "+sme"
+// NOSME-I16I64-NOT: "-target-feature" "+sve"
+// NOSME-I16I64-NOT: "-target-feature" "+sve2"
+// NOSME-I16I64-NOT: "-target-feature" "+bf16"
+// NOSME-I16I64: "-target-feature" "-sme-i16i64"
+
+// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sme-i16i64+nosme-i16i64 %s -### 2>&1 | FileCheck %s --check-prefix=SME-I16I64-REVERT
+// SME-I16I64-REVERT: "-target-feature" "+sme" "-target-feature" "+sve" "-target-feature" "+sve2" "-target-feature" "+bf16" "-target-feature" "-sme-i16i64"
+
+// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+nosme-f64f64 %s -### 2>&1 | FileCheck %s --check-prefix=NOSME-F64F64
+// NOSME-F64F64-NOT: "-target-feature" "+sme-f64f64"
+// NOSME-F64F64-NOT: "-target-feature" "+sme"
+// NOSME-F64F64-NOT: "-target-feature" "+sve"
+// NOSME-F64F64-NOT: "-target-feature" "+sve2"
+// NOSME-F64F64-NOT: "-target-feature" "+bf16"
+// NOSME-F64F64: "-target-feature" "-sme-f64f64"
+
+// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sme-f64f64+nosme-f64f64 %s -### 2>&1 | FileCheck %s --check-prefix=SME-F64F64-REVERT
+// SME-F64F64-REVERT: "-target-feature" "+sme" "-target-feature" "+sve" "-target-feature" "+sve2" "-target-feature" "+bf16" "-target-feature" "-sme-f64f64"
+
+// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sme-f64f64+nosme-i16i64 %s -### 2>&1 | FileCheck %s --check-prefix=SME-SUBFEATURE-MIX
+// SME-SUBFEATURE-MIX: "-target-feature" "+sme-f64f64" "-target-feature" "+sme" "-target-feature" "+sve" "-target-feature" "+sve2" "-target-feature" "+bf16" "-target-feature" "-sme-i16i64"
+
+// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sme-i16i64+nosme %s -### 2>&1 | FileCheck %s --check-prefix=SME-SUBFEATURE-CONFLICT
+// SME-SUBFEATURE-CONFLICT: "-target-feature" "+sve" "-target-feature" "+sve2" "-target-feature" "+bf16" "-target-feature" "-sme" "-target-feature" "-sme-f64f64" "-target-feature" "-sme-i16i64"
+
+// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sme-f64f64+nosve %s -### 2>&1 | FileCheck %s --check-prefix=SVE-SUBFEATURE-CONFLICT
+// SVE-SUBFEATURE-CONFLICT-NOT: "-target-feature" "+sve2"
+// SVE-SUBFEATURE-CONFLICT-NOT: "-target-feature" "+sve"
+// SVE-SUBFEATURE-CONFLICT-NOT: "-target-feature" "+sme"
+// SVE-SUBFEATURE-CONFLICT-NOT: "-target-feature" "+sme-f64f64"
+
+// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+nosme+sme-i16i64 %s -### 2>&1 | FileCheck %s --check-prefix=SME-SUBFEATURE-CONFLICT-REV
+// SME-SUBFEATURE-CONFLICT-REV: "-target-feature" "-sme-f64f64" "-target-feature" 

[PATCH] D134681: [Clang][AArch64][SME] Add outer product intrinsics

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc updated this revision to Diff 492693.
bryanpkc retitled this revision from "[Clang][AArch64] Add SME outer product 
intrinsics" to "[Clang][AArch64][SME] Add outer product intrinsics".
bryanpkc edited the summary of this revision.
bryanpkc added a comment.

Rebased and cleaned up the patch. Also added `_m` suffix to the intrinsics as 
required by the amendment in https://github.com/ARM-software/acle/pull/218.


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Files:
  clang/include/clang/Basic/arm_sme.td
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/AArch64.h
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mopa-za32.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mopa-za64.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mops-za32.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mops-za64.c

Index: clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mops-za64.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mops-za64.c
@@ -0,0 +1,74 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -triple aarch64-none-linux-gnu -target-feature +sme-f64f64 -target-feature +sme-i16i64 -target-feature +sve -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -triple aarch64-none-linux-gnu -target-feature +sme-f64f64 -target-feature +sme-i16i64 -target-feature +sve -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme-f64f64 -target-feature +sme-i16i64 -target-feature +sve -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme-f64f64 -target-feature +sme-i16i64 -target-feature +sve -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -triple aarch64-none-linux-gnu -target-feature +sme-f64f64 -target-feature +sme-i16i64 -target-feature +sve -target-feature +bf16 -S -O1 -Werror -o /dev/null %s
+
+#include 
+
+#ifdef SME_OVERLOADED_FORMS
+#define SME_ACLE_FUNC(A1,A2_UNUSED,A3) A1##A3
+#else
+#define SME_ACLE_FUNC(A1,A2,A3) A1##A2##A3
+#endif
+
+// CHECK-C-LABEL: @test_svmops_za64_s16(
+// CHECK-CXX-LABEL: @_Z20test_svmops_za64_s16u10__SVBool_tu10__SVBool_tu11__SVInt16_tu11__SVInt16_t(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PN:%.*]])
+// CHECK-NEXT:[[TMP1:%.*]] = tail call  @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PM:%.*]])
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.smops.wide.nxv8i16(i32 1,  [[TMP0]],  [[TMP1]],  [[ZN:%.*]],  [[ZM:%.*]])
+// CHECK-NEXT:ret void
+//
+__attribute__((arm_streaming)) void test_svmops_za64_s16(svbool_t pn, svbool_t pm, svint16_t zn, svint16_t zm) {
+  SME_ACLE_FUNC(svmops_za64, _s16, _m)(1, pn, pm, zn, zm);
+}
+
+// CHECK-C-LABEL: @test_svmops_za64_u16(
+// CHECK-CXX-LABEL: @_Z20test_svmops_za64_u16u10__SVBool_tu10__SVBool_tu12__SVUint16_tu12__SVUint16_t(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PN:%.*]])
+// CHECK-NEXT:[[TMP1:%.*]] = tail call  @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PM:%.*]])
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.umops.wide.nxv8i16(i32 0,  [[TMP0]],  [[TMP1]],  [[ZN:%.*]],  [[ZM:%.*]])
+// CHECK-NEXT:ret void
+//
+__attribute__((arm_streaming)) void test_svmops_za64_u16(svbool_t pn, svbool_t pm, svuint16_t zn, svuint16_t zm) {
+  SME_ACLE_FUNC(svmops_za64, _u16, _m)(0, pn, pm, zn, zm);
+}
+
+// CHECK-C-LABEL: @test_svmops_za64_f64(
+// CHECK-CXX-LABEL: @_Z20test_svmops_za64_f64u10__SVBool_tu10__SVBool_tu13__SVFloat64_tu13__SVFloat64_t(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PN:%.*]])
+// CHECK-NEXT:[[TMP1:%.*]] = tail call  @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PM:%.*]])
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.mops.nxv2f64(i32 1,  [[TMP0]],  [[TMP1]],  [[ZN:%.*]],  [[ZM:%.*]])
+// CHECK-NEXT:ret void
+//
+__attribute__((arm_streaming)) void test_svmops_za64_f64(svbool_t pn, svbool_t pm, svfloat64_t zn, svfloat64_t zm) {
+  SME_ACLE_FUNC(svmops_za64, _f64, _m)(1, pn, pm, zn, zm);
+}
+
+// CHECK-C-LABEL: @test_svsumops_za64_s16(
+// CHECK-CXX-LABEL: @_Z22test_svsumops_za64_s16u10__SVBool_tu10__SVBool_tu11__SVInt16_tu12__SVUint16_t(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  

[PATCH] D134680: [Clang][AArch64][SME] Add intrinsics for adding vector elements to ZA tile

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc updated this revision to Diff 492692.
bryanpkc edited the summary of this revision.
bryanpkc added a comment.

Added `_m` suffix to the intrinsics as required by the amendment in 
https://github.com/ARM-software/acle/pull/218.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134680/new/

https://reviews.llvm.org/D134680

Files:
  clang/include/clang/Basic/arm_sme.td
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/AArch64.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i32.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i64.c

Index: clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i64.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i64.c
@@ -0,0 +1,110 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -triple aarch64-none-linux-gnu -target-feature +sme-i16i64 -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -triple aarch64-none-linux-gnu -target-feature +sme-i16i64 -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme-i16i64 -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme-i16i64 -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -triple aarch64-none-linux-gnu -target-feature +sme-i16i64 -target-feature +sve -S -O1 -Werror -o /dev/null %s
+
+#include 
+
+#ifdef SME_OVERLOADED_FORMS
+#define SME_ACLE_FUNC(A1,A2_UNUSED,A3) A1##A3
+#else
+#define SME_ACLE_FUNC(A1,A2,A3) A1##A2##A3
+#endif
+
+// CHECK-C-LABEL: @test_svaddha_za64_u64(
+// CHECK-CXX-LABEL: @_Z21test_svaddha_za64_u64u10__SVBool_tu10__SVBool_tu12__SVUint64_t(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PN:%.*]])
+// CHECK-NEXT:[[TMP1:%.*]] = tail call  @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PM:%.*]])
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.addha.nxv2i64(i32 0,  [[TMP0]],  [[TMP1]],  [[ZN:%.*]])
+// CHECK-NEXT:ret void
+//
+__attribute__((arm_streaming)) void test_svaddha_za64_u64(svbool_t pn, svbool_t pm, svuint64_t zn) {
+  SME_ACLE_FUNC(svaddha_za64, _u64, _m)(0, pn, pm, zn);
+}
+
+// CHECK-C-LABEL: @test_svaddha_za64_u64_1(
+// CHECK-CXX-LABEL: @_Z23test_svaddha_za64_u64_1u10__SVBool_tu10__SVBool_tu12__SVUint64_t(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PN:%.*]])
+// CHECK-NEXT:[[TMP1:%.*]] = tail call  @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PM:%.*]])
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.addha.nxv2i64(i32 7,  [[TMP0]],  [[TMP1]],  [[ZN:%.*]])
+// CHECK-NEXT:ret void
+//
+__attribute__((arm_streaming)) void test_svaddha_za64_u64_1(svbool_t pn, svbool_t pm, svuint64_t zn) {
+  SME_ACLE_FUNC(svaddha_za64, _u64, _m)(7, pn, pm, zn);
+}
+
+// CHECK-C-LABEL: @test_svaddha_za64_s64(
+// CHECK-CXX-LABEL: @_Z21test_svaddha_za64_s64u10__SVBool_tu10__SVBool_tu11__SVInt64_t(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PN:%.*]])
+// CHECK-NEXT:[[TMP1:%.*]] = tail call  @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PM:%.*]])
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.addha.nxv2i64(i32 0,  [[TMP0]],  [[TMP1]],  [[ZN:%.*]])
+// CHECK-NEXT:ret void
+//
+__attribute__((arm_streaming)) void test_svaddha_za64_s64(svbool_t pn, svbool_t pm, svint64_t zn) {
+  SME_ACLE_FUNC(svaddha_za64, _s64, _m)(0, pn, pm, zn);
+}
+
+// CHECK-C-LABEL: @test_svaddha_za64_s64_1(
+// CHECK-CXX-LABEL: @_Z23test_svaddha_za64_s64_1u10__SVBool_tu10__SVBool_tu11__SVInt64_t(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PN:%.*]])
+// CHECK-NEXT:[[TMP1:%.*]] = tail call  @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PM:%.*]])
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.addha.nxv2i64(i32 7,  [[TMP0]],  [[TMP1]],  [[ZN:%.*]])
+// CHECK-NEXT:ret void
+//
+__attribute__((arm_streaming)) void test_svaddha_za64_s64_1(svbool_t pn, svbool_t pm, svint64_t zn) {
+  SME_ACLE_FUNC(svaddha_za64, _s64, _m)(7, pn, pm, zn);
+}
+
+// CHECK-C-LABEL: @test_svaddva_za64_u64(
+// CHECK-CXX-LABEL: @_Z21test_svaddva_za64_u64u10__SVBool_tu10__SVBool_tu12__SVUint64_t(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  

[PATCH] D134680: [Clang][AArch64][SME] Add intrinsics for adding vector elements to ZA tile

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc updated this revision to Diff 492682.
bryanpkc retitled this revision from "[Clang][AArch64] Add SME svaddha and 
svaddva intrinsics" to "[Clang][AArch64][SME] Add intrinsics for adding vector 
elements to ZA tile".
bryanpkc edited the summary of this revision.
bryanpkc added a comment.

Rebased and cleaned up the patch.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134680/new/

https://reviews.llvm.org/D134680

Files:
  clang/include/clang/Basic/arm_sme.td
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/AArch64.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i32.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i64.c

Index: clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i64.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i64.c
@@ -0,0 +1,110 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -triple aarch64-none-linux-gnu -target-feature +sme-i16i64 -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -triple aarch64-none-linux-gnu -target-feature +sme-i16i64 -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme-i16i64 -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme-i16i64 -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -triple aarch64-none-linux-gnu -target-feature +sme-i16i64 -target-feature +sve -S -O1 -Werror -o /dev/null %s
+
+#include 
+
+#ifdef SME_OVERLOADED_FORMS
+#define SME_ACLE_FUNC(A1,A2_UNUSED,A3) A1##A3
+#else
+#define SME_ACLE_FUNC(A1,A2,A3) A1##A2##A3
+#endif
+
+// CHECK-C-LABEL: @test_svaddha_za64_u64(
+// CHECK-CXX-LABEL: @_Z21test_svaddha_za64_u64u10__SVBool_tu10__SVBool_tu12__SVUint64_t(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PN:%.*]])
+// CHECK-NEXT:[[TMP1:%.*]] = tail call  @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PM:%.*]])
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.addha.nxv2i64(i32 0,  [[TMP0]],  [[TMP1]],  [[ZN:%.*]])
+// CHECK-NEXT:ret void
+//
+__attribute__((arm_streaming)) void test_svaddha_za64_u64(svbool_t pn, svbool_t pm, svuint64_t zn) {
+  SME_ACLE_FUNC(svaddha_za64, _u64,)(0, pn, pm, zn);
+}
+
+// CHECK-C-LABEL: @test_svaddha_za64_u64_1(
+// CHECK-CXX-LABEL: @_Z23test_svaddha_za64_u64_1u10__SVBool_tu10__SVBool_tu12__SVUint64_t(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PN:%.*]])
+// CHECK-NEXT:[[TMP1:%.*]] = tail call  @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PM:%.*]])
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.addha.nxv2i64(i32 7,  [[TMP0]],  [[TMP1]],  [[ZN:%.*]])
+// CHECK-NEXT:ret void
+//
+__attribute__((arm_streaming)) void test_svaddha_za64_u64_1(svbool_t pn, svbool_t pm, svuint64_t zn) {
+  SME_ACLE_FUNC(svaddha_za64, _u64,)(7, pn, pm, zn);
+}
+
+// CHECK-C-LABEL: @test_svaddha_za64_s64(
+// CHECK-CXX-LABEL: @_Z21test_svaddha_za64_s64u10__SVBool_tu10__SVBool_tu11__SVInt64_t(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PN:%.*]])
+// CHECK-NEXT:[[TMP1:%.*]] = tail call  @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PM:%.*]])
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.addha.nxv2i64(i32 0,  [[TMP0]],  [[TMP1]],  [[ZN:%.*]])
+// CHECK-NEXT:ret void
+//
+__attribute__((arm_streaming)) void test_svaddha_za64_s64(svbool_t pn, svbool_t pm, svint64_t zn) {
+  SME_ACLE_FUNC(svaddha_za64, _s64,)(0, pn, pm, zn);
+}
+
+// CHECK-C-LABEL: @test_svaddha_za64_s64_1(
+// CHECK-CXX-LABEL: @_Z23test_svaddha_za64_s64_1u10__SVBool_tu10__SVBool_tu11__SVInt64_t(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PN:%.*]])
+// CHECK-NEXT:[[TMP1:%.*]] = tail call  @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PM:%.*]])
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.addha.nxv2i64(i32 7,  [[TMP0]],  [[TMP1]],  [[ZN:%.*]])
+// CHECK-NEXT:ret void
+//
+__attribute__((arm_streaming)) void test_svaddha_za64_s64_1(svbool_t pn, svbool_t pm, svint64_t zn) {
+  SME_ACLE_FUNC(svaddha_za64, _s64,)(7, pn, pm, zn);
+}
+
+// CHECK-C-LABEL: @test_svaddva_za64_u64(
+// CHECK-CXX-LABEL: @_Z21test_svaddva_za64_u64u10__SVBool_tu10__SVBool_tu12__SVUint64_t(
+// 

[PATCH] D134679: [Clang][AArch64][SME] Add intrinsics for reading streaming vector length

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc updated this revision to Diff 492681.
bryanpkc retitled this revision from "[Clang][AArch64] Add SME svcntsb/h/w/d C 
intrinsics" to "[Clang][AArch64][SME] Add intrinsics for reading streaming 
vector length".
bryanpkc edited the summary of this revision.
bryanpkc added a comment.

Rebased and cleaned up the patch.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134679/new/

https://reviews.llvm.org/D134679

Files:
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/Basic/arm_sme.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_cnt.c

Index: clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_cnt.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_cnt.c
@@ -0,0 +1,46 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -o /dev/null %s
+
+#include 
+
+// CHECK-C-LABEL: @test_svcntsb(
+// CHECK-CXX-LABEL: @_Z12test_svcntsbv(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 @llvm.aarch64.sme.cntsb()
+// CHECK-NEXT:ret i64 [[TMP0]]
+//
+uint64_t test_svcntsb() {
+  return svcntsb();
+}
+
+// CHECK-C-LABEL: @test_svcntsh(
+// CHECK-CXX-LABEL: @_Z12test_svcntshv(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 @llvm.aarch64.sme.cntsh()
+// CHECK-NEXT:ret i64 [[TMP0]]
+//
+uint64_t test_svcntsh() {
+  return svcntsh();
+}
+
+// CHECK-C-LABEL: @test_svcntsw(
+// CHECK-CXX-LABEL: @_Z12test_svcntswv(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 @llvm.aarch64.sme.cntsw()
+// CHECK-NEXT:ret i64 [[TMP0]]
+//
+uint64_t test_svcntsw() {
+  return svcntsw();
+}
+
+// CHECK-C-LABEL: @test_svcntsd(
+// CHECK-CXX-LABEL: @_Z12test_svcntsdv(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 @llvm.aarch64.sme.cntsd()
+// CHECK-NEXT:ret i64 [[TMP0]]
+//
+uint64_t test_svcntsd() {
+  return svcntsd();
+}
Index: clang/lib/CodeGen/CodeGenFunction.h
===
--- clang/lib/CodeGen/CodeGenFunction.h
+++ clang/lib/CodeGen/CodeGenFunction.h
@@ -4249,6 +4249,9 @@
   unsigned IntID);
   llvm::Value *EmitAArch64SVEBuiltinExpr(unsigned BuiltinID, const CallExpr *E);
 
+  SmallVector
+  getSMEOverloadTypes(const SMETypeFlags , llvm::Type *ReturnType,
+  ArrayRef Ops);
   llvm::ScalableVectorType *getSVEType(const SMETypeFlags );
   llvm::Value *EmitSMELd1St1(SMETypeFlags TypeFlags,
  llvm::SmallVectorImpl ,
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -9309,6 +9309,19 @@
   return Builder.CreateAdd(Base, CastOffset, "tileslice");
 }
 
+SmallVector
+CodeGenFunction::getSMEOverloadTypes(const SMETypeFlags ,
+ llvm::Type *ResultType,
+ ArrayRef Ops) {
+  if (TypeFlags.isOverloadNone())
+return {};
+
+  llvm::Type *DefaultType = getSVEType(TypeFlags);
+
+  assert(TypeFlags.isOverloadDefault() && "Unexpected value for overloads");
+  return {DefaultType};
+}
+
 // Return the llvm vector type corresponding to the specified element TypeFlags.
 llvm::ScalableVectorType *
 CodeGenFunction::getSVEType(const SMETypeFlags ) {
@@ -9893,6 +9906,7 @@
   getContext().GetBuiltinType(BuiltinID, Error, );
   assert(Error == ASTContext::GE_None && "Should not codegen an error");
 
+  llvm::Type *Ty = ConvertType(E->getType());
   llvm::SmallVector Ops;
   for (unsigned i = 0, e = E->getNumArgs(); i != e; i++) {
 if ((ICEArguments & (1 << i)) == 0)
@@ -9923,6 +9937,12 @@
 return EmitSMEZero(TypeFlags, Ops, Builtin->LLVMIntrinsic);
   else if (TypeFlags.isLoadReg() || TypeFlags.isStoreReg())
 return EmitSMELdrStr(TypeFlags, Ops, Builtin->LLVMIntrinsic);
+  else if (Builtin->LLVMIntrinsic != 0) {
+Function *F = CGM.getIntrinsic(Builtin->LLVMIntrinsic,
+   getSMEOverloadTypes(TypeFlags, Ty, Ops));
+Value *Call = Builder.CreateCall(F, Ops);
+return Call;
+  }
 
   /// Should not happen
   return nullptr;
Index: clang/include/clang/Basic/arm_sme.td
===
--- 

[PATCH] D134677: [Clang][AArch64][SME] Add ZA zeroing intrinsics

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc updated this revision to Diff 492680.
bryanpkc added a comment.

Update patch with more context.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134677/new/

https://reviews.llvm.org/D134677

Files:
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/Basic/arm_sme.td
  clang/include/clang/Basic/arm_sve_sme_incl.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_zero.c

Index: clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_zero.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_zero.c
@@ -0,0 +1,47 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -o /dev/null %s
+
+#include 
+
+// CHECK-C-LABEL: @test_svzero_mask_za(
+// CHECK-CXX-LABEL: @_Z19test_svzero_mask_zav(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.zero(i32 0)
+// CHECK-NEXT:ret void
+//
+void test_svzero_mask_za() {
+  svzero_mask_za(0);
+}
+
+// CHECK-C-LABEL: @test_svzero_mask_za_1(
+// CHECK-CXX-LABEL: @_Z21test_svzero_mask_za_1v(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.zero(i32 176)
+// CHECK-NEXT:ret void
+//
+void test_svzero_mask_za_1() {
+  svzero_mask_za(176);
+}
+
+// CHECK-C-LABEL: @test_svzero_mask_za_2(
+// CHECK-CXX-LABEL: @_Z21test_svzero_mask_za_2v(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.zero(i32 255)
+// CHECK-NEXT:ret void
+//
+void test_svzero_mask_za_2() {
+  svzero_mask_za(255);
+}
+
+// CHECK-C-LABEL: @test_svzero_za(
+// CHECK-CXX-LABEL: @_Z14test_svzero_zav(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.zero(i32 255)
+// CHECK-NEXT:ret void
+//
+void test_svzero_za() {
+  svzero_za();
+}
Index: clang/lib/CodeGen/CodeGenFunction.h
===
--- clang/lib/CodeGen/CodeGenFunction.h
+++ clang/lib/CodeGen/CodeGenFunction.h
@@ -4256,6 +4256,9 @@
   llvm::Value *EmitSMEReadWrite(SMETypeFlags TypeFlags,
 llvm::SmallVectorImpl ,
 unsigned IntID);
+  llvm::Value *EmitSMEZero(SMETypeFlags TypeFlags,
+   llvm::SmallVectorImpl ,
+   unsigned IntID);
   llvm::Value *EmitAArch64SMEBuiltinExpr(unsigned BuiltinID, const CallExpr *E);
 
   llvm::Value *EmitAArch64BuiltinExpr(unsigned BuiltinID, const CallExpr *E,
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -9438,6 +9438,16 @@
   return Builder.CreateCall(F, Ops);
 }
 
+Value *CodeGenFunction::EmitSMEZero(SMETypeFlags TypeFlags,
+SmallVectorImpl ,
+unsigned IntID) {
+  // svzero_za() intrinsic zeros the entire za tile and has no paramters.
+  if (Ops.size() == 0)
+Ops.push_back(llvm::ConstantInt::get(Int32Ty, 255));
+  Function *F = CGM.getIntrinsic(IntID, {});
+  return Builder.CreateCall(F, Ops);
+}
+
 // Limit the usage of scalable llvm IR generated by the ACLE by using the
 // sve dup.x intrinsic instead of IRBuilder::CreateVectorSplat.
 Value *CodeGenFunction::EmitSVEDupX(Value *Scalar, llvm::Type *Ty) {
@@ -9894,6 +9904,8 @@
 return EmitSMELd1St1(TypeFlags, Ops, Builtin->LLVMIntrinsic);
   else if (TypeFlags.isMove())
 return EmitSMEReadWrite(TypeFlags, Ops, Builtin->LLVMIntrinsic);
+  else if (TypeFlags.isZero())
+return EmitSMEZero(TypeFlags, Ops, Builtin->LLVMIntrinsic);
 
   /// Should not happen
   return nullptr;
Index: clang/include/clang/Basic/arm_sve_sme_incl.td
===
--- clang/include/clang/Basic/arm_sve_sme_incl.td
+++ clang/include/clang/Basic/arm_sve_sme_incl.td
@@ -216,6 +216,7 @@
 def IsSharedZA: FlagType<0x20>;
 def IsPreservesZA : FlagType<0x40>;
 def IsMove: FlagType<0x80>;
+def IsZero: FlagType<0x100>;
 
 // These must be kept in sync with the flags in include/clang/Basic/TargetBuiltins.h
 class ImmCheckType {
Index: clang/include/clang/Basic/arm_sme.td

[PATCH] D134678: [Clang][AArch64][SME] Add intrinsics for ZA array load/store (LDR/STR)

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc updated this revision to Diff 492679.
bryanpkc retitled this revision from "[Clang][AArch64] Add SME ldr and str 
intrinsic" to "[Clang][AArch64][SME] Add intrinsics for ZA array load/store 
(LDR/STR)".
bryanpkc edited the summary of this revision.
bryanpkc added a comment.

Rebased and cleaned up the patch.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134678/new/

https://reviews.llvm.org/D134678

Files:
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/Basic/arm_sme.td
  clang/include/clang/Basic/arm_sve_sme_incl.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ldr.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_str.c

Index: clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_str.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_str.c
@@ -0,0 +1,43 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -o /dev/null %s
+
+#include 
+
+
+// CHECK-C-LABEL: @test_svstr_vnum_za(
+// CHECK-CXX-LABEL: @_Z18test_svstr_vnum_zajPv(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.str(i32 [[SLICE_BASE:%.*]], ptr [[PTR:%.*]])
+// CHECK-NEXT:ret void
+//
+void test_svstr_vnum_za(uint32_t slice_base, void *ptr) {
+  svstr_vnum_za(slice_base, 0, ptr);
+}
+
+// CHECK-C-LABEL: @test_svstr_vnum_za_1(
+// CHECK-CXX-LABEL: @_Z20test_svstr_vnum_za_1jPv(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[VSCALE:%.*]] = tail call i64 @llvm.vscale.i64()
+// CHECK-NEXT:[[MULVL:%.*]] = mul nuw nsw i64 [[VSCALE]], 240
+// CHECK-NEXT:[[TMP0:%.*]] = getelementptr i8, ptr [[PTR:%.*]], i64 [[MULVL]]
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.str(i32 [[SLICE_BASE:%.*]], ptr [[TMP0]])
+// CHECK-NEXT:ret void
+//
+void test_svstr_vnum_za_1(uint32_t slice_base, void *ptr) {
+  svstr_vnum_za(slice_base, 15, ptr);
+}
+
+// CHECK-C-LABEL: @test_svstr_vnum_za_2(
+// CHECK-CXX-LABEL: @_Z20test_svstr_vnum_za_2jPv(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[VSCALE:%.*]] = tail call i64 @llvm.vscale.i64()
+// CHECK-NEXT:[[MULVL:%.*]] = shl nuw nsw i64 [[VSCALE]], 8
+// CHECK-NEXT:[[TMP0:%.*]] = getelementptr i8, ptr [[PTR:%.*]], i64 [[MULVL]]
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.str(i32 [[SLICE_BASE:%.*]], ptr [[TMP0]])
+// CHECK-NEXT:ret void
+//
+void test_svstr_vnum_za_2(uint32_t slice_base, void *ptr) {
+  svstr_vnum_za(slice_base, 16, ptr);
+}
Index: clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ldr.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ldr.c
@@ -0,0 +1,42 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -o /dev/null %s
+
+#include 
+
+// CHECK-C-LABEL: @test_svldr_vnum_za(
+// CHECK-CXX-LABEL: @_Z18test_svldr_vnum_zajPKv(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.ldr(i32 [[SLICE_BASE:%.*]], ptr [[PTR:%.*]])
+// CHECK-NEXT:ret void
+//
+void test_svldr_vnum_za(uint32_t slice_base, const void *ptr) {
+  svldr_vnum_za(slice_base, 0, ptr);
+}
+
+// CHECK-C-LABEL: @test_svldr_vnum_za_1(
+// CHECK-CXX-LABEL: @_Z20test_svldr_vnum_za_1jPKv(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[VSCALE:%.*]] = tail call i64 @llvm.vscale.i64()
+// CHECK-NEXT:[[MULVL:%.*]] = mul nuw nsw i64 [[VSCALE]], 240
+// CHECK-NEXT:[[TMP0:%.*]] = getelementptr i8, ptr [[PTR:%.*]], i64 [[MULVL]]
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.ldr(i32 [[SLICE_BASE:%.*]], ptr [[TMP0]])
+// CHECK-NEXT:ret void
+//
+void test_svldr_vnum_za_1(uint32_t slice_base, const void *ptr) {
+  svldr_vnum_za(slice_base, 15, ptr);
+}
+
+// CHECK-C-LABEL: @test_svldr_vnum_za_2(
+// CHECK-CXX-LABEL: @_Z20test_svldr_vnum_za_2jPKv(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[VSCALE:%.*]] = tail call i64 

[PATCH] D127910: [Clang][AArch64][SME] Add vector load/store (ld1/st1) intrinsics

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc updated this revision to Diff 492586.
bryanpkc added a comment.

Minor clean-up. Sorry for the noise.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D127910/new/

https://reviews.llvm.org/D127910

Files:
  clang/include/clang/Basic/BuiltinsSME.def
  clang/include/clang/Basic/CMakeLists.txt
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/Basic/arm_sme.td
  clang/include/clang/Basic/arm_sve.td
  clang/include/clang/Basic/arm_sve_sme_incl.td
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Sema/SemaDeclAttr.cpp
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_int_const_expr_error.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1_vnum.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1_vnum.c
  clang/utils/TableGen/SveEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h

Index: clang/utils/TableGen/TableGenBackends.h
===
--- clang/utils/TableGen/TableGenBackends.h
+++ clang/utils/TableGen/TableGenBackends.h
@@ -101,6 +101,12 @@
 void EmitSveTypeFlags(llvm::RecordKeeper , llvm::raw_ostream );
 void EmitSveRangeChecks(llvm::RecordKeeper , llvm::raw_ostream );
 
+void EmitSmeHeader(llvm::RecordKeeper , llvm::raw_ostream );
+void EmitSmeBuiltins(llvm::RecordKeeper , llvm::raw_ostream );
+void EmitSmeBuiltinCG(llvm::RecordKeeper , llvm::raw_ostream );
+void EmitSmeTypeFlags(llvm::RecordKeeper , llvm::raw_ostream );
+void EmitSmeRangeChecks(llvm::RecordKeeper , llvm::raw_ostream );
+
 void EmitMveHeader(llvm::RecordKeeper , llvm::raw_ostream );
 void EmitMveBuiltinDef(llvm::RecordKeeper , llvm::raw_ostream );
 void EmitMveBuiltinSema(llvm::RecordKeeper , llvm::raw_ostream );
Index: clang/utils/TableGen/TableGen.cpp
===
--- clang/utils/TableGen/TableGen.cpp
+++ clang/utils/TableGen/TableGen.cpp
@@ -81,6 +81,11 @@
   GenArmSveBuiltinCG,
   GenArmSveTypeFlags,
   GenArmSveRangeChecks,
+  GenArmSmeHeader,
+  GenArmSmeBuiltins,
+  GenArmSmeBuiltinCG,
+  GenArmSmeTypeFlags,
+  GenArmSmeRangeChecks,
   GenArmCdeHeader,
   GenArmCdeBuiltinDef,
   GenArmCdeBuiltinSema,
@@ -219,6 +224,16 @@
"Generate arm_sve_typeflags.inc for clang"),
 clEnumValN(GenArmSveRangeChecks, "gen-arm-sve-sema-rangechecks",
"Generate arm_sve_sema_rangechecks.inc for clang"),
+clEnumValN(GenArmSmeHeader, "gen-arm-sme-header",
+   "Generate arm_sme.h for clang"),
+clEnumValN(GenArmSmeBuiltins, "gen-arm-sme-builtins",
+   "Generate arm_sme_builtins.inc for clang"),
+clEnumValN(GenArmSmeBuiltinCG, "gen-arm-sme-builtin-codegen",
+   "Generate arm_sme_builtin_cg_map.inc for clang"),
+clEnumValN(GenArmSmeTypeFlags, "gen-arm-sme-typeflags",
+   "Generate arm_sme_typeflags.inc for clang"),
+clEnumValN(GenArmSmeRangeChecks, "gen-arm-sme-sema-rangechecks",
+   "Generate arm_sme_sema_rangechecks.inc for clang"),
 clEnumValN(GenArmMveHeader, "gen-arm-mve-header",
"Generate arm_mve.h for clang"),
 clEnumValN(GenArmMveBuiltinDef, "gen-arm-mve-builtin-def",
@@ -438,6 +453,21 @@
   case GenArmSveRangeChecks:
 EmitSveRangeChecks(Records, OS);
 break;
+  case GenArmSmeHeader:
+EmitSmeHeader(Records, OS);
+break;
+  case GenArmSmeBuiltins:
+EmitSmeBuiltins(Records, OS);
+break;
+  case GenArmSmeBuiltinCG:
+EmitSmeBuiltinCG(Records, OS);
+break;
+  case GenArmSmeTypeFlags:
+EmitSmeTypeFlags(Records, OS);
+break;
+  case GenArmSmeRangeChecks:
+EmitSmeRangeChecks(Records, OS);
+break;
   case GenArmCdeHeader:
 EmitCdeHeader(Records, OS);
 break;
Index: clang/utils/TableGen/SveEmitter.cpp
===
--- clang/utils/TableGen/SveEmitter.cpp
+++ clang/utils/TableGen/SveEmitter.cpp
@@ -228,7 +228,7 @@
   }
 
   /// Emits the intrinsic declaration to the ostream.
-  void emitIntrinsic(raw_ostream ) const;
+  void emitIntrinsic(raw_ostream , SVEEmitter ) const;
 
 private:
   std::string getMergeSuffix() const { return MergeSuffix; }
@@ -346,8 +346,24 @@
   /// Create the SVETypeFlags used in CGBuiltins
   void createTypeFlags(raw_ostream );
 
+  /// Emit arm_sme.h.
+  void createSMEHeader(raw_ostream );
+
+  /// Emit all the SME __builtin prototypes and code needed by Sema.
+  void createSMEBuiltins(raw_ostream );
+
+  /// Emit all the information needed to map builtin -> LLVM IR intrinsic.
+  void createSMECodeGenMap(raw_ostream );
+
+  /// Emit all the range checks for the immediates.
+  

[PATCH] D127910: [Clang][AArch64][SME] Add vector load/store (ld1/st1) intrinsics

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc updated this revision to Diff 492585.
bryanpkc retitled this revision from "[Clang][AArch64] Add SME C intrinsics for 
load and store" to "[Clang][AArch64][SME] Add vector load/store (ld1/st1) 
intrinsics".
bryanpkc edited the summary of this revision.
bryanpkc added a comment.

Updated the patch to define the `__ARM_FEATURE_SME` macro when the feature is 
enabled.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D127910/new/

https://reviews.llvm.org/D127910

Files:
  clang/include/clang/Basic/BuiltinsSME.def
  clang/include/clang/Basic/CMakeLists.txt
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/Basic/arm_sme.td
  clang/include/clang/Basic/arm_sve.td
  clang/include/clang/Basic/arm_sve_sme_incl.td
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Sema/SemaDeclAttr.cpp
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_int_const_expr_error.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1_vnum.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1_vnum.c
  clang/utils/TableGen/SveEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h

Index: clang/utils/TableGen/TableGenBackends.h
===
--- clang/utils/TableGen/TableGenBackends.h
+++ clang/utils/TableGen/TableGenBackends.h
@@ -101,6 +101,12 @@
 void EmitSveTypeFlags(llvm::RecordKeeper , llvm::raw_ostream );
 void EmitSveRangeChecks(llvm::RecordKeeper , llvm::raw_ostream );
 
+void EmitSmeHeader(llvm::RecordKeeper , llvm::raw_ostream );
+void EmitSmeBuiltins(llvm::RecordKeeper , llvm::raw_ostream );
+void EmitSmeBuiltinCG(llvm::RecordKeeper , llvm::raw_ostream );
+void EmitSmeTypeFlags(llvm::RecordKeeper , llvm::raw_ostream );
+void EmitSmeRangeChecks(llvm::RecordKeeper , llvm::raw_ostream );
+
 void EmitMveHeader(llvm::RecordKeeper , llvm::raw_ostream );
 void EmitMveBuiltinDef(llvm::RecordKeeper , llvm::raw_ostream );
 void EmitMveBuiltinSema(llvm::RecordKeeper , llvm::raw_ostream );
Index: clang/utils/TableGen/TableGen.cpp
===
--- clang/utils/TableGen/TableGen.cpp
+++ clang/utils/TableGen/TableGen.cpp
@@ -81,6 +81,11 @@
   GenArmSveBuiltinCG,
   GenArmSveTypeFlags,
   GenArmSveRangeChecks,
+  GenArmSmeHeader,
+  GenArmSmeBuiltins,
+  GenArmSmeBuiltinCG,
+  GenArmSmeTypeFlags,
+  GenArmSmeRangeChecks,
   GenArmCdeHeader,
   GenArmCdeBuiltinDef,
   GenArmCdeBuiltinSema,
@@ -219,6 +224,16 @@
"Generate arm_sve_typeflags.inc for clang"),
 clEnumValN(GenArmSveRangeChecks, "gen-arm-sve-sema-rangechecks",
"Generate arm_sve_sema_rangechecks.inc for clang"),
+clEnumValN(GenArmSmeHeader, "gen-arm-sme-header",
+   "Generate arm_sme.h for clang"),
+clEnumValN(GenArmSmeBuiltins, "gen-arm-sme-builtins",
+   "Generate arm_sme_builtins.inc for clang"),
+clEnumValN(GenArmSmeBuiltinCG, "gen-arm-sme-builtin-codegen",
+   "Generate arm_sme_builtin_cg_map.inc for clang"),
+clEnumValN(GenArmSmeTypeFlags, "gen-arm-sme-typeflags",
+   "Generate arm_sme_typeflags.inc for clang"),
+clEnumValN(GenArmSmeRangeChecks, "gen-arm-sme-sema-rangechecks",
+   "Generate arm_sme_sema_rangechecks.inc for clang"),
 clEnumValN(GenArmMveHeader, "gen-arm-mve-header",
"Generate arm_mve.h for clang"),
 clEnumValN(GenArmMveBuiltinDef, "gen-arm-mve-builtin-def",
@@ -438,6 +453,21 @@
   case GenArmSveRangeChecks:
 EmitSveRangeChecks(Records, OS);
 break;
+  case GenArmSmeHeader:
+EmitSmeHeader(Records, OS);
+break;
+  case GenArmSmeBuiltins:
+EmitSmeBuiltins(Records, OS);
+break;
+  case GenArmSmeBuiltinCG:
+EmitSmeBuiltinCG(Records, OS);
+break;
+  case GenArmSmeTypeFlags:
+EmitSmeTypeFlags(Records, OS);
+break;
+  case GenArmSmeRangeChecks:
+EmitSmeRangeChecks(Records, OS);
+break;
   case GenArmCdeHeader:
 EmitCdeHeader(Records, OS);
 break;
Index: clang/utils/TableGen/SveEmitter.cpp
===
--- clang/utils/TableGen/SveEmitter.cpp
+++ clang/utils/TableGen/SveEmitter.cpp
@@ -228,7 +228,7 @@
   }
 
   /// Emits the intrinsic declaration to the ostream.
-  void emitIntrinsic(raw_ostream ) const;
+  void emitIntrinsic(raw_ostream , SVEEmitter ) const;
 
 private:
   std::string getMergeSuffix() const { return MergeSuffix; }
@@ -346,8 +346,24 @@
   /// Create the SVETypeFlags used in CGBuiltins
   void createTypeFlags(raw_ostream );
 
+  /// Emit arm_sme.h.
+  void createSMEHeader(raw_ostream );
+
+  /// Emit all the SME 

[PATCH] D141886: [Clang][test] Avoid FileCheck error when matching `-cc1`

[Bryan Chan via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG275ab246ee81: [Clang][test] Avoid FileCheck error when 
matching `-cc1` (authored by hezuoqiang hezuoqia...@huawei.com, 
committed by bryanpkc).

Changed prior to commit:
  https://reviews.llvm.org/D141886?vs=489995=491025#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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Files:
  clang/test/Driver/modules-ts.cpp
  clang/test/Driver/modules.cpp
  clang/test/OpenMP/driver.c


Index: clang/test/OpenMP/driver.c
===
--- clang/test/OpenMP/driver.c
+++ clang/test/OpenMP/driver.c
@@ -3,12 +3,12 @@
 //
 // RUN: %clang %s -### -o %t.o 2>&1 -fopenmp=libomp | FileCheck 
--check-prefix=CHECK-DEFAULT %s
 
-// CHECK-DEFAULT: -cc1
+// CHECK-DEFAULT: "-cc1"
 // CHECK-DEFAULT-NOT: -fnoopenmp-use-tls
 //
 // RUN: %clang %s -### -o %t.o 2>&1 -fopenmp=libomp -fnoopenmp-use-tls | 
FileCheck --check-prefix=CHECK-NO-TLS %s
 
-// CHECK-NO-TLS: -cc1
+// CHECK-NO-TLS: "-cc1"
 // CHECK-NO-TLS-SAME: -fnoopenmp-use-tls
 //
 // RUN: %clang %s -c -E -dM -fopenmp=libomp | FileCheck 
--check-prefix=CHECK-DEFAULT-VERSION %s
Index: clang/test/Driver/modules.cpp
===
--- clang/test/Driver/modules.cpp
+++ clang/test/Driver/modules.cpp
@@ -24,8 +24,7 @@
 // RUN: %clang -std=c++2a -fmodule-file=%t/module.pcm -Dexport= %s -S -o 
%t/module.o -v 2>&1 | FileCheck %s --check-prefix=CHECK-USE
 // RUN: %clang -std=c++20 -fmodule-file=%t/module.pcm -Dexport= %s -S -o 
%t/module.o -v 2>&1 | FileCheck %s --check-prefix=CHECK-USE
 //
-// CHECK-USE: -cc1
-// CHECK-USE-SAME: {{-emit-obj|-S}}
+// CHECK-USE: -cc1 {{.*}} {{-emit-obj|-S}}
 // CHECK-USE-SAME: -fmodule-file={{.*}}.pcm
 // CHECK-USE-SAME: -o {{.*}}.{{o|s}}{{"?}} {{.*}}-x c++
 // CHECK-USE-SAME: modules.cpp
Index: clang/test/Driver/modules-ts.cpp
===
--- clang/test/Driver/modules-ts.cpp
+++ clang/test/Driver/modules-ts.cpp
@@ -23,8 +23,7 @@
 // RUN: %clang -fmodules-ts -fmodule-file=%t.pcm -fintegrated-as -Dexport= %s 
-c -o %t.o -v 2>&1 | FileCheck %s --check-prefix=CHECK-USE
 //
 // CHECK-USE:  warning: the '-fmodules-ts' flag is deprecated and it will be 
removed in Clang 17; use '-std=c++20' or higher to use standard C++ modules 
instead [-Wdeprecated-module-ts]
-// CHECK-USE: -cc1
-// CHECK-USE-SAME: -emit-obj
+// CHECK-USE: -cc1 {{.*}} -emit-obj
 // CHECK-USE-SAME: -fmodule-file={{.*}}.pcm
 // CHECK-USE-SAME: -o {{.*}}.o{{"?}} {{.*}}-x c++
 // CHECK-USE-SAME: modules-ts.cpp


Index: clang/test/OpenMP/driver.c
===
--- clang/test/OpenMP/driver.c
+++ clang/test/OpenMP/driver.c
@@ -3,12 +3,12 @@
 //
 // RUN: %clang %s -### -o %t.o 2>&1 -fopenmp=libomp | FileCheck --check-prefix=CHECK-DEFAULT %s
 
-// CHECK-DEFAULT: -cc1
+// CHECK-DEFAULT: "-cc1"
 // CHECK-DEFAULT-NOT: -fnoopenmp-use-tls
 //
 // RUN: %clang %s -### -o %t.o 2>&1 -fopenmp=libomp -fnoopenmp-use-tls | FileCheck --check-prefix=CHECK-NO-TLS %s
 
-// CHECK-NO-TLS: -cc1
+// CHECK-NO-TLS: "-cc1"
 // CHECK-NO-TLS-SAME: -fnoopenmp-use-tls
 //
 // RUN: %clang %s -c -E -dM -fopenmp=libomp | FileCheck --check-prefix=CHECK-DEFAULT-VERSION %s
Index: clang/test/Driver/modules.cpp
===
--- clang/test/Driver/modules.cpp
+++ clang/test/Driver/modules.cpp
@@ -24,8 +24,7 @@
 // RUN: %clang -std=c++2a -fmodule-file=%t/module.pcm -Dexport= %s -S -o %t/module.o -v 2>&1 | FileCheck %s --check-prefix=CHECK-USE
 // RUN: %clang -std=c++20 -fmodule-file=%t/module.pcm -Dexport= %s -S -o %t/module.o -v 2>&1 | FileCheck %s --check-prefix=CHECK-USE
 //
-// CHECK-USE: -cc1
-// CHECK-USE-SAME: {{-emit-obj|-S}}
+// CHECK-USE: -cc1 {{.*}} {{-emit-obj|-S}}
 // CHECK-USE-SAME: -fmodule-file={{.*}}.pcm
 // CHECK-USE-SAME: -o {{.*}}.{{o|s}}{{"?}} {{.*}}-x c++
 // CHECK-USE-SAME: modules.cpp
Index: clang/test/Driver/modules-ts.cpp
===
--- clang/test/Driver/modules-ts.cpp
+++ clang/test/Driver/modules-ts.cpp
@@ -23,8 +23,7 @@
 // RUN: %clang -fmodules-ts -fmodule-file=%t.pcm -fintegrated-as -Dexport= %s -c -o %t.o -v 2>&1 | FileCheck %s --check-prefix=CHECK-USE
 //
 // CHECK-USE:  warning: the '-fmodules-ts' flag is deprecated and it will be removed in Clang 17; use '-std=c++20' or higher to use standard C++ modules instead [-Wdeprecated-module-ts]
-// CHECK-USE: -cc1
-// CHECK-USE-SAME: -emit-obj
+// CHECK-USE: -cc1 {{.*}} -emit-obj
 // CHECK-USE-SAME: -fmodule-file={{.*}}.pcm
 // CHECK-USE-SAME: -o {{.*}}.o{{"?}} {{.*}}-x c++
 // CHECK-USE-SAME: modules-ts.cpp
___
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[PATCH] D141886: [Clang][test] Avoid FileCheck error when matching `-cc1`

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc accepted this revision.
bryanpkc added a comment.
This revision is now accepted and ready to land.

LGTM


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[PATCH] D141886: [Clang][test] Avoid FileCheck error when matching `-cc1`

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc requested changes to this revision.
bryanpkc added inline comments.
This revision now requires changes to proceed.



Comment at: clang/test/Driver/modules-ts.cpp:23
 //
-// CHECK-USE: -cc1
+// CHECK-USE: -cc1{{[^[:xdigit:]]}}
 // CHECK-USE-SAME: -emit-obj

bryanpkc wrote:
> An easier-to-understand fix is to simply combine this line and the next:
> ```
> // CHECK-USE: -cc1 {{.*}} -emit-obj
> ```
Adding `-###` to this test totally changes the meaning of the test, and is not 
what I asked for. See lines 5 and 14 for examples of the correct approach.



Comment at: clang/test/Driver/modules.cpp:24-25
 //
-// RUN: %clang -std=c++2a -fmodule-file=%t/module.pcm -Dexport= %s -S -o 
%t/module.o -v 2>&1 | FileCheck %s --check-prefix=CHECK-USE
-// RUN: %clang -std=c++20 -fmodule-file=%t/module.pcm -Dexport= %s -S -o 
%t/module.o -v 2>&1 | FileCheck %s --check-prefix=CHECK-USE
+// RUN: %clang -std=c++2a -fmodule-file=%t/module.pcm -Dexport= %s -S -o 
%t/module.o -v -### 2>&1 | FileCheck %s --check-prefix=CHECK-USE
+// RUN: %clang -std=c++20 -fmodule-file=%t/module.pcm -Dexport= %s -S -o 
%t/module.o -v -### 2>&1 | FileCheck %s --check-prefix=CHECK-USE
 //

Do not add `-###`, which totally changes the meaning of the test. See line 17 
for an example of what you need to do here.


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[PATCH] D141886: [Clang][Test] Avoid matching version numbers

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc added a comment.

Thanks for the patch. I just have some simple suggestions.




Comment at: clang/test/Driver/modules-ts.cpp:23
 //
-// CHECK-USE: -cc1
+// CHECK-USE: -cc1{{[^[:xdigit:]]}}
 // CHECK-USE-SAME: -emit-obj

An easier-to-understand fix is to simply combine this line and the next:
```
// CHECK-USE: -cc1 {{.*}} -emit-obj
```



Comment at: clang/test/OpenMP/driver.c:6
 
-// CHECK-DEFAULT: -cc1
+// CHECK-DEFAULT: -cc1{{[^[:xdigit:]]}}
 // CHECK-DEFAULT-NOT: -fnoopenmp-use-tls

With `-###` on the command line, a better fix for this is:
```
// CHECK-DEFAULT: "-cc1"
```


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[PATCH] D134677: [Clang][AArch64][SME] Add ZA zeroing intrinsics

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc updated this revision to Diff 487384.
bryanpkc retitled this revision from "[Clang][AArch64] Add SME zero intrinsic" 
to "[Clang][AArch64][SME] Add ZA zeroing intrinsics".
bryanpkc edited the summary of this revision.

Repository:
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Files:
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/Basic/arm_sme.td
  clang/include/clang/Basic/arm_sve_sme_incl.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_zero.c

Index: clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_zero.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_zero.c
@@ -0,0 +1,47 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -o /dev/null %s
+
+#include 
+
+// CHECK-C-LABEL: @test_svzero_mask_za(
+// CHECK-CXX-LABEL: @_Z19test_svzero_mask_zav(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.zero(i32 0)
+// CHECK-NEXT:ret void
+//
+void test_svzero_mask_za() {
+  svzero_mask_za(0);
+}
+
+// CHECK-C-LABEL: @test_svzero_mask_za_1(
+// CHECK-CXX-LABEL: @_Z21test_svzero_mask_za_1v(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.zero(i32 176)
+// CHECK-NEXT:ret void
+//
+void test_svzero_mask_za_1() {
+  svzero_mask_za(176);
+}
+
+// CHECK-C-LABEL: @test_svzero_mask_za_2(
+// CHECK-CXX-LABEL: @_Z21test_svzero_mask_za_2v(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.zero(i32 255)
+// CHECK-NEXT:ret void
+//
+void test_svzero_mask_za_2() {
+  svzero_mask_za(255);
+}
+
+// CHECK-C-LABEL: @test_svzero_za(
+// CHECK-CXX-LABEL: @_Z14test_svzero_zav(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.zero(i32 255)
+// CHECK-NEXT:ret void
+//
+void test_svzero_za() {
+  svzero_za();
+}
Index: clang/lib/CodeGen/CodeGenFunction.h
===
--- clang/lib/CodeGen/CodeGenFunction.h
+++ clang/lib/CodeGen/CodeGenFunction.h
@@ -4256,6 +4256,9 @@
   llvm::Value *EmitSMEReadWrite(SMETypeFlags TypeFlags,
 llvm::SmallVectorImpl ,
 unsigned IntID);
+  llvm::Value *EmitSMEZero(SMETypeFlags TypeFlags,
+   llvm::SmallVectorImpl ,
+   unsigned IntID);
   llvm::Value *EmitAArch64SMEBuiltinExpr(unsigned BuiltinID, const CallExpr *E);
 
   llvm::Value *EmitAArch64BuiltinExpr(unsigned BuiltinID, const CallExpr *E,
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -9438,6 +9438,16 @@
   return Builder.CreateCall(F, Ops);
 }
 
+Value *CodeGenFunction::EmitSMEZero(SMETypeFlags TypeFlags,
+SmallVectorImpl ,
+unsigned IntID) {
+  // svzero_za() intrinsic zeros the entire za tile and has no paramters.
+  if (Ops.size() == 0)
+Ops.push_back(llvm::ConstantInt::get(Int32Ty, 255));
+  Function *F = CGM.getIntrinsic(IntID, {});
+  return Builder.CreateCall(F, Ops);
+}
+
 // Limit the usage of scalable llvm IR generated by the ACLE by using the
 // sve dup.x intrinsic instead of IRBuilder::CreateVectorSplat.
 Value *CodeGenFunction::EmitSVEDupX(Value *Scalar, llvm::Type *Ty) {
@@ -9894,6 +9904,8 @@
 return EmitSMELd1St1(TypeFlags, Ops, Builtin->LLVMIntrinsic);
   else if (TypeFlags.isMove())
 return EmitSMEReadWrite(TypeFlags, Ops, Builtin->LLVMIntrinsic);
+  else if (TypeFlags.isZero())
+return EmitSMEZero(TypeFlags, Ops, Builtin->LLVMIntrinsic);
 
   /// Should not happen
   return nullptr;
Index: clang/include/clang/Basic/arm_sve_sme_incl.td
===
--- clang/include/clang/Basic/arm_sve_sme_incl.td
+++ clang/include/clang/Basic/arm_sve_sme_incl.td
@@ -216,6 +216,7 @@
 def IsSharedZA: FlagType<0x20>;
 def IsPreservesZA : FlagType<0x40>;
 def IsMove: FlagType<0x80>;
+def IsZero: FlagType<0x100>;
 
 // These must be kept in sync 

[PATCH] D127910: [Clang][AArch64] Add SME C intrinsics for load and store

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc updated this revision to Diff 481205.
bryanpkc added a comment.

Removed some more unnecessary lines.


Repository:
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Files:
  clang/include/clang/Basic/BuiltinsSME.def
  clang/include/clang/Basic/CMakeLists.txt
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/Basic/arm_sme.td
  clang/include/clang/Basic/arm_sve.td
  clang/include/clang/Basic/arm_sve_sme_incl.td
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Sema/SemaDeclAttr.cpp
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_int_const_expr_error.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1_vnum.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1_vnum.c
  clang/utils/TableGen/SveEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h

Index: clang/utils/TableGen/TableGenBackends.h
===
--- clang/utils/TableGen/TableGenBackends.h
+++ clang/utils/TableGen/TableGenBackends.h
@@ -101,6 +101,12 @@
 void EmitSveTypeFlags(llvm::RecordKeeper , llvm::raw_ostream );
 void EmitSveRangeChecks(llvm::RecordKeeper , llvm::raw_ostream );
 
+void EmitSmeHeader(llvm::RecordKeeper , llvm::raw_ostream );
+void EmitSmeBuiltins(llvm::RecordKeeper , llvm::raw_ostream );
+void EmitSmeBuiltinCG(llvm::RecordKeeper , llvm::raw_ostream );
+void EmitSmeTypeFlags(llvm::RecordKeeper , llvm::raw_ostream );
+void EmitSmeRangeChecks(llvm::RecordKeeper , llvm::raw_ostream );
+
 void EmitMveHeader(llvm::RecordKeeper , llvm::raw_ostream );
 void EmitMveBuiltinDef(llvm::RecordKeeper , llvm::raw_ostream );
 void EmitMveBuiltinSema(llvm::RecordKeeper , llvm::raw_ostream );
Index: clang/utils/TableGen/TableGen.cpp
===
--- clang/utils/TableGen/TableGen.cpp
+++ clang/utils/TableGen/TableGen.cpp
@@ -81,6 +81,11 @@
   GenArmSveBuiltinCG,
   GenArmSveTypeFlags,
   GenArmSveRangeChecks,
+  GenArmSmeHeader,
+  GenArmSmeBuiltins,
+  GenArmSmeBuiltinCG,
+  GenArmSmeTypeFlags,
+  GenArmSmeRangeChecks,
   GenArmCdeHeader,
   GenArmCdeBuiltinDef,
   GenArmCdeBuiltinSema,
@@ -219,6 +224,16 @@
"Generate arm_sve_typeflags.inc for clang"),
 clEnumValN(GenArmSveRangeChecks, "gen-arm-sve-sema-rangechecks",
"Generate arm_sve_sema_rangechecks.inc for clang"),
+clEnumValN(GenArmSmeHeader, "gen-arm-sme-header",
+   "Generate arm_sme.h for clang"),
+clEnumValN(GenArmSmeBuiltins, "gen-arm-sme-builtins",
+   "Generate arm_sme_builtins.inc for clang"),
+clEnumValN(GenArmSmeBuiltinCG, "gen-arm-sme-builtin-codegen",
+   "Generate arm_sme_builtin_cg_map.inc for clang"),
+clEnumValN(GenArmSmeTypeFlags, "gen-arm-sme-typeflags",
+   "Generate arm_sme_typeflags.inc for clang"),
+clEnumValN(GenArmSmeRangeChecks, "gen-arm-sme-sema-rangechecks",
+   "Generate arm_sme_sema_rangechecks.inc for clang"),
 clEnumValN(GenArmMveHeader, "gen-arm-mve-header",
"Generate arm_mve.h for clang"),
 clEnumValN(GenArmMveBuiltinDef, "gen-arm-mve-builtin-def",
@@ -438,6 +453,21 @@
   case GenArmSveRangeChecks:
 EmitSveRangeChecks(Records, OS);
 break;
+  case GenArmSmeHeader:
+EmitSmeHeader(Records, OS);
+break;
+  case GenArmSmeBuiltins:
+EmitSmeBuiltins(Records, OS);
+break;
+  case GenArmSmeBuiltinCG:
+EmitSmeBuiltinCG(Records, OS);
+break;
+  case GenArmSmeTypeFlags:
+EmitSmeTypeFlags(Records, OS);
+break;
+  case GenArmSmeRangeChecks:
+EmitSmeRangeChecks(Records, OS);
+break;
   case GenArmCdeHeader:
 EmitCdeHeader(Records, OS);
 break;
Index: clang/utils/TableGen/SveEmitter.cpp
===
--- clang/utils/TableGen/SveEmitter.cpp
+++ clang/utils/TableGen/SveEmitter.cpp
@@ -228,7 +228,7 @@
   }
 
   /// Emits the intrinsic declaration to the ostream.
-  void emitIntrinsic(raw_ostream ) const;
+  void emitIntrinsic(raw_ostream , SVEEmitter ) const;
 
 private:
   std::string getMergeSuffix() const { return MergeSuffix; }
@@ -346,8 +346,24 @@
   /// Create the SVETypeFlags used in CGBuiltins
   void createTypeFlags(raw_ostream );
 
+  /// Emit arm_sme.h.
+  void createSMEHeader(raw_ostream );
+
+  /// Emit all the SME __builtin prototypes and code needed by Sema.
+  void createSMEBuiltins(raw_ostream );
+
+  /// Emit all the information needed to map builtin -> LLVM IR intrinsic.
+  void createSMECodeGenMap(raw_ostream );
+
+  /// Emit all the range checks for the immediates.
+  

[PATCH] D127910: [Clang][AArch64] Add SME C intrinsics for load and store

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc updated this revision to Diff 481137.
bryanpkc added a comment.

Removed some diffs that weren't necessary.


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Files:
  clang/include/clang/Basic/BuiltinsSME.def
  clang/include/clang/Basic/CMakeLists.txt
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/Basic/arm_sme.td
  clang/include/clang/Basic/arm_sve.td
  clang/include/clang/Basic/arm_sve_sme_incl.td
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Sema/SemaDeclAttr.cpp
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_int_const_expr_error.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1_vnum.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1_vnum.c
  clang/utils/TableGen/SveEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h

Index: clang/utils/TableGen/TableGenBackends.h
===
--- clang/utils/TableGen/TableGenBackends.h
+++ clang/utils/TableGen/TableGenBackends.h
@@ -101,6 +101,12 @@
 void EmitSveTypeFlags(llvm::RecordKeeper , llvm::raw_ostream );
 void EmitSveRangeChecks(llvm::RecordKeeper , llvm::raw_ostream );
 
+void EmitSmeHeader(llvm::RecordKeeper , llvm::raw_ostream );
+void EmitSmeBuiltins(llvm::RecordKeeper , llvm::raw_ostream );
+void EmitSmeBuiltinCG(llvm::RecordKeeper , llvm::raw_ostream );
+void EmitSmeTypeFlags(llvm::RecordKeeper , llvm::raw_ostream );
+void EmitSmeRangeChecks(llvm::RecordKeeper , llvm::raw_ostream );
+
 void EmitMveHeader(llvm::RecordKeeper , llvm::raw_ostream );
 void EmitMveBuiltinDef(llvm::RecordKeeper , llvm::raw_ostream );
 void EmitMveBuiltinSema(llvm::RecordKeeper , llvm::raw_ostream );
Index: clang/utils/TableGen/TableGen.cpp
===
--- clang/utils/TableGen/TableGen.cpp
+++ clang/utils/TableGen/TableGen.cpp
@@ -81,6 +81,11 @@
   GenArmSveBuiltinCG,
   GenArmSveTypeFlags,
   GenArmSveRangeChecks,
+  GenArmSmeHeader,
+  GenArmSmeBuiltins,
+  GenArmSmeBuiltinCG,
+  GenArmSmeTypeFlags,
+  GenArmSmeRangeChecks,
   GenArmCdeHeader,
   GenArmCdeBuiltinDef,
   GenArmCdeBuiltinSema,
@@ -219,6 +224,16 @@
"Generate arm_sve_typeflags.inc for clang"),
 clEnumValN(GenArmSveRangeChecks, "gen-arm-sve-sema-rangechecks",
"Generate arm_sve_sema_rangechecks.inc for clang"),
+clEnumValN(GenArmSmeHeader, "gen-arm-sme-header",
+   "Generate arm_sme.h for clang"),
+clEnumValN(GenArmSmeBuiltins, "gen-arm-sme-builtins",
+   "Generate arm_sme_builtins.inc for clang"),
+clEnumValN(GenArmSmeBuiltinCG, "gen-arm-sme-builtin-codegen",
+   "Generate arm_sme_builtin_cg_map.inc for clang"),
+clEnumValN(GenArmSmeTypeFlags, "gen-arm-sme-typeflags",
+   "Generate arm_sme_typeflags.inc for clang"),
+clEnumValN(GenArmSmeRangeChecks, "gen-arm-sme-sema-rangechecks",
+   "Generate arm_sme_sema_rangechecks.inc for clang"),
 clEnumValN(GenArmMveHeader, "gen-arm-mve-header",
"Generate arm_mve.h for clang"),
 clEnumValN(GenArmMveBuiltinDef, "gen-arm-mve-builtin-def",
@@ -438,6 +453,21 @@
   case GenArmSveRangeChecks:
 EmitSveRangeChecks(Records, OS);
 break;
+  case GenArmSmeHeader:
+EmitSmeHeader(Records, OS);
+break;
+  case GenArmSmeBuiltins:
+EmitSmeBuiltins(Records, OS);
+break;
+  case GenArmSmeBuiltinCG:
+EmitSmeBuiltinCG(Records, OS);
+break;
+  case GenArmSmeTypeFlags:
+EmitSmeTypeFlags(Records, OS);
+break;
+  case GenArmSmeRangeChecks:
+EmitSmeRangeChecks(Records, OS);
+break;
   case GenArmCdeHeader:
 EmitCdeHeader(Records, OS);
 break;
Index: clang/utils/TableGen/SveEmitter.cpp
===
--- clang/utils/TableGen/SveEmitter.cpp
+++ clang/utils/TableGen/SveEmitter.cpp
@@ -228,7 +228,7 @@
   }
 
   /// Emits the intrinsic declaration to the ostream.
-  void emitIntrinsic(raw_ostream ) const;
+  void emitIntrinsic(raw_ostream , SVEEmitter ) const;
 
 private:
   std::string getMergeSuffix() const { return MergeSuffix; }
@@ -346,8 +346,24 @@
   /// Create the SVETypeFlags used in CGBuiltins
   void createTypeFlags(raw_ostream );
 
+  /// Emit arm_sme.h.
+  void createSMEHeader(raw_ostream );
+
+  /// Emit all the SME __builtin prototypes and code needed by Sema.
+  void createSMEBuiltins(raw_ostream );
+
+  /// Emit all the information needed to map builtin -> LLVM IR intrinsic.
+  void createSMECodeGenMap(raw_ostream );
+
+  /// Emit all the range checks for the 

[PATCH] D127910: [Clang][AArch64] Add SME C intrinsics for load and store

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc marked 2 inline comments as done.
bryanpkc added a comment.

@david-arm, I have moved all the SME definitions into a new file, arm_sme.td. I 
have moved the common definitions into another file, arm_sve_sme_incl.td, which 
will be included by both arm_sve.td and arm_sme.td. SveEmitter has been updated 
to incorporate your suggestions.


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[PATCH] D127910: [Clang][AArch64] Add SME C intrinsics for load and store

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc updated this revision to Diff 481132.
bryanpkc marked 5 inline comments as done.
bryanpkc edited the summary of this revision.
bryanpkc added a comment.
Herald added a subscriber: mgrang.
Herald added a reviewer: aaron.ballman.

Updated the patch according to review comments which suggest to treat SME as a 
different architecture.


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Files:
  clang/include/clang/Basic/BuiltinsSME.def
  clang/include/clang/Basic/CMakeLists.txt
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/Basic/arm_sme.td
  clang/include/clang/Basic/arm_sve.td
  clang/include/clang/Basic/arm_sve_sme_incl.td
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Sema/SemaDeclAttr.cpp
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_int_const_expr_error.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1_vnum.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1_vnum.c
  clang/utils/TableGen/SveEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h

Index: clang/utils/TableGen/TableGenBackends.h
===
--- clang/utils/TableGen/TableGenBackends.h
+++ clang/utils/TableGen/TableGenBackends.h
@@ -101,6 +101,12 @@
 void EmitSveTypeFlags(llvm::RecordKeeper , llvm::raw_ostream );
 void EmitSveRangeChecks(llvm::RecordKeeper , llvm::raw_ostream );
 
+void EmitSmeHeader(llvm::RecordKeeper , llvm::raw_ostream );
+void EmitSmeBuiltins(llvm::RecordKeeper , llvm::raw_ostream );
+void EmitSmeBuiltinCG(llvm::RecordKeeper , llvm::raw_ostream );
+void EmitSmeTypeFlags(llvm::RecordKeeper , llvm::raw_ostream );
+void EmitSmeRangeChecks(llvm::RecordKeeper , llvm::raw_ostream );
+
 void EmitMveHeader(llvm::RecordKeeper , llvm::raw_ostream );
 void EmitMveBuiltinDef(llvm::RecordKeeper , llvm::raw_ostream );
 void EmitMveBuiltinSema(llvm::RecordKeeper , llvm::raw_ostream );
Index: clang/utils/TableGen/TableGen.cpp
===
--- clang/utils/TableGen/TableGen.cpp
+++ clang/utils/TableGen/TableGen.cpp
@@ -81,6 +81,11 @@
   GenArmSveBuiltinCG,
   GenArmSveTypeFlags,
   GenArmSveRangeChecks,
+  GenArmSmeHeader,
+  GenArmSmeBuiltins,
+  GenArmSmeBuiltinCG,
+  GenArmSmeTypeFlags,
+  GenArmSmeRangeChecks,
   GenArmCdeHeader,
   GenArmCdeBuiltinDef,
   GenArmCdeBuiltinSema,
@@ -219,6 +224,16 @@
"Generate arm_sve_typeflags.inc for clang"),
 clEnumValN(GenArmSveRangeChecks, "gen-arm-sve-sema-rangechecks",
"Generate arm_sve_sema_rangechecks.inc for clang"),
+clEnumValN(GenArmSmeHeader, "gen-arm-sme-header",
+   "Generate arm_sme.h for clang"),
+clEnumValN(GenArmSmeBuiltins, "gen-arm-sme-builtins",
+   "Generate arm_sme_builtins.inc for clang"),
+clEnumValN(GenArmSmeBuiltinCG, "gen-arm-sme-builtin-codegen",
+   "Generate arm_sme_builtin_cg_map.inc for clang"),
+clEnumValN(GenArmSmeTypeFlags, "gen-arm-sme-typeflags",
+   "Generate arm_sme_typeflags.inc for clang"),
+clEnumValN(GenArmSmeRangeChecks, "gen-arm-sme-sema-rangechecks",
+   "Generate arm_sme_sema_rangechecks.inc for clang"),
 clEnumValN(GenArmMveHeader, "gen-arm-mve-header",
"Generate arm_mve.h for clang"),
 clEnumValN(GenArmMveBuiltinDef, "gen-arm-mve-builtin-def",
@@ -438,6 +453,21 @@
   case GenArmSveRangeChecks:
 EmitSveRangeChecks(Records, OS);
 break;
+  case GenArmSmeHeader:
+EmitSmeHeader(Records, OS);
+break;
+  case GenArmSmeBuiltins:
+EmitSmeBuiltins(Records, OS);
+break;
+  case GenArmSmeBuiltinCG:
+EmitSmeBuiltinCG(Records, OS);
+break;
+  case GenArmSmeTypeFlags:
+EmitSmeTypeFlags(Records, OS);
+break;
+  case GenArmSmeRangeChecks:
+EmitSmeRangeChecks(Records, OS);
+break;
   case GenArmCdeHeader:
 EmitCdeHeader(Records, OS);
 break;
Index: clang/utils/TableGen/SveEmitter.cpp
===
--- clang/utils/TableGen/SveEmitter.cpp
+++ clang/utils/TableGen/SveEmitter.cpp
@@ -169,6 +169,9 @@
 
   SmallVector ImmChecks;
 
+  /// Extra attributes for the intrinsic declaration.
+  std::string DeclAttrs;
+
 public:
   Intrinsic(StringRef Name, StringRef Proto, uint64_t MergeTy,
 StringRef MergeSuffix, uint64_t MemoryElementTy, StringRef LLVMName,
@@ -196,6 +199,9 @@
 
   ArrayRef getImmChecks() const { return ImmChecks; }
 
+  /// Return a comma seperated string of declaration attributes.
+  std::string getDeclAttrs() const { return DeclAttrs; }

[PATCH] D127910: [Clang][AArch64] Add SME C intrinsics for load and store

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc commandeered this revision.
bryanpkc added a reviewer: sagarkulkarni19.
bryanpkc added a comment.

In D127910#3885699 , @david-arm wrote:

> Hi @sagarkulkarni19, just a gentle ping to see if you are still planning to 
> do more work on this patch?

@david-arm we are going to update this patch very soon. Sorry for the delays.


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[PATCH] D97080: [flang][driver] Add -fintrinsic-modules-path option

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc added inline comments.



Comment at: flang/lib/Frontend/CompilerInvocation.cpp:292
+  std::string driverPath = llvm::sys::fs::getMainExecutable(nullptr, nullptr);
+  driverPath = driverPath.substr(0, driverPath.size() - 9);
+  return driverPath.append("/../include/flang/");

Can you use `llvm::sys::path::remove_filename` here?


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[PATCH] D97119: [flang][driver] Add options for -std=f2018

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc added a comment.

I agree with @richard.barton.arm that we could add `-std=` now, even if only 
for a subset of possible language standards. I expect that standard conformance 
checks would be quite pervasive, and it would be better to design the 
infrastructure for such checks earlier rather than try to retrofit them at a 
later stage when we have to start supporting f202x, etc.


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[PATCH] D63329: Allow static linking of libc++ on Linux, just like -static-libstdc++

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc added a comment.
Herald added a subscriber: dang.

@erikjv Are you still working on this? Or is a better alternative being 
pursued? IIUC, this functionality is still missing in trunk.


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[PATCH] D89972: Add pipeline model for HiSilicon's TSV110

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc added inline comments.



Comment at: llvm/lib/Target/AArch64/AArch64SchedTSV110.td:9
+//
+// This file defines the machine model for ARM Huawei TSV110 to support
+// instruction scheduling and other instruction cost heuristics.

I suggest deleting the word `ARM` here to avoid confusion.



Comment at: llvm/lib/Target/AArch64/AArch64SchedTSV110.td:28
+  list UnsupportedFeatures = !listconcat(SVEUnsupported.F,
+   PAUnsupported.F);
+}

Indent to align with the previous argument?



Comment at: llvm/lib/Target/AArch64/AArch64SchedTSV110.td:53
+
+//Integer ALU
+def : WriteRes { let Latency = 1; }

Nit: Leave a space after the `//` delimiter.



Comment at: llvm/lib/Target/AArch64/AArch64SchedTSV110.td:128
+
+// Detailed Refinedments
+//===--===//

Type: `Refinements`


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[PATCH] D70804: [Frontend] Allow OpenMP offloading to aarch64

[Bryan Chan via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG74e6ce2529fa: [Frontend] Allow OpenMP offloading to aarch64 
(authored by bryanpkc).

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Files:
  clang/lib/Frontend/CompilerInvocation.cpp
  clang/test/OpenMP/openmp_offload_registration.cpp


Index: clang/test/OpenMP/openmp_offload_registration.cpp
===
--- clang/test/OpenMP/openmp_offload_registration.cpp
+++ clang/test/OpenMP/openmp_offload_registration.cpp
@@ -1,5 +1,6 @@
-// Test for offload registration code for two targets
+// Test offload registration for two targets, and test offload target 
validation.
 // RUN: %clang_cc1 -verify -fopenmp -x c -triple x86_64-unknown-linux-gnu 
-fopenmp-targets=x86_64-pc-linux-gnu,powerpc64le-ibm-linux-gnu -emit-llvm %s -o 
- | FileCheck %s
+// RUN: %clang_cc1 -verify -fopenmp -x c -triple x86_64-unknown-linux-gnu 
-fopenmp-targets=aarch64-unknown-linux-gnu -emit-llvm %s -o - | FileCheck %s
 // expected-no-diagnostics
 
 void foo() {
Index: clang/lib/Frontend/CompilerInvocation.cpp
===
--- clang/lib/Frontend/CompilerInvocation.cpp
+++ clang/lib/Frontend/CompilerInvocation.cpp
@@ -3070,7 +3070,8 @@
   llvm::Triple TT(A->getValue(i));
 
   if (TT.getArch() == llvm::Triple::UnknownArch ||
-  !(TT.getArch() == llvm::Triple::ppc ||
+  !(TT.getArch() == llvm::Triple::aarch64 ||
+TT.getArch() == llvm::Triple::ppc ||
 TT.getArch() == llvm::Triple::ppc64 ||
 TT.getArch() == llvm::Triple::ppc64le ||
 TT.getArch() == llvm::Triple::nvptx ||


Index: clang/test/OpenMP/openmp_offload_registration.cpp
===
--- clang/test/OpenMP/openmp_offload_registration.cpp
+++ clang/test/OpenMP/openmp_offload_registration.cpp
@@ -1,5 +1,6 @@
-// Test for offload registration code for two targets
+// Test offload registration for two targets, and test offload target validation.
 // RUN: %clang_cc1 -verify -fopenmp -x c -triple x86_64-unknown-linux-gnu -fopenmp-targets=x86_64-pc-linux-gnu,powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -verify -fopenmp -x c -triple x86_64-unknown-linux-gnu -fopenmp-targets=aarch64-unknown-linux-gnu -emit-llvm %s -o - | FileCheck %s
 // expected-no-diagnostics
 
 void foo() {
Index: clang/lib/Frontend/CompilerInvocation.cpp
===
--- clang/lib/Frontend/CompilerInvocation.cpp
+++ clang/lib/Frontend/CompilerInvocation.cpp
@@ -3070,7 +3070,8 @@
   llvm::Triple TT(A->getValue(i));
 
   if (TT.getArch() == llvm::Triple::UnknownArch ||
-  !(TT.getArch() == llvm::Triple::ppc ||
+  !(TT.getArch() == llvm::Triple::aarch64 ||
+TT.getArch() == llvm::Triple::ppc ||
 TT.getArch() == llvm::Triple::ppc64 ||
 TT.getArch() == llvm::Triple::ppc64le ||
 TT.getArch() == llvm::Triple::nvptx ||
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[PATCH] D70804: [Frontend] Allow OpenMP offloading to aarch64

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc updated this revision to Diff 232627.
bryanpkc marked 2 inline comments as done.
bryanpkc added a comment.

Removed unrelated changes from this patch.


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Files:
  clang/lib/Frontend/CompilerInvocation.cpp
  clang/test/OpenMP/openmp_offload_registration.cpp


Index: clang/test/OpenMP/openmp_offload_registration.cpp
===
--- clang/test/OpenMP/openmp_offload_registration.cpp
+++ clang/test/OpenMP/openmp_offload_registration.cpp
@@ -1,5 +1,6 @@
-// Test for offload registration code for two targets
+// Test offload registration for two targets, and test offload target 
validation.
 // RUN: %clang_cc1 -verify -fopenmp -x c -triple x86_64-unknown-linux-gnu 
-fopenmp-targets=x86_64-pc-linux-gnu,powerpc64le-ibm-linux-gnu -emit-llvm %s -o 
- | FileCheck %s
+// RUN: %clang_cc1 -verify -fopenmp -x c -triple x86_64-unknown-linux-gnu 
-fopenmp-targets=aarch64-unknown-linux-gnu -emit-llvm %s -o - | FileCheck %s
 // expected-no-diagnostics
 
 void foo() {
Index: clang/lib/Frontend/CompilerInvocation.cpp
===
--- clang/lib/Frontend/CompilerInvocation.cpp
+++ clang/lib/Frontend/CompilerInvocation.cpp
@@ -3070,7 +3070,8 @@
   llvm::Triple TT(A->getValue(i));
 
   if (TT.getArch() == llvm::Triple::UnknownArch ||
-  !(TT.getArch() == llvm::Triple::ppc ||
+  !(TT.getArch() == llvm::Triple::aarch64 ||
+TT.getArch() == llvm::Triple::ppc ||
 TT.getArch() == llvm::Triple::ppc64 ||
 TT.getArch() == llvm::Triple::ppc64le ||
 TT.getArch() == llvm::Triple::nvptx ||


Index: clang/test/OpenMP/openmp_offload_registration.cpp
===
--- clang/test/OpenMP/openmp_offload_registration.cpp
+++ clang/test/OpenMP/openmp_offload_registration.cpp
@@ -1,5 +1,6 @@
-// Test for offload registration code for two targets
+// Test offload registration for two targets, and test offload target validation.
 // RUN: %clang_cc1 -verify -fopenmp -x c -triple x86_64-unknown-linux-gnu -fopenmp-targets=x86_64-pc-linux-gnu,powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -verify -fopenmp -x c -triple x86_64-unknown-linux-gnu -fopenmp-targets=aarch64-unknown-linux-gnu -emit-llvm %s -o - | FileCheck %s
 // expected-no-diagnostics
 
 void foo() {
Index: clang/lib/Frontend/CompilerInvocation.cpp
===
--- clang/lib/Frontend/CompilerInvocation.cpp
+++ clang/lib/Frontend/CompilerInvocation.cpp
@@ -3070,7 +3070,8 @@
   llvm::Triple TT(A->getValue(i));
 
   if (TT.getArch() == llvm::Triple::UnknownArch ||
-  !(TT.getArch() == llvm::Triple::ppc ||
+  !(TT.getArch() == llvm::Triple::aarch64 ||
+TT.getArch() == llvm::Triple::ppc ||
 TT.getArch() == llvm::Triple::ppc64 ||
 TT.getArch() == llvm::Triple::ppc64le ||
 TT.getArch() == llvm::Triple::nvptx ||
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[PATCH] D70804: [Frontend] Allow OpenMP offloading to aarch64

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc marked 6 inline comments as done.
bryanpkc added inline comments.



Comment at: clang/test/OpenMP/openmp_offload_registration.cpp:3-5
+// RUN: %clang_cc1 -verify -fopenmp -x c -triple x86_64-unknown-linux-gnu 
-fopenmp-targets=aarch64-unknown-linux-gnu,powerpc64-ibm-linux-gnu -emit-llvm 
%s -o - | FileCheck %s
+// RUN: %clang_cc1 -verify -fopenmp -x c -triple x86_64-unknown-linux-gnu 
-fopenmp-targets=i686-pclinux-gnu,powerpc-ibm-linux-gnu -emit-llvm %s -o - | 
FileCheck %s
+// RUN: %clang_cc1 -verify -fopenmp -x c -triple x86_64-unknown-linux-gnu 
-fopenmp-targets=nvptx-nvidia-cuda,nvptx64-nvidia-cuda -emit-llvm %s -o - | 
FileCheck %s

ABataev wrote:
> Do not add tests targets other than aarch64
OK, thank you.



Comment at: clang/test/OpenMP/target_messages.cpp:4
+
+// RUN: not %clang_cc1 -fopenmp -std=c++11 -fopenmp-targets=aaa-bbb-ccc-ddd -o 
- %s 2>&1 | FileCheck %s
 // CHECK: error: OpenMP target is invalid: 'aaa-bbb-ccc-ddd'

ABataev wrote:
> bryanpkc wrote:
> > ABataev wrote:
> > > Why do you need the changes in this file?
> > The clean-up is not strictly necessary. I came across this file when I was 
> > looking for the right file to add the tests, and thought it would be better 
> > to group similar tests (and their corresponding CHECK patterns) together.
> Do not do this in this patch, these changes are not related to the patch 
> itself.
OK, I will remove these changes.


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[PATCH] D70804: [Frontend] Allow OpenMP offloading to aarch64

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc added inline comments.



Comment at: clang/test/OpenMP/target_messages.cpp:4
+
+// RUN: not %clang_cc1 -fopenmp -std=c++11 -fopenmp-targets=aaa-bbb-ccc-ddd -o 
- %s 2>&1 | FileCheck %s
 // CHECK: error: OpenMP target is invalid: 'aaa-bbb-ccc-ddd'

ABataev wrote:
> Why do you need the changes in this file?
The clean-up is not strictly necessary. I came across this file when I was 
looking for the right file to add the tests, and thought it would be better to 
group similar tests (and their corresponding CHECK patterns) together.


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[PATCH] D70804: [Frontend] Allow OpenMP offloading to aarch64

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc added a comment.

Pinging reviewers.


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[PATCH] D70804: [Frontend] Allow OpenMP offloading to aarch64

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc updated this revision to Diff 231582.
bryanpkc added a comment.

Add tests for -fopenmp-targets=.


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Files:
  clang/lib/Frontend/CompilerInvocation.cpp
  clang/test/OpenMP/openmp_offload_registration.cpp
  clang/test/OpenMP/target_messages.cpp


Index: clang/test/OpenMP/target_messages.cpp
===
--- clang/test/OpenMP/target_messages.cpp
+++ clang/test/OpenMP/target_messages.cpp
@@ -1,11 +1,13 @@
 // RUN: %clang_cc1 -verify -fopenmp -std=c++11 -o - %s
-// RUN: not %clang_cc1 -fopenmp -std=c++11 -fopenmp-targets=aaa-bbb-ccc-ddd -o 
- %s 2>&1 | FileCheck %s
-
 // RUN: %clang_cc1 -verify -fopenmp-simd -std=c++11 -o - %s
+
+// RUN: not %clang_cc1 -fopenmp -std=c++11 -fopenmp-targets=aaa-bbb-ccc-ddd -o 
- %s 2>&1 | FileCheck %s
 // CHECK: error: OpenMP target is invalid: 'aaa-bbb-ccc-ddd'
+
 // RUN: not %clang_cc1 -fopenmp -std=c++11 -triple nvptx64-nvidia-cuda -o - %s 
2>&1 | FileCheck --check-prefix CHECK-UNSUPPORTED-HOST-TARGET %s
 // RUN: not %clang_cc1 -fopenmp -std=c++11 -triple nvptx-nvidia-cuda -o - %s 
2>&1 | FileCheck --check-prefix CHECK-UNSUPPORTED-HOST-TARGET %s
 // CHECK-UNSUPPORTED-HOST-TARGET: error: The target 
'{{nvptx64-nvidia-cuda|nvptx-nvidia-cuda}}' is not a supported OpenMP host 
target.
+
 // RUN: not %clang_cc1 -fopenmp -std=c++11 -fopenmp-targets=hexagon-linux-gnu 
-o - %s 2>&1 | FileCheck --check-prefix CHECK-UNSUPPORTED-DEVICE-TARGET %s
 // CHECK-UNSUPPORTED-DEVICE-TARGET: OpenMP target is invalid: 
'hexagon-linux-gnu'
 
Index: clang/test/OpenMP/openmp_offload_registration.cpp
===
--- clang/test/OpenMP/openmp_offload_registration.cpp
+++ clang/test/OpenMP/openmp_offload_registration.cpp
@@ -1,5 +1,8 @@
-// Test for offload registration code for two targets
+// Test offload registration for two targets, and test offload target 
validation.
 // RUN: %clang_cc1 -verify -fopenmp -x c -triple x86_64-unknown-linux-gnu 
-fopenmp-targets=x86_64-pc-linux-gnu,powerpc64le-ibm-linux-gnu -emit-llvm %s -o 
- | FileCheck %s
+// RUN: %clang_cc1 -verify -fopenmp -x c -triple x86_64-unknown-linux-gnu 
-fopenmp-targets=aarch64-unknown-linux-gnu,powerpc64-ibm-linux-gnu -emit-llvm 
%s -o - | FileCheck %s
+// RUN: %clang_cc1 -verify -fopenmp -x c -triple x86_64-unknown-linux-gnu 
-fopenmp-targets=i686-pclinux-gnu,powerpc-ibm-linux-gnu -emit-llvm %s -o - | 
FileCheck %s
+// RUN: %clang_cc1 -verify -fopenmp -x c -triple x86_64-unknown-linux-gnu 
-fopenmp-targets=nvptx-nvidia-cuda,nvptx64-nvidia-cuda -emit-llvm %s -o - | 
FileCheck %s
 // expected-no-diagnostics
 
 void foo() {
Index: clang/lib/Frontend/CompilerInvocation.cpp
===
--- clang/lib/Frontend/CompilerInvocation.cpp
+++ clang/lib/Frontend/CompilerInvocation.cpp
@@ -3070,7 +3070,8 @@
   llvm::Triple TT(A->getValue(i));
 
   if (TT.getArch() == llvm::Triple::UnknownArch ||
-  !(TT.getArch() == llvm::Triple::ppc ||
+  !(TT.getArch() == llvm::Triple::aarch64 ||
+TT.getArch() == llvm::Triple::ppc ||
 TT.getArch() == llvm::Triple::ppc64 ||
 TT.getArch() == llvm::Triple::ppc64le ||
 TT.getArch() == llvm::Triple::nvptx ||


Index: clang/test/OpenMP/target_messages.cpp
===
--- clang/test/OpenMP/target_messages.cpp
+++ clang/test/OpenMP/target_messages.cpp
@@ -1,11 +1,13 @@
 // RUN: %clang_cc1 -verify -fopenmp -std=c++11 -o - %s
-// RUN: not %clang_cc1 -fopenmp -std=c++11 -fopenmp-targets=aaa-bbb-ccc-ddd -o - %s 2>&1 | FileCheck %s
-
 // RUN: %clang_cc1 -verify -fopenmp-simd -std=c++11 -o - %s
+
+// RUN: not %clang_cc1 -fopenmp -std=c++11 -fopenmp-targets=aaa-bbb-ccc-ddd -o - %s 2>&1 | FileCheck %s
 // CHECK: error: OpenMP target is invalid: 'aaa-bbb-ccc-ddd'
+
 // RUN: not %clang_cc1 -fopenmp -std=c++11 -triple nvptx64-nvidia-cuda -o - %s 2>&1 | FileCheck --check-prefix CHECK-UNSUPPORTED-HOST-TARGET %s
 // RUN: not %clang_cc1 -fopenmp -std=c++11 -triple nvptx-nvidia-cuda -o - %s 2>&1 | FileCheck --check-prefix CHECK-UNSUPPORTED-HOST-TARGET %s
 // CHECK-UNSUPPORTED-HOST-TARGET: error: The target '{{nvptx64-nvidia-cuda|nvptx-nvidia-cuda}}' is not a supported OpenMP host target.
+
 // RUN: not %clang_cc1 -fopenmp -std=c++11 -fopenmp-targets=hexagon-linux-gnu -o - %s 2>&1 | FileCheck --check-prefix CHECK-UNSUPPORTED-DEVICE-TARGET %s
 // CHECK-UNSUPPORTED-DEVICE-TARGET: OpenMP target is invalid: 'hexagon-linux-gnu'
 
Index: clang/test/OpenMP/openmp_offload_registration.cpp
===
--- clang/test/OpenMP/openmp_offload_registration.cpp
+++ clang/test/OpenMP/openmp_offload_registration.cpp
@@ -1,5 +1,8 @@
-// Test for offload registration code 

[PATCH] D70804: [Frontend] Allow OpenMP offloading to aarch64

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc added a comment.

In D70804#1763289 , @ABataev wrote:

> Tests are required


The tests for this were added in D30644 , but 
they are currently failing on AArch64 due to D32035 
. This patch allows those tests to pass again. 
What further testing should I add?


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[PATCH] D70804: [Frontend] Allow OpenMP offloading to aarch64

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc created this revision.
bryanpkc added reviewers: pawosm01, gtbercea.
Herald added subscribers: cfe-commits, guansong, kristof.beyls.
Herald added a reviewer: jdoerfert.
Herald added a project: clang.

D30644  added OpenMP offloading to AArch64 
targets, then D32035  changed the
frontend to throw an error when offloading is requested for an unsupported
target architecture. However the latter did not include AArch64 in the list
of supported architectures, causing the following unit tests to fail:

  libomptarget :: api/omp_get_num_devices.c
  libomptarget :: mapping/pr38704.c
  libomptarget :: offloading/offloading_success.c
  libomptarget :: offloading/offloading_success.cpp


Repository:
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Files:
  clang/lib/Frontend/CompilerInvocation.cpp


Index: clang/lib/Frontend/CompilerInvocation.cpp
===
--- clang/lib/Frontend/CompilerInvocation.cpp
+++ clang/lib/Frontend/CompilerInvocation.cpp
@@ -3070,7 +3070,8 @@
   llvm::Triple TT(A->getValue(i));
 
   if (TT.getArch() == llvm::Triple::UnknownArch ||
-  !(TT.getArch() == llvm::Triple::ppc ||
+  !(TT.getArch() == llvm::Triple::aarch64 ||
+TT.getArch() == llvm::Triple::ppc ||
 TT.getArch() == llvm::Triple::ppc64 ||
 TT.getArch() == llvm::Triple::ppc64le ||
 TT.getArch() == llvm::Triple::nvptx ||


Index: clang/lib/Frontend/CompilerInvocation.cpp
===
--- clang/lib/Frontend/CompilerInvocation.cpp
+++ clang/lib/Frontend/CompilerInvocation.cpp
@@ -3070,7 +3070,8 @@
   llvm::Triple TT(A->getValue(i));
 
   if (TT.getArch() == llvm::Triple::UnknownArch ||
-  !(TT.getArch() == llvm::Triple::ppc ||
+  !(TT.getArch() == llvm::Triple::aarch64 ||
+TT.getArch() == llvm::Triple::ppc ||
 TT.getArch() == llvm::Triple::ppc64 ||
 TT.getArch() == llvm::Triple::ppc64le ||
 TT.getArch() == llvm::Triple::nvptx ||
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[PATCH] D53633: [AArch64] Implement FP16FML intrinsics

[Bryan Chan via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL345344: [AArch64] Implement FP16FML intrinsics (authored by 
bryanpkc, committed by ).
Herald added a subscriber: llvm-commits.

Changed prior to commit:
  https://reviews.llvm.org/D53633?vs=170811=171230#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D53633

Files:
  cfe/trunk/include/clang/Basic/arm_neon.td
  cfe/trunk/include/clang/Basic/arm_neon_incl.td
  cfe/trunk/lib/Basic/Targets/AArch64.cpp
  cfe/trunk/lib/Basic/Targets/AArch64.h
  cfe/trunk/lib/CodeGen/CGBuiltin.cpp
  cfe/trunk/test/CodeGen/aarch64-neon-fp16fml.c
  cfe/trunk/test/Preprocessor/aarch64-target-features.c
  cfe/trunk/utils/TableGen/NeonEmitter.cpp

Index: cfe/trunk/utils/TableGen/NeonEmitter.cpp
===
--- cfe/trunk/utils/TableGen/NeonEmitter.cpp
+++ cfe/trunk/utils/TableGen/NeonEmitter.cpp
@@ -494,6 +494,7 @@
 std::pair emitDagSaveTemp(DagInit *DI);
 std::pair emitDagSplat(DagInit *DI);
 std::pair emitDagDup(DagInit *DI);
+std::pair emitDagDupTyped(DagInit *DI);
 std::pair emitDagShuffle(DagInit *DI);
 std::pair emitDagCast(DagInit *DI, bool IsBitCast);
 std::pair emitDagCall(DagInit *DI);
@@ -897,6 +898,18 @@
 Float = true;
 ElementBitwidth = 16;
 break;
+  case '0':
+Float = true;
+if (AppliedQuad)
+  Bitwidth /= 2;
+ElementBitwidth = 16;
+break;
+  case '1':
+Float = true;
+if (!AppliedQuad)
+  Bitwidth *= 2;
+ElementBitwidth = 16;
+break;
   case 'g':
 if (AppliedQuad)
   Bitwidth /= 2;
@@ -1507,6 +1520,8 @@
 return emitDagShuffle(DI);
   if (Op == "dup")
 return emitDagDup(DI);
+  if (Op == "dup_typed")
+return emitDagDupTyped(DI);
   if (Op == "splat")
 return emitDagSplat(DI);
   if (Op == "save_temp")
@@ -1771,6 +1786,28 @@
   return std::make_pair(T, S);
 }
 
+std::pair Intrinsic::DagEmitter::emitDagDupTyped(DagInit *DI) {
+  assert_with_loc(DI->getNumArgs() == 2, "dup_typed() expects two arguments");
+  std::pair A = emitDagArg(DI->getArg(0),
+  DI->getArgNameStr(0));
+  std::pair B = emitDagArg(DI->getArg(1),
+  DI->getArgNameStr(1));
+  assert_with_loc(B.first.isScalar(),
+  "dup_typed() requires a scalar as the second argument");
+
+  Type T = A.first;
+  assert_with_loc(T.isVector(), "dup_typed() used but target type is scalar!");
+  std::string S = "(" + T.str() + ") {";
+  for (unsigned I = 0; I < T.getNumElements(); ++I) {
+if (I != 0)
+  S += ", ";
+S += B.second;
+  }
+  S += "}";
+
+  return std::make_pair(T, S);
+}
+
 std::pair Intrinsic::DagEmitter::emitDagSplat(DagInit *DI) {
   assert_with_loc(DI->getNumArgs() == 2, "splat() expects two arguments");
   std::pair A = emitDagArg(DI->getArg(0),
Index: cfe/trunk/include/clang/Basic/arm_neon.td
===
--- cfe/trunk/include/clang/Basic/arm_neon.td
+++ cfe/trunk/include/clang/Basic/arm_neon.td
@@ -206,6 +206,15 @@
 : Op<(call "vdot", $p0, $p1,
   (bitcast $p1, (splat(bitcast "uint32x4_t", $p2), $p3)))>;
 
+def OP_FMLAL_LN : Op<(call "vfmlal_low", $p0, $p1,
+   (dup_typed $p1, (call "vget_lane", $p2, $p3)))>;
+def OP_FMLSL_LN : Op<(call "vfmlsl_low", $p0, $p1,
+   (dup_typed $p1, (call "vget_lane", $p2, $p3)))>;
+def OP_FMLAL_LN_Hi  : Op<(call "vfmlal_high", $p0, $p1,
+   (dup_typed $p1, (call "vget_lane", $p2, $p3)))>;
+def OP_FMLSL_LN_Hi  : Op<(call "vfmlsl_high", $p0, $p1,
+   (dup_typed $p1, (call "vget_lane", $p2, $p3)))>;
+
 //===--===//
 // Instructions
 //===--===//
@@ -1640,3 +1649,21 @@
   // Variants indexing into a 128-bit vector are A64 only.
   def UDOT_LANEQ : SOpInst<"vdot_laneq", "dd89i", "iUiQiQUi", OP_DOT_LNQ>;
 }
+
+// v8.2-A FP16 fused multiply-add long instructions.
+let ArchGuard = "defined(__ARM_FEATURE_FP16FML) && defined(__aarch64__)" in {
+  def VFMLAL_LOW  : SInst<"vfmlal_low", "ffHH", "UiQUi">;
+  def VFMLSL_LOW  : SInst<"vfmlsl_low", "ffHH", "UiQUi">;
+  def VFMLAL_HIGH : SInst<"vfmlal_high", "ffHH", "UiQUi">;
+  def VFMLSL_HIGH : SInst<"vfmlsl_high", "ffHH", "UiQUi">;
+
+  def VFMLAL_LANE_LOW  : SOpInst<"vfmlal_lane_low", "ffH0i", "UiQUi", OP_FMLAL_LN>;
+  def VFMLSL_LANE_LOW  : SOpInst<"vfmlsl_lane_low", "ffH0i", "UiQUi", OP_FMLSL_LN>;
+  def VFMLAL_LANE_HIGH : SOpInst<"vfmlal_lane_high", "ffH0i", "UiQUi", OP_FMLAL_LN_Hi>;
+  def VFMLSL_LANE_HIGH : SOpInst<"vfmlsl_lane_high", "ffH0i", "UiQUi", OP_FMLSL_LN_Hi>;
+
+  def VFMLAL_LANEQ_LOW  : SOpInst<"vfmlal_laneq_low", "ffH1i", "UiQUi", OP_FMLAL_LN>;
+  def VFMLSL_LANEQ_LOW  : SOpInst<"vfmlsl_laneq_low", 

[PATCH] D53633: [AArch64] Implement FP16FML intrinsics

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc added a comment.

In https://reviews.llvm.org/D53633#1274621, @t.p.northover wrote:

> I think this is reasonable.


Thanks Tim. Could you also review https://reviews.llvm.org/D53632, which is the 
LLVM part of this implementation?


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[PATCH] D53633: [AArch64] Implement FP16FML intrinsics

[Bryan Chan via Phabricator via cfe-commits]

bryanpkc created this revision.
bryanpkc added reviewers: SjoerdMeijer, bogden, efriedma, t.p.northover.
Herald added subscribers: cfe-commits, kristof.beyls, javed.absar.

Generate the FP16FML intrinsics into arm_neon.h (AArch64 only for now).
Add two new type modifiers to NeonEmitter to handle the new prototypes.
Define __ARM_FEATURE_FP16FML when +fp16fml is enabled and guard the
intrinsics with the macro in arm_neon.h.

Based on a patch by Gao Yiling.


Repository:
  rC Clang

https://reviews.llvm.org/D53633

Files:
  include/clang/Basic/arm_neon.td
  include/clang/Basic/arm_neon_incl.td
  lib/Basic/Targets/AArch64.cpp
  lib/Basic/Targets/AArch64.h
  lib/CodeGen/CGBuiltin.cpp
  test/CodeGen/aarch64-neon-fp16fml.c
  test/Preprocessor/aarch64-target-features.c
  utils/TableGen/NeonEmitter.cpp

Index: utils/TableGen/NeonEmitter.cpp
===
--- utils/TableGen/NeonEmitter.cpp
+++ utils/TableGen/NeonEmitter.cpp
@@ -494,6 +494,7 @@
 std::pair emitDagSaveTemp(DagInit *DI);
 std::pair emitDagSplat(DagInit *DI);
 std::pair emitDagDup(DagInit *DI);
+std::pair emitDagDupTyped(DagInit *DI);
 std::pair emitDagShuffle(DagInit *DI);
 std::pair emitDagCast(DagInit *DI, bool IsBitCast);
 std::pair emitDagCall(DagInit *DI);
@@ -897,6 +898,18 @@
 Float = true;
 ElementBitwidth = 16;
 break;
+  case '0':
+Float = true;
+if (AppliedQuad)
+  Bitwidth /= 2;
+ElementBitwidth = 16;
+break;
+  case '1':
+Float = true;
+if (!AppliedQuad)
+  Bitwidth *= 2;
+ElementBitwidth = 16;
+break;
   case 'g':
 if (AppliedQuad)
   Bitwidth /= 2;
@@ -1507,6 +1520,8 @@
 return emitDagShuffle(DI);
   if (Op == "dup")
 return emitDagDup(DI);
+  if (Op == "dup_typed")
+return emitDagDupTyped(DI);
   if (Op == "splat")
 return emitDagSplat(DI);
   if (Op == "save_temp")
@@ -1771,6 +1786,28 @@
   return std::make_pair(T, S);
 }
 
+std::pair Intrinsic::DagEmitter::emitDagDupTyped(DagInit *DI) {
+  assert_with_loc(DI->getNumArgs() == 2, "dup_typed() expects two arguments");
+  std::pair A = emitDagArg(DI->getArg(0),
+  DI->getArgNameStr(0));
+  std::pair B = emitDagArg(DI->getArg(1),
+  DI->getArgNameStr(1));
+  assert_with_loc(B.first.isScalar(),
+  "dup_typed() requires a scalar as the second argument");
+
+  Type T = A.first;
+  assert_with_loc(T.isVector(), "dup_typed() used but target type is scalar!");
+  std::string S = "(" + T.str() + ") {";
+  for (unsigned I = 0; I < T.getNumElements(); ++I) {
+if (I != 0)
+  S += ", ";
+S += B.second;
+  }
+  S += "}";
+
+  return std::make_pair(T, S);
+}
+
 std::pair Intrinsic::DagEmitter::emitDagSplat(DagInit *DI) {
   assert_with_loc(DI->getNumArgs() == 2, "splat() expects two arguments");
   std::pair A = emitDagArg(DI->getArg(0),
Index: test/Preprocessor/aarch64-target-features.c
===
--- test/Preprocessor/aarch64-target-features.c
+++ test/Preprocessor/aarch64-target-features.c
@@ -93,16 +93,20 @@
 // RUN: %clang -target aarch64-none-linux-gnu -march=armv8.2a+dotprod -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-DOTPROD %s
 // CHECK-DOTPROD: __ARM_FEATURE_DOTPROD 1
 
-// RUN: %clang -target aarch64-none-linux-gnueabi -march=armv8.2-a+nofp16fml+fp16 -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=CHECK-FULLFP16-VECTOR-SCALAR %s
-// RUN: %clang -target aarch64-none-linux-gnueabi -march=armv8.2-a+nofp16+fp16fml -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=CHECK-FULLFP16-VECTOR-SCALAR %s
-// RUN: %clang -target aarch64-none-linux-gnueabi -march=armv8.2-a+fp16+nofp16fml -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=CHECK-FULLFP16-VECTOR-SCALAR %s
-// RUN: %clang -target aarch64-none-linux-gnueabi -march=armv8-a+fp16fml -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=CHECK-FULLFP16-VECTOR-SCALAR %s
-// RUN: %clang -target aarch64-none-linux-gnueabi -march=armv8-a+fp16 -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=CHECK-FULLFP16-VECTOR-SCALAR %s
-// RUN: %clang -target aarch64-none-linux-gnueabi -march=armv8.4-a+nofp16fml+fp16 -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=CHECK-FULLFP16-VECTOR-SCALAR %s
-// RUN: %clang -target aarch64-none-linux-gnueabi -march=armv8.4-a+nofp16+fp16fml -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=CHECK-FULLFP16-VECTOR-SCALAR %s
-// RUN: %clang -target aarch64-none-linux-gnueabi -march=armv8.4-a+fp16+nofp16fml -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=CHECK-FULLFP16-VECTOR-SCALAR %s
-// RUN: %clang -target aarch64-none-linux-gnueabi -march=armv8.4-a+fp16fml -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=CHECK-FULLFP16-VECTOR-SCALAR %s
-// RUN: %clang -target