Hi All,
Attached my test case F.Y.R.
Best Regards,
Bell Song
> -Original Message-
> From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of
> Song, BinX
> Sent: Wednesday, January 31, 2018 3:01 PM
> To: edk2-devel@lists.01.org
> Cc: ler...@redhat.com; Dong, Eric
> Subject
Current CPU feature dependency check will hang on when meet below or
similar case:
if (IsCpuFeatureSupported (CPU_FEATURE_AESNI)) {
Status = RegisterCpuFeature (
"AESNI",
AesniGetConfigData,
AesniSupport,
AesniInitialize,
CPU_FEATUR
Thanks Paulo.
===
OVMF IA32: DXE worked, but SMM not.
Since the page fault is only occurring in IA32 with no paging enabled
(default case), I suspect that when we don't have paging, we are unable
to successfully validate the memory address when it's i.e. outside SMRAM
- that
On 1/31/2018 1:44 PM, Ni, Ruiyu wrote:
Mike, Laszlo,
Does the patch only apply to the operand?
If so, PatchAssembly looks too general.
How about the name like PatchAssemblyOperand?
On 1/31/2018 6:25 AM, Kinney, Michael D wrote:
Laszlo,
I agree that the function is better than a macro.
I thou
On 1/30/2018 11:33 PM, Laszlo Ersek wrote:
The SmmStartup() executes in SMM, which is very similar to real mode. Add
"BITS 16" before it and "BITS 32" after it (just before the @32bit label).
Remove the manual 0x66 operand-size override prefixes, for selecting
32-bit operands -- the sizes of our
Mike, Laszlo,
Does the patch only apply to the operand?
If so, PatchAssembly looks too general.
How about the name like PatchAssemblyOperand?
On 1/31/2018 6:25 AM, Kinney, Michael D wrote:
Laszlo,
I agree that the function is better than a macro.
I thought of the alignment issues as well. Co
Hi, Liming:
YES, its code need to be the raw execution code.
I mean:
1. We could use traditional asm code , compiled it, and use tools to translate
them to the raw execution code.
Is there any difficulty to do this?
So, it would depreciate the asm16 or nasmb concept.
Thanks
-邮件原件-
发件人: T
On 1/30/2018 11:33 PM, Laszlo Ersek wrote:
SMM emulation under KVM crashes the guest when the "jz" branch, added in
commit d4d87596c11d ("UefiCpuPkg/PiSmmCpuDxeSmm: Enable NXE if it's
supported", 2018-01-18), is taken.
Rework the propagation of CPUID.8001H:EDX.NX [bit 20] to IA32_EFER.NXE
[b
A minor comment.
Do you think is it better to add prefix for new definitions in
ExtendedFirmwarePerformance.h? Maybe FPDT_ ?
Thanks,
Star
-Original Message-
From: Bi, Dandan
Sent: Tuesday, January 30, 2018 9:54 PM
To: edk2-devel@lists.01.org
Cc: Gao, Liming ; Zeng, Star
Subject: [PATCH
Just pushed the patch at 19ef86eec6ed67c11b6a942865b143123180d394 with Liming's
and my RB.
Thanks,
Star
-Original Message-
From: Gao, Liming
Sent: Tuesday, January 30, 2018 5:06 PM
To: Zeng, Star ; Heyi Guo ;
leif.lindh...@linaro.org; linaro-u...@lists.linaro.org;
edk2-devel@lists.01.o
On 2018/1/30 21:21, Leif Lindholm wrote:
> On Tue, Jan 30, 2018 at 08:48:27PM +0800, Huangming (Mark) wrote:
>>
>>
>> On 2018/1/30 3:58, Leif Lindholm wrote:
>>> A few style comments below.
>>>
>>> On Fri, Jan 26, 2018 at 04:00:40PM +0800, Ming Huang wrote:
From: Jason Zhang
This
Laszlo,
I agree that the function is better than a macro.
I thought of the alignment issues as well. CopyMem()
is a good solution. We could also consider
WriteUnalignedxx() functions in BaseLib.
I was originally thinking this functionality would go
into BaseLib. But with the use of CopyMem(),
On 01/30/18 22:26, Kinney, Michael D wrote:
> Laszlo,
>
> Maybe we can add a macro to help:
>
> #define PATCH_X86_ASM(Label,Type,Value) *((Type *)(&Label) - 1) =
> (Type)(Value)
>
> PATCH_X86_ASM (gSmmCr0, UINT32, AsmReadCr0());
Before sending my previous email, I thought of something like
On 01/30/18 21:31, Kinney, Michael D wrote:
> Laszlo,
>
> We have already used this technique in other NASM files
> to remove DBs.
OK.
> Let us know if you have suggestions on how to make the
> C code that performs the patches easier to read and
> maintain.
How about this:
VOID
PatchAssem
Laszlo,
Maybe we can add a macro to help:
#define PATCH_X86_ASM(Label,Type,Value) *((Type *)(&Label) - 1) =
(Type)(Value)
PATCH_X86_ASM (gSmmCr0, UINT32, AsmReadCr0());
Mike
> -Original Message-
> From: Kinney, Michael D
> Sent: Tuesday, January 30, 2018 12:31 PM
> To: Laszlo Erse
Laszlo,
We have already used this technique in other NASM files
to remove DBs.
Let us know if you have suggestions on how to make the
C code that performs the patches easier to read and
maintain.
Mike
> -Original Message-
> From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org]
> On
On 01/30/18 18:22, Kinney, Michael D wrote:
> Laszlo,
>
> The DBs can be removed if the label is moved after
> the instruction and the patch is done to the label
> minus the size of the patch value.
Indeed I haven't thought of this.
If I understand correctly, it means
extern UINT8 gSmmCr0;
Laszlo,
The DBs can be removed if the label is moved after
the instruction and the patch is done to the label
minus the size of the patch value.
Mike
> -Original Message-
> From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org]
> On Behalf Of Laszlo Ersek
> Sent: Tuesday, January 30,
Dear developers, dear Jiewen,
I have been investigating the devel-MinPlatform branch of edk2-platforms for
educational purposes and got two questions regarding the Firmware Volume code
in PlatformInitPreMem, if you do not mind. I assume the tree was tested, so
most likely I misunderstood some t
Not my area of expertise.
Liming, Mike?
On Tue, Jan 16, 2018 at 12:01:51AM +, Marvin H?user wrote:
> Dear developers,
>
> First off, I'm writing this mail for educational purposes, so I
> would be very thankful if I got a reply, though you will not miss
> anything if you skip it.
>
> I was
On 30/01/2018 10:33, Laszlo Ersek wrote:
> Repo: https://github.com/lersek/edk2.git
> Branch: smm_startup_ia32_nocond
>
> This small series fixes the IA32 SMM regression on KVM that I reported
> recently. The first two patches are cleanups (no functional changes),
> the third patch is the fix.
>
The gSmmCr3, gSmmCr4, gSmmCr0 and gSmmJmpAddr global variables are used
for patching assembly instructions, thus we can never remove the DB
encodings for those instructions. At least we should add the intended
meanings in comments.
This patch only changes comments.
Cc: Eric Dong
Cc: Jian J Wang
The SmmStartup() executes in SMM, which is very similar to real mode. Add
"BITS 16" before it and "BITS 32" after it (just before the @32bit label).
Remove the manual 0x66 operand-size override prefixes, for selecting
32-bit operands -- the sizes of our operands trigger NASM to insert the
prefixes
SMM emulation under KVM crashes the guest when the "jz" branch, added in
commit d4d87596c11d ("UefiCpuPkg/PiSmmCpuDxeSmm: Enable NXE if it's
supported", 2018-01-18), is taken.
Rework the propagation of CPUID.8001H:EDX.NX [bit 20] to IA32_EFER.NXE
[bit 11] so that no code is executed conditiona
Repo: https://github.com/lersek/edk2.git
Branch: smm_startup_ia32_nocond
This small series fixes the IA32 SMM regression on KVM that I reported
recently. The first two patches are cleanups (no functional changes),
the third patch is the fix.
Cc: Eric Dong
Cc: Jian J Wang
Cc: Jiewen Yao
Cc: P
Current Pcd value support flexible format, this patch add support for
BPDG Tool to support L'' and '' format.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Yonghong Zhu
---
BaseTools/Source/Python/BPDG/GenVpd.py | 32 ++--
BaseTools/Source/Pyt
On Fri, Jan 26, 2018 at 04:00:49PM +0800, Ming Huang wrote:
> Add PXM method for Pcie device, HNS device and SAS device.
> Add STA method for HNS.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: hensonwang
> Signed-off-by: Ming Huang
> Signed-off-by: Heyi Guo
> ---
On Fri, Jan 26, 2018 at 04:00:48PM +0800, Ming Huang wrote:
> Add ITS affinity structure in SRAT.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ming Huang
> Signed-off-by: Heyi Guo
> ---
Looks sane to me.
Reviewed-by: Graeme Gregory
> Silicon/Hisilicon/Hi1616/
On Fri, Jan 26, 2018 at 04:00:37PM +0800, Ming Huang wrote:
> Add Processor Properties Topology Table, PPTT include
> Processor hierarchy node, Cache Type Structure and ID structure.
>
> PPTT is needed for lscpu command to show socket information correctly.
> https://bugs.linaro.org/show_bug.cgi?i
On Fri, Jan 26, 2018 at 04:00:36PM +0800, Ming Huang wrote:
> Move definition of Madt struct to head file, so PPTT driver
> can include it.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ming Huang
> Signed-off-by: Heyi Guo
> ---
Looks sane to me
Reviewed-by: Graem
Cc: Liming Gao
Cc: Star Zeng
Cc: Ruiyu Ni
Cc: Jaben Carsey
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Dandan Bi
---
ShellPkg/DynamicCommand/DpDynamicCommand/Dp.c | 609 -
ShellPkg/DynamicCommand/DpDynamicCommand/Dp.h | 7 +-
ShellPkg
V2:
Update FirmwarePerformanceSmm to receive the address
of performance records instead of records content.
Receive buffer address of Boot performance records
which are reported by SmmCorePerformanceLib.
Cc: Liming Gao
Cc: Star Zeng
Contributed-under: TianoCore Contribution Agreement 1.1
Signed
V2:
Update SmmCorePerformanceLib to report the buffer address of
boot performance records instead of records contents.
Updated to convert Pref entry to FPDT record in SMM phase and then
export records to FPDT table.
Cc: Liming Gao
Cc: Star Zeng
Contributed-under: TianoCore Contribution Agreemen
Updated to convert Pref entry to FPDT record in PEI phase and then
report the records to DxeCorePerfLib through GUID hob.
Cc: Liming Gao
Cc: Star Zeng
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Dandan Bi
---
.../Library/PeiPerformanceLib/PeiPerformanceLib.c | 565 +
V2:
Update DxecorePerformanceLib to report the boot performance table
address instead of records contents.
Updated to convert Pref entry to FPDT record in DXE phase and then
allocate boot performance table to save the record and report
the address of boot performance table to FirmwarePerformanceDx
Add FPDT records into boot performance table for S3 phase
Cc: Liming Gao
Cc: Star Zeng
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Dandan Bi
---
.../FirmwarePerformancePei.c | 59 +-
.../FirmwarePerformancePei.inf
V2:
Update FirmwarePerformanceDxe to receive the address
of performance records instead of records content.
1. Remove the macro EXTENSION_RECORD_SIZE, since the extension
size can be got through PcdExtFpdtBootRecordPadSize.
2. Hook EFI_SW_DXE_BS_PC_READY_TO_BOOT_EVENT to install ACPI table
3. Co
From: "Gao, Liming"
Cc: Liming Gao
Cc: Star Zeng
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Liming Gao
Signed-off-by: Dandan Bi
---
.../Include/Guid/ExtendedFirmwarePerformance.h | 291 +
MdeModulePkg/Include/Guid/FirmwarePerformance.h|
V2:
a.Update DxecorePerformanceLib/SmmCorePerformanceLib to report the
boot performance table address instead of records contents.
b.Update FirmwarePerformanceDxe/FirmwarePerformanceSmm to receive the address
of performance records.
This patch series also can be accessed at:
https://github.com/dan
On 8 January 2018 at 05:45, kalyan-nagabhirava
wrote:
> Application will Download platform code Image (kernel + DTB+ rootfs) and
> writes
> into Flash partition.
>
> Cc: Ard Biesheuvel
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: kalyan-nagabhirava
> ---
> Platfor
On 8 January 2018 at 05:45, kalyan-nagabhirava
wrote:
> Application will get file path of PK key and KEK key using rdk.conf file,
> once keys are
> Available, application will enable secure boot and validates the signed
> kernel Image.
>
> Cc: Ard Biesheuvel
> Contributed-under: TianoCore Con
On 8 January 2018 at 05:45, kalyan-nagabhirava
wrote:
> Implemented features related to secure boot and DRI (downloading the image
> and storing on flash),
> library has utility of file read and write operations for fat and raw flash
> partition, it reads file path
> and load the file content
On Tue, Jan 30, 2018 at 08:48:27PM +0800, Huangming (Mark) wrote:
>
>
> On 2018/1/30 3:58, Leif Lindholm wrote:
> > A few style comments below.
> >
> > On Fri, Jan 26, 2018 at 04:00:40PM +0800, Ming Huang wrote:
> >> From: Jason Zhang
> >>
> >> This module support updating the boot CPU firmware
On 8 January 2018 at 05:45, kalyan-nagabhirava
wrote:
> Linaro and RDK are working on standardizing the boot process for RDK STB
> boxes using Uefi.
> we implmented couple of RDK UEFI apllications(secure boot and DRI ) which are
> tested on
> RDK qemu platform
>
> Cc: Ard Biesheuvel
> Contri
On 01/29/18 20:48, Laszlo Ersek wrote:
> On 01/29/18 10:02, Wang, Jian J wrote:
>> Hi Laszlo,
>>
>> I don't know the history of these code but I guess they're converted
>> from .asm file. That may be why there's "DB 66h" prefix. I think
>> you're right these tricks should be replaced with more form
On 30 January 2018 at 12:52, Leif Lindholm wrote:
> On Tue, Jan 30, 2018 at 11:52:41AM +, Ard Biesheuvel wrote:
>> >> >> +STATIC
>> >> >> +EFI_STATUS
>> >> >> +EFIAPI
>> >> >> +SynQuacerSdMmcCapability (
>> >> >> + IN EFI_HANDLE ControllerHandle,
>> >> >> + IN
On Tue, Jan 30, 2018 at 11:52:41AM +, Ard Biesheuvel wrote:
> >> >> +STATIC
> >> >> +EFI_STATUS
> >> >> +EFIAPI
> >> >> +SynQuacerSdMmcCapability (
> >> >> + IN EFI_HANDLE ControllerHandle,
> >> >> + IN UINT8 Slot,
> >> >> + IN OUT VO
On 2018/1/30 3:58, Leif Lindholm wrote:
> A few style comments below.
>
> On Fri, Jan 26, 2018 at 04:00:40PM +0800, Ming Huang wrote:
>> From: Jason Zhang
>>
>> This module support updating the boot CPU firmware only.
>>
>> Contributed-under: TianoCore Contribution Agreement 1.1
>> Signed-off-b
On 26 January 2018 at 08:00, Ming Huang wrote:
> From: Jason Zhang
>
> This module support updating the boot CPU firmware only.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Jason Zhang
> Signed-off-by: Ming Huang
> Signed-off-by: Heyi Guo
This looks good to me
On 30 January 2018 at 11:47, Leif Lindholm wrote:
> On Tue, Jan 30, 2018 at 11:14:31AM +, Ard Biesheuvel wrote:
>> On 30 January 2018 at 11:00, Leif Lindholm wrote:
>> > On Tue, Jan 30, 2018 at 10:32:40AM +, Ard Biesheuvel wrote:
>> >> Implement support for the SynQuacer eMMC controller.
On Tue, Jan 30, 2018 at 11:14:31AM +, Ard Biesheuvel wrote:
> On 30 January 2018 at 11:00, Leif Lindholm wrote:
> > On Tue, Jan 30, 2018 at 10:32:40AM +, Ard Biesheuvel wrote:
> >> Implement support for the SynQuacer eMMC controller. This involves an
> >> implementation of the SD/MMC overr
On 30 January 2018 at 11:00, Leif Lindholm wrote:
> On Tue, Jan 30, 2018 at 10:32:40AM +, Ard Biesheuvel wrote:
>> Implement support for the SynQuacer eMMC controller. This involves an
>> implementation of the SD/MMC override protocol to handle a couple of
>> quirks that would otherwise preven
On Tue, Jan 30, 2018 at 10:32:40AM +, Ard Biesheuvel wrote:
> Implement support for the SynQuacer eMMC controller. This involves an
> implementation of the SD/MMC override protocol to handle a couple of
> quirks that would otherwise prevent this IP from being driven by the
> generic SDHCI drive
Implement support for the SynQuacer eMMC controller. This involves an
implementation of the SD/MMC override protocol to handle a couple of
quirks that would otherwise prevent this IP from being driven by the
generic SDHCI driver.
Also, add a HII page to the PlatformDxe driver that allows eMMC supp
On 30 January 2018 at 01:24, Zeng, Star wrote:
> Reviewed-by: Star Zeng
>
> Thanks Hao's investigation and Ard's contribution.
>
Thanks all
Pushed as 864701886fc3..b23fc39cd3c3
>
> Star
> -Original Message-
> From: Ard Biesheuvel [mailto:ard.biesheu...@linaro.org]
> Sent: Monday, Janua
+error_line = FileData[int (FileLine) - 1]
Please check FileLine is digit or not. If it is not digit, you need to skip
this statement.
>-Original Message-
>From: Feng, Bob C
>Sent: Monday, January 29, 2018 11:22 AM
>To: edk2-devel@lists.01.org
>Cc: Feng, Bob C ; Gao,
Ard,
No more comments from my side.
Thanks/Ray
> -Original Message-
> From: Ard Biesheuvel [mailto:ard.biesheu...@linaro.org]
> Sent: Monday, January 29, 2018 4:26 PM
> To: Wu, Hao A ; Zeng, Star ; Ni,
> Ruiyu
> Cc: edk2-devel@lists.01.org; leif.lindh...@linaro.org; Kinney, Michael D
> ;
Reviewed-by: Liming Gao
>-Original Message-
>From: Zeng, Star
>Sent: Tuesday, January 30, 2018 2:24 PM
>To: Heyi Guo ; leif.lindh...@linaro.org; linaro-
>u...@lists.linaro.org; edk2-devel@lists.01.org; graeme.greg...@linaro.org
>Cc: huangmin...@huawei.com; ard.biesheu...@linaro.org; Gao,
According to UEFI Spec, EFI_GRAPHICS_OUTPUT_PROTOCOL.Mode->Info->
PixelsPerScanLine may contain padding pixel elements outside the area
covered by HorizontalResolution for performance reasons or due to hardware
restrictions. CorebootPayloadPkg's FbGop driver doesn't follow this
requirement, and pro
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