Thanks Jiewen.
Reviewed-by: Giri P Mudusuru
> -Original Message-
> From: Yao, Jiewen
> Sent: Tuesday, September 6, 2016 6:21 PM
> To: edk2-devel@lists.01.org
> Cc: Mudusuru, Giri P ; Chan, Amy
>
> Subject:
Ard:
In InternalMemSetMem, Value64 = (((UINT64)Value32) << 32) | Value32; may cause
the below link error with VS IA32 build. It (<<) should be replaced by BaseLib
LShift API
BaseMemoryLib.lib(SetMem.obj) : error LNK2001: unresolved external symbol
__allshl
Thanks
Liming
> -Original
Reviewed-by: Liming Gao
> -Original Message-
> From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of
> Star Zeng
> Sent: Friday, September 02, 2016 7:59 PM
> To: edk2-devel@lists.01.org
> Cc: Zeng, Star
> Subject: [edk2] [PATCH
Add Giri as 2nd maintainer to IntelFsp2*Pkg and IntelSiliconPkg.
Cc: Giri P Mudusuru
Cc: Amy Chan
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao
---
Maintainers.txt | 3 +++
1 file changed,
Nico,
You want to develop an application which needs file system access support but
doesn't depend on Shell environment. So you link your application to
UefiShellLib and change the shell library to handle the case when it's not in
the Shell environment.
Is my understanding correct?
If yes, I
Reviewed-by: Ruiyu Ni
Regards,
Ray
>-Original Message-
>From: Leif Lindholm [mailto:leif.lindh...@linaro.org]
>Sent: Sunday, September 4, 2016 9:16 PM
>To: edk2-devel@lists.01.org
>Cc: Ni, Ruiyu ; Ard Biesheuvel
Nice!!!
Em ter, 6 de set de 2016 às 13:20, Bruce Cran escreveu:
> On 9/6/16 3:25 AM, Laszlo Ersek wrote:
>
> > The gmane web interface is gone, and I'm unaware of anyone who has
> > picked up the archive and exposed it under the same URLs (via domain
> > name transfer etc).
Thanks Jeff for adding comments to refer the SDM naming.
Reviewed series of patches.
Reviewed-by: Giri P Mudusuru
> -Original Message-
> From: Fan, Jeff
> Sent: Tuesday, September 6, 2016 4:39 AM
> To: edk2-devel@lists.01.org
> Cc: Kinney, Michael D
Ruiyu - any comments?
Regards,
Leif
On 4 September 2016 at 14:16, Leif Lindholm wrote:
> Drivers under OptionRomPkg wouldn't build standalone, since ARM and
> AARCH64 were missing from SUPPORTED_ARCHITECTURES. So add them.
> Also, add some compiler libraries needed
On 6 September 2016 at 13:41, Tian, Feng wrote:
> ATA/USB/NVME/SD are ok to me
>
> Reviewed-by: Feng Tian
>
Thanks everyone
Committed as
a2c9b0873a77 MdeModulePkg/AtaAtapiPassThru: enable 64-bit PCI DMA
167c3fb45674 MdeModulePkg/EhciDxe: enable 64-bit
On Tue, Sep 06, 2016 at 03:27:31PM +0100, Ard Biesheuvel wrote:
> Clang does not like separate definitions for the __alias__ and the
> __weak__ attributes, so merge the definitions into one.
>
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Ard Biesheuvel
Clang does not like separate definitions for the __alias__ and the
__weak__ attributes, so merge the definitions into one.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel
---
Note that the CI job is currently broken due to this
This adds ARM support to BaseMemoryLibOptDxe, partially based on the
cortex-strings library (ScanMem) and the existing CopyMem() implementation
from BaseMemoryLibStm in ArmPkg.
All string routines are accelerated except ScanMem16, ScanMem32,
ScanMem64 and IsZeroBuffer, which can wait for another
This adds AARCH64 support to BaseMemoryLibOptDxe, based on the cortex-strings
library. All string routines are accelerated except ScanMem16, ScanMem32,
ScanMem64 and IsZeroBuffer, which can wait for another day. (Very few
occurrences exist in the codebase)
Contributed-under: TianoCore
Since the default BaseMemoryLib should be callable from any context,
including ones where unaligned accesses are not allowed, it implements
InternalCopyMem() and InternalSetMem() using byte accesses only.
However, especially in a context where the MMU is off, such narrow
accesses may be
This adds ARM and AARCH64 support to both BaseMemoryLib (generic C) and
BaseMemoryLibOptDxe (accelerated). The former can be used anywhere, the
latter only in places where the caches are guaranteed to be on, not only
due to the unaligned accesses but also due to the fact that it uses
DC ZVA
ATA/USB/NVME/SD are ok to me
Reviewed-by: Feng Tian
-Original Message-
From: Ard Biesheuvel [mailto:ard.biesheu...@linaro.org]
Sent: Tuesday, September 6, 2016 6:36 PM
To: Ni, Ruiyu
Cc: edk2-devel-01 ; Tian, Feng
Dear edk2 developers,
Ive made a patch in the edk2 ShellPkg CodeModule. It improves compatibility
when no Efi Shell is available. Ive noted all details on Github. To not
duplicate the information, please visit this link below. You can also find
and compare the code there:
Hello Jiaxin,
Thank you very much for your timely help and support.
Regards,
Naveen
-Original Message-
From: Wu, Jiaxin [mailto:jiaxin...@intel.com]
Sent: Tuesday, September 06, 2016 4:35 PM
To: Santhapur Naveen; edk2-devel@lists.01.org
Cc: Ye, Ting; Fu, Siyuan
Subject: RE:
Cc: Michael Kinney
Cc: Feng Tian
Cc: Giri P Mudusuru
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan
---
UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h | 4
1
Cc: Michael Kinney
Cc: Feng Tian
Cc: Giri P Mudusuru
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan
---
UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h | 51
Cc: Michael Kinney
Cc: Feng Tian
Cc: Giri P Mudusuru
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan
---
UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h | 57
Cc: Michael Kinney
Cc: Feng Tian
Cc: Giri P Mudusuru
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan
---
UefiCpuPkg/Include/Register/Msr/PentiumMsr.h | 6 ++
1
Cc: Michael Kinney
Cc: Feng Tian
Cc: Giri P Mudusuru
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan
---
UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h | 83
Cc: Michael Kinney
Cc: Feng Tian
Cc: Giri P Mudusuru
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan
---
UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h | 271
Cc: Michael Kinney
Cc: Feng Tian
Cc: Giri P Mudusuru
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan
---
UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h | 25
Cc: Michael Kinney
Cc: Feng Tian
Cc: Giri P Mudusuru
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan
---
UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h | 167
Cc: Michael Kinney
Cc: Feng Tian
Cc: Giri P Mudusuru
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan
---
UefiCpuPkg/Include/Register/Msr/NehalemMsr.h | 465
Cc: Michael Kinney
Cc: Feng Tian
Cc: Giri P Mudusuru
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan
---
UefiCpuPkg/Include/Register/Msr/P6Msr.h | 83
Cc: Michael Kinney
Cc: Feng Tian
Cc: Giri P Mudusuru
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan
---
UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h | 218
Cc: Michael Kinney
Cc: Feng Tian
Cc: Giri P Mudusuru
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan
---
UefiCpuPkg/Include/Register/Msr/AtomMsr.h | 37
Cc: Michael Kinney
Cc: Feng Tian
Cc: Giri P Mudusuru
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan
---
UefiCpuPkg/Include/Register/Msr/HaswellMsr.h | 58
Cc: Michael Kinney
Cc: Feng Tian
Cc: Giri P Mudusuru
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan
---
UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h | 360
Cc: Michael Kinney
Cc: Feng Tian
Cc: Giri P Mudusuru
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan
---
UefiCpuPkg/Include/Register/ArchitecturalMsr.h | 352
Cc: Michael Kinney
Cc: Feng Tian
Cc: Giri P Mudusuru
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan
---
UefiCpuPkg/Include/Register/Msr/Core2Msr.h | 52
Cc: Michael Kinney
Cc: Feng Tian
Cc: Giri P Mudusuru
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan
---
UefiCpuPkg/Include/Register/Msr/CoreMsr.h | 58
Cc: Michael Kinney
Cc: Feng Tian
Cc: Giri P Mudusuru
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan
---
UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h | 3 +++
1
On 6 September 2016 at 12:13, Bhupesh Sharma wrote:
> Hi EDK2 experts,
>
> We have recently added the support for storing UEFI run-time variables on
> underlying NOR
> Flash slave on our ARMV8 NXP board.
>
> We are successfully able to change the values of variables like
Hi EDK2 experts,
We have recently added the support for storing UEFI run-time variables on
underlying NOR
Flash slave on our ARMV8 NXP board.
We are successfully able to change the values of variables like boot-order
using the latest
MdeModulePkg BDS:
Hi Laszlo.
Thanks for the answer, even being terrible news.
The archive helped me a lot to solve several situations in the past.
We know how this kind of information is important for the community.
Hope someone could give us some light on that.
Not sure if I can help to solve this, in case
Hi Naveen,
The patch has been committed:
SHA-1: 8c5f78a2cc15199e3f77ae4b156023af366fd6c7
* MdeModulePkg: Support classless IP for DHCPv4 TransmitReceive()
Thanks,
Jiaxin
> -Original Message-
> From: Santhapur Naveen [mailto:nave...@amiindia.co.in]
> Sent: Friday, September 2, 2016 2:16
On 6 September 2016 at 09:54, Ni, Ruiyu wrote:
> Ard,
> The patch to MdeModulePkg/PciHostBridgeDxe is good.
>
> Reviewed-by: Ruiyu Ni
>
Thanks Ray!
Who is responsible for the AtapPassThru, USB, NVME and SDHCI drivers?
>> -Original Message-
>>
Tested-by: Hegde Nagaraj P
-Original Message-
From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of Fu,
Siyuan
Sent: Tuesday, September 06, 2016 2:37 PM
To: Wu, Jiaxin ; edk2-devel@lists.01.org
Cc: Ye, Ting
On 09/05/16 19:51, Rafael Machado wrote:
> Hi everyone.
>
> Sorry for the possibly stupid question, maybe I lose something. Did we
> get to a conclusion about this?
> I tried to access the link https://lists.01.org/pipermail/edk2-devel/
> but didn't find to much information. Just e-mails from 3
Reviewed-by: Fu Siyuan
> -Original Message-
> From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of
> Jiaxin Wu
> Sent: Tuesday, September 6, 2016 4:51 PM
> To: edk2-devel@lists.01.org
> Cc: Ye, Ting ; Fu, Siyuan
Ard,
The patch to MdeModulePkg/PciHostBridgeDxe is good.
Reviewed-by: Ruiyu Ni
Thanks/Ray
> -Original Message-
> From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of
> Ard Biesheuvel
> Sent: Tuesday, September 6, 2016 3:48 PM
> To: edk2-devel-01
v2:
* Code refine.
* For DnsCache, the minimum value of TTL is selected between CNAME and A/
record.
According RFC 1034 - 3.6.2, if the query name is an alias, the name server
will include the CNAME record in the response and restart the query at the
domain name specified in the data field
In order to support recovery in PEI phase, a platform need initialize
USB controller. This logic is missing in current PchInitPeim.
We removed MultiPlatformInfoInit() because it is already done in
PlatformEarlyInitEntry().
We also initialize XhciMemBaseAddr to 0, or it is garbage value.
Cc:
The default PcdPeiIchEhciControllerMemoryBaseAddress value 0xFD00
conflict with the default TXE SECUMA MMIO address.
So we update to 0xFC00 to avoid conflict.
Cc: David Wei
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao
Also cc Ruiyu to see if any comments.
Thanks,
Star
-Original Message-
From: Ard Biesheuvel [mailto:ard.biesheu...@linaro.org]
Sent: Tuesday, September 6, 2016 3:48 PM
To: edk2-devel-01 ; Tian, Feng ;
Zeng, Star ; Gao,
Yes, take the minimum value of TTL is meaningful.
From: Fu, Siyuan
Sent: Tuesday, September 6, 2016 3:13 PM
To: Wu, Jiaxin ; edk2-devel@lists.01.org
Cc: Hegde Nagaraj P ; Ye, Ting
Subject: RE: [Patch] NetworkPkg/DnsDxe: Handle
Feng, Star: do you have any feedback on these patches? Thanks.
On 5 September 2016 at 10:17, Ard Biesheuvel wrote:
> After moving ArmVirtQemu to the generic PciHostBridgeDxe, we noticed that
> setting DmaAbove4G resulted in problems with the emulated EHCI USB host
>
Jiaxin,
For #2, it's ok, I didn't notice the change in your patch.
For #1, I think we shouldn't mix the CNAME RR and A RR, they are 2 different
answers and may have different TTL.
Best Regards
Siyuan
From: Wu, Jiaxin
Sent: Tuesday, September 6, 2016 3:05 PM
To: Fu, Siyuan
Hi Siyuan,
> I have 2 comments for the patch.
> 1. I think we can add the CNAME record to the DNS cache, just like the A and
> records, so the driver won't need to repeat the query if user query the
> host again.
In my opinion , the CNAME is unnecessary to cache to avoid the repeat the
Reviewed-by: Ye Ting
-Original Message-
From: Wu, Jiaxin
Sent: Tuesday, September 06, 2016 11:39 AM
To: edk2-devel@lists.01.org
Cc: Ye, Ting ; Fu, Siyuan
Subject: [Patch] NetworkPkg/IpSecDxe: Generate SPI randomly and correct
According to PCI spec the next AER capability is relative to
the beginning of PCI configuration space. Hence substract the
base offset to get the next capability.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Abdul Lateef Attar
---
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