Thanks to open the bug.
Yes, I will use your recommendation below when I check in the patch later.
Thank you
Yao Jiewen
From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of Jordan
Justen
Sent: Thursday, September 8, 2016 1:06 PM
To: Yao, Jiewen ;
Hi Eric,
Memory Page size Minimum (MPSMIN) is not exposed in the UEFI Scope.
Any schedule when this issue would be address in the SCT tool ?
Thanks,
Ramesh
-Original Message-
From: Jin, Eric [mailto:eric@intel.com]
Sent: 05 September 2016 10:54
To: Tian, Feng; Ramesh R.;
Hi Feng,
With the device we have , we tried 512 as size and all the devices returns
EFI_SUCCESS.
Thanks,
Ramesh
-Original Message-
From: Tian, Feng [mailto:feng.t...@intel.com]
Sent: 05 September 2016 08:48
To: Ramesh R.; edk2-devel; Jin, Eric
Cc: Tian, Feng
Subject: RE:
On 2016-09-07 15:31:12, Yao, Jiewen wrote:
>The problem I am seeing is “inconsistence”.
>
I opened this bug:
https://tianocore.acgmultimedia.com/show_bug.cgi?id=113
For now, can you consider the one I recommended? It is 70 characters:
Maintainers.txt: Add Giri as IntelFsp2*Pkg,
Reviewed the series of 4 patches.
Reviewed-by: Yonghong Zhu
Best Regards,
Zhu Yonghong
-Original Message-
From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of Liming
Gao
Sent: Tuesday, September 06, 2016 12:00 PM
To: edk2-devel@lists.01.org
Use newly created functions that abstract how XD/NX is detected,
enabled, and disabled. Also, use a new function to determine if
Branch Trace Storage is supported. Existing code is specific
to Intel processors.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Joseph
Create new functions to abstract how XD/NX is detected, enabled, and
disabled. Also, create a new function to determine if Branch Trace
Storage is supported. Existing code is specific to Intel processors.
This provides NULL implementations of the new functions.
Contributed-under: TianoCore
Create new functions to abstract how XD/NX is detected, enabled, and
disabled. Also, create a new function to determine if Branch Trace
Storage is supported. Existing code is specific to Intel processors.
This provides NULL implementations of the new functions.
Contributed-under: TianoCore
Create new functions to abstract how XD/NX is detected, enabled, and
disabled. Also, create a new function to determine if Branch Trace
Storage is supported. Existing code is specific to Intel processors.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Joseph Shifflett
This series abstracts accesses to various x86 features. Existing code used
Intel
specific MSR accesses to detect support and to enable/disable features.
Cc: Jeff Fan
Cc: Michael D Kinney
Cc: Kelly Steele
Cc: Jordan
Create new functions to abstract how XD/NX is detected, enabled, and
disabled. Also, create a new function to determine if Branch Trace
Storage is supported. Existing code is specific to Intel processors.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Joseph Shifflett
Agee with Jiewen to keep the doc and tool consistent.
Also the patch prefix "[edk2][PATCH]" should be excluded as it is not part of
the commit message title.
Thanks,
-Giri
> -Original Message-
> From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of Yao,
> Jiewen
>
Reviewed-by: Jordan Justen
On 2016-09-07 04:42:43, Laszlo Ersek wrote:
> Translating QEMU's virtio-block OpenFirmware device path to a UEFI device
> path prefix was one of the earliest case handled in QemuBootOrderLib. At
> that time, I terminated the translation
The problem I am seeing is “inconsistence”.
The https://github.com/tianocore/tianocore.github.io/wiki/Commit-Message-Format
mention 70 char as max.
But the tool check 76 char.
Can we make then consistent?
Either change wiki to 76 char, or change tool to 70 char.
Thank you
Yao Jiewen
From:
On 2016-09-07 10:49:21, Ard Biesheuvel wrote:
> On 7 September 2016 at 18:39, Jordan Justen wrote:
> >
> > If it is difficult to make a good short subject
> > line, then it might be a sign that the patch should be split. For
> > example, you could split this patch in 2.
On 7 September 2016 at 18:39, Jordan Justen wrote:
> On 2016-09-07 01:00:46, Yao, Jiewen wrote:
>>Jordan
>>
>>I have a quick check:
>>
>>Here is my observation:
>>
>>1) From
>>
>>
On 2016-09-07 01:00:46, Yao, Jiewen wrote:
>Jordan
>
>I have a quick check:
>
>Here is my observation:
>
>1) From
>
> https://github.com/tianocore/tianocore.github.io/wiki/Commit-Message-Format,
>it mentions:
>
> o The length of 'Pkg-Module:
Change Looks good. Can you please clarify the commit message on why to change
-_e type?
Reviewed-by: Jaben Carsey
> -Original Message-
> From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of
> Abdul Lateef Attar
> Sent: Monday, September 05,
On 7 September 2016 at 15:52, Ard Biesheuvel wrote:
> This adds ARM support to BaseMemoryLibOptDxe, partially based on the
> cortex-strings library (ScanMem) and the existing CopyMem() implementation
> from BaseMemoryLibStm in ArmPkg.
>
> All string routines are
> On Sep 7, 2016, at 8:27 AM, Leif Lindholm wrote:
>
> Hi all,
>
> This is a report for the archive, rather than anything easily fixable.
> While testing one of Ard's sets against CLANG, I tripped over a
> behaviour exposed by commit a1b8baccc30b
> (BaseTools GCC: use
Hi all,
This is a report for the archive, rather than anything easily fixable.
While testing one of Ard's sets against CLANG, I tripped over a
behaviour exposed by commit a1b8baccc30b
(BaseTools GCC: use 'gcc' as the linker command for GCC44 and later).
This commit changes the CLANG profiles to
On Wed, Sep 07, 2016 at 09:21:54AM +0100, Ard Biesheuvel wrote:
> Enable frame pointers on DEBUG builds so we can support backtraces in
> crash dumps.
>
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Ard Biesheuvel
This is really handy -
Since the default BaseMemoryLib should be callable from any context,
including ones where unaligned accesses are not allowed, it implements
InternalCopyMem() and InternalSetMem() using byte accesses only.
However, especially in a context where the MMU is off, such narrow
accesses may be
This adds ARM support to BaseMemoryLibOptDxe, partially based on the
cortex-strings library (ScanMem) and the existing CopyMem() implementation
from BaseMemoryLibStm in ArmPkg.
All string routines are accelerated except ScanMem16, ScanMem32,
ScanMem64 and IsZeroBuffer, which can wait for another
This adds ARM and AARCH64 support to both BaseMemoryLib (generic C) and
BaseMemoryLibOptDxe (accelerated). The former can be used anywhere, the
latter only in places where the caches are guaranteed to be on, not only
due to the unaligned accesses but also due to the fact that it uses
DC ZVA
This adds AARCH64 support to BaseMemoryLibOptDxe, based on the cortex-strings
library. All string routines are accelerated except ScanMem16, ScanMem32,
ScanMem64 and IsZeroBuffer, which can wait for another day. (Very few
occurrences exist in the codebase)
Contributed-under: TianoCore
On 7 September 2016 at 13:17, Ard Biesheuvel wrote:
> On 7 September 2016 at 13:06, Michael Zimmermann
> wrote:
>> this bug was introduced by:
>> d2fa09a ArmPlatformPkg/PrePi: switch to ASM_FUNC() asm macro
>>
>> Contributed-under: TianoCore
On 7 September 2016 at 12:59, Ard Biesheuvel wrote:
> On 7 September 2016 at 12:10, Ryan Harkin wrote:
>> On 31 August 2016 at 05:33, Michael Zimmermann
>> wrote:
>>> reviewed should mean tested ;)
>>>
>>> took me
On 7 September 2016 at 13:06, Michael Zimmermann
wrote:
> this bug was introduced by:
> d2fa09a ArmPlatformPkg/PrePi: switch to ASM_FUNC() asm macro
>
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: M1cha
> ---
>
this bug was introduced by:
d2fa09a ArmPlatformPkg/PrePi: switch to ASM_FUNC() asm macro
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: M1cha
---
ArmPlatformPkg/PrePi/Arm/ModuleEntryPoint.S | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
On 7 September 2016 at 12:10, Ryan Harkin wrote:
> On 31 August 2016 at 05:33, Michael Zimmermann
> wrote:
>> reviewed should mean tested ;)
>>
>> took me some time to find out why my system currently doesn't boot anymore
>
> I have just
Translating QEMU's virtio-block OpenFirmware device path to a UEFI device
path prefix was one of the earliest case handled in QemuBootOrderLib. At
that time, I terminated the translation output (the UEFI devpath prefix)
with a "/HD(" suffix.
The intent was for the translation to prefix-match only
On 7 September 2016 at 12:25, Michael Zimmermann
wrote:
>> However, looking at this
>> code, this is still not sufficient to find the *next* frame pointer on
>> the stack.
> are you sure about that? this code looks like it does just that:
>
> However, looking at this
> code, this is still not sufficient to find the *next* frame pointer on
> the stack.
are you sure about that? this code looks like it does just that:
https://github.com/torvalds/linux/blob/master/arch/arm/kernel/stacktrace.c
On Wed, Sep 7, 2016 at 1:03 PM, Ard
On 31 August 2016 at 05:33, Michael Zimmermann wrote:
> reviewed should mean tested ;)
>
> took me some time to find out why my system currently doesn't boot anymore
I have just bisected my TC2 boot failure down to this patch too.
> but here's the fix for this commit:
On 7 September 2016 at 10:48, Michael Zimmermann
wrote:
> nice, can we do this for ARM too? I usually need to add DEBUG((...))'s all
> over the place for hours until I found the reason for a fault.
>
This is going to be tricky. Unlike AARCH64, which unambiguously
nice, can we do this for ARM too? I usually need to add DEBUG((...))'s all
over the place for hours until I found the reason for a fault.
Thanks
Michael
On Wed, Sep 7, 2016 at 10:21 AM, Ard Biesheuvel
wrote:
> When dumping the CPU state after an unhandled fault, walk
In TlsConfigureSession(), below piece of code should also be removed. Others is
good to me.
HttpInstance->TlsConfigData.Version.Major = TLS10_PROTOCOL_VERSION_MAJOR;
HttpInstance->TlsConfigData.Version.Minor = TLS10_PROTOCOL_VERSION_MINOR;
Reviewed-by: Wu Jiaxin
Enable frame pointers on DEBUG builds so we can support backtraces in
crash dumps.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel
---
BaseTools/Conf/tools_def.template | 12 ++--
1 file changed, 6 insertions(+), 6
Thomas,
Sorry for the delayed response. The patch is good to me, only one comments:
> + TlsCtx = SSL_CTX_new (SSLv23_client_method ()); if (TlsCtx == NULL)
> + {
> +ASSERT (TlsCtx != NULL);
> +return NULL;
> + }
I think we can remove the assert. Return NULL is fine here.
When dumping the CPU state after an unhandled fault, walk the stack
frames and decode the return addresses so we can show a minimal
backtrace. Unfortunately, we do not have sufficient information to
show the function names, but at least we can see the modules and the
return addresses inside the
Jordan
I have a quick check:
Here is my observation:
1) From
https://github.com/tianocore/tianocore.github.io/wiki/Commit-Message-Format, it
mentions:
* The length of 'Pkg-Module: Brief-single-line-summary' should not exceed
70 characters
2) In the PatchCheck.py, we have
Jordan
I got error from BaseTools\Scripts\PatchCheck.py, if I add it.
Can you fix the tool to remove such limitation?
===
Checking patch file: C:\home\EdkIITransition\AllComboGit\edk2\0001-Maintainers.t
xt-Add-Giri-as-2nd-maintainer-to-IntelF.patch
The commit message format
Reviewed-by: Liming Gao
> -Original Message-
> From: Ard Biesheuvel [mailto:ard.biesheu...@linaro.org]
> Sent: Wednesday, September 07, 2016 2:48 PM
> To: edk2-devel@lists.01.org; leif.lindh...@linaro.org; Gao, Liming
>
> Cc: Kinney, Michael D
What about this patch subject instead?
Maintainers.txt: Add Giri as IntelFsp2*Pkg, IntelSiliconPkg maintainer
This way we can see the affected packages from the subject line.
-Jordan
On 2016-09-06 18:21:10, Jiewen Yao wrote:
> Add Giri as 2nd maintainer to IntelFsp2*Pkg and IntelSiliconPkg.
>
The ArmGicLib API function GicGetCpuRedistributorBase () declares
GicCpuRedistributorBase to iterate over the redistributors of all
CPUs, but then inadvertently advances GicRedistributorBase instead.
Reported-by: "Oliyil Kunnil, Vishal"
Contributed-under: TianoCore
On 7 September 2016 at 04:03, Gao, Liming wrote:
> Ard:
> In InternalMemSetMem, Value64 = (((UINT64)Value32) << 32) | Value32; may
> cause the below link error with VS IA32 build. It (<<) should be replaced by
> BaseLib LShift API
>
> BaseMemoryLib.lib(SetMem.obj) : error
This adds ARM support to BaseMemoryLibOptDxe, partially based on the
cortex-strings library (ScanMem) and the existing CopyMem() implementation
from BaseMemoryLibStm in ArmPkg.
All string routines are accelerated except ScanMem16, ScanMem32,
ScanMem64 and IsZeroBuffer, which can wait for another
This adds ARM and AARCH64 support to both BaseMemoryLib (generic C) and
BaseMemoryLibOptDxe (accelerated). The former can be used anywhere, the
latter only in places where the caches are guaranteed to be on, not only
due to the unaligned accesses but also due to the fact that it uses
DC ZVA
This adds AARCH64 support to BaseMemoryLibOptDxe, based on the cortex-strings
library. All string routines are accelerated except ScanMem16, ScanMem32,
ScanMem64 and IsZeroBuffer, which can wait for another day. (Very few
occurrences exist in the codebase)
Contributed-under: TianoCore
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