This module support updating the boot CPU firmware only.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jason Zhang <zhangjinso...@huawei.com>
Signed-off-by: Ming Huang <huangmin...@huawei.com>
Signed-off-by: Heyi Guo <heyi@linaro.org>
Reviewed-
Replace the old string with short one. The old one is
too long that can not be show integrallty in Setup nemu.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangmin...@huawei.com>
Signed-off-by: Heyi Guo <heyi@linaro.org>
Reviewed-by: L
Add ITS affinity structure in SRAT.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangmin...@huawei.com>
Signed-off-by: Heyi Guo <heyi@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheu...@linaro.org>
Reviewed-by: Graeme Gregory &
In SCT test,we find SP805 watchdog driver can't reset when timeout
so we use another driver in MdeModulePkg.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangmin...@huawei.com>
Signed-off-by: Heyi Guo <heyi@linaro.org>
Signed-off-by:
Modify the feature of BMC set boot option as switching generic
BDS. Break BMC SetBoot option out into BmcConfigBootLib.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangmin...@huawei.com>
Signed-off-by: Heyi Guo <heyi@linaro.org>
Revie
-by: Ming Huang <huangmin...@huawei.com>
Signed-off-by: Heyi Guo <heyi@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindh...@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheu...@linaro.org>
---
Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c |
com>
Signed-off-by: Heyi Guo <heyi@linaro.org>
Signed-off-by: Yan Zhang <zhangya...@huawei.com>
Reviewed-by: Leif Lindholm <leif.lindh...@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheu...@linaro.org>
---
Silicon/Hisilicon/Hi1610/Drivers/Pc
for PXE boot.
https://bugs.linaro.org/show_bug.cgi?id=2657
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jason Zhang <zhangjinso...@huawei.com>
Signed-off-by: Ming Huang <huangmin...@huawei.com>
Signed-off-by: Heyi Guo <heyi@linaro.org>
Reviewed
ed-off-by: Ming Huang <huangmin...@huawei.com>
Signed-off-by: Heyi Guo <heyi@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindh...@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheu...@linaro.org>
---
Platform/Hisilicon/D03/D03.dsc | 1 +
In SCT test,we find SP805 watchdog driver can't reset when timeout
so we use another driver in MdeModulePkg.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangmin...@huawei.com>
Signed-off-by: Heyi Guo <heyi@linaro.org>
Signed-off-by:
Unify all D0x(include D06 in further) to cache coherent DmaLib.
This can improve boot speed.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Wang Yue <wangyu...@huawei.com>
Signed-off-by: Ming Huang <huangmin...@huawei.com>
Signed-off-by: Heyi Guo <heyi
Add PXM method for Pcie device, HNS device and SAS device.
Add STA method for HNS.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: hensonwang <wanghuiqi...@huawei.com>
Signed-off-by: Ming Huang <huangmin...@huawei.com>
Signed-off-by: Heyi Guo <heyi@linar
Update NativeOhci bianry for changing DmaLib to CoherentDmaLib.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangmin...@huawei.com>
Signed-off-by: Heyi Guo <heyi@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindh...@linaro.org>
---
1 Workarounds for CVE-2017-5715 on Cortex A57/A72/A73 and A75 #1214.
2 Upgrade trusted firmware to 1.4
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangmin...@huawei.com>
Signed-off-by: Heyi Guo <heyi@linaro.org>
Reviewed-by: Leif Lindholm
1 Workarounds for CVE-2017-5715 on Cortex A57/A72/A73 and A75 #1214.
2 Upgrade trusted firmware to 1.4
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangmin...@huawei.com>
Signed-off-by: Heyi Guo <heyi@linaro.org>
Reviewed-by: Leif Lindholm
acros
for PPTT".
Code can also be found in github:
https://github.com/hisilicon/OpenPlatformPkg.git
branch: rp-1802-platforms-v3
Heyi Guo (15):
Hisilicon/D05: Move Madt definition to head file
Hisilicon/D05: Add PPTT support
Hisilicon/D0x/BDS: Switch to Generic BDS driver
His
Move definition of Madt struct to head file, so PPTT driver
can include it.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangmin...@huawei.com>
Signed-off-by: Heyi Guo <heyi@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheu...@linar
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangmin...@huawei.com>
Signed-off-by: Heyi Guo <heyi@linaro.org>
---
MdePkg/Include/IndustryStandard/Acpi62.h | 18 ++
1 file changed, 18 insertions(+)
diff --git a/Md
Add some macros to Acpi62.h for PPTT as ACPI 6.2 Spec.
Heyi Guo (1):
MdePkg ACPI: Add some macros for PPTT
MdePkg/Include/IndustryStandard/Acpi62.h | 18 ++
1 file changed, 18 insertions(+)
--
1.9.1
___
edk2-devel mailing list
From: Ming Huang
Correct processor flags struct of PPTT in Acpi62.h.
Ming Huang (1):
MdePkg ACPI: Correct processor flags struct of PPTT
MdePkg/Include/IndustryStandard/Acpi62.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--
1.9.1
From: Ming Huang <huangmin...@huawei.com>
The Type field of EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR should
be UINT8 as ACPI version 6.2 specification.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangmin...@huawei.com>
Signed-off-by: He
Correct processor struct of PPTT in Acpi62.h
Ming Huang (1):
MdePkg ACPI: Correct processor struct of PPTT
MdePkg/Include/IndustryStandard/Acpi62.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--
1.9.1
___
edk2-devel mailing list
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangmin...@huawei.com>
Signed-off-by: Heyi Guo <heyi@linaro.org>
---
MdePkg/Include/IndustryStandard/Acpi62.h | 18 ++
1 file changed, 18 insertions(+)
diff --git a/Md
Add some macros to Acpi62.h for PPTT as ACPI 6.2 Spec.
Heyi Guo (1):
MdePkg ACPI: Add some macros for PPTT
MdePkg/Include/IndustryStandard/Acpi62.h | 18 ++
1 file changed, 18 insertions(+)
--
1.9.1
___
edk2-devel mailing list
Move definition of Madt struct to head file, so PPTT driver
can include it.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangmin...@huawei.com>
Signed-off-by: Heyi Guo <heyi@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheu...@linar
ed-off-by: Heyi Guo <heyi@linaro.org>
Signed-off-by: Jason Zhang <zhangjinso...@huawei.com>
Reviewed-by: Leif Lindholm <leif.lindh...@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheu...@linaro.org>
---
Platform/Hisilicon/D03/D03.dsc
Modify the feature of BMC set boot option as switching generic
BDS. Break BMC SetBoot option out into BmcConfigBootLib.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangmin...@huawei.com>
Signed-off-by: Heyi Guo <heyi@linaro.org>
Revie
In SCT test,we find SP805 watchdog driver can't reset when timeout
so we use another driver in MdeModulePkg.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangmin...@huawei.com>
Signed-off-by: Heyi Guo <heyi@linaro.org>
Signed-off-by:
Signed-off-by: Ming Huang <huangmin...@huawei.com>
Signed-off-by: Heyi Guo <heyi@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindh...@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheu...@linaro.org>
Reviewed-by: Graeme Gregory <graeme.greg...@linaro.org>
Reveiwed
acros for
PPTT".(hash:c4e7557)
2 Correct the email of Graeme Gregory.
Code can also be found in github:
https://github.com/hisilicon/OpenPlatformPkg.git
branch: rp-1802-platforms-v4
Heyi Guo (15):
Hisilicon/D05: Move Madt definition to head file
Hisilicon/D05: Add PPTT support
His
Unify all D0x(include D06 in further) to cache coherent DmaLib.
This can improve boot speed.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Wang Yue <wangyu...@huawei.com>
Signed-off-by: Ming Huang <huangmin...@huawei.com>
Signed-off-by: Heyi Guo <heyi
for PXE boot.
https://bugs.linaro.org/show_bug.cgi?id=2657
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jason Zhang <zhangjinso...@huawei.com>
Signed-off-by: Ming Huang <huangmin...@huawei.com>
Signed-off-by: Heyi Guo <heyi@linaro.org>
Reviewed
This module support updating the boot CPU firmware only.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jason Zhang <zhangjinso...@huawei.com>
Signed-off-by: Ming Huang <huangmin...@huawei.com>
Signed-off-by: Heyi Guo <heyi@linaro.org>
Reviewed-
Add ITS affinity structure in SRAT.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangmin...@huawei.com>
Signed-off-by: Heyi Guo <heyi@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheu...@linaro.org>
Reviewed-by: Leif Lindholm <lei
Replace the old string with short one. The old one is
too long that can not be show integrallty in Setup nemu.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangmin...@huawei.com>
Signed-off-by: Heyi Guo <heyi@linaro.org>
Reviewed-by: L
Add PXM method for Pcie device, HNS device and SAS device.
Add STA method for HNS.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: hensonwang <wanghuiqi...@huawei.com>
Signed-off-by: Ming Huang <huangmin...@huawei.com>
Signed-off-by: Heyi Guo <heyi@linar
-by: Ming Huang <huangmin...@huawei.com>
Signed-off-by: Heyi Guo <heyi@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindh...@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheu...@linaro.org>
---
Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c |
ed-off-by: Ming Huang <huangmin...@huawei.com>
Signed-off-by: Heyi Guo <heyi@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindh...@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheu...@linaro.org>
---
Platform/Hisilicon/D03/D03.dsc | 1 +
com>
Signed-off-by: Heyi Guo <heyi@linaro.org>
Signed-off-by: Yan Zhang <zhangya...@huawei.com>
Reviewed-by: Leif Lindholm <leif.lindh...@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheu...@linaro.org>
---
Silicon/Hisilicon/Hi1610/Drivers/Pc
passed the build for qemu64 and
the function has not been tested yet.
Please let me know your comments about it.
Thanks.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo <heyi@linaro.org>
Cc: Ruiyu Ni <ruiyu...@intel.com>
Cc: Ard Biesheuvel
@redhat.com>
Cc: Michael D Kinney <michael.d.kin...@intel.com>
Heyi Guo (2):
MdeModulePkg/PciHostBridgeDxe: Add support for address translation
MdeModulePkg/PciBus: return CPU address for GetBarAttributes
MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c | 9 +-
.../Bus/Pci/Pc
PciIo::GetBarAttributes should return CPU view address according to
UEFI spec 2.7, so we change the implementation to follow the spec.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo <heyi@linaro.org>
Cc: Ruiyu Ni <ruiyu...@intel.com>
Cc: Ar
ost address + translation offset.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo <heyi@linaro.org>
Cc: Ruiyu Ni <ruiyu...@intel.com>
Cc: Ard Biesheuvel <ard.biesheu...@linaro.org>
Cc: Star Zeng <star.z...@intel.com>
Cc: Eric Dong <eric.d.
o PciHostBridgeResourceConflict is host address,
for it comes from ResAllocNode.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo <heyi@linaro.org>
Cc: Ruiyu Ni <ruiyu...@intel.com>
Cc: Ard Biesheuvel <ard.biesheu...@linaro.org>
Cc: Star Zen
el.com>
Cc: Eric Dong <eric.d...@intel.com>
Cc: Laszlo Ersek <ler...@redhat.com>
Cc: Michael D Kinney <michael.d.kin...@intel.com>
Heyi Guo (3):
MdeModulePkg/PciHostBridgeDxe: Add support for address translation
MdeModulePkg/PciBus: convert host address to device address
will cause stack overflow and then system exception,
and it may be not easy to find that the exception is actually caused
by stack overflow.
So we limit the number of reconnect retry to 10 to improve code
robustness.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo <h
der: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo <heyi@linaro.org>
Cc: Ruiyu Ni <ruiyu...@intel.com>
Cc: Ard Biesheuvel <ard.biesheu...@linaro.org>
Cc: Star Zeng <star.z...@intel.com>
Cc: Eric Dong <eric.d...@intel.com>
Cc: Laszlo Ersek <ler
Hi Jiewen,
I searched the code in EDK2, and found there is another implementation of
DxeTcg2PhysicalPresenceLib for OVMF: the function
Tcg2PhysicalPresenceLibProcessRequest()
is called in PlatformBootManagerAfterConsole() on OVMF, and it doesn't invoke
VariableLockProtocol->RequestToLock() in
Is there any work around if we don't have such trusted console on available
hardware platforms? Is there any example implementation which we can refer to?
Thanks,
Heyi
On Fri, Aug 10, 2018 at 09:12:46AM +, Yao, Jiewen wrote:
> by design a platform need define a trusted console and only
Hi folks,
The function Tcg2PhysicalPresenceLibProcessRequest in DxeTcg2PhysicalPresenceLib
requires to be invoked after console is ready, and in the function it will call
VariableLockProtocol->RequestToLock(), while variable RequestToLock() requires
to be called before "End Of Dxe" event, or else
It is said that python3 is not compatible with python2. Can we use python3 to
build edk2?
Thanks,
Heyi
___
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel
That's really good news; thank you all!
Heyi
On Mon, Aug 27, 2018 at 05:58:35PM +0200, Laszlo Ersek wrote:
> On 08/27/18 15:31, Zhu, Yonghong wrote:
> > We have a bugzilla. https://bugzilla.tianocore.org/show_bug.cgi?id=55
> > Current I am working on it. And planned to finish to migrate to
Workarounds for CVE-2017-5715 on Cortex A57/A72/A73 and A75 #1214.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangmin...@huawei.com>
Signed-off-by: Heyi Guo <heyi@linaro.org>
---
Platform/Hisilicon/D03/bl1.bin | Bin 14336 -> 12416
Workarounds for CVE-2017-5715 on Cortex A57/A72/A73 and A75 #1214.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangmin...@huawei.com>
Signed-off-by: Heyi Guo <heyi@linaro.org>
---
Platform/Hisilicon/D05/bl1.bin | Bin 14344 -> 12424
Workarounds for CVE-2017-5715 on Cortex A57/A72/A73 and A75 #1214.
Heyi Guo (2):
Hisilicon/D03: Update binary of trusted-firmware
Hisilicon/D05: Update binary of trusted-firmware
Platform/Hisilicon/D03/bl1.bin | Bin 14336 -> 12416 bytes
Platform/Hisilicon/D03/fip.bin | Bin 62513 ->
hang <zhangjinso...@huawei.com>
Signed-off-by: Heyi Guo <heyi@linaro.org>
Cc: Ard Biesheuvel <ard.biesheu...@linaro.org>
Cc: Leif Lindholm <leif.lindh...@linaro.org>
Cc: Graeme Gregory <graeme.greg...@linaro.org>
---
Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc |
From: Chenhui Sun <sunchen...@huawei.com>
Add description of SBSA watchdogs to ACPI GTDT on D05.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chenhui Sun <sunchen...@huawei.com>
Signed-off-by: Heyi Guo <heyi@linaro.org>
Cc: Ard Biesheuvel <ard.
We need to set PcdShellLibAutoInitialize to FALSE for
TftpDynamicCommand, or else we will get initialization failure when
loading TftpDynamicCommand module, for EFI Shell has not been started
at this moment.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo <h
Since D0x platforms always have network enabled, we would like to
enable tftp command by default so that we can download something in
EFI Shell.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo <heyi@linaro.org>
Cc: Ard Biesheuvel <ard.biesheu...@linar
Resetting timer compare register has a side effect of clearing GIC
pending status, if timer interrupt is level sensitive, so a "DSB SY"
is needed to make sure this change effect is synchronized.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo <heyi..
fixed if we add a "DSB" after reloading timer compare value, and
we think that it makes sense to do that.
Cc: Leif Lindholm <leif.lindh...@linaro.org>
Cc: Ard Biesheuvel <ard.biesheu...@linaro.org>
Cc: Marc Zyngier <marc.zyng...@arm.com>
Heyi Guo (1):
ArmPkg/TimerD
GICv3. D03 also works for this patch. If the
platforms only have GICv2, this change will have no impact on them.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: gongchengya <gongcheng...@huawei.com>
Signed-off-by: Heyi Guo <heyi@linaro.org>
Cc: Ard Biesh
hang <zhangjinso...@huawei.com>
Signed-off-by: Heyi Guo <heyi@linaro.org>
Cc: Ard Biesheuvel <ard.biesheu...@linaro.org>
Cc: Leif Lindholm <leif.lindh...@linaro.org>
Cc: Graeme Gregory <graeme.greg...@linaro.org>
---
Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc |
From: Chenhui Sun <sunchen...@huawei.com>
Add description of SBSA watchdogs to ACPI GTDT on D05.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chenhui Sun <sunchen...@huawei.com>
Signed-off-by: Heyi Guo <heyi@linaro.org>
Cc: Ard Biesheuvel <ard.
These 3 patches are to fix SBSA-ACS test failures for system timer and watch dog
timer on Hisilicon/D05.
Cc: Ard Biesheuvel
Cc: Leif Lindholm
Cc: Graeme Gregory
Cc: Haojian Zhuang
v2:
-
also remove a duplicated declaration of BmRepairAllControllers() in
InternalBm.h in this patch, for it is only a trivial change.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo <heyi@linaro.org>
Cc: Star Zeng <star.z...@intel.com>
Cc: Eric
;anthony.per...@citrix.com>
Cc: Julien Grall <julien.gr...@linaro.org>
Heyi Guo (6):
CorebootPayloadPkg/PciHostBridgeLib: Init PCI aperture to 0
OvmfPkg/PciHostBridgeLib: Init PCI aperture to 0
MdeModulePkg/PciHostBridgeLib.h: add address Translation
MdeModulePkg/PciHostBridgeDxe: A
ost address + translation offset.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo <heyi@linaro.org>
Cc: Ruiyu Ni <ruiyu...@intel.com>
Cc: Ard Biesheuvel <ard.biesheu...@linaro.org>
Cc: Star Zeng <star.z...@intel.com>
Cc: Eric Dong <eric.d.
an additional
change.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo <heyi@linaro.org>
Cc: Jordan Justen <jordan.l.jus...@intel.com>
Cc: Anthony Perard <anthony.per...@citrix.com>
Cc: Julien Grall <julien.gr...@linaro.org>
Cc: Ruiyu Ni
: to simplify the situation, we require the alignment of
Translation must be larger than any BAR alignment in the same root
bridge, so that resource allocation alignment can be applied to both
device address and host address.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by:
ert it to a PCI address". This means:
Translation = device address - host address
So we also use the above calculation for this Translation field to
keep consistent.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo <heyi@linaro.org>
---
Md
der: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo <heyi@linaro.org>
Cc: Ruiyu Ni <ruiyu...@intel.com>
Cc: Ard Biesheuvel <ard.biesheu...@linaro.org>
Cc: Star Zeng <star.z...@intel.com>
Cc: Eric Dong <eric.d...@intel.com>
Cc: Laszlo Ersek <ler
an additional change.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo <heyi@linaro.org>
Cc: Maurice Ma <maurice...@intel.com>
Cc: Prince Agyeman <prince.agye...@intel.com>
Cc: Benjamin You <benjamin@intel.com>
Cc: Ruiyu Ni <ruiyu...@intel
fixed if we add a "ISB" after reloading timer compare value, and
we agree that it makes sense to do that.
Cc: Leif Lindholm <leif.lindh...@linaro.org>
Cc: Ard Biesheuvel <ard.biesheu...@linaro.org>
Cc: Marc Zyngier <marc.zyng...@arm.com>
Heyi Guo (1):
ArmPkg/TimerD
ntribution Agreement 1.1
Signed-off-by: Heyi Guo <heyi@linaro.org>
Signed-off-by: Yi Li <phoenix.l...@huawei.com>
Cc: Leif Lindholm <leif.lindh...@linaro.org>
Cc: Ard Biesheuvel <ard.biesheu...@linaro.org>
Cc: Marc Zyngier <marc.zyng...@arm.com>
---
Notes:
: to simplify the situation, we require the alignment of
Translation must be larger than any BAR alignment in the same root
bridge, so that resource allocation alignment can be applied to both
device address and host address.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Hey
ert it to a PCI address". This means:
Translation = device address - host address
So we also use the above calculation for this Translation field to
keep consistent.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo <heyi@linaro.org>
Signed-off-by: Yi L
ost address + translation offset.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo <heyi@linaro.org>
Signed-off-by: Yi Li <phoenix.l...@huawei.com>
Reviewed-by: Ni Ruiyu <ruiyu...@intel.com>
Cc: Ruiyu Ni <ruiyu...@intel.com>
Cc: Ard Biesheuvel <
der: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo <heyi@linaro.org>
Signed-off-by: Yi Li <phoenix.l...@huawei.com>
Reviewed-by: Ni Ruiyu <ruiyu...@intel.com>
Cc: Ruiyu Ni <ruiyu...@intel.com>
Cc: Ard Biesheuvel <ard.biesheu...@linaro.org>
Cc: Star Zeng &l
will not suffer from an additional change.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo <heyi@linaro.org>
Signed-off-by: Yi Li <phoenix.l...@huawei.com>
Reviewed-by: Ni Ruiyu <ruiyu...@intel.com>
Cc: Maurice Ma <maurice...@intel.com>
Cc: Pri
t;benjamin@intel.com>
Cc: Jordan Justen <jordan.l.jus...@intel.com>
Cc: Anthony Perard <anthony.per...@citrix.com>
Cc: Julien Grall <julien.gr...@linaro.org>
Heyi Guo (6):
CorebootPayloadPkg/PciHostBridgeLib: clear aperture vars for (re)init
OvmfPkg/PciHostBridgeLib: clear
fixed if we add a "ISB" after reloading timer compare value, and
we agree that it makes sense to do that.
v3:
- Implement 1 comment from Marc.
Cc: Leif Lindholm <leif.lindh...@linaro.org>
Cc: Ard Biesheuvel <ard.biesheu...@linaro.org>
Cc: Marc Zyngier <marc.zyng...@arm
ntribution Agreement 1.1
Signed-off-by: Heyi Guo <heyi@linaro.org>
Signed-off-by: Yi Li <phoenix.l...@huawei.com>
Acked-by: Marc Zyngier <marc.zyng...@arm.com>
Cc: Leif Lindholm <leif.lindh...@linaro.org>
Cc: Ard Biesheuvel <ard.biesheu...@linaro.org>
Cc: Marc Z
will not suffer from an additional
change.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo <heyi@linaro.org>
Signed-off-by: Yi Li <phoenix.l...@huawei.com>
Cc: Jordan Justen <jordan.l.jus...@intel.com>
Cc: Anthony Perard <anthony.per...@citrix.
: to simplify the situation, we require the alignment of
Translation must be larger than any BAR alignment in the same root
bridge, so that resource allocation alignment can be applied to both
device address and host address.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: H
ert it to a PCI address". This means:
Translation = device address - host address
So we also use the above calculation for this Translation field to
keep consistent.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo <heyi@linaro.org>
Signed-off-by: Yi L
will not suffer from an additional change.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo <heyi@linaro.org>
Signed-off-by: Yi Li <phoenix.l...@huawei.com>
Cc: Maurice Ma <maurice...@intel.com>
Cc: Prince Agyeman <prince.agye...@intel.com>
Cc
ost address + translation offset.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo <heyi@linaro.org>
Signed-off-by: Yi Li <phoenix.l...@huawei.com>
Cc: Ruiyu Ni <ruiyu...@intel.com>
Cc: Ard Biesheuvel <ard.biesheu...@linaro.org>
Cc: Star Zeng <
der: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo <heyi@linaro.org>
Signed-off-by: Yi Li <phoenix.l...@huawei.com>
Cc: Ruiyu Ni <ruiyu...@intel.com>
Cc: Ard Biesheuvel <ard.biesheu...@linaro.org>
Cc: Star Zeng <star.z...@intel.com>
Cc: Eric Dong <eric.d
ted-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo <heyi@linaro.org>
Signed-off-by: Yi Li <phoenix.l...@huawei.com>
Cc: Ard Biesheuvel <ard.biesheu...@linaro.org>
Cc: Leif Lindholm <leif.lindh...@linaro.org>
Cc: Michael D Kinney <michael.d.k
les can be fetched from:
https://github.com/iwishguo/edk2-non-osi/tree/patch-sm750-fix-v2
v2:
- Unify binary files for D03 and D05 [Ard]
Cc: Ard Biesheuvel <ard.biesheu...@linaro.org>
Cc: Leif Lindholm <leif.lindh...@linaro.org>
Cc: Michael D Kinney <michael.d.kin...@intel.
other attributes.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo <heyi@linaro.org>
Signed-off-by: Yi Li <phoenix.l...@huawei.com>
Signed-off-by: Renhao Liang <liangren...@huawei.com>
Cc: Star Zeng <star.z...@intel.com>
Cc: Eric Dong &l
Signed-off-by: Heyi Guo <heyi@linaro.org>
Signed-off-by: Yi Li <phoenix.l...@huawei.com>
Cc: Ard Biesheuvel <ard.biesheu...@linaro.org>
Cc: Leif Lindholm <leif.lindh...@linaro.org>
Cc: Michael D Kinney <michael.d.kin...@intel.com>
---
Platform/Hisilicon/D03/D03.dsc
ntributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo <heyi@linaro.org>
Signed-off-by: Yi Li <phoenix.l...@huawei.com>
Signed-off-by: Renhao Liang <liangren...@huawei.com>
Cc: Star Zeng <star.z...@intel.com>
Cc: Eric Dong <eric.d...@intel.com&
tch-sm750-fix
Cc: Ard Biesheuvel <ard.biesheu...@linaro.org>
Cc: Leif Lindholm <leif.lindh...@linaro.org>
Cc: Michael D Kinney <michael.d.kin...@intel.com>
Heyi Guo (1):
Hisilicon/D0x/Sm750: Fix GOP framebuffer base
Platform/Hisilicon/D03/Drivers/Sm750Dxe/SmiGraphicsO
The code in SM750 driver treated the address returned from
PciIo->GetBarAttributes() as device address; this should be fixed
after edk2 commit dc080d3 since GetBarAttributes() returns host
address from then on.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo &l
This is to prepare for switching to generic PciHostBridge, and
CpuIo2Dxe is needed by generic PciHostBridge driver.
The driver is copied from ArmPkg/Drivers/ArmPciCpuIo2Dxe and changed
for D0x.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo <heyi@linaro.
This is to prepare for switching to generic PciHostBridge, and
PciSegmentLib is needed by generic PciHostBridge driver.
This module copied from
edk2-platforms/Silicon/Socionext/SynQuacer/Library/SynQuacerPciSegmentLib.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi
1.1
Signed-off-by: Heyi Guo <heyi@linaro.org>
Cc: Ard Biesheuvel <ard.biesheu...@linaro.org>
Cc: Leif Lindholm <leif.lindh...@linaro.org>
Cc: Michael D Kinney <michael.d.kin...@intel.com>
---
Pla
Signed-off-by: Heyi Guo <heyi@linaro.org>
Cc: Ard Biesheuvel <ard.biesheu...@linaro.org>
Cc: Leif Lindholm <leif.lindh...@linaro.org>
Cc: Michael D Kinney <michael.d.kin...@intel.com>
Cc: Haojian Zhuang <haojian.zhu...@linaro.org>
---
Silicon/Hisilicon/Hisilico
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