[gem5-dev] Change in gem5/gem5[master]: arch-riscv: Add interrupt handling

Alec Roelke has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/14377 ) Change subject: arch-riscv: Add interrupt handling .. arch-riscv: Add interrupt handling Implement the

[gem5-dev] Change in gem5/gem5[master]: arch-riscv: Fix reset function and style

Alec Roelke has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/14376 ) Change subject: arch-riscv: Fix reset function and style .. arch-riscv: Fix reset function and style In

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Fix usage of RegId constructor for VecElem

Giacomo Travaglini has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/15615 ) Change subject: arch-arm: Fix usage of RegId constructor for VecElem .. arch-arm: Fix usage of

[gem5-dev] Change in gem5/gem5[master]: cpu: Fix usage of setArchVecElem

Giacomo Travaglini has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/15655 ) Change subject: cpu: Fix usage of setArchVecElem .. cpu: Fix usage of setArchVecElem

[gem5-dev] Change in gem5/gem5[master]: cpu: Fix usage of setArchVecElem

Hello Gabe Black, Anthony Gutierrez, Jason Lowe-Power, Andreas Sandberg, Giacomo Gabrielli, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/15655 to look at the new patch set (#3). Change subject: cpu: Fix usage of setArchVecElem

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Fix usage of RegId constructor for VecElem

Hello Ciro Santilli, Andreas Sandberg, Giacomo Gabrielli, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/15615 to look at the new patch set (#3). Change subject: arch-arm: Fix usage of RegId constructor for VecElem

[gem5-dev] Change in gem5/gem5[master]: cpu: Fix usage of setArchVecElem

Hello Gabe Black, Anthony Gutierrez, Jason Lowe-Power, Andreas Sandberg, Giacomo Gabrielli, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/15655 to look at the new patch set (#2). Change subject: cpu: Fix usage of setArchVecElem

[gem5-dev] Change in gem5/gem5[master]: cpu: Fix usage of setArchVecElem

Hello Giacomo Gabrielli, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/15655 to review the following change. Change subject: cpu: Fix usage of setArchVecElem .. cpu:

[gem5-dev] Change in gem5/gem5[master]: arm: Fix usage of RegId constructor for VecElem

Hello Ciro Santilli, Andreas Sandberg, Giacomo Gabrielli, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/15615 to look at the new patch set (#2). Change subject: arm: Fix usage of RegId constructor for VecElem

[gem5-dev] Change in gem5/gem5[master]: base: Fix unitialized storage

Daniel Carvalho has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/15635 Change subject: base: Fix unitialized storage .. base: Fix unitialized storage The bitunion was not being

[gem5-dev] Change in gem5/gem5[master]: cpu: Fix VecElemClass bugs in cpu models

Hello Gabe Black, Anthony Gutierrez, Andreas Sandberg, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/15598 to look at the new patch set (#3). Change subject: cpu: Fix VecElemClass bugs in cpu models

[gem5-dev] Change in gem5/gem5[master]: cpu, arch, arch-arm: Wire unused VecElem code in the O3 model

Hello Gabe Black, Anthony Gutierrez, Andreas Sandberg, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/15601 to look at the new patch set (#3). Change subject: cpu, arch, arch-arm: Wire unused VecElem code in the O3 model

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Inital vector rename mode depending on A32/A64

Hello Ciro Santilli, Andreas Sandberg, Ciro Santilli, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/15599 to look at the new patch set (#2). Change subject: arch-arm: Inital vector rename mode depending on A32/A64

[gem5-dev] Change in gem5/gem5[master]: cpu: Add VecElem entries in MinorCPU Scoreboard

Hello Gabe Black, Anthony Gutierrez, Andreas Sandberg, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/15597 to look at the new patch set (#2). Change subject: cpu: Add VecElem entries in MinorCPU Scoreboard

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Read VMPIDR instead of MPIDR when EL2 is Enabled

Hello Andreas Sandberg, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/15617 to review the following change. Change subject: arch-arm: Read VMPIDR instead of MPIDR when EL2 is Enabled

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Added TLBI_ALL EL2 instruction

Hello Anouk Van Laer, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/15616 to review the following change. Change subject: arch-arm: Added TLBI_ALL EL2 instruction ..

[gem5-dev] Change in gem5/gem5[master]: cpu, arm: Fix usage of VecElem

Hello Giacomo Gabrielli, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/15615 to review the following change. Change subject: cpu, arm: Fix usage of VecElem .. cpu,

Re: [gem5-dev] Thoughts On Project Using C++14 (two years late)

Hi, On my local dev branch, I use C++14, but I don’t have the opportunity to compile/test all the possible Scons targets. Before April, we could upload a [WIP] patch on Gerrit with the new compiler flag(s) and share our thoughts from a different environment and on different targets. I agree

[gem5-dev] Change in gem5/gem5[master]: cpu, arch, arch-arm: Wire unused VecElem code in the O3 model

Giacomo Travaglini has uploaded a new patch set (#2). ( https://gem5-review.googlesource.com/c/public/gem5/+/15601 ) Change subject: cpu, arch, arch-arm: Wire unused VecElem code in the O3 model .. cpu, arch, arch-arm:

[gem5-dev] Change in gem5/gem5[master]: cpu: Fix VecElemClass bugs in cpu models

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/15598 Change subject: cpu: Fix VecElemClass bugs in cpu models .. cpu: Fix VecElemClass bugs in cpu models This

[gem5-dev] Change in gem5/gem5[master]: arch: Provide traceback when parsing ISA code

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/15595 Change subject: arch: Provide traceback when parsing ISA code .. arch: Provide traceback when parsing ISA

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Remove unused float operands

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/15596 Change subject: arch-arm: Remove unused float operands .. arch-arm: Remove unused float operands Removing

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Remove floatReg operand type

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/15604 Change subject: arch-arm: Remove floatReg operand type .. arch-arm: Remove floatReg operand type

[gem5-dev] Change in gem5/gem5[master]: cpu: O3 rename using the flatIndex instead of index

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/15600 Change subject: cpu: O3 rename using the flatIndex instead of index .. cpu: O3 rename using the flatIndex

[gem5-dev] Change in gem5/gem5[master]: arch: Fix VecElem Operand generation in ISA parser

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/15602 Change subject: arch: Fix VecElem Operand generation in ISA parser .. arch: Fix VecElem Operand generation

[gem5-dev] Change in gem5/gem5[master]: cpu, arch, arch-arm: Wire unused VecElem code in the O3 model

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/15601 Change subject: cpu, arch, arch-arm: Wire unused VecElem code in the O3 model .. cpu, arch, arch-arm:

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Use VecElem instead of FloatReg for FP instruction

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/15603 Change subject: arch-arm: Use VecElem instead of FloatReg for FP instruction .. arch-arm: Use VecElem

[gem5-dev] Change in gem5/gem5[master]: cpu: Add VecElem entries in MinorCPU Scoreboard

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/15597 Change subject: cpu: Add VecElem entries in MinorCPU Scoreboard .. cpu: Add VecElem entries in MinorCPU

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Inital vector rename mode depending on A32/A64

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/15599 Change subject: arch-arm: Inital vector rename mode depending on A32/A64 .. arch-arm: Inital vector rename

Re: [gem5-dev] Thoughts On Project Using C++14 (two years late)

Hi all, In practice, C++14 support should mean g++ version 5 or above or clang 3.4 or above. Clang supports all C++17 features from version 5, but most features should be supported from version 3.9 (a large subset is supported in 3.8). GCC version 7 and above seems to support most of C++17.

[gem5-dev] Cron /z/m5/regression/do-regression quick

* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing-ruby: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-atomic: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing: FAILED! *