Sascha Bischoff has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/64331?usp=email )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: arch-arm: Set ZCR_ELx before
Sascha Bischoff has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/64333?usp=email )
Change subject: arch,cpu: Add boilerplate support for matrix registers
..
arch,cpu: Add
Sascha Bischoff has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/64341?usp=email )
Change subject: system-arm: Enable SME in the bootloader
..
system-arm: Enable SME
Sascha Bischoff has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/64338?usp=email )
Change subject: arch, arch-arm, cpu: Add matrix reg support to the ISA
Parser
..
arch, arch-arm
Sascha Bischoff has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/64336?usp=email )
Change subject: arch-arm: Add interfaces to set and get SME vector length
..
arch-arm: Add
Sascha Bischoff has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/64332?usp=email )
Change subject: cpu-o3: Remove obsolete getRegIds and getTrueId
..
cpu-o3: Remove obsolete
Sascha Bischoff has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/64340?usp=email )
Change subject: mem-cache: masked writes are not whole-line writes
..
mem-cache: masked writes
Sascha Bischoff has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/64331?usp=email )
Change subject: arch-arm: Set ZCR_ELx before updating vector length in
decoder
..
arch-arm: Set
Sascha Bischoff has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/64337?usp=email )
Change subject: arch-arm: Implement SME access traps and extend the SVE ones
..
arch-arm
Sascha Bischoff has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/64342?usp=email )
Change subject: cpu-o3: print VecPredReg not VecReg
..
cpu-o3: print VecPredReg not VecReg
Fix
Sascha Bischoff has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/64335?usp=email )
Change subject: arch-arm: Add system registers added/used by SME
..
arch-arm: Add system registers
Hi Gabe,
As Jason said, some attempts at creating an output database went uncommitted. A
few years ago (2012, apparently…!) I worked on updating Nate’s Python stats
patches to allow the use of an SQLite database. As you can guess, it was never
committed. However, the patches can still be found
changeset 8732d8d0a9e5 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=8732d8d0a9e5
description:
mem: Fix MSHR assert triggering for invalidated prefetches
This changeset updates an assert in src/mem/cache/mshr.cc which was
erroneously catching
changeset 871eaaa0ab24 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=871eaaa0ab24
description:
misc: Bail out of DVFS dot if we cannot resolve the domains
This changeset updates the dot output to bail out if it is unable to
resolve the voltage or
a8f47eac src/python/m5/util/dot_writer.py
--- a/src/python/m5/util/dot_writer.py Fri Dec 11 17:29:53 2015 +
+++ b/src/python/m5/util/dot_writer.py Tue Dec 15 09:40:56 2015 +
@@ -35,6 +35,7 @@
#
# Authors: Andreas Hansson
# Uri Wiener
+# Sascha Bischoff
changeset 6e89c756e1fb in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=6e89c756e1fb
description:
sim: Add additional debug information when draining
This patch adds some additional information when draining the system
which
allows the user to debug
changeset a10d9e2ef671 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=a10d9e2ef671
description:
sim: Fix clock_domain unserialization
This patch addresses an issue with the unserialization of clock
domains. Previously, the previous performance level
changeset 7a9eeecf2b52 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=7a9eeecf2b52
description:
dev: Add basic checkpoint support to VirtIO9PProxy device
This patch adds very basic checkpoint support for the VirtIO9PProxy
device. Previously, attempts
changeset 406240a8e7ef in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=406240a8e7ef
description:
dev: Fix segfault in flash device
Fix a bug in which the flash device would write out of bounds and
could either trigger a segfault and corrupt the memory
changeset 8e240cd8132a in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=8e240cd8132a
description:
dev: Fix draining for UFSHostDevice and FlashDevice
This patch fixes the drain logic for the UFSHostDevice and the
FlashDevice. In the case of the
changeset 94d6ffac1e9b in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=94d6ffac1e9b
description:
mem: Auto-generate CommMonitor trace file names
Splits the CommMonitor trace_file parameter into three parameters.
Previously,
the trace was only enabled
changeset 266db8ff9ae8 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=266db8ff9ae8
description:
misc: Proper type check and import for PortRef
Rewriting the type checking around PortRef, which was interacting
strangely
with other Python scripts.
changeset eb34ae5204b8 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=eb34ae5204b8
description:
mem: CommMonitor trace warn on non-timing mode
Add a warning to the CommMonitor which will alert the user if they try
and record a trace when the system
changeset cc1e0ea8e450 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=cc1e0ea8e450
description:
mem: Add PortID to QueuedMasterPort constructor
This patch adds the PortID to the QueuedMasterPort. This allows a
PortID to be
specified as it previously
---
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/1991/#review4667
---
Ship it!
Looks fine to me.
- Sascha Bischoff
On Aug. 27, 2013, 1:32
changeset dcd0f0091854 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=dcd0f0091854
description:
cpu: Fix TrafficGen trace playback
This patch addresses an issue with trace playback in the TrafficGen
where the trace was reset but the header was not
changeset 68b47cb5c0a6 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=68b47cb5c0a6
description:
stats: Remove printing of SparseHist total
This patch removes the printing of the SparseHist total in the
stats.txt output file. This has been removed as
changeset dd486672c9d0 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=dd486672c9d0
description:
cpu: Fix bug when reading in TrafficGen state transitions
This patch fixes a bug with the traffic generator which occured when
reading in the state
changeset 2ddec848b8e8 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=2ddec848b8e8
description:
cpu: Check that minimum TrafficGen period is less than max period
Add a check which ensures that the minumum period for the LINEAR and
RANDOM traffic
On April 24, 2013, 9:37 p.m., Nathan Binkert wrote:
src/python/m5/stats/display.py, line 177
http://reviews.gem5.org/r/1643/diff/3/?file=35285#file35285line177
try/except may be faster here. I haven't benchmarked that though.
I had a look, seems like try/except is very slightly
On Feb. 8, 2013, 3:53 p.m., Nilay Vaish wrote:
src/python/m5/stats/info.py, line 95
http://reviews.gem5.org/r/1677/diff/1/?file=33681#file33681line95
Why is the difference between a float and a scalar?
A scalar is the gem5 stats system specific type (as defined in info.py),
On Feb. 5, 2013, 4:21 p.m., Nathan Binkert wrote:
This really confuses me. A the idea of the Formula class was that it was a
Vector, and we'd simply pretend that Formulas of length 1 were scalars. It
seems wrong to me to have two classes here and we need to fix the main
class
changeset a373b2e664ff in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=a373b2e664ff
description:
mem: Fix SenderState related cache deadlock
This patch fixes a potential deadlock in the caches. This deadlock
could occur when more than one cache is
changeset d05714c2ab9c in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=d05714c2ab9c
description:
base: Add warn() and inform() to m5.utils for use from python
This patch adds two fuctions to m5.util, warn and inform, which mirror
those
found in the
On Jan. 25, 2013, 9:58 a.m., Nilay Vaish wrote:
A double is 8 bytes, and each character in a text-based output is
probably = 1 byte, depending on the encoding. If the double value
actually holds less than 8 characters, I am surprised that a
float value does not suffice. What other info
On Jan. 25, 2013, 9:05 a.m., Nathan Binkert wrote:
src/python/m5/stats/display.py, line 222
http://reviews.gem5.org/r/1636/diff/1/?file=33198#file33198line222
Why is this in this commit? doesn't seem like a bugfix to me. What
problem is this fixing?
I have split this into a
On Jan. 25, 2013, 9:05 a.m., Nathan Binkert wrote:
src/python/m5/stats/__init__.py, line 317
http://reviews.gem5.org/r/1636/diff/1/?file=33196#file33196line317
Seems odd to get rid of pydoc in favor of doxygen.
We decided to use doxygen as it allowed us to have the documentation
On Jan. 25, 2013, 9:08 a.m., Nathan Binkert wrote:
src/python/m5/stats/info.py, line 923
http://reviews.gem5.org/r/1637/diff/1/?file=33200#file33200line923
I'm sure I'm being pedantic, but this is a bugfix for something else.
Yes it is. I have moved it into the generic bugfixes
On Jan. 25, 2013, 10:12 a.m., Nilay Vaish wrote:
src/python/m5/main.py, line 291
http://reviews.gem5.org/r/1638/diff/2/?file=33514#file33514line291
Why do you want this check here?
If both the text-based stats and the sql stats are disabled, then gem5 will not
produce any stats.
On Jan. 25, 2013, 9:20 a.m., Nathan Binkert wrote:
Nathan Binkert wrote:
Also continious - contiguous
Changed.
On Jan. 25, 2013, 9:20 a.m., Nathan Binkert wrote:
src/python/m5/stats/display.py, line 435
http://reviews.gem5.org/r/1640/diff/1/?file=33207#file33207line435
On Jan. 25, 2013, 9:28 a.m., Nathan Binkert wrote:
Looks good. Make me think that we should have a harmonic mean for
completeness. Seems like it would be relatively easy to add this to the
distribution stat as well.
Sounds like a good idea. Are you OK with this being added at a later
On Jan. 25, 2013, 9:41 a.m., Nilay Vaish wrote:
src/python/m5/stats/sql.py, line 265
http://reviews.gem5.org/r/1641/diff/1/?file=33215#file33215line265
salf?
Fixed. Thanks.
- Sascha
---
This is an automatically generated
On Jan. 25, 2013, 9:45 a.m., Nilay Vaish wrote:
src/python/m5/stats/display.py, line 182
http://reviews.gem5.org/r/1643/diff/1/?file=33218#file33218line182
Why do we need to re-create noNan?
We don't and it has been removed.
- Sascha
On Jan. 25, 2013, 9:46 a.m., Nilay Vaish wrote:
src/python/m5/stats/__init__.py, line 353
http://reviews.gem5.org/r/1643/diff/1/?file=33217#file33217line353
Since you are changing this function call, should not the function
definition also change?
Sorry, not quite sure how this
On Jan. 25, 2013, 9:48 a.m., Nathan Binkert wrote:
src/python/m5/stats/display.py, line 269
http://reviews.gem5.org/r/1643/diff/1/?file=33218#file33218line269
I don't think that you're improving anything here at all. Are you sure
you understand __getattr__?
This is not trying
changeset 35d4879ad7c2 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=35d4879ad7c2
description:
stats: Fix swig wrapping for Tick in stats
Tick was not correctly wrapped for the stats system, and therefore it
was not
possible to configure the stats
changeset 04dfa1898882 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=04dfa1898882
description:
Util: Added script to semantically diff two config.ini files
This script (util/diff_config.pl) takes two config.ini files and
compares them.
It
Binkert
+ * Sascha Bischoff
*/
// This file will contain default statistics for the simulator that
@@ -61,6 +74,8 @@
Time statTime(true);
Tick startTick;
+Event *dumpEvent;
+
struct SimTicksReset : public Callback
{
void process()
@@ -198,6 +213,9 @@
static Global
Hi,
This change stops me compiling gem5 for ARM with GCC 4.4.3 on Ubuntu 10.04
64bit. The errors I get are:
build/ARM/cpu/decode_cache.hh:61: error: using 'typename' outside of template
build/ARM/cpu/decode_cache.hh:62: error: using 'typename' outside of template
This appears to be due to the
49 matches
Mail list logo
