[gem5-dev] Change in public/gem5[master]: tests: Resurrect initest input file(s).

[Gabe Black (Gerrit)]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/6041



Change subject: tests: Resurrect initest input file(s).
..

tests: Resurrect initest input file(s).

Delete the current version of foo.ini which was modified, restore the
previous version, and initest.ini. Preprocess initest.ini which
includes foo.ini, and tidy up the resulting file. This file will
(mostly) get the initest unit test to work. Some other cleanups are
still necessary.

Change-Id: I4e46abc73ac89f88177eec92f572452f63ba8019
---
D src/unittest/foo.ini
A src/unittest/initest.ini
2 files changed, 17 insertions(+), 9 deletions(-)



diff --git a/src/unittest/foo.ini b/src/unittest/foo.ini
deleted file mode 100644
index 0f91c1f..000
--- a/src/unittest/foo.ini
+++ /dev/null
@@ -1,9 +0,0 @@
-[Foo]
-Foo1=89
-Foo2=384
-
-[General]
-Test3=89
-
-[Junk]
-Test4+=mia
diff --git a/src/unittest/initest.ini b/src/unittest/initest.ini
new file mode 100644
index 000..212c790
--- /dev/null
+++ b/src/unittest/initest.ini
@@ -0,0 +1,17 @@
+[General]
+   Test1=BARasdf
+   Test2=bar
+
+[Junk]
+Test3=yo
+Test4=mama
+
+[Foo]
+Foo1=89
+Foo2=384
+
+[General]
+Test3=89
+
+[Junk]
+Test4+=mia

--
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Gerrit-Project: public/gem5
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Gerrit-Change-Id: I4e46abc73ac89f88177eec92f572452f63ba8019
Gerrit-Change-Number: 6041
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
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[gem5-dev] Change in public/gem5[master]: arch-riscv: Move compressed ops out of ISA

[Alec Roelke (Gerrit)]

Alec Roelke has uploaded this change for review. (  
https://gem5-review.googlesource.com/6026



Change subject: arch-riscv: Move compressed ops out of ISA
..

arch-riscv: Move compressed ops out of ISA

This patch moves static portions of the compressed instruction
definitions out of the ISA generated code.

Change-Id: I61daae8b8c03a9e0f012790a132aa4d34a6ec296
---
M src/arch/riscv/insts/SConscript
A src/arch/riscv/insts/compressed.cc
A src/arch/riscv/insts/compressed.hh
M src/arch/riscv/isa/formats/compressed.isa
M src/arch/riscv/isa/includes.isa
5 files changed, 47 insertions(+), 29 deletions(-)



diff --git a/src/arch/riscv/insts/SConscript  
b/src/arch/riscv/insts/SConscript

index d058f85..39205a2 100644
--- a/src/arch/riscv/insts/SConscript
+++ b/src/arch/riscv/insts/SConscript
@@ -2,6 +2,7 @@

 if env['TARGET_ISA'] == 'riscv':
 Source('amo.cc')
+Source('compressed.cc')
 Source('mem.cc')
 Source('standard.cc')
 Source('static_inst.cc')
diff --git a/src/arch/riscv/insts/compressed.cc  
b/src/arch/riscv/insts/compressed.cc

new file mode 100644
index 000..8a8481e
--- /dev/null
+++ b/src/arch/riscv/insts/compressed.cc
@@ -0,0 +1,21 @@
+#include "arch/riscv/insts/compressed.hh"
+
+#include 
+#include 
+
+#include "arch/riscv/utility.hh"
+#include "cpu/static_inst.hh"
+
+namespace RiscvISA
+{
+
+std::string
+CompRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+std::stringstream ss;
+ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " <<
+registerName(_srcRegIdx[0]);
+return ss.str();
+}
+
+}
\ No newline at end of file
diff --git a/src/arch/riscv/insts/compressed.hh  
b/src/arch/riscv/insts/compressed.hh

new file mode 100644
index 000..7d7e693
--- /dev/null
+++ b/src/arch/riscv/insts/compressed.hh
@@ -0,0 +1,24 @@
+#ifndef __ARCH_RISCV_INSTS_COMPRESSED_HH__
+#define __ARCH_RISCV_INSTS_COMPRESSED_HH__
+
+#include 
+
+#include "arch/riscv/insts/static_inst.hh"
+#include "cpu/static_inst.hh"
+
+namespace RiscvISA
+{
+
+/**
+ * Base class for compressed operations that work only on registers
+ */
+class CompRegOp : public RiscvStaticInst
+{
+  protected:
+using RiscvStaticInst::RiscvStaticInst;
+std::string generateDisassembly(Addr pc, const SymbolTable *symtab)  
const;

+};
+
+}
+
+#endif // __ARCH_RISCV_INSTS_COMPRESSED_HH__
\ No newline at end of file
diff --git a/src/arch/riscv/isa/formats/compressed.isa  
b/src/arch/riscv/isa/formats/compressed.isa

index 1fd2319..91b6672 100644
--- a/src/arch/riscv/isa/formats/compressed.isa
+++ b/src/arch/riscv/isa/formats/compressed.isa
@@ -28,35 +28,6 @@
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 //
 // Authors: Alec Roelke
-
-output header {{
-/**
- * Base class for compressed operations that work only on registers
- */
-class CompRegOp : public RiscvStaticInst
-{
-  protected:
-/// Constructor
-CompRegOp(const char *mnem, MachInst _machInst, OpClass __opClass)
-: RiscvStaticInst(mnem, _machInst, __opClass)
-{}
-
-std::string
-generateDisassembly(Addr pc, const SymbolTable *symtab) const;
-};
-}};
-
-output decoder {{
-std::string
-CompRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab)  
const

-{
-std::stringstream ss;
-ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " <<
-registerName(_srcRegIdx[0]);
-return ss.str();
-}
-}};
-
 def format CROp(code, *opt_flags) {{
 iop = InstObjParams(name, Name, 'CompRegOp', code, opt_flags)
 header_output = BasicDeclare.subst(iop)
diff --git a/src/arch/riscv/isa/includes.isa  
b/src/arch/riscv/isa/includes.isa

index f4662da..9f3d99f 100644
--- a/src/arch/riscv/isa/includes.isa
+++ b/src/arch/riscv/isa/includes.isa
@@ -43,6 +43,7 @@
 #include 

 #include "arch/riscv/insts/amo.hh"
+#include "arch/riscv/insts/compressed.hh"
 #include "arch/riscv/insts/mem.hh"
 #include "arch/riscv/insts/standard.hh"
 #include "arch/riscv/insts/static_inst.hh"

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
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Gerrit-Change-Id: I61daae8b8c03a9e0f012790a132aa4d34a6ec296
Gerrit-Change-Number: 6026
Gerrit-PatchSet: 1
Gerrit-Owner: Alec Roelke 
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[gem5-dev] Change in public/gem5[master]: arch-riscv: Move static_inst into a directory

[Alec Roelke (Gerrit)]

Alec Roelke has uploaded this change for review. (  
https://gem5-review.googlesource.com/6021



Change subject: arch-riscv: Move static_inst into a directory
..

arch-riscv: Move static_inst into a directory

This patch creates an "insts" directory in src/arch/riscv to store
static portions of instruction definitions that aren't part of the code
generated by the ISA description.  It serves as a starting point for
future patches to simplify the ISA description.

Change-Id: I6700522143f6fa6c9b18a30e1fbdc8f80cdc7afa
---
A src/arch/riscv/insts/SConscript
A src/arch/riscv/insts/static_inst.cc
R src/arch/riscv/insts/static_inst.hh
M src/arch/riscv/isa/includes.isa
4 files changed, 37 insertions(+), 33 deletions(-)



diff --git a/src/arch/riscv/insts/SConscript  
b/src/arch/riscv/insts/SConscript

new file mode 100644
index 000..95e6afd
--- /dev/null
+++ b/src/arch/riscv/insts/SConscript
@@ -0,0 +1,4 @@
+Import('*')
+
+if env['TARGET_ISA'] == 'riscv':
+Source('static_inst.cc')
\ No newline at end of file
diff --git a/src/arch/riscv/insts/static_inst.cc  
b/src/arch/riscv/insts/static_inst.cc

new file mode 100644
index 000..8fc396d
--- /dev/null
+++ b/src/arch/riscv/insts/static_inst.cc
@@ -0,0 +1,19 @@
+#include "arch/riscv/insts/static_inst.hh"
+
+#include "arch/riscv/types.hh"
+#include "cpu/static_inst.hh"
+
+namespace RiscvISA
+{
+
+void
+RiscvMicroInst::advancePC(PCState ) const
+{
+if (flags[IsLastMicroop]) {
+pcState.uEnd();
+} else {
+pcState.uAdvance();
+}
+}
+
+} // namespace RiscvISA
\ No newline at end of file
diff --git a/src/arch/riscv/static_inst.hh  
b/src/arch/riscv/insts/static_inst.hh

similarity index 80%
rename from src/arch/riscv/static_inst.hh
rename to src/arch/riscv/insts/static_inst.hh
index bdcdee7..d360d44 100644
--- a/src/arch/riscv/static_inst.hh
+++ b/src/arch/riscv/insts/static_inst.hh
@@ -33,12 +33,15 @@
 #ifndef __ARCH_RISCV_STATIC_INST_HH__
 #define __ARCH_RISCV_STATIC_INST_HH__

-
-//
-// Base class for Riscv instructions, and some support functions
-//
+#include 

-namespace RiscvISA {
+#include "arch/riscv/types.hh"
+#include "cpu/exec_context.hh"
+#include "cpu/static_inst.hh"
+#include "mem/packet.hh"
+
+namespace RiscvISA
+{

 /**
  * Base class for all RISC-V static instructions.
@@ -46,20 +49,13 @@
 class RiscvStaticInst : public StaticInst
 {
   protected:
-// Constructor
-RiscvStaticInst(const char *mnem, MachInst _machInst,
-OpClass __opClass) : StaticInst(mnem, _machInst, __opClass)
-{}
+using StaticInst::StaticInst;

 virtual std::string
 generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;

   public:
-void
-advancePC(RiscvISA::PCState ) const
-{
-pc.advance();
-}
+void advancePC(PCState ) const { pc.advance(); }
 };

 /**
@@ -78,16 +74,9 @@
 flags[IsMacroop] = true;
 }

-~RiscvMacroInst()
-{
-microops.clear();
-}
+~RiscvMacroInst() { microops.clear(); }

-StaticInstPtr
-fetchMicroop(MicroPC upc) const
-{
-return microops[upc];
-}
+StaticInstPtr fetchMicroop(MicroPC upc) const { return microops[upc]; }

 Fault
 initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const
@@ -123,15 +112,7 @@
 flags[IsMicroop] = true;
 }

-void
-advancePC(RiscvISA::PCState ) const
-{
-if (flags[IsLastMicroop]) {
-pcState.uEnd();
-} else {
-pcState.uAdvance();
-}
-}
+void advancePC(PCState ) const;
 };

 }
diff --git a/src/arch/riscv/isa/includes.isa  
b/src/arch/riscv/isa/includes.isa

index c172d03..48f2b19 100644
--- a/src/arch/riscv/isa/includes.isa
+++ b/src/arch/riscv/isa/includes.isa
@@ -42,7 +42,7 @@
 #include 
 #include 

-#include "arch/riscv/static_inst.hh"
+#include "arch/riscv/insts/static_inst.hh"
 #include "cpu/static_inst.hh"
 #include "mem/packet.hh"
 #include "mem/request.hh"

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I6700522143f6fa6c9b18a30e1fbdc8f80cdc7afa
Gerrit-Change-Number: 6021
Gerrit-PatchSet: 1
Gerrit-Owner: Alec Roelke 
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[gem5-dev] Change in public/gem5[master]: arch-riscv: Move unknown out of ISA description

[Alec Roelke (Gerrit)]

Alec Roelke has uploaded this change for review. (  
https://gem5-review.googlesource.com/6023



Change subject: arch-riscv: Move unknown out of ISA description
..

arch-riscv: Move unknown out of ISA description

This patch removes the Unknown instruction type out of the ISA generated
code and puts it into arch/riscv/insts.  Since there isn't any dynamic
behavior to it, all that's left behind is a template for creating a new
Unknown instruction.

Change-Id: If7c3258a24ecadd3e00ab74586e1740e14f028db
---
M src/arch/riscv/insts/SConscript
M src/arch/riscv/insts/bitfields.hh
A src/arch/riscv/insts/unknown.cc
A src/arch/riscv/insts/unknown.hh
M src/arch/riscv/isa/formats/unknown.isa
M src/arch/riscv/isa/includes.isa
6 files changed, 61 insertions(+), 42 deletions(-)



diff --git a/src/arch/riscv/insts/SConscript  
b/src/arch/riscv/insts/SConscript

index fe90280..3da7ba3 100644
--- a/src/arch/riscv/insts/SConscript
+++ b/src/arch/riscv/insts/SConscript
@@ -2,4 +2,5 @@

 if env['TARGET_ISA'] == 'riscv':
 Source('standard.cc')
-Source('static_inst.cc')
\ No newline at end of file
+Source('static_inst.cc')
+Source('unknown.cc')
\ No newline at end of file
diff --git a/src/arch/riscv/insts/bitfields.hh  
b/src/arch/riscv/insts/bitfields.hh

index 45744e0..d664822 100644
--- a/src/arch/riscv/insts/bitfields.hh
+++ b/src/arch/riscv/insts/bitfields.hh
@@ -5,5 +5,6 @@

 #define CSRIMM  bits(machInst, 19, 15)
 #define FUNCT12 bits(machInst, 31, 20)
+#define OPCODE  bits(machInst, 6, 0)

 #endif // __ARCH_RISCV_BITFIELDS_HH__
\ No newline at end of file
diff --git a/src/arch/riscv/insts/unknown.cc  
b/src/arch/riscv/insts/unknown.cc

new file mode 100644
index 000..aaec865
--- /dev/null
+++ b/src/arch/riscv/insts/unknown.cc
@@ -0,0 +1,17 @@
+#include "arch/riscv/insts/unknown.hh"
+
+#include 
+
+#include "arch/riscv/insts/bitfields.hh"
+#include "cpu/static_inst.hh"
+
+namespace RiscvISA
+{
+
+std::string
+Unknown::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+return csprintf("unknown opcode 0x%02x", OPCODE);
+}
+
+}
\ No newline at end of file
diff --git a/src/arch/riscv/insts/unknown.hh  
b/src/arch/riscv/insts/unknown.hh

new file mode 100644
index 000..0540371
--- /dev/null
+++ b/src/arch/riscv/insts/unknown.hh
@@ -0,0 +1,40 @@
+#ifndef __ARCH_RISCV_UNKNOWN_INST_HH__
+#define __ARCH_RISCV_UNKNOWN_INST_HH__
+
+#include 
+#include 
+
+#include "arch/riscv/faults.hh"
+#include "arch/riscv/insts/static_inst.hh"
+#include "cpu/exec_context.hh"
+#include "cpu/static_inst.hh"
+
+namespace RiscvISA
+{
+
+/**
+ * Static instruction class for unknown (illegal) instructions.
+ * These cause simulator termination if they are executed in a
+ * non-speculative mode.  This is a leaf class.
+ */
+class Unknown : public RiscvStaticInst
+{
+  public:
+/// Constructor
+Unknown(MachInst _machInst)
+: RiscvStaticInst("unknown", _machInst, No_OpClass)
+{
+flags[IsNonSpeculative] = true;
+}
+
+Fault execute(ExecContext *, Trace::InstRecord *) const
+{
+return std::make_shared();
+}
+
+std::string generateDisassembly(Addr pc, const SymbolTable *symtab)  
const;

+};
+
+}
+
+#endif // __ARCH_RISCV_UNKNOWN_INST_HH__
\ No newline at end of file
diff --git a/src/arch/riscv/isa/formats/unknown.isa  
b/src/arch/riscv/isa/formats/unknown.isa

index b6d7649..7c2317f 100644
--- a/src/arch/riscv/isa/formats/unknown.isa
+++ b/src/arch/riscv/isa/formats/unknown.isa
@@ -34,47 +34,6 @@
 //
 // Unknown instructions
 //
-
-output header {{
-/**
- * Static instruction class for unknown (illegal) instructions.
- * These cause simulator termination if they are executed in a
- * non-speculative mode.  This is a leaf class.
- */
-class Unknown : public RiscvStaticInst
-{
-  public:
-/// Constructor
-Unknown(MachInst _machInst)
-: RiscvStaticInst("unknown", _machInst, No_OpClass)
-{
-flags[IsNonSpeculative] = true;
-}
-
-Fault execute(ExecContext *, Trace::InstRecord *) const;
-
-std::string
-generateDisassembly(Addr pc, const SymbolTable *symtab) const;
-};
-}};
-
-output decoder {{
-std::string
-Unknown::generateDisassembly(Addr pc, const SymbolTable *symtab) const
-{
-return csprintf("unknown opcode 0x%02x", OPCODE);
-}
-}};
-
-output exec {{
-Fault
-Unknown::execute(ExecContext *xc, Trace::InstRecord *traceData) const
-{
-Fault fault = std::make_shared();
-return fault;
-}
-}};
-
 def format Unknown() {{
 decode_block = 'return new Unknown(machInst);\n'
 }};
diff --git a/src/arch/riscv/isa/includes.isa  
b/src/arch/riscv/isa/includes.isa

index dfd0f37..cd43996 100644
--- a/src/arch/riscv/isa/includes.isa
+++ b/src/arch/riscv/isa/includes.isa
@@ -44,6 +44,7 @@

 #include "arch/riscv/insts/standard.hh"
 #include 

[gem5-dev] Change in public/gem5[master]: arch-riscv: Remove static parts of AMOs out of ISA

[Alec Roelke (Gerrit)]

Alec Roelke has uploaded this change for review. (  
https://gem5-review.googlesource.com/6025



Change subject: arch-riscv: Remove static parts of AMOs out of ISA
..

arch-riscv: Remove static parts of AMOs out of ISA

This patch removes the static parts of the RISC-V atomic memory
instructions out of the ISA generated code and into arch/riscv/insts. It
also makes the LR and SC instructions subclasses of MemInst from
arch/riscv/insts/mem.hh.

Change-Id: I6591f3d171045c4f1b457eb1264bbb7bd62b3e51
---
M src/arch/riscv/insts/SConscript
A src/arch/riscv/insts/amo.cc
A src/arch/riscv/insts/amo.hh
M src/arch/riscv/isa/formats/amo.isa
M src/arch/riscv/isa/includes.isa
5 files changed, 98 insertions(+), 97 deletions(-)



diff --git a/src/arch/riscv/insts/SConscript  
b/src/arch/riscv/insts/SConscript

index 49b31f0..d058f85 100644
--- a/src/arch/riscv/insts/SConscript
+++ b/src/arch/riscv/insts/SConscript
@@ -1,6 +1,7 @@
 Import('*')

 if env['TARGET_ISA'] == 'riscv':
+Source('amo.cc')
 Source('mem.cc')
 Source('standard.cc')
 Source('static_inst.cc')
diff --git a/src/arch/riscv/insts/amo.cc b/src/arch/riscv/insts/amo.cc
new file mode 100644
index 000..e492281
--- /dev/null
+++ b/src/arch/riscv/insts/amo.cc
@@ -0,0 +1,52 @@
+#include "arch/riscv/insts/amo.hh"
+
+#include 
+#include 
+
+#include "arch/riscv/utility.hh"
+#include "cpu/exec_context.hh"
+#include "cpu/static_inst.hh"
+
+using namespace std;
+
+namespace RiscvISA
+{
+
+string LoadReserved::generateDisassembly(Addr pc,
+const SymbolTable *symtab) const
+{
+stringstream ss;
+ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", ("
+<< registerName(_srcRegIdx[0]) << ')';
+return ss.str();
+}
+
+string StoreCond::generateDisassembly(Addr pc,
+const SymbolTable *symtab) const
+{
+stringstream ss;
+ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", "
+<< registerName(_srcRegIdx[1]) << ", ("
+<< registerName(_srcRegIdx[0]) << ')';
+return ss.str();
+}
+
+string AtomicMemOp::generateDisassembly(Addr pc,
+const SymbolTable *symtab) const
+{
+stringstream ss;
+ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", "
+<< registerName(_srcRegIdx[1]) << ", ("
+<< registerName(_srcRegIdx[0]) << ')';
+return ss.str();
+}
+
+string AtomicMemOpMicro::generateDisassembly(Addr pc,
+const SymbolTable *symtab) const
+{
+stringstream ss;
+ss << csprintf("0x%08x", machInst) << ' ' << mnemonic;
+return ss.str();
+}
+
+}
\ No newline at end of file
diff --git a/src/arch/riscv/insts/amo.hh b/src/arch/riscv/insts/amo.hh
new file mode 100644
index 000..6e81722
--- /dev/null
+++ b/src/arch/riscv/insts/amo.hh
@@ -0,0 +1,44 @@
+#ifndef __ARCH_RISCV_INSTS_AMO_HH__
+#define __ARCH_RISCV_INSTS_AMO_HH__
+
+#include 
+
+#include "arch/riscv/insts/mem.hh"
+#include "arch/riscv/insts/static_inst.hh"
+#include "cpu/static_inst.hh"
+
+namespace RiscvISA
+{
+
+class LoadReserved : public MemInst
+{
+  protected:
+using MemInst::MemInst;
+std::string generateDisassembly(Addr pc, const SymbolTable *symtab)  
const;

+};
+
+class StoreCond : public MemInst
+{
+  protected:
+using MemInst::MemInst;
+std::string generateDisassembly(Addr pc, const SymbolTable *symtab)  
const;

+};
+
+class AtomicMemOp : public RiscvMacroInst
+{
+  protected:
+using RiscvMacroInst::RiscvMacroInst;
+std::string generateDisassembly(Addr pc, const SymbolTable *symtab)  
const;

+};
+
+class AtomicMemOpMicro : public RiscvMicroInst
+{
+  protected:
+Request::Flags memAccessFlags;
+using RiscvMicroInst::RiscvMicroInst;
+std::string generateDisassembly(Addr pc, const SymbolTable *symtab)  
const;

+};
+
+}
+
+#endif // __ARCH_RISCV_INSTS_AMO_HH__
\ No newline at end of file
diff --git a/src/arch/riscv/isa/formats/amo.isa  
b/src/arch/riscv/isa/formats/amo.isa

index 80a5faa..ea4e148 100644
--- a/src/arch/riscv/isa/formats/amo.isa
+++ b/src/arch/riscv/isa/formats/amo.isa
@@ -33,103 +33,6 @@
 //
 // Atomic memory operation instructions
 //
-output header {{
-class LoadReserved : public RiscvStaticInst
-{
-  protected:
-Request::Flags memAccessFlags;
-
-LoadReserved(const char *mnem, ExtMachInst _machInst,
-OpClass __opClass)
-: RiscvStaticInst(mnem, _machInst, __opClass)
-{}
-
-std::string
-generateDisassembly(Addr pc, const SymbolTable *symtab) const;
-};
-
-class StoreCond : public RiscvStaticInst
-{
-  protected:
-Request::Flags memAccessFlags;
-
-StoreCond(const char* mnem, ExtMachInst _machInst, OpClass  
__opClass)

-: RiscvStaticInst(mnem, _machInst, __opClass)
-{}
-
-std::string
-generateDisassembly(Addr pc, const SymbolTable *symtab) const;
-};
-
-class AtomicMemOp : public 

[gem5-dev] Change in public/gem5[master]: arch-riscv: Move standard ops out of ISA

[Alec Roelke (Gerrit)]

Alec Roelke has uploaded this change for review. (  
https://gem5-review.googlesource.com/6022



Change subject: arch-riscv: Move standard ops out of ISA
..

arch-riscv: Move standard ops out of ISA

This patch removes static portions of the standard instruction types
from the generated ISA code and puts them into arch/riscv/insts. Some
dynamicallly-generated content is left behind for each individual
instruction's implementation.

Change-Id: I1bf47c8b8a92a5be74a50909fcc51d8551185a2a
---
M src/arch/riscv/insts/SConscript
A src/arch/riscv/insts/bitfields.hh
A src/arch/riscv/insts/standard.cc
A src/arch/riscv/insts/standard.hh
M src/arch/riscv/isa/formats/standard.isa
M src/arch/riscv/isa/includes.isa
6 files changed, 178 insertions(+), 141 deletions(-)



diff --git a/src/arch/riscv/insts/SConscript  
b/src/arch/riscv/insts/SConscript

index 95e6afd..fe90280 100644
--- a/src/arch/riscv/insts/SConscript
+++ b/src/arch/riscv/insts/SConscript
@@ -1,4 +1,5 @@
 Import('*')

 if env['TARGET_ISA'] == 'riscv':
+Source('standard.cc')
 Source('static_inst.cc')
\ No newline at end of file
diff --git a/src/arch/riscv/insts/bitfields.hh  
b/src/arch/riscv/insts/bitfields.hh

new file mode 100644
index 000..45744e0
--- /dev/null
+++ b/src/arch/riscv/insts/bitfields.hh
@@ -0,0 +1,9 @@
+#ifndef __ARCH_RISCV_BITFIELDS_HH__
+#define __ARCH_RISCV_BITFIELDS_HH__
+
+#include "base/bitfield.hh"
+
+#define CSRIMM  bits(machInst, 19, 15)
+#define FUNCT12 bits(machInst, 31, 20)
+
+#endif // __ARCH_RISCV_BITFIELDS_HH__
\ No newline at end of file
diff --git a/src/arch/riscv/insts/standard.cc  
b/src/arch/riscv/insts/standard.cc

new file mode 100644
index 000..a87fb7a
--- /dev/null
+++ b/src/arch/riscv/insts/standard.cc
@@ -0,0 +1,36 @@
+#include "arch/riscv/insts/standard.hh"
+
+#include 
+#include 
+
+#include "arch/riscv/insts/static_inst.hh"
+#include "arch/riscv/utility.hh"
+#include "cpu/static_inst.hh"
+
+using namespace std;
+
+namespace RiscvISA
+{
+
+string
+RegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+stringstream ss;
+ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " <<
+registerName(_srcRegIdx[0]) << ", " <<
+registerName(_srcRegIdx[1]);
+return ss.str();
+}
+
+string
+CSROp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+stringstream ss;
+ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", ";
+if (_numSrcRegs > 0)
+ss << registerName(_srcRegIdx[0]) << ", ";
+ss << MiscRegNames.at(csr);
+return ss.str();
+}
+
+}
\ No newline at end of file
diff --git a/src/arch/riscv/insts/standard.hh  
b/src/arch/riscv/insts/standard.hh

new file mode 100644
index 000..e8fc63f
--- /dev/null
+++ b/src/arch/riscv/insts/standard.hh
@@ -0,0 +1,131 @@
+#ifndef __ARCH_RISCV_STANDARD_INST_HH__
+#define __ARCH_RISCV_STANDARD_INST_HH__
+
+#include 
+
+#include "arch/riscv/insts/bitfields.hh"
+#include "arch/riscv/insts/static_inst.hh"
+#include "cpu/exec_context.hh"
+#include "cpu/static_inst.hh"
+
+namespace RiscvISA
+{
+
+/**
+ * Base class for operations that work only on registers
+ */
+class RegOp : public RiscvStaticInst
+{
+  protected:
+/// Constructor
+RegOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+: RiscvStaticInst(mnem, _machInst, __opClass)
+{}
+
+std::string
+generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
+/**
+ * Base class for operations with signed immediates
+ */
+class ImmOp : public RiscvStaticInst
+{
+  protected:
+int64_t imm;
+
+/// Constructor
+ImmOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+: RiscvStaticInst(mnem, _machInst, __opClass), imm(0)
+{}
+
+virtual std::string
+generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
+};
+
+/**
+ * Base class for operations with unsigned immediates
+ */
+class UImmOp : public RiscvStaticInst
+{
+  protected:
+uint64_t imm;
+
+/// Constructor
+UImmOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+: RiscvStaticInst(mnem, _machInst, __opClass), imm(0)
+{}
+
+virtual std::string
+generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
+};
+
+/**
+ * Base class for operations with branching
+ */
+class BranchOp : public ImmOp
+{
+  protected:
+/// Constructor
+BranchOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+: ImmOp(mnem, _machInst, __opClass)
+{}
+
+using StaticInst::branchTarget;
+
+virtual RiscvISA::PCState
+branchTarget(ThreadContext *tc) const
+{
+return StaticInst::branchTarget(tc);
+}
+
+virtual RiscvISA::PCState
+branchTarget(const RiscvISA::PCState ) const
+{
+return StaticInst::branchTarget(branchPC);
+}
+
+virtual std::string
+generateDisassembly(Addr pc, const SymbolTable *symtab) const = 

[gem5-dev] Change in public/gem5[master]: arch-riscv: Move parts of mem insts out of ISA

[Alec Roelke (Gerrit)]

Alec Roelke has uploaded this change for review. (  
https://gem5-review.googlesource.com/6024



Change subject: arch-riscv: Move parts of mem insts out of ISA
..

arch-riscv: Move parts of mem insts out of ISA

This patch moves static portions of the memory instructions out of the
ISA generated code and puts them into arch/riscv/insts.  It also
simplifies the definitions of load and store instructions by giving
them a common base class.

Change-Id: Ic6930cbfc6bb02e4b3477521e57b093eac0c8803
---
M src/arch/riscv/insts/SConscript
M src/arch/riscv/insts/bitfields.hh
A src/arch/riscv/insts/mem.cc
A src/arch/riscv/insts/mem.hh
M src/arch/riscv/isa/decoder.isa
M src/arch/riscv/isa/formats/mem.isa
M src/arch/riscv/isa/includes.isa
7 files changed, 112 insertions(+), 96 deletions(-)



diff --git a/src/arch/riscv/insts/SConscript  
b/src/arch/riscv/insts/SConscript

index 3da7ba3..49b31f0 100644
--- a/src/arch/riscv/insts/SConscript
+++ b/src/arch/riscv/insts/SConscript
@@ -1,6 +1,7 @@
 Import('*')

 if env['TARGET_ISA'] == 'riscv':
+Source('mem.cc')
 Source('standard.cc')
 Source('static_inst.cc')
 Source('unknown.cc')
\ No newline at end of file
diff --git a/src/arch/riscv/insts/bitfields.hh  
b/src/arch/riscv/insts/bitfields.hh

index d664822..eac070e 100644
--- a/src/arch/riscv/insts/bitfields.hh
+++ b/src/arch/riscv/insts/bitfields.hh
@@ -5,6 +5,9 @@

 #define CSRIMM  bits(machInst, 19, 15)
 #define FUNCT12 bits(machInst, 31, 20)
+#define IMM5bits(machInst, 11, 7)
+#define IMM7bits(machInst, 31, 25)
+#define IMMSIGN bits(machInst, 31)
 #define OPCODE  bits(machInst, 6, 0)

 #endif // __ARCH_RISCV_BITFIELDS_HH__
\ No newline at end of file
diff --git a/src/arch/riscv/insts/mem.cc b/src/arch/riscv/insts/mem.cc
new file mode 100644
index 000..a372d44
--- /dev/null
+++ b/src/arch/riscv/insts/mem.cc
@@ -0,0 +1,34 @@
+#include "arch/riscv/insts/mem.hh"
+
+#include 
+#include 
+
+#include "arch/riscv/insts/bitfields.hh"
+#include "arch/riscv/insts/static_inst.hh"
+#include "arch/riscv/utility.hh"
+#include "cpu/static_inst.hh"
+
+using namespace std;
+
+namespace RiscvISA
+{
+
+string
+Load::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+stringstream ss;
+ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " <<
+offset << '(' << registerName(_srcRegIdx[0]) << ')';
+return ss.str();
+}
+
+string
+Store::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+stringstream ss;
+ss << mnemonic << ' ' << registerName(_srcRegIdx[1]) << ", " <<
+offset << '(' << registerName(_srcRegIdx[0]) << ')';
+return ss.str();
+}
+
+}
diff --git a/src/arch/riscv/insts/mem.hh b/src/arch/riscv/insts/mem.hh
new file mode 100644
index 000..c7da897
--- /dev/null
+++ b/src/arch/riscv/insts/mem.hh
@@ -0,0 +1,43 @@
+#ifndef __ARCH_RISCV_INST_MEM_HH__
+#define __ARCH_RISCV_INST_MEM_HH__
+
+#include 
+
+#include "arch/riscv/insts/static_inst.hh"
+#include "cpu/exec_context.hh"
+#include "cpu/static_inst.hh"
+
+namespace RiscvISA
+{
+
+class MemInst : public RiscvStaticInst
+{
+  protected:
+int64_t offset;
+Request::Flags memAccessFlags;
+
+MemInst(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
+: RiscvStaticInst(mnem, _machInst, __opClass), offset(0)
+{}
+
+virtual std::string
+generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
+};
+
+class Load : public MemInst
+{
+  protected:
+using MemInst::MemInst;
+std::string generateDisassembly(Addr pc, const SymbolTable *symtab)  
const;

+};
+
+class Store : public MemInst
+{
+  protected:
+using MemInst::MemInst;
+std::string generateDisassembly(Addr pc, const SymbolTable *symtab)  
const;

+};
+
+}
+
+#endif // __ARCH_RISCV_INST_MEM_HH__
diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index a6f8816..2cfdeea 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -48,52 +48,52 @@
 }});
 format CompressedLoad {
 0x1: c_fld({{
-ldisp = CIMM3 << 3 | CIMM2 << 6;
+offset = CIMM3 << 3 | CIMM2 << 6;
 }}, {{
 Fp2_bits = Mem;
 }}, {{
-EA = Rp1 + ldisp;
+EA = Rp1 + offset;
 }});
 0x2: c_lw({{
-ldisp = CIMM2<1:1> << 2 |
+offset = CIMM2<1:1> << 2 |
 CIMM3 << 3 |
 CIMM2<0:0> << 6;
 }}, {{
 Rp2_sd = Mem_sw;
 }}, {{
-EA = Rp1 + ldisp;
+EA = Rp1 + offset;
 }});
 0x3: c_ld({{
-ldisp = CIMM3 << 3 | CIMM2 << 6;
+offset = CIMM3 << 3 | CIMM2 << 6;
 }}, {{
 Rp2_sd = Mem_sd;
 }}, {{
-EA = Rp1 + ldisp;
+ 

[gem5-dev] Change in public/gem5[master]: arch-riscv: Add missing system calls

[Alec Roelke (Gerrit)]

Alec Roelke has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/5322 )


Change subject: arch-riscv: Add missing system calls
..

arch-riscv: Add missing system calls

This patch adds all system calls present in riscv-gnu-toolchain at
commit hash 65cb174. Many of them do not have implementations in gem5, so
they are just placeholders.

[Remove the variadic macro and replace it with a function that has
default arguments because variadic macros may not be portable across
compilers]
[Remove spaces around default arguments of createSyscall for better
style]
[Switch from using a loose function to using SyscallDesc's new
constructor]

Change-Id: Iff97c689109121b39df423c72d0e79c6366e31b9
Reviewed-on: https://gem5-review.googlesource.com/5322
Reviewed-by: Gabe Black 
Maintainer: Alec Roelke 
---
M src/arch/riscv/linux/linux.hh
M src/arch/riscv/linux/process.cc
2 files changed, 356 insertions(+), 47 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved
  Alec Roelke: Looks good to me, approved



diff --git a/src/arch/riscv/linux/linux.hh b/src/arch/riscv/linux/linux.hh
index 0c76fa6..cfc1d4f 100644
--- a/src/arch/riscv/linux/linux.hh
+++ b/src/arch/riscv/linux/linux.hh
@@ -152,6 +152,41 @@
 uint64_t st_ctime_nsec;
 int32_t ___glibc_reserved[2];
 } tgt_stat64;
+
+typedef struct {
+int32_t val[2];
+} tgt_fsid_t;
+
+typedef struct {
+uint64_t f_type;
+uint64_t f_bsize;
+uint64_t f_blocks;
+uint64_t f_bfree;
+uint64_t f_bavail;
+uint64_t f_files;
+uint64_t f_ffree;
+tgt_fsid_t f_fsid;
+uint64_t f_namelen;
+uint64_t f_frsize;
+uint64_t f_flags;
+uint64_t f_spare[4];
+} tgt_statfs;
+
+typedef struct {
+int64_t uptime;
+uint64_t loads[3];
+uint64_t totalram;
+uint64_t freeram;
+uint64_t sharedram;
+uint64_t bufferram;
+uint64_t totalswap;
+uint64_t freeswap;
+uint16_t procs;
+uint16_t pad;
+uint64_t totalhigh;
+uint64_t freehigh;
+uint32_t mem_unit;
+} tgt_sysinfo;
 };

 #endif
diff --git a/src/arch/riscv/linux/process.cc  
b/src/arch/riscv/linux/process.cc

index 24ea056..1749aa8 100644
--- a/src/arch/riscv/linux/process.cc
+++ b/src/arch/riscv/linux/process.cc
@@ -70,60 +70,334 @@
 }

 std::map RiscvLinuxProcess::syscallDescs = {
-{17, SyscallDesc("getcwd", getcwdFunc)},
-{23, SyscallDesc("dup", dupFunc)},
-{25, SyscallDesc("fcntl", fcntl64Func)},
-{29, SyscallDesc("ioctl", ioctlFunc)},
-{34, SyscallDesc("mkdirat", unimplementedFunc)},
-{35, SyscallDesc("unlinkat", unlinkatFunc)},
-{37, SyscallDesc("linkat", unimplementedFunc)},
-{38, SyscallDesc("renameat", renameatFunc)},
-{46, SyscallDesc("ftruncate", ftruncate64Func)},
-{48, SyscallDesc("faccessat", faccessatFunc)},
-{49, SyscallDesc("chdir", unimplementedFunc)},
-{56, SyscallDesc("openat", openatFunc)},
-{57, SyscallDesc("close", closeFunc)},
-{61, SyscallDesc("getdents", unimplementedFunc)},
-{62, SyscallDesc("lseek", lseekFunc)},
-{63, SyscallDesc("read", readFunc)},
-{64, SyscallDesc("write", writeFunc)},
-{66, SyscallDesc("writev", writevFunc)},
-{67, SyscallDesc("pread", unimplementedFunc)},
-{68, SyscallDesc("pwrite", pwrite64Func)},
-{78, SyscallDesc("readlinkat", readlinkatFunc)},
-{79, SyscallDesc("fstatat", fstatat64Func)},
-{80, SyscallDesc("fstat", fstat64Func)},
-{93, SyscallDesc("exit", exitFunc)},
-{94, SyscallDesc("exit_group", exitGroupFunc)},
-{113, SyscallDesc("clock_gettime", clock_gettimeFunc)},
-{129, SyscallDesc("kill", unimplementedFunc)},
-{134, SyscallDesc("rt_sigaction", ignoreFunc, SyscallDesc::WarnOnce)},
-{135, SyscallDesc("rt_sigprocmask", ignoreFunc,  
SyscallDesc::WarnOnce)},

-{153, SyscallDesc("times", timesFunc)},
-{160, SyscallDesc("uname", unameFunc)},
-{163, SyscallDesc("getrlimit", getrlimitFunc)},
-{164, SyscallDesc("setrlimit", ignoreFunc)},
-{165, SyscallDesc("getrusage", getrusageFunc)},
-{169, SyscallDesc("gettimeofday", gettimeofdayFunc)},
-{172, SyscallDesc("getpid", getpidFunc)},
-{174, SyscallDesc("getuid", getuidFunc)},
-{175, SyscallDesc("geteuid", geteuidFunc)},
-{176, SyscallDesc("getgid", getgidFunc)},
-{177, SyscallDesc("getegid", getegidFunc)},
-{214, SyscallDesc("brk", brkFunc)},
-{215, SyscallDesc("munmap", munmapFunc)},
-{216, SyscallDesc("mremap", mremapFunc)},
-{222, SyscallDesc("mmap", mmapFunc)},
-{226, SyscallDesc("mprotect", ignoreFunc)},
+{0,SyscallDesc("io_setup")},
+{1,SyscallDesc("io_destroy")},
+{2,SyscallDesc("io_submit")},
+{3,SyscallDesc("io_cancel")},
+{4,

[gem5-dev] Change in public/gem5[master]: sim-se: Add default to SyscallDesc constructor

[Alec Roelke (Gerrit)]

Alec Roelke has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/5501 )


Change subject: sim-se: Add default to SyscallDesc constructor
..

sim-se: Add default to SyscallDesc constructor

This patch adds a default value of unimplementedFunc to SyscallDesc's
constructor's second argument, which makes adding system call
placeholders to SE mode cleaner.

Change-Id: I3e7efb3a887cc52d16d2095d3dd2e2a96fb882fb
Reviewed-on: https://gem5-review.googlesource.com/5501
Reviewed-by: Gabe Black 
Maintainer: Brandon Potter 
---
M src/sim/syscall_desc.hh
1 file changed, 6 insertions(+), 1 deletion(-)

Approvals:
  Gabe Black: Looks good to me, approved
  Brandon Potter: Looks good to me, approved



diff --git a/src/sim/syscall_desc.hh b/src/sim/syscall_desc.hh
index d72803e..451db08 100644
--- a/src/sim/syscall_desc.hh
+++ b/src/sim/syscall_desc.hh
@@ -51,9 +51,13 @@
 #include "base/types.hh"

 class Process;
+class SyscallDesc;
 class SyscallReturn;
 class ThreadContext;

+SyscallReturn unimplementedFunc(SyscallDesc *desc, int num,
+Process *p, ThreadContext *tc);
+
 /**
  * This class provides the wrapper interface for the system call
  * implementations which are defined in the sim/syscall_emul files and
@@ -66,7 +70,8 @@
 typedef SyscallReturn (*SyscallExecutor)(SyscallDesc*, int num,
  Process*, ThreadContext*);

-SyscallDesc(const char *name, SyscallExecutor sys_exec, int flags = 0)
+SyscallDesc(const char *name,
+SyscallExecutor sys_exec=unimplementedFunc, int flags=0)
 : _name(name), executor(sys_exec), _flags(flags), _warned(false)
 {
 }

--
To view, visit https://gem5-review.googlesource.com/5501
To unsubscribe, or for help writing mail filters, visit  
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I3e7efb3a887cc52d16d2095d3dd2e2a96fb882fb
Gerrit-Change-Number: 5501
Gerrit-PatchSet: 2
Gerrit-Owner: Alec Roelke 
Gerrit-Reviewer: Alec Roelke 
Gerrit-Reviewer: Brandon Potter 
Gerrit-Reviewer: Gabe Black 
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Re: [gem5-dev] gem5.opt => opt/gem5?

[Gabe Black]

I thought about this a bit more, and one thing that would be worse under
this scheme would be that generated source files would be generated
multiple times when building multiple builds since they'd no longer be in a
common location. I think it's pretty rare for people to build multiple
builds, and if they do this is probably a fairly small overhead, but it's
worth considering.

I don't think scons is that bad, although it can be very mysterious and
hard to understand without studying it a lot (which I've now been forced to
do). Replacing it with a whole different scheme would be a huge bit of work
(as I'm sure you noticed), and I'm not sure it'd end up being *that* much
better afterwards, but who knows for sure really.

I think for now I'll leave this on the back burner since I'm not certain I
need to do it to do some other things I'm thinking of, but I might find a
good reason to bump it up the list at some point. I still like the idea.

Gabe

On Tue, Nov 21, 2017 at 8:09 AM, Jason Lowe-Power 
wrote:

> Hey Gabe,
>
> I don't have any strong feelings on this, just a couple of points.
>
> 1) I think we should support "backwards compatibility" if we do this by
> having symlinks from the old names to the new names. This way we don't
> break all of the scripts people have been using.
> 2) How much effort is this and would it be better worth your time to
> replace SCons with a better build system (e.g., cmake or bazel)?
> Additionally, a lot of our build headaches stem from the high level of
> coupling between all of the source directories which makes it impossible to
> build a subset of gem5 into a library. Would it make sense to tackle this
> instead of shoehorning it into SCons?
>
> I don't mean to discourage you from taking our current system and making
> it incrementally better!
>
> Cheers,
> Jason
>
> On Tue, Nov 21, 2017 at 6:01 AM Andreas Sandberg 
> wrote:
>
>> Hi Gabe,
>>
>> I can definitely see the reasoning behind this. I think revisiting this
>> is a good idea. However, I'm a bit reluctant since it affects a lot of
>> existing build scripts and test infrastructure.
>>
>> Another benefit that you didn't mention is that this avoid some annoying
>> "issues" when the build system runs tests. We currently run tests using
>> the build/ARM/tests/opt/** targets. This would all become consistent
>> with the rest of the build system.
>>
>> Another change we should consider making while we are doing this is to
>> swap architecture and optimisation levels. The opt Arm target would then
>> become build/opt/ARM/gem5.opt. That would be a lot nicer for code (e.g.,
>> libraries) that we share between different targets. Ideally, we should
>> only rebuild the src/cpu and src/arch/ directories when switching
>> targets, but that's a more ambitious goal.
>>
>> Cheers,
>> Andreas
>>
>>
>> On 21/11/2017 05:28, Gabe Black wrote:
>> > Hi folks. I've been digging around in the scons files, and I was
>> thinking
>> > about the possibility of treating opt, fast, debug, etc., as actual
>> > variants from the scons perspective instead of having them all live in
>> the
>> > same directory but with different extensions. I think the biggest
>> > difference this might make is that, for instance, the opt version of the
>> > gem5 X86 binary would be build/X86/opt/gem5 and not build/X86/gem5.opt.
>> >
>> > There wouldn't be any amazing direct benefit from doing things that way
>> > that I can see at the moment, but it would make our build structure fit
>> a
>> > little more naturally into the way scons wants to do things. It might
>> also
>> > make it more feasible to use real scons builders for things like Source,
>> > etc., instead of wrapper classes. Another benefit would be if you
>> wanted to
>> > compile all the files in a particular part of the source tree (like the
>> > unit tests, although those shouldn't be lumped together anyway), you
>> could
>> > just give scons the path and it wouldn't build all possible versions of
>> the
>> > sources in that directory, just the one in the variant you gave it.
>> Using
>> > the unit tests as an example, you could run 'scons
>> build/ARM/opt/unittest'
>> > and get the opt versions of all the unit tests.
>> >
>> > Any objections?
>> >
>> > Gabe
>> > ___
>> > gem5-dev mailing list
>> > gem5-dev@gem5.org
>> > http://m5sim.org/mailman/listinfo/gem5-dev
>>
>> IMPORTANT NOTICE: The contents of this email and any attachments are
>> confidential and may also be privileged. If you are not the intended
>> recipient, please notify the sender immediately and do not disclose the
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>> information in any medium. Thank you.
>> ___
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>
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[gem5-dev] Change in public/gem5[master]: tests: Fix the stats unit test.

[Gabe Black (Gerrit)]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/6001



Change subject: tests: Fix the stats unit test.
..

tests: Fix the stats unit test.

This has been broken since February. The interface for opening
initializing where the stats output should go was changed, but the
test wasn't updated.

Change-Id: I54bd8be15bf870352d5fcfad95ded28d87c7cc5a
---
M src/unittest/stattestmain.py
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/unittest/stattestmain.py b/src/unittest/stattestmain.py
index 70fef59..60b041c 100644
--- a/src/unittest/stattestmain.py
+++ b/src/unittest/stattestmain.py
@@ -6,7 +6,7 @@

 # Initialize the global statistics
 m5.stats.initSimStats()
-m5.stats.initText("cout")
+m5.stats.addStatVisitor("cout")

 # We're done registering statistics.  Enable the stats package now.
 m5.stats.enable()

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Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I54bd8be15bf870352d5fcfad95ded28d87c7cc5a
Gerrit-Change-Number: 6001
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[gem5-dev] Change in public/gem5[master]: sparc: Move integer StaticInst base classes out of the ISA desc.

[Gabe Black (Gerrit)]

Gabe Black has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/5483 )


Change subject: sparc: Move integer StaticInst base classes out of the ISA  
desc.

..

sparc: Move integer StaticInst base classes out of the ISA desc.

Change-Id: I24008c1e2a94ad8dc4cc13739214928eb846a496
Reviewed-on: https://gem5-review.googlesource.com/5483
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
---
M src/arch/sparc/insts/SConscript
A src/arch/sparc/insts/integer.cc
A src/arch/sparc/insts/integer.hh
M src/arch/sparc/isa/formats/integerop.isa
M src/arch/sparc/isa/includes.isa
5 files changed, 261 insertions(+), 194 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/sparc/insts/SConscript  
b/src/arch/sparc/insts/SConscript

index f608554..3a5ac2e 100644
--- a/src/arch/sparc/insts/SConscript
+++ b/src/arch/sparc/insts/SConscript
@@ -34,6 +34,7 @@
 if env['TARGET_ISA'] == 'sparc':
 Source('blockmem.cc')
 Source('branch.cc')
+Source('integer.cc')
 Source('mem.cc')
 Source('micro.cc')
 Source('priv.cc')
diff --git a/src/arch/sparc/insts/integer.cc  
b/src/arch/sparc/insts/integer.cc

new file mode 100644
index 000..9639649
--- /dev/null
+++ b/src/arch/sparc/insts/integer.cc
@@ -0,0 +1,126 @@
+/*
+ * Copyright (c) 2006-2007 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ *  Gabe Black
+ *  Steve Reinhardt
+ */
+
+#include "arch/sparc/insts/integer.hh"
+
+namespace SparcISA
+{
+
+
+//
+// Integer operate instructions
+//
+
+bool
+IntOp::printPseudoOps(std::ostream , Addr pc,
+  const SymbolTable *symbab) const
+{
+if (!std::strcmp(mnemonic, "or") && _srcRegIdx[0].index() == 0) {
+printMnemonic(os, "mov");
+printSrcReg(os, 1);
+ccprintf(os, ", ");
+printDestReg(os, 0);
+return true;
+}
+return false;
+}
+
+bool
+IntOpImm::printPseudoOps(std::ostream , Addr pc,
+ const SymbolTable *symbab) const
+{
+if (!std::strcmp(mnemonic, "or")) {
+if (_numSrcRegs > 0 && _srcRegIdx[0].index() == 0) {
+if (imm == 0) {
+printMnemonic(os, "clr");
+} else {
+printMnemonic(os, "mov");
+ccprintf(os, " %#x, ", imm);
+}
+printDestReg(os, 0);
+return true;
+} else if (imm == 0) {
+printMnemonic(os, "mov");
+printSrcReg(os, 0);
+ccprintf(os, ", ");
+printDestReg(os, 0);
+return true;
+}
+}
+return false;
+}
+
+std::string
+IntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+std::stringstream response;
+
+if (printPseudoOps(response, pc, symtab))
+return response.str();
+printMnemonic(response, mnemonic);
+printRegArray(response, _srcRegIdx, _numSrcRegs);
+if (_numDestRegs && _numSrcRegs)
+response << ", ";
+printDestReg(response, 0);
+return response.str();
+}
+
+std::string
+IntOpImm::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+std::stringstream response;
+
+if (printPseudoOps(response, pc, symtab))
+return 

[gem5-dev] Change in public/gem5[master]: sparc: Move the mem base classes out of the ISA description.

[Gabe Black (Gerrit)]

Gabe Black has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/5482 )


Change subject: sparc: Move the mem base classes out of the ISA description.
..

sparc: Move the mem base classes out of the ISA description.

Change-Id: Ifbeee464e2d7f872e192f065ad3494f52d274596
Reviewed-on: https://gem5-review.googlesource.com/5482
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
---
M src/arch/sparc/insts/SConscript
A src/arch/sparc/insts/blockmem.cc
A src/arch/sparc/insts/blockmem.hh
A src/arch/sparc/insts/mem.cc
A src/arch/sparc/insts/mem.hh
M src/arch/sparc/isa/formats/mem/blockmem.isa
M src/arch/sparc/isa/formats/mem/util.isa
M src/arch/sparc/isa/includes.isa
8 files changed, 356 insertions(+), 213 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/sparc/insts/SConscript  
b/src/arch/sparc/insts/SConscript

index 8848566..f608554 100644
--- a/src/arch/sparc/insts/SConscript
+++ b/src/arch/sparc/insts/SConscript
@@ -32,7 +32,9 @@
 Import('*')

 if env['TARGET_ISA'] == 'sparc':
+Source('blockmem.cc')
 Source('branch.cc')
+Source('mem.cc')
 Source('micro.cc')
 Source('priv.cc')
 Source('static_inst.cc')
diff --git a/src/arch/sparc/insts/blockmem.cc  
b/src/arch/sparc/insts/blockmem.cc

new file mode 100644
index 000..e8e9301
--- /dev/null
+++ b/src/arch/sparc/insts/blockmem.cc
@@ -0,0 +1,88 @@
+/*
+ * Copyright (c) 2006-2007 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ *  Gabe Black
+ */
+
+#include "arch/sparc/insts/blockmem.hh"
+
+namespace SparcISA
+{
+
+std::string
+BlockMemMicro::generateDisassembly(Addr pc, const SymbolTable *symtab)  
const

+{
+std::stringstream response;
+bool load = flags[IsLoad];
+bool save = flags[IsStore];
+
+printMnemonic(response, mnemonic);
+if (save) {
+printReg(response, _srcRegIdx[0]);
+ccprintf(response, ", ");
+}
+ccprintf(response, "[ ");
+printReg(response, _srcRegIdx[!save ? 0 : 1]);
+ccprintf(response, " + ");
+printReg(response, _srcRegIdx[!save ? 1 : 2]);
+ccprintf(response, " ]");
+if (load) {
+ccprintf(response, ", ");
+printReg(response, _destRegIdx[0]);
+}
+
+return response.str();
+}
+
+std::string
+BlockMemImmMicro::generateDisassembly(Addr pc, const SymbolTable *symtab)  
const

+{
+std::stringstream response;
+bool load = flags[IsLoad];
+bool save = flags[IsStore];
+
+printMnemonic(response, mnemonic);
+if (save) {
+printReg(response, _srcRegIdx[1]);
+ccprintf(response, ", ");
+}
+ccprintf(response, "[ ");
+printReg(response, _srcRegIdx[0]);
+if (imm >= 0)
+ccprintf(response, " + 0x%x ]", imm);
+else
+ccprintf(response, " + -0x%x ]", -imm);
+if (load) {
+ccprintf(response, ", ");
+printReg(response, _destRegIdx[0]);
+}
+
+return response.str();
+}
+
+}
diff --git a/src/arch/sparc/insts/blockmem.hh  
b/src/arch/sparc/insts/blockmem.hh

new file mode 100644
index 000..5216b2d
--- /dev/null
+++ b/src/arch/sparc/insts/blockmem.hh
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2006-2007 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with 

[gem5-dev] Change in public/gem5[master]: sparc: Move the microop/macroop base classes out of the ISA desc.

[Gabe Black (Gerrit)]

Gabe Black has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/5481 )


Change subject: sparc: Move the microop/macroop base classes out of the ISA  
desc.

..

sparc: Move the microop/macroop base classes out of the ISA desc.

These were just raw C++ classes.

Change-Id: Id2101400d885c6938efb6b94f2949722cfbb94ae
Reviewed-on: https://gem5-review.googlesource.com/5481
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
---
M src/arch/sparc/insts/SConscript
A src/arch/sparc/insts/micro.cc
A src/arch/sparc/insts/micro.hh
M src/arch/sparc/isa/formats/formats.isa
D src/arch/sparc/isa/formats/micro.isa
M src/arch/sparc/isa/includes.isa
6 files changed, 172 insertions(+), 133 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/sparc/insts/SConscript  
b/src/arch/sparc/insts/SConscript

index 24b7485..8848566 100644
--- a/src/arch/sparc/insts/SConscript
+++ b/src/arch/sparc/insts/SConscript
@@ -33,6 +33,7 @@

 if env['TARGET_ISA'] == 'sparc':
 Source('branch.cc')
+Source('micro.cc')
 Source('priv.cc')
 Source('static_inst.cc')
 Source('trap.cc')
diff --git a/src/arch/sparc/insts/micro.cc b/src/arch/sparc/insts/micro.cc
new file mode 100644
index 000..6415324
--- /dev/null
+++ b/src/arch/sparc/insts/micro.cc
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2006-2007 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "arch/sparc/insts/micro.hh"
+
+namespace SparcISA
+{
+
+std::string
+SparcMacroInst::generateDisassembly(Addr pc, const SymbolTable *symtab)  
const

+{
+std::stringstream response;
+printMnemonic(response, mnemonic);
+return response.str();
+}
+
+}
diff --git a/src/arch/sparc/insts/micro.hh b/src/arch/sparc/insts/micro.hh
new file mode 100644
index 000..d8c3adc
--- /dev/null
+++ b/src/arch/sparc/insts/micro.hh
@@ -0,0 +1,126 @@
+/*
+ * Copyright (c) 2006-2007 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN 

[gem5-dev] Change in public/gem5[master]: sparc: Return debug faults from unimplemented instructions.

[Gabe Black (Gerrit)]

Gabe Black has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/5465 )


Change subject: sparc: Return debug faults from unimplemented instructions.
..

sparc: Return debug faults from unimplemented instructions.

These had been marked as non-speculative so that their execute
functions would only be called if the instruction should really be
executed. Instead, we can return faults which will cause the same
behavior when the instruction is committed and let the instruction
execute as normal.

Change-Id: I39fa5073e93399424144724b99bdc12070e42286
Reviewed-on: https://gem5-review.googlesource.com/5465
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
---
M src/arch/sparc/insts/unimp.hh
1 file changed, 10 insertions(+), 13 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/sparc/insts/unimp.hh b/src/arch/sparc/insts/unimp.hh
index c0d9785..a63443a 100644
--- a/src/arch/sparc/insts/unimp.hh
+++ b/src/arch/sparc/insts/unimp.hh
@@ -31,6 +31,9 @@
 #ifndef __ARCH_SPARC_INSTS_UNIMP_HH__
 #define __ARCH_SPARC_INSTS_UNIMP_HH__

+#include 
+
+#include "arch/generic/debugfaults.hh"
 #include "arch/sparc/insts/static_inst.hh"
 #include "base/cprintf.hh"

@@ -55,17 +58,14 @@
 /// Constructor
 FailUnimplemented(const char *_mnemonic, ExtMachInst _machInst) :
 SparcStaticInst(_mnemonic, _machInst, No_OpClass)
-{
-// don't call execute() (which panics) if we're on a
-// speculative path
-flags[IsNonSpeculative] = true;
-}
+{}

 Fault
 execute(ExecContext *xc, Trace::InstRecord *traceData) const override
 {
-panic("attempt to execute unimplemented instruction '%s' "
-  "(inst 0x%08x)", mnemonic, machInst);
+return std::make_shared(
+"attempt to execute unimplemented instruction '%s'  
(inst %#08x)",

+mnemonic, machInst);
 }

 std::string
@@ -94,17 +94,14 @@
 /// Constructor
 WarnUnimplemented(const char *_mnemonic, ExtMachInst _machInst) :
 SparcStaticInst(_mnemonic, _machInst, No_OpClass),  
warned(false)

-{
-// don't call execute() (which panics) if we're on a
-// speculative path
-flags[IsNonSpeculative] = true;
-}
+{}

 Fault
 execute(ExecContext *xc, Trace::InstRecord *traceData) const override
 {
 if (!warned) {
-warn("instruction '%s' unimplemented\n", mnemonic);
+return std::make_shared(
+"instruction '%s' unimplemented\n", mnemonic);
 warned = true;
 }
 return NoFault;

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I39fa5073e93399424144724b99bdc12070e42286
Gerrit-Change-Number: 5465
Gerrit-PatchSet: 5
Gerrit-Owner: Gabe Black 
Gerrit-Assignee: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-CC: Andreas Sandberg 
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[gem5-dev] Change in public/gem5[master]: sparc: Pull the unimplemented formats out of the ISA description.

[Gabe Black (Gerrit)]

Gabe Black has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/5464 )


Change subject: sparc: Pull the unimplemented formats out of the ISA  
description.

..

sparc: Pull the unimplemented formats out of the ISA description.

These are simple classes which don't need to be in the ISA description.

Change-Id: Ia0bb45f50c4da2536855efcb3c17c7780b431332
Reviewed-on: https://gem5-review.googlesource.com/5464
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
---
A src/arch/sparc/insts/unimp.hh
M src/arch/sparc/isa/formats/unimp.isa
M src/arch/sparc/isa/includes.isa
3 files changed, 123 insertions(+), 98 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/sparc/insts/unimp.hh b/src/arch/sparc/insts/unimp.hh
new file mode 100644
index 000..c0d9785
--- /dev/null
+++ b/src/arch/sparc/insts/unimp.hh
@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Steve Reinhardt
+ */
+
+#ifndef __ARCH_SPARC_INSTS_UNIMP_HH__
+#define __ARCH_SPARC_INSTS_UNIMP_HH__
+
+#include "arch/sparc/insts/static_inst.hh"
+#include "base/cprintf.hh"
+
+namespace SparcISA
+{
+
+
+//
+// Unimplemented instructions
+//
+
+/**
+ * Static instruction class for unimplemented instructions that
+ * cause simulator termination.  Note that these are recognized
+ * (legal) instructions that the simulator does not support; the
+ * 'Unknown' class is used for unrecognized/illegal instructions.
+ * This is a leaf class.
+ */
+class FailUnimplemented : public SparcStaticInst
+{
+  public:
+/// Constructor
+FailUnimplemented(const char *_mnemonic, ExtMachInst _machInst) :
+SparcStaticInst(_mnemonic, _machInst, No_OpClass)
+{
+// don't call execute() (which panics) if we're on a
+// speculative path
+flags[IsNonSpeculative] = true;
+}
+
+Fault
+execute(ExecContext *xc, Trace::InstRecord *traceData) const override
+{
+panic("attempt to execute unimplemented instruction '%s' "
+  "(inst 0x%08x)", mnemonic, machInst);
+}
+
+std::string
+generateDisassembly(Addr pc, const SymbolTable *symtab) const override
+{
+return csprintf("%-10s (unimplemented)", mnemonic);
+}
+};
+
+/**
+ * Base class for unimplemented instructions that cause a warning
+ * to be printed (but do not terminate simulation).  This
+ * implementation is a little screwy in that it will print a
+ * warning for each instance of a particular unimplemented machine
+ * instruction, not just for each unimplemented opcode.  Should
+ * probably make the 'warned' flag a static member of the derived
+ * class.
+ */
+class WarnUnimplemented : public SparcStaticInst
+{
+  private:
+/// Have we warned on this instruction yet?
+mutable bool warned;
+
+  public:
+/// Constructor
+WarnUnimplemented(const char *_mnemonic, ExtMachInst _machInst) :
+SparcStaticInst(_mnemonic, _machInst, No_OpClass),  
warned(false)

+{
+// don't call execute() (which panics) if we're on a
+// speculative path
+flags[IsNonSpeculative] = true;
+}
+
+Fault
+execute(ExecContext *xc, Trace::InstRecord *traceData) const 

[gem5-dev] Change in public/gem5[master]: sparc: Pull the "Uknown" StaticInst class out of the ISA description.

[Gabe Black (Gerrit)]

Gabe Black has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/5463 )


Change subject: sparc: Pull the "Uknown" StaticInst class out of the ISA  
description.

..

sparc: Pull the "Uknown" StaticInst class out of the ISA description.

The only thing the Unknown format does is return an instance of this
class, so there's no reason to have it in the ISA description.

Change-Id: I3f8187b1450a8622a974c030c0cb552b26f6b5f0
Reviewed-on: https://gem5-review.googlesource.com/5463
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
---
A src/arch/sparc/insts/unknown.hh
M src/arch/sparc/isa/formats/unknown.isa
M src/arch/sparc/isa/includes.isa
3 files changed, 69 insertions(+), 38 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/sparc/insts/unknown.hh  
b/src/arch/sparc/insts/unknown.hh

new file mode 100644
index 000..b5826e4
--- /dev/null
+++ b/src/arch/sparc/insts/unknown.hh
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ *  Steve Reinhardt
+ */
+
+#ifndef __ARCH_SPARC_INSTS_UNKNOWN_HH__
+#define __ARCH_SPARC_INSTS_UNKNOWN_HH__
+
+#include "arch/sparc/insts/static_inst.hh"
+
+namespace SparcISA
+{
+
+/**
+ * Class for Unknown/Illegal instructions
+ */
+class Unknown : public SparcStaticInst
+{
+  public:
+
+// Constructor
+Unknown(ExtMachInst _machInst) :
+SparcStaticInst("unknown", _machInst, No_OpClass)
+{}
+
+Fault
+execute(ExecContext *, Trace::InstRecord *) const override
+{
+return std::make_shared();
+}
+
+std::string
+generateDisassembly(Addr pc, const SymbolTable *symtab) const override
+{
+return "Unknown instruction";
+}
+
+};
+
+}
+
+#endif // __ARCH_SPARC_INSTS_UNKNOWN_HH__
diff --git a/src/arch/sparc/isa/formats/unknown.isa  
b/src/arch/sparc/isa/formats/unknown.isa

index f6f9e87..9e02dea 100644
--- a/src/arch/sparc/isa/formats/unknown.isa
+++ b/src/arch/sparc/isa/formats/unknown.isa
@@ -32,44 +32,6 @@
 // Unknown instructions
 //

-output header {{
-/**
- * Class for Unknown/Illegal instructions
- */
-class Unknown : public SparcStaticInst
-{
-  public:
-
-// Constructor
-Unknown(ExtMachInst _machInst) :
-SparcStaticInst("unknown", _machInst, No_OpClass)
-{
-}
-
-Fault execute(ExecContext *, Trace::InstRecord *) const;
-
-std::string generateDisassembly(Addr pc,
-const SymbolTable *symtab) const;
-
-};
-}};
-
-output decoder {{
-std::string Unknown::generateDisassembly(Addr pc,
-const SymbolTable *symtab) const
-{
-return "Unknown instruction";
-}
-}};
-
-output exec {{
-Fault Unknown::execute(ExecContext *xc,
-Trace::InstRecord *traceData) const
-{
-return std::make_shared();
-}
-}};
-
 def format Unknown() {{
 decode_block = 'return new Unknown(machInst);\n'
 }};
diff --git a/src/arch/sparc/isa/includes.isa  
b/src/arch/sparc/isa/includes.isa

index fb0196f..9077f7c 100644
--- a/src/arch/sparc/isa/includes.isa
+++ b/src/arch/sparc/isa/includes.isa
@@ -44,6 

[gem5-dev] Change in public/gem5[master]: sparc: Pull most of the Nop format out of the ISA description.

[Gabe Black (Gerrit)]

Gabe Black has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/5462 )


Change subject: sparc: Pull most of the Nop format out of the ISA  
description.

..

sparc: Pull most of the Nop format out of the ISA description.

The Nop format mostly just made instructions that inherited from the
Nop base class but with different mnemonics, so there doesn't need
to be very much dynamic content.

Change-Id: I1cf5e25ca8372f9b71f56d49756879c7545c9f6c
Reviewed-on: https://gem5-review.googlesource.com/5462
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
---
A src/arch/sparc/insts/nop.cc
A src/arch/sparc/insts/nop.hh
M src/arch/sparc/isa/decoder.isa
M src/arch/sparc/isa/formats/nop.isa
M src/arch/sparc/isa/includes.isa
5 files changed, 184 insertions(+), 58 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/sparc/insts/nop.cc b/src/arch/sparc/insts/nop.cc
new file mode 100644
index 000..d125790
--- /dev/null
+++ b/src/arch/sparc/insts/nop.cc
@@ -0,0 +1,90 @@
+// Copyright (c) 2006-2007 The Regents of The University of Michigan
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Gabe Black
+//  Steve Reinhardt
+
+
+//
+// Nop instruction
+//
+
+// Per-cpu-model nop execute method.
+def template NopExec {{
+}};
+
+output header {{
+/**
+ * Nop class.
+ */
+class Nop : public SparcStaticInst
+{
+  public:
+// Constructor
+Nop(const char *mnem, ExtMachInst _machInst, OpClass  
__opClass) :

+SparcStaticInst(mnem, _machInst, __opClass)
+{
+flags[IsNop] = true;
+}
+
+Fault
+execute(ExecContext *xc, Trace::InstRecord *traceData) const
+{
+return NoFault;
+}
+
+std::string generateDisassembly(Addr pc,
+const SymbolTable *symtab) const;
+};
+}};
+
+output decoder {{
+std::string Nop::generateDisassembly(Addr pc,
+const SymbolTable *symtab) const
+{
+std::stringstream response;
+printMnemonic(response, mnemonic);
+return response.str();
+}
+}};
+
+def template NopExecute {{
+Fault %(class_name)s::execute(ExecContext *xc,
+Trace::InstRecord *traceData) const
+{
+// Nothing to see here, move along
+return NoFault;
+}
+}};
+
+// Primary format for integer operate instructions:
+def format Nop(code, *opt_flags) {{
+iop = InstObjParams(name, Name, 'Nop', code, opt_flags)
+header_output = BasicDeclare.subst(iop)
+decoder_output = BasicConstructor.subst(iop)
+decode_block = BasicDecode.subst(iop)
+exec_output = NopExecute.subst(iop)
+}};
diff --git a/src/arch/sparc/insts/nop.hh b/src/arch/sparc/insts/nop.hh
new file mode 100644
index 000..b0237be
--- /dev/null
+++ b/src/arch/sparc/insts/nop.hh
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2006-2007 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: 

[gem5-dev] Change in public/gem5[master]: sparc: Pull more StaticInst base classes out of the ISA desc.

[Gabe Black (Gerrit)]

Gabe Black has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/5461 )


Change subject: sparc: Pull more StaticInst base classes out of the ISA  
desc.

..

sparc: Pull more StaticInst base classes out of the ISA desc.

These are for the trap and branch instructions.

Change-Id: Idedab6f3e6c6c954c1f8a36dae52976cf25ad394
Reviewed-on: https://gem5-review.googlesource.com/5461
Reviewed-by: Gabe Black 
Reviewed-by: Jason Lowe-Power 
Maintainer: Gabe Black 
---
M src/arch/sparc/insts/SConscript
A src/arch/sparc/insts/branch.cc
A src/arch/sparc/insts/branch.hh
A src/arch/sparc/insts/trap.cc
A src/arch/sparc/insts/trap.hh
M src/arch/sparc/isa/formats/branch.isa
M src/arch/sparc/isa/formats/trap.isa
M src/arch/sparc/isa/includes.isa
8 files changed, 357 insertions(+), 209 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Gabe Black: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/sparc/insts/SConscript  
b/src/arch/sparc/insts/SConscript

index 1e27973..24b7485 100644
--- a/src/arch/sparc/insts/SConscript
+++ b/src/arch/sparc/insts/SConscript
@@ -32,5 +32,7 @@
 Import('*')

 if env['TARGET_ISA'] == 'sparc':
+Source('branch.cc')
 Source('priv.cc')
 Source('static_inst.cc')
+Source('trap.cc')
diff --git a/src/arch/sparc/insts/branch.cc b/src/arch/sparc/insts/branch.cc
new file mode 100644
index 000..a49fd8c
--- /dev/null
+++ b/src/arch/sparc/insts/branch.cc
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2006-2007 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ *  Steve Reinhardt
+ */
+
+#include "arch/sparc/insts/branch.hh"
+
+
+//
+// Branch instructions
+//
+
+namespace SparcISA
+{
+
+template class BranchNBits<19>;
+template class BranchNBits<22>;
+template class BranchNBits<30>;
+
+std::string
+Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+std::stringstream response;
+
+printMnemonic(response, mnemonic);
+printRegArray(response, _srcRegIdx, _numSrcRegs);
+if (_numDestRegs && _numSrcRegs)
+response << ", ";
+printDestReg(response, 0);
+
+return response.str();
+}
+
+std::string
+BranchImm13::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+std::stringstream response;
+
+printMnemonic(response, mnemonic);
+printRegArray(response, _srcRegIdx, _numSrcRegs);
+if (_numSrcRegs > 0)
+response << ", ";
+ccprintf(response, "0x%x", imm);
+if (_numDestRegs > 0)
+response << ", ";
+printDestReg(response, 0);
+
+return response.str();
+}
+
+std::string
+BranchDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+std::stringstream response;
+std::string symbol;
+Addr symbol_addr;
+
+Addr target = disp + pc;
+
+printMnemonic(response, mnemonic);
+ccprintf(response, "0x%x", target);
+
+if (symtab && symtab->findNearestSymbol(target, symbol, symbol_addr)) {
+ccprintf(response, " <%s", symbol);
+if (symbol_addr != target)
+ccprintf(response, "+%d>", target - symbol_addr);
+else
+ccprintf(response, ">");
+}
+
+return response.str();
+}
+
+}
diff --git 

[gem5-dev] Change in public/gem5[master]: sparc: Pull flat static instruction classes out of the ISA.

[Gabe Black (Gerrit)]

Gabe Black has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/5422 )


Change subject: sparc: Pull flat static instruction classes out of the ISA.
..

sparc: Pull flat static instruction classes out of the ISA.

These classes are just used as base classes for other instructions
and don't need to be part of the ISA definition. Pull them into
standard C++ files.

Change-Id: If3e0bd82b1e676f20459bc0293fbda49de66b554
Reviewed-on: https://gem5-review.googlesource.com/5422
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
---
M src/arch/sparc/insts/SConscript
A src/arch/sparc/insts/priv.cc
A src/arch/sparc/insts/priv.hh
M src/arch/sparc/isa/decoder.isa
M src/arch/sparc/isa/formats/priv.isa
M src/arch/sparc/isa/includes.isa
6 files changed, 291 insertions(+), 237 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/sparc/insts/SConscript  
b/src/arch/sparc/insts/SConscript

index 94996f6..1e27973 100644
--- a/src/arch/sparc/insts/SConscript
+++ b/src/arch/sparc/insts/SConscript
@@ -32,4 +32,5 @@
 Import('*')

 if env['TARGET_ISA'] == 'sparc':
+Source('priv.cc')
 Source('static_inst.cc')
diff --git a/src/arch/sparc/insts/priv.cc b/src/arch/sparc/insts/priv.cc
new file mode 100644
index 000..ce6d044
--- /dev/null
+++ b/src/arch/sparc/insts/priv.cc
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2006-2007 The Regents of The University of Michigan
+ * All rights reserved
+ * Copyright 2017 Google Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ *  Gabe Black
+ *  Steve Reinhardt
+ */
+
+#include "arch/sparc/insts/priv.hh"
+
+namespace SparcISA
+{
+
+std::string
+Priv::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+std::stringstream response;
+
+printMnemonic(response, mnemonic);
+
+return response.str();
+}
+
+std::string
+RdPriv::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+std::stringstream response;
+
+printMnemonic(response, mnemonic);
+
+ccprintf(response, " %%%s, ", regName);
+printDestReg(response, 0);
+
+return response.str();
+}
+
+std::string
+WrPriv::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+std::stringstream response;
+
+printMnemonic(response, mnemonic);
+
+ccprintf(response, " ");
+// If the first reg is %g0, don't print it.
+// This improves readability
+if (_srcRegIdx[0].index() != 0) {
+printSrcReg(response, 0);
+ccprintf(response, ", ");
+}
+printSrcReg(response, 1);
+ccprintf(response, ", %%%s", regName);
+
+return response.str();
+}
+
+std::string
+WrPrivImm::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+std::stringstream response;
+
+printMnemonic(response, mnemonic);
+
+ccprintf(response, " ");
+// If the first reg is %g0, don't print it.
+// This improves readability
+if (_srcRegIdx[0].index() != 0) {
+printSrcReg(response, 0);
+ccprintf(response, ", ");
+}
+ccprintf(response, "%#x, %%%s", imm, regName);
+
+return response.str();
+}
+
+}
diff --git a/src/arch/sparc/insts/priv.hh b/src/arch/sparc/insts/priv.hh
new file mode 100644
index 000..6530d09
--- /dev/null
+++ b/src/arch/sparc/insts/priv.hh
@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2006-2007 The Regents of The University of 

[gem5-dev] Change in public/gem5[master]: scons: Move some compiler flag setting code to the SConstruct.

[Gabe Black (Gerrit)]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/5981



Change subject: scons: Move some compiler flag setting code to the  
SConstruct.

..

scons: Move some compiler flag setting code to the SConstruct.

These settings are invariant, so there's no reason to apply them over
and over again for the child environments used for various build
products.

Change-Id: Icb4053105e4f1c43008f2422ba30c7206b7ff365
---
M SConstruct
M src/SConscript
2 files changed, 35 insertions(+), 38 deletions(-)



diff --git a/SConstruct b/SConstruct
index 095b58b..36db216 100755
--- a/SConstruct
+++ b/SConstruct
@@ -473,6 +473,25 @@
 if compareVersions(gcc_version, "5.0") > 0:
 main.Append(CCFLAGS=['-Wno-error=suggest-override'])

+# The address sanitizer is available for gcc >= 4.8
+if GetOption('with_asan'):
+if GetOption('with_ubsan') and \
+compareVersions(env['GCC_VERSION'], '4.9') >= 0:
+env.Append(CCFLAGS=['-fsanitize=address,undefined',
+'-fno-omit-frame-pointer'],
+   LINKFLAGS='-fsanitize=address,undefined')
+else:
+env.Append(CCFLAGS=['-fsanitize=address',
+'-fno-omit-frame-pointer'],
+   LINKFLAGS='-fsanitize=address')
+# Only gcc >= 4.9 supports UBSan, so check both the version
+# and the command-line option before adding the compiler and
+# linker flags.
+elif GetOption('with_ubsan') and \
+compareVersions(env['GCC_VERSION'], '4.9') >= 0:
+env.Append(CCFLAGS='-fsanitize=undefined')
+env.Append(LINKFLAGS='-fsanitize=undefined')
+
 elif main['CLANG']:
 # Check for a supported version of clang, >= 3.1 is needed to
 # support similar features as gcc 4.8. See
@@ -513,6 +532,22 @@
 if sys.platform.startswith('freebsd'):
 main.Append(LIBS=['thr'])

+# We require clang >= 3.1, so there is no need to check any
+# versions here.
+if GetOption('with_ubsan'):
+if GetOption('with_asan'):
+env.Append(CCFLAGS=['-fsanitize=address,undefined',
+'-fno-omit-frame-pointer'],
+   LINKFLAGS='-fsanitize=address,undefined')
+else:
+env.Append(CCFLAGS='-fsanitize=undefined',
+   LINKFLAGS='-fsanitize=undefined')
+
+elif GetOption('with_asan'):
+env.Append(CCFLAGS=['-fsanitize=address',
+'-fno-omit-frame-pointer'],
+   LINKFLAGS='-fsanitize=address')
+
 else:
 print termcap.Yellow + termcap.Bold + 'Error' + termcap.Normal,
 print "Don't know what compiler options to use for your compiler."
diff --git a/src/SConscript b/src/SConscript
index f9560af..a40955b 100755
--- a/src/SConscript
+++ b/src/SConscript
@@ -952,44 +952,6 @@
 new_env.Label = label
 new_env.Append(**kwargs)

-if env['GCC']:
-# The address sanitizer is available for gcc >= 4.8
-if GetOption('with_asan'):
-if GetOption('with_ubsan') and \
-compareVersions(env['GCC_VERSION'], '4.9') >= 0:
-new_env.Append(CCFLAGS=['-fsanitize=address,undefined',
-'-fno-omit-frame-pointer'])
-new_env.Append(LINKFLAGS='-fsanitize=address,undefined')
-else:
-new_env.Append(CCFLAGS=['-fsanitize=address',
-'-fno-omit-frame-pointer'])
-new_env.Append(LINKFLAGS='-fsanitize=address')
-# Only gcc >= 4.9 supports UBSan, so check both the version
-# and the command-line option before adding the compiler and
-# linker flags.
-elif GetOption('with_ubsan') and \
-compareVersions(env['GCC_VERSION'], '4.9') >= 0:
-new_env.Append(CCFLAGS='-fsanitize=undefined')
-new_env.Append(LINKFLAGS='-fsanitize=undefined')
-
-
-if env['CLANG']:
-# We require clang >= 3.1, so there is no need to check any
-# versions here.
-if GetOption('with_ubsan'):
-if GetOption('with_asan'):
-new_env.Append(CCFLAGS=['-fsanitize=address,undefined',
-'-fno-omit-frame-pointer'])
-new_env.Append(LINKFLAGS='-fsanitize=address,undefined')
-else:
-new_env.Append(CCFLAGS='-fsanitize=undefined')
-new_env.Append(LINKFLAGS='-fsanitize=undefined')
-
-elif GetOption('with_asan'):
-new_env.Append(CCFLAGS=['-fsanitize=address',
-'-fno-omit-frame-pointer'])
-new_env.Append(LINKFLAGS='-fsanitize=address')
-
 werror_env = new_env.Clone()
 # Treat warnings as errors but white list some warnings that we
 # want to 

[gem5-dev] Change in public/gem5[master]: scons: Minor cleanup of how partial linking is handled in makeEnv.

[Gabe Black (Gerrit)]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/5985



Change subject: scons: Minor cleanup of how partial linking is handled in  
makeEnv.

..

scons: Minor cleanup of how partial linking is handled in makeEnv.

Git rid of the unused partial_objs variable, and change append to
extend since the result of builders is a list of nodes and not
individual nodes, even if there's only one target.

Change-Id: Ie51225d3ea699eb7da18199ac3bf3e868e3994a6
---
M src/SConscript
1 file changed, 11 insertions(+), 13 deletions(-)



diff --git a/src/SConscript b/src/SConscript
index 28ae354..2930bab 100755
--- a/src/SConscript
+++ b/src/SConscript
@@ -968,42 +968,40 @@
 static_objs.append(make_static(s))
 shared_objs.append(make_shared(s))

-partial_objs = []
-
 for group in Source.source_groups:
 srcs = lib_sources.with_tag(Source.link_group_tag(group))
 if not srcs:
 continue

+group_static = [ make_static(s) for s in srcs ]
+group_shared = [ make_shared(s) for s in srcs ]
+
 # If partial linking is disabled, add these sources to the build
 # directly, and short circuit this loop.
 if disable_partial:
-for s in srcs:
-static_objs.append(make_static(s))
-shared_objs.append(make_shared(s))
+static_objs.extend(group_static)
+shared_objs.extend(group_shared)
 continue

 # Set up the static partially linked objects.
-source_objs = [ make_static(s) for s in srcs ]
 file_name = new_env.subst("${OBJPREFIX}lib${OBJSUFFIX}.partial")
 target = File(joinpath(group, file_name))
-partial = env.PartialStatic(target=target, source=source_objs)
-static_objs.append(partial)
+partial = env.PartialStatic(target=target, source=group_static)
+static_objs.extend(partial)

 # Set up the shared partially linked objects.
-source_objs = [ make_shared(s) for s in srcs ]
 file_name =  
new_env.subst("${SHOBJPREFIX}lib${SHOBJSUFFIX}.partial")

 target = File(joinpath(group, file_name))
-partial = env.PartialShared(target=target, source=source_objs)
-shared_objs.append(partial)
+partial = env.PartialShared(target=target, source=group_shared)
+shared_objs.extend(partial)

 static_date = make_static(date_source)
 new_env.Depends(static_date, static_objs)
-static_objs.append(static_date)
+static_objs.extend(static_date)

 shared_date = make_shared(date_source)
 new_env.Depends(shared_date, shared_objs)
-shared_objs.append(shared_date)
+shared_objs.extend(shared_date)

 # First make a library of everything but main() so other programs can
 # link against m5.

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[gem5-dev] Change in public/gem5[master]: scons: Switch from "guards" to "tags" on source files.

[Gabe Black (Gerrit)]

Hello Jason Lowe-Power, Andreas Sandberg,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/5822

to look at the new patch set (#3).

Change subject: scons: Switch from "guards" to "tags" on source files.
..

scons: Switch from "guards" to "tags" on source files.

Tags are just arbitrary strings which are attached to source files
which mark them as having some property. By default, all source files
have the "gem5 lib" tag added to them which marks them as part of the
gem5 library, the primary component of the gem5 binary but also a
seperable component for use in, for example, system C.

The tags can be completely overridden by setting the "tags" parameter
on Source, etc., functions, and can be augmented by setting "add_tags"
which are tags that will be added, or alternatively additional tags.
It's possible to specify both, in which case the tags will be set to
the union of tags and add_tags. add_tags is supposed to be a way to
add extra tags to the default without actually overriding the default.
Both tags and add_tags can be a list/tuple/etc of tags, or a single
string which will be converted into a set internally.

Other existing tags include:
1. "python" for files that need or are used with python and are
   excluded when the --without-python option is set
2. "main" for the file(s) which implement the gem5 binary's main
   function.
3. The name of a unit test to group its files together.
4. Tags which group source files for partial linking.

By grouping the "tags" into a single parameter instead of taking all
extra parameters as tags, the extra parameters can, in the future, be
passed to the underlying scons environment. Also, the tags are either
present or not. With guards, they could be present and True, present
and False, or not present at all.

Change-Id: I6d0404211a393968df66f7eddfe019897b6573a2
---
M src/SConscript
M src/python/SConscript
M src/sim/SConscript
M src/unittest/SConscript
4 files changed, 94 insertions(+), 101 deletions(-)


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Gerrit-Change-Number: 5822
Gerrit-PatchSet: 3
Gerrit-Owner: Gabe Black 
Gerrit-Assignee: Jason Lowe-Power 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
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[gem5-dev] Change in public/gem5[master]: scons: Remove the extra_deps option from the helper function make_obj.

[Gabe Black (Gerrit)]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/5983



Change subject: scons: Remove the extra_deps option from the helper  
function make_obj.

..

scons: Remove the extra_deps option from the helper function make_obj.

This had only one use, and made the function more complicated than it
needed to be.

Change-Id: I22147a0c1239b457c577a6a24b423065e539833b
---
M src/SConscript
1 file changed, 8 insertions(+), 13 deletions(-)



diff --git a/src/SConscript b/src/SConscript
index 34bbcc0..61af95b 100755
--- a/src/SConscript
+++ b/src/SConscript
@@ -951,19 +951,12 @@
 new_env.Label = label
 new_env.Append(**kwargs)

-def make_obj(source, static, extra_deps=None):
-'''This function creates a scons node of the requested type, and  
sets

-up any additional dependencies.'''
-
+def make_obj(source, static):
+'''This function creates a scons node of the requested type.'''
 if static:
-obj = new_env.StaticObject(source.tnode)
+return new_env.StaticObject(source.tnode)
 else:
-obj = new_env.SharedObject(source.tnode)
-
-if extra_deps:
-new_env.Depends(obj, extra_deps)
-
-return obj
+return new_env.SharedObject(source.tnode)

 lib_sources = Source.all.with_tag('gem5 lib')

@@ -1008,10 +1001,12 @@
 partial = env.PartialShared(target=target, source=source_objs)
 shared_objs.append(partial)

-static_date = make_obj(date_source, static=True,  
extra_deps=static_objs)

+static_date = make_obj(date_source, static=True)
+new_env.Depends(static_date, static_objs)
 static_objs.append(static_date)

-shared_date = make_obj(date_source, static=False,  
extra_deps=shared_objs)

+shared_date = make_obj(date_source, static=False)
+new_env.Depends(shared_date, shared_objs)
 shared_objs.append(shared_date)

 # First make a library of everything but main() so other programs can

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[gem5-dev] Change in public/gem5[master]: scons: Break make_obj into make_static and make_shared functions.

[Gabe Black (Gerrit)]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/5984



Change subject: scons: Break make_obj into make_static and make_shared  
functions.

..

scons: Break make_obj into make_static and make_shared functions.

The make_obj function took a boolean value which just selected which
of the two lines it in would actually do something. This change breaks
it into two lambdas, make_static and make_shared, which just do
whichever line would have been requested, making the funciton name more
self descriptive and getting rid of the generally unnamed and opaque
boolean argument.

Change-Id: I457e40034b7e7f5a3e7294a8e1f15bbd42e0720e
---
M src/SConscript
1 file changed, 12 insertions(+), 16 deletions(-)



diff --git a/src/SConscript b/src/SConscript
index 61af95b..28ae354 100755
--- a/src/SConscript
+++ b/src/SConscript
@@ -951,12 +951,8 @@
 new_env.Label = label
 new_env.Append(**kwargs)

-def make_obj(source, static):
-'''This function creates a scons node of the requested type.'''
-if static:
-return new_env.StaticObject(source.tnode)
-else:
-return new_env.SharedObject(source.tnode)
+make_static = lambda source: new_env.StaticObject(source.tnode)
+make_shared = lambda source: new_env.SharedObject(source.tnode)

 lib_sources = Source.all.with_tag('gem5 lib')

@@ -969,8 +965,8 @@
 shared_objs = []

 for s in lib_sources.with_tag(Source.ungrouped_tag):
-static_objs.append(make_obj(s, True))
-shared_objs.append(make_obj(s, False))
+static_objs.append(make_static(s))
+shared_objs.append(make_shared(s))

 partial_objs = []

@@ -983,29 +979,29 @@
 # directly, and short circuit this loop.
 if disable_partial:
 for s in srcs:
-static_objs.append(make_obj(s, True))
-shared_objs.append(make_obj(s, False))
+static_objs.append(make_static(s))
+shared_objs.append(make_shared(s))
 continue

 # Set up the static partially linked objects.
-source_objs = [ make_obj(s, True) for s in srcs ]
+source_objs = [ make_static(s) for s in srcs ]
 file_name = new_env.subst("${OBJPREFIX}lib${OBJSUFFIX}.partial")
 target = File(joinpath(group, file_name))
 partial = env.PartialStatic(target=target, source=source_objs)
 static_objs.append(partial)

 # Set up the shared partially linked objects.
-source_objs = [ make_obj(s, False) for s in srcs ]
+source_objs = [ make_shared(s) for s in srcs ]
 file_name =  
new_env.subst("${SHOBJPREFIX}lib${SHOBJSUFFIX}.partial")

 target = File(joinpath(group, file_name))
 partial = env.PartialShared(target=target, source=source_objs)
 shared_objs.append(partial)

-static_date = make_obj(date_source, static=True)
+static_date = make_static(date_source)
 new_env.Depends(static_date, static_objs)
 static_objs.append(static_date)

-shared_date = make_obj(date_source, static=False)
+shared_date = make_shared(date_source)
 new_env.Depends(shared_date, shared_objs)
 shared_objs.append(shared_date)

@@ -1015,11 +1011,11 @@
 shared_lib = new_env.SharedLibrary(libname, shared_objs)

 # Now link a stub with main() and the static library.
-main_objs = [ make_obj(s, True) for s in Source.all.with_tag('main') ]
+main_objs = [ make_static(s) for s in Source.all.with_tag('main') ]

 for test in UnitTest.all:
 test_sources = Source.all.with_tag(str(test.target))
-test_objs = [ make_obj(s, static=True) for s in test_sources ]
+test_objs = [ make_static(s) for s in test_sources ]
 if test.main:
 test_objs += main_objs
 path = 'unittest/%s.%s' % (test.target, label)

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[gem5-dev] Change in public/gem5[master]: scons: Get rid of a flag which makes Werror optional.

[Gabe Black (Gerrit)]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/5982



Change subject: scons: Get rid of a flag which makes Werror optional.
..

scons: Get rid of a flag which makes Werror optional.

This flag wasn't being used. Also move the Werror code to the
SConstruct now that it's being applied universally.

Change-Id: I18b00d4b41bc1add9271ca299c020c14970a6926
---
M SConstruct
M src/SConscript
2 files changed, 14 insertions(+), 22 deletions(-)



diff --git a/SConstruct b/SConstruct
index 36db216..09c3476 100755
--- a/SConstruct
+++ b/SConstruct
@@ -359,6 +359,13 @@
 shared_partial_flags = ['-r', '-nostdlib']
 main.Append(PSHLINKFLAGS=shared_partial_flags)
 main.Append(PLINKFLAGS=shared_partial_flags)
+
+# Treat warnings as errors but white list some warnings that we
+# want to allow (e.g., deprecation warnings).
+main.Append(CCFLAGS=['-Werror',
+ '-Wno-error=deprecated-declarations',
+ '-Wno-error=deprecated',
+])
 else:
 print termcap.Yellow + termcap.Bold + 'Error' + termcap.Normal,
 print "Don't know what compiler options to use for your compiler."
diff --git a/src/SConscript b/src/SConscript
index a40955b..34bbcc0 100755
--- a/src/SConscript
+++ b/src/SConscript
@@ -172,11 +172,10 @@
 self.tags.add(Source._current_group_tag)

 '''Add a c/c++ source file to the build'''
-def __init__(self, source, tags=None, add_tags=None, Werror=True):
+def __init__(self, source, tags=None, add_tags=None):
 '''specify the source file, and any tags'''
 super(Source, self).__init__(source, tags, add_tags)
 self._add_link_group_tag()
-self.Werror = Werror

 class PySource(SourceFile):
 '''Add a python source file to the named package'''
@@ -952,31 +951,17 @@
 new_env.Label = label
 new_env.Append(**kwargs)

-werror_env = new_env.Clone()
-# Treat warnings as errors but white list some warnings that we
-# want to allow (e.g., deprecation warnings).
-werror_env.Append(CCFLAGS=['-Werror',
-   '-Wno-error=deprecated-declarations',
-   '-Wno-error=deprecated',
-   ])
-
-def make_obj(source, static, extra_deps = None):
-'''This function adds the specified source to the correct
-build environment, and returns the corresponding SCons Object
-nodes'''
-
-if source.Werror:
-env = werror_env
-else:
-env = new_env
+def make_obj(source, static, extra_deps=None):
+'''This function creates a scons node of the requested type, and  
sets

+up any additional dependencies.'''

 if static:
-obj = env.StaticObject(source.tnode)
+obj = new_env.StaticObject(source.tnode)
 else:
-obj = env.SharedObject(source.tnode)
+obj = new_env.SharedObject(source.tnode)

 if extra_deps:
-env.Depends(obj, extra_deps)
+new_env.Depends(obj, extra_deps)

 return obj


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Re: [gem5-dev] SPARC cls and statute of limitation on reviews

[Gabe Black]

Ok, sounds good. I was thinking that sort of thing would make sense, but
didn't want to go that way unilaterally.

Gabe

On Tue, Nov 21, 2017 at 6:05 AM, Andreas Sandberg 
wrote:

> Hi Gabe,
>
> I won't have time to review them anytime soon. Since only Jason has
> offered to review some of them, I'd suggest that we go for a more
> relaxed review policy for SPARC. I would be happy for you to self
> approve these changes since you are the SPARC maintainer and there are
> no other obvious reviewers.
>
> Cheers,
> Andreas
>
>
>
> On 18/11/2017 01:45, Jason Lowe-Power wrote:
>
>> Hey Gabe,
>>
>> I'll *try* to find some time this weekend to skim them. I'll aim for
>> giving
>> at least +1, after which I'm fine with you taking responsibility for any
>> bugs and pushing :).
>>
>> I'll also try to catch up on all of the gem5 things that have been flying
>> past my inbox. We'll see how that goes, though.
>>
>> Cheers,
>> Jason
>>
>> ---
>> Jason Lowe-Power
>> Assistant Professor, Computer Science Department
>> University of California, Davis
>> 3049 Kemper Hall
>> https://faculty.engineering.ucdavis.edu/lowepower/
>>
>>
>> On Fri, Nov 17, 2017 at 3:39 PM Gabe Black  wrote:
>>
>> Hi folks. I have a series of CLs for the SPARC ISA (
>>> https://gem5-review.googlesource.com/c/public/gem5/+/5421/2, etc.) which
>>> haven'b gotten reviews in a while. I realize there may not be anyone to
>>> jump in and review SPARC changes, and I even chose to tinker with SPARC
>>> since it's a relatively quite corner where I'm not likely to disrupt
>>> anybody.
>>>
>>> I do, however, want to get those changes checked in at some point. Does
>>> anyone want to review them? Is there a point where there's been enough
>>> time
>>> for anybody who was sufficiently motivated to look at them, and I can go
>>> ahead and check them in unreviewed?
>>>
>>> Gabe
>>> ___
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>>> http://m5sim.org/mailman/listinfo/gem5-dev
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[gem5-dev] Change in public/gem5[master]: arch-arm: ArmPMU refactor

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/5764 )


Change subject: arch-arm: ArmPMU refactor
..

arch-arm: ArmPMU refactor

Change the definition of PMU events in order to integrate events not
cannot easily be represented by probe points. The software
increment event is now defined as a special type with its separate
implementation in pmu.cc and pmu.hh.

Change-Id: I43874b9641bf38c54f6ba2c26386542b6a73e282
Signed-off-by: Jose Marinho 
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/5764
Maintainer: Andreas Sandberg 
---
M src/arch/arm/ArmPMU.py
M src/arch/arm/pmu.cc
M src/arch/arm/pmu.hh
3 files changed, 506 insertions(+), 204 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/arm/ArmPMU.py b/src/arch/arm/ArmPMU.py
index 83c7dd4..a87c20b 100644
--- a/src/arch/arm/ArmPMU.py
+++ b/src/arch/arm/ArmPMU.py
@@ -43,38 +43,61 @@
 from m5.params import isNullPointer
 from m5.proxy import *

+class ProbeEvent(object):
+def __init__(self, pmu, _eventId, obj, *listOfNames):
+self.obj = obj
+self.names = listOfNames
+self.eventId = _eventId
+self.pmu = pmu
+
+def register(self):
+if self.obj:
+for name in self.names:
+self.pmu.getCCObject().addEventProbe(self.eventId,
+self.obj.getCCObject(), name)
+
+class SoftwareIncrement(object):
+def __init__(self,pmu, _eventId):
+self.eventId = _eventId
+self.pmu = pmu
+
+def register(self):
+self.pmu.getCCObject().addSoftwareIncrementEvent(self.eventId)
+
+ARCH_EVENT_CORE_CYCLES = 0x11
+
 class ArmPMU(SimObject):
+
 type = 'ArmPMU'
 cxx_class = 'ArmISA::PMU'
 cxx_header = 'arch/arm/pmu.hh'

 cxx_exports = [
 PyBindMethod("addEventProbe"),
+PyBindMethod("addSoftwareIncrementEvent"),
 ]

-# To prevent cycles in the configuration hierarchy, we don't keep
-# a list of supported events as a configuration param. Instead, we
-# keep them in a local list and register them using the
-# addEventProbe interface when other SimObjects register their
-# probe listeners.
-_deferred_event_types = []
+_events = None
+
+def addEvent(self, newObject):
+if not (isinstance(newObject, ProbeEvent)
+or isinstance(newObject, SoftwareIncrement)):
+raise TypeError("argument must be of ProbeEvent or "
+"SoftwareIncrement type")
+
+if not self._events:
+self._events = []
+
+self._events.append(newObject)
+
 # Override the normal SimObject::regProbeListeners method and
 # register deferred event handlers.
 def regProbeListeners(self):
-for event_id, obj, name in self._deferred_event_types:
-self.getCCObject().addEventProbe(event_id, obj.getCCObject(),  
name)

+for event in self._events:
+   event.register()

 self.getCCObject().regProbeListeners()

-def addEventProbe(self, event_id, obj, *args):
-"""Add a probe-based event to the PMU if obj is not None."""
-
-if obj is None:
-return
-
-for name in args:
-self._deferred_event_types.append((event_id, obj, name))
-
 def addArchEvents(self,
   cpu=None,
   itb=None, dtb=None,
@@ -95,25 +118,28 @@
 bpred = cpu.branchPred if cpu and not  
isNullPointer(cpu.branchPred) \

 else None

+self.addEvent(SoftwareIncrement(self,0x00))
 # 0x01: L1I_CACHE_REFILL
-self.addEventProbe(0x02, itb, "Refills")
+self.addEvent(ProbeEvent(self,0x02, itb, "Refills"))
 # 0x03: L1D_CACHE_REFILL
 # 0x04: L1D_CACHE
-self.addEventProbe(0x05, dtb, "Refills")
-self.addEventProbe(0x06, cpu, "RetiredLoads")
-self.addEventProbe(0x07, cpu, "RetiredStores")
-self.addEventProbe(0x08, cpu, "RetiredInsts")
+self.addEvent(ProbeEvent(self,0x05, dtb, "Refills"))
+self.addEvent(ProbeEvent(self,0x06, cpu, "RetiredLoads"))
+self.addEvent(ProbeEvent(self,0x07, cpu, "RetiredStores"))
+self.addEvent(ProbeEvent(self,0x08, cpu, "RetiredInsts"))
 # 0x09: EXC_TAKEN
 # 0x0A: EXC_RETURN
 # 0x0B: CID_WRITE_RETIRED
-self.addEventProbe(0x0C, cpu, "RetiredBranches")
+self.addEvent(ProbeEvent(self,0x0C, cpu, "RetiredBranches"))
 # 0x0D: BR_IMMED_RETIRED
 # 0x0E: BR_RETURN_RETIRED
 # 0x0F: UNALIGEND_LDST_RETIRED
-self.addEventProbe(0x10, bpred, "Misses")
-self.addEventProbe(0x11, cpu, "ActiveCycles")
-self.addEventProbe(0x12, bpred, "Branches")
-self.addEventProbe(0x13, cpu, 

[gem5-dev] Change in public/gem5[master]: cpu, cpu, sim: move Cycle probe update

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/5762 )


Change subject: cpu, cpu, sim: move Cycle probe update
..

cpu, cpu, sim: move Cycle probe update

Move the code responsible for performing the actual probe point notify
into BaseCPU. Use BaseCPU activateContext and suspendContext to keep
track of sleep cycles. Create a probe point (ppActiveCycles) that does
not count cycles where the processor was asleep. Rename ppCycles
to ppAllCycles to reflect its nature.

Change-Id: I1907ddd07d0ff9f2ef22cc9f61f5f46c630c9d66
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/5762
Maintainer: Andreas Sandberg 
Reviewed-by: Jason Lowe-Power 
---
M src/cpu/base.cc
M src/cpu/base.hh
M src/cpu/kvm/base.cc
M src/cpu/minor/pipeline.hh
M src/cpu/o3/cpu.cc
M src/cpu/simple/atomic.cc
M src/cpu/simple/base.cc
M src/cpu/simple/timing.cc
8 files changed, 88 insertions(+), 19 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index af55ee1..a41a0c3 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -133,6 +133,7 @@
   _switchedOut(p->switched_out),  
_cacheLineSize(p->system->cacheLineSize()),

   interrupts(p->interrupts), profileEvent(NULL),
   numThreads(p->numThreads), system(p->system),
+  previousCycle(0), previousState(CPU_STATE_SLEEP),
   functionTraceStream(nullptr), currentFunctionStart(0),
   currentFunctionEnd(0), functionEntryTick(0),
   addressMonitor(p->numThreads),
@@ -385,12 +386,16 @@
 void
 BaseCPU::regProbePoints()
 {
-ppCycles = pmuProbePoint("Cycles");
+ppAllCycles = pmuProbePoint("Cycles");
+ppActiveCycles = pmuProbePoint("ActiveCycles");

 ppRetiredInsts = pmuProbePoint("RetiredInsts");
 ppRetiredLoads = pmuProbePoint("RetiredLoads");
 ppRetiredStores = pmuProbePoint("RetiredStores");
 ppRetiredBranches = pmuProbePoint("RetiredBranches");
+
+ppSleeping = new ProbePointArg(this->getProbeManager(),
+ "Sleeping");
 }

 void
@@ -520,9 +525,10 @@
 // Squash enter power gating event while cpu gets activated
 if (enterPwrGatingEvent.scheduled())
 deschedule(enterPwrGatingEvent);
-
 // For any active thread running, update CPU power state to active (ON)
 ClockedObject::pwrState(Enums::PwrState::ON);
+
+updateCycleCounters(CPU_STATE_WAKEUP);
 }

 void
@@ -535,6 +541,9 @@
 }
 }

+// All CPU thread are suspended, update cycle count
+updateCycleCounters(CPU_STATE_SLEEP);
+
 // All CPU threads suspended, enter lower power state for the CPU
 ClockedObject::pwrState(Enums::PwrState::CLK_GATED);

@@ -547,6 +556,12 @@
 }

 void
+BaseCPU::haltContext(ThreadID thread_num)
+{
+updateCycleCounters(BaseCPU::CPU_STATE_SLEEP);
+}
+
+void
 BaseCPU::enterPwrGating(void)
 {
 ClockedObject::pwrState(Enums::PwrState::OFF);
@@ -579,6 +594,10 @@
 _taskId = oldCPU->taskId();
 // Take over the power state of the switchedOut CPU
 ClockedObject::pwrState(oldCPU->pwrState());
+
+previousState = oldCPU->previousState;
+previousCycle = oldCPU->previousCycle;
+
 _switchedOut = false;

 ThreadID size = threadContexts.size();
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 13c56a9..52598fd 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -63,6 +63,7 @@
 #include "sim/full_system.hh"
 #include "sim/insttracer.hh"
 #include "sim/probe/pmu.hh"
+#include "sim/probe/probe.hh"
 #include "sim/system.hh"
 #include "debug/Mwait.hh"

@@ -277,7 +278,7 @@
 virtual void suspendContext(ThreadID thread_num);

 /// Notify the CPU that the indicated context is now halted.
-virtual void haltContext(ThreadID thread_num) {}
+virtual void haltContext(ThreadID thread_num);

/// Given a Thread Context pointer return the thread num
int findContext(ThreadContext *tc);
@@ -489,6 +490,7 @@
  */
 virtual void probeInstCommit(const StaticInstPtr );

+   protected:
 /**
  * Helper method to instantiate probe points belonging to this
  * object.
@@ -498,9 +500,6 @@
  */
 ProbePoints::PMUUPtr pmuProbePoint(const char *name);

-/** CPU cycle counter */
-ProbePoints::PMUUPtr ppCycles;
-
 /**
  * Instruction commit probe point.
  *
@@ -519,9 +518,58 @@
 /** Retired branches (any type) */
 ProbePoints::PMUUPtr ppRetiredBranches;

+/** CPU cycle counter even if any thread Context is suspended*/
+ProbePoints::PMUUPtr ppAllCycles;
+
+/** CPU cycle counter, only counts if any thread contexts is active **/
+ProbePoints::PMUUPtr ppActiveCycles;
+
+/**
+ * ProbePoint that signals transitions of 

[gem5-dev] Change in public/gem5[master]: arch-arm: Do not increment PMU cycle event in WFI/WFE

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/5763 )


Change subject: arch-arm: Do not increment PMU cycle event in WFI/WFE
..

arch-arm: Do not increment PMU cycle event in WFI/WFE

Change-Id: I09531e9992e045254e5ee989dd11ccabbf84e4ce
Reviewed-by: Sascha Bischoff 
Reviewed-on: https://gem5-review.googlesource.com/5763
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
---
M src/arch/arm/ArmPMU.py
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/arm/ArmPMU.py b/src/arch/arm/ArmPMU.py
index 4292fd5..83c7dd4 100644
--- a/src/arch/arm/ArmPMU.py
+++ b/src/arch/arm/ArmPMU.py
@@ -111,7 +111,7 @@
 # 0x0E: BR_RETURN_RETIRED
 # 0x0F: UNALIGEND_LDST_RETIRED
 self.addEventProbe(0x10, bpred, "Misses")
-self.addEventProbe(0x11, cpu, "Cycles")
+self.addEventProbe(0x11, cpu, "ActiveCycles")
 self.addEventProbe(0x12, bpred, "Branches")
 self.addEventProbe(0x13, cpu, "RetiredLoads", "RetiredStores")
 # 0x14: L1I_CACHE

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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I09531e9992e045254e5ee989dd11ccabbf84e4ce
Gerrit-Change-Number: 5763
Gerrit-PatchSet: 4
Gerrit-Owner: Andreas Sandberg 
Gerrit-Reviewer: Andreas Sandberg 
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[gem5-dev] Change in public/gem5[master]: sim: Fix need to save address space info during serialization.

[Austin Harris (Gerrit)]

Austin Harris has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/5901 )


Change subject: sim: Fix need to save address space info during  
serialization.

..

sim: Fix need to save address space info during serialization.

This fixes a fatal already mapped error in
FuncPageTable::allocate that occurs in some cases
when restoring from a checkpoint.

Change-Id: Ib726a69358118626663e42b7f14889b0d3a98de0
Reported-by: Ruohuang Zheng 
Signed-off-by: Austin Harris 
Reviewed-on: https://gem5-review.googlesource.com/5901
Reviewed-by: Gabe Black 
Reviewed-by: Andreas Sandberg 
Maintainer: Jason Lowe-Power 
---
M src/sim/mem_state.hh
M src/sim/process.cc
2 files changed, 28 insertions(+), 1 deletion(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved



diff --git a/src/sim/mem_state.hh b/src/sim/mem_state.hh
index 03a7197..ca07a64 100644
--- a/src/sim/mem_state.hh
+++ b/src/sim/mem_state.hh
@@ -31,6 +31,8 @@
 #ifndef SRC_SIM_MEM_STATE_HH
 #define SRC_SIM_MEM_STATE_HH

+#include "sim/serialize.hh"
+
 /**
  * This class holds the memory state for the Process class and all of its
  * derived, architecture-specific children.
@@ -45,7 +47,7 @@
  * pointer interface because two process can potentially share their  
virtual

  * address space if certain options are passed into the clone(2).
  */
-class MemState
+class MemState : public Serializable
 {
   public:
 MemState(Addr brk_point, Addr stack_base, Addr max_stack_size,
@@ -87,6 +89,29 @@
 void setNextThreadStackBase(Addr ntsb) { _nextThreadStackBase = ntsb; }
 void setMmapEnd(Addr mmap_end) { _mmapEnd = mmap_end; }

+void
+serialize(CheckpointOut ) const override
+{
+paramOut(cp, "brkPoint", _brkPoint);
+paramOut(cp, "stackBase", _stackBase);
+paramOut(cp, "stackSize", _stackSize);
+paramOut(cp, "maxStackSize", _maxStackSize);
+paramOut(cp, "stackMin", _stackMin);
+paramOut(cp, "nextThreadStackBase", _nextThreadStackBase);
+paramOut(cp, "mmapEnd", _mmapEnd);
+}
+void
+unserialize(CheckpointIn ) override
+{
+paramIn(cp, "brkPoint", _brkPoint);
+paramIn(cp, "stackBase", _stackBase);
+paramIn(cp, "stackSize", _stackSize);
+paramIn(cp, "maxStackSize", _maxStackSize);
+paramIn(cp, "stackMin", _stackMin);
+paramIn(cp, "nextThreadStackBase", _nextThreadStackBase);
+paramIn(cp, "mmapEnd", _mmapEnd);
+}
+
   private:
 Addr _brkPoint;
 Addr _stackBase;
diff --git a/src/sim/process.cc b/src/sim/process.cc
index bfc52c3..ee90667 100644
--- a/src/sim/process.cc
+++ b/src/sim/process.cc
@@ -367,6 +367,7 @@
 void
 Process::serialize(CheckpointOut ) const
 {
+memState->serialize(cp);
 pTable->serialize(cp);
 /**
  * Checkpoints for file descriptors currently do not work. Need to
@@ -384,6 +385,7 @@
 void
 Process::unserialize(CheckpointIn )
 {
+memState->unserialize(cp);
 pTable->unserialize(cp);
 /**
  * Checkpoints for file descriptors currently do not work. Need to

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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: Ib726a69358118626663e42b7f14889b0d3a98de0
Gerrit-Change-Number: 5901
Gerrit-PatchSet: 3
Gerrit-Owner: Austin Harris 
Gerrit-Assignee: Brandon Potter 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Austin Harris 
Gerrit-Reviewer: Brandon Potter 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
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Re: [gem5-dev] gem5.opt => opt/gem5?

[Jason Lowe-Power]

Hey Gabe,

I don't have any strong feelings on this, just a couple of points.

1) I think we should support "backwards compatibility" if we do this by
having symlinks from the old names to the new names. This way we don't
break all of the scripts people have been using.
2) How much effort is this and would it be better worth your time to
replace SCons with a better build system (e.g., cmake or bazel)?
Additionally, a lot of our build headaches stem from the high level of
coupling between all of the source directories which makes it impossible to
build a subset of gem5 into a library. Would it make sense to tackle this
instead of shoehorning it into SCons?

I don't mean to discourage you from taking our current system and making it
incrementally better!

Cheers,
Jason

On Tue, Nov 21, 2017 at 6:01 AM Andreas Sandberg 
wrote:

> Hi Gabe,
>
> I can definitely see the reasoning behind this. I think revisiting this
> is a good idea. However, I'm a bit reluctant since it affects a lot of
> existing build scripts and test infrastructure.
>
> Another benefit that you didn't mention is that this avoid some annoying
> "issues" when the build system runs tests. We currently run tests using
> the build/ARM/tests/opt/** targets. This would all become consistent
> with the rest of the build system.
>
> Another change we should consider making while we are doing this is to
> swap architecture and optimisation levels. The opt Arm target would then
> become build/opt/ARM/gem5.opt. That would be a lot nicer for code (e.g.,
> libraries) that we share between different targets. Ideally, we should
> only rebuild the src/cpu and src/arch/ directories when switching
> targets, but that's a more ambitious goal.
>
> Cheers,
> Andreas
>
>
> On 21/11/2017 05:28, Gabe Black wrote:
> > Hi folks. I've been digging around in the scons files, and I was thinking
> > about the possibility of treating opt, fast, debug, etc., as actual
> > variants from the scons perspective instead of having them all live in
> the
> > same directory but with different extensions. I think the biggest
> > difference this might make is that, for instance, the opt version of the
> > gem5 X86 binary would be build/X86/opt/gem5 and not build/X86/gem5.opt.
> >
> > There wouldn't be any amazing direct benefit from doing things that way
> > that I can see at the moment, but it would make our build structure fit a
> > little more naturally into the way scons wants to do things. It might
> also
> > make it more feasible to use real scons builders for things like Source,
> > etc., instead of wrapper classes. Another benefit would be if you wanted
> to
> > compile all the files in a particular part of the source tree (like the
> > unit tests, although those shouldn't be lumped together anyway), you
> could
> > just give scons the path and it wouldn't build all possible versions of
> the
> > sources in that directory, just the one in the variant you gave it. Using
> > the unit tests as an example, you could run 'scons
> build/ARM/opt/unittest'
> > and get the opt versions of all the unit tests.
> >
> > Any objections?
> >
> > Gabe
> > ___
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> > gem5-dev@gem5.org
> > http://m5sim.org/mailman/listinfo/gem5-dev
>
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[gem5-dev] Change in public/gem5[master]: scons: Build error introduced by site_tools/default.py

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/5941 )


Change subject: scons: Build error introduced by site_tools/default.py
..

scons: Build error introduced by site_tools/default.py

One of the latest commits affecting the build system introduced a change
in the environment setting: rather than using the ENV dictionary,
environment key-val pairs were saved directly into the class. This
patch reverts that behaviour.

Change-Id: If206ba0a34ac8c35695a493cb90654b7ec81971b
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/5941
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
---
M site_scons/site_tools/default.py
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/site_scons/site_tools/default.py  
b/site_scons/site_tools/default.py

index 73c4a9e..9d02ab7 100644
--- a/site_scons/site_tools/default.py
+++ b/site_scons/site_tools/default.py
@@ -64,7 +64,7 @@
 for key,val in sorted(os.environ.iteritems()):
 if key in use_vars or \
 any([key.startswith(prefix) for prefix in use_prefixes]):
-env[key] = val
+env['ENV'][key] = val

 # Tell scons to avoid implicit command dependencies to avoid issues
 # with the param wrappes being compiled twice (see

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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: If206ba0a34ac8c35695a493cb90654b7ec81971b
Gerrit-Change-Number: 5941
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-CC: Gabe Black 
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[gem5-dev] Change in public/gem5[master]: arch-arm: Fix MSR/MRS disassemble

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/5861 )


Change subject: arch-arm: Fix MSR/MRS disassemble
..

arch-arm: Fix MSR/MRS disassemble

This patch is fixing the Aarch64 MSR/MRS disassemble, which was
previously printing unexisting integer registers as source/destination
operands rather than the system register name

Change-Id: Iac9d5f2f2fea85abd9a398320ef7aa4844d43c0e
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Nikos Nikoleris 
Reviewed-on: https://gem5-review.googlesource.com/5861
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
---
M src/arch/arm/insts/misc64.cc
M src/arch/arm/insts/misc64.hh
M src/arch/arm/isa/formats/aarch64.isa
M src/arch/arm/isa/insts/data64.isa
M src/arch/arm/isa/templates/misc64.isa
5 files changed, 132 insertions(+), 13 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc
index 465bafa..b40de02 100644
--- a/src/arch/arm/insts/misc64.cc
+++ b/src/arch/arm/insts/misc64.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2013 ARM Limited
+ * Copyright (c) 2011-2013,2017 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -53,7 +53,7 @@

 std::string
 RegRegRegImmOp64::generateDisassembly(
-Addr pc, const SymbolTable *symtab) const
+Addr pc, const SymbolTable *symtab) const
 {
 std::stringstream ss;
 printMnemonic(ss, "", false);
@@ -71,3 +71,27 @@
 {
 return csprintf("%-10s (inst %#08x)", "unknown", machInst);
 }
+
+std::string
+MiscRegRegImmOp64::generateDisassembly(
+Addr pc, const SymbolTable *symtab) const
+{
+std::stringstream ss;
+printMnemonic(ss);
+printMiscReg(ss, dest);
+ss << ", ";
+printIntReg(ss, op1);
+return ss.str();
+}
+
+std::string
+RegMiscRegImmOp64::generateDisassembly(
+Addr pc, const SymbolTable *symtab) const
+{
+std::stringstream ss;
+printMnemonic(ss);
+printIntReg(ss, dest);
+ss << ", ";
+printMiscReg(ss, op1);
+return ss.str();
+}
diff --git a/src/arch/arm/insts/misc64.hh b/src/arch/arm/insts/misc64.hh
index 5a0e182..384d946 100644
--- a/src/arch/arm/insts/misc64.hh
+++ b/src/arch/arm/insts/misc64.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2013 ARM Limited
+ * Copyright (c) 2011-2013,2017 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -89,4 +89,38 @@
 std::string generateDisassembly(Addr pc, const SymbolTable *symtab)  
const;

 };

+class MiscRegRegImmOp64 : public ArmStaticInst
+{
+  protected:
+MiscRegIndex dest;
+IntRegIndex op1;
+uint32_t imm;
+
+MiscRegRegImmOp64(const char *mnem, ExtMachInst _machInst,
+  OpClass __opClass, MiscRegIndex _dest,
+  IntRegIndex _op1, uint32_t _imm) :
+ArmStaticInst(mnem, _machInst, __opClass),
+dest(_dest), op1(_op1), imm(_imm)
+{}
+
+std::string generateDisassembly(Addr pc, const SymbolTable *symtab)  
const;

+};
+
+class RegMiscRegImmOp64 : public ArmStaticInst
+{
+  protected:
+IntRegIndex dest;
+MiscRegIndex op1;
+uint32_t imm;
+
+RegMiscRegImmOp64(const char *mnem, ExtMachInst _machInst,
+  OpClass __opClass, IntRegIndex _dest,
+  MiscRegIndex _op1, uint32_t _imm) :
+ArmStaticInst(mnem, _machInst, __opClass),
+dest(_dest), op1(_op1), imm(_imm)
+{}
+
+std::string generateDisassembly(Addr pc, const SymbolTable *symtab)  
const;

+};
+
 #endif
diff --git a/src/arch/arm/isa/formats/aarch64.isa  
b/src/arch/arm/isa/formats/aarch64.isa

index 2c33e24..d640caf 100644
--- a/src/arch/arm/isa/formats/aarch64.isa
+++ b/src/arch/arm/isa/formats/aarch64.isa
@@ -369,12 +369,13 @@
 return new Dczva(machInst, rt, (IntRegIndex)  
miscReg, iss);


 if (read) {
-StaticInstPtr si = new Mrs64(machInst, rt,  
(IntRegIndex) miscReg, iss);
+StaticInstPtr si = new Mrs64(machInst, rt,  
miscReg, iss);

 if (miscRegInfo[miscReg][MISCREG_UNVERIFIABLE])
 si->setFlag(StaticInst::IsUnverifiable);
 return si;
-} else
-return new Msr64(machInst, (IntRegIndex)  
miscReg, rt, iss);

+} else {
+return new Msr64(machInst, miscReg, rt, iss);
+}
 } else 

[gem5-dev] Change in public/gem5[master]: arch-arm: Fix MCR/MRC disassemble

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/5862 )


Change subject: arch-arm: Fix MCR/MRC disassemble
..

arch-arm: Fix MCR/MRC disassemble

This patch is fixing the Aarch32 MCR/MRC disassemble, which was
previously printing unexisting integer registers as source/destination
operands rather than the coprocessor register name

Change-Id: I1937938c43680200cf6c5c9558e835ce2b209adc
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Nikos Nikoleris 
Reviewed-on: https://gem5-review.googlesource.com/5862
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
---
M src/arch/arm/insts/misc.cc
1 file changed, 2 insertions(+), 4 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc
index 059f86f..ec1b935 100644
--- a/src/arch/arm/insts/misc.cc
+++ b/src/arch/arm/insts/misc.cc
@@ -259,10 +259,9 @@
 {
 std::stringstream ss;
 printMnemonic(ss);
-printIntReg(ss, dest);
+printMiscReg(ss, dest);
 ss << ", ";
 printIntReg(ss, op1);
-ccprintf(ss, ", #%d", imm);
 return ss.str();
 }

@@ -273,8 +272,7 @@
 printMnemonic(ss);
 printIntReg(ss, dest);
 ss << ", ";
-printIntReg(ss, op1);
-ccprintf(ss, ", #%d", imm);
+printMiscReg(ss, op1);
 return ss.str();
 }


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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I1937938c43680200cf6c5c9558e835ce2b209adc
Gerrit-Change-Number: 5862
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nikos Nikoleris 
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Re: [gem5-dev] SPARC cls and statute of limitation on reviews

[Andreas Sandberg]

Hi Gabe,

I won't have time to review them anytime soon. Since only Jason has
offered to review some of them, I'd suggest that we go for a more
relaxed review policy for SPARC. I would be happy for you to self
approve these changes since you are the SPARC maintainer and there are
no other obvious reviewers.

Cheers,
Andreas


On 18/11/2017 01:45, Jason Lowe-Power wrote:

Hey Gabe,

I'll *try* to find some time this weekend to skim them. I'll aim for giving
at least +1, after which I'm fine with you taking responsibility for any
bugs and pushing :).

I'll also try to catch up on all of the gem5 things that have been flying
past my inbox. We'll see how that goes, though.

Cheers,
Jason

---
Jason Lowe-Power
Assistant Professor, Computer Science Department
University of California, Davis
3049 Kemper Hall
https://faculty.engineering.ucdavis.edu/lowepower/


On Fri, Nov 17, 2017 at 3:39 PM Gabe Black  wrote:


Hi folks. I have a series of CLs for the SPARC ISA (
https://gem5-review.googlesource.com/c/public/gem5/+/5421/2, etc.) which
haven'b gotten reviews in a while. I realize there may not be anyone to
jump in and review SPARC changes, and I even chose to tinker with SPARC
since it's a relatively quite corner where I'm not likely to disrupt
anybody.

I do, however, want to get those changes checked in at some point. Does
anyone want to review them? Is there a point where there's been enough time
for anybody who was sufficiently motivated to look at them, and I can go
ahead and check them in unreviewed?

Gabe
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Re: [gem5-dev] gem5.opt => opt/gem5?

[Andreas Sandberg]

Hi Gabe,

I can definitely see the reasoning behind this. I think revisiting this
is a good idea. However, I'm a bit reluctant since it affects a lot of
existing build scripts and test infrastructure.

Another benefit that you didn't mention is that this avoid some annoying
"issues" when the build system runs tests. We currently run tests using
the build/ARM/tests/opt/** targets. This would all become consistent
with the rest of the build system.

Another change we should consider making while we are doing this is to
swap architecture and optimisation levels. The opt Arm target would then
become build/opt/ARM/gem5.opt. That would be a lot nicer for code (e.g.,
libraries) that we share between different targets. Ideally, we should
only rebuild the src/cpu and src/arch/ directories when switching
targets, but that's a more ambitious goal.

Cheers,
Andreas


On 21/11/2017 05:28, Gabe Black wrote:

Hi folks. I've been digging around in the scons files, and I was thinking
about the possibility of treating opt, fast, debug, etc., as actual
variants from the scons perspective instead of having them all live in the
same directory but with different extensions. I think the biggest
difference this might make is that, for instance, the opt version of the
gem5 X86 binary would be build/X86/opt/gem5 and not build/X86/gem5.opt.

There wouldn't be any amazing direct benefit from doing things that way
that I can see at the moment, but it would make our build structure fit a
little more naturally into the way scons wants to do things. It might also
make it more feasible to use real scons builders for things like Source,
etc., instead of wrapper classes. Another benefit would be if you wanted to
compile all the files in a particular part of the source tree (like the
unit tests, although those shouldn't be lumped together anyway), you could
just give scons the path and it wouldn't build all possible versions of the
sources in that directory, just the one in the variant you gave it. Using
the unit tests as an example, you could run 'scons build/ARM/opt/unittest'
and get the opt versions of all the unit tests.

Any objections?

Gabe
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[gem5-dev] Change in public/gem5[master]: cpu-o3: Prevent cpu from suspending if it is already draining

[Nikos Nikoleris (Gerrit)]

Nikos Nikoleris has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/5881 )


Change subject: cpu-o3: Prevent cpu from suspending if it is already  
draining

..

cpu-o3: Prevent cpu from suspending if it is already draining

Suspending the current thread context while draining due to a quiesce
pseudo instruction (for example a wfi instruction) could deadlock the
cpu and prevent it from successfully draining. This change ensures
that the cpu is not draining before suspending the thread context.

Change-Id: I7c019847f5a870d4bc9ce2b19936bc3dc45e5fd7
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/5881
Reviewed-by: Jason Lowe-Power 
Maintainer: Andreas Sandberg 
---
M src/cpu/o3/thread_context_impl.hh
1 file changed, 6 insertions(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/cpu/o3/thread_context_impl.hh  
b/src/cpu/o3/thread_context_impl.hh

index fdaa351..d9f84fb 100755
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2012, 2016 ARM Limited
+ * Copyright (c) 2010-2012, 2016-2017 ARM Limited
  * Copyright (c) 2013 Advanced Micro Devices, Inc.
  * All rights reserved
  *
@@ -109,6 +109,11 @@
 if (thread->status() == ThreadContext::Suspended)
 return;

+if (cpu->isDraining()) {
+DPRINTF(O3CPU, "Ignoring suspend on TC due to pending drain\n");
+return;
+}
+
 thread->lastActivate = curTick();
 thread->lastSuspend = curTick();


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Gerrit-Change-Number: 5881
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Gerrit-Owner: Nikos Nikoleris 
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[gem5-dev] Change in public/gem5[master]: scons: Build error introduced by site_tools/default.py

[Giacomo Travaglini (Gerrit)]

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/5941



Change subject: scons: Build error introduced by site_tools/default.py
..

scons: Build error introduced by site_tools/default.py

One of the latest commits affecting the build system introduced a change
in the environment setting: rather than using the ENV dictionary,
environment key-val pairs were saved directly into the class. This
patch reverts that behaviour.

Change-Id: If206ba0a34ac8c35695a493cb90654b7ec81971b
Signed-off-by: Giacomo Travaglini 
---
M site_scons/site_tools/default.py
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/site_scons/site_tools/default.py  
b/site_scons/site_tools/default.py

index 73c4a9e..9d02ab7 100644
--- a/site_scons/site_tools/default.py
+++ b/site_scons/site_tools/default.py
@@ -64,7 +64,7 @@
 for key,val in sorted(os.environ.iteritems()):
 if key in use_vars or \
 any([key.startswith(prefix) for prefix in use_prefixes]):
-env[key] = val
+env['ENV'][key] = val

 # Tell scons to avoid implicit command dependencies to avoid issues
 # with the param wrappes being compiled twice (see

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[gem5-dev] Change in public/gem5[master]: arch-arm: HVC instruction undefined in secure EL1

[Giacomo Travaglini (Gerrit)]

Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/5921

to review the following change.


Change subject: arch-arm: HVC instruction undefined in secure EL1
..

arch-arm: HVC instruction undefined in secure EL1

Since EL2 is not available in secure mode, any HVC call from secure mode
should be treated as undefined. This behaviour was implemented in
aarch32 HVC but not in 64 bit version

Change-Id: Ibaa4d8b1e8fe01d2ba3ef07494c09a4d3e7e87b0
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M src/arch/arm/isa/insts/misc64.isa
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/arch/arm/isa/insts/misc64.isa  
b/src/arch/arm/isa/insts/misc64.isa

index 58f08f5..00724c0 100644
--- a/src/arch/arm/isa/insts/misc64.isa
+++ b/src/arch/arm/isa/insts/misc64.isa
@@ -53,7 +53,7 @@
 SCR scr = Scr64;

 if (!ArmSystem::haveVirtualization(xc->tcBase()) ||
-(ArmSystem::haveSecurity(xc->tcBase()) && !scr.hce)) {
+(ArmSystem::haveSecurity(xc->tcBase()) && (!scr.ns || !scr.hce))) {
 fault = disabledFault();
 } else {
 fault = std::make_shared(machInst, bits(machInst,  
20, 5));


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[gem5-dev] Cron <m5test@zizzer> /z/m5/regression/do-regression quick

[Cron Daemon]

* build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-atomic: FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing: 
FAILED!
* build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-timing-ruby: 
FAILED!
* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/o3-timing: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-timing: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-timing-ruby:
 FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/minor-timing: 
FAILED!* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-atomic: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-timing-ruby:
 FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-atomic: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-timing: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/minor-timing: 
FAILED!
* build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-timing: FAILED!
* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/o3-timing: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/minor-timing: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-timing: 
FAILED!
* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/o3-timing: 
FAILED!
* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/o3-timing: 
FAILED!
* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/o3-timing: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-timing: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-atomic: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing-ruby:
 FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-timing-ruby:
 FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/simple-timing: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-timing-ruby:
 FAILED!
* build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/minor-timing: FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/minor-timing: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/minor-timing: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/simple-timing-ruby:
 FAILED!
* build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/o3-timing: FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/simple-atomic: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/minor-timing: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-atomic: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-atomic: 
FAILED!
* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/o3-timing: 
FAILED!
* 
build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple:
 CHANGED!
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing: CHANGED!
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing: CHANGED!
* 
build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level:
 CHANGED!
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic: 
CHANGED!
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual:
 CHANGED!
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual:
 CHANGED!
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing: 
CHANGED!
* 
build/NULL_MOESI_hammer/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_hammer:
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build/NULL_MESI_Two_Level/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MESI_Two_Level:
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* 
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* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby: 
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build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple:
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build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level:
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* build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing: CHANGED!
* 
build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple:
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* 
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*