[gem5-dev] Change in gem5/gem5[develop]: arch,base,mem,sim: Fix style in base/types.hh and remove extra includes.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39855 )



Change subject: arch,base,mem,sim: Fix style in base/types.hh and remove  
extra includes.

..

arch,base,mem,sim: Fix style in base/types.hh and remove extra includes.

The base/refcnt.hh header was not used in base/types.hh at all, and
enum/ByteOrder.hh was there just so other files could find it. Instead,
this change moves enum/Byteorder.hh to sim/byteswap.hh where it's fits
with the purpose of the header.

This change also fixes some style problems with the code in
base/types.hh itself.

Change-Id: I471ae5cb2cca9169ba8616fb8411b40108a3ffb2
---
M src/arch/arm/freebsd/freebsd.hh
M src/arch/arm/isa_traits.hh
M src/arch/mips/isa_traits.hh
M src/arch/power/isa_traits.hh
M src/arch/riscv/isa_traits.hh
M src/arch/sparc/isa_traits.hh
M src/arch/sparc/solaris/solaris.hh
M src/arch/x86/isa_traits.hh
M src/base/pixel.hh
M src/base/types.hh
M src/mem/packet.hh
M src/sim/byteswap.hh
12 files changed, 36 insertions(+), 19 deletions(-)



diff --git a/src/arch/arm/freebsd/freebsd.hh  
b/src/arch/arm/freebsd/freebsd.hh

index ef9da65..23fa0af 100644
--- a/src/arch/arm/freebsd/freebsd.hh
+++ b/src/arch/arm/freebsd/freebsd.hh
@@ -34,6 +34,7 @@
 #define __ARCH_ARM_FREEBSD_FREEBSD_HH__

 #include "kern/freebsd/freebsd.hh"
+#include "sim/byteswap.hh"

 class ArmFreebsd : public FreeBSD
 {
diff --git a/src/arch/arm/isa_traits.hh b/src/arch/arm/isa_traits.hh
index 798db72..d8ef5e7 100644
--- a/src/arch/arm/isa_traits.hh
+++ b/src/arch/arm/isa_traits.hh
@@ -43,6 +43,7 @@
 #define __ARCH_ARM_ISA_TRAITS_HH__

 #include "base/types.hh"
+#include "sim/byteswap.hh"

 namespace ArmISA
 {
diff --git a/src/arch/mips/isa_traits.hh b/src/arch/mips/isa_traits.hh
index aac595a..cf83d74 100644
--- a/src/arch/mips/isa_traits.hh
+++ b/src/arch/mips/isa_traits.hh
@@ -31,6 +31,7 @@
 #define __ARCH_MIPS_ISA_TRAITS_HH__

 #include "base/types.hh"
+#include "sim/byteswap.hh"

 namespace MipsISA
 {
diff --git a/src/arch/power/isa_traits.hh b/src/arch/power/isa_traits.hh
index 4cf0c44..fd230eb 100644
--- a/src/arch/power/isa_traits.hh
+++ b/src/arch/power/isa_traits.hh
@@ -32,6 +32,7 @@
 #define __ARCH_POWER_ISA_TRAITS_HH__

 #include "base/types.hh"
+#include "sim/byteswap.hh"

 namespace PowerISA
 {
diff --git a/src/arch/riscv/isa_traits.hh b/src/arch/riscv/isa_traits.hh
index 4cf455d..ee6d8f7 100644
--- a/src/arch/riscv/isa_traits.hh
+++ b/src/arch/riscv/isa_traits.hh
@@ -43,6 +43,7 @@
 #define __ARCH_RISCV_ISA_TRAITS_HH__

 #include "base/types.hh"
+#include "sim/byteswap.hh"

 namespace RiscvISA
 {
diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh
index 3f7cdac..c1690dd 100644
--- a/src/arch/sparc/isa_traits.hh
+++ b/src/arch/sparc/isa_traits.hh
@@ -30,6 +30,7 @@
 #define __ARCH_SPARC_ISA_TRAITS_HH__

 #include "base/types.hh"
+#include "sim/byteswap.hh"

 namespace SparcISA
 {
diff --git a/src/arch/sparc/solaris/solaris.hh  
b/src/arch/sparc/solaris/solaris.hh

index 0462832..7a5aaaf 100644
--- a/src/arch/sparc/solaris/solaris.hh
+++ b/src/arch/sparc/solaris/solaris.hh
@@ -30,6 +30,7 @@
 #define __ARCH_SPARC_SOLARIS_SOLARIS_HH__

 #include "kern/solaris/solaris.hh"
+#include "sim/byteswap.hh"

 class SparcSolaris : public Solaris
 {
diff --git a/src/arch/x86/isa_traits.hh b/src/arch/x86/isa_traits.hh
index dee98dc..befadab 100644
--- a/src/arch/x86/isa_traits.hh
+++ b/src/arch/x86/isa_traits.hh
@@ -39,6 +39,7 @@
 #define __ARCH_X86_ISATRAITS_HH__

 #include "base/types.hh"
+#include "sim/byteswap.hh"

 namespace X86ISA
 {
diff --git a/src/base/pixel.hh b/src/base/pixel.hh
index 7937e89..3cca761 100644
--- a/src/base/pixel.hh
+++ b/src/base/pixel.hh
@@ -47,6 +47,7 @@
 #include "base/cprintf.hh"
 #include "base/str.hh"
 #include "base/types.hh"
+#include "sim/byteswap.hh"

 /**
  * Internal gem5 representation of a Pixel.
diff --git a/src/base/types.hh b/src/base/types.hh
index 7ae573d..0b93073 100644
--- a/src/base/types.hh
+++ b/src/base/types.hh
@@ -42,10 +42,6 @@
 #include 
 #include 

-#include "base/refcnt.hh"
-/* Hide the fact that this enum is generated by Python */
-#include "enums/ByteOrder.hh"
-
 /** uint64_t constant */
 #define ULL(N)  ((uint64_t)N##ULL)
 /** int64_t constant */
@@ -100,35 +96,45 @@
 constexpr operator uint64_t() const { return c; }

 /** Prefix increment operator. */
-Cycles& operator++()
-{ ++c; return *this; }
+Cycles& operator++() { ++c; return *this; }

 /** Prefix decrement operator. Is only temporarily used in the O3 CPU.  
*/

-Cycles& operator--()
-{ assert(c != 0); --c; return *this; }
+Cycles& operator--() { assert(c != 0); --c; return *this; }

 /** In-place addition of cycles. */
-Cycles& operator+=(const Cycles& cc)
-{ c += cc.c; return *this; }
+Cycles& operator+=(const Cycles& cc) { c += cc.c; return *this; }

 /** Greater than comp

[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Delete some unused register related constants.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39677 )


Change subject: arch-x86: Delete some unused register related constants.
..

arch-x86: Delete some unused register related constants.

Change-Id: Id5305a863675061b4afb27c71b329180605381b5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39677
Reviewed-by: Bobby R. Bruce 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M src/arch/x86/registers.hh
1 file changed, 0 insertions(+), 8 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/x86/registers.hh b/src/arch/x86/registers.hh
index c041a07..fdd6d6b 100644
--- a/src/arch/x86/registers.hh
+++ b/src/arch/x86/registers.hh
@@ -83,14 +83,6 @@
 //There is no such register in X86
 const int ZeroReg = NUM_INTREGS;
 const int StackPointerReg = INTREG_RSP;
-//X86 doesn't seem to have a link register
-const int ReturnAddressReg = 0;
-const int ReturnValueReg = INTREG_RAX;
-const int FramePointerReg = INTREG_RBP;
-
-// Some OS syscalls use a second register (rdx) to return a second
-// value
-const int SyscallPseudoReturnReg = INTREG_RDX;

 // Not applicable to x86
 using VecElem = ::DummyVecElem;

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id5305a863675061b4afb27c71b329180605381b5
Gerrit-Change-Number: 39677
Gerrit-PatchSet: 3
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: sim: Move cur tick to its own files

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39835 )



Change subject: sim: Move cur tick to its own files
..

sim: Move cur tick to its own files

When declared within sim/core.hh, unit tests that use the
current tick would have to unnecessarily include many other
extra files.

Change-Id: Ib4348312afb90765edb4f94c80785df1275b2004
Signed-off-by: Daniel R. Carvalho 
---
M src/sim/SConscript
M src/sim/core.cc
M src/sim/core.hh
A src/sim/cur_tick.cc
A src/sim/cur_tick.hh
5 files changed, 85 insertions(+), 19 deletions(-)



diff --git a/src/sim/SConscript b/src/sim/SConscript
index 78d9bf5..fe18d24 100644
--- a/src/sim/SConscript
+++ b/src/sim/SConscript
@@ -44,6 +44,7 @@
 Source('async.cc')
 Source('backtrace_%s.cc' % env['BACKTRACE_IMPL'])
 Source('core.cc')
+Source('cur_tick.cc')
 Source('tags.cc')
 Source('cxx_config.cc')
 Source('cxx_manager.cc')
diff --git a/src/sim/core.cc b/src/sim/core.cc
index 928e6c8..baa56ab 100644
--- a/src/sim/core.cc
+++ b/src/sim/core.cc
@@ -37,14 +37,6 @@
 #include "base/cprintf.hh"
 #include "base/logging.hh"
 #include "base/output.hh"
-#include "sim/eventq.hh"
-
-namespace Gem5Internal
-{
-
-__thread Tick *_curTickPtr;
-
-} // namespace Gem5Internal

 namespace SimClock {
 /// The simulated frequency of curTick(). (In ticks per second)
diff --git a/src/sim/core.hh b/src/sim/core.hh
index c592049..30c8949 100644
--- a/src/sim/core.hh
+++ b/src/sim/core.hh
@@ -39,17 +39,9 @@
 #include 

 #include "base/types.hh"
-
-namespace Gem5Internal
-{
-
-// This pointer is maintained by curEventQueue in src/sim/eventq.hh.
-extern __thread Tick *_curTickPtr;
-
-} // namespace Gem5Internal
-
-/// The universal simulation clock.
-inline Tick curTick() { return *Gem5Internal::_curTickPtr; }
+// @todo The next include is not needed in this file, but must be kept
+// until the transitive includes are fixed
+#include "sim/cur_tick.hh"

 /// These are variables that are set based on the simulator frequency
 ///@{
diff --git a/src/sim/cur_tick.cc b/src/sim/cur_tick.cc
new file mode 100644
index 000..630a7fb
--- /dev/null
+++ b/src/sim/cur_tick.cc
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2021 Daniel R. Carvalho
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "sim/cur_tick.hh"
+
+namespace Gem5Internal
+{
+
+__thread Tick *_curTickPtr;
+
+} // namespace Gem5Internal
diff --git a/src/sim/cur_tick.hh b/src/sim/cur_tick.hh
new file mode 100644
index 000..0aee611
--- /dev/null
+++ b/src/sim/cur_tick.hh
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2021 Daniel R. Carvalho
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED 

[gem5-dev] Change in gem5/gem5[develop]: base,tests: Add a basic mock class to handle curTick

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39836 )



Change subject: base,tests: Add a basic mock class to handle curTick
..

base,tests: Add a basic mock class to handle curTick

Add this basic mock class that handles the initialization
and update of the current tick.

Change-Id: Iba8ecc049acdd097caa4d9cf05ac8d78bbaf03cc
Signed-off-by: Daniel R. Carvalho 
---
A src/base/gtest/cur_tick_mock.hh
1 file changed, 48 insertions(+), 0 deletions(-)



diff --git a/src/base/gtest/cur_tick_mock.hh  
b/src/base/gtest/cur_tick_mock.hh

new file mode 100644
index 000..5afe2a3
--- /dev/null
+++ b/src/base/gtest/cur_tick_mock.hh
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2021 Daniel R. Carvalho
+ * All rights reserved
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "base/types.hh"
+#include "sim/cur_tick.hh"
+
+namespace {
+
+class GTestTickHandler
+{
+  public:
+GTestTickHandler()
+{
+if (Gem5Internal::_curTickPtr == nullptr) {
+Gem5Internal::_curTickPtr = new Tick(0);
+}
+}
+
+/** Assign a value to the current simulation tick. */
+void setCurTick(Tick tick) { *Gem5Internal::_curTickPtr = tick; }
+};
+
+} // anonymous namespace

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iba8ecc049acdd097caa4d9cf05ac8d78bbaf03cc
Gerrit-Change-Number: 39836
Gerrit-PatchSet: 1
Gerrit-Owner: Daniel Carvalho 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: systemc: set Gem5ToTlmBridge blockingRrequest with TLM_UPDATE returning

[Yu-hsin Wang (Gerrit) via gem5-dev]

Yu-hsin Wang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39815 )



Change subject: systemc: set Gem5ToTlmBridge blockingRrequest with  
TLM_UPDATE returning

..

systemc: set Gem5ToTlmBridge blockingRrequest with TLM_UPDATE returning

In Gem5ToTlmBridge::pec, the function expects blockingRequest should be
set no matter the tlm peer returns TLM_UPDATE or TLM_ACCEPTED.
However, current implementation only sets blockingRequest when the tlm
peer returns TLM_ACCEPTED. We should also set blockingRequest when the
tlm peer returns TLM_UPDATE.

Change-Id: I87bba3201cd68d52ded93c9c200f4fa4a40bdf5b
---
M src/systemc/tlm_bridge/gem5_to_tlm.cc
1 file changed, 2 insertions(+), 0 deletions(-)



diff --git a/src/systemc/tlm_bridge/gem5_to_tlm.cc  
b/src/systemc/tlm_bridge/gem5_to_tlm.cc

index f03548c..fa07ca7 100644
--- a/src/systemc/tlm_bridge/gem5_to_tlm.cc
+++ b/src/systemc/tlm_bridge/gem5_to_tlm.cc
@@ -368,6 +368,8 @@
 } else if (status == tlm::TLM_UPDATED) {
 // The Timing annotation must be honored:
 sc_assert(phase == tlm::END_REQ || phase == tlm::BEGIN_RESP);
+// Accepted but is now blocking until END_REQ (exclusion rule).
+blockingRequest = trans;
 auto cb = [this, trans, phase]() { pec(*trans, phase); };
 system->schedule(new EventFunctionWrapper(cb, "pec", true),
  curTick() + delay.value());

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I87bba3201cd68d52ded93c9c200f4fa4a40bdf5b
Gerrit-Change-Number: 39815
Gerrit-PatchSet: 1
Gerrit-Owner: Yu-hsin Wang 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-mips: Delete unused register related constants.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39679 )


Change subject: arch-mips: Delete unused register related constants.
..

arch-mips: Delete unused register related constants.

Change-Id: If14aa686eda59ff9c148371b4b7f6075b2abd1d8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39679
Maintainer: Bobby R. Bruce 
Reviewed-by: Bobby R. Bruce 
Tested-by: kokoro 
---
M src/arch/mips/registers.hh
1 file changed, 0 insertions(+), 8 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/mips/registers.hh b/src/arch/mips/registers.hh
index aaebf35..0a78008 100644
--- a/src/arch/mips/registers.hh
+++ b/src/arch/mips/registers.hh
@@ -106,17 +106,11 @@

 // semantically meaningful register indices
 const int ZeroReg = 0;
-const int AssemblerReg = 1;
 const int SyscallSuccessReg = 7;
 const int FirstArgumentReg = 4;
 const int ReturnValueReg = 2;

-const int KernelReg0 = 26;
-const int KernelReg1 = 27;
-const int GlobalPointerReg = 28;
 const int StackPointerReg = 29;
-const int FramePointerReg = 30;
-const int ReturnAddressReg = 31;

 const int SyscallPseudoReturnReg = 3;

@@ -279,8 +273,6 @@

 const int NumMiscRegs = MISCREG_NUMREGS;

-const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
-
 // Not applicable to MIPS
 using VecElem = ::DummyVecElem;
 using VecReg = ::DummyVecReg;

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If14aa686eda59ff9c148371b4b7f6075b2abd1d8
Gerrit-Change-Number: 39679
Gerrit-PatchSet: 4
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: cpu: Style fixes in cpu/reg_class.hh.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39676 )


Change subject: cpu: Style fixes in cpu/reg_class.hh.
..

cpu: Style fixes in cpu/reg_class.hh.

Change-Id: Ie8815c6351609dc9fba9d485e9496b7f7c8ce927
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39676
Reviewed-by: Bobby R. Bruce 
Reviewed-by: Daniel Carvalho 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M src/cpu/reg_class.hh
1 file changed, 44 insertions(+), 35 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/cpu/reg_class.hh b/src/cpu/reg_class.hh
index 356caf3..d48e700 100644
--- a/src/cpu/reg_class.hh
+++ b/src/cpu/reg_class.hh
@@ -72,7 +72,8 @@
  * between different classes of registers. For example, a integer register  
with

  * index 3 is represented by Regid(IntRegClass, 3).
  */
-class RegId {
+class RegId
+{
   protected:
 static const char* regClassStrings[];
 RegClass regClass;
@@ -91,7 +92,8 @@

 explicit RegId(RegClass reg_class, RegIndex reg_idx, ElemIndex  
elem_idx)

 : regClass(reg_class), regIdx(reg_idx), elemIdx(elem_idx),
-  numPinnedWrites(0) {
+  numPinnedWrites(0)
+{
 if (elemIdx == ILLEGAL_ELEM_INDEX) {
 panic_if(regClass == VecElemClass,
 "Creating vector physical index w/o element index");
@@ -101,19 +103,21 @@
 }
 }

-bool operator==(const RegId& that) const {
-return regClass == that.classValue() && regIdx == that.index()
- && elemIdx ==  
that.elemIndex();

+bool
+operator==(const RegId& that) const
+{
+return regClass == that.classValue() && regIdx == that.index() &&
+elemIdx == that.elemIndex();
 }

-bool operator!=(const RegId& that) const {
-return !(*this==that);
-}
+bool operator!=(const RegId& that) const { return !(*this==that); }

 /** Order operator.
  * The order is required to implement maps with key type RegId
  */
-bool operator<(const RegId& that) const {
+bool
+operator<(const RegId& that) const
+{
 return regClass < that.classValue() ||
 (regClass == that.classValue() && (
regIdx < that.index() ||
@@ -123,7 +127,8 @@
 /**
  * Return true if this register can be renamed
  */
-bool isRenameable() const
+bool
+isRenameable() const
 {
 return regClass != MiscRegClass;
 }
@@ -134,7 +139,8 @@
  * constant zero value throughout the execution).
  */

-inline bool isZeroReg() const
+inline bool
+isZeroReg() const
 {
 return regClass == IntRegClass && regIdx == TheISA::ZeroReg;
 }
@@ -160,14 +166,6 @@
 /** @Return true if it is a  condition-code physical register. */
 bool isMiscReg() const { return regClass == MiscRegClass; }

-/**
- * Return true if this register can be renamed
- */
-bool isRenameable()
-{
-return regClass != MiscRegClass;
-}
-
 /** Index accessors */
 /** @{ */
 const RegIndex& index() const { return regIdx; }
@@ -176,7 +174,8 @@
 /** Index flattening.
  * Required to be able to use a vector for the register mapping.
  */
-inline RegIndex flatIndex() const
+inline RegIndex
+flatIndex() const
 {
 switch (regClass) {
   case IntRegClass:
@@ -187,7 +186,7 @@
   case MiscRegClass:
 return regIdx;
   case VecElemClass:
-return Scale*regIdx + elemIdx;
+return Scale * regIdx + elemIdx;
 }
 panic("Trying to flatten a register without class!");
 return -1;
@@ -205,7 +204,8 @@
 void setNumPinnedWrites(int num_writes) { numPinnedWrites =  
num_writes; }


 friend std::ostream&
-operator<<(std::ostream& os, const RegId& rid) {
+operator<<(std::ostream& os, const RegId& rid)
+{
 return os << rid.className() << "{" << rid.index() << "}";
 }
 };
@@ -220,7 +220,8 @@
  * Like a register ID but physical. The inheritance is private because the
  * only relationship between this types is functional, and it is done to
  * prevent code replication. */
-class PhysRegId : private RegId {
+class PhysRegId : private RegId
+{
   private:
 PhysRegIndex flatIdx;
 int numPinnedWritesToComplete;
@@ -258,15 +259,21 @@
  * RegIds.
  */
 /** @{ */
-bool operator<(const PhysRegId& that) const {
+bool
+operator<(const PhysRegId& that) const
+{
 return RegId::operator<(that);
 }

-bool operator==(const PhysRegId& that) const {
+bool
+operator==(const PhysRegId& that) const
+{
 return RegId::operator==(that);
 }

-bool operator!=(c

[gem5-dev] Change in gem5/gem5[develop]: base: Make the default checkBpLen method return true.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39661 )


Change subject: base: Make the default checkBpLen method return true.
..

base: Make the default checkBpLen method return true.

This was checking that the breakpoint length was equal to the length of
the ISA specific MachInst type. Instead, force the ISA specific remote
GDB subclass to implement a check if it wants to, specific to its needs.
The base implementation will just approve of any length, which should be
fine with a well behaved GDB client.

Change-Id: Id7325b788f8445049855f8104082b8e4da1fe300
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39661
Reviewed-by: Daniel Carvalho 
Reviewed-by: Bobby R. Bruce 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M src/base/remote_gdb.cc
1 file changed, 1 insertion(+), 2 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, but someone else must approve
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/base/remote_gdb.cc b/src/base/remote_gdb.cc
index 02cb11a..bde1acf 100644
--- a/src/base/remote_gdb.cc
+++ b/src/base/remote_gdb.cc
@@ -141,7 +141,6 @@
 #include "base/intmath.hh"
 #include "base/socket.hh"
 #include "base/trace.hh"
-#include "config/the_isa.hh"
 #include "cpu/base.hh"
 #include "cpu/static_inst.hh"
 #include "cpu/thread_context.hh"
@@ -786,7 +785,7 @@
 bool
 BaseRemoteGDB::checkBpLen(size_t len)
 {
-return len == sizeof(TheISA::MachInst);
+return true;
 }

 bool

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id7325b788f8445049855f8104082b8e4da1fe300
Gerrit-Change-Number: 39661
Gerrit-PatchSet: 4
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: base: Delete the unused RemoteGDB::(set|clear)TempBreakpoint methods.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39660 )


Change subject: base: Delete the unused RemoteGDB::(set| 
clear)TempBreakpoint methods.

..

base: Delete the unused RemoteGDB::(set|clear)TempBreakpoint methods.

These are not used by anything, and use the ISA specific
TheISA::MachInst type.

Change-Id: Iae08e672b00834ccc5f11295b4c4529fbe7f8d0e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39660
Reviewed-by: Bobby R. Bruce 
Reviewed-by: Daniel Carvalho 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M src/base/remote_gdb.cc
M src/base/remote_gdb.hh
2 files changed, 0 insertions(+), 18 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, but someone else must approve
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/base/remote_gdb.cc b/src/base/remote_gdb.cc
index 1e86a69..02cb11a 100644
--- a/src/base/remote_gdb.cc
+++ b/src/base/remote_gdb.cc
@@ -712,21 +712,6 @@
 }

 void
-BaseRemoteGDB::clearTempBreakpoint(Addr &bkpt)
-{
-DPRINTF(GDBMisc, "setTempBreakpoint: addr=%#x\n", bkpt);
-removeHardBreak(bkpt, sizeof(TheISA::MachInst));
-bkpt = 0;
-}
-
-void
-BaseRemoteGDB::setTempBreakpoint(Addr bkpt)
-{
-DPRINTF(GDBMisc, "setTempBreakpoint: addr=%#x\n", bkpt);
-insertHardBreak(bkpt, sizeof(TheISA::MachInst));
-}
-
-void
 BaseRemoteGDB::scheduleInstCommitEvent(Event *ev, int delta)
 {
 // Here "ticks" aren't simulator ticks which measure time, they're
diff --git a/src/base/remote_gdb.hh b/src/base/remote_gdb.hh
index c71abfe..cbfb46f 100644
--- a/src/base/remote_gdb.hh
+++ b/src/base/remote_gdb.hh
@@ -257,9 +257,6 @@
 void insertHardBreak(Addr addr, size_t len);
 void removeHardBreak(Addr addr, size_t len);

-void clearTempBreakpoint(Addr &bkpt);
-void setTempBreakpoint(Addr bkpt);
-
 /*
  * GDB commands.
  */

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iae08e672b00834ccc5f11295b4c4529fbe7f8d0e
Gerrit-Change-Number: 39660
Gerrit-PatchSet: 3
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: cpu: Style fixes in cpu/exec_context.hh and thread_context.hh.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39659 )


Change subject: cpu: Style fixes in cpu/exec_context.hh and  
thread_context.hh.

..

cpu: Style fixes in cpu/exec_context.hh and thread_context.hh.

Change-Id: I2eb82cc6f6ba29c1df74e53b78b57c1a65577837
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39659
Reviewed-by: Daniel Carvalho 
Reviewed-by: Bobby R. Bruce 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M src/cpu/exec_context.hh
M src/cpu/thread_context.hh
2 files changed, 30 insertions(+), 34 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh
index c0b8dcd..42dafbc 100644
--- a/src/cpu/exec_context.hh
+++ b/src/cpu/exec_context.hh
@@ -105,36 +105,35 @@
 /** Vector Register Interfaces. */
 /** @{ */
 /** Reads source vector register operand. */
-virtual const TheISA::VecRegContainer&
-readVecRegOperand(const StaticInst *si, int idx) const = 0;
+virtual const TheISA::VecRegContainer& readVecRegOperand(
+const StaticInst *si, int idx) const = 0;

 /** Gets destination vector register operand for modification. */
-virtual TheISA::VecRegContainer&
-getWritableVecRegOperand(const StaticInst *si, int idx) = 0;
+virtual TheISA::VecRegContainer& getWritableVecRegOperand(
+const StaticInst *si, int idx) = 0;

 /** Sets a destination vector register operand to a value. */
-virtual void
-setVecRegOperand(const StaticInst *si, int idx,
- const TheISA::VecRegContainer& val) = 0;
+virtual void setVecRegOperand(const StaticInst *si, int idx,
+const TheISA::VecRegContainer& val) = 0;
 /** @} */

 /** Vector Register Lane Interfaces. */
 /** @{ */
 /** Reads source vector 8bit operand. */
-virtual ConstVecLane8
-readVec8BitLaneOperand(const StaticInst *si, int idx) const = 0;
+virtual ConstVecLane8 readVec8BitLaneOperand(
+const StaticInst *si, int idx) const = 0;

 /** Reads source vector 16bit operand. */
-virtual ConstVecLane16
-readVec16BitLaneOperand(const StaticInst *si, int idx) const = 0;
+virtual ConstVecLane16 readVec16BitLaneOperand(
+const StaticInst *si, int idx) const = 0;

 /** Reads source vector 32bit operand. */
-virtual ConstVecLane32
-readVec32BitLaneOperand(const StaticInst *si, int idx) const = 0;
+virtual ConstVecLane32 readVec32BitLaneOperand(
+const StaticInst *si, int idx) const = 0;

 /** Reads source vector 64bit operand. */
-virtual ConstVecLane64
-readVec64BitLaneOperand(const StaticInst *si, int idx) const = 0;
+virtual ConstVecLane64 readVec64BitLaneOperand(
+const StaticInst *si, int idx) const = 0;

 /** Write a lane of the destination vector operand. */
 /** @{ */
@@ -225,9 +224,9 @@
  * mode need not override (though in that case this function
  * should never be called).
  */
-virtual Fault readMem(Addr addr, uint8_t *data, unsigned int size,
-Request::Flags flags,
-const std::vector& byte_enable)
+virtual Fault
+readMem(Addr addr, uint8_t *data, unsigned int size,
+Request::Flags flags, const std::vector& byte_enable)
 {
 panic("ExecContext::readMem() should be overridden\n");
 }
@@ -239,9 +238,9 @@
  * mode need not override (though in that case this function
  * should never be called).
  */
-virtual Fault initiateMemRead(Addr addr, unsigned int size,
-Request::Flags flags,
-const std::vector& byte_enable)
+virtual Fault
+initiateMemRead(Addr addr, unsigned int size,
+Request::Flags flags, const std::vector& byte_enable)
 {
 panic("ExecContext::initiateMemRead() should be overridden\n");
 }
@@ -263,9 +262,9 @@
  * For atomic-mode contexts, perform an atomic AMO (a.k.a., Atomic
  * Read-Modify-Write Memory Operation)
  */
-virtual Fault amoMem(Addr addr, uint8_t *data, unsigned int size,
- Request::Flags flags,
- AtomicOpFunctorPtr amo_op)
+virtual Fault
+amoMem(Addr addr, uint8_t *data, unsigned int size,
+Request::Flags flags, AtomicOpFunctorPtr amo_op)
 {
 panic("ExecContext::amoMem() should be overridden\n");
 }
@@ -274,9 +273,9 @@
  * For timing-mode contexts, initiate an atomic AMO (atomic
  * read-modify-write memory operation)
  */
-virtual Fault initiateMemAMO(Addr addr, unsigned int size,
- Request::Flags flags,
- AtomicOpFunctorPtr amo_op)
+virtual Fault
+initiateMemAMO(

[gem5-dev] Change in gem5/gem5[develop]: base,cpu,sim: Stop "using namespace TheISA".

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39655 )


Change subject: base,cpu,sim: Stop "using namespace TheISA".
..

base,cpu,sim: Stop "using namespace TheISA".

This was mostly not used to begin with, but also when it was used, it
would obscure places where there were types, functions, etc, which were
switched between ISAs at compile time, and which would need to be
cleaned up to allow more than one ISA at a time.

Change-Id: Ieb372feff91b7e946b477fb78e54bcd0c2138966
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39655
Reviewed-by: Bobby R. Bruce 
Reviewed-by: Daniel Carvalho 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M src/base/remote_gdb.cc
M src/cpu/checker/cpu.cc
M src/cpu/checker/cpu_impl.hh
M src/cpu/exetrace.cc
M src/cpu/inteltrace.cc
M src/cpu/o3/cpu.cc
M src/cpu/o3/lsq_unit_impl.hh
M src/cpu/simple/atomic.cc
M src/cpu/simple/base.cc
M src/cpu/simple/timing.cc
M src/cpu/thread_context.cc
M src/sim/process.cc
M src/sim/syscall_emul.cc
M src/sim/system.cc
14 files changed, 43 insertions(+), 71 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, but someone else must approve
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/base/remote_gdb.cc b/src/base/remote_gdb.cc
index 0c1215e..1e86a69 100644
--- a/src/base/remote_gdb.cc
+++ b/src/base/remote_gdb.cc
@@ -151,8 +151,6 @@
 #include "sim/full_system.hh"
 #include "sim/system.hh"

-using namespace TheISA;
-
 static const char GDBStart = '$';
 static const char GDBEnd = '#';
 static const char GDBGoodP = '+';
@@ -803,7 +801,7 @@
 bool
 BaseRemoteGDB::checkBpLen(size_t len)
 {
-return len == sizeof(MachInst);
+return len == sizeof(TheISA::MachInst);
 }

 bool
diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc
index 8815530..a9baf88 100644
--- a/src/cpu/checker/cpu.cc
+++ b/src/cpu/checker/cpu.cc
@@ -52,8 +52,6 @@
 #include "params/CheckerCPU.hh"
 #include "sim/full_system.hh"

-using namespace TheISA;
-
 void
 CheckerCPU::init()
 {
diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index 733cf1c..7fe05c6 100644
--- a/src/cpu/checker/cpu_impl.hh
+++ b/src/cpu/checker/cpu_impl.hh
@@ -59,8 +59,6 @@
 #include "sim/sim_object.hh"
 #include "sim/stats.hh"

-using namespace TheISA;
-
 template 
 void
 Checker::advancePC(const Fault &fault)
@@ -200,7 +198,7 @@
 Fault fault = NoFault;

 // maintain $r0 semantics
-thread->setIntReg(ZeroReg, 0);
+thread->setIntReg(TheISA::ZeroReg, 0);

 // Check if any recent PC changes match up with anything we
 // expect to happen.  This is mostly to check if traps or
diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc
index 02ede1a..7bf60e7 100644
--- a/src/cpu/exetrace.cc
+++ b/src/cpu/exetrace.cc
@@ -53,8 +53,6 @@
 #include "debug/FmtTicksOff.hh"
 #include "enums/OpClass.hh"

-using namespace TheISA;
-
 namespace Trace {

 void
@@ -77,7 +75,7 @@
 Addr cur_pc = pc.instAddr();
 Loader::SymbolTable::const_iterator it;
 ccprintf(outs, "%#x", cur_pc);
-if (Debug::ExecSymbol && (!FullSystem || !inUserMode(thread)) &&
+if (Debug::ExecSymbol && (!FullSystem || !TheISA::inUserMode(thread))  
&&

 (it = Loader::debugSymbolTable.findNearest(cur_pc)) !=
 Loader::debugSymbolTable.end()) {
 Addr delta = cur_pc - it->address;
diff --git a/src/cpu/inteltrace.cc b/src/cpu/inteltrace.cc
index 4e36a9d..2212dbf 100644
--- a/src/cpu/inteltrace.cc
+++ b/src/cpu/inteltrace.cc
@@ -34,8 +34,6 @@
 #include "cpu/exetrace.hh"
 #include "cpu/static_inst.hh"

-using namespace TheISA;
-
 namespace Trace {

 void
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 56cf46c..c84f89b 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -64,8 +64,6 @@

 struct BaseCPUParams;

-using namespace TheISA;
-
 BaseO3CPU::BaseO3CPU(const BaseCPUParams ¶ms)
 : BaseCPU(params)
 {
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index 2c6a16c..d811480 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -610,7 +610,6 @@
 Fault
 LSQUnit::executeLoad(const DynInstPtr &inst)
 {
-using namespace TheISA;
 // Execute a specific load.
 Fault load_fault = NoFault;

@@ -678,7 +677,6 @@
 Fault
 LSQUnit::executeStore(const DynInstPtr &store_inst)
 {
-using namespace TheISA;
 // Make sure that a store exists.
 assert(stores != 0);

diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index ae4ffec..f0c276b 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -58,8 +58,6 @@
 #include "sim/full_system.hh"
 #include "sim/system.hh"

-using namespace TheISA;
-
 void
 AtomicSimpleCPU::init()
 {
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 113f8e6..62df848 100644
--- a/src/cpu/simple/ba

[gem5-dev] Change in gem5/gem5[develop]: dev: Set the "status" field of the HDLCD device tree node to "ok".

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/37936 )


Change subject: dev: Set the "status" field of the HDLCD device tree node  
to "ok".

..

dev: Set the "status" field of the HDLCD device tree node to "ok".

This makes the kernel enable the device.

Change-Id: I2c237b9ba038c5128e2a7e020587ac46ef7b4abd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37936
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M src/dev/arm/RealView.py
1 file changed, 1 insertion(+), 5 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index 0b5fdda..8969bc0 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -531,7 +531,7 @@
 pixel_chunk = Param.Unsigned(32, "Number of pixels to handle in one  
batch")

 virt_refresh_rate = Param.Frequency("20Hz", "Frame refresh rate "
 "in KVM mode")
-_status = "disabled"
+_status = "ok"

 encoder = Param.Display(Display1080p(), "Display encoder")

@@ -563,10 +563,6 @@
 node.append(FdtPropertyWords("clocks",  
state.phandle(self.pxl_clk)))

 node.append(FdtPropertyStrings("clock-names", ["pxlclk"]))

-# This driver is disabled by default since the required DT nodes
-# haven't been standardized yet. To use it,  override this status  
to
-# "ok" and add the display configuration nodes required by the  
driver.

-# See the driver for more information.
 node.append(FdtPropertyStrings("status", [ self._status ]))

 self.addIommuProperty(state, node)

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I2c237b9ba038c5128e2a7e020587ac46ef7b4abd
Gerrit-Change-Number: 37936
Gerrit-PatchSet: 18
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: misc,python: Fix Pre-commit hooks to ignore non-utf-8 files

[Bobby R. Bruce (Gerrit) via gem5-dev]

Bobby R. Bruce has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39795 )



Change subject: misc,python: Fix Pre-commit hooks to ignore non-utf-8 files
..

misc,python: Fix Pre-commit hooks to ignore non-utf-8 files

Previously if binary blobs were modified the pre-commit hook attempted
to run style-checks on the binary, causing an error when attempting to
decode to utf-8. This commit runs a check on each file to ensure it's
utf-8 encoded before running pre-commit procedures. If not utf-8, the
pre-commit checks are not performed on that file.

Change-Id: Id1263cac0d6c190ad1a3d67720b3f373e0e42234
Issue-on: https://gem5.atlassian.net/browse/GEM5-903
---
M util/style/style.py
1 file changed, 27 insertions(+), 1 deletion(-)



diff --git a/util/style/style.py b/util/style/style.py
index e765a92..2fb3def 100644
--- a/util/style/style.py
+++ b/util/style/style.py
@@ -40,6 +40,7 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 from abc import ABCMeta, abstractmethod
+import codecs
 import difflib
 import re
 import sys
@@ -86,6 +87,29 @@
 return rex.match(fname)
 return match_re

+def _not_utf8(fname: str) -> bool:
+"""Returns True if a file is not utf-8.
+
+Parameters
+--
+fname: str
+The file to check
+
+Returns
+---
+bool
+False if the file is utf-8 formatted, otherwise True.
+"""
+
+try:
+f = codecs.open(fname, encoding='utf-8', errors='strict')
+for line in f:
+pass
+except UnicodeDecodeError:
+return True
+
+return False
+
 # This list contains a list of functions that are called to determine
 # if a file should be excluded from the style matching rules or
 # not. The functions are called with the file name relative to the
@@ -101,7 +125,9 @@
 # project that does not follow the gem5 coding convention
 _re_ignore("tests/test-progs/asmtest/src/riscv/"),
 # Ignore RISC-V assembly dump files
-_re_ignore("tests/test-progs/asmtest/dump/riscv/")
+_re_ignore("tests/test-progs/asmtest/dump/riscv/"),
+# Ignore files that are not utf-8 formatted.
+_not_utf8
 ]

 def check_ignores(fname):

--
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Gerrit-Change-Number: 39795
Gerrit-PatchSet: 1
Gerrit-Owner: Bobby R. Bruce 
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[gem5-dev] Change in gem5/gem5[develop]: sim: Fix compilation error for debug builds.

[Richard Cooper (Gerrit) via gem5-dev]

Richard Cooper has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39760 )



Change subject: sim: Fix compilation error for debug builds.
..

sim: Fix compilation error for debug builds.

https://gem5-review.googlesource.com/c/public/gem5/+/39537 removed the
implicit use of the std:: namespace. This change adds a missing
namespace specifier for debug builds.

Change-Id: I1d70602a870a25f68d7fec4b4931ba7cbbb4f4ca
---
M src/sim/sim_object.cc
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/sim/sim_object.cc b/src/sim/sim_object.cc
index 17dbd1d..28a0863 100644
--- a/src/sim/sim_object.cc
+++ b/src/sim/sim_object.cc
@@ -160,7 +160,7 @@
 void
 debugObjectBreak(const char *objs)
 {
-SimObject::debugObjectBreak(string(objs));
+SimObject::debugObjectBreak(std::string(objs));
 }
 #endif


--
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[gem5-dev] Re: Testlib six dependency

[Jason Lowe-Power via gem5-dev]

I don't know... We've had a few discussions about this. There's some
separation between the underlying infrastructure in testlib and the code
that uses it in tests. We could move it to tests/testlib, I guess. It would
make it more clear that there's no upstream version of it.

Either way is fine with me.

Jason

On Tue, Jan 26, 2021 at 9:45 AM Andreas Sandberg 
wrote:

> Hi Jason,
>
> Thanks for confirming that. I have posted an update here:
> https://gem5-review.googlesource.com/c/public/gem5/+/39759
>
> Since there is no upstream for testlib, should we move it into tests/
> somewhere instead of keeping it in ext/?
>
> Cheers,
> Andreas
> On 26/01/2021 16:21, Jason Lowe-Power wrote:
>
> Hi Andreas,
>
> There is no upstream for testlib. It's a purely gem5 project. We should
> fix it in tree.
>
> Jason
>
> On Tue, Jan 26, 2021 at 4:56 AM Andreas Sandberg via gem5-dev <
> gem5-dev@gem5.org> wrote:
>
>> Hi Everyone,
>>
>> I have just posted a series of patches [1] that get rid of 'six' as a
>> dependency in gem5. However, there is still a dependency on six coming
>> from testlib. What's the process there? Should we fix it upstream and
>> backport it or is testlib now effectively a gem5 project?
>>
>> Cheers,
>> Abdreas
>>
>> [1] https://gem5-review.googlesource.com/c/public/gem5/+/39758
>>
>> IMPORTANT NOTICE: The contents of this email and any attachments are
>> confidential and may also be privileged. If you are not the intended
>> recipient, please notify the sender immediately and do not disclose the
>> contents to any other person, use it for any purpose, or store or copy the
>> information in any medium. Thank you.
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[gem5-dev] Re: Testlib six dependency

[Andreas Sandberg via gem5-dev]

Hi Jason,

Thanks for confirming that. I have posted an update here: 
https://gem5-review.googlesource.com/c/public/gem5/+/39759

Since there is no upstream for testlib, should we move it into tests/ somewhere 
instead of keeping it in ext/?

Cheers,
Andreas

On 26/01/2021 16:21, Jason Lowe-Power wrote:
Hi Andreas,

There is no upstream for testlib. It's a purely gem5 project. We should fix it 
in tree.

Jason

On Tue, Jan 26, 2021 at 4:56 AM Andreas Sandberg via gem5-dev 
mailto:gem5-dev@gem5.org>> wrote:
Hi Everyone,

I have just posted a series of patches [1] that get rid of 'six' as a
dependency in gem5. However, there is still a dependency on six coming
from testlib. What's the process there? Should we fix it upstream and
backport it or is testlib now effectively a gem5 project?

Cheers,
Abdreas

[1] https://gem5-review.googlesource.com/c/public/gem5/+/39758

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[gem5-dev] Change in gem5/gem5[develop]: tests: Remove Python 2.7 glue code from testlib

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39759 )



Change subject: tests: Remove Python 2.7 glue code from testlib
..

tests: Remove Python 2.7 glue code from testlib

Remove the dependency on six in testlib.

Change-Id: I247088d119cf8f9d815632eae16a1cbf87930516
Signed-off-by: Andreas Sandberg 
---
M ext/testlib/configuration.py
M ext/testlib/handlers.py
M ext/testlib/loader.py
M ext/testlib/log.py
M ext/testlib/terminal.py
5 files changed, 4 insertions(+), 13 deletions(-)



diff --git a/ext/testlib/configuration.py b/ext/testlib/configuration.py
index e5b7598..f2d93d6 100644
--- a/ext/testlib/configuration.py
+++ b/ext/testlib/configuration.py
@@ -83,7 +83,6 @@
 import os
 import re

-from six import add_metaclass
 from pickle import HIGHEST_PROTOCOL as highest_pickle_protocol

 from testlib.helper import absdirpath, AttrDict, FrozenAttrDict
@@ -602,8 +601,7 @@
 # one in the list will be saved.
 common_args = AttrDict({arg.name:arg for arg in common_args})

-@add_metaclass(abc.ABCMeta)
-class ArgParser(object):
+class ArgParser(object, metaclass=abc.ABCMeta):
 class ExtendAction(argparse.Action):
 def __call__(self, parser, namespace, values, option_string=None):
 items = getattr(namespace, self.dest, [])
diff --git a/ext/testlib/handlers.py b/ext/testlib/handlers.py
index 723a855..b62322f 100644
--- a/ext/testlib/handlers.py
+++ b/ext/testlib/handlers.py
@@ -31,8 +31,6 @@


 '''
-from __future__ import print_function
-
 import multiprocessing
 import os
 import sys
@@ -46,7 +44,7 @@
 import testlib.state as state
 import testlib.terminal as terminal

-from six.moves import queue as Queue
+from queue import Queue
 from testlib.configuration import constants


diff --git a/ext/testlib/loader.py b/ext/testlib/loader.py
index 2d76996..58b1b2e 100644
--- a/ext/testlib/loader.py
+++ b/ext/testlib/loader.py
@@ -67,7 +67,6 @@

 import os
 import re
-import six
 import sys
 import traceback

diff --git a/ext/testlib/log.py b/ext/testlib/log.py
index 1bdb373..fb5907c 100644
--- a/ext/testlib/log.py
+++ b/ext/testlib/log.py
@@ -32,8 +32,6 @@
 '''
 import testlib.wrappers as wrappers

-from six import add_metaclass
-
 class LogLevel():
 Fatal = 0
 Error = 1
@@ -56,8 +54,7 @@
 RecordTypeCounterMetaclass.counter += 1


-@add_metaclass(RecordTypeCounterMetaclass)
-class Record(object):
+class Record(object, metaclass=RecordTypeCounterMetaclass):
 '''
 A generic object that is passed to the :class:`Log` and its handlers.

diff --git a/ext/testlib/terminal.py b/ext/testlib/terminal.py
index bc4c855..be489f5 100644
--- a/ext/testlib/terminal.py
+++ b/ext/testlib/terminal.py
@@ -28,7 +28,6 @@
 import fcntl
 import termios
 import struct
-import six

 # Intended usage example:
 #
@@ -85,7 +84,7 @@
 def __init__(self, cap_string):
 for i, c in enumerate(color_names):
 setattr(self, c, cap_string('setaf', i))
-for name, cap in six.iteritems(capability_map):
+for name, cap in capability_map.items():
 setattr(self, name, cap_string(cap))

 termcap = ColorStrings(cap_string)

--
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Gerrit-Branch: develop
Gerrit-Change-Id: I247088d119cf8f9d815632eae16a1cbf87930516
Gerrit-Change-Number: 39759
Gerrit-PatchSet: 1
Gerrit-Owner: Andreas Sandberg 
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[gem5-dev] Change in gem5/gem5[develop]: configs: Remove Python 2.7 glue code

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39755 )


Change subject: configs: Remove Python 2.7 glue code
..

configs: Remove Python 2.7 glue code

Remove uses of six and from __future__ imports as they are no longer
needed.

Change-Id: I6e2f270557d7343bbad30c8e6d743e363c43715a
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39755
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M configs/common/Benchmarks.py
M configs/common/CacheConfig.py
M configs/common/Caches.py
M configs/common/CpuConfig.py
M configs/common/FSConfig.py
M configs/common/FileSystemConfig.py
M configs/common/GPUTLBConfig.py
M configs/common/GPUTLBOptions.py
M configs/common/HMC.py
M configs/common/MemConfig.py
M configs/common/ObjectList.py
M configs/common/Options.py
M configs/common/SimpleOpts.py
M configs/common/Simulation.py
M configs/common/SysPaths.py
M configs/common/__init__.py
M configs/common/cores/__init__.py
M configs/common/cores/arm/HPI.py
M configs/common/cores/arm/O3_ARM_v7a.py
M configs/common/cores/arm/__init__.py
M configs/common/cores/arm/ex5_LITTLE.py
M configs/common/cores/arm/ex5_big.py
M configs/common/cpu2000.py
M configs/dram/lat_mem_rd.py
M configs/dram/low_power_sweep.py
M configs/dram/sweep.py
M configs/example/apu_se.py
M configs/example/etrace_replay.py
M configs/example/fs.py
M configs/example/garnet_synth_traffic.py
M configs/example/hmc_hello.py
M configs/example/hmctest.py
M configs/example/memcheck.py
M configs/example/memtest.py
M configs/example/read_config.py
M configs/example/ruby_direct_test.py
M configs/example/ruby_gpu_random_test.py
M configs/example/ruby_mem_test.py
M configs/example/ruby_random_test.py
M configs/example/sc_main.py
M configs/example/se.py
M configs/learning_gem5/part1/caches.py
M configs/learning_gem5/part1/simple.py
M configs/learning_gem5/part1/two_level.py
M configs/learning_gem5/part2/hello_goodbye.py
M configs/learning_gem5/part2/run_simple.py
M configs/learning_gem5/part2/simple_cache.py
M configs/learning_gem5/part2/simple_memobj.py
M configs/learning_gem5/part3/msi_caches.py
M configs/learning_gem5/part3/ruby_caches_MI_example.py
M configs/learning_gem5/part3/ruby_test.py
M configs/learning_gem5/part3/simple_ruby.py
M configs/learning_gem5/part3/test_caches.py
M configs/network/Network.py
M configs/network/__init__.py
M configs/nvm/sweep.py
M configs/nvm/sweep_hybrid.py
M configs/ruby/GPU_VIPER.py
M configs/ruby/Ruby.py
M configs/splash2/cluster.py
M configs/splash2/run.py
M configs/topologies/BaseTopology.py
M configs/topologies/Cluster.py
M configs/topologies/Crossbar.py
M configs/topologies/CrossbarGarnet.py
M configs/topologies/MeshDirCorners_XY.py
M configs/topologies/Mesh_XY.py
M configs/topologies/Mesh_westfirst.py
M configs/topologies/Pt2Pt.py
M configs/topologies/__init__.py
70 files changed, 16 insertions(+), 241 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/configs/common/Benchmarks.py b/configs/common/Benchmarks.py
index 8477d77..591c044 100644
--- a/configs/common/Benchmarks.py
+++ b/configs/common/Benchmarks.py
@@ -24,9 +24,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
-from __future__ import absolute_import
-
 from common.SysPaths import script, disk, binary
 from os import environ as env
 from m5.defines import buildEnv
diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py
index bd80c1a..bd68465 100644
--- a/configs/common/CacheConfig.py
+++ b/configs/common/CacheConfig.py
@@ -40,9 +40,6 @@
 # Configure the M5 cache hierarchy config in one place
 #

-from __future__ import print_function
-from __future__ import absolute_import
-
 import m5
 from m5.objects import *
 from common.Caches import *
diff --git a/configs/common/Caches.py b/configs/common/Caches.py
index 77213e8..1468b95 100644
--- a/configs/common/Caches.py
+++ b/configs/common/Caches.py
@@ -37,9 +37,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
-from __future__ import absolute_import
-
 from m5.defines import buildEnv
 from m5.objects import *

diff --git a/configs/common/CpuConfig.py b/configs/common/CpuConfig.py
index 27febe2..d34143c 100644
--- a/configs/common/CpuConfig.py
+++ b/configs/common/CpuConfig.py
@@ -33,9 +33,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
-from __future__ import absolute_import
-
 from m5 import fatal
 import m5.ob

[gem5-dev] Change in gem5/gem5[develop]: util: Remove Python 2.7 glue code

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39756 )


Change subject: util: Remove Python 2.7 glue code
..

util: Remove Python 2.7 glue code

Remove uses of six and from __future__ imports as they are no longer
needed.

Change-Id: I8d6aae84d8192b301d541b8dc81275f4932f9f2f
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39756
Reviewed-by: Gabe Black 
Reviewed-by: Jason Lowe-Power 
Tested-by: kokoro 
---
M util/build_cross_gcc/build_cross_gcc.py
M util/cpt_upgrader.py
M util/style/verifiers.py
3 files changed, 8 insertions(+), 18 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/util/build_cross_gcc/build_cross_gcc.py  
b/util/build_cross_gcc/build_cross_gcc.py

index 51f7fcc..3afd4bf 100755
--- a/util/build_cross_gcc/build_cross_gcc.py
+++ b/util/build_cross_gcc/build_cross_gcc.py
@@ -32,7 +32,6 @@
 import os.path
 import pickle
 import shutil
-import six
 import subprocess
 import textwrap

@@ -145,9 +144,9 @@
 # Settings.
 #

-class MetaSetting(type):
+class MetaSetting(abc.ABCMeta):
 def __new__(mcls, name, bases, d):
-cls = super(MetaSetting, mcls).__new__(mcls, name, bases, d)
+cls = super().__new__(mcls, name, bases, d)
 key = d.get('key', None)
 if key is not None:
 assert('default' in d)
@@ -157,9 +156,7 @@
 all_settings[key] = instance
 return cls

-@six.add_metaclass(MetaSetting)
-@six.add_metaclass(abc.ABCMeta)
-class Setting(object):
+class Setting(object, metaclass=MetaSetting):
 key = None

 @abc.abstractmethod
@@ -420,17 +417,15 @@
 # Steps of the build process.
 #

-class MetaStep(type):
+class MetaStep(abc.ABCMeta):
 def __new__(mcls, name, bases, d):
-cls = super(MetaStep, mcls).__new__(mcls, name, bases, d)
+cls = super().__new__(mcls, name, bases, d)
 number = d.get('number', None)
 if number is not None:
 all_steps[number] = cls()
 return cls

-@six.add_metaclass(MetaStep)
-@six.add_metaclass(abc.ABCMeta)
-class Step(object):
+class Step(object, metaclass=MetaStep):
 'Steps to set up a cross compiling gcc.'
 number = None

diff --git a/util/cpt_upgrader.py b/util/cpt_upgrader.py
index 9964aac..15dc2ab 100755
--- a/util/cpt_upgrader.py
+++ b/util/cpt_upgrader.py
@@ -69,8 +69,7 @@
 # upgraders in private branches.


-
-from six.moves import configparser
+import configparser
 import glob, types, sys, os
 import os.path as osp

diff --git a/util/style/verifiers.py b/util/style/verifiers.py
index 7d27fda..798ddfc 100644
--- a/util/style/verifiers.py
+++ b/util/style/verifiers.py
@@ -47,8 +47,6 @@
 import re
 import sys

-from six import add_metaclass
-
 from . import style
 from . import sort_includes
 from .region import *
@@ -102,8 +100,7 @@
 return regions


-@add_metaclass(ABCMeta)
-class Verifier(object):
+class Verifier(object, metaclass=ABCMeta):
 """Base class for style verifiers

 Verifiers check for style violations and optionally fix such
@@ -224,7 +221,6 @@
 """
 pass

-@add_metaclass(ABCMeta)
 class LineVerifier(Verifier):
 def check(self, filename, regions=all_regions, fobj=None,  
silent=False):

 close = False

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8d6aae84d8192b301d541b8dc81275f4932f9f2f
Gerrit-Change-Number: 39756
Gerrit-PatchSet: 2
Gerrit-Owner: Andreas Sandberg 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Re: Testlib six dependency

[Jason Lowe-Power via gem5-dev]

Hi Andreas,

There is no upstream for testlib. It's a purely gem5 project. We should fix
it in tree.

Jason

On Tue, Jan 26, 2021 at 4:56 AM Andreas Sandberg via gem5-dev <
gem5-dev@gem5.org> wrote:

> Hi Everyone,
>
> I have just posted a series of patches [1] that get rid of 'six' as a
> dependency in gem5. However, there is still a dependency on six coming
> from testlib. What's the process there? Should we fix it upstream and
> backport it or is testlib now effectively a gem5 project?
>
> Cheers,
> Abdreas
>
> [1] https://gem5-review.googlesource.com/c/public/gem5/+/39758
>
> IMPORTANT NOTICE: The contents of this email and any attachments are
> confidential and may also be privileged. If you are not the intended
> recipient, please notify the sender immediately and do not disclose the
> contents to any other person, use it for any purpose, or store or copy the
> information in any medium. Thank you.
> ___
> gem5-dev mailing list -- gem5-dev@gem5.org
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[gem5-dev] Change in gem5/gem5[develop]: sim: Use the Temperature type in power/thermal models

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39455 )


Change subject: sim: Use the Temperature type in power/thermal models
..

sim: Use the Temperature type in power/thermal models

The thermal models currently work on temperatures in Celsius stored in
plain doubles. Switch to using Temperature instead and internal
processing in Kelvin. There should be no impact on the result since
all thermal processes work on temperature deltas.

Change-Id: I22d0261ae102f30d86051f24a2d88b067b321c91
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39455
Tested-by: kokoro 
Reviewed-by: Daniel Carvalho 
Maintainer: Jason Lowe-Power 
---
M src/dev/arm/rv_ctrl.cc
M src/sim/power/mathexpr_powermodel.cc
M src/sim/power/power_model.cc
M src/sim/power/power_model.hh
M src/sim/power/thermal_domain.cc
M src/sim/power/thermal_domain.hh
M src/sim/power/thermal_model.cc
M src/sim/power/thermal_model.hh
M src/sim/power/thermal_node.hh
9 files changed, 46 insertions(+), 41 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/dev/arm/rv_ctrl.cc b/src/dev/arm/rv_ctrl.cc
index 2d80bc2..6cacb4d 100644
--- a/src/dev/arm/rv_ctrl.cc
+++ b/src/dev/arm/rv_ctrl.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010,2013,2015 ARM Limited
+ * Copyright (c) 2010, 2013, 2015, 2021 Arm Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -304,7 +304,7 @@
 // Temperature reported in uC
 ThermalModel * tm = system->getThermalModel();
 if (tm) {
-double t = tm->getTemp();
+double t = tm->getTemperature().toCelsius();
 if (t < 0)
 warn("Temperature below zero!\n");
 return fmax(0, t) * 100;
diff --git a/src/sim/power/mathexpr_powermodel.cc  
b/src/sim/power/mathexpr_powermodel.cc

index 4f3f927..e66d8d9 100644
--- a/src/sim/power/mathexpr_powermodel.cc
+++ b/src/sim/power/mathexpr_powermodel.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2017, 2020 ARM Limited
+ * Copyright (c) 2016-2017, 2020-2021 Arm Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -86,7 +86,7 @@

 // Automatic variables:
 if (name == "temp") {
-return _temp;
+return _temp.toCelsius();
 } else if (name == "voltage") {
 return clocked_object->voltage();
 } else if (name=="clock_period") {
diff --git a/src/sim/power/power_model.cc b/src/sim/power/power_model.cc
index 42515ac..e79ecbc 100644
--- a/src/sim/power/power_model.cc
+++ b/src/sim/power/power_model.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2018 ARM Limited
+ * Copyright (c) 2016-2018, 2021 Arm Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -66,7 +66,7 @@
 // The temperature passed here will be overwritten, if there is
 // a thermal model present
 for (auto & pms: states_pm){
-pms->setTemperature(p.ambient_temp.toCelsius());
+pms->setTemperature(p.ambient_temp);
 }

 dynamicPower
@@ -86,7 +86,7 @@
 }

 void
-PowerModel::thermalUpdateCallback(const double & temp)
+PowerModel::thermalUpdateCallback(const Temperature &temp)
 {
 for (auto & pms: states_pm)
 pms->setTemperature(temp);
diff --git a/src/sim/power/power_model.hh b/src/sim/power/power_model.hh
index e6f5431..3a0fc64 100644
--- a/src/sim/power/power_model.hh
+++ b/src/sim/power/power_model.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, 2018 ARM Limited
+ * Copyright (c) 2016, 2018, 2021 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -39,6 +39,7 @@
 #define __SIM_POWER_POWER_MODEL_HH__

 #include "base/statistics.hh"
+#include "base/temperature.hh"
 #include "enums/PMType.hh"
 #include "params/PowerModel.hh"
 #include "params/PowerModelState.hh"
@@ -75,9 +76,9 @@
 /**
  * Temperature update.
  *
- * @param temp Current temperature of the HW part (Celsius)
+ * @param temp Current temperature of the HW part
  */
-virtual void setTemperature(double temp) { _temp = temp; }
+virtual void setTemperature(Temperature temp) { _temp = temp; }

 void setClockedObject(ClockedObject * clkobj) {
 clocked_object = clkobj;
@@ -86,7 +87,7 @@
   protected:

 /** Current temperature */
-double _temp;
+Temperature _temp;

 /** The clocked object we belong to */
 ClockedObject * clocked_object;
@@ -125,18 +126,18 @@

 virtual void regProbePoints();

-void thermalUpdateCallback(const double & temp);
+void thermalUpdateCallback(const Temperature &temp);

   protected:
 /** Listener class to catch thermal events */
-class ThermalProbeListen

[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Implement Generic Watchdog

[Giacomo Travaglini (Gerrit) via gem5-dev]

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39699 )


Change subject: dev-arm: Implement Generic Watchdog
..

dev-arm: Implement Generic Watchdog

Change-Id: I53bcb6ae77c0bcc080f4be0bd2339d4d1f6a4b28
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39699
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/dev/arm/RealView.py
M src/dev/arm/SConscript
A src/dev/arm/watchdog_generic.cc
A src/dev/arm/watchdog_generic.hh
4 files changed, 435 insertions(+), 0 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index 7d90111..588e4a9 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -441,6 +441,21 @@

 yield node

+class GenericWatchdog(PioDevice):
+type = 'GenericWatchdog'
+cxx_header = 'dev/arm/watchdog_generic.hh'
+
+refresh_start = Param.Addr("Start address for the refresh frame")
+control_start = Param.Addr("Start address for the control frame")
+pio_latency = Param.Latency('10ns', "Delay for PIO r/w")
+
+ws0 = Param.ArmInterruptPin("WS0 Signal")
+ws1 = Param.ArmInterruptPin("WS1 Signal")
+
+system_counter = Param.SystemCounter(Parent.any,
+"The Watchdog uses the Generic Timer system counter as the  
timebase "

+"against which the decision to trigger an interrupt is made.")
+
 class A9GlobalTimer(BasicPioDevice):
 type = 'A9GlobalTimer'
 cxx_header = "dev/arm/timer_a9global.hh"
diff --git a/src/dev/arm/SConscript b/src/dev/arm/SConscript
index cc3efcf..c78483f 100644
--- a/src/dev/arm/SConscript
+++ b/src/dev/arm/SConscript
@@ -81,6 +81,7 @@
 Source('smmu_v3_deviceifc.cc');
 Source('smmu_v3_transl.cc');
 Source('timer_sp804.cc')
+Source('watchdog_generic.cc')
 Source('watchdog_sp805.cc')
 Source('gpu_nomali.cc')
 Source('pci_host.cc')
diff --git a/src/dev/arm/watchdog_generic.cc  
b/src/dev/arm/watchdog_generic.cc

new file mode 100644
index 000..3361665
--- /dev/null
+++ b/src/dev/arm/watchdog_generic.cc
@@ -0,0 +1,263 @@
+/*
+ * Copyright (c) 2020 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "dev/arm/watchdog_generic.hh"
+
+#include "dev/arm/base_gic.hh"
+#include "params/GenericWatchdog.hh"
+
+
+GenericWatchdog::GenericWatchdog(const GenericWatchdogParams &p)
+: PioDevice(p),
+  timeoutEvent([this]{ timeout(); }, name()),
+  controlStatus(0),
+  offset(0),
+  compare(0),
+  iidr(0),
+  refreshFrame(p.refresh_start, p.refresh_start + 0x1),
+  controlFrame(p.control_start, p.control_start + 0x1),
+  pioLatency(p.pio_latency),
+  cnt(*p.system_counter

[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Instantiate Generic Watchdog in Foundation platform

[Giacomo Travaglini (Gerrit) via gem5-dev]

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39700 )


Change subject: dev-arm: Instantiate Generic Watchdog in Foundation platform
..

dev-arm: Instantiate Generic Watchdog in Foundation platform

Change-Id: I75496eeabeabb81804d4055f8257309324d6476a
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39700
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/dev/arm/RealView.py
1 file changed, 6 insertions(+), 0 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index 588e4a9..0b5fdda 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -1085,6 +1085,11 @@

 ### On-chip devices ###

+el2_watchdog = GenericWatchdog(
+control_start=0x2a44,
+refresh_start=0x2a45,
+ws0=ArmSPI(num=59), ws1=ArmSPI(num=60))
+
 # Trusted Watchdog, SP805
 trusted_watchdog = Sp805(pio_addr=0x2a49, interrupt=ArmSPI(num=56))

@@ -1109,6 +1114,7 @@
 def _on_chip_devices(self):
 return [
 self.generic_timer_mem,
+self.el2_watchdog,
 self.trusted_watchdog,
 self.system_watchdog
 ] + self.generic_timer_mem.frames

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I75496eeabeabb81804d4055f8257309324d6476a
Gerrit-Change-Number: 39700
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Add a fake SP810 to the VExpress_GEM5_Foundation

[Giacomo Travaglini (Gerrit) via gem5-dev]

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39696 )


Change subject: dev-arm: Add a fake SP810 to the VExpress_GEM5_Foundation
..

dev-arm: Add a fake SP810 to the VExpress_GEM5_Foundation

The device is part of the FVP Foundation Platform:

https://static.docs.arm.com/100961/1190/armv8_a_fp_ug_100961_1190_00_en.pdf

Change-Id: I81c11312f29d8e59ac5f8ce2fe165d9474027d82
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39696
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/dev/arm/RealView.py
1 file changed, 7 insertions(+), 0 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index c168cfd..0c65ff2 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -1363,6 +1363,8 @@
 AddrRange(0x4000, 0x8000),
 ]

+sp810_fake = AmbaFake(pio_addr=0x1C02, ignore_access=True)
+
 gic = Gicv3(dist_addr=0x2f00, redist_addr=0x2f10,
 maint_int=ArmPPI(num=25), gicv4=False,
 its=NULL)
@@ -1378,6 +1380,11 @@
 self.gic
 ]

+def _off_chip_devices(self):
+return super(VExpress_GEM5_Foundation, self)._off_chip_devices() +  
[

+self.sp810_fake,
+]
+
 def setupBootLoader(self, cur_sys, loc, boot_loader=None):
 if boot_loader is None:
 boot_loader = [ loc('boot_v2.arm64') ]

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I81c11312f29d8e59ac5f8ce2fe165d9474027d82
Gerrit-Change-Number: 39696
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Add a PL111 to the VExpress_GEM5_Foundation

[Giacomo Travaglini (Gerrit) via gem5-dev]

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39697 )


Change subject: dev-arm: Add a PL111 to the VExpress_GEM5_Foundation
..

dev-arm: Add a PL111 to the VExpress_GEM5_Foundation

The device is part of the FVP Foundation platform:

https://static.docs.arm.com/100961/1190/armv8_a_fp_ug_100961_1190_00_en.pdf

Change-Id: I91226cb10a3be50c59e32288b3643c550e8b538d
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39697
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/dev/arm/RealView.py
1 file changed, 3 insertions(+), 0 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index 0c65ff2..7d90111 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -1365,6 +1365,8 @@

 sp810_fake = AmbaFake(pio_addr=0x1C02, ignore_access=True)

+clcd = Pl111(pio_addr=0x1c1f, interrupt=ArmSPI(num=46))
+
 gic = Gicv3(dist_addr=0x2f00, redist_addr=0x2f10,
 maint_int=ArmPPI(num=25), gicv4=False,
 its=NULL)
@@ -1382,6 +1384,7 @@

 def _off_chip_devices(self):
 return super(VExpress_GEM5_Foundation, self)._off_chip_devices() +  
[

+self.clcd,
 self.sp810_fake,
 ]


--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I91226cb10a3be50c59e32288b3643c550e8b538d
Gerrit-Change-Number: 39697
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: dev-arm: A SystemCounterListener doesn't have to be Serializable

[Giacomo Travaglini (Gerrit) via gem5-dev]

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39698 )


Change subject: dev-arm: A SystemCounterListener doesn't have to be  
Serializable

..

dev-arm: A SystemCounterListener doesn't have to be Serializable

The class is not making use of any Serializable utility.
By removing this dependency we can extend it more easilly

Change-Id: Ia321b8f0deeb92adde008551eb921dcfd365e675
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39698
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/dev/arm/generic_timer.hh
1 file changed, 4 insertions(+), 3 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/dev/arm/generic_timer.hh b/src/dev/arm/generic_timer.hh
index 16d2ce3..9a6663c 100644
--- a/src/dev/arm/generic_timer.hh
+++ b/src/dev/arm/generic_timer.hh
@@ -71,7 +71,7 @@

 /// Abstract class for elements whose events depend on the counting speed
 /// of the System Counter
-class SystemCounterListener : public Serializable
+class SystemCounterListener
 {
   public:
 /// Called from the SystemCounter when a change in counting speed  
occurred

@@ -174,7 +174,8 @@
 };

 /// Per-CPU architected timer.
-class ArchTimer : public SystemCounterListener, public Drainable
+class ArchTimer : public SystemCounterListener, public Drainable,
+  public Serializable
 {
   protected:
 /// Control register.
@@ -297,7 +298,7 @@
 RegVal readMiscReg(int misc_reg, unsigned cpu);

   protected:
-class CoreTimers : public SystemCounterListener
+class CoreTimers : public SystemCounterListener, public Serializable
 {
   public:
 CoreTimers(GenericTimer &_parent, ArmSystem &system, unsigned cpu,

--
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Gerrit-Branch: develop
Gerrit-Change-Id: Ia321b8f0deeb92adde008551eb921dcfd365e675
Gerrit-Change-Number: 39698
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: dev-arm, system-arm: Remove HDLcd from VExpress_GEM5_VX platforms

[Giacomo Travaglini (Gerrit) via gem5-dev]

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38796 )


Change subject: dev-arm, system-arm: Remove HDLcd from VExpress_GEM5_VX  
platforms

..

dev-arm, system-arm: Remove HDLcd from VExpress_GEM5_VX platforms

This is a major change in our platform configuration.
At the moment the VExpress_GEM5_V1 and VExpress_GEM5_V2 platforms
both instantiate an HDLcd device. As the presence of the device
can slow down host performances when the software stack is
aware of its presence, we have historically been providing
an entry in the hdlcd DTB node to "hide" the entry from the
DTB parser:

status = "disable";

This default entry in the hdlcd node will in fact prevent the driver
from bringing up the device. Unfortunately this is useful for
experienced users only which are aware of this knob.

In order to make things more transparent, and to avoid any confusion
(e.g. having the hdlcd present in the config.ini, but not being able to
program it in Linux) we are deprecating this solution; we are removing
the HDLcd from the aforementioned platforms.

Users not interested on simulating a display controller won't
notice the difference.
Users interested on including it, will now have to switch to a new

VExpress_GEM5_Vx_HLCD platform

which will enabled the HDLcd without any further tweaking required

JIRA: https://gem5.atlassian.net/browse/GEM5-866

Change-Id: I4b1920efe764080115a57f52d8a3df2e6e2386a0
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38796
Tested-by: kokoro 
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
---
M src/dev/arm/RealView.py
M system/arm/dt/Makefile
R system/arm/dt/platforms/vexpress_gem5_v1_hdlcd.dtsi
R system/arm/dt/platforms/vexpress_gem5_v2_hdlcd.dtsi
4 files changed, 66 insertions(+), 16 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index f988452..c168cfd 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2009-2020 ARM Limited
+# Copyright (c) 2009-2021 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -1299,11 +1299,18 @@
 ]

 class VExpress_GEM5_V1(VExpress_GEM5_V1_Base):
+"""
+We subclass VExpress_GEM5_V1_Base in order to alias it to
+VExpress_GEM5_V1, which is what gem5 scripts are currently using
+"""
+pass
+
+class VExpress_GEM5_V1_HDLcd(VExpress_GEM5_V1_Base):
 hdlcd  = HDLcd(pxl_clk=VExpress_GEM5_V1_Base.dcc.osc_pxl,
pio_addr=0x2b00, interrupt=ArmSPI(num=95))

 def _on_chip_devices(self):
-return super(VExpress_GEM5_V1,self)._on_chip_devices() + [
+return super(VExpress_GEM5_V1_HDLcd,self)._on_chip_devices() + [
 self.hdlcd,
 ]

@@ -1327,11 +1334,18 @@
 cur_sys, boot_loader)

 class VExpress_GEM5_V2(VExpress_GEM5_V2_Base):
+"""
+We subclass VExpress_GEM5_V2_Base in order to alias it to
+VExpress_GEM5_V2, which is what gem5 scripts are currently using
+"""
+pass
+
+class VExpress_GEM5_V2_HDLcd(VExpress_GEM5_V2_Base):
 hdlcd  = HDLcd(pxl_clk=VExpress_GEM5_V2_Base.dcc.osc_pxl,
pio_addr=0x2b00, interrupt=ArmSPI(num=95))

 def _on_chip_devices(self):
-return super(VExpress_GEM5_V2,self)._on_chip_devices() + [
+return super(VExpress_GEM5_V2_HDLcd,self)._on_chip_devices() + [
 self.hdlcd,
 ]

diff --git a/system/arm/dt/Makefile b/system/arm/dt/Makefile
index fb7ac30..8332f76 100644
--- a/system/arm/dt/Makefile
+++ b/system/arm/dt/Makefile
@@ -1,4 +1,4 @@
-# Copyright (c) 2015-2016, 2019-2020 ARM Limited
+# Copyright (c) 2015-2016, 2019-2021 ARM Limited
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -36,21 +36,34 @@
 TARGET_PREFIX=\
armv7_gem5_v1 \
armv8_gem5_v1 \
-   armv8_gem5_v2
+   armv8_gem5_v2 \
+   armv7_gem5_v1_hdlcd \
+   armv8_gem5_v1_hdlcd \
+   armv8_gem5_v2_hdlcd

 TARGETS=\
$(foreach prefix, $(TARGET_PREFIX), $(call CREATE_TARGET, $(prefix))) \
armv8_gem5_v1_big_little_2_2.dtb \
armv8_gem5_v1_big_little_2_4.dtb \
armv8_gem5_v2_big_little_2_2.dtb \
-   armv8_gem5_v2_big_little_2_4.dtb
+   armv8_gem5_v2_big_little_2_4.dtb \
+   armv8_gem5_v1_hdlcd_big_little_2_2.dtb \
+   armv8_gem5_v1_hdlcd_big_little_2_4.dtb \
+   armv8_gem5_v2_hdlcd_big_little_2_2.dtb \
+   armv8_gem5_v2_hdlcd_big_little_2_4.dtb

 VEXPRESS_GEM5_V1_DTSIS=\
-   platforms/vexpress_gem5_v1.dtsi \
+   platforms/vexpress_gem5_v1_base.dtsi
+
+VEXPRESS_GEM5_V1_HDLCD_DTSIS=\
+   platforms/vexpress_gem5_v1_hdl

[gem5-dev] Change in gem5/gem5[develop]: system-arm: Enabled HDLcd by default in DTS

[Giacomo Travaglini (Gerrit) via gem5-dev]

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38797 )


Change subject: system-arm: Enabled HDLcd by default in DTS
..

system-arm: Enabled HDLcd by default in DTS

This is fine as people using *_hdlcd.dtsi are willing to simulate
an HDLcd

JIRA: https://gem5.atlassian.net/browse/GEM5-866

Change-Id: Ifd5d6ecc81de920dbc29a05b07f30c13dcee3aa4
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38797
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M system/arm/dt/platforms/display.dtsi
M system/arm/dt/platforms/vexpress_gem5_v1_hdlcd.dtsi
M system/arm/dt/platforms/vexpress_gem5_v2_hdlcd.dtsi
3 files changed, 4 insertions(+), 15 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/system/arm/dt/platforms/display.dtsi  
b/system/arm/dt/platforms/display.dtsi

index 16a029a..64c41e6 100644
--- a/system/arm/dt/platforms/display.dtsi
+++ b/system/arm/dt/platforms/display.dtsi
@@ -55,8 +55,6 @@
 };

 &dp0 {
-   status = "ok";
-
port {
dp0_output: endpoint@0 {
remote-endpoint = <&dp0_virt_input>;
diff --git a/system/arm/dt/platforms/vexpress_gem5_v1_hdlcd.dtsi  
b/system/arm/dt/platforms/vexpress_gem5_v1_hdlcd.dtsi

index efca66d..a11dcb6 100644
--- a/system/arm/dt/platforms/vexpress_gem5_v1_hdlcd.dtsi
+++ b/system/arm/dt/platforms/vexpress_gem5_v1_hdlcd.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2019 ARM Limited
+ * Copyright (c) 2015-2019, 2021 ARM Limited
  * All rights reserved
  *
  * Redistribution and use in source and binary forms, with or without
@@ -29,18 +29,13 @@
 /include/ "vexpress_gem5_v1_base.dtsi"

 / {
-   /* The display processor needs custom configuration to setup its
- * output ports. Disable it by default in the platform until the
- * DT bindings have stabilize.
-*/
dp0: hdlcd@2b00 {
compatible = "arm,hdlcd";
reg = <0x0 0x2b00 0x0 0x1000>;
interrupts = <0 63 4>;
clocks = <&osc_pxl>;
clock-names = "pxlclk";
-
-   status = "disabled";
+   status = "ok";
};
 };

diff --git a/system/arm/dt/platforms/vexpress_gem5_v2_hdlcd.dtsi  
b/system/arm/dt/platforms/vexpress_gem5_v2_hdlcd.dtsi

index 6775727..3e8003a 100644
--- a/system/arm/dt/platforms/vexpress_gem5_v2_hdlcd.dtsi
+++ b/system/arm/dt/platforms/vexpress_gem5_v2_hdlcd.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2019 ARM Limited
+ * Copyright (c) 2015-2019, 2021 ARM Limited
  * All rights reserved
  *
  * Redistribution and use in source and binary forms, with or without
@@ -29,17 +29,13 @@
 /include/ "vexpress_gem5_v2_base.dtsi"

 / {
-   /* The display processor needs custom configuration to setup its
-* output ports. Disable it by default in the platform until the
-* DT bindings have stabilize.
-*/
dp0: hdlcd@2b00 {
compatible = "arm,hdlcd";
reg = <0x0 0x2b00 0x0 0x1000>;
interrupts = <0 63 4>;
clocks = <&osc_pxl>;
clock-names = "pxlclk";
-   status = "disabled";
+   status = "ok";
};
 };


--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ifd5d6ecc81de920dbc29a05b07f30c13dcee3aa4
Gerrit-Change-Number: 38797
Gerrit-PatchSet: 5
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Jenkins build is back to normal : Nightly #199

[jenkins-no-reply--- via gem5-dev]

See 
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[gem5-dev] Testlib six dependency

[Andreas Sandberg via gem5-dev]

Hi Everyone,

I have just posted a series of patches [1] that get rid of 'six' as a
dependency in gem5. However, there is still a dependency on six coming
from testlib. What's the process there? Should we fix it upstream and
backport it or is testlib now effectively a gem5 project?

Cheers,
Abdreas

[1] https://gem5-review.googlesource.com/c/public/gem5/+/39758

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[gem5-dev] Change in gem5/gem5[develop]: configs: Remove Python 2.7 glue code

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39755 )



Change subject: configs: Remove Python 2.7 glue code
..

configs: Remove Python 2.7 glue code

Remove uses of six and from __future__ imports as they are no longer
needed.

Change-Id: I6e2f270557d7343bbad30c8e6d743e363c43715a
Signed-off-by: Andreas Sandberg 
---
M configs/common/Benchmarks.py
M configs/common/CacheConfig.py
M configs/common/Caches.py
M configs/common/CpuConfig.py
M configs/common/FSConfig.py
M configs/common/FileSystemConfig.py
M configs/common/GPUTLBConfig.py
M configs/common/GPUTLBOptions.py
M configs/common/HMC.py
M configs/common/MemConfig.py
M configs/common/ObjectList.py
M configs/common/Options.py
M configs/common/SimpleOpts.py
M configs/common/Simulation.py
M configs/common/SysPaths.py
M configs/common/__init__.py
M configs/common/cores/__init__.py
M configs/common/cores/arm/HPI.py
M configs/common/cores/arm/O3_ARM_v7a.py
M configs/common/cores/arm/__init__.py
M configs/common/cores/arm/ex5_LITTLE.py
M configs/common/cores/arm/ex5_big.py
M configs/common/cpu2000.py
M configs/dram/lat_mem_rd.py
M configs/dram/low_power_sweep.py
M configs/dram/sweep.py
M configs/example/apu_se.py
M configs/example/etrace_replay.py
M configs/example/fs.py
M configs/example/garnet_synth_traffic.py
M configs/example/hmc_hello.py
M configs/example/hmctest.py
M configs/example/memcheck.py
M configs/example/memtest.py
M configs/example/read_config.py
M configs/example/ruby_direct_test.py
M configs/example/ruby_gpu_random_test.py
M configs/example/ruby_mem_test.py
M configs/example/ruby_random_test.py
M configs/example/sc_main.py
M configs/example/se.py
M configs/learning_gem5/part1/caches.py
M configs/learning_gem5/part1/simple.py
M configs/learning_gem5/part1/two_level.py
M configs/learning_gem5/part2/hello_goodbye.py
M configs/learning_gem5/part2/run_simple.py
M configs/learning_gem5/part2/simple_cache.py
M configs/learning_gem5/part2/simple_memobj.py
M configs/learning_gem5/part3/msi_caches.py
M configs/learning_gem5/part3/ruby_caches_MI_example.py
M configs/learning_gem5/part3/ruby_test.py
M configs/learning_gem5/part3/simple_ruby.py
M configs/learning_gem5/part3/test_caches.py
M configs/network/Network.py
M configs/network/__init__.py
M configs/nvm/sweep.py
M configs/nvm/sweep_hybrid.py
M configs/ruby/GPU_VIPER.py
M configs/ruby/Ruby.py
M configs/splash2/cluster.py
M configs/splash2/run.py
M configs/topologies/BaseTopology.py
M configs/topologies/Cluster.py
M configs/topologies/Crossbar.py
M configs/topologies/CrossbarGarnet.py
M configs/topologies/MeshDirCorners_XY.py
M configs/topologies/Mesh_XY.py
M configs/topologies/Mesh_westfirst.py
M configs/topologies/Pt2Pt.py
M configs/topologies/__init__.py
70 files changed, 16 insertions(+), 241 deletions(-)



diff --git a/configs/common/Benchmarks.py b/configs/common/Benchmarks.py
index 8477d77..591c044 100644
--- a/configs/common/Benchmarks.py
+++ b/configs/common/Benchmarks.py
@@ -24,9 +24,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
-from __future__ import absolute_import
-
 from common.SysPaths import script, disk, binary
 from os import environ as env
 from m5.defines import buildEnv
diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py
index bd80c1a..bd68465 100644
--- a/configs/common/CacheConfig.py
+++ b/configs/common/CacheConfig.py
@@ -40,9 +40,6 @@
 # Configure the M5 cache hierarchy config in one place
 #

-from __future__ import print_function
-from __future__ import absolute_import
-
 import m5
 from m5.objects import *
 from common.Caches import *
diff --git a/configs/common/Caches.py b/configs/common/Caches.py
index 77213e8..1468b95 100644
--- a/configs/common/Caches.py
+++ b/configs/common/Caches.py
@@ -37,9 +37,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
-from __future__ import absolute_import
-
 from m5.defines import buildEnv
 from m5.objects import *

diff --git a/configs/common/CpuConfig.py b/configs/common/CpuConfig.py
index 27febe2..d34143c 100644
--- a/configs/common/CpuConfig.py
+++ b/configs/common/CpuConfig.py
@@ -33,9 +33,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
-from __future__ import absolute_import
-
 from m5 import fatal
 import m5.objects

diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index 6fd39a5..6665225 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -38,20 +38,12 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT O

[gem5-dev] Change in gem5/gem5[develop]: tests: Remove Python 2.7 glue code

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39757 )



Change subject: tests: Remove Python 2.7 glue code
..

tests: Remove Python 2.7 glue code

Remove uses of six and from __future__ imports as they are no longer
needed.

Change-Id: I74b5250722abe1e202f31a9ec1d4cc04039df168
Signed-off-by: Andreas Sandberg 
---
M tests/configs/gpu-ruby.py
M tests/gem5/configs/base_config.py
M tests/gem5/configs/checkpoint.py
M tests/gem5/configs/switcheroo.py
M tests/gem5/fixture.py
M tests/gem5/fs/linux/arm/run.py
M tests/gem5/memory/test.py
M tests/main.py
M tests/run.py
9 files changed, 4 insertions(+), 17 deletions(-)



diff --git a/tests/configs/gpu-ruby.py b/tests/configs/gpu-ruby.py
index a463fe3..b561d02 100644
--- a/tests/configs/gpu-ruby.py
+++ b/tests/configs/gpu-ruby.py
@@ -33,8 +33,6 @@
 #  Author: Brad Beckmann
 #

-from __future__ import print_function
-
 import m5
 from m5.objects import *
 from m5.defines import buildEnv
diff --git a/tests/gem5/configs/base_config.py  
b/tests/gem5/configs/base_config.py

index 5623db8..b18cecf 100644
--- a/tests/gem5/configs/base_config.py
+++ b/tests/gem5/configs/base_config.py
@@ -42,12 +42,10 @@
 from common import Options
 from common.Caches import *
 from ruby import Ruby
-from six import add_metaclass

 _have_kvm_support = 'BaseKvmCPU' in globals()

-@add_metaclass(ABCMeta)
-class BaseSystem(object):
+class BaseSystem(object, metaclass=ABCMeta):
 """Base system builder.

 This class provides some basic functionality for creating an ARM
diff --git a/tests/gem5/configs/checkpoint.py  
b/tests/gem5/configs/checkpoint.py

index a652094..3545095 100644
--- a/tests/gem5/configs/checkpoint.py
+++ b/tests/gem5/configs/checkpoint.py
@@ -33,8 +33,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
-
 from multiprocessing import Process
 import sys
 import os
diff --git a/tests/gem5/configs/switcheroo.py  
b/tests/gem5/configs/switcheroo.py

index cb47f90..fb1db81 100644
--- a/tests/gem5/configs/switcheroo.py
+++ b/tests/gem5/configs/switcheroo.py
@@ -33,8 +33,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
-
 import m5
 import _m5
 from m5.objects import *
diff --git a/tests/gem5/fixture.py b/tests/gem5/fixture.py
index 467eb43..5ffb248 100644
--- a/tests/gem5/fixture.py
+++ b/tests/gem5/fixture.py
@@ -44,7 +44,8 @@
 import threading
 import gzip

-from six.moves import urllib
+import urllib.error
+import urllib.request

 from testlib.fixture import Fixture
 from testlib.configuration import config, constants
diff --git a/tests/gem5/fs/linux/arm/run.py b/tests/gem5/fs/linux/arm/run.py
index a0d782b..3dccebb 100644
--- a/tests/gem5/fs/linux/arm/run.py
+++ b/tests/gem5/fs/linux/arm/run.py
@@ -36,8 +36,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
-
 import sys
 import os
 import os.path
diff --git a/tests/gem5/memory/test.py b/tests/gem5/memory/test.py
index 7b839f2..db20ab5 100644
--- a/tests/gem5/memory/test.py
+++ b/tests/gem5/memory/test.py
@@ -28,7 +28,6 @@
 Test file for simple memory test
 TODO: Add stats checking
 '''
-import six

 from testlib import *

@@ -50,7 +49,7 @@


 for name, params in simple_mem_params:
-args = ['--' + key + '=' + val for key,val in six.iteritems(params)]
+args = ['--' + key + '=' + val for key,val in params.items()]

 gem5_verify_config(
 name='simple_mem_' + name,
diff --git a/tests/main.py b/tests/main.py
index 3287ef1..39717f6 100755
--- a/tests/main.py
+++ b/tests/main.py
@@ -5,7 +5,6 @@

 Discovers and runs all tests from a given root directory.
 '''
-from __future__ import print_function

 import sys
 import os
diff --git a/tests/run.py b/tests/run.py
index a8b612b..c3360ac 100644
--- a/tests/run.py
+++ b/tests/run.py
@@ -36,8 +36,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
-
 import os
 import sys
 import re

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I74b5250722abe1e202f31a9ec1d4cc04039df168
Gerrit-Change-Number: 39757
Gerrit-PatchSet: 1
Gerrit-Owner: Andreas Sandberg 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch, mem, cpu, systemc: Remove Python 2.7 glue code

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39758 )



Change subject: arch, mem, cpu, systemc: Remove Python 2.7 glue code
..

arch, mem, cpu, systemc: Remove Python 2.7 glue code

Remove uses of six and from __future__ imports as they are no longer
needed.

Change-Id: Ib10d01d9398795f46eedeb91a02736f248917b6a
Signed-off-by: Andreas Sandberg 
---
M src/arch/arm/fastmodel/SConscript
M src/arch/micro_asm.py
M src/arch/micro_asm_test.py
M src/arch/x86/isa/microops/fpop.isa
M src/arch/x86/isa/microops/limmop.isa
M src/arch/x86/isa/microops/mediaop.isa
M src/arch/x86/isa/microops/regop.isa
M src/cpu/BaseCPU.py
M src/cpu/minor/MinorCPU.py
M src/cpu/o3/O3CPU.py
M src/cpu/simple/BaseSimpleCPU.py
M src/mem/qos/QoSPolicy.py
M src/mem/slicc/main.py
M src/mem/slicc/util.py
M src/systemc/tests/config.py
M src/systemc/tests/verify.py
M src/unittest/genini.py
17 files changed, 10 insertions(+), 48 deletions(-)



diff --git a/src/arch/arm/fastmodel/SConscript  
b/src/arch/arm/fastmodel/SConscript

index f5516fa..21b3d3c 100644
--- a/src/arch/arm/fastmodel/SConscript
+++ b/src/arch/arm/fastmodel/SConscript
@@ -35,7 +35,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
 from itertools import cycle

 Import('*')
diff --git a/src/arch/micro_asm.py b/src/arch/micro_asm.py
index 53026c1..0305a02 100644
--- a/src/arch/micro_asm.py
+++ b/src/arch/micro_asm.py
@@ -24,8 +24,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
-
 import os
 import sys
 import re
diff --git a/src/arch/micro_asm_test.py b/src/arch/micro_asm_test.py
index e34e06e..8bab7b9 100755
--- a/src/arch/micro_asm_test.py
+++ b/src/arch/micro_asm_test.py
@@ -24,8 +24,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
-
 from micro_asm import MicroAssembler, Combinational_Macroop, Rom_Macroop,  
Rom


 class Bah(object):
diff --git a/src/arch/x86/isa/microops/fpop.isa  
b/src/arch/x86/isa/microops/fpop.isa

index 238fa93..346f0d6 100644
--- a/src/arch/x86/isa/microops/fpop.isa
+++ b/src/arch/x86/isa/microops/fpop.isa
@@ -105,8 +105,6 @@

 let {{

-import six
-
 # Make these empty strings so that concatenating onto
 # them will always work.
 header_output = ""
@@ -199,8 +197,7 @@

 return cls

-@six.add_metaclass(FpOpMeta)
-class FpUnaryOp(X86Microop):
+class FpUnaryOp(X86Microop, metaclass=FpOpMeta):
 # This class itself doesn't act as a microop
 abstract = True

@@ -235,8 +232,7 @@
 "dataSize" : self.dataSize,
 "spm" : self.spm}

-@six.add_metaclass(FpOpMeta)
-class FpBinaryOp(X86Microop):
+class FpBinaryOp(X86Microop, metaclass=FpOpMeta):
 # This class itself doesn't act as a microop
 abstract = True

diff --git a/src/arch/x86/isa/microops/limmop.isa  
b/src/arch/x86/isa/microops/limmop.isa

index b46be03..51310b4 100644
--- a/src/arch/x86/isa/microops/limmop.isa
+++ b/src/arch/x86/isa/microops/limmop.isa
@@ -106,16 +106,12 @@
 }};

 let {{
-import six
-if six.PY3:
-long = int
-
 class LimmOp(X86Microop):
 def __init__(self, dest, imm, dataSize="env.dataSize"):
 self.className = "Limm"
 self.mnemonic = "limm"
 self.dest = dest
-if isinstance(imm, (int, long)):
+if isinstance(imm, int):
 imm = "ULL(%d)" % imm
 self.imm = imm
 self.dataSize = dataSize
@@ -145,7 +141,7 @@
 self.className = "Lfpimm"
 self.mnemonic = "lfpimm"
 self.dest = dest
-if isinstance(imm, (int, long)):
+if isinstance(imm, int):
 imm = "ULL(%d)" % imm
 elif isinstance(imm, float):
 imm = "floatToBits64(%.16f)" % imm
diff --git a/src/arch/x86/isa/microops/mediaop.isa  
b/src/arch/x86/isa/microops/mediaop.isa

index 7e5fd10..e149d44 100644
--- a/src/arch/x86/isa/microops/mediaop.isa
+++ b/src/arch/x86/isa/microops/mediaop.isa
@@ -202,8 +202,7 @@
 return cls


-@six.add_metaclass(MediaOpMeta)
-class MediaOp(X86Microop):
+class MediaOp(X86Microop, metaclass=MediaOpMeta):
 # This class itself doesn't act as a microop
 abstract = True

diff --git a/src/arch/x86/isa/microops/regop.isa  
b/src/arch/x86/isa/microops/regop.isa

index da1f9ae..c465dcc 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -416,8 +416,7 @@
 return c

[gem5-dev] Change in gem5/gem5[develop]: util: Remove Python 2.7 glue code

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39756 )



Change subject: util: Remove Python 2.7 glue code
..

util: Remove Python 2.7 glue code

Remove uses of six and from __future__ imports as they are no longer
needed.

Change-Id: I8d6aae84d8192b301d541b8dc81275f4932f9f2f
Signed-off-by: Andreas Sandberg 
---
M util/build_cross_gcc/build_cross_gcc.py
M util/cpt_upgrader.py
M util/style/verifiers.py
3 files changed, 8 insertions(+), 18 deletions(-)



diff --git a/util/build_cross_gcc/build_cross_gcc.py  
b/util/build_cross_gcc/build_cross_gcc.py

index 51f7fcc..3afd4bf 100755
--- a/util/build_cross_gcc/build_cross_gcc.py
+++ b/util/build_cross_gcc/build_cross_gcc.py
@@ -32,7 +32,6 @@
 import os.path
 import pickle
 import shutil
-import six
 import subprocess
 import textwrap

@@ -145,9 +144,9 @@
 # Settings.
 #

-class MetaSetting(type):
+class MetaSetting(abc.ABCMeta):
 def __new__(mcls, name, bases, d):
-cls = super(MetaSetting, mcls).__new__(mcls, name, bases, d)
+cls = super().__new__(mcls, name, bases, d)
 key = d.get('key', None)
 if key is not None:
 assert('default' in d)
@@ -157,9 +156,7 @@
 all_settings[key] = instance
 return cls

-@six.add_metaclass(MetaSetting)
-@six.add_metaclass(abc.ABCMeta)
-class Setting(object):
+class Setting(object, metaclass=MetaSetting):
 key = None

 @abc.abstractmethod
@@ -420,17 +417,15 @@
 # Steps of the build process.
 #

-class MetaStep(type):
+class MetaStep(abc.ABCMeta):
 def __new__(mcls, name, bases, d):
-cls = super(MetaStep, mcls).__new__(mcls, name, bases, d)
+cls = super().__new__(mcls, name, bases, d)
 number = d.get('number', None)
 if number is not None:
 all_steps[number] = cls()
 return cls

-@six.add_metaclass(MetaStep)
-@six.add_metaclass(abc.ABCMeta)
-class Step(object):
+class Step(object, metaclass=MetaStep):
 'Steps to set up a cross compiling gcc.'
 number = None

diff --git a/util/cpt_upgrader.py b/util/cpt_upgrader.py
index 9964aac..15dc2ab 100755
--- a/util/cpt_upgrader.py
+++ b/util/cpt_upgrader.py
@@ -69,8 +69,7 @@
 # upgraders in private branches.


-
-from six.moves import configparser
+import configparser
 import glob, types, sys, os
 import os.path as osp

diff --git a/util/style/verifiers.py b/util/style/verifiers.py
index 7d27fda..798ddfc 100644
--- a/util/style/verifiers.py
+++ b/util/style/verifiers.py
@@ -47,8 +47,6 @@
 import re
 import sys

-from six import add_metaclass
-
 from . import style
 from . import sort_includes
 from .region import *
@@ -102,8 +100,7 @@
 return regions


-@add_metaclass(ABCMeta)
-class Verifier(object):
+class Verifier(object, metaclass=ABCMeta):
 """Base class for style verifiers

 Verifiers check for style violations and optionally fix such
@@ -224,7 +221,6 @@
 """
 pass

-@add_metaclass(ABCMeta)
 class LineVerifier(Verifier):
 def check(self, filename, regions=all_regions, fobj=None,  
silent=False):

 close = False

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8d6aae84d8192b301d541b8dc81275f4932f9f2f
Gerrit-Change-Number: 39756
Gerrit-PatchSet: 1
Gerrit-Owner: Andreas Sandberg 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: riscv: Export the system call ABI for use in gem5 ops.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39318 )


Change subject: riscv: Export the system call ABI for use in gem5 ops.
..

riscv: Export the system call ABI for use in gem5 ops.

This ABI is effectively used by both the gem5 ops and system calls, in
system calls because it only relies on registers, and in gem5 ops by
inheritance.

Even though these ABIs happen to be the same and were initially defined
to be the same, this change creates a root "reg" ABI which will act as a
root for both so that there isn't an implication that changes to one
should be changes to both.

Change-Id: I8726d8628503be2ad7616a71cc48b66f13e7d955
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39318
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Ayaz Akram 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/arch/riscv/SConscript
M src/arch/riscv/isa/formats/m5ops.isa
M src/arch/riscv/isa/includes.isa
R src/arch/riscv/reg_abi.cc
C src/arch/riscv/reg_abi.hh
M src/arch/riscv/registers.hh
M src/arch/riscv/se_workload.hh
7 files changed, 23 insertions(+), 22 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve
  Ayaz Akram: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/riscv/SConscript b/src/arch/riscv/SConscript
index 0179fbc..472264f 100644
--- a/src/arch/riscv/SConscript
+++ b/src/arch/riscv/SConscript
@@ -51,8 +51,8 @@
 Source('process.cc')
 Source('pagetable.cc')
 Source('pagetable_walker.cc')
+Source('reg_abi.cc')
 Source('remote_gdb.cc')
-Source('se_workload.cc')
 Source('tlb.cc')

 Source('linux/se_workload.cc')
diff --git a/src/arch/riscv/isa/formats/m5ops.isa  
b/src/arch/riscv/isa/formats/m5ops.isa

index 11834f6..986438b 100644
--- a/src/arch/riscv/isa/formats/m5ops.isa
+++ b/src/arch/riscv/isa/formats/m5ops.isa
@@ -36,12 +36,11 @@


 def format M5Op() {{
-iop = InstObjParams(name, Name, 'PseudoOp',
-'uint64_t result;\n'
-'PseudoInst::pseudoInst('
-'xc->tcBase(), M5FUNC, result);\n'
-'a0 = result',
-['IsNonSpeculative', 'IsSerializeAfter'])
+iop = InstObjParams(name, Name, 'PseudoOp', '''
+uint64_t result;
+PseudoInst::pseudoInst(xc->tcBase(), M5FUNC, result);
+a0 = result''',
+['IsNonSpeculative', 'IsSerializeAfter'])
 header_output = BasicDeclare.subst(iop)
 decoder_output = BasicConstructor.subst(iop)
 decode_block = BasicDecode.subst(iop)
diff --git a/src/arch/riscv/isa/includes.isa  
b/src/arch/riscv/isa/includes.isa

index d77d68e..799559a 100644
--- a/src/arch/riscv/isa/includes.isa
+++ b/src/arch/riscv/isa/includes.isa
@@ -81,6 +81,7 @@
 #include "arch/generic/memhelpers.hh"
 #include "arch/riscv/faults.hh"
 #include "arch/riscv/mmu.hh"
+#include "arch/riscv/reg_abi.hh"
 #include "arch/riscv/registers.hh"
 #include "arch/riscv/utility.hh"
 #include "base/condcodes.hh"
diff --git a/src/arch/riscv/se_workload.cc b/src/arch/riscv/reg_abi.cc
similarity index 91%
rename from src/arch/riscv/se_workload.cc
rename to src/arch/riscv/reg_abi.cc
index ce4679c..25aee6f 100644
--- a/src/arch/riscv/se_workload.cc
+++ b/src/arch/riscv/reg_abi.cc
@@ -25,13 +25,11 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */

-#include "arch/riscv/se_workload.hh"
+#include "arch/riscv/reg_abi.hh"

 namespace RiscvISA
 {

-const std::vector SEWorkload::SyscallABI::ArgumentRegs = {
-10, 11, 12, 13, 14, 15, 16
-};
+const std::vector RegABI64::ArgumentRegs = {10, 11, 12, 13, 14, 15,  
16};


 } // namespace RiscvISA
diff --git a/src/arch/riscv/se_workload.cc b/src/arch/riscv/reg_abi.hh
similarity index 82%
copy from src/arch/riscv/se_workload.cc
copy to src/arch/riscv/reg_abi.hh
index ce4679c..492c117 100644
--- a/src/arch/riscv/se_workload.cc
+++ b/src/arch/riscv/reg_abi.hh
@@ -25,13 +25,22 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */

-#include "arch/riscv/se_workload.hh"
+#ifndef __ARCH_RISCV_REG_ABI_HH__
+#define __ARCH_RISCV_REG_ABI_HH__
+
+#include 
+
+#include "sim/syscall_abi.hh"

 namespace RiscvISA
 {

-const std::vector SEWorkload::SyscallABI::ArgumentRegs = {
-10, 11, 12, 13, 14, 15, 16
+//FIXME RISCV needs to handle 64 bit arguments in its 32 bit ISA.
+struct RegABI64 : public GenericSyscallABI64
+{
+static const std::vector ArgumentRegs;
 };

 } // namespace RiscvISA
+
+#endif // __ARCH_RISCV_REG_ABI_HH__
diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh
index 84a1924..9721635 100644
--- a/src/arch/riscv/registers.hh
+++ b/src/arch/riscv/registers.hh
@@ -93,11 +93,8 @@
 const int ZeroReg = 0;
 const int ReturnAddrReg = 1;
 const int StackPointerReg = 2;
-const int Glo

[gem5-dev] Change in gem5/gem5[develop]: python: Require a unit in anyToFrequency and anyToLatency

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39435 )


Change subject: python: Require a unit in anyToFrequency and anyToLatency
..

python: Require a unit in anyToFrequency and anyToLatency

The anytToFrequency and anyToLatency conversion functions are
currently ambiguous when called without a unit. Fix this by always
requiring a unit.

Change-Id: I5ea94e655f7ca82c0efe70b9f9f7f734fbf711c1
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39435
Tested-by: kokoro 
Reviewed-by: Daniel Carvalho 
---
M src/python/m5/util/convert.py
M tests/pyunit/util/test_convert.py
2 files changed, 32 insertions(+), 34 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/python/m5/util/convert.py b/src/python/m5/util/convert.py
index 1d78f82..e66eb5c 100644
--- a/src/python/m5/util/convert.py
+++ b/src/python/m5/util/convert.py
@@ -199,32 +199,40 @@
 return toMetricFloat(value, 'latency', 's')

 def anyToLatency(value):
-"""result is a clock period"""
-try:
-return 1 / toFrequency(value)
-except (ValueError, ZeroDivisionError):
-pass
+"""Convert a magnitude and unit to a clock period."""

-try:
-return toLatency(value)
-except ValueError:
-pass
-
-raise ValueError("cannot convert '%s' to clock period" % value)
+magnitude, unit = toNum(value,
+target_type='latency',
+units=('Hz', 's'),
+prefixes=metric_prefixes,
+converter=float)
+if unit == 's':
+return magnitude
+elif unit == 'Hz':
+try:
+return 1.0 / magnitude
+except ZeroDivisionError:
+raise ValueError(f"cannot convert '{value}' to clock period")
+else:
+raise ValueError(f"'{value}' needs a valid unit to be  
unambiguous.")


 def anyToFrequency(value):
-"""result is a clock period"""
-try:
-return toFrequency(value)
-except ValueError:
-pass
+"""Convert a magnitude and unit to a clock frequency."""

-try:
-return 1 / toLatency(value)
-except ValueError as ZeroDivisionError:
-pass
-
-raise ValueError("cannot convert '%s' to clock period" % value)
+magnitude, unit = toNum(value,
+target_type='frequency',
+units=('Hz', 's'),
+prefixes=metric_prefixes,
+converter=float)
+if unit == 'Hz':
+return magnitude
+elif unit == 's':
+try:
+return 1.0 / magnitude
+except ZeroDivisionError:
+raise ValueError(f"cannot convert '{value}' to frequency")
+else:
+raise ValueError(f"'{value}' needs a valid unit to be  
unambiguous.")


 def toNetworkBandwidth(value):
 return toMetricFloat(value, 'network bandwidth', 'bps')
diff --git a/tests/pyunit/util/test_convert.py  
b/tests/pyunit/util/test_convert.py

index a9c9d46..da61843 100644
--- a/tests/pyunit/util/test_convert.py
+++ b/tests/pyunit/util/test_convert.py
@@ -163,28 +163,18 @@
 self.assertEqual(conv('1kHz'), 1e-3)

 self.assertRaises(ValueError, conv, '42k')
-
-@unittest.expectedFailure
-def test_anyToLatency_ambiguous(self):
-# This the behavior of anyToFrequency is currently ambiguous
-# (and surprising) for unitless quantities. The following
-# should be true to be consistent with the other conversion
-# functions, but that isn't currently the case.
-self.assertEqual(convert.anyToLatency('42'), 42.0)
-
+self.assertRaises(ValueError, conv, '42')

 def test_anyToFrequency(self):
 conv = convert.anyToFrequency

-# This is ambiguous and should probably not be allowed.
-self.assertEqual(conv('42'), 42.0)
-
 self.assertEqual(conv('42kHz'), 42e3)

 self.assertEqual(conv('0.1s'), 10.0)
 self.assertEqual(conv('1ms'), 1000.0)

 self.assertRaises(ValueError, conv, '42k')
+self.assertRaises(ValueError, conv, '42')

 def test_toNetworkBandwidth(self):
 conv = convert.toNetworkBandwidth

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I5ea94e655f7ca82c0efe70b9f9f7f734fbf711c1
Gerrit-Change-Number: 39435
Gerrit-PatchSet: 6
Gerrit-Owner: Andreas Sandberg 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Revi

[gem5-dev] Change in gem5/gem5[develop]: base, python: Add a Temperature type and associated param

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39218 )


Change subject: base, python: Add a Temperature type and associated param
..

base, python: Add a Temperature type and associated param

Add a class to represent a temperature. The class stores temperatures
in Kelvin and provides helper methods to convert to/from Celsius. The
corresponding param type automatically converts from Kelvin, Celsius,
and Fahrenheit to the underlying C++ type.

Change-Id: I5783cc4f4fecbea5aba9821dfc71bfa77c3f75a9
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39218
Maintainer: Jason Lowe-Power 
Reviewed-by: Daniel Carvalho 
Reviewed-by: Gabe Black 
Tested-by: kokoro 
---
M src/base/SConscript
A src/base/temperature.cc
A src/base/temperature.hh
A src/base/temperature.test.cc
M src/python/m5/params.py
M src/python/m5/util/convert.py
M src/python/pybind11/core.cc
M tests/pyunit/util/test_convert.py
8 files changed, 478 insertions(+), 2 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/base/SConscript b/src/base/SConscript
index 3937314..204ed3c 100644
--- a/src/base/SConscript
+++ b/src/base/SConscript
@@ -72,6 +72,8 @@
 GTest('str.test', 'str.test.cc', 'str.cc')
 Source('time.cc')
 Source('version.cc')
+Source('temperature.cc')
+GTest('temperature.test', 'temperature.test.cc', 'temperature.cc')
 Source('trace.cc')
 GTest('trie.test', 'trie.test.cc')
 Source('types.cc')
diff --git a/src/base/temperature.cc b/src/base/temperature.cc
new file mode 100644
index 000..b1d9c9a
--- /dev/null
+++ b/src/base/temperature.cc
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2021 Arm Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "base/temperature.hh"
+
+Temperature
+Temperature::fromKelvin(double _value)
+{
+return Temperature(_value);
+}
+
+Temperature
+Temperature::fromCelsius(double _value)
+{
+return Temperature(273.15 + _value);
+}
+
+Temperature
+Temperature::fromFahrenheit(double _value)
+{
+return Temperature((_value + 459.67) / 1.8);
+}
+
+double
+Temperature::toFahrenheit() const
+{
+return value * 1.8 - 459.67;
+}
+
+std::ostream &
+operator<<(std::ostream &out, const Temperature &temp)
+{
+out << temp.value << "K";
+return out;
+}
diff --git a/src/base/temperature.hh b/src/base/temperature.hh
new file mode 100644
index 000..bcb5199
--- /dev/null
+++ b/src/base/temperature.hh
@@ -0,0 +1,176 @@
+/*
+ * Copyright (c) 2021 Arm Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to int

[gem5-dev] Change in gem5/gem5[develop]: sim: Use the Temperature param type

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39219 )


Change subject: sim: Use the Temperature param type
..

sim: Use the Temperature param type

Add support for passing typed temperatures using the new Temperature
param type.

Change-Id: If68d619fd824e171d895a5cbbe4d0325d4c4f4db
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39219
Tested-by: kokoro 
Reviewed-by: Gabe Black 
Reviewed-by: Daniel Carvalho 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M src/sim/power/PowerModel.py
M src/sim/power/ThermalDomain.py
M src/sim/power/ThermalModel.py
M src/sim/power/power_model.cc
M src/sim/power/thermal_domain.cc
M src/sim/power/thermal_model.cc
6 files changed, 11 insertions(+), 11 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Daniel Carvalho: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/sim/power/PowerModel.py b/src/sim/power/PowerModel.py
index 2047c64..cfbd8cb 100644
--- a/src/sim/power/PowerModel.py
+++ b/src/sim/power/PowerModel.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2016-2018 ARM Limited
+# Copyright (c) 2016-2018, 2021 Arm Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -63,4 +63,4 @@
 pm_type = Param.PMType("All", "Type of power model")

 # Ambient temperature to be used when no thermal model is present
-ambient_temp = Param.Float(25.0, "Ambient temperature")
+ambient_temp = Param.Temperature("25.0C", "Ambient temperature")
diff --git a/src/sim/power/ThermalDomain.py b/src/sim/power/ThermalDomain.py
index 3fd5cad..57c53b2 100644
--- a/src/sim/power/ThermalDomain.py
+++ b/src/sim/power/ThermalDomain.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2015 ARM Limited
+# Copyright (c) 2015, 2021 Arm Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -46,4 +46,4 @@
 ]

 # Static temperature which may change over time
-initial_temperature = Param.Float(25.0, "Initial temperature")
+initial_temperature = Param.Temperature("25.0C", "Initial temperature")
diff --git a/src/sim/power/ThermalModel.py b/src/sim/power/ThermalModel.py
index 2894dd8..90710e1 100644
--- a/src/sim/power/ThermalModel.py
+++ b/src/sim/power/ThermalModel.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2015 ARM Limited
+# Copyright (c) 2015, 2021 Arm Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -77,7 +77,7 @@
 ]

 # Static temperature which may change over time
-temperature = Param.Float(25.0, "Operational temperature in Celsius")
+temperature = Param.Temperature("25.0C", "Operational temperature")


 # Represents a thermal capacitor
diff --git a/src/sim/power/power_model.cc b/src/sim/power/power_model.cc
index fbc67d3..42515ac 100644
--- a/src/sim/power/power_model.cc
+++ b/src/sim/power/power_model.cc
@@ -66,7 +66,7 @@
 // The temperature passed here will be overwritten, if there is
 // a thermal model present
 for (auto & pms: states_pm){
-pms->setTemperature(p.ambient_temp);
+pms->setTemperature(p.ambient_temp.toCelsius());
 }

 dynamicPower
diff --git a/src/sim/power/thermal_domain.cc  
b/src/sim/power/thermal_domain.cc

index a5eb33c..b0868be 100644
--- a/src/sim/power/thermal_domain.cc
+++ b/src/sim/power/thermal_domain.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015 ARM Limited
+ * Copyright (c) 2015, 2021 Arm Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -49,7 +49,7 @@
 #include "sim/sub_system.hh"

 ThermalDomain::ThermalDomain(const Params &p)
-: SimObject(p), _initTemperature(p.initial_temperature),
+: SimObject(p), _initTemperature(p.initial_temperature.toCelsius()),
 node(NULL), subsystem(NULL),
 ADD_STAT(currentTemp, "Temperature in centigrade degrees")
 {
diff --git a/src/sim/power/thermal_model.cc b/src/sim/power/thermal_model.cc
index a37240b..c57e284 100644
--- a/src/sim/power/thermal_model.cc
+++ b/src/sim/power/thermal_model.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015 ARM Limited
+ * Copyright (c) 2015, 2021 Arm Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -51,7 +51,7 @@
  * ThermalReference
  */
 ThermalReference::ThermalReference(const Params &p)
-: SimObject(p), _temperature(p.temperature), node(NULL)
+: SimObject(p), _temperature(p.temperature.toCelsius()), node(NULL)
 {
 }


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Gerrit-Project: public/gem5
Gerrit-Branch: develop