Hi Gabe,
I don't know much about the port extraction in gem5, so I don't really
have a comment here, but I can say a few things about connecting systemc
and gem5 objects.
>>> I'm thinking there are two different ways to do this. The first would be
>>> to make a systemc interface type which is
Hi,
I am following the discussion for a while now and finally found the time
to look at Gabe's proposal.
As I see it, there are three approaches for combining gem5 and SystemC
as outlined below. (Sorry for repeating stuff that was mentioned before,
I just find it helpful to summarize some
: I59ec4755917288c56b981031a5fb6fd003b7288e
Gerrit-Change-Number: 7541
Gerrit-PatchSet: 4
Gerrit-Owner: Christian Menard <christian.men...@tu-dresden.de>
Gerrit-Reviewer: B.A. Zeeb <ba...@cam.ac.uk>
Gerrit-Reviewer: Christian Menard <christian.men...@tu-dresden.de>
Gerrit-Reviewer:
Christian Menard has submitted this change and it was merged. (
https://gem5-review.googlesource.com/7701 )
Change subject: arch-x86: consistent style of comments in system files
..
arch-x86: consistent style of comments
: I59ec4755917288c56b981031a5fb6fd003b7288e
Gerrit-Change-Number: 7541
Gerrit-PatchSet: 3
Gerrit-Owner: Christian Menard <christian.men...@tu-dresden.de>
Gerrit-Reviewer: B.A. Zeeb <ba...@cam.ac.uk>
Gerrit-Reviewer: Christian Menard <christian.men...@tu-dresden.de>
Gerrit-Reviewer:
Christian Menard has uploaded this change for review. (
https://gem5-review.googlesource.com/7701
Change subject: arch-x86: consistent style of comments in system files
..
arch-x86: consistent style of comments in system
Christian Menard has submitted this change and it was merged. (
https://gem5-review.googlesource.com/7601 )
Change subject: arch-x86: Granularity bit and segment limit
..
arch-x86: Granularity bit and segment limit
If set
tself
>> in the name of what it's going to run to instead having a workload which
>> knows how to set things up for itself, more like how a gem5 process
>> instance sets up for itself on initialization. That would bring things more
>> in line between FS and SE, and would
at least that aspect of it) isn't
> how it should be done.
>
> Gabe
>
> On Mon, Jan 22, 2018 at 9:46 AM, Christian Menard <
> christian.men...@tu-dresden.de> wrote:
>
>> Hi everybody,
>>
>> I have some old patches lying around that extend the x8
Hi everybody,
I have some old patches lying around that extend the x86 system by
support for the Multiboot boot sequence standard [1]. Maximilian (CC)
currently uses these patches for his work and recently rebased them to
the current gem5. He uploaded them to gerrit as a single patch for
review
finition or on how
> to implement certain kinds of instructions, I'd be happy to help.
>
> -Alec Roelke
>
> On Thu, Jan 11, 2018 at 4:37 AM, Christian Menard <
> christian.men...@tu-dresden.de> wrote:
>
>> Hi all,
>>
>> I have a student who is intere
that might be in the
way? Do you have an idea on what would be a good way to implement custom
instructions for RISC-V?
Cheers,
Christian
--
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Research Assistant
TU Dresden
Faculty of Computer Science
Chair for Compiler Construction
01062 Dresden
Phone: +49 351 463-42441
e
Christian Menard has uploaded this change for review. (
https://gem5-review.googlesource.com/5441
Change subject: misc: Add function to check if a TLM target can receive a
timing req.
..
misc: Add function to check
Hi Yasir,
as far as I know heterogeneous ISAs is not supported and will not be supported
anytime soon. However, there are workarounds. For instance, you can use the
TLM bridge to connect two (or more) gem5 systems to each other. This requires
some tricks and linker magic, but it works. I was
for using
the TLM-Bridge. If you implement an accelerator from scratch, why don't you do
so in gem5 directly? Why do you need the TLM bridge?
I saw your e-mails on 'SystemC and GEM5 SE Mode' and will look into this issue
when I find the time.
Best regards,
Christian Menard
On Monday, 19 June 2017
Christian Menard has submitted this change and it was merged. (
https://gem5-review.googlesource.com/3480 )
Change subject: misc: Reorder sources in util/tlm and rewrite build scripts
..
misc: Reorder sources in util/tlm
Christian Menard has submitted this change and it was merged. (
https://gem5-review.googlesource.com/3482 )
Change subject: misc: check address range in the SystemC example
..
misc: check address range in the SystemC example
: I641ed94f542626864fb7af499ad1be8fd4ad929f
Gerrit-Change-Number: 3480
Gerrit-PatchSet: 5
Gerrit-Owner: Christian Menard <christian.men...@tu-dresden.de>
Gerrit-Reviewer: Christian Menard <christian.men...@tu-dresden.de>
Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-Reviewer: Matthias Jung <
Christian Menard has uploaded this change for review. (
https://gem5-review.googlesource.com/3482
Change subject: misc: check address range in the SystemC example
..
misc: check address range in the SystemC example
Using
: I641ed94f542626864fb7af499ad1be8fd4ad929f
Gerrit-Change-Number: 3480
Gerrit-PatchSet: 4
Gerrit-Owner: Christian Menard <christian.men...@tu-dresden.de>
Gerrit-Reviewer: Christian Menard <christian.men...@tu-dresden.de>
Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-Reviewer: Matthias Jung <
Christian Menard has uploaded a new patch set (#2). (
https://gem5-review.googlesource.com/3480 )
Change subject: misc: Reorder sources in util/tlm and rewrite build scripts
..
misc: Reorder sources in util/tlm and rewrite
Christian Menard has uploaded this change for review. (
https://gem5-review.googlesource.com/3480
Change subject: misc: Reorder sources in util/tlm and rewrite build scripts
..
misc: Reorder sources in util/tlm and rewrite
nd similarly the assembly
> file shouldn't be required when building on ARM with pthreads.
>
> Gabe
> ___
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R
changeset 4d1f9823013a in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=4d1f9823013a
description:
misc: Clean up and complete the gem5<->SystemC-TLM bridge [6/10]
The current TLM bridge only provides a Slave Port that allows the gem5
world to send
he diff anyway and hope it works now.
- Christian
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-------
actors and cleans up
the existing code, and adds a Master Port that allows the SystemC world to send
requests to the gem5 world.
This patch:
* Update the README
Diffs (updated)
-
util/tlm/README c10c50cb8ac9
Diff: http://reviews.gem5.org/r/3777/diff/
Testing
---
Thanks,
Chr
changeset 2a5b4e334f7d in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=2a5b4e334f7d
description:
misc: Clean up and complete the gem5<->SystemC-TLM bridge [9/10]
The current TLM bridge only provides a Slave Port that allows the gem5
world to send
changeset 2191b87e3b47 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=2191b87e3b47
description:
misc: fix includes in util/systemc
This fixes compilation errors with clang on OS X.
Reviewed at http://reviews.gem5.org/r/3807/
Signed-off-by:
changeset 3de6ee321c3e in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=3de6ee321c3e
description:
misc: Clean up and complete the gem5<->SystemC-TLM bridge [3/10]
The current TLM bridge only provides a Slave Port that allows the gem5
world to send
UPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Christian Menard
+ */
+
+#include
BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Christian Menard
19:14:58 2017 -0500
@@ -35,8 +35,10 @@
#
# Authors: Andrew Bardsley
# Curtis Dunham
+# Christian Menard
from m5.params import *
+from m5.proxy import *
from MemObject import MemObject
class ExternalMaster(MemObject):
@@ -50,3 +52,5 @@
port_data = Param.String
BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE
changeset 77ab27b06d62 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=77ab27b06d62
description:
misc: Clean up and complete the gem5<->SystemC-TLM bridge [7/10]
The current TLM bridge only provides a Slave Port that allows the gem5
world to send
ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Christian Menard
+
+import os
+
+gem5_arch = 'ARM'
+gem5_variant = 'opt'
+#gem5_variant = 'debug'
+
+gem5_root = '#../../../..'
+
+target = 'gem5.' + gem5_variant + '.sc'
+
+env = Environment()
+
+# Impor
changeset 9487cdff1bc3 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=9487cdff1bc3
description:
misc: Clean up and complete the gem5<->SystemC-TLM bridge [8/10]
The current TLM bridge only provides a Slave Port that allows the gem5
world to send
ystemc/sc_module.cc Thu Feb 09 19:03:58 2017 -0500
+++ b/util/systemc/sc_module.cc Thu Feb 09 19:10:25 2017 -0500
@@ -43,6 +43,7 @@
* Steve Reinhardt
* Andrew Bardsley
* Matthias Jung
+ * Christian Menard
*/
/**
@@ -77,7 +78,7 @@
::setClockFre
changeset 8caffc398ae7 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=8caffc398ae7
description:
misc: Fix order of object construction in the CxxConfigManager
The CxxConfigManager schould create objects by traversing the object
tree
starting from
changeset b20a1364e019 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=b20a1364e019
description:
misc: Clean up and complete the gem5<->SystemC-TLM bridge [10/10]
The current TLM bridge only provides a Slave Port that allows the gem5
world to send
cb8ac9
util/tlm/run_gem5.sh c10c50cb8ac9
Diff: http://reviews.gem5.org/r/3527/diff/
Testing
---
The examples provided in util/tlm (now util/tlm/examples/slave_port) still
compile and run error free.
Thanks,
Christian Menard
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11809:54adb162f4ea
---
misc: fix includes in util/systemc
This fixes compilation errors with clang on OS X.
Diffs
-
util/systemc/sc_module.cc c10c50cb8ac9
Diff: http://reviews.gem5.org/r/3807/diff/
Testing
---
Thanks,
Christian Menard
t are called at before and after
simulate()
Diffs
-
util/tlm/sim_control.hh PRE-CREATION
util/tlm/sim_control.cc PRE-CREATION
Diff: http://reviews.gem5.org/r/3799/diff/
Testing
---
Thanks,
Christian Menard
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ar annotates to packets.
Diffs
-
util/tlm/sc_master_port.cc PRE-CREATION
util/tlm/sc_slave_port.cc PRE-CREATION
Diff: http://reviews.gem5.org/r/3798/diff/
Testing
---
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handled when END_REQ was skipped
and ' == blockingRequest && phase == tlm::BEGIN_RESP'
evaluates to true.
Diffs
-
util/tlm/sc_slave_port.cc PRE-CREATION
Diff: http://reviews.gem5.org/r/3797/diff/
Testing
---
Thank
lm/sc_ext.cc c10c50cb8ac9
util/tlm/sc_master_port.hh PRE-CREATION
util/tlm/sc_master_port.cc PRE-CREATION
util/tlm/sc_slave_port.cc PRE-CREATION
Diff: http://reviews.gem5.org/r/3796/diff/
Testing
---
Thanks,
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/r/3775/diff/
Testing
---
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r and a gem5
memory is part of the patch.
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iator_socket.
Diffs
-
util/tlm/sc_slave_port.hh PRE-CREATION
util/tlm/sc_slave_port.cc PRE-CREATION
Diff: http://reviews.gem5.org/r/3686/diff/
Testing
---
Example applications are still running.
Thanks,
Christian Menard
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ill
compile and run error free.
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Christian Menard
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tlm/examples/slave_port/SConstruct PRE-CREATION
util/tlm/examples/slave_port/main.cc PRE-CREATION
Diff: http://reviews.gem5.org/r/3695/diff/
Testing
---
Examples compile and run.
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util/tlm/README c10c50cb8ac9
Diff: http://reviews.gem5.org/r/3777/diff/
Testing
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/sc_module.hh c10c50cb8ac9
Diff: http://reviews.gem5.org/r/3774/diff/
Testing
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actors and cleans up
the existing code, and adds a Master Port that allows the SystemC world to send
requests to the gem5 world.
This patch:
* Update the README
Diffs (updated)
-
util/tlm/README c10c50cb8ac9
Diff: http://reviews.gem5.org/r/3777/diff/
Testing
---
Thanks,
Christian
ct PRE-CREATION
util/tlm/examples/master_port/main.cc PRE-CREATION
Diff: http://reviews.gem5.org/r/3528/diff/
Testing
---
A simple example application consisting of a TLM traffic generator and a gem5
memory is part of the patch.
Thanks,
Christian
actors and cleans up
the existing code, and adds a Master Port that allows the SystemC world to send
requests to the gem5 world.
This patch:
* Update the README
Diffs (updated)
-
util/tlm/README c10c50cb8ac9
Diff: http://reviews.gem5.org/r/3777/diff/
Testing
---
Thanks,
Chr
s is an automatically generated e-mail. To reply, visit:
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-------
On Feb. 2, 2017, 11:23 a.m., Christian Menard wrote:
>
> ---
> This is an automatically generated e-mail. To reply, visit:
&
il/tlm/master_transactor.cc PRE-CREATION
util/tlm/sc_master_port.hh PRE-CREATION
util/tlm/sc_master_port.cc PRE-CREATION
util/tlm/sc_slave_port.hh PRE-CREATION
Diff: http://reviews.gem5.org/r/3775/diff/
Testing
---
Thanks,
Christian
> On Jan. 31, 2017, 4:10 p.m., Jason Lowe-Power wrote:
> > I don't follow why you don't need to pay for the payload delay. Is that
> > taken care of at some other point in the System-C model?
>
> Christian Menard wrote:
> Simply paying for the payload delay in the t
rg/r/3799/#review9356
---
On Jan. 31, 2017, 10:58 a.m., Christian Menard wrote:
>
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3799/
> ---
798/#review9355
---
On Jan. 30, 2017, 4:40 p.m., Christian Menard wrote:
>
> ---
> This is an automatically generated e-mail. To reply, visit:
> htt
or BEGIN_RESP should
be sent.
[1] http://reviews.gem5.org/r/3796/
[2] http://reviews.gem5.org/r/3797/
[3] http://reviews.gem5.org/r/3798/
[4] http://reviews.gem5.org/r/3799/
Cheers,
Christian
On Wednesday, 11 January 2017 13:45:46 CET Christian Menard wrote:
> Hi Andreas,
>
&g
: http://reviews.gem5.org/r/3799/diff/
Testing
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Testing
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when END_REQ was skipped
and ' == blockingRequest && phase == tlm::BEGIN_RESP'
evaluates to true.
Diffs
-
util/tlm/sc_slave_port.cc PRE-CREATION
Diff: http://reviews.gem5.org/r/3797/diff/
Testing
---
Thank
: http://reviews.gem5.org/r/3796/diff/
Testing
---
Thanks,
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il/tlm/sim_control_if.hh PRE-CREATION
util/tlm/slave_transactor.hh PRE-CREATION
util/tlm/slave_transactor.cc PRE-CREATION
Diff: http://reviews.gem5.org/r/3775/diff/
Testing
---
Thanks,
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gem5-dev@gem5.or
cc PRE-CREATION
Diff: http://reviews.gem5.org/r/3686/diff/
Testing
---
Example applications are still running.
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util/tlm/examples/master_port/traffic_generator.cc PRE-CREATION
Diff: http://reviews.gem5.org/r/3528/diff/
Testing
---
A simple example application consisting of a TLM traffic generator and a gem5
memory is part of the patch.
Thanks,
Christian
EATION
util/tlm/sc_master_port.cc PRE-CREATION
Diff: http://reviews.gem5.org/r/3775/diff/
Testing
---
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il/tlm/sim_control.hh PRE-CREATION
util/tlm/sc_slave_port.cc PRE-CREATION
util/tlm/sc_master_port.cc PRE-CREATION
Diff: http://reviews.gem5.org/r/3775/diff/
Testing
---
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Ship it!
Ship It!
- Christian Menard
On Dec. 16, 2016, 4:24 p.m
the fields. That way we 1) put the delays closer to where they really
> should occur, and 2) avoid having to remember what packet should have what
> delay fields.
>
> Does that make sense?
>
> Andreas
>
> On 09/01/2017, 13:58, "Christian Menard" <christian.men...
] http://www.mail-archive.com/gem5-dev@gem5.org/msg21318.html
[12] http://reviews.gem5.org/r/3778/
--
Dipl.-Ing. Christian Menard
Research Assistant
TU Dresden
Faculty of Computer Science
Chair for Compiler Construction
01062 Dresden
Phone: +49 351 463-42441
e-Mail: christian.men...@tu-dres
the bug by removing the alphabetical ordering.
Diffs
-
src/sim/cxx_manager.cc c10c50cb8ac9
Diff: http://reviews.gem5.org/r/3778/diff/
Testing
---
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if this patch is save or if it would cause other
issues. Please let me know what you think.
Cheers,
Christian
[1] http://reviews.gem5.org/r/3778/
--
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Chair for Compiler Construction
01062 Dresden
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/3778/diff/
Testing
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: http://reviews.gem5.org/r/3527/diff/
Testing
---
The examples provided in util/tlm (now util/tlm/examples/slave_port) still
compile and run error free.
Thanks,
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: http://reviews.gem5.org/r/3528/diff/
Testing
---
A simple example application consisting of a TLM traffic generator and a gem5
memory is part of the patch.
Thanks,
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quests to the gem5 world.
This patch:
* Update the README
Diffs
-
util/tlm/README c10c50cb8ac9
Diff: http://reviews.gem5.org/r/3777/diff/
Testing
---
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Diff: http://reviews.gem5.org/r/3775/diff/
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e_port/SConstruct PRE-CREATION
util/tlm/examples/slave_port/main.cc PRE-CREATION
util/tlm/sim_control.hh PRE-CREATION
util/tlm/sim_control.cc PRE-CREATION
Diff: http://reviews.gem5.org/r/3695/diff/
Testing
---
Examples compile and run.
Thanks,
Christian
util/tlm/sim_control.cc PRE-CREATION
Diff: http://reviews.gem5.org/r/3695/diff/
Testing
---
Examples compile and run.
Thanks,
Christian Menard
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esting
---
Example applications are still running.
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iator_socket.
Diffs (updated)
-
util/tlm/sc_slave_port.hh PRE-CREATION
util/tlm/sc_slave_port.cc PRE-CREATION
Diff: http://reviews.gem5.org/r/3686/diff/
Testing
---
Example applications are still running.
Thanks,
Christian Menard
EATION
Diff: http://reviews.gem5.org/r/3528/diff/
Testing
---
A simple example application consisting of a TLM traffic generator and a gem5
memory is part of the patch.
Thanks,
Christian Menard
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ic generator and a gem5
memory is part of the patch.
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: http://reviews.gem5.org/r/3527/diff/
Testing
---
The examples provided in util/tlm (now util/tlm/examples/slave_port) still
compile and run error free.
Thanks,
Christian Menard
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_port) still
compile and run error free.
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modules
to easily genrerate new Requests.
Diffs
-
src/mem/external_master.cc c10c50cb8ac9
src/mem/ExternalMaster.py c10c50cb8ac9
src/mem/external_master.hh c10c50cb8ac9
Diff: http://reviews.gem5.org/r/3480/diff/
Testing
---
Used in a SystemC transactor
Thanks,
Christian Menard
/
Testing
---
Used in a SystemC transactor
Thanks,
Christian Menard
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moduels. Since sc_channel is derived from sc_module, this
patch does not break compatibility with existing code.
Diffs
-
util/systemc/sc_module.hh c10c50cb8ac9
util/systemc/sc_module.cc c10c50cb8ac9
Diff: http://reviews.gem5.org/r/3774/diff/
Testing
---
Thanks,
Christian Menard
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Ship it!
Ship It!
- Christian Menard
On May 25, 2016, 11:03 p.m
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Ship it!
Ship It!
- Christian Menard
On May 28, 2016, 7:37 p.m
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Examples compile and run.
Thanks,
Christian Menard
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Examples compile and run.
Thanks,
Christian Menard
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and run.
Thanks,
Christian Menard
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Examples compile and run.
Thanks,
Christian Menard
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g/r/3695/#comment7767>
Add more comments and update the README
- Christian Menard
On Nov. 7, 2016, 4:43 p.m., Christian Menard wrote:
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/report_handler.cc PRE-CREATION
util/tlm/examples/master_port/SConstruct PRE-CREATION
util/tlm/gem5_slave_transactor.hh PRE-CREATION
util/tlm/gem5_slave_transactor.cc PRE-CREATION
Diff: http://reviews.gem5.org/r/3695/diff/
Testing
---
Examples compile and run.
Thanks,
Christian Menard
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