Re: [gem5-dev] Adding a systemc TLM DMI like mechanism to gem5

[Dr. Matthias Jung]

Hi Gabe,

one of the main reasons for DMI is to speedup simulations, similar to the 
temporal decoupling in TLM LT or debug transport in order to make the 
boot-loading. AFAIK DMI is mainly used in virtual platforms that target 
software development and not hardware architecture design space explorations, 
because you skip interconnects, caches etc. In commercial tools you can just 
switch on or switch off DMI and therefore you can have a nice trade-off between 
speed and accuracy by using the same models. 

Since gem5 is mainly there for computer-system architecture research, I’m not 
sure if the DMI feature is really required. From a TLM2 perspective, even if a 
TLM target model included in gem5 offers DMI, the gem5 core model (initiator) 
does not have to use it, right? Do you have any concrete use case where you 
could exploit DMI? 

For KVM: maybe somebody with KVM experience should comment that.

Best regards,
Matthias

> Am 28.02.2019 um 06:13 schrieb Gabe Black :
> 
> Hi folks. TLM is a communication protocol/mechanism built on top of
> systemc. It supports a mechanism called DMI which stands for direct memory
> interface. The idea is that an entity sending a request into the system can
> ask if the target can give it a pointer it can use to directly access that
> memory in the future. The target, if it supports that sort of thing,
> returns a descriptor which describes a region of memory that can be
> accessed in that way. If that needs to be invalidated in the future, then
> there's another mechanism the target can use to communicate back to the
> sender telling it to throw away that descriptor.
> 
> The way this mechanism is implemented in TLM is a bit less than ideal since
> every request has a field that says whether the requester wants to know
> about DMI, and so the target has to perform an extra check on all the
> requests in case someone is asking when that's useful to communicate only a
> very small fraction of the time, perhaps only once during an entire
> simulation.
> 
> Aside from that though, this mechanism has some nice properties. First, it
> avoids having to globally identify what a memory is or where it is for a
> particular simulation. A memory is just a thing on the other end of a
> request that may let you get at it directly if you ask nicely. Also, if
> there's something in the way that would get messed up if you skipped over
> it, say a cache, it can block those requests from getting through to
> targets. This could be useful for KVM for instance, when it's collecting
> regions to act as RAM for the virtual machine.
> 
> I haven't fully figured out what a good way to avoid the check-every-time
> problem of the systemc mechanism, and ideally whatever I/we come up with
> will be compatible enough to be bridged effectively, but I'm thinking some
> sort of explicit additional call like getAddrRanges which would propogate
> through the hierarchy at specific points, either to a specific address or
> as a broadcast.
> 
> I know some folks have looked at gem5's memory system protocol and
> systemc's TLM before, for instance either to try making gem5 use TLM
> natively, or for the systemc TLM bridges. What do you think about adding
> this sort of mechainsm to gem5? Are there any pitfalls to avoid, known
> issues to figure out, suggested avenues to explore, etc? Please let me
> know. This is likely something I'm going to want to pursue in the next few
> weeks.
> 
> Gabe
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Re: [gem5-dev] hooking up gem5's memory system and systemc models

[Matthias Jung]

Hi Gabe,

> Am 02.11.2018 um 00:32 schrieb Gabe Black :
> 
> Connecting systemc and gem5 objects:
> 
> I'm thinking there are two different ways to do this. The first would be to
> make a systemc interface type which is the same as or inherits from the
> gem5 port interface. The systemc module/model would need to speak the gem5
> protocol directly, and this wouldn't be very easy to use when passing
> through packets (or whatever TLM calls them) which were generated by a
> module which didn't buy into using gem5's memory system protocol natively.

I think we should keep the TLM2.0 interoperability here such that we can
easily add any TLM2 model.

> Looking at the code in util/tlm, I don't 100% understand what's going on
> there (although the examples are great, thank you for those), but it looks
> like you've already done something at least sort of like this. Is any of
> that applicable here?

Yes we build a so called transactor which is able to translate between TLM’s
generic payload and gem5’s packets. Also the transactor handles the two 
different ways of implementing backpressure of gem5 and TLM. This is the
main difference of both protocols.

> I understand this less, although I'll keep looking at it to try to grok all
> the moving pieces. I haven't really learned much about TLM so that may be a
> limiting factor in learning how this works. This seems like a more robust
> solution and would leverage the work that's already been done, but I'm not
> sure how much work it would be or if there would be significant gotchas
> involved somewhere.

Actually TLM is not so much different to the gem5 implementation. If you want
we could have a short Skype telco, where I could highlight the differneces
and explain to you how TLM works in general.

> How about pulling the port extraction out of c++ and into python? Then the
> various python flavors of port could know what function to call on their
> parent, and what type their parent is supposed to be. That would complicate
> things for the C++ only config though…

Yes, for example if you use gem5 just as a core model in a SystemC virtual
platform. There should be still the possibility to do that.

Best,
Matthias
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Re: [gem5-dev] systemc reviews

[Matthias Jung]

Hi Christian,

I think you summarised the 3 approaches very well. I mean, we have
approach 1 already. It makes sense if Gabe drives approach 2 because
it has many advantages compared to approach 1. I think we could see
approach 3 as a longterm goal and we should go for approach 2 for now.

Thanks for all the opinions so far,
Best,
Matthias

> Am 11.06.2018 um 18:02 schrieb Christian Menard 
> :
> 
> Hi,
> 
> I am following the discussion for a while now and finally found the time
> to look at Gabe's proposal.
> 
> As I see it, there are three approaches for combining gem5 and SystemC
> as outlined below. (Sorry for repeating stuff that was mentioned before,
> I just find it helpful to summarize some points)
> 
> 1. Bridging gem5 ans Systemc.
> This is the approach I and Matthias implemented and presented last
> year. It provides bridges between the gem5 and SystemC communication
> interfaces, as well as a wrapper SystemC module that hosts a complete
> gem5 simulation on top of the SystemC kernel. While this approach
> certainly has limitations, it allows to combine gem5 and SystemC models.
> 
> 2. Implementing the SystemC standard using gem5
> This is the approach proposed by Gabe which, as I understand it,
> provides a wrapper around gem5 implementing the SystemC standard. With
> this approach, gem5 becomes a fully fledged SystemC kernel which
> arbitrary standard compliant SystemC models can run on. Compared to
> approach 1, this allows for more interaction between both domains, as
> everything can be compiled in a single pass and there is not just one
> single point of interaction. However, this approach prevents certain use
> cases, e.g. where SystemC models are closed source or where a specific
> SystemC implementation is required.
> 
> 3. Replacing the gem5 simulation kernel by SystemC.
> This is the most radical approach but also gives most flexibility. It
> replaces the entire gem5 simulation kernel by SystemC. In this approach,
> gem5 could be seen as a system modeling framework and as an abstraction
> layer on top of SystemC. This would give maximum flexibility as
> arbitrary SystemC and gem5 models can be combined and even the SystemC
> kernel can be exchanged arbitrarily. However, it is not clear (at least
> to me) how exactly gem5 and SystemC modules could be connected and
> interact with each other. I think for this approach to work, aspects of
> approach 1 or/and 2 are still required.
> 
> So as I see it: 3 covers more use cases than 2 but both are in a way
> superior to the existing approach (1). However, in order to implement 3
> a lot of changes to the code base are required. Implementing these
> changes will take some time, so there will probably be two versions of
> gem5: a legacy one and the SystemC one. This again produces more work in
> maintaining the code base. Now I wonder: who is willing to do all this
> work?
> 
> While I favour approach 3 for its benefits and the points Matthias made,
> I still like Gabe's idea very much. It minimizes the changes required to
> the existing code base while providing many benefits to a broader
> community. As Gabe mentioned before, his approach neither breaks with
> the existing bridges implemented by me and Matthias, nor does it prevent
> implementation of approach 3 in the future. To sum it up: there are no
> objections from my side.
> 
> Unfortunately, I am not very active in hardware modeling anymore, but I
> am very interested in this development and I hope to find the time to
> have a look on the patches soon.
> 
> Best,
> 
> Christian
> 
> Matthias Jung  writes:
> 
>> Hi Gabe,
>> 
>> I totally agree with you. SytemC is a standard and the code maintained
>> by accellera is just an „example“ of how SystemC could be implemented.
>> 
>> However, that is part of my argument. If I want to use e.g. another
>> fancy SystemC kernel (e.g. https://dl.acm.org/citation.cfm?id=2987374)
>> or a commercial one like the one in the Synopsys toolchains, I cannot
>> use gem5 (beside the coupling that is already there, which has also
>> several drawbacks). So I like more the separation of simulation models
>> and the kernel. 
>> 
>> But I also understand it from your side. In Google you don’t have this
>> specific need and you want to find quickly a solution with less effort.
>> Anyway we should discuss if a full switch to SystemC as a kernel might
>> be a reasonable long term goal. I think many people would benefit from
>> that.
>> 
>> I’m also keen to know Christian’s, Andreas’ and Jason’s opinions.
>> 
>> It’s a pitty that gem5 and SystemC started back at the same time
>> and evolved separately...
>> 
>> Best,

Re: [gem5-dev] systemc reviews

[Matthias Jung]

Hi Gabe,

I totally agree with you. SytemC is a standard and the code maintained
by accellera is just an „example“ of how SystemC could be implemented.

However, that is part of my argument. If I want to use e.g. another
fancy SystemC kernel (e.g. https://dl.acm.org/citation.cfm?id=2987374)
or a commercial one like the one in the Synopsys toolchains, I cannot
use gem5 (beside the coupling that is already there, which has also
several drawbacks). So I like more the separation of simulation models
and the kernel. 

But I also understand it from your side. In Google you don’t have this
specific need and you want to find quickly a solution with less effort.
Anyway we should discuss if a full switch to SystemC as a kernel might
be a reasonable long term goal. I think many people would benefit from
that.

I’m also keen to know Christian’s, Andreas’ and Jason’s opinions.

It’s a pitty that gem5 and SystemC started back at the same time
and evolved separately...

Best,
Matthias

> Am 09.06.2018 um 02:34 schrieb Gabe Black :
> 
> Also, I should point out that the systemc standard defines a set of
> mechanisms and an interface, not an implementation. The Accellera version
> of systemc is *not* the standard, it's just an implementation (a very
> common and important one) of that standard. It's dangerous to conflate
> those two ideas, and it leads to a lot of problems for everybody.
> 
> Gabe
> 
> On Fri, Jun 8, 2018 at 12:50 PM Gabe Black  wrote:
> 
>> Giacomo, if you're proposing linking in the systemc library and then
>> adding wrappers to somehow plug that into gem5's underlying mechanisms, I'm
>> not sure that's technically feasible since the existing implementation
>> isn't intended to be built on top of something else. Also a lot of the
>> mechanisms are built into base classes, and so if you change what data
>> members are in the base classes, ie the internal implementation, you break
>> existing binaries. There isn't much a wrapper can do in that case.
>> 
>> If you're proposing rebuilding gem5 on top of systemc, there are a variety
>> of reasons I'm not proposing that which I've gone through exhaustively (at
>> least I feel exhausted from it) in other places (you didn't miss it, that
>> was internally at Google).
>> 
>> This approach addresses best addresses the problem we (Google) are trying
>> to solve, which is to leverage existing models vendors may have developed
>> already in systemc, or which may be developed primarily in systemc in the
>> future. Rather than ask them to rewrite their models as gem5 models,
>> simultaneously develop two models, one for systemc and one for gem5, or to
>> architect their model as a core with two interface layers, one for each
>> system, any of which may be prohibitive from an engineering effort
>> perspective, this way they can write a systemc model (or take one they
>> already wrote) and then just recompile it with a different systemc header
>> and use it directly as a model within gem5.
>> 
>> There will be very little modification to gem5 proper for this, and so if
>> this sort of integration doesn't do what you want you can just ignore it or
>> even turn it off and not suffer any overhead, and then use whatever other
>> mechanism you like.
>> 
>> Matthias, while being able to use closed source models would be nice, it
>> isn't the problem we're trying to solve, and reimplementing gem5 on top of
>> systemc would be a lot more work that doesn't really gain us anything.
>> 
>> Jason, thanks. Please start with that python CL if you have a chance since
>> I think it's about ready to go in, Andreas just wanted you to ack it before
>> checking it in.
>> 
>> Gabe
>> 
>> 
>> On Fri, Jun 8, 2018 at 7:15 AM Jason Lowe-Power 
>> wrote:
>> 
>>> I'll have some time next week to dig into this.
>>> 
>>> Cheers,
>>> Jason
>>> 
>>> On Fri, Jun 8, 2018, 7:13 AM Dr.-Ing. Matthias Jung >>> 
>>> wrote:
>>> 
>>>> Hi Giacomo, Gabe,
>>>> 
>>>> I'm a large supporter of SystemC because its 'the' IEEE standard for
>>>> simulation, therefore I support always activities towards that
>>> direction.
>>>> However I have a similar concern like Giacomo.
>>>> 
>>>> I would prefer to just 'use' the SystemC kernel by accellera as kernel
>>> for
>>>> gem5 in order to have a proper separation between model and kernel. I
>>> think
>>>> its very interesting for many people to use gem5 in their SystemC
>>>> environment also together with commercial IP SystemC models that have a
>>>

Re: [gem5-dev] systemc reviews

[Dr.-Ing. Matthias Jung]

Hi Giacomo, Gabe,

I'm a large supporter of SystemC because its 'the' IEEE standard for 
simulation, therefore I support always activities towards that direction. 
However I have a similar concern like Giacomo.

I would prefer to just 'use' the SystemC kernel by accellera as kernel for gem5 
in order to have a proper separation between model and kernel. I think its very 
interesting for many people to use gem5 in their SystemC environment also 
together with commercial IP SystemC models that have a closed source. With the 
current aimed approach it would be required to have access to the source code 
of all used models in the system and commercial SystemC tools like Synopsys 
Platform Architect etc. could not be used.


Best,
Matthias

8. Juni 2018 15:47, "Giacomo Travaglini"  schrieb:

> Hi Gabe,
> 
> I have had a quick glance at the patches and there's one thing I don't 
> understand:
> 
> It seems to me that you are sort of reimplementing the SystemC runtime kernel 
> inside
> 
> gem5 for scratch.
> 
> Is there a reason for doing it? Can't we just link to the external SystemC 
> library
> 
> and just write some wrappers?
> 
> Thanks in advance for the clarifications
> 
> Giacomo
> 
> 
> From: gem5-dev  on behalf of Gabe Black 
> 
> Sent: 08 June 2018 06:32:52
> To: gem5 Developer List
> Subject: [gem5-dev] systemc reviews
> 
> Hi folks. I've posted a lot of systemc reviews recently, and I expect to
> keep doing so for the foreseeable future. To keep the pool of pending CLs
> from growing from a lot to unmanageably a lot please don't let them sit too
> long if you feel comfortable trying to review them. Alot of these earlier
> ones aren't very interesting, they're just defining header files, stubbed
> out implementations, or importing code from the Accellera version of
> SystemC. There are a few that are a little more interesting though, to keep
> you from getting bored ;-)
> 
> Gabe
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Re: [gem5-dev] Protobuf compilation errors

[Matthias Jung]

Hey,

by the way, when we talk about protobuf, I recently found this:

https://capnproto.org

Its claimed, that capnproto is faster than protobuf,
However, I cannot confirm that because I have not tried it.

Has somebody else experience with capnproto?

Best,
Matthias

> Am 21.03.2018 um 16:37 schrieb Matteo Andreozzi :
> 
> Hi Andreas,
> Thanks for sending this out. I’ve been experiencing issues on Mac using 
> clang, the issue in detail is:
> 
> Scons tries to build a test program including message.h from protobuf to 
> check if the protobuf C libraries are present
> Protobuf versions later than 3.3.0 use the LANG_CXX11 macro without defining 
> it first, in at least one of their files (atom.h).
> This causes the compilation of the test program to fail , due to the -Wundef 
> directive being set, and scons assuming that no protobuf is available in the 
> system.
> 
> The quick and dirty fix which I have on my local workspace is to remove 
> -Wundef from Sconstruct, which anyway never triggered before with the 
> exception of protobuf (on MSC_VER in the past, now on LANG_CXX11), see below:
> 
> main.Append(CCFLAGS=['-fno-strict-aliasing'])
> # Enable -Wall and -Wextra and then disable the few warnings that
> # we consistently violate
> -main.Append(CCFLAGS=['-Wall', '-Wundef', '-Wextra',
> +main.Append(CCFLAGS=['-Wall', '-Wextra',
>  '-Wno-sign-compare', '-Wno-unused-parameter'])
> # We always compile using C++11
> main.Append(CXXFLAGS=['-std=c++11'])
> 
> 
> From: Andreas Sandberg 
> Date: Wednesday, 21 March 2018 at 15:25
> To: gem5 Developer List 
> Cc: Gabe Black , Matteo Andreozzi 
> 
> Subject: Protobuf compilation errors
> 
> Hi Everyone,
> 
> We have been experiencing some issues with some combinations of
> different versions of protobuf and gcc/clang. Most of the issues seem to
> be related to undefined macros (-Wundef), but I have some vague memories
> of other issues as well (unclear indentation?).
> 
> In the short term, it seems like we need to disable -Werror for files
> that are generated by protoc. Another option would be to add
> -Wno-error=undef to the global environment. What would be the preferred
> solution here? I think I'm in favour of the former, but don't understand
> the build system well enough to implement it.
> 
> Cheers,
> Andreas
> 
> 
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Re: [gem5-dev] testing framework

[Matthias Jung]

Hey,

It would be also nice if we have something that we could also use for test the 
SystemC stuff. Right now this is not possible with the current framework. 
Because we have to build gem5 without python as a library for the SystemC 
stuff... and then build again with linking of the gem5 library.

Regards
Matthias 

> Am 17.11.2017 um 17:43 schrieb Andreas Sandberg :
> 
> I'm generally in favour of switching to an existing unit test framework.
> I haven't surveyed the C++ test framework landscape, but judging by the
> users (Chromium, LLVM, ...) GTest seems pretty solid.
> 
> As far as I can tell, GTest is all BSD. Is that correct?
> 
> Cheers,
> Andreas
> 
>> On 16/11/2017 05:04, Gabe Black wrote:
>> Hi folks. How is the test framework integration coming along? Is there
>> anything I can do to help?
>> 
>> Also, looking at the whimsy documentation and talking to some other folks
>> at Google, it looks like the framework is good at running tests, but
>> doesn't itself really implement, for instance, unit tests which have their
>> own C++ main function, etc.
>> 
>> Does anyone have an opinion about using the google gtest library for
>> writing C++ unit tests? I've only worked with it a little bit
>> superficially, but so far it seems pretty nice and seems like it would fit
>> into whimsy fairly well.
>> 
>> Gabe
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[gem5-dev] Change in public/gem5[master]: tlm: Elastic Trace Example with L2 Cache Added

[Matthias Jung (Gerrit)]

Matthias Jung has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/4900 )


Change subject: tlm: Elastic Trace Example with L2 Cache Added
..

tlm: Elastic Trace Example with L2 Cache Added

The SystemC TLM examples already include an example setup for elastic
traces. However, in the provided examples the L2 cache is omitted. This
patch provides an additionall example, which also includes an L2 cache
on the gem5 side.

Change-Id: I49e9fa074b60007694abff37663f0400caf72099
Reviewed-on: https://gem5-review.googlesource.com/4900
Reviewed-by: Jason Lowe-Power <ja...@lowepower.com>
Reviewed-by: Christian Menard <christian.men...@tu-dresden.de>
Maintainer: Jason Lowe-Power <ja...@lowepower.com>
---
M util/tlm/README
A util/tlm/examples/tlm_elastic_slave_with_l2.py
2 files changed, 137 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Christian Menard: Looks good to me, but someone else must approve



diff --git a/util/tlm/README b/util/tlm/README
index 6fd353c..69fda0b 100644
--- a/util/tlm/README
+++ b/util/tlm/README
@@ -184,6 +184,10 @@

 > ../../build/ARM/gem5.opt ./conf/tlm_elastic_slave.py

+or
+
+> ../../build/ARM/gem5.opt ./conf/tlm_elastic_slave_with_l2.py
+
 Then:

 > build/examples/slave_port/gem5.sc m5out/config.ini
diff --git a/util/tlm/examples/tlm_elastic_slave_with_l2.py  
b/util/tlm/examples/tlm_elastic_slave_with_l2.py

new file mode 100644
index 000..492f999
--- /dev/null
+++ b/util/tlm/examples/tlm_elastic_slave_with_l2.py
@@ -0,0 +1,133 @@
+# Copyright (c) 2016, University of Kaiserslautern
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+#
+# 1. Redistributions of source code must retain the above copyright notice,
+#this list of conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright
+#notice, this list of conditions and the following disclaimer in the
+#documentation and/or other materials provided with the distribution.
+#
+# 3. Neither the name of the copyright holder nor the names of its
+#contributors may be used to endorse or promote products derived from
+#this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A  
PARTICULAR

+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Matthias Jung
+
+import m5
+import optparse
+
+from m5.objects import *
+from m5.util import addToPath, fatal
+
+addToPath('../../../configs/common/')
+
+from Caches import *
+
+# This configuration shows a simple setup of a Elastic Trace Player  
(eTraceCPU)

+# and an external TLM port for SystemC co-simulation.
+#
+# We assume a DRAM size of 512MB and L1 cache sizes of 32KB and an L2 cache
+# size of 1MB.
+#
+# Base System Architecture:
+#
+#  +---+   ^
+# +-+  | eTraceCPU |   |
+# | System Port |  +-+-+   |
+# +--+--+  | $D1 | $I1 |   |
+#| +--+--+--+--+   |
+#|| |  | gem5 World (see this file)
+#| +--v-v--+   |
+#| | toL2Bus   |   |
+#| +-+-+   |
+#|   | |
+#| +-v-+   |
+#| |L2 |   |
+#| +-+-+   |
+#|   | |
+# +--v---v-+   |
+# |   Membus   |   v
+# ++---+   External Port (see sc_port.*)
+#  |   ^
+#  +---v---+   | TLM World
+#  |  TLM  |   | (see sc_target.*)
+#  +---+   v
+#
+#
+# Create a system with a Crossbar and an Elastic Trace Player as CPU:
+
+# Setup System:
+system = System(cpu=TraceCPU(cpu_id=0),
+mem_mode='timing',
+mem_ranges = [AddrRange('1024MB')],
+cache_line_size = 64)
+

[gem5-dev] Change in public/gem5[master]: tlm: Elastic Trace Example with L2 Cache Added

[Matthias Jung (Gerrit)]

Matthias Jung has uploaded this change for review. (  
https://gem5-review.googlesource.com/4900



Change subject: tlm: Elastic Trace Example with L2 Cache Added
..

tlm: Elastic Trace Example with L2 Cache Added

The SystemC TLM examples already include an example setup for elastic
traces. However, in the provided examples the L2 cache is omitted. This
patch provides an additionall example, which also includes an L2 cache
on the gem5 side.

Change-Id: I49e9fa074b60007694abff37663f0400caf72099
---
M util/tlm/README
A util/tlm/examples/tlm_elastic_slave_with_l2.py
2 files changed, 137 insertions(+), 0 deletions(-)



diff --git a/util/tlm/README b/util/tlm/README
index 6fd353c..69fda0b 100644
--- a/util/tlm/README
+++ b/util/tlm/README
@@ -184,6 +184,10 @@

 > ../../build/ARM/gem5.opt ./conf/tlm_elastic_slave.py

+or
+
+> ../../build/ARM/gem5.opt ./conf/tlm_elastic_slave_with_l2.py
+
 Then:

 > build/examples/slave_port/gem5.sc m5out/config.ini
diff --git a/util/tlm/examples/tlm_elastic_slave_with_l2.py  
b/util/tlm/examples/tlm_elastic_slave_with_l2.py

new file mode 100644
index 000..492f999
--- /dev/null
+++ b/util/tlm/examples/tlm_elastic_slave_with_l2.py
@@ -0,0 +1,133 @@
+# Copyright (c) 2016, University of Kaiserslautern
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+#
+# 1. Redistributions of source code must retain the above copyright notice,
+#this list of conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright
+#notice, this list of conditions and the following disclaimer in the
+#documentation and/or other materials provided with the distribution.
+#
+# 3. Neither the name of the copyright holder nor the names of its
+#contributors may be used to endorse or promote products derived from
+#this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A  
PARTICULAR

+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Matthias Jung
+
+import m5
+import optparse
+
+from m5.objects import *
+from m5.util import addToPath, fatal
+
+addToPath('../../../configs/common/')
+
+from Caches import *
+
+# This configuration shows a simple setup of a Elastic Trace Player  
(eTraceCPU)

+# and an external TLM port for SystemC co-simulation.
+#
+# We assume a DRAM size of 512MB and L1 cache sizes of 32KB and an L2 cache
+# size of 1MB.
+#
+# Base System Architecture:
+#
+#  +---+   ^
+# +-+  | eTraceCPU |   |
+# | System Port |  +-+-+   |
+# +--+--+  | $D1 | $I1 |   |
+#| +--+--+--+--+   |
+#|| |  | gem5 World (see this file)
+#| +--v-v--+   |
+#| | toL2Bus   |   |
+#| +-+-+   |
+#|   | |
+#| +-v-+   |
+#| |L2 |   |
+#| +-+-+   |
+#|   | |
+# +--v---v-+   |
+# |   Membus   |   v
+# ++---+   External Port (see sc_port.*)
+#  |   ^
+#  +---v---+   | TLM World
+#  |  TLM  |   | (see sc_target.*)
+#  +---+   v
+#
+#
+# Create a system with a Crossbar and an Elastic Trace Player as CPU:
+
+# Setup System:
+system = System(cpu=TraceCPU(cpu_id=0),
+mem_mode='timing',
+mem_ranges = [AddrRange('1024MB')],
+cache_line_size = 64)
+
+# Create a top-level voltage domain:
+system.voltage_domain = VoltageDomain()
+
+# Create a source clock for the system. This is used as the clock period  
for

+# xbar and memory:
+system.clk_domain = SrcClockDomain(clock =  '1GHz',
+voltage_domain = system.voltage_domain)
+
+# Create a CPU voltage domain:
+system.cpu_voltage_domain = VoltageDomain()
+
+# Create a separate clock domain for the CPUs. In

Re: [gem5-dev] Workshop Videos

[Matthias Jung]

Hey,

They are there, you have to switch the camera in the videos' menu.

Regards
Matthias

> Am 22.09.2017 um 21:54 schrieb Boris Shingarov :
> 
> Dear Colleagues,
> Am  I missing / looking in the wrong place for the gem5 Workshop videos?   
> The workshop's page on the gem5 wiki points to the main Summit Live  page, 
> but that seems to have only the videos from the big Auditorium?   Are the 
> ones from the gem5 workshop uploaded yet?
> Boris
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[gem5-dev] Change in public/gem5[master]: tlm: Don't set SystemC time resolution

[Matthias Jung (Gerrit)]

Matthias Jung has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/4520 )


Change subject: tlm: Don't set SystemC time resolution
..

tlm: Don't set SystemC time resolution

Some simulators already set the time resolution of SystemC. By coupling
gem5 by means of SystemC with an other tool this can lead to problems:
When the resolution is set twice the simulation will not work.
Therefore, the line is changed to an assertion that checks if the time
resolution of the SystemC simulation is set to gem5's value of 1ps.

Change-Id: I8aafab9dd593eb4697a3c7f69ce181fd9cdd05c4
Reviewed-on: https://gem5-review.googlesource.com/4520
Reviewed-by: Paul Rosenfeld <prosenf...@micron.com>
Reviewed-by: Jason Lowe-Power <ja...@lowepower.com>
Maintainer: Jason Lowe-Power <ja...@lowepower.com>
---
M util/tlm/src/sim_control.cc
1 file changed, 2 insertions(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Paul Rosenfeld: Looks good to me, approved



diff --git a/util/tlm/src/sim_control.cc b/util/tlm/src/sim_control.cc
index a96daf2..fae8db0 100644
--- a/util/tlm/src/sim_control.cc
+++ b/util/tlm/src/sim_control.cc
@@ -86,7 +86,8 @@
 Trace::setDebugLogger();

 Gem5SystemC::setTickFrequency();
-sc_core::sc_set_time_resolution(1, sc_core::SC_PS);
+assert(sc_core::sc_get_time_resolution()
+== sc_core::sc_time(1,sc_core::SC_PS));

 Gem5SystemC::Module::setupEventQueues(*this);
 initSignals();

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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I8aafab9dd593eb4697a3c7f69ce181fd9cdd05c4
Gerrit-Change-Number: 4520
Gerrit-PatchSet: 2
Gerrit-Owner: Matthias Jung <jun...@eit.uni-kl.de>
Gerrit-Reviewer: Christian Menard <christian.men...@tu-dresden.de>
Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-Reviewer: Matthias Jung <jun...@eit.uni-kl.de>
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Re: [gem5-dev] [EXT] Re: Merging the TLM/SystemC examples?

[Matthias Jung]

Hi Paul,

I think it’s a good idea, we just ping each other once we start doing something.

Regards
Matthias

> Am 17.08.2017 um 16:09 schrieb Paul Rosenfeld (prosenfeld) 
> <prosenf...@micron.com>:
> 
> Hi Matthias, 
> 
> It seems like every time I settle in to try to do something on gem5, 15 other 
> higher priority projects crop up. Although I very much want to work on this, 
> it appears that the earliest I may have time is October. 
> 
> Could you ping me if you (or anyone else out there in gem5 land) start 
> working on this? I will do the same if I start working on it but I don't want 
> to accidentally duplicate effort. 
> 
> Regards, 
> Paul
> 
> -Original Message-
> From: gem5-dev [mailto:gem5-dev-boun...@gem5.org] On Behalf Of Matthias Jung
> Sent: Monday, July 10, 2017 5:31 AM
> To: gem5 Developer List <gem5-dev@gem5.org>
> Subject: [EXT] Re: [gem5-dev] Merging the TLM/SystemC examples?
> 
> Hi Paul,
> 
> I have it on my todo list to bring the complete functionality to util/systemc 
> to util/tlm because I also need checkpoints. If everything is ported we could 
> probably remove util/systemc probably. If you port the features over to TLM 
> you can select me as a reviewer. If you need any help or assistance please 
> let me know ;)
> 
> Regards
> Matthias
> 
> 
>> Am 06.07.2017 um 14:58 schrieb Paul Rosenfeld (prosenfeld) 
>> <prosenf...@micron.com>:
>> 
>> Hello all,
>> 
>> I've been looking at the SystemC example (util/systemc) and the TLM examples 
>> (util/tlm) and trying to figure out if both examples are actually needed. As 
>> far as I can tell, the TLM example is basically a more well-structured and 
>> recently updated clone of the SystemC example. However, the SystemC example 
>> has some extra features that the TLM example doesn't such as the ability to 
>> create/restore checkpoints, set parameters, and switch CPUs. So the question 
>> I have is: if I were to port the SystemC example's extra features over to 
>> the TLM example, would the SystemC example still be needed or are they 
>> attempting to show different things that I'm just not seeing?
>> 
>> Regards,
>> Paul
>> ___
>> gem5-dev mailing list
>> gem5-dev@gem5.org
>> http://m5sim.org/mailman/listinfo/gem5-dev
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[gem5-dev] Change in public/gem5[master]: tlm: Don't set SystemC time resolution

[Matthias Jung (Gerrit)]

Matthias Jung has uploaded this change for review. (  
https://gem5-review.googlesource.com/4520



Change subject: tlm: Don't set SystemC time resolution
..

tlm: Don't set SystemC time resolution

Some simulators already set the time resolution of SystemC. By coupling
gem5 by means of SystemC with an other tool this can lead to problems:
When the resolution is set twice the simulation will not work.
Therefore, the line is changed to an assertion that checks if the time
resolution of the SystemC simulation is set to gem5's value of 1ps.

Change-Id: I8aafab9dd593eb4697a3c7f69ce181fd9cdd05c4
---
M util/tlm/src/sim_control.cc
1 file changed, 2 insertions(+), 1 deletion(-)



diff --git a/util/tlm/src/sim_control.cc b/util/tlm/src/sim_control.cc
index a96daf2..fae8db0 100644
--- a/util/tlm/src/sim_control.cc
+++ b/util/tlm/src/sim_control.cc
@@ -86,7 +86,8 @@
 Trace::setDebugLogger();

 Gem5SystemC::setTickFrequency();
-sc_core::sc_set_time_resolution(1, sc_core::SC_PS);
+assert(sc_core::sc_get_time_resolution()
+== sc_core::sc_time(1,sc_core::SC_PS));

 Gem5SystemC::Module::setupEventQueues(*this);
 initSignals();

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Gerrit-Change-Number: 4520
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Re: [gem5-dev] running system C models as gem5 SimObjects

[Matthias Jung]

Hey,

> Am 27.07.2017 um 09:14 schrieb Andreas Hansson :
> 
> Overall I strongly support aligning gem5 and SystemC further. The best
> outcome, in my view, would be if gem5 was transitioned to work on the
> SystemC kernel, allowing interoperability and more elaborate event
> semantics, and then also transitioned to use the TLM ports. That would be
> quite a work package though.

I see it the same way, SystemC/TLM is an IEEE standard which is widely used in
industry. And therefore there would be a much larger interoperability and
also the chance to integrate much more available models to gem5 or vice versa.
I also have a large interest in pushing this further!

From a TLM view, most of the components could just use the standard TLM methods
like b_transport, nb_transport and debug_transport because its indeed very
related to Atomic, Timing and Functional methods of gem5, respectively.

Some modules would require paylod extensions or even additional protocol phases.
But beside this the transition to TLM standard interfaces would be maybe easier
than the job of switching to the SystemC kernel ;) But this would be required
in order to get the PEQs working for TLM...


Just a shameless plug for the SystemC work that we have done so far:
http://samos-conference.com/Resources_Samos_Websites/Proceedings_Repository_SAMOS/2017/49_Final_Paper.pdf

Regards
Matthias


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Re: [gem5-dev] Combining Master & Slave port in GEM5-TLM

[Matthias Jung]

Hi,
You don't need something extra. Just instantiate one sim_control, one slave and 
one master and bind slave and master to the sim_control. That's all.

For more details have a look on the paper: 
http://samos-conference.com/Resources_Samos_Websites/Proceedings_Repository_SAMOS/2017/49_Final_Paper.pdf

Regards
Matthias 

--

Dr.-Ing. Matthias Jung

Member
Advanced Silicon Technologies & Design Methodologies


University of Kaiserslautern
Microelectronic Systems Design Research Group
Erwin-Schrödinger-Straße 12/228
67663 Kaiserslautern, Germany

Phone: +49 631 205 3579
Fax: +49 631 205 4437
jun...@eit.uni-kl.de
http://ems.eit.uni-kl.de

> Am 18.07.2017 um 19:04 schrieb Qureshi Yasir Mahmood <yasir.qure...@epfl.ch>:
> 
> Hi,
> 
> In GEM5-TLM, there are two separate examples for master_port and slave_port. 
> I am thinking to combine, so that in the same simulation we have both the 
> master_port as well as slave_port in the TLM world. When looking into this, I 
> realized we have this sim_control, to which I can either bind a master 
> transactor or slave transactor.
> So do you think to have both master and slave ports I need to define a new 
> transactor, which has both master and slave functionalities ?
> 
> The motivation for this is to support an accelerator or device which is a 
> slave to the system, so the CPU can issue requests to it, but if it wants to 
> read to write directly from memory it should also have a master port 
> (Assuming memory is in GEM5-world).
> 
> Regards
> Yasir
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Re: [gem5-dev] Merging the TLM/SystemC examples?

[Matthias Jung]

Hi Paul,

I have it on my todo list to bring the complete functionality to util/systemc 
to util/tlm because I also need checkpoints. If everything is ported we could 
probably remove util/systemc probably. If you port the features over to TLM you 
can select me as a reviewer. If you need any help or assistance please let me 
know ;)

Regards
Matthias


> Am 06.07.2017 um 14:58 schrieb Paul Rosenfeld (prosenfeld) 
> :
> 
> Hello all,
> 
> I've been looking at the SystemC example (util/systemc) and the TLM examples 
> (util/tlm) and trying to figure out if both examples are actually needed. As 
> far as I can tell, the TLM example is basically a more well-structured and 
> recently updated clone of the SystemC example. However, the SystemC example 
> has some extra features that the TLM example doesn't such as the ability to 
> create/restore checkpoints, set parameters, and switch CPUs. So the question 
> I have is: if I were to port the SystemC example's extra features over to the 
> TLM example, would the SystemC example still be needed or are they attempting 
> to show different things that I'm just not seeing?
> 
> Regards,
> Paul
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[gem5-dev] Restructuring Wiki wrt. Citation Credit

[Matthias Jung]

Hey,

I want to ask: why not restructuring the main page and the publication page a 
little wrt. citation credits ? 

http://gem5.org/Main_Page
http://gem5.org/Publications

Hi have observed that, for example, people are using gem5 to wok on a memory 
specific topic and cite only the original gem5 paper and do not add the 
relevant citations to the DRAM controller paper or DRAMPower etc. 

What I suppose is to restructure the paper page according to specific features, 
e.g. DRAM, KVM, GPU … and write a sentence that people should cite the original 
gem5 paper and additionally the listed papers when they used specific features: 
If you use X, please cite Y etc.

Of course this will not guarantee that people do it right in the future, but at 
least it will help or make them aware of it.

What do you think? If you guys agree I would start to update the pages.
Regards
Matthias
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Re: [gem5-dev] gem5 does not compile on Mac OS Sierra

[Matthias Jung]

Hey,

Commit 1d10cd6185edfd46d51f6562bff832a9b5d36cff solved the problem.

Thanks to Andreas Sandberg for fixing it!

Regards

> Am 19.05.2017 um 15:53 schrieb Matthias Jung <jun...@eit.uni-kl.de>:
> 
> Hey,
> 
> I get the following compiling issue with gem5 on macOS Sierra (10.12.4) with 
> clang Apple LLVM 8.1.0:
> 
> 
> 
> In file included from build/ARM/arch/arm/generated/generic_cpu_exec_6.cc:11:
> build/ARM/arch/arm/generated/exec-ns.cc.inc:189454:39: error: implicit 
> conversion from 'int' to 'Element' (aka 'signed char') changes value from 128 
> to -128
>  [-Werror,-Wconstant-conversion]
>destElem = (Element)1 << (sizeof(Element) * 8 - 1);
> ~ ~~~^~~~
> build/ARM/arch/arm/generated/exec-ns.cc.inc:189506:28: note: in instantiation 
> of member function 'ArmISAInst::SqaddDX::execute' requested here
>Fault SqaddDX::execute(
>   ^
> build/ARM/arch/arm/generated/exec-ns.cc.inc:189454:39: error: implicit 
> conversion from 'int' to 'Element' (aka 'short') changes value from 32768 to 
> -32768
>  [-Werror,-Wconstant-conversion]
>destElem = (Element)1 << (sizeof(Element) * 8 - 1);
> ~ ~~~^~~~
> build/ARM/arch/arm/generated/exec-ns.cc.inc:189510:29: note: in instantiation 
> of member function 'ArmISAInst::SqaddDX::execute' requested here
>Fault SqaddDX::execute(
>^
> build/ARM/arch/arm/generated/exec-ns.cc.inc:189601:39: error: implicit 
> conversion from 'int' to 'Element' (aka 'signed char') changes value from 128 
> to -128
>  [-Werror,-Wconstant-conversion]
>destElem = (Element)1 << (sizeof(Element) * 8 - 1);
> ~ ~~~^~~~
> build/ARM/arch/arm/generated/exec-ns.cc.inc:189653:28: note: in instantiation 
> of member function 'ArmISAInst::SqaddQX::execute' requested here
>Fault SqaddQX::execute(
>   ^
> build/ARM/arch/arm/generated/exec-ns.cc.inc:189601:39: error: implicit 
> conversion from 'int' to 'Element' (aka 'short') changes value from 32768 to 
> -32768
>  [-Werror,-Wconstant-conversion]
>destElem = (Element)1 << (sizeof(Element) * 8 - 1);
> ~ ~~~^~~~
> build/ARM/arch/arm/generated/exec-ns.cc.inc:189657:29: note: in instantiation 
> of member function 'ArmISAInst::SqaddQX::execute' requested here
>Fault SqaddQX::execute(
>^
> build/ARM/arch/arm/generated/exec-ns.cc.inc:189757:39: error: implicit 
> conversion from 'int' to 'Element' (aka 'signed char') changes value from 128 
> to -128
>  [-Werror,-Wconstant-conversion]
>destElem = (Element)1 << (sizeof(Element) * 8 - 1);
> ~ ~~~^~~~
> build/ARM/arch/arm/generated/exec-ns.cc.inc:189809:29: note: in instantiation 
> of member function 'ArmISAInst::SqaddScX::execute' requested here
>Fault SqaddScX::execute(
>^
> build/ARM/arch/arm/generated/exec-ns.cc.inc:189757:39: error: implicit 
> conversion from 'int' to 'Element' (aka 'short') changes value from 32768 to 
> -32768
>  [-Werror,-Wconstant-conversion]
>destElem = (Element)1 << (sizeof(Element) * 8 - 1);
> ~ ~~~^~~~
> build/ARM/arch/arm/generated/exec-ns.cc.inc:189813:30: note: in instantiation 
> of member function 'ArmISAInst::SqaddScX::execute' requested here
>Fault SqaddScX::execute(
> ^
> build/ARM/arch/arm/generated/exec-ns.cc.inc:189919:37: error: implicit 
> conversion from 'int' to 'Element' (aka 'short') changes value from 32768 to 
> -32768
>  [-Werror,-Wconstant-conversion]
>Element maxNeg = (Element)1 << (sizeof(Element) * 8 - 1);
>~~   ~~~^~~~
> build/ARM/arch/arm/generated/exec-ns.cc.inc:189984:34: note: in instantiation 
> of member function 'ArmISAInst::SqdmlalElemX::execute' requested here
>Fault SqdmlalElemX::execute(
> ^
> build/ARM/arch/arm/generated/exec-ns.cc.inc:190086:37: error: implicit 
> conversion from 'int' to 'Element' (aka 'short') changes value from 32768 to 
> -32768
>  [-Werror,-Wconstant-conversion]
>Element maxNeg = (Element)1 << (sizeof(Element) * 8 - 1);
>~~   ~~~^~~~
> build/ARM/arch/arm/generated/exec-ns.cc.inc:190151:35: note: in instantiation 
> of 

[gem5-dev] gem5 does not compile on Mac OS Sierra

[Matthias Jung]

  Element maxNeg = (Element)1 << (sizeof(Element) * 8 - 1);
~~   ~~~^~~~
build/ARM/arch/arm/generated/exec-ns.cc.inc:122062:31: note: in instantiation 
of member function 'ArmISAInst::VqrdmulhQ::execute' requested here
Fault VqrdmulhQ::execute(
  ^
fatal error: too many errors emitted, stopping now [-ferror-limit=]
20 errors generated.
scons: *** [build/ARM/arch/arm/generated/generic_cpu_exec_4.o] Error 1
scons: building terminated because of errors.


Has somebody an idea? This is generated code, so I won’t try to fix something 
here or?

Any inputs, pointers or hints are appreciated.

Regards
Matthias



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Member
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University of Kaiserslautern
Microelectronic Systems Design Research Group
Erwin-Schrödinger-Straße 12/228
67663 Kaiserslautern, Germany

Phone: +49 631 205 3579
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[gem5-dev] Change in public/gem5[master]: ext: Include SystemC 2.3.1 into gem5

[Matthias Jung (Gerrit)]

Matthias Jung has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/2240 )


Change subject: ext: Include SystemC 2.3.1 into gem5
..

ext: Include SystemC 2.3.1 into gem5

In the past it happened several times that some changes in gem5 broke the
SystemC coupling. Recently Accelera has changed the licence for SystemC
from their own licence to Apache2.0, which is compatible with gem5.
However, SystemC usually relies on the Boost library, but I was able to
exchange the boost calls by c++11 alternatives. The recent SystemC version
is placed into /ext and is integrated into gem5's build system. The goal is
to integrate some SystemC tests for the CI in some following patches.

Change-Id: I4b66ec806b5e3cffc1d7c85d3735ff4fa5b31fd0
Reviewed-on: https://gem5-review.googlesource.com/2240
Reviewed-by: Andreas Sandberg <andreas.sandb...@arm.com>
Maintainer: Andreas Sandberg <andreas.sandb...@arm.com>
---
A ext/systemc/AUTHORS
A ext/systemc/ChangeLog
A ext/systemc/INSTALL
A ext/systemc/LICENSE
A ext/systemc/NEWS
A ext/systemc/NOTICE
A ext/systemc/README.gem5.md
A ext/systemc/README.md
A ext/systemc/README.sysc
A ext/systemc/RELEASENOTES
A ext/systemc/SConscript
A ext/systemc/src/README_TLM.txt
A ext/systemc/src/sysc/communication/sc_buffer.h
A ext/systemc/src/sysc/communication/sc_clock.cpp
A ext/systemc/src/sysc/communication/sc_clock.h
A ext/systemc/src/sysc/communication/sc_clock_ports.h
A ext/systemc/src/sysc/communication/sc_communication_ids.h
A ext/systemc/src/sysc/communication/sc_event_finder.cpp
A ext/systemc/src/sysc/communication/sc_event_finder.h
A ext/systemc/src/sysc/communication/sc_event_queue.cpp
A ext/systemc/src/sysc/communication/sc_event_queue.h
A ext/systemc/src/sysc/communication/sc_export.cpp
A ext/systemc/src/sysc/communication/sc_export.h
A ext/systemc/src/sysc/communication/sc_fifo.h
A ext/systemc/src/sysc/communication/sc_fifo_ifs.h
A ext/systemc/src/sysc/communication/sc_fifo_ports.h
A ext/systemc/src/sysc/communication/sc_host_mutex.h
A ext/systemc/src/sysc/communication/sc_interface.cpp
A ext/systemc/src/sysc/communication/sc_interface.h
A ext/systemc/src/sysc/communication/sc_mutex.cpp
A ext/systemc/src/sysc/communication/sc_mutex.h
A ext/systemc/src/sysc/communication/sc_mutex_if.h
A ext/systemc/src/sysc/communication/sc_port.cpp
A ext/systemc/src/sysc/communication/sc_port.h
A ext/systemc/src/sysc/communication/sc_prim_channel.cpp
A ext/systemc/src/sysc/communication/sc_prim_channel.h
A ext/systemc/src/sysc/communication/sc_semaphore.cpp
A ext/systemc/src/sysc/communication/sc_semaphore.h
A ext/systemc/src/sysc/communication/sc_semaphore_if.h
A ext/systemc/src/sysc/communication/sc_signal.cpp
A ext/systemc/src/sysc/communication/sc_signal.h
A ext/systemc/src/sysc/communication/sc_signal_ifs.h
A ext/systemc/src/sysc/communication/sc_signal_ports.cpp
A ext/systemc/src/sysc/communication/sc_signal_ports.h
A ext/systemc/src/sysc/communication/sc_signal_resolved.cpp
A ext/systemc/src/sysc/communication/sc_signal_resolved.h
A ext/systemc/src/sysc/communication/sc_signal_resolved_ports.cpp
A ext/systemc/src/sysc/communication/sc_signal_resolved_ports.h
A ext/systemc/src/sysc/communication/sc_signal_rv.h
A ext/systemc/src/sysc/communication/sc_signal_rv_ports.h
A ext/systemc/src/sysc/communication/sc_writer_policy.h
A ext/systemc/src/sysc/datatypes/bit/sc_bit.cpp
A ext/systemc/src/sysc/datatypes/bit/sc_bit.h
A ext/systemc/src/sysc/datatypes/bit/sc_bit_ids.h
A ext/systemc/src/sysc/datatypes/bit/sc_bit_proxies.h
A ext/systemc/src/sysc/datatypes/bit/sc_bv.h
A ext/systemc/src/sysc/datatypes/bit/sc_bv_base.cpp
A ext/systemc/src/sysc/datatypes/bit/sc_bv_base.h
A ext/systemc/src/sysc/datatypes/bit/sc_logic.cpp
A ext/systemc/src/sysc/datatypes/bit/sc_logic.h
A ext/systemc/src/sysc/datatypes/bit/sc_lv.h
A ext/systemc/src/sysc/datatypes/bit/sc_lv_base.cpp
A ext/systemc/src/sysc/datatypes/bit/sc_lv_base.h
A ext/systemc/src/sysc/datatypes/bit/sc_proxy.h
A ext/systemc/src/sysc/datatypes/fx/fx.h
A ext/systemc/src/sysc/datatypes/fx/sc_context.h
A ext/systemc/src/sysc/datatypes/fx/sc_fix.h
A ext/systemc/src/sysc/datatypes/fx/sc_fixed.h
A ext/systemc/src/sysc/datatypes/fx/sc_fx_ids.h
A ext/systemc/src/sysc/datatypes/fx/sc_fxcast_switch.cpp
A ext/systemc/src/sysc/datatypes/fx/sc_fxcast_switch.h
A ext/systemc/src/sysc/datatypes/fx/sc_fxdefs.cpp
A ext/systemc/src/sysc/datatypes/fx/sc_fxdefs.h
A ext/systemc/src/sysc/datatypes/fx/sc_fxnum.cpp
A ext/systemc/src/sysc/datatypes/fx/sc_fxnum.h
A ext/systemc/src/sysc/datatypes/fx/sc_fxnum_observer.cpp
A ext/systemc/src/sysc/datatypes/fx/sc_fxnum_observer.h
A ext/systemc/src/sysc/datatypes/fx/sc_fxtype_params.cpp
A ext/systemc/src/sysc/datatypes/fx/sc_fxtype_params.h
A ext/systemc/src/sysc/datatypes/fx/sc_fxval.cpp
A ext/systemc/src/sysc/datatypes/fx/sc_fxval.h
A ext/systemc/src/sysc/datatypes/fx/sc_fxval_observer.cpp
A ext/systemc/src/sysc/datatypes/fx/sc_fxva

[gem5-dev] Change in public/gem5[master]: ext: Include SystemC 2.3.1 into gem5

[Matthias Jung (Gerrit)]

/systemc/src/tlm_core/tlm_1/README.txt
A ext/systemc/src/tlm_core/tlm_1/tlm_analysis/tlm_analysis.h
A ext/systemc/src/tlm_core/tlm_1/tlm_analysis/tlm_analysis_fifo.h
A ext/systemc/src/tlm_core/tlm_1/tlm_analysis/tlm_analysis_if.h
A ext/systemc/src/tlm_core/tlm_1/tlm_analysis/tlm_analysis_port.h
A ext/systemc/src/tlm_core/tlm_1/tlm_analysis/tlm_analysis_triple.h
A ext/systemc/src/tlm_core/tlm_1/tlm_analysis/tlm_write_if.h
A ext/systemc/src/tlm_core/tlm_1/tlm_req_rsp/tlm_1_interfaces/tlm_core_ifs.h
A ext/systemc/src/tlm_core/tlm_1/tlm_req_rsp/tlm_1_interfaces/tlm_fifo_ifs.h
A  
ext/systemc/src/tlm_core/tlm_1/tlm_req_rsp/tlm_1_interfaces/tlm_master_slave_ifs.h

A ext/systemc/src/tlm_core/tlm_1/tlm_req_rsp/tlm_1_interfaces/tlm_tag.h
A ext/systemc/src/tlm_core/tlm_1/tlm_req_rsp/tlm_adapters/tlm_adapters.h
A  
ext/systemc/src/tlm_core/tlm_1/tlm_req_rsp/tlm_channels/tlm_fifo/circular_buffer.h
A  
ext/systemc/src/tlm_core/tlm_1/tlm_req_rsp/tlm_channels/tlm_fifo/tlm_fifo.h
A  
ext/systemc/src/tlm_core/tlm_1/tlm_req_rsp/tlm_channels/tlm_fifo/tlm_fifo_peek.h
A  
ext/systemc/src/tlm_core/tlm_1/tlm_req_rsp/tlm_channels/tlm_fifo/tlm_fifo_put_get.h
A  
ext/systemc/src/tlm_core/tlm_1/tlm_req_rsp/tlm_channels/tlm_fifo/tlm_fifo_resize.h
A  
ext/systemc/src/tlm_core/tlm_1/tlm_req_rsp/tlm_channels/tlm_req_rsp_channels/tlm_put_get_imp.h
A  
ext/systemc/src/tlm_core/tlm_1/tlm_req_rsp/tlm_channels/tlm_req_rsp_channels/tlm_req_rsp_channels.h

A ext/systemc/src/tlm_core/tlm_1/tlm_req_rsp/tlm_ports/tlm_event_finder.h
A  
ext/systemc/src/tlm_core/tlm_1/tlm_req_rsp/tlm_ports/tlm_nonblocking_port.h

A ext/systemc/src/tlm_core/tlm_1/tlm_req_rsp/tlm_req_rsp.h
A ext/systemc/src/tlm_core/tlm_2/README.txt
A ext/systemc/src/tlm_core/tlm_2/tlm_2_interfaces/tlm_2_interfaces.h
A ext/systemc/src/tlm_core/tlm_2/tlm_2_interfaces/tlm_dmi.h
A ext/systemc/src/tlm_core/tlm_2/tlm_2_interfaces/tlm_fw_bw_ifs.h
A ext/systemc/src/tlm_core/tlm_2/tlm_generic_payload/tlm_array.h
A ext/systemc/src/tlm_core/tlm_2/tlm_generic_payload/tlm_endian_conv.h
A ext/systemc/src/tlm_core/tlm_2/tlm_generic_payload/tlm_generic_payload.h
A ext/systemc/src/tlm_core/tlm_2/tlm_generic_payload/tlm_gp.h
A ext/systemc/src/tlm_core/tlm_2/tlm_generic_payload/tlm_helpers.h
A ext/systemc/src/tlm_core/tlm_2/tlm_generic_payload/tlm_phase.h
A ext/systemc/src/tlm_core/tlm_2/tlm_quantum/tlm_global_quantum.h
A ext/systemc/src/tlm_core/tlm_2/tlm_quantum/tlm_quantum.h
A ext/systemc/src/tlm_core/tlm_2/tlm_sockets/tlm_initiator_socket.h
A ext/systemc/src/tlm_core/tlm_2/tlm_sockets/tlm_sockets.h
A ext/systemc/src/tlm_core/tlm_2/tlm_sockets/tlm_target_socket.h
A ext/systemc/src/tlm_core/tlm_2/tlm_version.h
A ext/systemc/src/tlm_utils/README.txt
A ext/systemc/src/tlm_utils/instance_specific_extensions.h
A ext/systemc/src/tlm_utils/multi_passthrough_initiator_socket.h
A ext/systemc/src/tlm_utils/multi_passthrough_target_socket.h
A ext/systemc/src/tlm_utils/multi_socket_bases.h
A ext/systemc/src/tlm_utils/passthrough_target_socket.h
A ext/systemc/src/tlm_utils/peq_with_cb_and_phase.h
A ext/systemc/src/tlm_utils/peq_with_get.h
A ext/systemc/src/tlm_utils/simple_initiator_socket.h
A ext/systemc/src/tlm_utils/simple_target_socket.h
A ext/systemc/src/tlm_utils/tlm2_base_protocol_checker.h
A ext/systemc/src/tlm_utils/tlm_quantumkeeper.h
362 files changed, 138,299 insertions(+), 0 deletions(-)


--
To view, visit https://gem5-review.googlesource.com/2240
To unsubscribe, visit https://gem5-review.googlesource.com/settings

Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I4b66ec806b5e3cffc1d7c85d3735ff4fa5b31fd0
Gerrit-Change-Number: 2240
Gerrit-PatchSet: 7
Gerrit-Owner: Matthias Jung <jun...@eit.uni-kl.de>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-Reviewer: Matthias Jung <jun...@eit.uni-kl.de>
Gerrit-Reviewer: Éder F. Zulian <ederf...@gmail.com>
___
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[gem5-dev] Change in public/gem5[master]: ext: Include SystemC 2.3.1 into gem5

[Matthias Jung (Gerrit)]

/src/tlm_core/tlm_1/README.txt
A ext/systemc/src/tlm_core/tlm_1/tlm_analysis/tlm_analysis.h
A ext/systemc/src/tlm_core/tlm_1/tlm_analysis/tlm_analysis_fifo.h
A ext/systemc/src/tlm_core/tlm_1/tlm_analysis/tlm_analysis_if.h
A ext/systemc/src/tlm_core/tlm_1/tlm_analysis/tlm_analysis_port.h
A ext/systemc/src/tlm_core/tlm_1/tlm_analysis/tlm_analysis_triple.h
A ext/systemc/src/tlm_core/tlm_1/tlm_analysis/tlm_write_if.h
A ext/systemc/src/tlm_core/tlm_1/tlm_req_rsp/tlm_1_interfaces/tlm_core_ifs.h
A ext/systemc/src/tlm_core/tlm_1/tlm_req_rsp/tlm_1_interfaces/tlm_fifo_ifs.h
A  
ext/systemc/src/tlm_core/tlm_1/tlm_req_rsp/tlm_1_interfaces/tlm_master_slave_ifs.h

A ext/systemc/src/tlm_core/tlm_1/tlm_req_rsp/tlm_1_interfaces/tlm_tag.h
A ext/systemc/src/tlm_core/tlm_1/tlm_req_rsp/tlm_adapters/tlm_adapters.h
A  
ext/systemc/src/tlm_core/tlm_1/tlm_req_rsp/tlm_channels/tlm_fifo/circular_buffer.h
A  
ext/systemc/src/tlm_core/tlm_1/tlm_req_rsp/tlm_channels/tlm_fifo/tlm_fifo.h
A  
ext/systemc/src/tlm_core/tlm_1/tlm_req_rsp/tlm_channels/tlm_fifo/tlm_fifo_peek.h
A  
ext/systemc/src/tlm_core/tlm_1/tlm_req_rsp/tlm_channels/tlm_fifo/tlm_fifo_put_get.h
A  
ext/systemc/src/tlm_core/tlm_1/tlm_req_rsp/tlm_channels/tlm_fifo/tlm_fifo_resize.h
A  
ext/systemc/src/tlm_core/tlm_1/tlm_req_rsp/tlm_channels/tlm_req_rsp_channels/tlm_put_get_imp.h
A  
ext/systemc/src/tlm_core/tlm_1/tlm_req_rsp/tlm_channels/tlm_req_rsp_channels/tlm_req_rsp_channels.h

A ext/systemc/src/tlm_core/tlm_1/tlm_req_rsp/tlm_ports/tlm_event_finder.h
A  
ext/systemc/src/tlm_core/tlm_1/tlm_req_rsp/tlm_ports/tlm_nonblocking_port.h

A ext/systemc/src/tlm_core/tlm_1/tlm_req_rsp/tlm_req_rsp.h
A ext/systemc/src/tlm_core/tlm_2/README.txt
A ext/systemc/src/tlm_core/tlm_2/tlm_2_interfaces/tlm_2_interfaces.h
A ext/systemc/src/tlm_core/tlm_2/tlm_2_interfaces/tlm_dmi.h
A ext/systemc/src/tlm_core/tlm_2/tlm_2_interfaces/tlm_fw_bw_ifs.h
A ext/systemc/src/tlm_core/tlm_2/tlm_generic_payload/tlm_array.h
A ext/systemc/src/tlm_core/tlm_2/tlm_generic_payload/tlm_endian_conv.h
A ext/systemc/src/tlm_core/tlm_2/tlm_generic_payload/tlm_generic_payload.h
A ext/systemc/src/tlm_core/tlm_2/tlm_generic_payload/tlm_gp.h
A ext/systemc/src/tlm_core/tlm_2/tlm_generic_payload/tlm_helpers.h
A ext/systemc/src/tlm_core/tlm_2/tlm_generic_payload/tlm_phase.h
A ext/systemc/src/tlm_core/tlm_2/tlm_quantum/tlm_global_quantum.h
A ext/systemc/src/tlm_core/tlm_2/tlm_quantum/tlm_quantum.h
A ext/systemc/src/tlm_core/tlm_2/tlm_sockets/tlm_initiator_socket.h
A ext/systemc/src/tlm_core/tlm_2/tlm_sockets/tlm_sockets.h
A ext/systemc/src/tlm_core/tlm_2/tlm_sockets/tlm_target_socket.h
A ext/systemc/src/tlm_core/tlm_2/tlm_version.h
A ext/systemc/src/tlm_utils/README.txt
A ext/systemc/src/tlm_utils/instance_specific_extensions.h
A ext/systemc/src/tlm_utils/multi_passthrough_initiator_socket.h
A ext/systemc/src/tlm_utils/multi_passthrough_target_socket.h
A ext/systemc/src/tlm_utils/multi_socket_bases.h
A ext/systemc/src/tlm_utils/passthrough_target_socket.h
A ext/systemc/src/tlm_utils/peq_with_cb_and_phase.h
A ext/systemc/src/tlm_utils/peq_with_get.h
A ext/systemc/src/tlm_utils/simple_initiator_socket.h
A ext/systemc/src/tlm_utils/simple_target_socket.h
A ext/systemc/src/tlm_utils/tlm2_base_protocol_checker.h
A ext/systemc/src/tlm_utils/tlm_quantumkeeper.h
363 files changed, 138,304 insertions(+), 0 deletions(-)


--
To view, visit https://gem5-review.googlesource.com/2240
To unsubscribe, visit https://gem5-review.googlesource.com/settings

Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I4b66ec806b5e3cffc1d7c85d3735ff4fa5b31fd0
Gerrit-Change-Number: 2240
Gerrit-PatchSet: 6
Gerrit-Owner: Matthias Jung <jun...@eit.uni-kl.de>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Matthias Jung <jun...@eit.uni-kl.de>
Gerrit-Reviewer: Éder F. Zulian <ederf...@gmail.com>
Gerrit-CC: Jason Lowe-Power <ja...@lowepower.com>
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[gem5-dev] Change in public/gem5[master]: ext: Include SystemC 2.3.1 into gem5

[Matthias Jung (Gerrit)]

/systemc/src/tlm_core/tlm_1/README.txt
A ext/systemc/src/tlm_core/tlm_1/tlm_analysis/tlm_analysis.h
A ext/systemc/src/tlm_core/tlm_1/tlm_analysis/tlm_analysis_fifo.h
A ext/systemc/src/tlm_core/tlm_1/tlm_analysis/tlm_analysis_if.h
A ext/systemc/src/tlm_core/tlm_1/tlm_analysis/tlm_analysis_port.h
A ext/systemc/src/tlm_core/tlm_1/tlm_analysis/tlm_analysis_triple.h
A ext/systemc/src/tlm_core/tlm_1/tlm_analysis/tlm_write_if.h
A ext/systemc/src/tlm_core/tlm_1/tlm_req_rsp/tlm_1_interfaces/tlm_core_ifs.h
A ext/systemc/src/tlm_core/tlm_1/tlm_req_rsp/tlm_1_interfaces/tlm_fifo_ifs.h
A  
ext/systemc/src/tlm_core/tlm_1/tlm_req_rsp/tlm_1_interfaces/tlm_master_slave_ifs.h

A ext/systemc/src/tlm_core/tlm_1/tlm_req_rsp/tlm_1_interfaces/tlm_tag.h
A ext/systemc/src/tlm_core/tlm_1/tlm_req_rsp/tlm_adapters/tlm_adapters.h
A  
ext/systemc/src/tlm_core/tlm_1/tlm_req_rsp/tlm_channels/tlm_fifo/circular_buffer.h
A  
ext/systemc/src/tlm_core/tlm_1/tlm_req_rsp/tlm_channels/tlm_fifo/tlm_fifo.h
A  
ext/systemc/src/tlm_core/tlm_1/tlm_req_rsp/tlm_channels/tlm_fifo/tlm_fifo_peek.h
A  
ext/systemc/src/tlm_core/tlm_1/tlm_req_rsp/tlm_channels/tlm_fifo/tlm_fifo_put_get.h
A  
ext/systemc/src/tlm_core/tlm_1/tlm_req_rsp/tlm_channels/tlm_fifo/tlm_fifo_resize.h
A  
ext/systemc/src/tlm_core/tlm_1/tlm_req_rsp/tlm_channels/tlm_req_rsp_channels/tlm_put_get_imp.h
A  
ext/systemc/src/tlm_core/tlm_1/tlm_req_rsp/tlm_channels/tlm_req_rsp_channels/tlm_req_rsp_channels.h

A ext/systemc/src/tlm_core/tlm_1/tlm_req_rsp/tlm_ports/tlm_event_finder.h
A  
ext/systemc/src/tlm_core/tlm_1/tlm_req_rsp/tlm_ports/tlm_nonblocking_port.h

A ext/systemc/src/tlm_core/tlm_1/tlm_req_rsp/tlm_req_rsp.h
A ext/systemc/src/tlm_core/tlm_2/README.txt
A ext/systemc/src/tlm_core/tlm_2/tlm_2_interfaces/tlm_2_interfaces.h
A ext/systemc/src/tlm_core/tlm_2/tlm_2_interfaces/tlm_dmi.h
A ext/systemc/src/tlm_core/tlm_2/tlm_2_interfaces/tlm_fw_bw_ifs.h
A ext/systemc/src/tlm_core/tlm_2/tlm_generic_payload/tlm_array.h
A ext/systemc/src/tlm_core/tlm_2/tlm_generic_payload/tlm_endian_conv.h
A ext/systemc/src/tlm_core/tlm_2/tlm_generic_payload/tlm_generic_payload.h
A ext/systemc/src/tlm_core/tlm_2/tlm_generic_payload/tlm_gp.h
A ext/systemc/src/tlm_core/tlm_2/tlm_generic_payload/tlm_helpers.h
A ext/systemc/src/tlm_core/tlm_2/tlm_generic_payload/tlm_phase.h
A ext/systemc/src/tlm_core/tlm_2/tlm_quantum/tlm_global_quantum.h
A ext/systemc/src/tlm_core/tlm_2/tlm_quantum/tlm_quantum.h
A ext/systemc/src/tlm_core/tlm_2/tlm_sockets/tlm_initiator_socket.h
A ext/systemc/src/tlm_core/tlm_2/tlm_sockets/tlm_sockets.h
A ext/systemc/src/tlm_core/tlm_2/tlm_sockets/tlm_target_socket.h
A ext/systemc/src/tlm_core/tlm_2/tlm_version.h
A ext/systemc/src/tlm_utils/README.txt
A ext/systemc/src/tlm_utils/instance_specific_extensions.h
A ext/systemc/src/tlm_utils/multi_passthrough_initiator_socket.h
A ext/systemc/src/tlm_utils/multi_passthrough_target_socket.h
A ext/systemc/src/tlm_utils/multi_socket_bases.h
A ext/systemc/src/tlm_utils/passthrough_target_socket.h
A ext/systemc/src/tlm_utils/peq_with_cb_and_phase.h
A ext/systemc/src/tlm_utils/peq_with_get.h
A ext/systemc/src/tlm_utils/simple_initiator_socket.h
A ext/systemc/src/tlm_utils/simple_target_socket.h
A ext/systemc/src/tlm_utils/tlm2_base_protocol_checker.h
A ext/systemc/src/tlm_utils/tlm_quantumkeeper.h
363 files changed, 138,304 insertions(+), 0 deletions(-)


--
To view, visit https://gem5-review.googlesource.com/2240
To unsubscribe, visit https://gem5-review.googlesource.com/settings

Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I4b66ec806b5e3cffc1d7c85d3735ff4fa5b31fd0
Gerrit-Change-Number: 2240
Gerrit-PatchSet: 5
Gerrit-Owner: Matthias Jung <jun...@eit.uni-kl.de>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Matthias Jung <jun...@eit.uni-kl.de>
Gerrit-Reviewer: Éder F. Zulian <ederf...@gmail.com>
Gerrit-CC: Jason Lowe-Power <ja...@lowepower.com>
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Re: [gem5-dev] testing the gem5 library

[Matthias Jung]

Hi Andreas and Gabe,

thats still my plan, I’m preparing a regression test for the SystemC stuff.
I will upload it after my holidays ;) 

A good way to test is to run also the gem5/util/tlm/examples.

Regards
Matthias

> Am 29.04.2017 um 14:04 schrieb Andreas Hansson :
> 
> Hi Gabe,
> 
> The best would be to test the SystemC main.cc which is in util/systemc and
> links to libgem5. I know that Matthias has worked on getting SystemC
> included in ext so that we can build this all as part of the regressions.
> 
> Andreas
> 
> On 28/04/2017, 22:13, "gem5-dev on behalf of Gabe Black"
>  wrote:
> 
>> Hey folks. Does anyone know of a way to verify that the gem5 library
>> (build/ARM/libgem5_opt.so, for instance) still works? I have a change
>> ready
>> to go which affects how it's built, and I'd like to make sure I haven't
>> broken the library version of things before I check it in.
>> 
>> Gabe
>> ___
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>> gem5-dev@gem5.org
>> http://m5sim.org/mailman/listinfo/gem5-dev
> 
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Re: [gem5-dev] Review Request 3838: ext: Update DRAMPower

[Matthias Jung]

> On Feb. 26, 2017, 9:52 vorm., Andreas Hansson wrote:
> > Great. Thanks Matthias!
> > 
> > How can we best make sure the functionality is matched by the DRAMCtrl? Is 
> > there anyone that already played around with bank-wise refresh?
> 
> Radhika Jagtap wrote:
> I've got a patch that matches DRAMCtrl to the new DRAMPower API which I'm 
> working on merging with this ext/* patch to make a single commit. Expect a 
> post in a couple days. Not played around with bank-wise refresh yet. By 
> default it is disabled. The main issue now resloved is that intermediate 
> statsdump in gem5 will now use window energy calculations from DRAMPower to 
> give correct energy deltas over a statsdump period (previously the dumped 
> stats were cumulative).
> 
> Matthias Jung wrote:
> We have a full bankwise refresh implementation in DRAMSys. It shouldnt be 
> hard to bring that to gem5 too.

Should I bring this to the new git, as it is? or should i add a submodule?


- Matthias


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This is an automatically generated e-mail. To reply, visit:
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-------


On Feb. 24, 2017, 9:56 nachm., Matthias Jung wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3838/
> ---
> 
> (Updated Feb. 24, 2017, 9:56 nachm.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 11881:910b9376009a
> ---
> ext: Update DRAMPower
> 
> This patch syncs the DRAMPower library of gem5 to the external
> one on github (https://github.com/ravenrd/DRAMPower) of which
> I am one of the maintainers.
> 
> The version used is the commit:
> 90d6290f802c29b3de9e10233ceee22290907ce6
> from 30. Oct. 2016.
> 
> The new version features a bank-wise power estimation.
> Furthermore, PASR and Per-Bank Refresh is supported.
> 
> More Informtation can be found in the following papers:
> 
> A Bank-Wise DRAM Power Model for System Simulations
> Deepak M. Mathew, Eder F. Zulian, Subash. Kannoth, Matthias Jung, Christian 
> Weis, Norbert Wehn.
> International Conference on High-Performance and Embedded Architectures and 
> Compilers 2016 (HiPEAC), Workshop on: Rapid Simulation and Performance 
> Evaluation: Methods and Tools (RAPIDO), Stockholm, 2017.
> 
> A New Bank Sensitive DRAMPower Model for Efficient Design Space Exploration
> Matthias Jung, Deepak M. Mathew, Eder F. Zulian, Christian Weis, Norbert Wehn.
> International Workshop on Power And Timing Modeling, Optimization and 
> Simulation (PATMOS 2016), September, 2016, Bremen, Germany
> 
> 
> Diffs
> -
> 
>   ext/drampower/README.md 5ea85692a53e 
>   ext/drampower/SConscript 5ea85692a53e 
>   ext/drampower/src/CAHelpers.cc PRE-CREATION 
>   ext/drampower/src/CmdHandlers.cc PRE-CREATION 
>   ext/drampower/src/CommandAnalysis.h 5ea85692a53e 
>   ext/drampower/src/CommandAnalysis.cc 5ea85692a53e 
>   ext/drampower/src/MemBankWiseParams.h PRE-CREATION 
>   ext/drampower/src/MemBankWiseParams.cc PRE-CREATION 
>   ext/drampower/src/MemCommand.h 5ea85692a53e 
>   ext/drampower/src/MemPowerSpec.h 5ea85692a53e 
>   ext/drampower/src/MemPowerSpec.cc 5ea85692a53e 
>   ext/drampower/src/MemTimingSpec.h 5ea85692a53e 
>   ext/drampower/src/MemTimingSpec.cc 5ea85692a53e 
>   ext/drampower/src/MemoryPowerModel.h 5ea85692a53e 
>   ext/drampower/src/MemoryPowerModel.cc 5ea85692a53e 
>   ext/drampower/src/TraceParser.h 5ea85692a53e 
>   ext/drampower/src/TraceParser.cc 5ea85692a53e 
>   ext/drampower/src/libdrampower/LibDRAMPower.h 5ea85692a53e 
>   ext/drampower/src/libdrampower/LibDRAMPower.cc 5ea85692a53e 
>   ext/drampower/test/libdrampowertest/Makefile 5ea85692a53e 
>   ext/drampower/test/libdrampowertest/commands.trace 5ea85692a53e 
>   ext/drampower/test/libdrampowertest/lib_test.cc 5ea85692a53e 
> 
> Diff: http://reviews.gem5.org/r/3838/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Matthias Jung
> 
>

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[gem5-dev] Change in public/gem5[master]: ext: Include SystemC 2.3.1 into gem5

[Matthias Jung (Gerrit)]

Matthias Jung has uploaded this change for review. (  
https://gem5-review.googlesource.com/2240



Change subject: ext: Include SystemC 2.3.1 into gem5
..

ext: Include SystemC 2.3.1 into gem5

In the past it happened several times that some changes in gem5 broke the
SystemC coupling. Recently Accelera has changed the licence for SystemC from
their own licence to Apache2.0, which is compatible with gem5. However,  
SystemC
usually relies on the Boost library, but I was able to exchange the boost  
calls

by c++11 alternatives. The recent SystemC version is placed into /ext and is
integrated into gem5's build system. The goal is to integrate some SystemC
tests for the CI in some following patches.

Change-Id: I4b66ec806b5e3cffc1d7c85d3735ff4fa5b31fd0
---
M SConstruct
A ext/systemc/AUTHORS
A ext/systemc/ChangeLog
A ext/systemc/INSTALL
A ext/systemc/LICENSE
A ext/systemc/NEWS
A ext/systemc/NOTICE
A ext/systemc/README.md
A ext/systemc/README.sysc
A ext/systemc/RELEASENOTES
A ext/systemc/SConscript
A ext/systemc/src/README_TLM.txt
A ext/systemc/src/sysc/communication/sc_buffer.h
A ext/systemc/src/sysc/communication/sc_clock.cpp
A ext/systemc/src/sysc/communication/sc_clock.h
A ext/systemc/src/sysc/communication/sc_clock_ports.h
A ext/systemc/src/sysc/communication/sc_communication_ids.h
A ext/systemc/src/sysc/communication/sc_event_finder.cpp
A ext/systemc/src/sysc/communication/sc_event_finder.h
A ext/systemc/src/sysc/communication/sc_event_queue.cpp
A ext/systemc/src/sysc/communication/sc_event_queue.h
A ext/systemc/src/sysc/communication/sc_export.cpp
A ext/systemc/src/sysc/communication/sc_export.h
A ext/systemc/src/sysc/communication/sc_fifo.h
A ext/systemc/src/sysc/communication/sc_fifo_ifs.h
A ext/systemc/src/sysc/communication/sc_fifo_ports.h
A ext/systemc/src/sysc/communication/sc_host_mutex.h
A ext/systemc/src/sysc/communication/sc_interface.cpp
A ext/systemc/src/sysc/communication/sc_interface.h
A ext/systemc/src/sysc/communication/sc_mutex.cpp
A ext/systemc/src/sysc/communication/sc_mutex.h
A ext/systemc/src/sysc/communication/sc_mutex_if.h
A ext/systemc/src/sysc/communication/sc_port.cpp
A ext/systemc/src/sysc/communication/sc_port.h
A ext/systemc/src/sysc/communication/sc_prim_channel.cpp
A ext/systemc/src/sysc/communication/sc_prim_channel.h
A ext/systemc/src/sysc/communication/sc_semaphore.cpp
A ext/systemc/src/sysc/communication/sc_semaphore.h
A ext/systemc/src/sysc/communication/sc_semaphore_if.h
A ext/systemc/src/sysc/communication/sc_signal.cpp
A ext/systemc/src/sysc/communication/sc_signal.h
A ext/systemc/src/sysc/communication/sc_signal_ifs.h
A ext/systemc/src/sysc/communication/sc_signal_ports.cpp
A ext/systemc/src/sysc/communication/sc_signal_ports.h
A ext/systemc/src/sysc/communication/sc_signal_resolved.cpp
A ext/systemc/src/sysc/communication/sc_signal_resolved.h
A ext/systemc/src/sysc/communication/sc_signal_resolved_ports.cpp
A ext/systemc/src/sysc/communication/sc_signal_resolved_ports.h
A ext/systemc/src/sysc/communication/sc_signal_rv.h
A ext/systemc/src/sysc/communication/sc_signal_rv_ports.h
A ext/systemc/src/sysc/communication/sc_writer_policy.h
A ext/systemc/src/sysc/datatypes/bit/sc_bit.cpp
A ext/systemc/src/sysc/datatypes/bit/sc_bit.h
A ext/systemc/src/sysc/datatypes/bit/sc_bit_ids.h
A ext/systemc/src/sysc/datatypes/bit/sc_bit_proxies.h
A ext/systemc/src/sysc/datatypes/bit/sc_bv.h
A ext/systemc/src/sysc/datatypes/bit/sc_bv_base.cpp
A ext/systemc/src/sysc/datatypes/bit/sc_bv_base.h
A ext/systemc/src/sysc/datatypes/bit/sc_logic.cpp
A ext/systemc/src/sysc/datatypes/bit/sc_logic.h
A ext/systemc/src/sysc/datatypes/bit/sc_lv.h
A ext/systemc/src/sysc/datatypes/bit/sc_lv_base.cpp
A ext/systemc/src/sysc/datatypes/bit/sc_lv_base.h
A ext/systemc/src/sysc/datatypes/bit/sc_proxy.h
A ext/systemc/src/sysc/datatypes/fx/fx.h
A ext/systemc/src/sysc/datatypes/fx/sc_context.h
A ext/systemc/src/sysc/datatypes/fx/sc_fix.h
A ext/systemc/src/sysc/datatypes/fx/sc_fixed.h
A ext/systemc/src/sysc/datatypes/fx/sc_fx_ids.h
A ext/systemc/src/sysc/datatypes/fx/sc_fxcast_switch.cpp
A ext/systemc/src/sysc/datatypes/fx/sc_fxcast_switch.h
A ext/systemc/src/sysc/datatypes/fx/sc_fxdefs.cpp
A ext/systemc/src/sysc/datatypes/fx/sc_fxdefs.h
A ext/systemc/src/sysc/datatypes/fx/sc_fxnum.cpp
A ext/systemc/src/sysc/datatypes/fx/sc_fxnum.h
A ext/systemc/src/sysc/datatypes/fx/sc_fxnum_observer.cpp
A ext/systemc/src/sysc/datatypes/fx/sc_fxnum_observer.h
A ext/systemc/src/sysc/datatypes/fx/sc_fxtype_params.cpp
A ext/systemc/src/sysc/datatypes/fx/sc_fxtype_params.h
A ext/systemc/src/sysc/datatypes/fx/sc_fxval.cpp
A ext/systemc/src/sysc/datatypes/fx/sc_fxval.h
A ext/systemc/src/sysc/datatypes/fx/sc_fxval_observer.cpp
A ext/systemc/src/sysc/datatypes/fx/sc_fxval_observer.h
A ext/systemc/src/sysc/datatypes/fx/sc_ufix.h
A ext/systemc/src/sysc/datatypes/fx/sc_ufixed.h
A ext/systemc/src/sysc/datatypes/fx/scfx_ieee.h
A ext/systemc/src/sysc/datatypes/fx

Re: [gem5-dev] Review Request 3838: ext: Update DRAMPower

[Matthias Jung]

> On Feb. 26, 2017, 9:52 vorm., Andreas Hansson wrote:
> > Great. Thanks Matthias!
> > 
> > How can we best make sure the functionality is matched by the DRAMCtrl? Is 
> > there anyone that already played around with bank-wise refresh?
> 
> Radhika Jagtap wrote:
> I've got a patch that matches DRAMCtrl to the new DRAMPower API which I'm 
> working on merging with this ext/* patch to make a single commit. Expect a 
> post in a couple days. Not played around with bank-wise refresh yet. By 
> default it is disabled. The main issue now resloved is that intermediate 
> statsdump in gem5 will now use window energy calculations from DRAMPower to 
> give correct energy deltas over a statsdump period (previously the dumped 
> stats were cumulative).

We have a full bankwise refresh implementation in DRAMSys. It shouldnt be hard 
to bring that to gem5 too.


- Matthias


---
This is an automatically generated e-mail. To reply, visit:
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-------


On Feb. 24, 2017, 9:56 nachm., Matthias Jung wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3838/
> ---
> 
> (Updated Feb. 24, 2017, 9:56 nachm.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 11881:910b9376009a
> ---
> ext: Update DRAMPower
> 
> This patch syncs the DRAMPower library of gem5 to the external
> one on github (https://github.com/ravenrd/DRAMPower) of which
> I am one of the maintainers.
> 
> The version used is the commit:
> 90d6290f802c29b3de9e10233ceee22290907ce6
> from 30. Oct. 2016.
> 
> The new version features a bank-wise power estimation.
> Furthermore, PASR and Per-Bank Refresh is supported.
> 
> More Informtation can be found in the following papers:
> 
> A Bank-Wise DRAM Power Model for System Simulations
> Deepak M. Mathew, Eder F. Zulian, Subash. Kannoth, Matthias Jung, Christian 
> Weis, Norbert Wehn.
> International Conference on High-Performance and Embedded Architectures and 
> Compilers 2016 (HiPEAC), Workshop on: Rapid Simulation and Performance 
> Evaluation: Methods and Tools (RAPIDO), Stockholm, 2017.
> 
> A New Bank Sensitive DRAMPower Model for Efficient Design Space Exploration
> Matthias Jung, Deepak M. Mathew, Eder F. Zulian, Christian Weis, Norbert Wehn.
> International Workshop on Power And Timing Modeling, Optimization and 
> Simulation (PATMOS 2016), September, 2016, Bremen, Germany
> 
> 
> Diffs
> -
> 
>   ext/drampower/README.md 5ea85692a53e 
>   ext/drampower/SConscript 5ea85692a53e 
>   ext/drampower/src/CAHelpers.cc PRE-CREATION 
>   ext/drampower/src/CmdHandlers.cc PRE-CREATION 
>   ext/drampower/src/CommandAnalysis.h 5ea85692a53e 
>   ext/drampower/src/CommandAnalysis.cc 5ea85692a53e 
>   ext/drampower/src/MemBankWiseParams.h PRE-CREATION 
>   ext/drampower/src/MemBankWiseParams.cc PRE-CREATION 
>   ext/drampower/src/MemCommand.h 5ea85692a53e 
>   ext/drampower/src/MemPowerSpec.h 5ea85692a53e 
>   ext/drampower/src/MemPowerSpec.cc 5ea85692a53e 
>   ext/drampower/src/MemTimingSpec.h 5ea85692a53e 
>   ext/drampower/src/MemTimingSpec.cc 5ea85692a53e 
>   ext/drampower/src/MemoryPowerModel.h 5ea85692a53e 
>   ext/drampower/src/MemoryPowerModel.cc 5ea85692a53e 
>   ext/drampower/src/TraceParser.h 5ea85692a53e 
>   ext/drampower/src/TraceParser.cc 5ea85692a53e 
>   ext/drampower/src/libdrampower/LibDRAMPower.h 5ea85692a53e 
>   ext/drampower/src/libdrampower/LibDRAMPower.cc 5ea85692a53e 
>   ext/drampower/test/libdrampowertest/Makefile 5ea85692a53e 
>   ext/drampower/test/libdrampowertest/commands.trace 5ea85692a53e 
>   ext/drampower/test/libdrampowertest/lib_test.cc 5ea85692a53e 
> 
> Diff: http://reviews.gem5.org/r/3838/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Matthias Jung
> 
>

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Re: [gem5-dev] Review Request 3838: ext: Update DRAMPower

[Matthias Jung]

> On Feb. 25, 2017, 2:34 nachm., Jason Lowe-Power wrote:
> > Going forward, I think we should reconsider how we link other projects in 
> > the ext folder. Especially since we're moving to git, I wonder if we could 
> > use something like sub repos to get a similar effect without having to pull 
> > all of this code into the gem5 repo. I guess the downside to this would be 
> > an extra step for users to have to recursively clone the repo.
> > 
> > This comment is not on topic for this patch, sorry. This patch is fine as 
> > it is :).
> 
> Radhika Jagtap wrote:
> Yes, absolutely, we could use git sub modules. I'll look into this for 
> future.

I have good experiences w.r.t. submodules, We use them internally a lot. The 
only thing that is required is that people have to clone with an recursive flag:

git clone --recursive ssh.github.com/gem5/example/path


- Matthias


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---


On Feb. 24, 2017, 9:56 nachm., Matthias Jung wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3838/
> ---
> 
> (Updated Feb. 24, 2017, 9:56 nachm.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 11881:910b9376009a
> ---
> ext: Update DRAMPower
> 
> This patch syncs the DRAMPower library of gem5 to the external
> one on github (https://github.com/ravenrd/DRAMPower) of which
> I am one of the maintainers.
> 
> The version used is the commit:
> 90d6290f802c29b3de9e10233ceee22290907ce6
> from 30. Oct. 2016.
> 
> The new version features a bank-wise power estimation.
> Furthermore, PASR and Per-Bank Refresh is supported.
> 
> More Informtation can be found in the following papers:
> 
> A Bank-Wise DRAM Power Model for System Simulations
> Deepak M. Mathew, Eder F. Zulian, Subash. Kannoth, Matthias Jung, Christian 
> Weis, Norbert Wehn.
> International Conference on High-Performance and Embedded Architectures and 
> Compilers 2016 (HiPEAC), Workshop on: Rapid Simulation and Performance 
> Evaluation: Methods and Tools (RAPIDO), Stockholm, 2017.
> 
> A New Bank Sensitive DRAMPower Model for Efficient Design Space Exploration
> Matthias Jung, Deepak M. Mathew, Eder F. Zulian, Christian Weis, Norbert Wehn.
> International Workshop on Power And Timing Modeling, Optimization and 
> Simulation (PATMOS 2016), September, 2016, Bremen, Germany
> 
> 
> Diffs
> -
> 
>   ext/drampower/README.md 5ea85692a53e 
>   ext/drampower/SConscript 5ea85692a53e 
>   ext/drampower/src/CAHelpers.cc PRE-CREATION 
>   ext/drampower/src/CmdHandlers.cc PRE-CREATION 
>   ext/drampower/src/CommandAnalysis.h 5ea85692a53e 
>   ext/drampower/src/CommandAnalysis.cc 5ea85692a53e 
>   ext/drampower/src/MemBankWiseParams.h PRE-CREATION 
>   ext/drampower/src/MemBankWiseParams.cc PRE-CREATION 
>   ext/drampower/src/MemCommand.h 5ea85692a53e 
>   ext/drampower/src/MemPowerSpec.h 5ea85692a53e 
>   ext/drampower/src/MemPowerSpec.cc 5ea85692a53e 
>   ext/drampower/src/MemTimingSpec.h 5ea85692a53e 
>   ext/drampower/src/MemTimingSpec.cc 5ea85692a53e 
>   ext/drampower/src/MemoryPowerModel.h 5ea85692a53e 
>   ext/drampower/src/MemoryPowerModel.cc 5ea85692a53e 
>   ext/drampower/src/TraceParser.h 5ea85692a53e 
>   ext/drampower/src/TraceParser.cc 5ea85692a53e 
>   ext/drampower/src/libdrampower/LibDRAMPower.h 5ea85692a53e 
>   ext/drampower/src/libdrampower/LibDRAMPower.cc 5ea85692a53e 
>   ext/drampower/test/libdrampowertest/Makefile 5ea85692a53e 
>   ext/drampower/test/libdrampowertest/commands.trace 5ea85692a53e 
>   ext/drampower/test/libdrampowertest/lib_test.cc 5ea85692a53e 
> 
> Diff: http://reviews.gem5.org/r/3838/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Matthias Jung
> 
>

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[gem5-dev] Review Request 3838: ext: Update DRAMPower

[Matthias Jung]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3838/
---

Review request for Default.


Repository: gem5


Description
---

Changeset 11881:910b9376009a
---
ext: Update DRAMPower

This patch syncs the DRAMPower library of gem5 to the external
one on github (https://github.com/ravenrd/DRAMPower) of which
I am one of the maintainers.

The version used is the commit:
90d6290f802c29b3de9e10233ceee22290907ce6
from 30. Oct. 2016.

The new version features a bank-wise power estimation.
Furthermore, PASR and Per-Bank Refresh is supported.

More Informtation can be found in the following papers:

A Bank-Wise DRAM Power Model for System Simulations
Deepak M. Mathew, Eder F. Zulian, Subash. Kannoth, Matthias Jung, Christian 
Weis, Norbert Wehn.
International Conference on High-Performance and Embedded Architectures and 
Compilers 2016 (HiPEAC), Workshop on: Rapid Simulation and Performance 
Evaluation: Methods and Tools (RAPIDO), Stockholm, 2017.

A New Bank Sensitive DRAMPower Model for Efficient Design Space Exploration
Matthias Jung, Deepak M. Mathew, Eder F. Zulian, Christian Weis, Norbert Wehn.
International Workshop on Power And Timing Modeling, Optimization and 
Simulation (PATMOS 2016), September, 2016, Bremen, Germany


Diffs
-

  ext/drampower/README.md 5ea85692a53e 
  ext/drampower/SConscript 5ea85692a53e 
  ext/drampower/src/CAHelpers.cc PRE-CREATION 
  ext/drampower/src/CmdHandlers.cc PRE-CREATION 
  ext/drampower/src/CommandAnalysis.h 5ea85692a53e 
  ext/drampower/src/CommandAnalysis.cc 5ea85692a53e 
  ext/drampower/src/MemBankWiseParams.h PRE-CREATION 
  ext/drampower/src/MemBankWiseParams.cc PRE-CREATION 
  ext/drampower/src/MemCommand.h 5ea85692a53e 
  ext/drampower/src/MemPowerSpec.h 5ea85692a53e 
  ext/drampower/src/MemPowerSpec.cc 5ea85692a53e 
  ext/drampower/src/MemTimingSpec.h 5ea85692a53e 
  ext/drampower/src/MemTimingSpec.cc 5ea85692a53e 
  ext/drampower/src/MemoryPowerModel.h 5ea85692a53e 
  ext/drampower/src/MemoryPowerModel.cc 5ea85692a53e 
  ext/drampower/src/TraceParser.h 5ea85692a53e 
  ext/drampower/src/TraceParser.cc 5ea85692a53e 
  ext/drampower/src/libdrampower/LibDRAMPower.h 5ea85692a53e 
  ext/drampower/src/libdrampower/LibDRAMPower.cc 5ea85692a53e 
  ext/drampower/test/libdrampowertest/Makefile 5ea85692a53e 
  ext/drampower/test/libdrampowertest/commands.trace 5ea85692a53e 
  ext/drampower/test/libdrampowertest/lib_test.cc 5ea85692a53e 

Diff: http://reviews.gem5.org/r/3838/diff/


Testing
---


Thanks,

Matthias Jung

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[gem5-dev] Review Request 3812: ext: Include SystemC 2.3.1 into gem5

[Matthias Jung]

/systemc/src/sysc/qt/md/ksr1.s PRE-CREATION 
  ext/systemc/src/sysc/qt/md/ksr1_b.s PRE-CREATION 
  ext/systemc/src/sysc/qt/md/m88k.Makefile PRE-CREATION 
  ext/systemc/src/sysc/qt/md/m88k.h PRE-CREATION 
  ext/systemc/src/sysc/qt/md/m88k.c PRE-CREATION 
  ext/systemc/src/sysc/qt/md/m88k.s PRE-CREATION 
  ext/systemc/src/sysc/qt/md/m88k_b.s PRE-CREATION 
  ext/systemc/src/sysc/qt/md/mips-irix5.s PRE-CREATION 
  ext/systemc/src/sysc/qt/md/mips.h PRE-CREATION 
  ext/systemc/src/sysc/qt/md/mips.s PRE-CREATION 
  ext/systemc/src/sysc/qt/md/mips_b.s PRE-CREATION 
  ext/systemc/src/sysc/qt/md/null.c PRE-CREATION 
  ext/systemc/src/sysc/qt/md/null.s PRE-CREATION 
  ext/systemc/src/sysc/qt/md/powerpc.README PRE-CREATION 
  ext/systemc/src/sysc/qt/md/powerpc.c PRE-CREATION 
  ext/systemc/src/sysc/qt/md/powerpc_mach.h PRE-CREATION 
  ext/systemc/src/sysc/qt/md/powerpc_mach.s PRE-CREATION 
  ext/systemc/src/sysc/qt/md/powerpc_mach_b.s PRE-CREATION 
  ext/systemc/src/sysc/qt/md/powerpc_sys5.h PRE-CREATION 
  ext/systemc/src/sysc/qt/md/powerpc_sys5.s PRE-CREATION 
  ext/systemc/src/sysc/qt/md/powerpc_sys5_b.s PRE-CREATION 
  ext/systemc/src/sysc/qt/md/pthreads.Makefile PRE-CREATION 
  ext/systemc/src/sysc/qt/md/solaris.README PRE-CREATION 
  ext/systemc/src/sysc/qt/md/sparc.h PRE-CREATION 
  ext/systemc/src/sysc/qt/md/sparc.s PRE-CREATION 
  ext/systemc/src/sysc/qt/md/sparc_b.s PRE-CREATION 
  ext/systemc/src/sysc/qt/md/vax.h PRE-CREATION 
  ext/systemc/src/sysc/qt/md/vax.s PRE-CREATION 
  ext/systemc/src/sysc/qt/md/vax_b.s PRE-CREATION 
  ext/systemc/src/sysc/qt/meas.c PRE-CREATION 
  ext/systemc/src/sysc/qt/qt.h PRE-CREATION 
  ext/systemc/src/sysc/qt/qt.c PRE-CREATION 
  ext/systemc/src/sysc/qt/qtmd.h PRE-CREATION 
  ext/systemc/src/sysc/qt/stp.h PRE-CREATION 
  ext/systemc/src/sysc/qt/stp.c PRE-CREATION 
  ext/systemc/src/sysc/qt/time/README.time PRE-CREATION 
  ext/systemc/src/sysc/qt/time/assim PRE-CREATION 
  ext/systemc/src/sysc/qt/time/cswap PRE-CREATION 
  ext/systemc/src/sysc/qt/time/go PRE-CREATION 
  ext/systemc/src/sysc/qt/time/init PRE-CREATION 
  ext/systemc/src/sysc/qt/time/prim PRE-CREATION 
  ext/systemc/src/sysc/qt/time/raw PRE-CREATION 
  ext/systemc/src/sysc/systemc.pc.in PRE-CREATION 
  ext/systemc/src/sysc/tracing/sc_trace.h PRE-CREATION 
  ext/systemc/src/sysc/tracing/sc_trace.cpp PRE-CREATION 
  ext/systemc/src/sysc/tracing/sc_trace_file_base.h PRE-CREATION 
  ext/systemc/src/sysc/tracing/sc_trace_file_base.cpp PRE-CREATION 
  ext/systemc/src/sysc/tracing/sc_tracing_ids.h PRE-CREATION 
  ext/systemc/src/sysc/tracing/sc_vcd_trace.h PRE-CREATION 
  ext/systemc/src/sysc/tracing/sc_vcd_trace.cpp PRE-CREATION 
  ext/systemc/src/sysc/tracing/sc_wif_trace.h PRE-CREATION 
  ext/systemc/src/sysc/tracing/sc_wif_trace.cpp PRE-CREATION 
  ext/systemc/src/sysc/utils/sc_hash.h PRE-CREATION 
  ext/systemc/src/sysc/utils/sc_hash.cpp PRE-CREATION 
  ext/systemc/src/sysc/utils/sc_iostream.h PRE-CREATION 
  ext/systemc/src/sysc/utils/sc_list.h PRE-CREATION 
  ext/systemc/src/sysc/utils/sc_list.cpp PRE-CREATION 
  ext/systemc/src/sysc/utils/sc_machine.h PRE-CREATION 
  ext/systemc/src/sysc/utils/sc_mempool.h PRE-CREATION 
  ext/systemc/src/sysc/utils/sc_mempool.cpp PRE-CREATION 
  ext/systemc/src/sysc/utils/sc_pq.h PRE-CREATION 

Diff: http://reviews.gem5.org/r/3812/diff/


Testing
---


Thanks,

Matthias Jung

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Re: [gem5-dev] Review Request 3795: misc: Add Python.h header to pyevents.hh

[Matthias Jung]

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---

Ship it!


Ship It!

- Matthias Jung


On Jan. 27, 2017, 5:32 nachm., Jason Lowe-Power wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3795/
> ---
> 
> (Updated Jan. 27, 2017, 5:32 nachm.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> misc: Add Python.h header to pyevents.hh
> 
> 
> Diffs
> -
> 
>   src/python/swig/pyevent.hh cd7f3a1dbf55 
> 
> Diff: http://reviews.gem5.org/r/3795/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Jason Lowe-Power
> 
>

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Re: [gem5-dev] Review Request 3807: misc: fix includes in util/systemc

[Matthias Jung]

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---

Ship it!


Indeed, I have tested it, now it works

- Matthias Jung


On Feb. 5, 2017, 2:06 nachm., Christian Menard wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3807/
> ---
> 
> (Updated Feb. 5, 2017, 2:06 nachm.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 11809:54adb162f4ea
> ---
> misc: fix includes in util/systemc
> 
> This fixes compilation errors with clang on OS X.
> 
> 
> Diffs
> -
> 
>   util/systemc/sc_module.cc c10c50cb8ac9 
> 
> Diff: http://reviews.gem5.org/r/3807/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Christian Menard
> 
>

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Re: [gem5-dev] Review Request 3803: sim: Patch to fix the statfs build

[Matthias Jung]

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---

Ship it!


gem5 works again on macOS!
Thanks for repairing!

- Matthias Jung


On Feb. 3, 2017, 4:25 nachm., Bjoern A. Zeeb wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3803/
> ---
> 
> (Updated Feb. 3, 2017, 4:25 nachm.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> See developers mailing list.  Trying to unbreak statfs.
> 
> 
> Diffs
> -
> 
>   src/sim/syscall_emul.hh 63325e5b0a9d 
> 
> Diff: http://reviews.gem5.org/r/3803/diff/
> 
> 
> Testing
> ---
> 
> Builds on FreeBSD now.
> 
> 
> Thanks,
> 
> Bjoern A. Zeeb
> 
>

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Re: [gem5-dev] Review Request 3804: sim: fix build breakage in process.cc after brandon@11801

[Matthias Jung]

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---

Ship it!


Ship It!

- Matthias Jung


On Feb. 3, 2017, 4:29 nachm., Bjoern A. Zeeb wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3804/
> ---
> 
> (Updated Feb. 3, 2017, 4:29 nachm.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Seeing build breakage after brandon@11801:
> 
>  [ CXX] X86/sim/process.cc -> .o 
> build/X86/sim/process.cc:137:64: error: field '_pid' is uninitialized when 
> used here [-Werror,-Wuninitialized]
> static_cast(new ArchPageTable(name(), _pid, system)) 
> :
>^
> build/X86/sim/process.cc:138:64: error: field '_pid' is uninitialized when 
> used here [-Werror,-Wuninitialized]
> static_cast(new FuncPageTable(name(), _pid))),
>^
> 2 errors generated.
> 
> 
> Diffs
> -
> 
>   src/sim/process.cc 63325e5b0a9d 
> 
> Diff: http://reviews.gem5.org/r/3804/diff/
> 
> 
> Testing
> ---
> 
> Compiles now on FreeBSD 10 with clang.
> 
> 
> Thanks,
> 
> Bjoern A. Zeeb
> 
>

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Re: [gem5-dev] Review Request 3777: misc: Clean up and complete the gem5<->SystemC-TLM bridge [6/6]

[Matthias Jung]

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---

Ship it!


Ship It!

- Matthias Jung


On Feb. 2, 2017, 4:06 nachm., Christian Menard wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3777/
> ---
> 
> (Updated Feb. 2, 2017, 4:06 nachm.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 11799:2c639f8b2ab4
> ---
> misc: Clean up and complete the gem5<->SystemC-TLM bridge [6/6]
> 
> The current TLM bridge only provides a Slave Port that allows the gem5 world 
> to
> send request to the SystemC world. This patch series refractors and cleans up
> the existing code, and adds a Master Port that allows the SystemC world to 
> send
> requests to the gem5 world.
> 
> This patch:
>  * Update the README
> 
> 
> Diffs
> -
> 
>   util/tlm/README c10c50cb8ac9 
> 
> Diff: http://reviews.gem5.org/r/3777/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Christian Menard
> 
>

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Re: [gem5-dev] Review Request 3775: misc: Clean up and complete the gem5<->SystemC-TLM bridge [5/6]

[Matthias Jung]

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Ship it!


Ship It!

- Matthias Jung


On Feb. 2, 2017, 11:23 vorm., Christian Menard wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3775/
> ---
> 
> (Updated Feb. 2, 2017, 11:23 vorm.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 11798:3a490c57058d
> ---
> misc: Clean up and complete the gem5<->SystemC-TLM bridge [5/6]
> 
> The current TLM bridge only provides a Slave Port that allows the gem5 world 
> to
> send request to the SystemC world. This patch series refractors and cleans up
> the existing code, and adds a Master Port that allows the SystemC world to 
> send
> requests to the gem5 world.
> 
> This patch:
>  * Introduce transactor modules that represent the gem5 ports in the SystemC
>world.
>  * Update the SimControl module and let it keep track of the gem5 ports.
> 
> 
> Diffs
> -
> 
>   util/tlm/slave_transactor.hh PRE-CREATION 
>   util/tlm/slave_transactor.cc PRE-CREATION 
>   util/tlm/sc_slave_port.cc PRE-CREATION 
>   util/tlm/sim_control.hh PRE-CREATION 
>   util/tlm/sim_control.cc PRE-CREATION 
>   util/tlm/sim_control_if.hh PRE-CREATION 
>   util/tlm/examples/master_port/main.cc PRE-CREATION 
>   util/tlm/examples/master_port/tlm.py PRE-CREATION 
>   util/tlm/examples/slave_port/main.cc PRE-CREATION 
>   util/tlm/examples/slave_port/run_gem5.sh PRE-CREATION 
>   util/tlm/examples/slave_port/tlm.py PRE-CREATION 
>   util/tlm/master_transactor.hh PRE-CREATION 
>   util/tlm/master_transactor.cc PRE-CREATION 
>   util/tlm/sc_master_port.hh PRE-CREATION 
>   util/tlm/sc_master_port.cc PRE-CREATION 
>   util/tlm/sc_slave_port.hh PRE-CREATION 
> 
> Diff: http://reviews.gem5.org/r/3775/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Christian Menard
> 
>

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Re: [gem5-dev] Review Request 3774: misc: Implement the Base SystemC Module as an sc_channel.

[Matthias Jung]

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Ship it!


Ship It!

- Matthias Jung


On Jan. 9, 2017, 12:17 nachm., Christian Menard wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3774/
> ---
> 
> (Updated Jan. 9, 2017, 12:17 nachm.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> misc: Implement the Base SystemC Module as an sc_channel.
> 
> Implementing the Module as an sc_channel allows derived classes to provide
> SystemC interfaces. Other SystemC modules can connect to these interfaces. 
> This
> meachanism can be used to control gem5 and acces gem5 components from within
> arbitrary SystemC moduels. Since sc_channel is derived from sc_module, this
> patch does not break compatibility with existing code.
> 
> 
> Diffs
> -
> 
>   util/systemc/sc_module.hh c10c50cb8ac9 
>   util/systemc/sc_module.cc c10c50cb8ac9 
> 
> Diff: http://reviews.gem5.org/r/3774/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Christian Menard
> 
>

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Re: [gem5-dev] Review Request 3778: misc: Fix order of object construction in the CxxConfigManager

[Matthias Jung]

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---

Ship it!


Ship It!

- Matthias Jung


On Jan. 30, 2017, 2:37 nachm., Christian Menard wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3778/
> ---
> 
> (Updated Jan. 30, 2017, 2:37 nachm.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> The CxxConfigManager schould create objects by traversing the object tree 
> starting from the root object. However, currently objects are created in 
> aplphabetical order, which only works if the root object alphabetically comes 
> before any system object (e.g. 'root' < 'system'. Otherwise (e.g. 'a_system' 
> < 'root'), object construction may fail. The reason for this behaviour is, 
> that the call to findObject() in the sorting code also constructs the object 
> if it is not yet existent. Then findTraversalOrder() calls findObject("root") 
> and subseqeuently calls findObject() on all the children, and so on. However, 
> the call to findTraversalOrder() is redundant, since all objects are already 
> created in alphabetical order. This patch simply removes the alphabetical 
> ordering, leading to the objects being created starting from 'root'.
> 
> 
> Diffs
> -
> 
>   src/sim/cxx_manager.cc c10c50cb8ac9 
> 
> Diff: http://reviews.gem5.org/r/3778/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Christian Menard
> 
>

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Re: [gem5-dev] Review Request 3527: misc: Clean up and complete the gem5<->SystemC-TLM bridge [1/6]

[Matthias Jung]

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Ship it!


Ship It!

- Matthias Jung


On Jan. 30, 2017, 3:55 nachm., Christian Menard wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3527/
> ---
> 
> (Updated Jan. 30, 2017, 3:55 nachm.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 11794:3b95cfab373f
> ---
> misc: Clean up and complete the gem5<->SystemC-TLM bridge [1/6]
> 
> The current TLM bridge only provides a Slave Port that allows the gem5 world 
> to
> send request to the SystemC world. This patch series refractors and cleans up
> the existing code, and adds a Master Port that allows the SystemC world to 
> send
> requests to the gem5 world.
> 
> This patch:
>  * Restructure the existing sources in preparation of the addition of the new
>Master Port.
>  * Refractor names to allow for distinction of the slave and master port.
>  * Replace the Makefile by a SConstruct.
> 
> 
> Diffs
> -
> 
>   configs/common/MemConfig.py c10c50cb8ac9 
>   util/tlm/sc_ext.hh c10c50cb8ac9 
>   util/tlm/sc_ext.cc c10c50cb8ac9 
>   util/tlm/sc_mm.hh c10c50cb8ac9 
>   util/tlm/sc_mm.cc c10c50cb8ac9 
>   util/tlm/sc_peq.hh PRE-CREATION 
>   util/tlm/sc_port.hh c10c50cb8ac9 
>   util/tlm/sc_port.cc c10c50cb8ac9 
>   util/tlm/sc_slave_port.hh PRE-CREATION 
>   util/tlm/sc_slave_port.cc PRE-CREATION 
>   util/tlm/sc_target.hh c10c50cb8ac9 
>   util/tlm/sc_target.cc c10c50cb8ac9 
>   util/tlm/sim_control.hh PRE-CREATION 
>   util/tlm/sim_control.cc PRE-CREATION 
>   util/tlm/tgen.cfg c10c50cb8ac9 
>   util/tlm/tlm.py c10c50cb8ac9 
>   util/tlm/tlm_elastic.py c10c50cb8ac9 
>   util/tlm/Makefile c10c50cb8ac9 
>   util/tlm/examples/slave_port/SConstruct PRE-CREATION 
>   util/tlm/examples/slave_port/main.cc PRE-CREATION 
>   util/tlm/examples/slave_port/run_gem5.sh PRE-CREATION 
>   util/tlm/examples/slave_port/sc_target.hh PRE-CREATION 
>   util/tlm/examples/slave_port/sc_target.cc PRE-CREATION 
>   util/tlm/examples/slave_port/tgen.cfg PRE-CREATION 
>   util/tlm/examples/slave_port/tlm.py PRE-CREATION 
>   util/tlm/examples/slave_port/tlm_elastic.py PRE-CREATION 
>   util/tlm/main.cc c10c50cb8ac9 
>   util/tlm/run_gem5.sh c10c50cb8ac9 
> 
> Diff: http://reviews.gem5.org/r/3527/diff/
> 
> 
> Testing
> ---
> 
> The examples provided in util/tlm (now util/tlm/examples/slave_port) still 
> compile and run error free.
> 
> 
> Thanks,
> 
> Christian Menard
> 
>

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Re: [gem5-dev] Review Request 3686: misc: Clean up and complete the gem5<->SystemC-TLM bridge [3/6]

[Matthias Jung]

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Ship it!


Ship It!

- Matthias Jung


On Jan. 30, 2017, 4:03 nachm., Christian Menard wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3686/
> ---
> 
> (Updated Jan. 30, 2017, 4:03 nachm.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 11796:362dd9be3b96
> ---
> misc: Clean up and complete the gem5<->SystemC-TLM bridge [3/6]
> 
> The current TLM bridge only provides a Slave Port that allows the gem5 world 
> to
> send request to the SystemC world. This patch series refractors and cleans up
> the existing code, and adds a Master Port that allows the SystemC world to 
> send
> requests to the gem5 world.
> 
> This patch:
>  * Simplify the Slave Port by using a simple_initiator_socket.
> 
> 
> Diffs
> -
> 
>   util/tlm/sc_slave_port.hh PRE-CREATION 
>   util/tlm/sc_slave_port.cc PRE-CREATION 
> 
> Diff: http://reviews.gem5.org/r/3686/diff/
> 
> 
> Testing
> ---
> 
> Example applications are still running.
> 
> 
> Thanks,
> 
> Christian Menard
> 
>

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Re: [gem5-dev] Review Request 3528: misc: Clean up and complete the gem5<->SystemC-TLM bridge [2/6]

[Matthias Jung]

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Ship it!


Ship It!

- Matthias Jung


On Feb. 2, 2017, 3:59 nachm., Christian Menard wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3528/
> ---
> 
> (Updated Feb. 2, 2017, 3:59 nachm.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 11795:321da7e75035
> ---
> misc: Clean up and complete the gem5<->SystemC-TLM bridge [2/6]
> 
> The current TLM bridge only provides a Slave Port that allows the gem5 world 
> to
> send request to the SystemC world. This patch series refractors and cleans up
> the existing code, and adds a Master Port that allows the SystemC world to 
> send
> requests to the gem5 world.
> 
> This patch:
>  * Add the Master Port.
>  * Add an example application that isslustrates its use.
> 
> 
> Diffs
> -
> 
>   util/tlm/sc_master_port.hh PRE-CREATION 
>   util/tlm/sc_master_port.cc PRE-CREATION 
>   util/tlm/sim_control.cc PRE-CREATION 
>   util/tlm/examples/master_port/tlm.py PRE-CREATION 
>   util/tlm/examples/master_port/traffic_generator.hh PRE-CREATION 
>   util/tlm/examples/master_port/traffic_generator.cc PRE-CREATION 
>   util/tlm/examples/master_port/SConstruct PRE-CREATION 
>   util/tlm/examples/master_port/main.cc PRE-CREATION 
> 
> Diff: http://reviews.gem5.org/r/3528/diff/
> 
> 
> Testing
> ---
> 
> A simple example application consisting of a TLM traffic generator and a gem5 
> memory is part of the patch.
> 
> 
> Thanks,
> 
> Christian Menard
> 
>

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Re: [gem5-dev] Review Request 3799: misc: Clean up and complete the gem5<->SystemC-TLM bridge [10/6]

[Matthias Jung]

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Ship it!


Ship It!

- Matthias Jung


On Jan. 31, 2017, 10:58 vorm., Christian Menard wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3799/
> ---
> 
> (Updated Jan. 31, 2017, 10:58 vorm.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 11803:ee5f72396d89
> ---
> misc: Clean up and complete the gem5<->SystemC-TLM bridge [10/6]
> 
> The current TLM bridge only provides a Slave Port that allows the gem5 world 
> to
> send request to the SystemC world. This patch series refractors and cleans up
> the existing code, and adds a Master Port that allows the SystemC world to 
> send
> requests to the gem5 world.
> 
> This patch:
>   * Add callbacks for the Gem5SimControl that are called at before and after
> simulate()
> 
> 
> Diffs
> -
> 
>   util/tlm/sim_control.hh PRE-CREATION 
>   util/tlm/sim_control.cc PRE-CREATION 
> 
> Diff: http://reviews.gem5.org/r/3799/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Christian Menard
> 
>

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Re: [gem5-dev] Review Request 3798: misc: Clean up and complete the gem5<->SystemC-TLM bridge [9/6]

[Matthias Jung]

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Ship it!


Ship It!

- Matthias Jung


On Feb. 1, 2017, 5:57 nachm., Christian Menard wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3798/
> ---
> 
> (Updated Feb. 1, 2017, 5:57 nachm.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 11802:31b809f6c634
> ---
> misc: Clean up and complete the gem5<->SystemC-TLM bridge [9/6]
> 
> The current TLM bridge only provides a Slave Port that allows the gem5 world 
> to
> send request to the SystemC world. This patch series refractors and cleans up
> the existing code, and adds a Master Port that allows the SystemC world to 
> send
> requests to the gem5 world.
> 
> This patch:
>   * Pay for the header delay that the gem5 XBar annotates to packets.
> 
> 
> Diffs
> -
> 
>   util/tlm/sc_master_port.cc PRE-CREATION 
>   util/tlm/sc_slave_port.cc PRE-CREATION 
> 
> Diff: http://reviews.gem5.org/r/3798/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Christian Menard
> 
>

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Re: [gem5-dev] Review Request 3796: misc: Clean up and complete the gem5<->SystemC-TLM bridge [7/6]

[Matthias Jung]

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Ship it!


Ship It!

- Matthias Jung


On Jan. 30, 2017, 4:13 nachm., Christian Menard wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3796/
> ---
> 
> (Updated Jan. 30, 2017, 4:13 nachm.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 11800:b5ad6c483119
> ---
> misc: Clean up and complete the gem5<->SystemC-TLM bridge [7/6]
> 
> The current TLM bridge only provides a Slave Port that allows the gem5 world 
> to
> send request to the SystemC world. This patch series refractors and cleans up
> the existing code, and adds a Master Port that allows the SystemC world to 
> send
> requests to the gem5 world.
> 
> This patch:
>  * Implement 'pipe through' for gem5 Packets (see explanation below)
> 
> Basically, this patch ensures that all transactions that originated in the 
> gem5
> world are converted back to the original packet when entering the gem5 world.
> So far, this only worked for packets that are responded to by a SyctemC
> component (e.g. when a gem5 CPU sends a request to a SystemC memory). By
> implementing the 'pipe through' this patch ensures, that packets that are
> responded to by a gem5 component (e.g. when a gem5 CPU sends a request to a
> gem5 memory via a SystemC interconnect) are handled properly.
> 
> 
> Diffs
> -
> 
>   util/tlm/sc_ext.hh c10c50cb8ac9 
>   util/tlm/sc_ext.cc c10c50cb8ac9 
>   util/tlm/sc_master_port.hh PRE-CREATION 
>   util/tlm/sc_master_port.cc PRE-CREATION 
>   util/tlm/sc_slave_port.cc PRE-CREATION 
> 
> Diff: http://reviews.gem5.org/r/3796/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Christian Menard
> 
>

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Re: [gem5-dev] Review Request 3797: misc: Clean up and complete the gem5<->SystemC-TLM bridge [8/6]

[Matthias Jung]

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Ship it!


Ship It!

- Matthias Jung


On Jan. 30, 2017, 4:38 nachm., Christian Menard wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3797/
> ---
> 
> (Updated Jan. 30, 2017, 4:38 nachm.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 11801:de4b2f94184c
> ---
> misc: Clean up and complete the gem5<->SystemC-TLM bridge [7/6]
> 
> The current TLM bridge only provides a Slave Port that allows the gem5 world 
> to
> send request to the SystemC world. This patch series refractors and cleans up
> the existing code, and adds a Master Port that allows the SystemC world to 
> send
> requests to the gem5 world.
> 
> This patch:
>   * bugfix: The BEGIN_RESP also needs to be handled when END_REQ was skipped
> and ' == blockingRequest && phase == tlm::BEGIN_RESP'
> evaluates to true.
> 
> 
> Diffs
> -
> 
>   util/tlm/sc_slave_port.cc PRE-CREATION 
> 
> Diff: http://reviews.gem5.org/r/3797/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Christian Menard
> 
>

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Re: [gem5-dev] Review Request 3695: misc: Clean up and complete the gem5<->SystemC-TLM bridge [4/6]

[Matthias Jung]

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Ship it!


Ship It!

- Matthias Jung


On Jan. 30, 2017, 4:49 nachm., Christian Menard wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3695/
> ---
> 
> (Updated Jan. 30, 2017, 4:49 nachm.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 11797:10f25f7e5c12
> ---
> misc: Clean up and complete the gem5<->SystemC-TLM bridge [4/6]
> 
> The current TLM bridge only provides a Slave Port that allows the gem5 world 
> to
> send request to the SystemC world. This patch series refractors and cleans up
> the existing code, and adds a Master Port that allows the SystemC world to 
> send
> requests to the gem5 world.
> 
> This patch:
>  * Move common code of the example to a common directory.
>  * Move the cli parsing from the SimControl module to a separate example 
> object.
>  * Add comments describing the Gem5SimControl module.
> 
> 
> Diffs
> -
> 
>   util/tlm/examples/common/cli_parser.hh PRE-CREATION 
>   util/tlm/examples/common/cli_parser.cc PRE-CREATION 
>   util/tlm/examples/common/report_handler.hh PRE-CREATION 
>   util/tlm/examples/common/report_handler.cc PRE-CREATION 
>   util/tlm/examples/master_port/SConstruct PRE-CREATION 
>   util/tlm/examples/master_port/main.cc PRE-CREATION 
>   util/tlm/examples/slave_port/SConstruct PRE-CREATION 
>   util/tlm/examples/slave_port/main.cc PRE-CREATION 
>   util/tlm/sim_control.hh PRE-CREATION 
>   util/tlm/sim_control.cc PRE-CREATION 
> 
> Diff: http://reviews.gem5.org/r/3695/diff/
> 
> 
> Testing
> ---
> 
> Examples compile and run.
> 
> 
> Thanks,
> 
> Christian Menard
> 
>

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Re: [gem5-dev] Review Request 3775: misc: Clean up and complete the gem5<->SystemC-TLM bridge [5/6]

[Matthias Jung]

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I have one small remark:

in the file run_gem5.sh, this:

```sh
--tlm-memory=memory \
```

should be this:

```sh
--tlm-memory=transactor \
```

Regards
Matthias

- Matthias Jung


On Jan. 30, 2017, 4:05 nachm., Christian Menard wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3775/
> ---
> 
> (Updated Jan. 30, 2017, 4:05 nachm.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 11798:dfab50bb946b
> ---
> misc: Clean up and complete the gem5<->SystemC-TLM bridge [5/6]
> 
> The current TLM bridge only provides a Slave Port that allows the gem5 world 
> to
> send request to the SystemC world. This patch series refractors and cleans up
> the existing code, and adds a Master Port that allows the SystemC world to 
> send
> requests to the gem5 world.
> 
> This patch:
>  * Introduce transactor modules that represent the gem5 ports in the SystemC
>world.
>  * Update the SimControl module and let it keep track of the gem5 ports.
> 
> 
> Diffs
> -
> 
>   util/tlm/examples/master_port/main.cc PRE-CREATION 
>   util/tlm/examples/master_port/tlm.py PRE-CREATION 
>   util/tlm/examples/slave_port/main.cc PRE-CREATION 
>   util/tlm/examples/slave_port/tlm.py PRE-CREATION 
>   util/tlm/master_transactor.hh PRE-CREATION 
>   util/tlm/master_transactor.cc PRE-CREATION 
>   util/tlm/sc_master_port.hh PRE-CREATION 
>   util/tlm/sc_master_port.cc PRE-CREATION 
>   util/tlm/sc_slave_port.hh PRE-CREATION 
>   util/tlm/sc_slave_port.cc PRE-CREATION 
>   util/tlm/sim_control.hh PRE-CREATION 
>   util/tlm/sim_control.cc PRE-CREATION 
>   util/tlm/sim_control_if.hh PRE-CREATION 
>   util/tlm/slave_transactor.hh PRE-CREATION 
>   util/tlm/slave_transactor.cc PRE-CREATION 
> 
> Diff: http://reviews.gem5.org/r/3775/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Christian Menard
> 
>

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Re: [gem5-dev] Compilation error for gem5 after statfs change

[Matthias Jung]

Hi Bjoern,

on my MAC I run into the same issue:
http://qa.gem5.org//1905/compiling-problem-gem5-mac-os-10-11-6-scons-build-arm-gem5-opt


When I use your patch I run into some other errors:

In file included from build/ARM/arch/arm/linux/process.cc:56:
build/ARM/sim/syscall_emul.hh:545:41: error: no member named 'f_namemax' in 
'statfs'
tgt->f_namelen = TheISA::htog(host->f_namemax);
    ^
build/ARM/sim/syscall_emul.hh:551:34: error: no member named 'f_spare' in 
'statfs'
memcpy(>f_spare, >f_spare, sizeof(host->f_spare));
     ^
build/ARM/sim/syscall_emul.hh:551:56: error: no member named 'f_spare' in 
'statfs'
memcpy(>f_spare, >f_spare, sizeof(host->f_spare));
   ^
3 errors generated.
scons: *** [build/ARM/arch/arm/linux/process.o] Error 1
scons: building terminated because of errors.


If I can help somehow to fix it and get gem5 running on OSX again please let me 
know.


Regards
Matthias


> Am 25.01.2017 um 00:46 schrieb Bjoern A. Zeeb 
> :
> 
> On 24 Jan 2017, at 22:08, Jason Lowe-Power wrote:
> 
>> Hi Brandon,
>> 
>> I think this is a "real" bug:
>> http://qa.gem5.org//1905/compiling-problem-gem5-mac-os-10-11-6-scons-build-arm-gem5-opt.
>> I think there are a few more places that need an #ifdef NO_STATFS. Could
>> you look into it and post a patch if there's a problem? If not, please
>> reply to the gem5 QA post and let them know.
> 
> Can people try this one and probably get the #ifdefs right for NetBSD as 
> well?  There are at least 3 different checks for that code;  if people don’t 
> care about “style” I could get it right, but ..
> 
> diff -r e47703369039 src/sim/syscall_emul.hh
> --- a/src/sim/syscall_emul.hh   Fri Jan 20 14:12:58 2017 -0500
> +++ b/src/sim/syscall_emul.hh   Tue Jan 24 23:45:04 2017 +
> @@ -70,6 +70,8 @@
> #include 
> #if (NO_STATFS == 0)
> #include 
> +#else
> +#include 
> #endif
> #include 
> #include 
> @@ -530,20 +532,25 @@
> {
> TypedBufferArg tgt(addr);
> 
> +tgt->f_type = TheISA::htog(host->f_type);
> #if defined(__OpenBSD__) || defined(__APPLE__) || defined(__FreeBSD__)
> -tgt->f_type = 0;
> +tgt->f_bsize = TheISA::htog(host->f_iosize);
> #else
> -tgt->f_type = TheISA::htog(host->f_type);
> +tgt->f_bsize = TheISA::htog(host->f_bsize);
> #endif
> -tgt->f_bsize = TheISA::htog(host->f_bsize);
> tgt->f_blocks = TheISA::htog(host->f_blocks);
> tgt->f_bfree = TheISA::htog(host->f_bfree);
> tgt->f_bavail = TheISA::htog(host->f_bavail);
> tgt->f_files = TheISA::htog(host->f_files);
> tgt->f_ffree = TheISA::htog(host->f_ffree);
> memcpy(>f_fsid, >f_fsid, sizeof(host->f_fsid));
> +#if defined(__OpenBSD__) || defined(__APPLE__) || defined(__FreeBSD__)
> +tgt->f_namelen = TheISA::htog(host->f_namemax);
> +tgt->f_frsize = TheISA::htog(host->f_bsize);
> +#else
> tgt->f_namelen = TheISA::htog(host->f_namelen);
> tgt->f_frsize = TheISA::htog(host->f_frsize);
> +#endif
> memcpy(>f_spare, >f_spare, sizeof(host->f_spare));
> 
> tgt.copyOut(mem);
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Re: [gem5-dev] Review Request 3360: misc: Add support for switching multiple cores in SystemC

[Matthias Jung]

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Ship it!


Ship It!

- Matthias Jung


On Dez. 16, 2016, 4:24 nachm., Paul Rosenfeld wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3360/
> ---
> 
> (Updated Dez. 16, 2016, 4:24 nachm.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 11763:0b76489963ee
> ---
> misc: Add support for switching multiple cores in SystemC
> 
> This patch adds a '-n' flag to the gem5 SystemC driver which allows
> multiple CPUs to be switched out to a new CPU. Primarily this involves
> appending CPU numbers to the objects searched for in the config
> manager if there are multiple CPUs in the system.
> 
> Note that an equivalent change should be made to the util/cxx_config driver,
> but I wanted to get input on this first before making the same change over
> there
> 
> 
> Diffs
> -
> 
>   util/systemc/main.cc 29d401db3746 
> 
> Diff: http://reviews.gem5.org/r/3360/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Paul Rosenfeld
> 
>

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Re: [gem5-dev] Review Request 3783: mem: Update DRAM configuration names

[Matthias Jung]

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---


For me it looks nice:

it addresses an issue that I raised before because there was only one DDR4 x16 
Device with 8 banks.
Now we have also x8 and x4 with 16 banks.

- Matthias Jung


On Jan. 17, 2017, 10:04 nachm., Curtis Dunham wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3783/
> ---
> 
> (Updated Jan. 17, 2017, 10:04 nachm.)
> 
> 
> Review request for Default and Matthias Jung.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> mem: Update DRAM configuration names
> 
> Names of DRAM configurations were updated to reflect both
> the channel and device data width.
> 
> Previous naming format was:
>   __
> 
> The following nomenclature is now used:
>   __x
> where n = The number of devices per rank on the channel
>   x = Device width
> 
> Total channel width can be calculated by n*w
> 
> Example:
> A 64-bit DDR4, 2400 channel consisting of 4-bit devices:
>   n = 16
>   w = 4
> The resulting configuration name is:
>   DDR4_2400_16x4
> 
> Updated scripts to match new naming convention.
> 
> Added unique configurations for DDR4 for:
> 1) 16x4
> 2) 8x8
> 3) 4x16
> 
> Change-Id: Ibd7f763b7248835c624309143cb9fc29d56a69d1
> Reviewed-by: Radhika Jagtap <radhika.jag...@arm.com>
> Reviewed-by: Curtis Dunham <curtis.dun...@arm.com>
> 
> 
> Diffs
> -
> 
>   tests/configs/realview-simple-timing-dual.py 97eebddaae84 
>   tests/configs/realview-simple-timing.py 97eebddaae84 
>   tests/configs/realview-switcheroo-full.py 97eebddaae84 
>   tests/configs/realview-switcheroo-o3.py 97eebddaae84 
>   tests/configs/realview-switcheroo-timing.py 97eebddaae84 
>   tests/configs/realview64-minor-dual.py 97eebddaae84 
>   tests/configs/realview64-minor.py 97eebddaae84 
>   tests/configs/realview64-o3-checker.py 97eebddaae84 
>   tests/configs/o3-timing-checker.py 97eebddaae84 
>   tests/configs/o3-timing-mp.py 97eebddaae84 
>   tests/configs/o3-timing-mt.py 97eebddaae84 
>   tests/configs/o3-timing.py 97eebddaae84 
>   tests/configs/pc-o3-timing.py 97eebddaae84 
>   tests/configs/pc-simple-timing.py 97eebddaae84 
>   tests/configs/pc-switcheroo-full.py 97eebddaae84 
>   tests/configs/realview-minor-dual.py 97eebddaae84 
>   tests/configs/realview-minor.py 97eebddaae84 
>   tests/configs/realview-o3-checker.py 97eebddaae84 
>   tests/configs/realview-o3-dual.py 97eebddaae84 
>   tests/configs/realview-o3.py 97eebddaae84 
>   src/mem/DRAMCtrl.py 97eebddaae84 
>   tests/configs/minor-timing-mp.py 97eebddaae84 
>   tests/configs/minor-timing.py 97eebddaae84 
>   configs/example/memcheck.py 97eebddaae84 
>   configs/learning_gem5/part1/simple.py 97eebddaae84 
>   configs/learning_gem5/part1/two_level.py 97eebddaae84 
>   configs/common/HMC.py 97eebddaae84 
>   configs/common/MemConfig.py 97eebddaae84 
>   configs/common/Options.py 97eebddaae84 
>   configs/dram/lat_mem_rd.py 97eebddaae84 
>   configs/dram/sweep.py 97eebddaae84 
>   configs/example/hmctest.py 97eebddaae84 
>   tests/configs/realview64-o3-dual.py 97eebddaae84 
>   tests/configs/realview64-o3.py 97eebddaae84 
>   tests/configs/realview64-simple-timing-dual.py 97eebddaae84 
>   tests/configs/realview64-simple-timing.py 97eebddaae84 
>   tests/configs/realview64-switcheroo-full.py 97eebddaae84 
>   tests/configs/realview64-switcheroo-o3.py 97eebddaae84 
>   tests/configs/realview64-switcheroo-timing.py 97eebddaae84 
>   tests/configs/tgen-dram-ctrl.py 97eebddaae84 
>   tests/configs/tsunami-minor-dual.py 97eebddaae84 
>   tests/configs/tsunami-minor.py 97eebddaae84 
>   tests/configs/tsunami-o3-dual.py 97eebddaae84 
>   tests/configs/tsunami-o3.py 97eebddaae84 
>   tests/configs/tsunami-simple-timing-dual.py 97eebddaae84 
>   tests/configs/tsunami-simple-timing.py 97eebddaae84 
>   tests/configs/tsunami-switcheroo-full.py 97eebddaae84 
> 
> Diff: http://reviews.gem5.org/r/3783/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Curtis Dunham
> 
>

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Re: [gem5-dev] Review Request 3783: mem: Update DRAM configuration names

[Matthias Jung]

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---

Ship it!


Ship It!

- Matthias Jung


On Jan. 17, 2017, 10:04 nachm., Curtis Dunham wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3783/
> ---
> 
> (Updated Jan. 17, 2017, 10:04 nachm.)
> 
> 
> Review request for Default and Matthias Jung.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> mem: Update DRAM configuration names
> 
> Names of DRAM configurations were updated to reflect both
> the channel and device data width.
> 
> Previous naming format was:
>   __
> 
> The following nomenclature is now used:
>   __x
> where n = The number of devices per rank on the channel
>   x = Device width
> 
> Total channel width can be calculated by n*w
> 
> Example:
> A 64-bit DDR4, 2400 channel consisting of 4-bit devices:
>   n = 16
>   w = 4
> The resulting configuration name is:
>   DDR4_2400_16x4
> 
> Updated scripts to match new naming convention.
> 
> Added unique configurations for DDR4 for:
> 1) 16x4
> 2) 8x8
> 3) 4x16
> 
> Change-Id: Ibd7f763b7248835c624309143cb9fc29d56a69d1
> Reviewed-by: Radhika Jagtap <radhika.jag...@arm.com>
> Reviewed-by: Curtis Dunham <curtis.dun...@arm.com>
> 
> 
> Diffs
> -
> 
>   tests/configs/realview-simple-timing-dual.py 97eebddaae84 
>   tests/configs/realview-simple-timing.py 97eebddaae84 
>   tests/configs/realview-switcheroo-full.py 97eebddaae84 
>   tests/configs/realview-switcheroo-o3.py 97eebddaae84 
>   tests/configs/realview-switcheroo-timing.py 97eebddaae84 
>   tests/configs/realview64-minor-dual.py 97eebddaae84 
>   tests/configs/realview64-minor.py 97eebddaae84 
>   tests/configs/realview64-o3-checker.py 97eebddaae84 
>   tests/configs/o3-timing-checker.py 97eebddaae84 
>   tests/configs/o3-timing-mp.py 97eebddaae84 
>   tests/configs/o3-timing-mt.py 97eebddaae84 
>   tests/configs/o3-timing.py 97eebddaae84 
>   tests/configs/pc-o3-timing.py 97eebddaae84 
>   tests/configs/pc-simple-timing.py 97eebddaae84 
>   tests/configs/pc-switcheroo-full.py 97eebddaae84 
>   tests/configs/realview-minor-dual.py 97eebddaae84 
>   tests/configs/realview-minor.py 97eebddaae84 
>   tests/configs/realview-o3-checker.py 97eebddaae84 
>   tests/configs/realview-o3-dual.py 97eebddaae84 
>   tests/configs/realview-o3.py 97eebddaae84 
>   src/mem/DRAMCtrl.py 97eebddaae84 
>   tests/configs/minor-timing-mp.py 97eebddaae84 
>   tests/configs/minor-timing.py 97eebddaae84 
>   configs/example/memcheck.py 97eebddaae84 
>   configs/learning_gem5/part1/simple.py 97eebddaae84 
>   configs/learning_gem5/part1/two_level.py 97eebddaae84 
>   configs/common/HMC.py 97eebddaae84 
>   configs/common/MemConfig.py 97eebddaae84 
>   configs/common/Options.py 97eebddaae84 
>   configs/dram/lat_mem_rd.py 97eebddaae84 
>   configs/dram/sweep.py 97eebddaae84 
>   configs/example/hmctest.py 97eebddaae84 
>   tests/configs/realview64-o3-dual.py 97eebddaae84 
>   tests/configs/realview64-o3.py 97eebddaae84 
>   tests/configs/realview64-simple-timing-dual.py 97eebddaae84 
>   tests/configs/realview64-simple-timing.py 97eebddaae84 
>   tests/configs/realview64-switcheroo-full.py 97eebddaae84 
>   tests/configs/realview64-switcheroo-o3.py 97eebddaae84 
>   tests/configs/realview64-switcheroo-timing.py 97eebddaae84 
>   tests/configs/tgen-dram-ctrl.py 97eebddaae84 
>   tests/configs/tsunami-minor-dual.py 97eebddaae84 
>   tests/configs/tsunami-minor.py 97eebddaae84 
>   tests/configs/tsunami-o3-dual.py 97eebddaae84 
>   tests/configs/tsunami-o3.py 97eebddaae84 
>   tests/configs/tsunami-simple-timing-dual.py 97eebddaae84 
>   tests/configs/tsunami-simple-timing.py 97eebddaae84 
>   tests/configs/tsunami-switcheroo-full.py 97eebddaae84 
> 
> Diff: http://reviews.gem5.org/r/3783/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Curtis Dunham
> 
>

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[gem5-dev] changeset in gem5: config: Fix missing include in fs.py

[Matthias Jung]

changeset f1ffedcf3b98 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=f1ffedcf3b98
description:
config: Fix missing include in fs.py

Bugfix for Elastic Traces

This patch fixes the bug when elastic traces are used:


build/ARM/gem5.opt \
configs/example/fs.py \
--cpu-type=arm_detailed \
--num-cpu=1 \
--mem-type=SimpleMemory \
--mem-size=512MB \
--mem-channels=1 \
--caches \
--elastic-trace-en \
--data-trace-file=data.proto.gz \
--inst-trace-file=inst.proto.gz \
--machine-type=VExpress_EMM \
--dtb-filename=vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb \
--kernel=vmlinux.aarch32.ll_20131205.0-gem5 \
--disk-image=linux-aarch32-ael.img


NameError: global name 'CpuConfig' is not defined

Signed-off by: Jason Lowe-Power 

diffstat:

 configs/example/fs.py |  1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diffs (11 lines):

diff -r c10c50cb8ac9 -r f1ffedcf3b98 configs/example/fs.py
--- a/configs/example/fs.py Tue Jan 03 17:31:39 2017 +
+++ b/configs/example/fs.py Mon Jan 09 09:32:13 2017 -0600
@@ -59,6 +59,7 @@
 from common import Simulation
 from common import CacheConfig
 from common import MemConfig
+from common import CpuConfig
 from common.Caches import *
 from common import Options
 
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[gem5-dev] changeset in gem5: misc: fixes deprecated sc_time function for S...

[Matthias Jung]

changeset 494ab5474716 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=494ab5474716
description:
misc: fixes deprecated sc_time function for SystemC 2.3.1

The non-standard sc_time constructors

- sc_time( uint64, bool scale )
- sc_time( double, bool scale )

have been deprecated in SystemC 2.3.1 and a warning is issued when being
used. Insted the new 'sc_time::from_value' function is used to omit the
warning message.

Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>

diffstat:

 util/systemc/sc_module.cc |  5 +++--
 1 files changed, 3 insertions(+), 2 deletions(-)

diffs (22 lines):

diff -r ac5237fa4230 -r 494ab5474716 util/systemc/sc_module.cc
--- a/util/systemc/sc_module.cc Mon Jan 09 09:33:42 2017 -0600
+++ b/util/systemc/sc_module.cc Mon Jan 09 09:34:36 2017 -0600
@@ -42,6 +42,7 @@
  * Authors: Nathan Binkert
  *  Steve Reinhardt
  *  Andrew Bardsley
+ *  Matthias Jung
  */
 
 /**
@@ -221,8 +222,8 @@
 
 /* The next event is scheduled in the future, wait until
  *  then or until externalSchedulingEvent */
-eventLoopEnterEvent.notify(sc_core::sc_time(
-sc_dt::uint64(wait_period), 0));
+eventLoopEnterEvent.notify(sc_core::sc_time::from_value(
+sc_dt::uint64(wait_period)));
 
 return;
 } else if (gem5_time > next_event_time) {
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[gem5-dev] changeset in gem5: misc: Documentation Update

[Matthias Jung]

changeset ac5237fa4230 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=ac5237fa4230
description:
misc: Documentation Update

Updates for READMEs of /util/cxx_config, /util/systemc, /util/tlm.
Some minor corrections, mostly with respect to MAC/OSX

Signed-off-by: Jason Lowe-Power 

diffstat:

 util/cxx_config/README |   9 +
 util/systemc/README|  27 +--
 util/tlm/README|  18 +-
 3 files changed, 51 insertions(+), 3 deletions(-)

diffs (92 lines):

diff -r f1ffedcf3b98 -r ac5237fa4230 util/cxx_config/README
--- a/util/cxx_config/READMEMon Jan 09 09:32:13 2017 -0600
+++ b/util/cxx_config/READMEMon Jan 09 09:33:42 2017 -0600
@@ -19,6 +19,15 @@
 > scons --with-cxx-config --without-python build/ARM/libgem5_opt.so
 > cd util/cxx_config
 
+Note: For MAC / OSX this command should be used:
+> scons --with-cxx-config --without-python build/ARM/libgem5_opt.dylib
+
+Set a proper LD_LIBRARY_PATH e.g. for bash:
+> export LD_LIBRARY_PATH="$LD_LIBRARY_PATH:/path/to/gem5/build/ARM/"
+
+or for MAC / OSX:
+> export DYLD_LIBRARY_PATH="$DYLD_LIBRARY_PATH:/path/to/gem5/build/ARM/"
+
 Then edit Makefile to set the paths for PYTHON and run make
 
 > make
diff -r f1ffedcf3b98 -r ac5237fa4230 util/systemc/README
--- a/util/systemc/README   Mon Jan 09 09:32:13 2017 -0600
+++ b/util/systemc/README   Mon Jan 09 09:33:42 2017 -0600
@@ -32,9 +32,29 @@
 > cd ../..
 > scons build/ARM/gem5.opt
 > scons --with-cxx-config --without-python build/ARM/libgem5_opt.so
-> cd util/cxx_config
+> cd util/systemc
 
-Then edit Makefile to set the paths for SystemC and run make
+Note: For MAC / OSX this command should be used:
+> scons --with-cxx-config --without-python build/ARM/libgem5_opt.dylib
+
+Set a proper LD_LIBRARY_PATH e.g. for bash:
+> export LD_LIBRARY_PATH="$LD_LIBRARY_PATH:/path/to/gem5/build/ARM/"
+
+or for MAC / OSX:
+> export DYLD_LIBRARY_PATH="$DYLD_LIBRARY_PATH:/path/to/gem5/build/ARM/"
+
+
+Then edit the Makefile to set the paths for SystemC, e.g:
+
+Linux:
+SYSTEMC_INC = /opt/systemc/include
+SYSTEMC_LIB = /opt/systemc/lib-linux64
+
+MAC / OSX:
+SYSTEMC_INC = /opt/systemc/include
+SYSTEMC_LIB = /opt/systemc/lib-macosx64
+
+Then run make:
 
 > make
 
@@ -57,3 +77,6 @@
 The .ini file can also be read by the Python .ini file reader example:
 
 > ../../build/ARM/gem5.opt ../../configs/example/read_ini.py m5out/config.ini
+
+If you are interested in SystemC Transaction Level Modeling (TLM2) please have
+a look into /util/tlm.
diff -r f1ffedcf3b98 -r ac5237fa4230 util/tlm/README
--- a/util/tlm/README   Mon Jan 09 09:32:13 2017 -0600
+++ b/util/tlm/README   Mon Jan 09 09:33:42 2017 -0600
@@ -35,10 +35,26 @@
 > scons --with-cxx-config --without-python build/ARM/libgem5_opt.so
 > cd util/tlm
 
+Note: For MAC / OSX this command should be used:
+> scons --with-cxx-config --without-python build/ARM/libgem5_opt.dylib
+
 Set a proper LD_LIBRARY_PATH e.g. for bash:
 > export LD_LIBRARY_PATH="$LD_LIBRARY_PATH:/path/to/gem5/build/ARM/"
 
-Then edit the Makefile to set the paths for SystemC and run make
+or for MAC / OSX:
+> export DYLD_LIBRARY_PATH="$DYLD_LIBRARY_PATH:/path/to/gem5/build/ARM/"
+
+Then edit the Makefile to set the paths for SystemC:
+
+Linux:
+SYSTEMC_INC = /opt/systemc/include
+SYSTEMC_LIB = /opt/systemc/lib-linux64
+
+MAC / OSX:
+SYSTEMC_INC = /opt/systemc/include
+SYSTEMC_LIB = /opt/systemc/lib-macosx64
+
+Then run make:
 
 > make
 
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Re: [gem5-dev] Review Request 3762: config: Fix missing include in fs.py

[Matthias Jung]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3762/
---

(Updated Dez. 10, 2016, 10:33 vorm.)


Review request for Default.


Summary (updated)
-

config: Fix missing include in fs.py


Repository: gem5


Description
---

Bugfix for Elastic Traces

This patch fixes the bug when elastic traces are used:

```bash
build/ARM/gem5.opt \
configs/example/fs.py \
--cpu-type=arm_detailed \
--num-cpu=1 \
--mem-type=SimpleMemory \
--mem-size=512MB \
--mem-channels=1 \
--caches \
--elastic-trace-en \
--data-trace-file=data.proto.gz \
--inst-trace-file=inst.proto.gz \
--machine-type=VExpress_EMM \
--dtb-filename=vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb \
--kernel=vmlinux.aarch32.ll_20131205.0-gem5 \
--disk-image=linux-aarch32-ael.img
```

NameError: global name 'CpuConfig' is not defined


Diffs
-

  configs/example/fs.py 78ef8daecd81 

Diff: http://reviews.gem5.org/r/3762/diff/


Testing
---


Thanks,

Matthias Jung

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Re: [gem5-dev] Review Request 3762: Bugfix for Elastic Traces

[Matthias Jung]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3762/
---

(Updated Dec. 10, 2016, 10:31 a.m.)


Review request for Default.


Repository: gem5


Description
---

Bugfix for Elastic Traces

This patch fixes the bug when elastic traces are used:

```bash
build/ARM/gem5.opt \
configs/example/fs.py \
--cpu-type=arm_detailed \
--num-cpu=1 \
--mem-type=SimpleMemory \
--mem-size=512MB \
--mem-channels=1 \
--caches \
--elastic-trace-en \
--data-trace-file=data.proto.gz \
--inst-trace-file=inst.proto.gz \
--machine-type=VExpress_EMM \
--dtb-filename=vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb \
--kernel=vmlinux.aarch32.ll_20131205.0-gem5 \
--disk-image=linux-aarch32-ael.img
```

NameError: global name 'CpuConfig' is not defined


Diffs (updated)
-

  configs/example/fs.py 78ef8daecd81 

Diff: http://reviews.gem5.org/r/3762/diff/


Testing
---


Thanks,

Matthias Jung

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[gem5-dev] Review Request 3762: Bugfix for Elastic Traces

[Matthias Jung]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3762/
---

Review request for Default.


Repository: gem5


Description
---

Bugfix for Elastic Traces

This patch fixes the bug when elastic traces are used:

```bash
build/ARM/gem5.opt \
configs/example/fs.py \
--cpu-type=arm_detailed \
--num-cpu=1 \
--mem-type=SimpleMemory \
--mem-size=512MB \
--mem-channels=1 \
--caches \
--elastic-trace-en \
--data-trace-file=data.proto.gz \
--inst-trace-file=inst.proto.gz \
--machine-type=VExpress_EMM \
--dtb-filename=vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb \
--kernel=vmlinux.aarch32.ll_20131205.0-gem5 \
--disk-image=linux-aarch32-ael.img
```

NameError: global name 'CpuConfig' is not defined


Diffs
-

  configs/example/fs.py 057b388cce03 

Diff: http://reviews.gem5.org/r/3762/diff/


Testing
---


Thanks,

Matthias Jung

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Re: [gem5-dev] Review Request 3686: misc: use a simple_initiator_socket to implement the SystemC TLM Slave Port

[Matthias Jung]

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---

Ship it!


Ship It!

- Matthias Jung


On Okt. 28, 2016, 4:55 nachm., Christian Menard wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3686/
> ---
> 
> (Updated Okt. 28, 2016, 4:55 nachm.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 11691:9733d3adf993
> ---
> misc: use a simple_initiator_socket to implement the SystemC TLM Slave Port
> 
> 
> Diffs
> -
> 
>   util/tlm/sc_slave_port.hh PRE-CREATION 
>   util/tlm/sc_slave_port.cc PRE-CREATION 
> 
> Diff: http://reviews.gem5.org/r/3686/diff/
> 
> 
> Testing
> ---
> 
> Example applications are still running.
> 
> 
> Thanks,
> 
> Christian Menard
> 
>

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Re: [gem5-dev] Review Request 3527: misc: prepare the TLM sources for the addition of a TLM->Gem5 Master Port

[Matthias Jung]

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---



util/tlm/README (line 4)
<http://reviews.gem5.org/r/3527/#comment7758>

Both directions are implemented, Initiator (Master) and Target (Slave)



util/tlm/examples/slave_port/sc_target.cc (line 61)
<http://reviews.gem5.org/r/3527/#comment7759>

once the patch is accepted i will change this to something like this:

```c++
unsigned int size = 1024 * 1024 * 1024;
memory = (unsigned char *)mmap(NULL, size, PROT_READ | PROT_WRITE, 
MAP_PRIVATE | MAP_ANON | MAP_NORESERVE, -1, 0);
```


- Matthias Jung


On Okt. 28, 2016, 12:27 nachm., Christian Menard wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3527/
> ---
> 
> (Updated Okt. 28, 2016, 12:27 nachm.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> The current TLM code only provides a Slave Port that allows the gem5 world to 
> send requests to the the TLM world. This patch restructures the existing 
> source code in util/tlm in order to allow for code reuse and a clear file 
> structure whenn adding a master port implementation. It also replaces the 
> Makefile by a SConstruct.
> 
> 
> Diffs
> -
> 
>   util/tlm/tlm.py b3d5f0e9e258 
>   util/tlm/tlm_elastic.py b3d5f0e9e258 
>   util/tlm/sim_control.cc PRE-CREATION 
>   util/tlm/tgen.cfg b3d5f0e9e258 
>   util/tlm/sc_target.hh b3d5f0e9e258 
>   util/tlm/sc_target.cc b3d5f0e9e258 
>   util/tlm/sim_control.hh PRE-CREATION 
>   util/tlm/sc_mm.cc b3d5f0e9e258 
>   util/tlm/sc_port.hh b3d5f0e9e258 
>   util/tlm/sc_port.cc b3d5f0e9e258 
>   util/tlm/sc_slave_port.hh PRE-CREATION 
>   util/tlm/sc_slave_port.cc PRE-CREATION 
>   util/tlm/sc_ext.hh b3d5f0e9e258 
>   util/tlm/sc_ext.cc b3d5f0e9e258 
>   util/tlm/sc_mm.hh b3d5f0e9e258 
>   util/tlm/examples/slave_port/tlm_elastic.py PRE-CREATION 
>   util/tlm/main.cc b3d5f0e9e258 
>   util/tlm/run_gem5.sh b3d5f0e9e258 
>   util/tlm/examples/slave_port/run_gem5.sh PRE-CREATION 
>   util/tlm/examples/slave_port/sc_target.hh PRE-CREATION 
>   util/tlm/examples/slave_port/sc_target.cc PRE-CREATION 
>   util/tlm/examples/slave_port/tgen.cfg PRE-CREATION 
>   util/tlm/examples/slave_port/tlm.py PRE-CREATION 
>   configs/common/MemConfig.py b3d5f0e9e258 
>   util/tlm/Makefile b3d5f0e9e258 
>   util/tlm/README b3d5f0e9e258 
>   util/tlm/examples/slave_port/SConstruct PRE-CREATION 
>   util/tlm/examples/slave_port/main.cc PRE-CREATION 
> 
> Diff: http://reviews.gem5.org/r/3527/diff/
> 
> 
> Testing
> ---
> 
> The examples provided in util/tlm (now util/tlm/examples/slave_port) still 
> compile and run error free.
> 
> 
> Thanks,
> 
> Christian Menard
> 
>

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Re: [gem5-dev] Review Request 3528: misc: add a TLM to Gem5 Master Port

[Matthias Jung]

---
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---



util/tlm/examples/master_port/main.cc (line 54)
<http://reviews.gem5.org/r/3528/#comment7754>

This function is also in the target example, could we source out all 
doublicated functions to a common dir/file?



util/tlm/examples/master_port/main.cc (line 74)
<http://reviews.gem5.org/r/3528/#comment7757>

Similar to the Target (the example TLM memory): put this sc_module in a 
seperated file...



util/tlm/examples/master_port/tlm.py (line 62)
<http://reviews.gem5.org/r/3528/#comment7755>

remove it if you dont need it



util/tlm/sc_master_port.cc (line 99)
<http://reviews.gem5.org/r/3528/#comment7756>

    XXX flag?


- Matthias Jung


On Okt. 28, 2016, 4:42 nachm., Christian Menard wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3528/
> ---
> 
> (Updated Okt. 28, 2016, 4:42 nachm.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 11690:b9fc391b2477
> ---
> misc: add a TLM to Gem5 Master Port
> 
> The current TLM code only provides a Slave Port that allows the gem5 world to
> send requests to the the TLM world. This patch adds a Master Port that allows
> the TLM world to send requests to the gem5 world. Furthermore, the patch
> provides a simple example application based on a TLM traffic generator.
> 
> 
> Diffs
> -
> 
>   util/tlm/README b3d5f0e9e258 
>   util/tlm/examples/master_port/SConstruct PRE-CREATION 
>   util/tlm/examples/master_port/main.cc PRE-CREATION 
>   util/tlm/examples/master_port/tlm.py PRE-CREATION 
>   util/tlm/sc_master_port.hh PRE-CREATION 
>   util/tlm/sc_master_port.cc PRE-CREATION 
>   util/tlm/sim_control.cc PRE-CREATION 
> 
> Diff: http://reviews.gem5.org/r/3528/diff/
> 
> 
> Testing
> ---
> 
> A simple example application consisting of a TLM traffic generator and a gem5 
> memory is part of the patch.
> 
> 
> Thanks,
> 
> Christian Menard
> 
>

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Re: [gem5-dev] Review Request 3527: misc: prepare the TLM sources for the addition of a TLM->Gem5 Master Port

[Matthias Jung]

---
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---

Ship it!


Ship It!

- Matthias Jung


On Juli 13, 2016, 12:55 nachm., Christian Menard wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3527/
> ---
> 
> (Updated Juli 13, 2016, 12:55 nachm.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> The current TLM code only provides a Slave Port that allows the gem5 world to 
> send requests to the the TLM world. This patch restructures the existing 
> source code in util/tlm in order to allow for code reuse and a clear file 
> structure whenn adding a master port implementation.
> 
> 
> Diffs
> -
> 
>   util/tlm/tgen.cfg 704b0198f747b766b839c577614eb2924fd1dfee 
>   util/tlm/tlm.py 704b0198f747b766b839c577614eb2924fd1dfee 
>   util/tlm/tlm_elastic.py 704b0198f747b766b839c577614eb2924fd1dfee 
>   util/tlm/sc_port.hh 704b0198f747b766b839c577614eb2924fd1dfee 
>   util/tlm/sc_port.cc 704b0198f747b766b839c577614eb2924fd1dfee 
>   util/tlm/sc_target.hh 704b0198f747b766b839c577614eb2924fd1dfee 
>   util/tlm/sc_target.cc 704b0198f747b766b839c577614eb2924fd1dfee 
>   util/tlm/sim_control.hh PRE-CREATION 
>   configs/common/MemConfig.py 704b0198f747b766b839c577614eb2924fd1dfee 
>   util/tlm/Makefile 704b0198f747b766b839c577614eb2924fd1dfee 
>   util/tlm/README 704b0198f747b766b839c577614eb2924fd1dfee 
>   util/tlm/examples/slave_port/main.cc PRE-CREATION 
>   util/tlm/main.cc 704b0198f747b766b839c577614eb2924fd1dfee 
>   util/tlm/payload_event.hh PRE-CREATION 
>   util/tlm/run_gem5.sh 704b0198f747b766b839c577614eb2924fd1dfee 
> 
> Diff: http://reviews.gem5.org/r/3527/diff/
> 
> 
> Testing
> ---
> 
> The examples provided in util/tlm (now util/tlm/examples/slave_port) still 
> compile and run error free.
> 
> 
> Thanks,
> 
> Christian Menard
> 
>

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Re: [gem5-dev] Review Request 3663: config: Make configs/common a Python package

[Matthias Jung]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3663/#review8837
---

Ship it!


Ship It!

- Matthias Jung


On Okt. 13, 2016, 2:10 nachm., Andreas Hansson wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3663/
> ---
> 
> (Updated Okt. 13, 2016, 2:10 nachm.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 11671:6e5527f38e5b
> ---
> config: Make configs/common a Python package
> 
> Continue along the same line as the recent patch that made the
> Ruby-related config scripts Python packages and make also the
> configs/common directory a package.
> 
> All affected config scripts are updated (hopefully).
> 
> Note that this change makes it apparent that the current organisation
> and naming of the config directory and its subdirectories is rather
> chaotic. We mix scripts that are directly invoked with scripts that
> merely contain convenience functions. While it is not addressed in
> this patch we should follow up with a re-organisation of the
> config structure, and renaming of some of the packages.
> 
> 
> Diffs
> -
> 
>   configs/common/__init__.py 6ce719503eae 
>   configs/dist/sw.py 6ce719503eae 
>   configs/dram/lat_mem_rd.py 6ce719503eae 
>   configs/dram/sweep.py 6ce719503eae 
>   configs/example/apu_se.py 6ce719503eae 
>   configs/example/arm/devices.py 6ce719503eae 
>   configs/example/arm/fs_bigLITTLE.py 6ce719503eae 
>   configs/example/etrace_replay.py 6ce719503eae 
>   configs/example/fs.py 6ce719503eae 
>   configs/example/garnet_synth_traffic.py 6ce719503eae 
>   configs/example/hmctest.py 6ce719503eae 
>   configs/example/ruby_direct_test.py 6ce719503eae 
>   configs/example/ruby_gpu_random_test.py 6ce719503eae 
>   configs/example/ruby_mem_test.py 6ce719503eae 
>   configs/example/ruby_random_test.py 6ce719503eae 
>   configs/example/se.py 6ce719503eae 
>   configs/learning_gem5/part1/caches.py 6ce719503eae 
>   configs/learning_gem5/part1/two_level.py 6ce719503eae 
>   configs/ruby/Ruby.py 6ce719503eae 
>   configs/splash2/cluster.py 6ce719503eae 
>   configs/splash2/run.py 6ce719503eae 
>   tests/configs/alpha_generic.py 6ce719503eae 
>   tests/configs/arm_generic.py 6ce719503eae 
>   tests/configs/base_config.py 6ce719503eae 
>   tests/configs/checkpoint.py 6ce719503eae 
>   tests/configs/gpu-randomtest-ruby.py 6ce719503eae 
>   tests/configs/gpu-ruby.py 6ce719503eae 
>   tests/configs/learning-gem5-p1-two-level.py 6ce719503eae 
>   tests/configs/memtest-filter.py 6ce719503eae 
>   tests/configs/memtest-ruby.py 6ce719503eae 
>   tests/configs/memtest.py 6ce719503eae 
>   tests/configs/o3-timing-mp-ruby.py 6ce719503eae 
>   tests/configs/o3-timing-mt.py 6ce719503eae 
>   tests/configs/o3-timing-ruby.py 6ce719503eae 
>   tests/configs/o3-timing.py 6ce719503eae 
>   tests/configs/pc-simple-timing-ruby.py 6ce719503eae 
>   tests/configs/rubytest-ruby.py 6ce719503eae 
>   tests/configs/simple-timing-mp-ruby.py 6ce719503eae 
>   tests/configs/simple-timing-ruby.py 6ce719503eae 
>   tests/configs/switcheroo.py 6ce719503eae 
>   tests/configs/t1000-simple-atomic.py 6ce719503eae 
>   tests/configs/twosys-tsunami-simple-atomic.py 6ce719503eae 
>   tests/configs/x86_generic.py 6ce719503eae 
> 
> Diff: http://reviews.gem5.org/r/3663/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Andreas Hansson
> 
>

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Re: [gem5-dev] Review Request 3596: mem: make DDR4 x16

[Matthias Jung]

> On Aug. 12, 2016, 2:35 nachm., Matthias Jung wrote:
> > Technically everything seams right. However, I think the x8 configuration 
> > could also be interesting as an default option. E.g. when people want to 
> > see the effect on their application when having more **banks** (16). I 
> > suggest to keep both configuration: one as _device_x16_ and another one 
> > _device_x8_.
> 
> Wendy Elsasser wrote:
> Hi Matthias,
> I agree that the x8 (and x4) configurations are more interesting.  Now 
> that we have public datasheets for all device widths, we have an internal 
> patch that we will upload shortly that contains updated configurations to 
> address your concern.
> Will this suffice?
> 
> Thanks,
> Wendy

I think its okay when the patch comes soon.


- Matthias


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---


On Aug. 11, 2016, 9:07 vorm., Curtis Dunham wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3596/
> ---
> 
> (Updated Aug. 11, 2016, 9:07 vorm.)
> 
> 
> Review request for Default and Matthias Jung.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> mem: make DDR4 x16
> 
> 
> Diffs
> -
> 
>   src/mem/DRAMCtrl.py e9096175eb38ac39f37c91bfdf2a450b9664e222 
> 
> Diff: http://reviews.gem5.org/r/3596/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Curtis Dunham
> 
>

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Re: [gem5-dev] Review Request 3596: mem: make DDR4 x16

[Matthias Jung]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3596/#review8814
---

Ship it!


Ship It!

- Matthias Jung


On Aug. 11, 2016, 9:07 vorm., Curtis Dunham wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3596/
> ---
> 
> (Updated Aug. 11, 2016, 9:07 vorm.)
> 
> 
> Review request for Default and Matthias Jung.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> mem: make DDR4 x16
> 
> 
> Diffs
> -
> 
>   src/mem/DRAMCtrl.py e9096175eb38ac39f37c91bfdf2a450b9664e222 
> 
> Diff: http://reviews.gem5.org/r/3596/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Curtis Dunham
> 
>

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Re: [gem5-dev] Review Request 3602: mem: Add DRAM low-power functionality

[Matthias Jung]

---
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http://reviews.gem5.org/r/3602/#review8749
---


Again my comment, maybe refer to the mentioned paper, since other DRAM 
controllers usually use timeouts for the transition to the low power modes. But 
the benefits of this "staggered" approach are explained in the mentioned paper. 
So people can follow why its done like this ...

- Matthias Jung


On Aug. 11, 2016, 9:08 vorm., Curtis Dunham wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3602/
> ---
> 
> (Updated Aug. 11, 2016, 9:08 vorm.)
> 
> 
> Review request for Default and Matthias Jung.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> mem: Add DRAM low-power functionality
> 
> Added power-down state transitions to the DRAM controller model.
> 
> Added per rank parameter, outstandingEvents, which tracks the number
> of outstanding command events and is used to determine when the
> controller should transition to a low power state.
> The controller will only transition when there are no outstanding events
> scheduled and the number of command entries for the given rank is 0.
> 
> The outstandingEvents parameter is incremented for every RD/WR burst,
> PRE, and REF event scheduled.  ACT is implicitly covered by RD/WR
> since burst will always issue and complete after a required ACT.
> The parameter is decremented when the event is serviced (completed).
> 
> The controller will automatically transition to ACT power down,
> PRE power down, or SREF.
> 
> Transition to ACT power down state scheduled from:
> 1) The RespondEvent, where read data is received from the memory.
>ACT power-down entry will be scheduled when one or more banks is
>open, all commands for the rank have completed (no more commands
>scheduled), and there are no commands in queue for the rank
> 
> Transition to PRE power down scheduled from:
> 1) respondEvent, when all banks are closed, all commands have
>completed, and there are no commands in queue for the rank
> 2) prechargeEvent when all banks are closed, all commands have
>completed, and there are no commands in queue for the rank
> 3) refreshEvent, after the refresh is complete when the previous
>state was ACT power-down
> 4) refreshEvent, after the refresh is complete when the previous
>state was PRE power-down and there are commands in the queue.
> 
> Transistion to SREF will be scheduled from:
> 1) refreshEvent, after the refresh is completes when the previous
>state was PRE power-down with no commands in queue
> 
> Power-down exit commands are scheduled from:
> 1) The refreshEvent, prior to issuing a refresh
> 2) doDRAMAccess, to wake-up the rank for RD/WR command issue.
> 
> Self-refresh exit commands are scheduled from:
> 1) The next request event, when the queue has commands for the rank
>in the readQueue or there are commands for the rank in the
>writeQueue and the bus state is WRITE.
> 
> Change-Id: I6103f660776e36c686655e71d92ec7b5b752050a
> Reviewed-by: Radhika Jagtap <radhika.jag...@arm.com>
> 
> 
> Diffs
> -
> 
>   src/mem/dram_ctrl.hh e9096175eb38ac39f37c91bfdf2a450b9664e222 
>   src/mem/dram_ctrl.cc e9096175eb38ac39f37c91bfdf2a450b9664e222 
> 
> Diff: http://reviews.gem5.org/r/3602/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Curtis Dunham
> 
>

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Re: [gem5-dev] Review Request 3599: mem: Sort memory commands and update DRAMPower

[Matthias Jung]

---
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http://reviews.gem5.org/r/3599/#review8714
---

Ship it!


Ship It!

- Matthias Jung


On Aug. 11, 2016, 9:07 vorm., Curtis Dunham wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3599/
> ---
> 
> (Updated Aug. 11, 2016, 9:07 vorm.)
> 
> 
> Review request for Default and Matthias Jung.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> mem: Sort memory commands and update DRAMPower
> 
> Add local variable to stores commands to be issued.
> These commands are in order within a single bank but will be out
> of order across banks & ranks.
> 
> A new procedure, flushCmdList, sorts commands across banks / ranks,
> and flushes the sorted list, up to curTick() to DRAMPower.
> This is currently called in refresh, once all previous commands are
> guaranteed to have completed.  Could be called in other events like
> the powerEvent as well.
> 
> By only flushing commands up to curTick(), will not get out of sync
> when flushed at a periodic stats dump (done in subsequent patch).
> 
> Change-Id: I4ac65a52407f64270db1e16a1fb04cfe7f638851
> Reviewed-by: Radhika Jagtap <radhika.jag...@arm.com>
> 
> 
> Diffs
> -
> 
>   src/mem/dram_ctrl.hh e9096175eb38ac39f37c91bfdf2a450b9664e222 
>   src/mem/dram_ctrl.cc e9096175eb38ac39f37c91bfdf2a450b9664e222 
> 
> Diff: http://reviews.gem5.org/r/3599/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Curtis Dunham
> 
>

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Re: [gem5-dev] Review Request 3600: mem: Modify drain to ensure banks and power are idled

[Matthias Jung]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3600/#review8707
---

Ship it!


Ship It!

- Matthias Jung


On Aug. 11, 2016, 9:08 vorm., Curtis Dunham wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3600/
> ---
> 
> (Updated Aug. 11, 2016, 9:08 vorm.)
> 
> 
> Review request for Default and Matthias Jung.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> mem: Modify drain to ensure banks and power are idled
> 
> Add constraint that all ranks have to be in PWR_IDLE
> before signaling drain complete
> 
> This will ensure that the banks are all closed and the rank
> has exited any low-power states.
> 
> On suspend, update the power stats to sync the DRAM power logic
> 
> The logic maintains the location of the signalDrainDone
> method, which is still triggered from either:
> 1) Read response event
> 2) Next request event
> 
> This ensures that the drain will complete in the READ bus
> state and minimizes the changes required.
> 
> Change-Id: If1476e631ea7d5999fe50a0c9379c5967a90e3d1
> Reviewed-by: Radhika Jagtap <radhika.jag...@arm.com>
> 
> 
> Diffs
> -
> 
>   src/mem/dram_ctrl.cc e9096175eb38ac39f37c91bfdf2a450b9664e222 
>   src/mem/dram_ctrl.hh e9096175eb38ac39f37c91bfdf2a450b9664e222 
> 
> Diff: http://reviews.gem5.org/r/3600/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Curtis Dunham
> 
>

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Re: [gem5-dev] Review Request 3597: mem: add DRAM powerdown timing

[Matthias Jung]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3597/#review8607
---

Ship it!


This patch adds power down related DRAM timing parameters. It is straight 
forward and can be included immediatly.

- Matthias Jung


On Aug. 11, 2016, 9:07 vorm., Curtis Dunham wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3597/
> ---
> 
> (Updated Aug. 11, 2016, 9:07 vorm.)
> 
> 
> Review request for Default and Matthias Jung.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> mem: add DRAM powerdown timing
> 
> 
> Diffs
> -
> 
>   src/mem/DRAMCtrl.py e9096175eb38ac39f37c91bfdf2a450b9664e222 
>   src/mem/dram_ctrl.hh e9096175eb38ac39f37c91bfdf2a450b9664e222 
>   src/mem/dram_ctrl.cc e9096175eb38ac39f37c91bfdf2a450b9664e222 
> 
> Diff: http://reviews.gem5.org/r/3597/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Curtis Dunham
> 
>

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Re: [gem5-dev] Review Request 3603: mem: add DRAM powerdown current

[Matthias Jung]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3603/#review8612
---

Ship it!


This patch adds current values to the DRAM configuration which are needed for 
DRAM Power-Down Simulations with DRAM Power. Everything is straight forward and 
can be added directly.

- Matthias Jung


On Aug. 11, 2016, 9:08 vorm., Curtis Dunham wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3603/
> ---
> 
> (Updated Aug. 11, 2016, 9:08 vorm.)
> 
> 
> Review request for Default and Matthias Jung.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> mem: add DRAM powerdown current
> 
> Change-Id: I763cffe0c69f5ebbbf6a6eb12bec5c13d5d0161d
> Reviewed-by: Andreas Hansson <andreas.hans...@arm.com>
> Reviewed-by: Radhika Jagtap <radhika.jag...@arm.com>
> 
> 
> Diffs
> -
> 
>   src/mem/DRAMCtrl.py e9096175eb38ac39f37c91bfdf2a450b9664e222 
> 
> Diff: http://reviews.gem5.org/r/3603/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Curtis Dunham
> 
>

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Re: [gem5-dev] Review Request 3602: mem: Add DRAM low-power functionality

[Matthias Jung]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3602/#review8611
---


I will do a detailed review and testing in the next days.

What this patch does is basically the "Staggered Powerdown" concept that we 
presented 2014 at VLSISOC. Similar to line 86 can you refer to this mentioned 
paper:

- Optimized Active and Power-Down Mode Refresh Control in 3D-DRAMs, M. Jung, M. 
Sadri, C. Weis, N. Wehn, L. Benini. IFIP/IEEE International Conference on Very 
Large Scale Integration (VLSI-SoC), October, 2014, Playa del Carmen, Mexico.

This will help interested people to understand why we use the refresh event for 
self-refresh entry and not a timeout based approach.

- Matthias Jung


On Aug. 11, 2016, 9:08 vorm., Curtis Dunham wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3602/
> ---
> 
> (Updated Aug. 11, 2016, 9:08 vorm.)
> 
> 
> Review request for Default and Matthias Jung.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> mem: Add DRAM low-power functionality
> 
> Added power-down state transitions to the DRAM controller model.
> 
> Added per rank parameter, outstandingEvents, which tracks the number
> of outstanding command events and is used to determine when the
> controller should transition to a low power state.
> The controller will only transition when there are no outstanding events
> scheduled and the number of command entries for the given rank is 0.
> 
> The outstandingEvents parameter is incremented for every RD/WR burst,
> PRE, and REF event scheduled.  ACT is implicitly covered by RD/WR
> since burst will always issue and complete after a required ACT.
> The parameter is decremented when the event is serviced (completed).
> 
> The controller will automatically transition to ACT power down,
> PRE power down, or SREF.
> 
> Transition to ACT power down state scheduled from:
> 1) The RespondEvent, where read data is received from the memory.
>ACT power-down entry will be scheduled when one or more banks is
>open, all commands for the rank have completed (no more commands
>scheduled), and there are no commands in queue for the rank
> 
> Transition to PRE power down scheduled from:
> 1) respondEvent, when all banks are closed, all commands have
>completed, and there are no commands in queue for the rank
> 2) prechargeEvent when all banks are closed, all commands have
>completed, and there are no commands in queue for the rank
> 3) refreshEvent, after the refresh is complete when the previous
>state was ACT power-down
> 4) refreshEvent, after the refresh is complete when the previous
>state was PRE power-down and there are commands in the queue.
> 
> Transistion to SREF will be scheduled from:
> 1) refreshEvent, after the refresh is completes when the previous
>state was PRE power-down with no commands in queue
> 
> Power-down exit commands are scheduled from:
> 1) The refreshEvent, prior to issuing a refresh
> 2) doDRAMAccess, to wake-up the rank for RD/WR command issue.
> 
> Self-refresh exit commands are scheduled from:
> 1) The next request event, when the queue has commands for the rank
>in the readQueue or there are commands for the rank in the
>writeQueue and the bus state is WRITE.
> 
> Change-Id: I6103f660776e36c686655e71d92ec7b5b752050a
> Reviewed-by: Radhika Jagtap <radhika.jag...@arm.com>
> 
> 
> Diffs
> -
> 
>   src/mem/dram_ctrl.hh e9096175eb38ac39f37c91bfdf2a450b9664e222 
>   src/mem/dram_ctrl.cc e9096175eb38ac39f37c91bfdf2a450b9664e222 
> 
> Diff: http://reviews.gem5.org/r/3602/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Curtis Dunham
> 
>

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Re: [gem5-dev] Review Request 3598: mem: update DDR3 die revision

[Matthias Jung]

---
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---

Ship it!


This patch uses newer numbers from a recent datasheet. These numbers will lead 
to a more optimistic result in terms of DRAMPower!

- Matthias Jung


On Aug. 11, 2016, 9:07 vorm., Curtis Dunham wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3598/
> ---
> 
> (Updated Aug. 11, 2016, 9:07 vorm.)
> 
> 
> Review request for Default and Matthias Jung.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> mem: update DDR3 die revision
> 
> Change-Id: I8992ddc1664c3ed4b2d36d8a34e4ce8be113b9de
> Reviewed-by: Radhika Jagtap <radhika.jag...@arm.com>
> 
> 
> Diffs
> -
> 
>   src/mem/DRAMCtrl.py e9096175eb38ac39f37c91bfdf2a450b9664e222 
> 
> Diff: http://reviews.gem5.org/r/3598/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Curtis Dunham
> 
>

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Re: [gem5-dev] Review Request 3596: mem: make DDR4 x16

[Matthias Jung]

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---


Technically everything seams right. However, I think the x8 configuration could 
also be interesting as an default option. E.g. when people want to see the 
effect on their application when having more **banks** (16). I suggest to keep 
both configuration: one as _device_x16_ and another one _device_x8_.

- Matthias Jung


On Aug. 11, 2016, 9:07 vorm., Curtis Dunham wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3596/
> ---
> 
> (Updated Aug. 11, 2016, 9:07 vorm.)
> 
> 
> Review request for Default and Matthias Jung.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> mem: make DDR4 x16
> 
> 
> Diffs
> -
> 
>   src/mem/DRAMCtrl.py e9096175eb38ac39f37c91bfdf2a450b9664e222 
> 
> Diff: http://reviews.gem5.org/r/3596/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Curtis Dunham
> 
>

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Re: [gem5-dev] Review Request 3528: misc: add a TLM to Gem5 Master Port implementation

[Matthias Jung]

> On Juni 23, 2016, 7:09 nachm., Matthias Jung wrote:
> > Dear Christian,
> > 
> > thank you for this nice contribution. I will have a look on your patch and 
> > maybe I can help you fixing your issue.
> > 
> > Regards
> > Matthias
> 
> Andreas Hansson wrote:
> Christian, Matthias, is there any sensible way we could actually get some 
> of this functionality tested? Including SystemC in ext seems problematic due 
> to the non-BSD compatible license, but perhaps we should do something like we 
> do with protobuf, and check if the host HAS_SYSTEMC or similar, and if so 
> compile the extra bits, and run the extra tests etc.
> 
> This is tremendously useful functionality, and it feels like it is bolted 
> on rather than properly integrated at the moment (not because of the 
> functionality, but due to the non-default use). Any thoughts or suggestions?
> 
> Matthias Jung wrote:
> What about an automated shell script that downloads SystemC from 
> http://accellera.org/images/downloads/standards/systemc/systemc-2.3.1.tgz and 
> compiles it? Its maybe a little complicated but makes things easy for people 
> that don't have SystemC by default. Usually people install SystemC in 
> /opt/systemc so thats a place that could be checked for existance. 
> Christian? what do you think?
> 
> Andreas Hansson wrote:
> I don't like the idea of the download, and would rather suggest we should 
> rely on pkg-config. Supposedly SystemC 2.3.1 actually does support pkg-config 
> properly, with package names SystemC, TLM and TLM2. Could someone confirm? If 
> that is the case, we could use the same flow as for protobuf for the 
> determination of HAVE_SYSTEMC.
> 
> The next step would be to build in support if SystemC is present and look 
> in more detail at how we deal with "with python" and building of the gem5 
> lib. Perhaps we want to revisit this flow and not mandate going via the lib 
> for SystemC (and rather just use a different main.cc)?

```bash
find .  -iname *.pc
/opt/systemc/lib-macosx64/pkgconfig/systemc.pc
/opt/systemc/lib-macosx64/pkgconfig/tlm.pc
```

seems that pkg-config is used.


- Matthias


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---


On Juni 24, 2016, 10:20 vorm., Christian Menard wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3528/
> ---
> 
> (Updated Juni 24, 2016, 10:20 vorm.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> The current TLM code only provides a Slave Port that allows the gem5 world to 
> send requests to the the TLM world. This patch adds a Master Port that allows 
> the TLM world to send requests to the gem5 world. Furthermore, the patch 
> provides a simple example application based on a TLM traffic generator.
> 
> As of now the example code does not run error free. It eventually results in 
> an erro "fatal: Missed an event at time ...". So for now I leave the patch 
> for discussion until the error is resolved.
> 
> 
> Diffs
> -
> 
>   util/tlm/README dd6dfd38b6c2 
>   util/tlm/examples/master_port/Makefile PRE-CREATION 
>   util/tlm/examples/master_port/main.cc PRE-CREATION 
>   util/tlm/examples/master_port/tlm.py PRE-CREATION 
>   util/tlm/examples/slave_port/Makefile PRE-CREATION 
>   util/tlm/sc_master_port.hh PRE-CREATION 
>   util/tlm/sc_master_port.cc PRE-CREATION 
>   util/tlm/sim_control.cc PRE-CREATION 
> 
> Diff: http://reviews.gem5.org/r/3528/diff/
> 
> 
> Testing
> ---
> 
> A simple example application consisting of a TLM traffic generator and a gem5 
> memory. Currently the test fails.
> 
> 
> Thanks,
> 
> Christian Menard
> 
>

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Re: [gem5-dev] Review Request 3528: misc: add a TLM to Gem5 Master Port implementation

[Matthias Jung]

> On Juni 23, 2016, 7:09 nachm., Matthias Jung wrote:
> > Dear Christian,
> > 
> > thank you for this nice contribution. I will have a look on your patch and 
> > maybe I can help you fixing your issue.
> > 
> > Regards
> > Matthias
> 
> Andreas Hansson wrote:
> Christian, Matthias, is there any sensible way we could actually get some 
> of this functionality tested? Including SystemC in ext seems problematic due 
> to the non-BSD compatible license, but perhaps we should do something like we 
> do with protobuf, and check if the host HAS_SYSTEMC or similar, and if so 
> compile the extra bits, and run the extra tests etc.
> 
> This is tremendously useful functionality, and it feels like it is bolted 
> on rather than properly integrated at the moment (not because of the 
> functionality, but due to the non-default use). Any thoughts or suggestions?

What about an automated shell script that downloads SystemC from 
http://accellera.org/images/downloads/standards/systemc/systemc-2.3.1.tgz and 
compiles it? Its maybe a little complicated but makes things easy for people 
that don't have SystemC by default. Usually people install SystemC in 
/opt/systemc so thats a place that could be checked for existance. 
Christian? what do you think?


- Matthias


---
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---


On Juni 24, 2016, 10:20 vorm., Christian Menard wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3528/
> ---
> 
> (Updated Juni 24, 2016, 10:20 vorm.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> The current TLM code only provides a Slave Port that allows the gem5 world to 
> send requests to the the TLM world. This patch adds a Master Port that allows 
> the TLM world to send requests to the gem5 world. Furthermore, the patch 
> provides a simple example application based on a TLM traffic generator.
> 
> As of now the example code does not run error free. It eventually results in 
> an erro "fatal: Missed an event at time ...". So for now I leave the patch 
> for discussion until the error is resolved.
> 
> 
> Diffs
> -
> 
>   util/tlm/README dd6dfd38b6c2 
>   util/tlm/examples/master_port/Makefile PRE-CREATION 
>   util/tlm/examples/master_port/main.cc PRE-CREATION 
>   util/tlm/examples/master_port/tlm.py PRE-CREATION 
>   util/tlm/examples/slave_port/Makefile PRE-CREATION 
>   util/tlm/sc_master_port.hh PRE-CREATION 
>   util/tlm/sc_master_port.cc PRE-CREATION 
>   util/tlm/sim_control.cc PRE-CREATION 
> 
> Diff: http://reviews.gem5.org/r/3528/diff/
> 
> 
> Testing
> ---
> 
> A simple example application consisting of a TLM traffic generator and a gem5 
> memory. Currently the test fails.
> 
> 
> Thanks,
> 
> Christian Menard
> 
>

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[gem5-dev] changeset in gem5: ext: Update DRAMPower

[Matthias Jung]

changeset 2efa95cf8504 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=2efa95cf8504
description:
ext: Update DRAMPower

Sync DRAMPower to external tool

This patch syncs the DRAMPower library of gem5 to the external
one on github (https://github.com/ravenrd/DRAMPower) of which
I am a maintainer.

The version used is the commit:
902a00a1797c48a9df97ec88868f20e847680ae6
from 07.  May.  2016.

Committed by Jason Lowe-Power <ja...@lowepower.com>

diffstat:

 ext/drampower/README.md |4 +-
 ext/drampower/src/CmdScheduler.cc   |  212 +++---
 ext/drampower/src/CmdScheduler.h|   80 ++--
 ext/drampower/src/CommandAnalysis.cc|  294 
 ext/drampower/src/CommandAnalysis.h |   29 +-
 ext/drampower/src/MemArchitectureSpec.h |   20 +-
 ext/drampower/src/MemCommand.cc |   43 +-
 ext/drampower/src/MemCommand.h  |   42 ++-
 ext/drampower/src/MemTimingSpec.h   |   62 ++--
 ext/drampower/src/MemoryPowerModel.cc   |  331 ++-
 ext/drampower/src/MemoryPowerModel.h|   12 +-
 ext/drampower/src/MemorySpecification.h |   11 +-
 ext/drampower/src/TraceParser.cc|   21 +-
 ext/drampower/src/TraceParser.h |1 +
 ext/drampower/src/Utils.h   |4 +-
 ext/drampower/src/libdrampower/LibDRAMPower.cc  |9 +-
 ext/drampower/src/libdrampower/LibDRAMPower.h   |2 +
 ext/drampower/test/libdrampowertest/lib_test.cc |5 +-
 src/mem/dram_ctrl.hh|3 +-
 19 files changed, 560 insertions(+), 625 deletions(-)

diffs (truncated from 2229 to 300 lines):

diff -r adafd259839e -r 2efa95cf8504 ext/drampower/README.md
--- a/ext/drampower/README.md   Fri Jul 01 10:31:33 2016 -0500
+++ b/ext/drampower/README.md   Fri Jul 01 10:31:36 2016 -0500
@@ -252,8 +252,8 @@
 
 **To cite the DRAMPower Tool:**
 ```
-[1] "DRAMPower: Open-source DRAM power & energy estimation tool"
-Karthik Chandrasekar, Christian Weis, Yonghui Li, Benny Akesson, Norbert Wehn, 
and Kees Goossens
+[1] DRAMPower: Open-source DRAM Power & Energy Estimation Tool
+Karthik Chandrasekar, Christian Weis, Yonghui Li, Sven Goossens, Matthias 
Jung, Omar Naji, Benny Akesson, Norbert Wehn, and Kees Goossens
 URL: http://www.drampower.info
 ```
 
diff -r adafd259839e -r 2efa95cf8504 ext/drampower/src/CmdScheduler.cc
--- a/ext/drampower/src/CmdScheduler.cc Fri Jul 01 10:31:33 2016 -0500
+++ b/ext/drampower/src/CmdScheduler.cc Fri Jul 01 10:31:36 2016 -0500
@@ -31,7 +31,7 @@
  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
- * Authors: Karthik Chandrasekar
+ * Authors: Karthik Chandrasekar, Yonghui Li, Sven Goossens
  *
  */
 #include "CmdScheduler.h"
@@ -42,17 +42,20 @@
 #include   // For max
 
 
+#define MILLION 100
+
+
 using namespace std;
 using namespace Data;
 
 // Read the traces and get the transaction. Each transaction is executed by
 // scheduling a number of commands to the memory. Hence, the transactions are
 // translated into a sequence of commands which will be used for power 
analysis.
-void cmdScheduler::transTranslation(MemorySpecification memSpec,
+void cmdScheduler::transTranslation(const MemorySpecification& memSpec,
 ifstream& trans_trace, int grouping, int 
interleaving, int burst, int powerdown)
 {
   commands.open("commands.trace", ifstream::out);
-  MemArchitectureSpec& memArchSpec = memSpec.memArchSpec;
+  const MemArchitectureSpec& memArchSpec = memSpec.memArchSpec;
   nBanks  = memArchSpec.nbrOfBanks;
   nColumns= memArchSpec.nbrOfColumns;
   burstLength = memArchSpec.burstLength;
@@ -77,13 +80,14 @@
 } // cmdScheduler::transTranslation
 
 // initialize the variables and vectors for starting command scheduling.
-void cmdScheduler::schedulingInitialization(MemorySpecification memSpec)
+void cmdScheduler::schedulingInitialization(const MemorySpecification& memSpec)
 {
-  MemTimingSpec& memTimingSpec = memSpec.memTimingSpec;
+  const MemTimingSpec& memTimingSpec = memSpec.memTimingSpec;
 
-  ACT.resize(2 * memSpec.memArchSpec.nbrOfBanks);
-  RDWR.resize(2 * memSpec.memArchSpec.nbrOfBanks);
-  PRE.resize(memSpec.memArchSpec.nbrOfBanks);
+  const size_t numBanks = static_cast(memSpec.memArchSpec.nbrOfBanks);
+  ACT.resize(2 * numBanks);
+  RDWR.resize(2 * numBanks);
+  PRE.resize(numBanks);
   bankaccess = memSpec.memArchSpec.nbrOfBanks;
   if (!ACT.empty()) {
 ACT.erase(ACT.begin(), ACT.end());
@@ -96,14 +100,15 @@
   }
 
   ///initialization//
-  for (unsigned i = 0; i < memSpec.memArchSpec.nbrOfBanks; i++) {
+  for (int64_t i = 0; i < m

[gem5-dev] changeset in gem5: misc: SystemC Elastic Trace Player Example.

[Matthias Jung]

changeset adafd259839e in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=adafd259839e
description:
misc: SystemC Elastic Trace Player Example.

This patch adds an example configuration for elastic trace playing into 
the
SystemC world, similar to the already existing traffic generator 
example in
/util/tlm.

Committed by Jason Lowe-Power <ja...@lowepower.com>

diffstat:

 util/tlm/README |   23 
 util/tlm/tlm_elastic.py |  123 
 2 files changed, 146 insertions(+), 0 deletions(-)

diffs (157 lines):

diff -r 602835f8dc9d -r adafd259839e util/tlm/README
--- a/util/tlm/README   Fri Jul 01 09:50:18 2016 -0500
+++ b/util/tlm/README   Fri Jul 01 10:31:33 2016 -0500
@@ -94,3 +94,26 @@
 The system should boot now.
 
 For conveniance a run_gem5.sh file holds all those commands
+
+
+III. Elastic Trace Setup
+
+
+Elastic traces can also be replayed into the SystemC world.
+For more information on elastic traces please refer to:
+
+ - http://www.gem5.org/TraceCPU
+
+ - Exploring System Performance using Elastic Traces:
+   Fast, Accurate and Portable
+   R. Jagtap, S. Diestelhorst, A. Hansson, M. Jung, N. Wehn.
+   IEEE International Conference on Embedded Computer Systems Architectures
+   Modeling and Simulation (SAMOS), July, 2016, Samos Island, Greece.
+
+Similar to I. the simulation can be set up with this command:
+
+> ../../build/ARM/gem5.opt ./tlm_elastic.py
+
+Then:
+
+> ./gem5.opt.sc m5out/config.ini
diff -r 602835f8dc9d -r adafd259839e util/tlm/tlm_elastic.py
--- /dev/null   Thu Jan 01 00:00:00 1970 +
+++ b/util/tlm/tlm_elastic.py   Fri Jul 01 10:31:33 2016 -0500
@@ -0,0 +1,123 @@
+# Copyright (c) 2016, University of Kaiserslautern
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+#
+# 1. Redistributions of source code must retain the above copyright notice,
+#this list of conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright
+#notice, this list of conditions and the following disclaimer in the
+#documentation and/or other materials provided with the distribution.
+#
+# 3. Neither the name of the copyright holder nor the names of its
+#contributors may be used to endorse or promote products derived from
+#this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Matthias Jung
+
+import m5
+import optparse
+
+from m5.objects import *
+from m5.util import addToPath, fatal
+
+addToPath('../../configs/common/')
+
+from Caches import *
+
+# This configuration shows a simple setup of a Elastic Trace Player (eTraceCPU)
+# and an external TLM port for SystemC co-simulation.
+#
+# We assume a DRAM size of 512MB and L1 cache sizes of 32KB.
+#
+# Base System Architecture:
+#
+#  +---+   ^
+# +-+  | eTraceCPU |   |
+# | System Port |  +-+-+   |
+# +--+--+  | $D1 | $I1 |   |
+#| +--+--+--+--+   |
+#|| |  | gem5 World
+#|| |  | (see this file)
+#|| |  |
+# +--vv-v--+   |
+# |   Membus   |   v
+# ++---+   External Port (see sc_port.*)
+#  |   ^
+#  +---v---+   | TLM World
+#  |  TLM  |   | (see sc_target.*)
+#  +---+   v
+#
+#
+# Create a system with a Crossbar and an Elastic Trace Player as CPU:
+
+# Setup System:
+system = System(cpu=TraceCPU(cpu_id=0),
+mem_mode='timing',
+mem_ranges = [AddrRange('512MB')],
+cache_line_size = 64)
+
+# Create a top-level voltage domain:
+system.voltage_domain = VoltageDomain()
+
+# Create a source clock for the system. This is used as the clock period for
+# xbar and memory:
+system.clk_domain = SrcCloc

Re: [gem5-dev] Review Request 3525: ext: Update DRAMPower

[Matthias Jung]

> On Juni 26, 2016, 9:59 nachm., Andreas Hansson wrote:
> > I realise I am commenting on DRAMPower changes here, so feel free to ignore.
> > 
> > There seems to be an awful lot of changes from unsigned to signed types, 
> > which feels rather unintuitive. Why not uint64_t if the value is truly 
> > unsigned? It seems odd to remove that clear communication of intent.
> > 
> > There also seems to be quite a few static_cast cause by the above 
> > change, which clutters the code. If the bank, for example, is unsigned this 
> > should not be needed.
> 
> Matthias Jung wrote:
> there where some discussions about that issue in DRAMPowers git repro:
> 
> https://github.com/ravenrd/DRAMPower/issues/10#issuecomment-207067743
> 
> Andreas Hansson wrote:
> I am not against updating, but some of these style issues would be good 
> to get resolved as even clang and gcc complain.

I discussed that internally with Sven, Benny and Éder that we will include 
these suggestions in the release of DRAMPower v4.1.
Since we have other pending tasks for this release, it will take some more 
time, which would keep this patch ideling on the review board.
I would suggest that this patch is pushed to gem5 now in order to include the 
latest improved version of DRAMPower and we will come up with v4.1. as fast as 
possible.


- Matthias


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---


On Juni 22, 2016, 7:52 nachm., Matthias Jung wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3525/
> ---
> 
> (Updated Juni 22, 2016, 7:52 nachm.)
> 
> 
> Review request for Default and Andreas Sandberg.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Sync DRAMPower to external tool
> 
> This patch syncs the DRAMPower library of gem5 to the external
> one on github (https://github.com/ravenrd/DRAMPower) of which
> I am a maintainer.
> 
> The version used is the commit:
> 902a00a1797c48a9df97ec88868f20e847680ae6
> from 07.  May.  2016.
> 
> 
> Diffs
> -
> 
>   ext/drampower/README.md dd6dfd38b6c2 
>   ext/drampower/src/CmdScheduler.h dd6dfd38b6c2 
>   ext/drampower/src/CmdScheduler.cc dd6dfd38b6c2 
>   ext/drampower/src/CommandAnalysis.h dd6dfd38b6c2 
>   ext/drampower/src/CommandAnalysis.cc dd6dfd38b6c2 
>   ext/drampower/src/MemArchitectureSpec.h dd6dfd38b6c2 
>   ext/drampower/src/MemCommand.h dd6dfd38b6c2 
>   ext/drampower/src/MemCommand.cc dd6dfd38b6c2 
>   ext/drampower/src/MemTimingSpec.h dd6dfd38b6c2 
>   ext/drampower/src/MemoryPowerModel.h dd6dfd38b6c2 
>   ext/drampower/src/MemoryPowerModel.cc dd6dfd38b6c2 
>   ext/drampower/src/MemorySpecification.h dd6dfd38b6c2 
>   ext/drampower/src/TraceParser.h dd6dfd38b6c2 
>   ext/drampower/src/TraceParser.cc dd6dfd38b6c2 
>   ext/drampower/src/Utils.h dd6dfd38b6c2 
>   ext/drampower/src/libdrampower/LibDRAMPower.h dd6dfd38b6c2 
>   ext/drampower/src/libdrampower/LibDRAMPower.cc dd6dfd38b6c2 
>   ext/drampower/test/libdrampowertest/lib_test.cc dd6dfd38b6c2 
>   src/mem/dram_ctrl.hh dd6dfd38b6c2 
> 
> Diff: http://reviews.gem5.org/r/3525/diff/
> 
> 
> Testing
> ---
> 
> Everything compiles.
> 
> 
> Thanks,
> 
> Matthias Jung
> 
>

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Re: [gem5-dev] Review Request 3525: ext: Update DRAMPower

[Matthias Jung]

> On Juni 26, 2016, 9:59 nachm., Andreas Hansson wrote:
> > I realise I am commenting on DRAMPower changes here, so feel free to ignore.
> > 
> > There seems to be an awful lot of changes from unsigned to signed types, 
> > which feels rather unintuitive. Why not uint64_t if the value is truly 
> > unsigned? It seems odd to remove that clear communication of intent.
> > 
> > There also seems to be quite a few static_cast cause by the above 
> > change, which clutters the code. If the bank, for example, is unsigned this 
> > should not be needed.

there where some discussions about that issue in DRAMPowers git repro:

https://github.com/ravenrd/DRAMPower/issues/10#issuecomment-207067743


- Matthias


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On Juni 22, 2016, 7:52 nachm., Matthias Jung wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3525/
> ---
> 
> (Updated Juni 22, 2016, 7:52 nachm.)
> 
> 
> Review request for Default and Andreas Sandberg.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Sync DRAMPower to external tool
> 
> This patch syncs the DRAMPower library of gem5 to the external
> one on github (https://github.com/ravenrd/DRAMPower) of which
> I am a maintainer.
> 
> The version used is the commit:
> 902a00a1797c48a9df97ec88868f20e847680ae6
> from 07.  May.  2016.
> 
> 
> Diffs
> -
> 
>   ext/drampower/README.md dd6dfd38b6c2 
>   ext/drampower/src/CmdScheduler.h dd6dfd38b6c2 
>   ext/drampower/src/CmdScheduler.cc dd6dfd38b6c2 
>   ext/drampower/src/CommandAnalysis.h dd6dfd38b6c2 
>   ext/drampower/src/CommandAnalysis.cc dd6dfd38b6c2 
>   ext/drampower/src/MemArchitectureSpec.h dd6dfd38b6c2 
>   ext/drampower/src/MemCommand.h dd6dfd38b6c2 
>   ext/drampower/src/MemCommand.cc dd6dfd38b6c2 
>   ext/drampower/src/MemTimingSpec.h dd6dfd38b6c2 
>   ext/drampower/src/MemoryPowerModel.h dd6dfd38b6c2 
>   ext/drampower/src/MemoryPowerModel.cc dd6dfd38b6c2 
>   ext/drampower/src/MemorySpecification.h dd6dfd38b6c2 
>   ext/drampower/src/TraceParser.h dd6dfd38b6c2 
>   ext/drampower/src/TraceParser.cc dd6dfd38b6c2 
>   ext/drampower/src/Utils.h dd6dfd38b6c2 
>   ext/drampower/src/libdrampower/LibDRAMPower.h dd6dfd38b6c2 
>   ext/drampower/src/libdrampower/LibDRAMPower.cc dd6dfd38b6c2 
>   ext/drampower/test/libdrampowertest/lib_test.cc dd6dfd38b6c2 
>   src/mem/dram_ctrl.hh dd6dfd38b6c2 
> 
> Diff: http://reviews.gem5.org/r/3525/diff/
> 
> 
> Testing
> ---
> 
> Everything compiles.
> 
> 
> Thanks,
> 
> Matthias Jung
> 
>

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Re: [gem5-dev] Review Request 3527: misc: prepare the TLM sources for the addition of a TLM->Gem5 Master Port

[Matthias Jung]

---
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---


please build your patch on top of this: http://reviews.gem5.org/r/3477/
I hope that this patch will be comitted to gem5 soon since it got already a lot 
of ship its.

So we will avoid merge problems ;)

- Matthias Jung


On Juni 23, 2016, 3:32 nachm., Christian Menard wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3527/
> ---
> 
> (Updated Juni 23, 2016, 3:32 nachm.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> The current TLM code only provides a Slave Port that allows the gem5 world to 
> send requests to the the TLM world. This patch restructures the existing 
> source code in util/tlm in order to allow for code reuse and a clear file 
> structure whenn adding a master port implementation.
> 
> 
> Diffs
> -
> 
>   configs/common/MemConfig.py dd6dfd38b6c2 
>   util/tlm/Makefile dd6dfd38b6c2 
>   util/tlm/README dd6dfd38b6c2 
>   util/tlm/examples/slave_port/Makefile PRE-CREATION 
>   util/tlm/examples/slave_port/main.cc PRE-CREATION 
>   util/tlm/examples/slave_port/run_gem5.sh PRE-CREATION 
>   util/tlm/examples/slave_port/sc_target.hh PRE-CREATION 
>   util/tlm/examples/slave_port/sc_target.cc PRE-CREATION 
>   util/tlm/examples/slave_port/tgen.cfg PRE-CREATION 
>   util/tlm/examples/slave_port/tlm.py PRE-CREATION 
>   util/tlm/main.cc dd6dfd38b6c2 
>   util/tlm/payload_event.hh PRE-CREATION 
>   util/tlm/run_gem5.sh dd6dfd38b6c2 
>   util/tlm/sc_port.hh dd6dfd38b6c2 
>   util/tlm/sc_port.cc dd6dfd38b6c2 
>   util/tlm/sc_slave_port.hh PRE-CREATION 
>   util/tlm/sc_slave_port.cc PRE-CREATION 
>   util/tlm/sc_target.hh dd6dfd38b6c2 
>   util/tlm/sc_target.cc dd6dfd38b6c2 
>   util/tlm/sim_control.hh PRE-CREATION 
>   util/tlm/sim_control.cc PRE-CREATION 
>   util/tlm/tgen.cfg dd6dfd38b6c2 
>   util/tlm/tlm.py dd6dfd38b6c2 
> 
> Diff: http://reviews.gem5.org/r/3527/diff/
> 
> 
> Testing
> ---
> 
> The examples provided in util/tlm (now util/tlm/examples/slave_port) still 
> compile and run error free.
> 
> 
> Thanks,
> 
> Christian Menard
> 
>

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Re: [gem5-dev] Review Request 3528: misc: add a TLM to Gem5 Master Port implementation

[Matthias Jung]

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---


Dear Christian,

thank you for this nice contribution. I will have a look on your patch and 
maybe I can help you fixing your issue.

Regards
Matthias

- Matthias Jung


On Juni 23, 2016, 3:32 nachm., Christian Menard wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3528/
> ---
> 
> (Updated Juni 23, 2016, 3:32 nachm.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> The current TLM code only provides a Slave Port that allows the gem5 world to 
> send requests to the the TLM world. This patch adds a Master Port that allows 
> the TLM world to send requests to the gem5 world. Furthermore, the patch 
> provides a simple example application based on a TLM traffic generator.
> 
> As of now the example code does not run error free. It eventually results in 
> an erro "fatal: Missed an event at time ...". So for now I leave the patch 
> for discussion until the error is resolved.
> 
> 
> Diffs
> -
> 
>   util/tlm/README dd6dfd38b6c2 
>   util/tlm/examples/master_port/Makefile PRE-CREATION 
>   util/tlm/examples/master_port/main.cc PRE-CREATION 
>   util/tlm/examples/master_port/tlm.py PRE-CREATION 
>   util/tlm/examples/slave_port/Makefile PRE-CREATION 
>   util/tlm/sc_master_port.hh PRE-CREATION 
>   util/tlm/sc_master_port.cc PRE-CREATION 
>   util/tlm/sim_control.cc PRE-CREATION 
> 
> Diff: http://reviews.gem5.org/r/3528/diff/
> 
> 
> Testing
> ---
> 
> A simple example application consisting of a TLM traffic generator and a gem5 
> memory. Currently the test fails.
> 
> 
> Thanks,
> 
> Christian Menard
> 
>

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Re: [gem5-dev] Review Request 3525: ext: Update DRAMPower

[Matthias Jung]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3525/
---

(Updated Juni 22, 2016, 7:52 nachm.)


Review request for Default and Andreas Sandberg.


Changes
---

Description Changed


Repository: gem5


Description (updated)
---

Sync DRAMPower to external tool

This patch syncs the DRAMPower library of gem5 to the external
one on github (https://github.com/ravenrd/DRAMPower) of which
I am a maintainer.

The version used is the commit:
902a00a1797c48a9df97ec88868f20e847680ae6
from 07.  May.  2016.


Diffs
-

  ext/drampower/README.md dd6dfd38b6c2 
  ext/drampower/src/CmdScheduler.h dd6dfd38b6c2 
  ext/drampower/src/CmdScheduler.cc dd6dfd38b6c2 
  ext/drampower/src/CommandAnalysis.h dd6dfd38b6c2 
  ext/drampower/src/CommandAnalysis.cc dd6dfd38b6c2 
  ext/drampower/src/MemArchitectureSpec.h dd6dfd38b6c2 
  ext/drampower/src/MemCommand.h dd6dfd38b6c2 
  ext/drampower/src/MemCommand.cc dd6dfd38b6c2 
  ext/drampower/src/MemTimingSpec.h dd6dfd38b6c2 
  ext/drampower/src/MemoryPowerModel.h dd6dfd38b6c2 
  ext/drampower/src/MemoryPowerModel.cc dd6dfd38b6c2 
  ext/drampower/src/MemorySpecification.h dd6dfd38b6c2 
  ext/drampower/src/TraceParser.h dd6dfd38b6c2 
  ext/drampower/src/TraceParser.cc dd6dfd38b6c2 
  ext/drampower/src/Utils.h dd6dfd38b6c2 
  ext/drampower/src/libdrampower/LibDRAMPower.h dd6dfd38b6c2 
  ext/drampower/src/libdrampower/LibDRAMPower.cc dd6dfd38b6c2 
  ext/drampower/test/libdrampowertest/lib_test.cc dd6dfd38b6c2 
  src/mem/dram_ctrl.hh dd6dfd38b6c2 

Diff: http://reviews.gem5.org/r/3525/diff/


Testing
---

Everything compiles.


Thanks,

Matthias Jung

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Re: [gem5-dev] Review Request 3525: ext: Update DRAMPower

[Matthias Jung]

---
This is an automatically generated e-mail. To reply, visit:
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---

(Updated Juni 22, 2016, 7:47 nachm.)


Review request for Default and Andreas Sandberg.


Changes
---

Summary Changed


Summary (updated)
-

ext: Update DRAMPower


Repository: gem5


Description
---

This patch syncs the DRAMPower library of gem5 to the external one on github 
(https://github.com/ravenrd/DRAMPower) of which I am a maintainer.
The version used is commit 902a00a1797c48a9df97ec88868f20e847680ae6 from 07. 
May. 2016.


Diffs
-

  ext/drampower/README.md dd6dfd38b6c2 
  ext/drampower/src/CmdScheduler.h dd6dfd38b6c2 
  ext/drampower/src/CmdScheduler.cc dd6dfd38b6c2 
  ext/drampower/src/CommandAnalysis.h dd6dfd38b6c2 
  ext/drampower/src/CommandAnalysis.cc dd6dfd38b6c2 
  ext/drampower/src/MemArchitectureSpec.h dd6dfd38b6c2 
  ext/drampower/src/MemCommand.h dd6dfd38b6c2 
  ext/drampower/src/MemCommand.cc dd6dfd38b6c2 
  ext/drampower/src/MemTimingSpec.h dd6dfd38b6c2 
  ext/drampower/src/MemoryPowerModel.h dd6dfd38b6c2 
  ext/drampower/src/MemoryPowerModel.cc dd6dfd38b6c2 
  ext/drampower/src/MemorySpecification.h dd6dfd38b6c2 
  ext/drampower/src/TraceParser.h dd6dfd38b6c2 
  ext/drampower/src/TraceParser.cc dd6dfd38b6c2 
  ext/drampower/src/Utils.h dd6dfd38b6c2 
  ext/drampower/src/libdrampower/LibDRAMPower.h dd6dfd38b6c2 
  ext/drampower/src/libdrampower/LibDRAMPower.cc dd6dfd38b6c2 
  ext/drampower/test/libdrampowertest/lib_test.cc dd6dfd38b6c2 
  src/mem/dram_ctrl.hh dd6dfd38b6c2 

Diff: http://reviews.gem5.org/r/3525/diff/


Testing
---

Everything compiles.


Thanks,

Matthias Jung

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[gem5-dev] Review Request 3525: mem: Update DRAMPower

[Matthias Jung]

---
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---

Review request for Default and Andreas Sandberg.


Repository: gem5


Description
---

This patch syncs the DRAMPower library of gem5 to the external one on github 
(https://github.com/ravenrd/DRAMPower) of which I am a maintainer.
The version used is commit 902a00a1797c48a9df97ec88868f20e847680ae6 from 07. 
May. 2016.


Diffs
-

  ext/drampower/README.md dd6dfd38b6c2 
  ext/drampower/src/CmdScheduler.h dd6dfd38b6c2 
  ext/drampower/src/CmdScheduler.cc dd6dfd38b6c2 
  ext/drampower/src/CommandAnalysis.h dd6dfd38b6c2 
  ext/drampower/src/CommandAnalysis.cc dd6dfd38b6c2 
  ext/drampower/src/MemArchitectureSpec.h dd6dfd38b6c2 
  ext/drampower/src/MemCommand.h dd6dfd38b6c2 
  ext/drampower/src/MemCommand.cc dd6dfd38b6c2 
  ext/drampower/src/MemTimingSpec.h dd6dfd38b6c2 
  ext/drampower/src/MemoryPowerModel.h dd6dfd38b6c2 
  ext/drampower/src/MemoryPowerModel.cc dd6dfd38b6c2 
  ext/drampower/src/MemorySpecification.h dd6dfd38b6c2 
  ext/drampower/src/TraceParser.h dd6dfd38b6c2 
  ext/drampower/src/TraceParser.cc dd6dfd38b6c2 
  ext/drampower/src/Utils.h dd6dfd38b6c2 
  ext/drampower/src/libdrampower/LibDRAMPower.h dd6dfd38b6c2 
  ext/drampower/src/libdrampower/LibDRAMPower.cc dd6dfd38b6c2 
  ext/drampower/test/libdrampowertest/lib_test.cc dd6dfd38b6c2 
  src/mem/dram_ctrl.hh dd6dfd38b6c2 

Diff: http://reviews.gem5.org/r/3525/diff/


Testing
---

Everything compiles.


Thanks,

Matthias Jung

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Re: [gem5-dev] Review Request 3477: misc: SystemC Elastic Trace Player Example

[Matthias Jung]

---
This is an automatically generated e-mail. To reply, visit:
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---

(Updated Juni 22, 2016, 2:34 nachm.)


Review request for Default and Andreas Sandberg.


Changes
---

last thing fixed ...


Repository: gem5


Description
---

This patch adds an example configuration for elastic trace playing into the
SystemC world, similar to the already existing traffic generator example in
/util/tlm.


Diffs (updated)
-

  util/tlm/README 43d1cc5f3078 
  util/tlm/tlm_elastic.py PRE-CREATION 

Diff: http://reviews.gem5.org/r/3477/diff/


Testing
---


Thanks,

Matthias Jung

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Re: [gem5-dev] Review Request 3477: misc: SystemC Elastic Trace Player Example

[Matthias Jung]

---
This is an automatically generated e-mail. To reply, visit:
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---

(Updated Juni 22, 2016, 2:28 nachm.)


Review request for Default and Andreas Sandberg.


Changes
---

Readme updated.


Repository: gem5


Description
---

This patch adds an example configuration for elastic trace playing into the
SystemC world, similar to the already existing traffic generator example in
/util/tlm.


Diffs (updated)
-

  util/tlm/README 051205720574 
  util/tlm/tlm_elastic.py PRE-CREATION 

Diff: http://reviews.gem5.org/r/3477/diff/


Testing
---


Thanks,

Matthias Jung

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Re: [gem5-dev] Review Request 3477: misc: SystemC Elastic Trace Player Example

[Matthias Jung]

> On Juni 15, 2016, 2:23 nachm., Andreas Sandberg wrote:
> > util/tlm/tlm_elastic.py, line 126
> > <http://reviews.gem5.org/r/3477/diff/2/?file=55598#file55598line126>
> >
> > This shouldn't be needed since you're not in FS mode (and you're 
> > simulating a trace CPU).
> 
> Matthias Jung wrote:
> Actually cpu.createInterruptController() is needed it wont work else :/

fatal condition interrupts.size() != numThreads occurred: CPU system.cpu has 0 
interrupt controllers, but is expecting one per thread (1)


- Matthias


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---


On Juni 14, 2016, 9:06 nachm., Matthias Jung wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3477/
> ---
> 
> (Updated Juni 14, 2016, 9:06 nachm.)
> 
> 
> Review request for Default and Andreas Sandberg.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> This patch adds an example configuration for elastic trace playing into the
> SystemC world, similar to the already existing traffic generator example in
> /util/tlm.
> 
> 
> Diffs
> -
> 
>   util/tlm/README fc247b9c42b6 
>   util/tlm/tlm_elastic.py PRE-CREATION 
> 
> Diff: http://reviews.gem5.org/r/3477/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Matthias Jung
> 
>

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[gem5-dev] Review Request 3524: misc: Compilation error with clang on macOS

[Matthias Jung]

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---

Review request for Default.


Repository: gem5


Description
---

A compilation error occurs when compiling with clan on macOS:

``` scons

[ CXX] ARM/sim/power/mathexpr_powermodel.cc -> .o
In file included from build/ARM/sim/mathexpr.cc:40:
build/ARM/sim/mathexpr.hh:87:36: error: implicit instantiation of undefined 
template 'std::__1::array<MathExpr::OpSearch, 6>'
std::array<OpSearch, uNeg + 1> ops;
   ^
/Applications/Xcode.app/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/bin/../include/c++/v1/__tuple:116:65:
 note: template is declared here
template  struct _LIBCPP_TYPE_VIS_ONLY array;
^
 [SWIG] ARM/python/m5/internal/AbstractMemory_vector.i -> _wrap.cc, .py
 [SWIG] ARM/python/m5/internal/AbstractNVM_vector.i -> _wrap.cc, .py
 
```
 
this is due to missing includes in mathexpr.hh


Diffs
-

  src/sim/mathexpr.hh 80e79ae636ca 

Diff: http://reviews.gem5.org/r/3524/diff/


Testing
---


Thanks,

Matthias Jung

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Re: [gem5-dev] Review Request 3477: misc: SystemC Elastic Trace Player Example

[Matthias Jung]

> On Juni 15, 2016, 2:23 nachm., Andreas Sandberg wrote:
> > Thanks for your patch!
> > 
> > I think this config script is independant enough that you should consider 
> > not using the Options helper in configs/common. I would argue that it just 
> > creates confusion due to the large number of unused options. I would 
> > suggest that you make it as independent as possible of the functionality in 
> > config/common/ and make it completely stand alone instead. However, don't 
> > consider these comments to be blockers for submission, they are just 
> > nice-to-have improvements.
> 
> Jason Lowe-Power wrote:
> I agree with this, Andreas! What Andreas said is a much clearer way to 
> get to the point I was making in my review.
> 
> I would really like to see this change. Although I won't block it either, 
> it seems like it shouldn't take long to update. I hope you choose to, 
> Matthias.

Thank you for the suggestions, of course I will address them and update the 
patch! We should get this into gem5 before the SAMOS conference (mid of july) 
where we will present the new elastic trace player approach and the systemc 
player.

Thanks again and regards
Matthias


> On Juni 15, 2016, 2:23 nachm., Andreas Sandberg wrote:
> > util/tlm/tlm_elastic.py, line 126
> > <http://reviews.gem5.org/r/3477/diff/2/?file=55598#file55598line126>
> >
> > This shouldn't be needed since you're not in FS mode (and you're 
> > simulating a trace CPU).

Actually cpu.createInterruptController() is needed it wont work else :/


- Matthias


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On Juni 14, 2016, 9:06 nachm., Matthias Jung wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3477/
> ---
> 
> (Updated Juni 14, 2016, 9:06 nachm.)
> 
> 
> Review request for Default and Andreas Sandberg.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> This patch adds an example configuration for elastic trace playing into the
> SystemC world, similar to the already existing traffic generator example in
> /util/tlm.
> 
> 
> Diffs
> -
> 
>   util/tlm/README fc247b9c42b6 
>   util/tlm/tlm_elastic.py PRE-CREATION 
> 
> Diff: http://reviews.gem5.org/r/3477/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Matthias Jung
> 
>

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Re: [gem5-dev] Review Request 3473: misc: fix a compile error due to incompability with SystemC 2.3.1

[Matthias Jung]

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Ship it!


Ship It!

- Matthias Jung


On Juni 6, 2016, 9:58 vorm., Christian Menard wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3473/
> ---
> 
> (Updated Juni 6, 2016, 9:58 vorm.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> This patch fixes an ambigous call compile error
> 
> 
> Diffs
> -
> 
>   util/systemc/main.cc 4ad81380c5e82fbfd6f58a01450672c38f7a0a9e 
> 
> Diff: http://reviews.gem5.org/r/3473/diff/
> 
> 
> Testing
> ---
> 
> The SystemC example compiles and runs
> 
> 
> Thanks,
> 
> Christian Menard
> 
>

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Re: [gem5-dev] Review Request 3132: misc: Separate stats file is generated for SystemC-gem5 co-simulation

[Matthias Jung]

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Ship it!


Ship It!

- Matthias Jung


On Mai 30, 2016, 9:37 vorm., Abdul Mutaal Ahmad wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3132/
> ---
> 
> (Updated Mai 30, 2016, 9:37 vorm.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> In previous versions of systemC-gem5 coupling statistics were not updated for 
> the systemc-gem5 simulation. systemC-gem5 simulation only need the previously 
> built config.ini file and normal gem5 simulation has to be run once to 
> generate config.ini file. Thus stats.txt inside the m5out folder is redundant 
> for systemC-gem5 simulation. A new stats file is now generated with the all 
> the statistics for systemC-gem5 simulation. This will also resolve the stats 
> issue in tlm-sysmtemC simulation.
> 
> 
> Diffs
> -
> 
>   util/systemc/main.cc UNKNOWN 
>   util/systemc/stats.hh UNKNOWN 
>   util/systemc/stats.cc UNKNOWN 
>   util/tlm/main.cc UNKNOWN 
> 
> Diff: http://reviews.gem5.org/r/3132/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Abdul Mutaal Ahmad
> 
>

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Re: [gem5-dev] Review Request 3480: ExternalMaster: add a masterId so that external ports can generate packages

[Matthias Jung]

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---

Ship it!


Ship It!

- Matthias Jung


On Mai 26, 2016, 11:38 vorm., Christian Menard wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3480/
> ---
> 
> (Updated Mai 26, 2016, 11:38 vorm.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> The Request constructor requires a MasterID. However, an external transactor 
> has no chance of getting a MasterID as it does not have a pointer to the 
> System. This patch adds a MasterID to ExternalMaster in order to allow 
> external modules to genrerate Packets.
> 
> 
> Diffs
> -
> 
>   src/mem/external_master.hh 54cf9a388a9d 
>   src/mem/external_master.cc 54cf9a388a9d 
>   src/mem/ExternalMaster.py 54cf9a388a9d 
> 
> Diff: http://reviews.gem5.org/r/3480/diff/
> 
> 
> Testing
> ---
> 
> Used in a SystemC transactor
> 
> 
> Thanks,
> 
> Christian Menard
> 
>

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Re: [gem5-dev] Review Request 3480: ExternalMaster: add a masterId so that external ports can generate packages

[Matthias Jung]

> On Mai 28, 2016, 7:21 nachm., Matthias Jung wrote:
> > Are the examples in /util/tlm and /util/systemc still working with this 
> > change?
> 
> Andreas Hansson wrote:
> What is the SystemC license? Should we consider including all/parts in 
> ext/ so that we can always build (and test) this support?

Hi Andreas,
SystemC has its own licence, called SystemC Open Source Licence. I don't know 
if this fits to gem5's BSD licence ...

http://accellera.org/images/about/policies/SystemC_Open_Source_License_v3.3.pdf

Regards
Matthias


- Matthias


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On Mai 26, 2016, 11:38 vorm., Christian Menard wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3480/
> ---
> 
> (Updated Mai 26, 2016, 11:38 vorm.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> The Request constructor requires a MasterID. However, an external transactor 
> has no chance of getting a MasterID as it does not have a pointer to the 
> System. This patch adds a MasterID to ExternalMaster in order to allow 
> external modules to genrerate Packets.
> 
> 
> Diffs
> -
> 
>   src/mem/external_master.hh 54cf9a388a9d 
>   src/mem/external_master.cc 54cf9a388a9d 
>   src/mem/ExternalMaster.py 54cf9a388a9d 
> 
> Diff: http://reviews.gem5.org/r/3480/diff/
> 
> 
> Testing
> ---
> 
> Used in a SystemC transactor
> 
> 
> Thanks,
> 
> Christian Menard
> 
>

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Re: [gem5-dev] Review Request 3478: misc: Documentation Update

[Matthias Jung]

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---

(Updated Mai 28, 2016, 7:37 nachm.)


Review request for Default.


Summary (updated)
-

misc: Documentation Update


Repository: gem5


Description (updated)
---

Some minor corrections in the READMEs of /util/cxx_config, /util/systemc, 
/util/tlm, mostly with respect to MAC/OSX.


Diffs
-

  util/cxx_config/README fc247b9c42b6 
  util/systemc/README fc247b9c42b6 
  util/tlm/README fc247b9c42b6 

Diff: http://reviews.gem5.org/r/3478/diff/


Testing
---


Thanks,

Matthias Jung

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Re: [gem5-dev] Review Request 3478: misc: Updates for READMEs of /util/cxx_config, /util/systemc, /util/tlm

[Matthias Jung]

> On Mai 26, 2016, 2:35 nachm., Jason Lowe-Power wrote:
> > I always appreciate documentation patches! If you ever get bored, it would 
> > be greatly appreciated if you put some of this information on the gem5 
> > wiki. As it is now, it's hard to know where to look for this documentation.

my plan is to write an technical report or a short paper on all this SystemC 
stuff, then I will add this text to the wiki, too ;)


- Matthias


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On Mai 25, 2016, 10:32 nachm., Matthias Jung wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3478/
> ---
> 
> (Updated Mai 25, 2016, 10:32 nachm.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Some minor corrections, mostly with respect to MAC/OSX
> 
> 
> Diffs
> -
> 
>   util/cxx_config/README fc247b9c42b6 
>   util/systemc/README fc247b9c42b6 
>   util/tlm/README fc247b9c42b6 
> 
> Diff: http://reviews.gem5.org/r/3478/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Matthias Jung
> 
>

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Re: [gem5-dev] Review Request 3473: systemc example: Fixed an ambiguous call error and a typo in the README

[Matthias Jung]

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util/systemc/main.cc (line 292)
<http://reviews.gem5.org/r/3473/#comment7257>

I think this is not the right approach for System 2.3.1.

It should be implemented like this:
wait(sc_core::sc_time::from_value(wait_period));

- Line 135 checks that gem5 and SystemC have the same time unit.
- Please mark changes to SystemC code as _misc_


- Matthias Jung


On Mai 26, 2016, 10:13 vorm., Christian Menard wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3473/
> ---
> 
> (Updated Mai 26, 2016, 10:13 vorm.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> gcc 6.1.1 complained about the call to sc_time being ambiguous
> 
> 
> Diffs
> -
> 
>   util/systemc/README 54cf9a388a9d 
>   util/systemc/main.cc 54cf9a388a9d 
> 
> Diff: http://reviews.gem5.org/r/3473/diff/
> 
> 
> Testing
> ---
> 
> The example compiles and runs
> 
> 
> Thanks,
> 
> Christian Menard
> 
>

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Re: [gem5-dev] Review Request 3480: ExternalMaster: add a masterId so that external ports can generate packages

[Matthias Jung]

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---


Are the examples in /util/tlm and /util/systemc still working with this change?

- Matthias Jung


On Mai 26, 2016, 11:38 vorm., Christian Menard wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3480/
> ---
> 
> (Updated Mai 26, 2016, 11:38 vorm.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> The Request constructor requires a MasterID. However, an external transactor 
> has no chance of getting a MasterID as it does not have a pointer to the 
> System. This patch adds a MasterID to ExternalMaster in order to allow 
> external modules to genrerate Packets.
> 
> 
> Diffs
> -
> 
>   src/mem/external_master.hh 54cf9a388a9d 
>   src/mem/external_master.cc 54cf9a388a9d 
>   src/mem/ExternalMaster.py 54cf9a388a9d 
> 
> Diff: http://reviews.gem5.org/r/3480/diff/
> 
> 
> Testing
> ---
> 
> Used in a SystemC transactor
> 
> 
> Thanks,
> 
> Christian Menard
> 
>

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Re: [gem5-dev] Review Request 3477: misc: SystemC Elastic Trace Player Example

[Matthias Jung]

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http://reviews.gem5.org/r/3477/
---

(Updated Mai 28, 2016, 7:18 nachm.)


Review request for Default.


Changes
---

Dear Radhika and Jason,
Thank you very much for your comments and suggestions. I resolved all issues!

Finally, I decided to include the caches, since it is only one line of code and 
the system can be directly used as an entry point for simulations with e.g. 
DRAMSys.

Regards
Matthias


Repository: gem5


Description
---

This patch adds an example configuration for elastic trace playing into the
SystemC world, similar to the already existing traffic generator example in
/util/tlm.


Diffs (updated)
-

  util/tlm/README fc247b9c42b6 
  util/tlm/tlm_elastic.py PRE-CREATION 

Diff: http://reviews.gem5.org/r/3477/diff/


Testing
---


Thanks,

Matthias Jung

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[gem5-dev] Review Request 3479: misc: fixes deprecated sc_time function for SystemC 2.3.1

[Matthias Jung]

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Review request for Default.


Repository: gem5


Description
---

The non-standard sc_time constructors

- sc_time( uint64, bool scale )
- sc_time( double, bool scale )

have been deprecated in SystemC 2.3.1 and a warning is issued when being used.
Insted the new 'sc_time::from_value' function is used to omit the warning 
message.


Diffs
-

  util/systemc/sc_module.cc fc247b9c42b6 

Diff: http://reviews.gem5.org/r/3479/diff/


Testing
---


Thanks,

Matthias Jung

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[gem5-dev] Review Request 3478: misc: Updates for READMEs of /util/cxx_config, /util/systemc, /util/tlm

[Matthias Jung]

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Review request for Default.


Repository: gem5


Description
---

Some minor corrections, mostly with respect to MAC/OSX


Diffs
-

  util/cxx_config/README fc247b9c42b6 
  util/systemc/README fc247b9c42b6 
  util/tlm/README fc247b9c42b6 

Diff: http://reviews.gem5.org/r/3478/diff/


Testing
---


Thanks,

Matthias Jung

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Re: [gem5-dev] Review Request 3473: systemc example: Fixed an ambiguous call error and a typo in the README

[Matthias Jung]

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please fix the patch ...

- Matthias Jung


On Mai 19, 2016, 9:49 vorm., Christian Menard wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3473/
> ---
> 
> (Updated Mai 19, 2016, 9:49 vorm.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> gcc 6.1.1 complained about the call to sc_time being ambiguous
> 
> 
> Diffs
> -
> 
>   util/systemc/README a886e02 
>   util/systemc/main.cc 75a7785 
> 
> Diff: http://reviews.gem5.org/r/3473/diff/
> 
> 
> Testing
> ---
> 
> The example compiles and runs
> 
> 
> Thanks,
> 
> Christian Menard
> 
>

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