[gem5-dev] [L] Change in gem5/gem5[develop]: stdlib: make cache size optional in classic

Tom Rollet has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/68798?usp=email ) Change subject: stdlib: make cache size optional in classic .. stdlib: make cache size optional in

[gem5-dev] [M] Change in gem5/gem5[develop]: stdlib: remove useless cache init function

Tom Rollet has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/68797?usp=email ) Change subject: stdlib: remove useless cache init function .. stdlib: remove useless cache init

[gem5-dev] [M] Change in gem5/gem5[develop]: stdlib: add custom import of cache models

Tom Rollet has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/68799?usp=email ) Change subject: stdlib: add custom import of cache models .. stdlib: add custom import of cache models

[gem5-dev] [S] Change in gem5/gem5[develop]: cpu-o3: fix false positive in AddressSanitizer

Tom Rollet has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/68357?usp=email ) Change subject: cpu-o3: fix false positive in AddressSanitizer .. cpu-o3: fix false positive in AddressSanitizer

[gem5-dev] [S] Change in gem5/gem5[develop]: cpu-o3: fix false positive in AddressSanitizer

Tom Rollet has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/68357?usp=email ) Change subject: cpu-o3: fix false positive in AddressSanitizer .. cpu-o3: fix false positive in

[gem5-dev] [S] Change in gem5/gem5[develop]: cpu: remove RefCounted from MinorDynInst

Tom Rollet has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/68299?usp=email ) Change subject: cpu: remove RefCounted from MinorDynInst .. cpu: remove RefCounted from MinorDynInst

[gem5-dev] [L] Change in gem5/gem5[develop]: base: remove refcnt.hh file

Tom Rollet has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/68300?usp=email ) Change subject: base: remove refcnt.hh file .. base: remove refcnt.hh file Remove now useless

[gem5-dev] [S] Change in gem5/gem5[develop]: cpu-o3: remove RefCounted from DynInst

Tom Rollet has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/68297?usp=email ) Change subject: cpu-o3: remove RefCounted from DynInst .. cpu-o3: remove RefCounted from DynInst

[gem5-dev] [XL] Change in gem5/gem5[develop]: arch,cpu: remove RefCounted from StaticInst

Tom Rollet has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/68298?usp=email ) Change subject: arch,cpu: remove RefCounted from StaticInst .. arch,cpu: remove RefCounted from

[gem5-dev] Change in gem5/gem5[develop]: python: remove SimObject children on NULL assignment

Tom Rollet has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/51647 ) Change subject: python: remove SimObject children on NULL assignment .. python: remove SimObject children on NULL assignment

[gem5-dev] Change in gem5/gem5[develop]: python: remove SimObject children on NULL assignment

Tom Rollet has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/51647 ) Change subject: python: remove SimObject children on NULL assignment .. python: remove SimObject children on NULL

[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: Naming cleanup for LSQRequest and Request

Tom Rollet has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/51067 ) Change subject: cpu-o3: Naming cleanup for LSQRequest and Request .. cpu-o3: Naming cleanup for LSQRequest and Request

[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: remove LSQSenderState

Tom Rollet has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/50733 ) Change subject: cpu-o3: remove LSQSenderState .. cpu-o3: remove LSQSenderState The LSQSenderState that was attached to

[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: remove useless 'using'-s

Tom Rollet has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/51347 ) Change subject: cpu-o3: remove useless 'using'-s .. cpu-o3: remove useless 'using'-s Change-Id:

[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: remove useless 'using'-s

Tom Rollet has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/51347 ) Change subject: cpu-o3: remove useless 'using'-s .. cpu-o3: remove useless 'using'-s Change-Id:

[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: remove false dummy entry in LSQ

Tom Rollet has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/50732 ) Change subject: cpu-o3: remove false dummy entry in LSQ .. cpu-o3: remove false dummy entry in LSQ The constructor of the

[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: Naming cleanup for LSQRequest and Request

Tom Rollet has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/51067 ) Change subject: cpu-o3: Naming cleanup for LSQRequest and Request .. cpu-o3: Naming cleanup for LSQRequest and

[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: replace 'stores' counter per storeQueue.size()

Tom Rollet has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/50730 ) Change subject: cpu-o3: replace 'stores' counter per storeQueue.size() .. cpu-o3: replace 'stores' counter per

[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: remove useless indirection from lsq to cpu

Tom Rollet has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/50731 ) Change subject: cpu-o3: remove useless indirection from lsq to cpu .. cpu-o3: remove useless indirection from lsq to cpu

[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: replace 'loads' counter per loadQueue.size()

Tom Rollet has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/50729 ) Change subject: cpu-o3: replace 'loads' counter per loadQueue.size() .. cpu-o3: replace 'loads' counter per loadQueue.size()

[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: remove useless indirection from lsq to cpu

Tom Rollet has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/50731 ) Change subject: cpu-o3: remove useless indirection from lsq to cpu .. cpu-o3: remove useless indirection from lsq

[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: replace 'stores' counter per storeQueue.size()

Tom Rollet has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/50730 ) Change subject: cpu-o3: replace 'stores' counter per storeQueue.size() .. cpu-o3: replace 'stores' counter per

[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: replace 'loads' counter per loadQueue.size()

Tom Rollet has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/50729 ) Change subject: cpu-o3: replace 'loads' counter per loadQueue.size() .. cpu-o3: replace 'loads' counter per

[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: remove false dummy entry in LSQ

Tom Rollet has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/50732 ) Change subject: cpu-o3: remove false dummy entry in LSQ .. cpu-o3: remove false dummy entry in LSQ The

[gem5-dev] Change in gem5/gem5[develop]: cpu: add perfect Branch Predictor

Tom Rollet has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/50727 ) Change subject: cpu: add perfect Branch Predictor .. cpu: add perfect Branch Predictor This commit adds a oracle

[gem5-dev] Change in gem5/gem5[develop]: tests: add tests for the perfect BP

Tom Rollet has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/50728 ) Change subject: tests: add tests for the perfect BP .. tests: add tests for the perfect BP Change-Id:

[gem5-dev] Change in gem5/gem5[develop]: scons: fix hook for 'deprecated' attribute

Tom Rollet has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/48843 ) Change subject: scons: fix hook for 'deprecated' attribute .. scons: fix hook for 'deprecated' attribute On the new

[gem5-dev] Change in gem5/gem5[develop]: scons: fix hook for 'deprecated' attribute

Tom Rollet has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/48843 ) Change subject: scons: fix hook for 'deprecated' attribute .. scons: fix hook for 'deprecated' attribute On the

[gem5-dev] Change in gem5/gem5[develop]: mem-cache: Add MSHR debuging information

Tom Rollet has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/47041 ) Change subject: mem-cache: Add MSHR debuging information .. mem-cache: Add MSHR debuging information Add debug statment in

[gem5-dev] Change in gem5/gem5[develop]: mem-cache: Queue,QueueEntry, NSHR::TargetList inherit from Named

Tom Rollet has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/47040 ) Change subject: mem-cache: Queue,QueueEntry, NSHR::TargetList inherit from Named .. mem-cache: Queue,QueueEntry,

[gem5-dev] Change in gem5/gem5[develop]: mem-cache: change Cache debug flag to MSHR in MSHR code

Tom Rollet has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/47039 ) Change subject: mem-cache: change Cache debug flag to MSHR in MSHR code .. mem-cache: change Cache debug flag to MSHR in

[gem5-dev] Change in gem5/gem5[develop]: sim: Add serialization for file descriptor array

Tom Rollet has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/46619 ) Change subject: sim: Add serialization for file descriptor array .. sim: Add serialization for file descriptor array Add

[gem5-dev] Change in gem5/gem5[develop]: mem-cache: change Cache debug flag to MSHR in MSHR code

Tom Rollet has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/47039 ) Change subject: mem-cache: change Cache debug flag to MSHR in MSHR code .. mem-cache: change Cache debug flag to

[gem5-dev] Change in gem5/gem5[develop]: mem-cache: Add MSHR debuging information

Tom Rollet has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/47041 ) Change subject: mem-cache: Add MSHR debuging information .. mem-cache: Add MSHR debuging information Add debug

[gem5-dev] Change in gem5/gem5[develop]: mem-cache: Make Queue and QueueEntry inherit from Named class

Tom Rollet has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/47040 ) Change subject: mem-cache: Make Queue and QueueEntry inherit from Named class .. mem-cache: Make Queue and

[gem5-dev] Change in gem5/gem5[develop]: mem: add MSHR debuging stats

Tom Rollet has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/46979 ) Change subject: mem: add MSHR debuging stats .. mem: add MSHR debuging stats MSHR does not have debug stat.

[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: Add loadToUse stat

Tom Rollet has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/46679 ) Change subject: cpu-o3: Add loadToUse stat .. cpu-o3: Add loadToUse stat Add stat in o3 model to track the latency of load

[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: fix commit DPRINTF ROB arguments order

Tom Rollet has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/46599 ) Change subject: cpu-o3: fix commit DPRINTF ROB arguments order .. cpu-o3: fix commit DPRINTF ROB arguments order Change-Id:

[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: Add loadToUse stat

Tom Rollet has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/46679 ) Change subject: cpu-o3: Add loadToUse stat .. cpu-o3: Add loadToUse stat Add stat in o3 model to track the

[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: fix dispatch assert triggering on debug mode

Tom Rollet has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/46600 ) Change subject: cpu-o3: fix dispatch assert triggering on debug mode .. cpu-o3: fix dispatch assert triggering on debug mode

[gem5-dev] Change in gem5/gem5[develop]: sim: Add serialization for host backed files

Tom Rollet has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/46619 ) Change subject: sim: Add serialization for host backed files .. sim: Add serialization for host backed files

[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: fix dispatch assert triggering on debug mode

Tom Rollet has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/46600 ) Change subject: cpu-o3: fix dispatch assert triggering on debug mode .. cpu-o3: fix dispatch assert triggering on

[gem5-dev] Change in gem5/gem5[develop]: cpu: fix commit DPRINTF ROB arguments order

Tom Rollet has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/46599 ) Change subject: cpu: fix commit DPRINTF ROB arguments order .. cpu: fix commit DPRINTF ROB arguments order