changeset f5e86115a07a in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=f5e86115a07a
description:
sim: fold checkpoint restore code into instantiate()
The separate restoreCheckpoint() call is gone; just pass
the checkpoint dir as an optional arg to
changeset 3f6413fc37a2 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=3f6413fc37a2
description:
sim: revamp unserialization procedure
Replace direct call to unserialize() on each SimObject with a pair of
calls for better control over initialization in
changeset b4aa25440bdd in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=b4aa25440bdd
description:
x86: minor checkpointing bug fixes
diffstat:
src/arch/x86/interrupts.hh | 4 ++--
src/arch/x86/isa.cc| 5 +
2 files changed, 7 insertions(+), 2 deletions(-)
changeset c76a14014c27 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=c76a14014c27
description:
misc: add some AMD copyright notices
Meant to add these with the previous batch of csets.
diffstat:
configs/common/Simulation.py | 1 +
src/python/m5/SimObject.py
On 2010-08-17 14:56:45, Ali Saidi wrote:
src/base/intmath.hh, line 84
http://reviews.m5sim.org/r/164/diff/1/?file=1817#file1817line84
How about a warning if it's called with an exponent 20?
I'd prefer something a little more robust. One option is to track old and new
result
On 2010-08-17 14:56:45, Ali Saidi wrote:
src/base/intmath.hh, line 84
http://reviews.m5sim.org/r/164/diff/1/?file=1817#file1817line84
How about a warning if it's called with an exponent 20?
Steve Reinhardt wrote:
I'd prefer something a little more robust. One option
On Sun, Aug 15, 2010 at 6:07 PM, Min Kyu Jeong mkje...@gmail.com wrote:
I needed to spit out a code that reads from a register, and writes to it
again. The thing is arch reg indices are renamed (reg renaming and shadow
reg file), so many structures are needed to be looked up to find a
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On 2010-07-29 21:52:09, Steve Reinhardt wrote
On Fri, Aug 13, 2010 at 10:54 PM, Gabe Black gbl...@eecs.umich.edu wrote:
Steve Reinhardt wrote:
On Fri, Aug 13, 2010 at 6:32 AM, Gabe Black gbl...@eecs.umich.edu wrote:
changeset 67c670459d01 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=67c670459d01
description
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src/dev/arm/timer_sp804.cc
http://reviews.m5sim.org/r/164/#comment334
On 2010-08-13 23:21:30, Gabe Black wrote:
src/base/intmath.hh, line 84
http://reviews.m5sim.org/r/164/diff/1/?file=1817#file1817line84
This isn't particularly efficient. A better algorithm would be to
square n over and over and multiply it in if the appropriate bit in e is
On 2010-08-14 00:33:43, Gabe Black wrote:
src/mem/cache/cache_impl.hh, line 561
http://reviews.m5sim.org/r/192/diff/1/?file=1911#file1911line561
Don't comment out code, delete it. Why is this assert no longer needed?
I don't know the cache code so I apologize if it's obvious.
On 2010-08-14 00:45:14, Gabe Black wrote:
The ISA parser is foundational for a LOT of code and shouldn't be changed
unless it's absolutely necessary or the end goal itself. There are a lot of
changes to it here, and without going through them it's likely most of them
could/should be
On Sat, Aug 14, 2010 at 9:43 AM, Gabe Black gbl...@eecs.umich.edu wrote:
@@ -889,11 +894,6 @@
effAddrValid = true;
fault = cpu-read(req, sreqLow, sreqHigh, data, lqIdx);
} else {
-
- // Return a fixed value to keep simulation deterministic even
- // along
On Fri, Aug 13, 2010 at 6:32 AM, Gabe Black gbl...@eecs.umich.edu wrote:
changeset 67c670459d01 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=67c670459d01
description:
CPU: Add readBytes and writeBytes functions to the exec contexts.
@@ -889,11 +894,6 @@
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Is this right? Seems like genrand(1) and genrand(2) will now do the same
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src/dev/io_device.cc
http://reviews.m5sim.org/r/188/#comment308
Did
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This works, so I hate to complain, but it would be a lot more pythonic to
On 2010-08-09 12:13:59, Nathan Binkert wrote:
util/m5/m5.c, line 68
http://reviews.m5sim.org/r/121/diff/1/?file=1333#file1333line68
I actually just noticed that you're zeroing sizeof(buf). Perhaps you
should do what gabe said and just touch one word per page. Seems like this
On Mon, Aug 9, 2010 at 12:23 PM, nathan binkert n...@binkert.org wrote:
Seems like an overoptimization to me, unless we plan on using readfile to
bring in some really huge files. Also, there's no harm in doing this in
non-x86 ISAs. I won't fight putting those changes in, I'm just
On Tue, Aug 3, 2010 at 10:43 PM, nathan binkert n...@binkert.org wrote:
No, I don't think those should be SimObjects since they're really just
handy abstractions for use internal to the I8042 (PS/2 keyboard and
mouse controller). It would be reasonable, though, to still put
serialization
On Wed, Aug 4, 2010 at 8:43 AM, nathan binkert n...@binkert.org wrote:
So should we be converting these subobjects to SimObjects to make it
easier to serialize them? Joel previously ran into a bug with the
timer object (the MC one) where the Tsunami code was properly
calling its
On Wed, Aug 4, 2010 at 12:40 PM, nathan binkert n...@binkert.org wrote:
Perhaps we could figure out if we (or Joel :) could somewhat quickly
implement some of the Serialization changes that we discussed.
Did we ever write down what those changes were? I recall that
discussion but not the
I've had success with the postreview extension and the -o argument.
Steve
On Mon, Aug 2, 2010 at 11:24 PM, Gabe Black gbl...@eecs.umich.edu wrote:
Here are my patches that implement the readBytes/writeBytes exec
context functions. They also include the patches that get rid of ozone
and
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You need a space after for and if (see
That's useful information... most of my motivation for iterChildren()
was to be consistent with other python methods like iteritems(),
iterkeys(), etc., so if that's going away then I'm less motivated to
stick with it. I haven't played with python3 so I didn't know that.
See, I told you that you
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Ship it!
- Steve
On 2010-07-28 16:05:00, Joel Hestness wrote:
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Thanks! Just a couple minor things...
- Did you test this with the other
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(Updated 2010-07-29 21:30:08.431457)
Review request for Default.
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Review request for Default.
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(Updated 2010-07-29 21:42:28.129201)
Review request for Default.
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bus: clean up default responder code.
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configs: clean up checkpoint code in
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sim: fold checkpoint restore code into
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sim: revamp unserialization procedure
://reviews.m5sim.org/r/27/#comment268
Beats me, it didn't cross my mind...
- Steve
On 2010-07-29 21:42:28, Steve Reinhardt wrote:
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changeset b28e7286990c in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=b28e7286990c
description:
.hgignore: added src/doxygen
diffstat:
.hgignore | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diffs (8 lines):
diff -r a3a439363a47 -r b28e7286990c .hgignore
I'm confused... what exactly is the problem? Doesn't it work just to
create two independent tests?
Steve
On Mon, Jul 26, 2010 at 12:20 PM, Gabriel Michael Black
gbl...@eecs.umich.edu wrote:
I don't think we/I found a good solution. I had (and may still have) copied
and pasted versions of
to be passed.
Thanks,
Min
On Thu, Jul 15, 2010 at 10:01 AM, Steve Reinhardt ste...@gmail.com
mailto:ste...@gmail.com wrote:
On Wed, Jul 14, 2010 at 8:35 AM, Min Kyu Jeong mkje...@gmail.com
mailto:mkje...@gmail.com wrote:
b) memory is atomic (is it a possible combination? dyn_inst
For your second part (the thread suspend/activate) I agree that at
first glance it looks like a bug. Korey has been the most recent
person to work with O3 SMT thread handling, and I see his name
attached to some of the lines in question, so I'll let him respond...
Steve
On Wed, Jul 21, 2010 at
On Thu, Jul 22, 2010 at 10:03 AM, Korey Sewell ksew...@umich.edu wrote:
The problem is that there are some conventions that we would need to point
out and follow (i.e. Do threads start out Halted, Idle, or ???)
Yea, I know that's the key to the problems we had before, is that
different people
On Thu, Jul 22, 2010 at 1:12 PM, Timothy M Jones tjon...@inf.ed.ac.uk wrote:
So, after all this, which version do you want me to implement? TID or ASID?
I'll have a go at either.
I think you should go with the TID since that's the normal approach.
If Korey needs to use the ASID instead for
In generalI think this is the kind of ISA hook we should be using...
in the sense that checking TheISA::HasUnalignedMemAcc is much better
than (TheISA == x86 || TheISA == Power). I think it's useful not
only to avoid the overhead of a dynamic check for an ISA that doesn't
need it, but also to
On Sat, Jul 17, 2010 at 4:52 AM, Korey Sewell ksew...@umich.edu wrote:
A hint for this is that the InOrderCPU was passing the nextPC to the branch
predictor instead of the PC, so there is a ras statement there that you'll
need to be aware of to update.
That seems odd... I assume you're
changeset b543b8e5fcbc in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=b543b8e5fcbc
description:
SimObject: transparently forward Python attribute refs to C++.
This tidbit was pulled from a larger patch for Tim's sake, so
the comment reflects functions
On Wed, Jul 14, 2010 at 6:46 AM, Jiayuan Meng jerryh...@gmail.com wrote:
Thank you all for the suggestions!
=== I have the following questions: ===
1. how would M5 support plugins with pseudo instructions in the ISA?
Following Gabe's thoughts:
* M5 can provide general, customizable pseudo
For the classic (non-Ruby) m5 memory system, the coherence protocol
is pretty tightly integrated with the cache model. I don't know that
you can just disable it.
You certainly can set different block sizes on different caches (as I
think you already tried)... if you really want to pursue this
You're right that it could be done either way. I think the rationale
is that this way you don't need to search a list to see if your
address is on it. If the common case is that there are no locked
blocks in the entire cache though then that's not a big deal since the
list will be empty anyway.
Alpha has to do the same thing on interrupts... the way this is
handled is that there's a per-thread lock flag in the CPU that gets
cleared on interrupts, and if that flag is not set then we fail the SC
without even sending it to the cache. (At least that's my
recollection of how it works.)
on uncachable accesses.
Ali
On Thu, 15 Jul 2010 16:27:56 -0700, Steve Reinhardt
begin_of_the_skype_highlighting end_of_the_skype_highlighting
ste...@gmail.com
wrote:
Alpha has to do the same thing on interrupts... the way this is
handled is that there's a per-thread lock flag
Very cool!
On Thu, Jul 15, 2010 at 4:50 PM, Ali Saidi sa...@umich.edu wrote:
The uart is still a bit flaky and there is tons more todo, however:
m5 slave terminal: Terminal 0
[ 0.00] Linux version 2.6.28-arm2-eb-a9-arm-nano-tiny-up-wa-4.3.3
(alisa...@aus-bc5-b7) (gcc
On Tue, Jul 13, 2010 at 5:47 PM, Gabriel Michael Black
gbl...@eecs.umich.edu wrote:
Quoting Steve Reinhardt ste...@gmail.com:
On Tue, Jul 13, 2010 at 11:20 AM, Gabe Black gbl...@eecs.umich.edu
wrote:
I can't say it was -the- reason, but one reason is that the TLBs as is
don't actually send
On Mon, Jul 12, 2010 at 8:20 AM, Jiayuan Meng jerryh...@gmail.com wrote:
Dear M5 Team,
I'll soon start to work on integrating our M5-based simulator, MV5, into
M5. I've read some documentation on the current status of M5, and I'd like
to share my plan/ideas with you and hear your suggestions.
All the discussion of different extensions to TimingSimpleCPU got me
thinking again about what a mess it is. I walked through the code
with Brad Joel a few weeks ago, and it's still the same basic
structure of everything being driven by callbacks, with numerous cases
where we call the next
On Tue, Jul 13, 2010 at 10:35 AM, Korey Sewell ksew...@umich.edu wrote:
Thoughts? Volunteers? :-)
I had thoughts on similar tasks where you would need to do some editing on a
memory request
after it's been sent to the CPU.
I wouldnt mind a shim object so to speak, but what about
On Tue, Jul 13, 2010 at 11:20 AM, Gabe Black gbl...@eecs.umich.edu wrote:
I can't say it was -the- reason, but one reason is that the TLBs as is
don't actually send the packets for the CPU, so they can't split
anything into multiple transactions easily. I'm intrigued by the idea of
putting the
On Sun, Jul 11, 2010 at 11:25 PM, Gabe Black gbl...@eecs.umich.edu wrote:
Lets say I'm trying to read 3 uint16_ts. If I take the data from the
packet and just case it to a uint16_t *, the host memory used as the
packet payload may not be 2 byte aligned. What I'd need to do to ensure
I can
On Sat, Jul 10, 2010 at 11:37 PM, Gabe Black gbl...@eecs.umich.edu wrote:
In ARM's SIMD instruction set extension Neon, there are some
instructions which can load or store 3 of something, and that something
can be 1, 2, 4, or 8 bytes. To implement this properly, I'm planning to
add readBytes
On 2010-07-10 08:52:15, Steve Reinhardt wrote:
src/sim/sim_object.cc, line 275
http://reviews.m5sim.org/r/51/diff/1/?file=757#file757line275
I'd prefer a more informative message like Error: setMaxInsts called
on non-CPU (and same with the following function
as
possible and add anything extra into some subclass of them?
Tim
On 10/07/2010 13:03, Steve Reinhardt wrote:
If you do look at the patch, you'll see that it's a pretty minor hook
in the BaseSimpleCPU code, and doesn't touch atomic.* or timing.* at
all. Plus warming up state like caches
On 2010-07-10 08:52:15, Steve Reinhardt wrote:
src/sim/eventq.hh, line 489
http://reviews.m5sim.org/r/51/diff/1/?file=755#file755line489
I don't like getting rid of this assertion... it's actually pretty
useful in knowing when something's not right. You should add some code
On 2010-07-10 08:57:34, Steve Reinhardt wrote:
I'm curious about the overall need for this... is there really a situation
where it matters? If there's some path that's not appropriately
setting/checking/ignoring the whenReady field I'd rather fix that than add
this feature
On 2010-07-10 08:52:15, Steve Reinhardt wrote:
src/sim/eventq.hh, line 489
http://reviews.m5sim.org/r/51/diff/1/?file=755#file755line489
I don't like getting rid of this assertion... it's actually pretty
useful in knowing when something's not right. You should add some code
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It looks like this is identical to the Alpha version of this code, and is
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Is the root problem here that when I have an A-B port connection, then I
Thanks, Timothy! This looks like a great addition and I really
appreciate your effort to contribute your changes back.
I did several comments on reviewboard, but rather than flood the list
with a bunch of ship it! comments, I'll just say here that
everything I didn't comment on looks good to me.
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OK, looking a little closer I see that Impl is also used to get the DynInst
On Sat, Jul 10, 2010 at 3:11 PM, Gabe Black gbl...@eecs.umich.edu wrote:
I'm replying on m5-dev instead of review board since this is wandering
away from the topic of Timothy's code. Please let me know if we're
trying to keep things on there anyway.
No, I think you made the right move.
I've
changeset aab017d1adc6 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=aab017d1adc6
description:
cache: fix bug in SC upgrade handling
This bug was introduced with the recent rework of SC
failure handling in cset f97b62be544f.
diffstat:
.
Steve
On Thu, Jul 8, 2010 at 5:55 PM, Steve Reinhardt steve.reinha...@amd.com wrote:
changeset aab017d1adc6 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=aab017d1adc6
description:
cache: fix bug in SC upgrade handling
This bug was introduced
Just to add my two cents:
- As far as the memory system goes, I thought the drain protocol took
care of the case where an object thought it was drained but then
wasn't anymore. For example, if there's a request at the L1 and the
L2 thinks it's drained, then when that request goes from the L1 to
On Sun, Jul 4, 2010 at 4:54 PM, Ali Saidi sa...@umich.edu wrote:
Right, unless it is possible to take a checkpoint with a simple cpu
and then restore with the inorder cpu. In fact, that brings up my next
question. How does switching cpu work in conjunction with
checkpointing? Is it possible to
changeset 2a5e4070155e in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=2a5e4070155e
description:
process: minor format/style cleanup
diffstat:
src/sim/process.cc | 26 --
1 files changed, 16 insertions(+), 10 deletions(-)
diffs (88 lines):
changeset cf7c4345ea82 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=cf7c4345ea82
description:
process: get rid of some unused code vars
diffstat:
src/sim/process.cc | 72 --
src/sim/process.hh | 7 -
2
, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Author: Steve Reinhardt
+#
+
+# Basic test script for checkpointing.
+#
+# Given an M5 command and an interval (in ticks), this script will:
+# 1
changeset 1803e46ddf57 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=1803e46ddf57
description:
checkpointing: fix minor bug
Somehow we now need to explicitly specialize on
'signed char' and not just 'char' to catch cases
like int8_t
diffstat:
changeset e8ff1fb26dbc in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=e8ff1fb26dbc
description:
checkpointing: minor cleanup.
Move some static checkpoint stuff into the
Checkpoint object namespace.
diffstat:
src/sim/serialize.cc | 61
changeset acc1fbbef239 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=acc1fbbef239
description:
sim: fold StartupCallback into SimObject
There used to be a reason to have StartupCallback
be a separate object, but not any more. Now
it's just
changeset 81328f5e764a in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=81328f5e764a
description:
sim: allow SimObject subclasses to define classmethods
(without requiring a leading underscore)
Also a little cleanup on type names in SimObject.py.
changeset 249f174e6f37 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=249f174e6f37
description:
checkpointing: another small overload fix
On Nate's advice, overload 'char' as well as 'signed char'
and 'unsigned char'.
diffstat:
src/base/str.cc |
On Fri, Jul 2, 2010 at 10:10 PM, nathan binkert n...@binkert.org wrote:
Not that I can tell... it mostly seems to be stuff that either depends
on or is in lieu of unserialization, or maybe stuff that could be
moved to init() but just didn't get put there. Not that it's always
easy to tell by
On Sat, Jul 3, 2010 at 1:56 PM, soumyaroop roy s...@cse.usf.edu wrote:
Now, this is my understanding of how a checkpoint is taken. Please
correct me if I am wrong. I noted that when checkpointing is specified
with these options: --take-checkpoint=N --at-instruction, the
max_insts_any_thread
On Thu, Jun 24, 2010 at 9:34 AM, nathan binkert n...@binkert.org wrote:
if checkpoint arg provided:
for each SimObject:
if checkpoint has section for this SimObject:
call unserialize()
else:
call unserializeNoData()
else:
for each SimObject:
call
On Fri, Jul 2, 2010 at 6:07 PM, nathan binkert n...@binkert.org wrote:
Only the last two really do anything I'd characterize as startup,
and only BaseCPU seems to use startup() to actually schedule any
events (though Bus::startup() does depend on curTick, so it needs to
come after
So wouldn't a functional table walker be basically be the same as an
atomic-mode one? I'd think it's only the timing-mode version that
really needs all the explicit state. That is, if you were going to
have two versions, I'd think you'd have a functional/atomic one and a
timing one, not a
' .):
return getattr(self._ccObject, attr)
Just less code and I know that you like less code :)
Steve Reinhardt wrote:
Sounds good to me... I'll give it a try.
I did this to be more parallel with the rest of __getattr__:
# If the attribute exists on the C
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(Updated 2010-06-27 23:37:29.206019)
Review request for Default.
Summary
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(Updated 2010-06-27 23:41:59.518566)
Review request for Default.
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it is.
- Steve
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On 2010-06-27 23:37:29, Steve Reinhardt wrote
On Mon, Jun 28, 2010 at 8:53 PM, Nathan Binkert n...@binkert.org wrote:
Is there anything useful in the queue that's not in this set of changes that
you posted for review?
This is really just laying the groundwork for the restructuring of
init/startup I discussed a few days ago, but that code
Did anyone else get a regression email since this one? It's the last
one I received. The regressions are still running; it looks like it's
just the mail that's not getting sent out. I don't know if that's
related to the increased frequency of other annoying messages from
zizzer or not.
Steve
it a try.
- Steve
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On 2010-06-27 23:41:59, Steve Reinhardt wrote
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Review request for Default.
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sim: fold StartupCallback into
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Review request for Default.
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sim: make Python Root object a
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sim: move iterating over SimObjects
OK, I got ahead of myself... this doesn't compile. I may redo this whole
optional argument scheme using *posargs after all.
- Steve
On 2010-06-27 21:30:03, Steve Reinhardt wrote:
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http://reviews.m5sim.org/r/26/
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(Updated 2010-06-27 22:19:51.672485)
Review request for Default.
Summary
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Hi Korey,
You really threw me for a loop with this one... I was testing out a
simple change, which I often do using m5.debug since it compiles
faster, and the inorder tests kept failing. I could see that it was
due to some changes you made recently, but I had pulled both the code
changes and the
On Wed, Jun 23, 2010 at 10:30 PM, nathan binkert n...@binkert.org wrote:
I've long thought that it would be nice if we could have multi step
init/startup. The basic way to do it is to have init() return a bool.
If it's true, then that object should have init called again in a
second round.
On Wed, Jun 23, 2010 at 10:48 PM, Gabe Black gbl...@eecs.umich.edu wrote:
The entire SimObject startup process has always been a little mysterious
to me as far as what all the steps are and what they're for, and it
sounds like it's getting more complicated. For those of us that don't
already
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