Re: [m5-dev] Review Request: sparc: compilation fixes for inorder

[Korey Sewell]

> On 2011-03-16 15:17:00, Gabe Black wrote:
> > There are a number of style issues to clean up, but otherwise this seems 
> > mostly ok. I'm still not crazy about having an mt.hh that's only used in 
> > InOrder and MIPS, as far as I'm aware. That's ISA specific behavior 
> > masquerading as something generic, but that's probably a separate issue 
> > from this change.

Agreed on the mt.hh file, I've been thinking of ways to mask that out. I need 
to double check, but if those are just per-thread RegFile calls are just 
triggered through instruction calls then maybe the ISA description can handle 
it.


> On 2011-03-16 15:17:00, Gabe Black wrote:
> > src/arch/sparc/registers.hh, line 80
> > 
> >
> > This seems redundant. Can't the CPU model add them up just as easily?

The CPU Model could calculate these but it would be the same line wherever you 
put it. 

I'm not sure it's redundant though, since there isn't necessarily a constant 
that just encapsulates all the registers available and there other places 
throughout the code where we are adding constants together to make a easy 
generic term to use for other objects to draw form.

Overall, I thought this was the right place because all the register dependency 
tracking and sizing of Register Files basically uses this file's constants.


- Korey


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On 2011-03-14 17:39:33, Korey Sewell wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/583/
> ---
> 
> (Updated 2011-03-14 17:39:33)
> 
> 
> Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and 
> Nathan Binkert.
> 
> 
> Summary
> ---
> 
> sparc: compilation fixes for inorder
> Add a few constants and functions that the InOrder model wants for SPARC.
> * * *
> sparc: add eaComp function
> InOrder separates the address generation from the actual access so give
> Sparc that functionality
> * * *
> sparc: add control flags for branches
> branch predictors and other cpu model functions need to know specific 
> information
> about branches, so add the necessary flags here
> 
> 
> Diffs
> -
> 
>   src/arch/sparc/isa/decoder.isa 6c9b532da0a6 
>   src/arch/sparc/isa/formats/branch.isa 6c9b532da0a6 
>   src/arch/sparc/isa/formats/mem/basicmem.isa 6c9b532da0a6 
>   src/arch/sparc/isa/formats/mem/swap.isa 6c9b532da0a6 
>   src/arch/sparc/isa/formats/mem/util.isa 6c9b532da0a6 
>   src/arch/sparc/mt.hh PRE-CREATION 
>   src/arch/sparc/registers.hh 6c9b532da0a6 
>   src/cpu/inorder/cpu.cc 6c9b532da0a6 
>   src/cpu/inorder/inorder_dyn_inst.cc 6c9b532da0a6 
> 
> Diff: http://reviews.m5sim.org/r/583/diff
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Korey
> 
>

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Re: [m5-dev] Review Request: isa: get rid of expandForMT function

[Korey Sewell]

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---

(Updated 2011-03-17 20:17:57.438673)


Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan 
Binkert.


Summary
---

isa: get rid of expandForMT function
MIPS is the only ISA that cares about having a piece of ISA state integrate
multiple threads so add constants for MIPS and relieve the other ISAs from 
having
to define this. Also, InOrder was the only core that was actively calling
this function
* * *
isa: get rid of corespecific type
The CoreSpecific type was used as a proxy to pass in HW specific params to
a MIPS CPU, but since MIPS FS hasnt been touched for awhile, it makes sense
to not force every other ISA to use CoreSpecific as well use a special
reset function to set it. That probably should go in a PowerOn reset fault
 anyway.


Diffs (updated)
-

  src/arch/alpha/isa.hh 6c9b532da0a6 
  src/arch/alpha/types.hh 6c9b532da0a6 
  src/arch/arm/types.hh 6c9b532da0a6 
  src/arch/mips/isa.hh 6c9b532da0a6 
  src/arch/mips/isa.cc 6c9b532da0a6 
  src/arch/mips/types.hh 6c9b532da0a6 
  src/arch/power/types.hh 6c9b532da0a6 
  src/arch/sparc/types.hh 6c9b532da0a6 
  src/arch/x86/types.hh 6c9b532da0a6 
  src/cpu/BaseCPU.py 6c9b532da0a6 
  src/cpu/base.hh 6c9b532da0a6 
  src/cpu/inorder/cpu.hh 6c9b532da0a6 
  src/cpu/inorder/cpu.cc 6c9b532da0a6 

Diff: http://reviews.m5sim.org/r/578/diff


Testing
---


Thanks,

Korey

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Re: [m5-dev] Review Request: cpu: split o3-specific parts out of BaseDynInst

[Korey Sewell]

> On 2011-03-03 20:41:09, Ali Saidi wrote:
> > Please don't ship this until I have a chance to try it, I just want to make 
> > sure it doesn't break ARM_FS/O3.
> 
> Korey Sewell wrote:
> Sure, I'd welcome a go of things from some other folks to test if I 
> haven't introduced something quirky.
> 
> After there is some commentary, I'll make sure to run the full 
> regressions before committing this because as we all know BaseDynInst is a 
> pretty fundamental part of M5.
> 
> Also, I'll be posting an update to this diff soon that will make the 
> setRegOperand pure virtual (I mistakenly thought those were 
> templated member functions in the first go-round).
> 
> Ali Saidi wrote:
> Anything happen with your update diff? If you could verify it passes the 
> arm/o3 full system regression I just committed and then I'll give it a go on 
> a bunch more tests.

Gabe made a good point about the virtual function overhead on the commonly used 
set*Operand functions and I've just been waffling on whether to even make those 
pure virtual or not.

However, I'll go ahead and take a hard look at this again , run the 
regressions, and post an update tomorrow so we can move on with this potential 
change.


- Korey


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On 2011-03-01 13:49:24, Korey Sewell wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/529/
> ---
> 
> (Updated 2011-03-01 13:49:24)
> 
> 
> Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and 
> Nathan Binkert.
> 
> 
> Summary
> ---
> 
> cpu: split o3-specific parts out of BaseDynInst
> The bigger picture goal is that I want to get the InorderDynInst class 
> derived from the
> BaseDynInst, since there is no need to replicate a lot of useful code already 
> defined
> in BaseDynInst (e.g. microcode identification, etc.) and Inorder can take 
> advantage
> of common code that handles microcode and other features that other ISAs need.
> 
> But to do this, there are a lot of o3-specific things that are in 
> BaseDynInst, that I pushed to
> O3DynInst in this patch. Book-keeping variables that handle the IQ,LSQ,ROB 
> are unnecessary in
> the base class but generic variables that will work across CPUs (IsSquashed, 
> IsCompleted, etc.)
> are kept in the base class.
> 
> The upside is more consistency across the simple models (branch prediction 
> and instruction
> identification are all in one common place).
> 
> I really wanted to define pure virtual functions for read/write(to memory) 
> and the
> setRegOperand, but virtual functions in a templated class is a 
> no-no and
> I couldn't get around that (suggestions?).
> 
> Also, I'd rather not use the "this->" pointer all over the place to access 
> member variables of
> the templated Base class, but it had to be done.
> 
> Other than those quirks, simulator functionality should stay the same as the 
> O3 Model always references
> the O3DynInst pointer and the InOrder model doesnt currently make use of the 
> base dyn inst. class.
> (but it will be easier to derive from now...)
> 
> 
> Diffs
> -
> 
>   src/cpu/base_dyn_inst.hh cf1afc88070f 
>   src/cpu/base_dyn_inst_impl.hh cf1afc88070f 
>   src/cpu/o3/dyn_inst.hh cf1afc88070f 
>   src/cpu/o3/dyn_inst_impl.hh cf1afc88070f 
> 
> Diff: http://reviews.m5sim.org/r/529/diff
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Korey
> 
>

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Re: [m5-dev] Review Request: patch from Vince Weaver for review

[Ali Saidi]

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---

Ship it!


- Ali


On 2011-03-17 16:05:56, Lisa Hsu wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/588/
> ---
> 
> (Updated 2011-03-17 16:05:56)
> 
> 
> Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and 
> Nathan Binkert.
> 
> 
> Summary
> ---
> 
> X86:  SE syscalls: patch from Vince Weaver for review
> 
> 
> Diffs
> -
> 
>   src/arch/x86/linux/syscalls.cc 2e269d6fb3e6 
> 
> Diff: http://reviews.m5sim.org/r/588/diff
> 
> 
> Testing
> ---
> 
> I've done minimal testing on these, i.e. I've pushed them to a clean tree and 
> run X86 SPEC2k6 binaries on them, some of which didn't work prior to the 
> patches but now do.  Others remain broken.  Vince, however, has done lots of 
> testing and basically needed these to run SPEC2K workloads to completion for 
> his thesis.  In other words, I bet these patches are good, but not complete 
> for the purposes of running SPEC2k6.
> 
> 
> Thanks,
> 
> Lisa
> 
>

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Re: [m5-dev] Review Request: X86 ioctl: Another patch from Vince Weaver

[Ali Saidi]

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---

Ship it!


- Ali


On 2011-03-17 16:06:13, Lisa Hsu wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/589/
> ---
> 
> (Updated 2011-03-17 16:06:13)
> 
> 
> Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and 
> Nathan Binkert.
> 
> 
> Summary
> ---
> 
> X86 ioctl:  Another patch from Vince Weaver
> 
> 
> Diffs
> -
> 
>   src/arch/x86/linux/syscalls.cc 2e269d6fb3e6 
>   src/sim/syscall_emul.hh 2e269d6fb3e6 
> 
> Diff: http://reviews.m5sim.org/r/589/diff
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Lisa
> 
>

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Re: [m5-dev] Review Request: sim: Fixes Simulation.py to allow more than 1 core for standard switching.

[Ali Saidi]

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---

Ship it!


I haven't verified it myself, but it looks correct by inspection.

- Ali


On 2011-03-11 15:09:54, Anthony Gutierrez wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/564/
> ---
> 
> (Updated 2011-03-11 15:09:54)
> 
> 
> Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and 
> Nathan Binkert.
> 
> 
> Summary
> ---
> 
> sim: Fixes Simulation.py to allow more than 1 core for standard switching. 
> This patch moves the assignment of testsys.switch_cpus, 
> testsys.switch_cpus_1, switch_cpu_list, and switch_cpu_list1 outside of the 
> for loop so they are assigned only once, after switch_cpus and switch_cpus_1 
> are constructed.
> 
> 
> Diffs
> -
> 
>   configs/common/Simulation.py 77aa0f94e7f2 
> 
> Diff: http://reviews.m5sim.org/r/564/diff
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Anthony
> 
>

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Re: [m5-dev] Review Request: cpu: split o3-specific parts out of BaseDynInst

[Ali Saidi]

> On 2011-03-03 20:41:09, Ali Saidi wrote:
> > Please don't ship this until I have a chance to try it, I just want to make 
> > sure it doesn't break ARM_FS/O3.
> 
> Korey Sewell wrote:
> Sure, I'd welcome a go of things from some other folks to test if I 
> haven't introduced something quirky.
> 
> After there is some commentary, I'll make sure to run the full 
> regressions before committing this because as we all know BaseDynInst is a 
> pretty fundamental part of M5.
> 
> Also, I'll be posting an update to this diff soon that will make the 
> setRegOperand pure virtual (I mistakenly thought those were 
> templated member functions in the first go-round).

Anything happen with your update diff? If you could verify it passes the arm/o3 
full system regression I just committed and then I'll give it a go on a bunch 
more tests. 


- Ali


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On 2011-03-01 13:49:24, Korey Sewell wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/529/
> ---
> 
> (Updated 2011-03-01 13:49:24)
> 
> 
> Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and 
> Nathan Binkert.
> 
> 
> Summary
> ---
> 
> cpu: split o3-specific parts out of BaseDynInst
> The bigger picture goal is that I want to get the InorderDynInst class 
> derived from the
> BaseDynInst, since there is no need to replicate a lot of useful code already 
> defined
> in BaseDynInst (e.g. microcode identification, etc.) and Inorder can take 
> advantage
> of common code that handles microcode and other features that other ISAs need.
> 
> But to do this, there are a lot of o3-specific things that are in 
> BaseDynInst, that I pushed to
> O3DynInst in this patch. Book-keeping variables that handle the IQ,LSQ,ROB 
> are unnecessary in
> the base class but generic variables that will work across CPUs (IsSquashed, 
> IsCompleted, etc.)
> are kept in the base class.
> 
> The upside is more consistency across the simple models (branch prediction 
> and instruction
> identification are all in one common place).
> 
> I really wanted to define pure virtual functions for read/write(to memory) 
> and the
> setRegOperand, but virtual functions in a templated class is a 
> no-no and
> I couldn't get around that (suggestions?).
> 
> Also, I'd rather not use the "this->" pointer all over the place to access 
> member variables of
> the templated Base class, but it had to be done.
> 
> Other than those quirks, simulator functionality should stay the same as the 
> O3 Model always references
> the O3DynInst pointer and the InOrder model doesnt currently make use of the 
> base dyn inst. class.
> (but it will be easier to derive from now...)
> 
> 
> Diffs
> -
> 
>   src/cpu/base_dyn_inst.hh cf1afc88070f 
>   src/cpu/base_dyn_inst_impl.hh cf1afc88070f 
>   src/cpu/o3/dyn_inst.hh cf1afc88070f 
>   src/cpu/o3/dyn_inst_impl.hh cf1afc88070f 
> 
> Diff: http://reviews.m5sim.org/r/529/diff
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Korey
> 
>

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Re: [m5-dev] Review Request: swig: get rid of m5.internal.random module (swig/random.i)

[Ali Saidi]

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---

Ship it!


- Ali


On 2011-03-17 17:39:34, Steve Reinhardt wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/595/
> ---
> 
> (Updated 2011-03-17 17:39:34)
> 
> 
> Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and 
> Nathan Binkert.
> 
> 
> Summary
> ---
> 
> swig: get rid of m5.internal.random module (swig/random.i)
> 
> Thanks to swig this was interfering with the standard Python
> random module.  The only function in that module was seed(),
> which erroneously called srand48().  Moved the function to
> m5.internal.core, renamed it seedRandom(), and made it call
> random_mt.init() instead.
> 
> 
> Diffs
> -
> 
>   src/python/SConscript e4b508942ecb 
>   src/python/swig/core.i e4b508942ecb 
>   src/python/swig/random.i e4b508942ecb 
> 
> Diff: http://reviews.m5sim.org/r/595/diff
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Steve
> 
>

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Re: [m5-dev] Review Request: ISA parser: Set up op_src_decl and op_dest_decl for pc operands.

[Korey Sewell]

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---



src/arch/isa_parser.py


Hi Gabe, not to be nitpicky but what are you trying to accomplish with this 
change? 

I have no objection to it, I'm just trying to understand how this applies 
to a particular line of code in defining an instruction. 

Is there a short example you can provide that demonstrates what kind of 
ISA-description you will be able to use with this?


- Korey


On 2011-03-17 14:51:31, Gabe Black wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/587/
> ---
> 
> (Updated 2011-03-17 14:51:31)
> 
> 
> Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and 
> Nathan Binkert.
> 
> 
> Summary
> ---
> 
> ISA parser: Set up op_src_decl and op_dest_decl for pc operands.
> 
> 
> Diffs
> -
> 
>   src/arch/isa_parser.py 5138d1e453f1 
> 
> Diff: http://reviews.m5sim.org/r/587/diff
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Gabe
> 
>

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Re: [m5-dev] changeset in m5: Ruby: expose a simple mod function in slicc int...

[Hsu, Lisa]

When I made this change (this has been sitting in my tree a long time), I 
didn't know SLICC at all.  Now, I could probably figure it out, but it's not 
clear to me that it's worth even the minor effort. 

Lisa

-Original Message-
From: bink...@gmail.com [mailto:bink...@gmail.com] On Behalf Of nathan binkert
Sent: Thursday, March 17, 2011 5:30 PM
To: M5 Developer List
Cc: Hsu, Lisa
Subject: Re: [m5-dev] changeset in m5: Ruby: expose a simple mod function in 
slicc int...

>        Ruby: expose a simple mod function in slicc interface.

I don't care too much, but why not just add % to the language itself?
That'd be pretty trivial to do.

  Nate


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Re: [m5-dev] Review Request: swig: get rid of m5.internal.random module (swig/random.i)

[Nathan Binkert]

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Ship it!


- Nathan


On 2011-03-17 17:39:34, Steve Reinhardt wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/595/
> ---
> 
> (Updated 2011-03-17 17:39:34)
> 
> 
> Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and 
> Nathan Binkert.
> 
> 
> Summary
> ---
> 
> swig: get rid of m5.internal.random module (swig/random.i)
> 
> Thanks to swig this was interfering with the standard Python
> random module.  The only function in that module was seed(),
> which erroneously called srand48().  Moved the function to
> m5.internal.core, renamed it seedRandom(), and made it call
> random_mt.init() instead.
> 
> 
> Diffs
> -
> 
>   src/python/SConscript e4b508942ecb 
>   src/python/swig/core.i e4b508942ecb 
>   src/python/swig/random.i e4b508942ecb 
> 
> Diff: http://reviews.m5sim.org/r/595/diff
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Steve
> 
>

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[m5-dev] Review Request: swig: get rid of m5.internal.random module (swig/random.i)

[Steve Reinhardt]

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---

Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan 
Binkert.


Summary
---

swig: get rid of m5.internal.random module (swig/random.i)

Thanks to swig this was interfering with the standard Python
random module.  The only function in that module was seed(),
which erroneously called srand48().  Moved the function to
m5.internal.core, renamed it seedRandom(), and made it call
random_mt.init() instead.


Diffs
-

  src/python/SConscript e4b508942ecb 
  src/python/swig/core.i e4b508942ecb 
  src/python/swig/random.i e4b508942ecb 

Diff: http://reviews.m5sim.org/r/595/diff


Testing
---


Thanks,

Steve

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Re: [m5-dev] changeset in m5: Ruby: expose a simple mod function in slicc int...

[nathan binkert]

>        Ruby: expose a simple mod function in slicc interface.

I don't care too much, but why not just add % to the language itself?
That'd be pretty trivial to do.

  Nate
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Re: [m5-dev] Review Request: ISA parser: Set up op_src_decl and op_dest_decl for pc operands.

[Ali Saidi]

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Ship it!


- Ali


On 2011-03-17 14:51:31, Gabe Black wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/587/
> ---
> 
> (Updated 2011-03-17 14:51:31)
> 
> 
> Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and 
> Nathan Binkert.
> 
> 
> Summary
> ---
> 
> ISA parser: Set up op_src_decl and op_dest_decl for pc operands.
> 
> 
> Diffs
> -
> 
>   src/arch/isa_parser.py 5138d1e453f1 
> 
> Diff: http://reviews.m5sim.org/r/587/diff
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Gabe
> 
>

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Re: [m5-dev] Review Request: O3: Tighten memory order violation checking to 16 bytes.

[Ali Saidi]

> On 2011-02-27 21:41:48, Gabe Black wrote:
> > Should we put an assert in there to make sure no access is bigger than 16 
> > bytes? Also what about unaligned accesses? I think those will be split on 
> > cache block boundaries which may be bigger or smaller than 16 bytes. We 
> > might have an access that spans from one 16 byte chunk to the next. These 
> > aren't really problems with this change, but it might make them easier to 
> > hit.
> > 
> > I'm assuming this had some effect on the regressions. Did things generally 
> > go faster, slower, etc.?

Not major changes, but things usually sped up a little bit.


- Ali


---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/520/#review915
---


On 2011-02-27 18:52:51, Ali Saidi wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/520/
> ---
> 
> (Updated 2011-02-27 18:52:51)
> 
> 
> Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and 
> Nathan Binkert.
> 
> 
> Summary
> ---
> 
> O3: Tighten memory order violation checking to 16 bytes.
> 
> The comment in the code suggests that the checking granularity should be 16
> bytes, however in reality the shift by 8 is 256 bytes which seems much
> larger than required.
> 
> 
> Diffs
> -
> 
>   src/cpu/o3/lsq_unit_impl.hh 9dc17725f795 
> 
> Diff: http://reviews.m5sim.org/r/520/diff
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Ali
> 
>

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[m5-dev] changeset in m5: Automated merge with ssh://h...@repo.m5sim.org/m5

[Ali Saidi]

changeset ed9c6b16e977 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=ed9c6b16e977
description:
Automated merge with ssh://h...@repo.m5sim.org/m5

diffstat:

 configs/common/Caches.py   
| 3 +
 configs/common/FSConfig.py 
|11 +-
 src/arch/alpha/predecoder.hh   
| 6 +
 src/arch/arm/insts/branch.hh   
| 1 +
 src/arch/arm/insts/macromem.cc 
|86 +-
 src/arch/arm/insts/macromem.hh 
|21 +
 src/arch/arm/insts/mem.hh  
| 8 +-
 src/arch/arm/intregs.hh
| 2 +
 src/arch/arm/isa.cc
|10 +
 src/arch/arm/isa/formats/fp.isa
| 2 +-
 src/arch/arm/isa/insts/branch.isa  
|35 +-
 src/arch/arm/isa/insts/ldr.isa 
|25 +-
 src/arch/arm/isa/insts/m5ops.isa   
| 6 +-
 src/arch/arm/isa/insts/macromem.isa
|84 +-
 src/arch/arm/isa/insts/mem.isa 
|25 +-
 src/arch/arm/isa/insts/misc.isa
|20 +-
 src/arch/arm/isa/insts/str.isa 
|14 +-
 src/arch/arm/isa/operands.isa  
| 6 +-
 src/arch/arm/isa/templates/branch.isa  
|37 +
 src/arch/arm/isa/templates/macromem.isa
|35 +
 src/arch/arm/isa/templates/mem.isa 
|24 +-
 src/arch/arm/isa/templates/pred.isa
|32 +
 src/arch/arm/linux/process.cc  
|34 +-
 src/arch/arm/linux/system.cc   
|24 +
 src/arch/arm/linux/system.hh   
|13 +
 src/arch/arm/miscregs.hh   
|17 +-
 src/arch/arm/predecoder.hh 
|13 +-
 src/arch/arm/types.hh  
|13 +
 src/arch/mips/predecoder.hh
| 6 +
 src/arch/power/predecoder.hh   
| 6 +
 src/arch/sparc/predecoder.hh   
| 7 +
 src/arch/x86/predecoder.hh 
| 6 +
 src/cpu/o3/comm.hh 
|57 +-
 src/cpu/o3/commit.hh   
| 3 +-
 src/cpu/o3/commit_impl.hh  
|28 +-
 src/cpu/o3/cpu.cc  
| 5 +-
 src/cpu/o3/fetch.hh
| 4 +-
 src/cpu/o3/fetch_impl.hh   
|15 +-
 src/cpu/o3/iew_impl.hh 
| 6 +-
 src/cpu/o3/lsq_unit_impl.hh
| 4 +-
 src/cpu/simple/atomic.cc   
| 3 +
 src/cpu/simple/timing.cc   
| 4 +
 src/cpu/static_inst.hh 
| 1 +
 src/dev/io_device.cc   
| 3 +
 src/kern/linux/events.cc   
|37 +
 src/kern/linux/events.hh   
|27 +
 src/mem/cache/BaseCache.py 
| 1 +
 src/mem/cache/base.cc  
| 1 +
 src/mem/cache/base.hh  
| 5 +
 src/mem/cache/cache_impl.hh
| 2 +-
 src/sim/pseudo_inst.cc 
|34 +
 src/sim/pseudo_inst.hh 
| 1 +
 src/sim/syscall_emul.cc

[m5-dev] changeset in m5: ARM: Update stats for the previous changes and ...

[Ali Saidi]

changeset d062791aad69 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=d062791aad69
description:
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.

diffstat:

 tests/SConscript   
|3 +-
 tests/configs/realview-o3.py   
|   99 +
 tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini  
|3 +
 tests/long/00.gzip/ref/arm/linux/o3-timing/simout  
|8 +-
 tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt   
|  782 
 tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini  
|2 +-
 tests/long/00.gzip/ref/arm/linux/simple-atomic/simout  
|   10 +-
 tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt   
|   36 +-
 tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini  
|5 +-
 tests/long/00.gzip/ref/arm/linux/simple-timing/simout  
|   10 +-
 tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt   
|  210 +-
 tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini  
|  950 ++
 tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr  
|   43 +
 tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout  
|   16 +
 tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt   
|  750 +++
 tests/long/10.linux-boot/ref/arm/linux/realview-o3/status  
|1 +
 tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal 
|0 
 tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini   
|7 +-
 tests/long/10.mcf/ref/arm/linux/o3-timing/simout   
|   10 +-
 tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt
|  787 
 tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini   
|4 +-
 tests/long/10.mcf/ref/arm/linux/simple-atomic/simout   
|   10 +-
 tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt
|   36 +-
 tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini   
|7 +-
 tests/long/10.mcf/ref/arm/linux/simple-timing/simout   
|   10 +-
 tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt
|  182 +-
 tests/long/20.parser/ref/arm/linux/o3-timing/config.ini
|3 +
 tests/long/20.parser/ref/arm/linux/o3-timing/simout
|8 +-
 tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt 
|  782 
 tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini
|4 +-
 tests/long/20.parser/ref/arm/linux/simple-atomic/simout
|   10 +-
 tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt 
|   36 +-
 tests/long/20.parser/ref/arm/linux/simple-timing/config.ini
|7 +-
 tests/long/20.parser/ref/arm/linux/simple-timing/simout
|   10 +-
 tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt 
|  250 +-
 tests/long/30.eon/ref/arm/linux/o3-timing/config.ini   
|5 +-
 tests/long/30.eon/ref/arm/linux/o3-timing/simout   
|   12 +-
 tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt
|  773 
 tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini   
|2 +-
 tests/long/30.eon/ref/arm/linux/simple-atomic/simout   
|   10 +-
 tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt
|   36 +-
 tests/long/30.eon/ref/arm/linux/simple-timing/config.ini   
|5 +-
 tests/long/30.eon/ref/arm/linux/simple-timing/simout   
|   10 +-
 tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt
|  164 +-
 tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini   
|3 +
 tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout   
|8 +-
 tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
|  777 
 tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini   
|2 +-
 tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout   
|   10 +-
 tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
|   36 +-
 tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini   
|5 +-
 tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout   
|   10 +-
 tests/long/40.perlbmk/r

[m5-dev] changeset in m5: ARM: Add minimal ARM_SE support for m5threads.

[Chris Emmons]

changeset 12bd3ad81f9d in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=12bd3ad81f9d
description:
ARM: Add minimal ARM_SE support for m5threads.

Updated some of the assembly code sequences to use armv7 instructions 
and
coprocessor 15 for storing the TLS pointer.

diffstat:

 src/arch/arm/linux/process.cc |  34 --
 src/sim/syscall_emul.cc   |  14 ++
 src/sim/syscall_emul.hh   |   2 ++
 3 files changed, 36 insertions(+), 14 deletions(-)

diffs (141 lines):

diff -r 93982cb5044c -r 12bd3ad81f9d src/arch/arm/linux/process.cc
--- a/src/arch/arm/linux/process.cc Thu Mar 17 19:20:20 2011 -0500
+++ b/src/arch/arm/linux/process.cc Thu Mar 17 19:20:20 2011 -0500
@@ -197,7 +197,7 @@
 /* 117 */ SyscallDesc("ipc", unimplementedFunc),
 /* 118 */ SyscallDesc("fsync", unimplementedFunc),
 /* 119 */ SyscallDesc("sigreturn", unimplementedFunc),
-/* 120 */ SyscallDesc("clone", unimplementedFunc),
+/* 120 */ SyscallDesc("clone", cloneFunc),
 /* 121 */ SyscallDesc("setdomainname", unimplementedFunc),
 /* 122 */ SyscallDesc("uname", unameFunc),
 /* 123 */ SyscallDesc("unused#123", unimplementedFunc),
@@ -239,7 +239,7 @@
 /* 159 */ SyscallDesc("sched_get_priority_max", unimplementedFunc),
 /* 160 */ SyscallDesc("sched_get_priority_min", unimplementedFunc),
 /* 161 */ SyscallDesc("sched_rr_get_interval", unimplementedFunc),
-/* 162 */ SyscallDesc("nanosleep", unimplementedFunc),
+/* 162 */ SyscallDesc("nanosleep", ignoreWarnOnceFunc),
 /* 163 */ SyscallDesc("mremap", mremapFunc), // ARM-specific
 /* 164 */ SyscallDesc("setresuid", unimplementedFunc),
 /* 165 */ SyscallDesc("getresuid", unimplementedFunc),
@@ -251,8 +251,8 @@
 /* 171 */ SyscallDesc("getresgid", unimplementedFunc),
 /* 172 */ SyscallDesc("prctl", unimplementedFunc),
 /* 173 */ SyscallDesc("rt_sigreturn", unimplementedFunc),
-/* 174 */ SyscallDesc("rt_sigaction", ignoreFunc),
-/* 175 */ SyscallDesc("rt_sigprocmask", unimplementedFunc),
+/* 174 */ SyscallDesc("rt_sigaction", ignoreWarnOnceFunc),
+/* 175 */ SyscallDesc("rt_sigprocmask", ignoreWarnOnceFunc),
 /* 176 */ SyscallDesc("rt_sigpending", unimplementedFunc),
 /* 177 */ SyscallDesc("rt_sigtimedwait", unimplementedFunc),
 /* 178 */ SyscallDesc("rt_sigqueueinfo", ignoreFunc),
@@ -317,7 +317,7 @@
 /* 237 */ SyscallDesc("fremovexattr", unimplementedFunc),
 /* 238 */ SyscallDesc("tkill", unimplementedFunc),
 /* 239 */ SyscallDesc("sendfile64", unimplementedFunc),
-/* 240 */ SyscallDesc("futex", unimplementedFunc),
+/* 240 */ SyscallDesc("futex", ignoreWarnOnceFunc),
 /* 241 */ SyscallDesc("sched_setaffinity", unimplementedFunc),
 /* 242 */ SyscallDesc("sched_getaffinity", unimplementedFunc),
 /* 243 */ SyscallDesc("io_setup", unimplementedFunc),
@@ -456,6 +456,7 @@
 
 tc->getMemPort()->writeBlob(ArmLinuxProcess::commPage + 0x0ff0,
 (uint8_t *)&tlsPtr, sizeof(tlsPtr));
+tc->setMiscReg(MISCREG_TPIDRURO,tlsPtr);
 return 0;
 }
 
@@ -508,7 +509,7 @@
 ThreadContext *tc = system->getThreadContext(contextIds[0]);
 
 uint8_t swiNeg1[] = {
-0xff, 0xff, 0xff, 0xef  //swi -1
+0xff, 0xff, 0xff, 0xef  // swi -1
 };
 
 // Fill this page with swi -1 so we'll no if we land in it somewhere.
@@ -521,7 +522,8 @@
 // @todo Add a barrrier in this code
 uint8_t memory_barrier[] =
 {
-0x0e, 0xf0, 0xa0, 0xe1  //usr_ret lr
+0x5f, 0xf0, 0x7f, 0xf5, // dmb
+0x0e, 0xf0, 0xa0, 0xe1  // return
 };
 tc->getMemPort()->writeBlob(commPage + 0x0fa0, memory_barrier,
 sizeof(memory_barrier));
@@ -531,18 +533,22 @@
 // @todo replace this with ldrex/strex and dmb
 uint8_t cmpxchg[] =
 {
-0x00, 0x30, 0x92, 0xe5, //ldr r3, [r2]
-0x00, 0x30, 0x53, 0xe0, //subs r3, r3, r0
-0x00, 0x10, 0x82, 0x05, //streq r1, [r2]
-0x03, 0x00, 0xa0, 0xe1, //mov r0, r3
-0x0e, 0xf0, 0xa0, 0xe1  //usr_ret lr
+0x9f, 0x3f, 0x92, 0xe1,  // ldrexr3, [r2]
+0x00, 0x30, 0x53, 0xe0,  // subs r3, r3, r0
+0x91, 0x3f, 0x82, 0x01,  // strexeq  r3, r1, [r2]
+0x01, 0x00, 0x33, 0x03,  // teqeqr3, #1
+0xfa, 0xff, 0xff, 0x0a,  // beq 1b
+0x00, 0x00, 0x73, 0xe2,  // rsbs r0, r3, #0
+0x5f, 0xf0, 0x7f, 0xf5,  // dmb
+0x0e, 0xf0, 0xa0, 0xe1   // return
 };
 tc->getMemPort()->writeBlob(commPage + 0x0fc0, cmpxchg, sizeof(cmpxchg));
 
 uint8_t get_tls[] =
 {
-0x08, 0x00, 0x9f, 0xe5, //ldr r0, [pc, #(16 - 8)]
-0x0e, 0xf0, 0xa0, 0xe1  //usr_ret lr
+// read user read-only thread id register
+0x70, 0x0f, 0x1d, 0xee, // mrc p15, 0, r0, c13, c0, 3
+0x0e, 0xf0, 0xa0, 0xe1  // return
 };
 tc->getMemPort()->writeBlo

[m5-dev] changeset in m5: ARM: Fix subtle bug in LDM.

[Ali Saidi]

changeset 93982cb5044c in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=93982cb5044c
description:
ARM: Fix subtle bug in LDM.

If the instruction faults mid-op the base register shouldn't be written 
back.

diffstat:

 src/arch/arm/insts/macromem.cc  |  77 
 src/arch/arm/isa/insts/macromem.isa |  21 -
 src/cpu/static_inst.hh  |   1 +
 3 files changed, 68 insertions(+), 31 deletions(-)

diffs (204 lines):

diff -r ac8ef72e9700 -r 93982cb5044c src/arch/arm/insts/macromem.cc
--- a/src/arch/arm/insts/macromem.ccThu Mar 17 19:20:20 2011 -0500
+++ b/src/arch/arm/insts/macromem.ccThu Mar 17 19:20:20 2011 -0500
@@ -58,8 +58,13 @@
 {
 uint32_t regs = reglist;
 uint32_t ones = number_of_ones(reglist);
-// Remember that writeback adds a uop
-numMicroops = ones + (writeback ? 1 : 0) + 1;
+// Remember that writeback adds a uop or two and the temp register adds one
+numMicroops = ones + (writeback ? (load ? 2 : 1) : 0) + 1;
+
+// It's technically legal to do a lot of nothing
+if (!ones)
+numMicroops = 1;
+
 microOps = new StaticInstPtr[numMicroops];
 uint32_t addr = 0;
 
@@ -70,28 +75,13 @@
 addr += 4;
 
 StaticInstPtr *uop = microOps;
-StaticInstPtr wbUop;
-if (writeback) {
-if (up) {
-wbUop = new MicroAddiUop(machInst, rn, rn, ones * 4);
-} else {
-wbUop = new MicroSubiUop(machInst, rn, rn, ones * 4);
-}
-}
 
 // Add 0 to Rn and stick it in ureg0.
 // This is equivalent to a move.
 *uop = new MicroAddiUop(machInst, INTREG_UREG0, rn, 0);
 
-// Write back at the start for loads. This covers the ldm exception return
-// case where the base needs to be written in the old mode. Stores may need
-// the original value of the base, but they don't change mode and can
-// write back at the end like before.
-if (load && writeback) {
-*++uop = wbUop;
-}
-
 unsigned reg = 0;
+unsigned regIdx = 0;
 bool force_user = user & !bits(reglist, 15);
 bool exception_ret = user & bits(reglist, 15);
 
@@ -101,19 +91,28 @@
 reg++;
 replaceBits(regs, reg, 0);
 
-unsigned regIdx = reg;
+regIdx = reg;
 if (force_user) {
 regIdx = intRegInMode(MODE_USER, regIdx);
 }
 
 if (load) {
-if (reg == INTREG_PC && exception_ret) {
-// This must be the exception return form of ldm.
-*++uop = new MicroLdrRetUop(machInst, regIdx,
-   INTREG_UREG0, up, addr);
+if (writeback && i == ones - 1) {
+// If it's a writeback and this is the last register
+// do the load into a temporary register which we'll move
+// into the final one later
+*++uop = new MicroLdrUop(machInst, INTREG_UREG1, INTREG_UREG0,
+up, addr);
 } else {
-*++uop = new MicroLdrUop(machInst, regIdx,
-INTREG_UREG0, up, addr);
+// Otherwise just do it normally
+if (reg == INTREG_PC && exception_ret) {
+// This must be the exception return form of ldm.
+*++uop = new MicroLdrRetUop(machInst, regIdx,
+   INTREG_UREG0, up, addr);
+} else {
+*++uop = new MicroLdrUop(machInst, regIdx,
+INTREG_UREG0, up, addr);
+}
 }
 } else {
 *++uop = new MicroStrUop(machInst, regIdx, INTREG_UREG0, up, addr);
@@ -125,8 +124,32 @@
 addr -= 4;
 }
 
-if (!load && writeback) {
-*++uop = wbUop;
+if (writeback && ones) {
+// put the register update after we're done all loading
+if (up)
+*++uop = new MicroAddiUop(machInst, rn, rn, ones * 4);
+else
+*++uop = new MicroSubiUop(machInst, rn, rn, ones * 4);
+
+// If this was a load move the last temporary value into place
+// this way we can't take an exception after we update the base
+// register.
+if (load && reg == INTREG_PC && exception_ret) {
+*++uop = new MicroUopRegMovRet(machInst, 0, INTREG_UREG1);
+warn("creating instruction with exception return at curTick:%d\n",
+curTick());
+} else if (load) {
+*++uop = new MicroUopRegMov(machInst, regIdx, INTREG_UREG1);
+if (reg == INTREG_PC) {
+(*uop)->setFlag(StaticInstBase::IsControl);
+(*uop)->setFlag(StaticInstBase::IsCondControl);
+(*uop)->setFlag(StaticInstBase::IsIndirectControl);
+// This is created as a RAS POP
+if (rn == INTREG_S

[m5-dev] changeset in m5: ARM: Identify branches as conditional or uncond...

[Ali Saidi]

changeset 18368caa8489 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=18368caa8489
description:
ARM: Identify branches as conditional or unconditional and  direct or 
indirect.

diffstat:

 src/arch/arm/insts/branch.hh  |   1 +
 src/arch/arm/isa/insts/branch.isa |  35 ++--
 src/arch/arm/isa/templates/branch.isa |  37 +++
 src/arch/arm/predecoder.hh|   7 +++--
 src/arch/arm/types.hh |  13 
 5 files changed, 83 insertions(+), 10 deletions(-)

diffs (294 lines):

diff -r 21e4f3a569fb -r 18368caa8489 src/arch/arm/insts/branch.hh
--- a/src/arch/arm/insts/branch.hh  Thu Mar 17 19:20:20 2011 -0500
+++ b/src/arch/arm/insts/branch.hh  Thu Mar 17 19:20:20 2011 -0500
@@ -57,6 +57,7 @@
   int32_t _imm) :
 PredOp(mnem, _machInst, __opClass), imm(_imm)
 {}
+
 };
 
 // Conditionally Branch to a target computed with an immediate
diff -r 21e4f3a569fb -r 18368caa8489 src/arch/arm/isa/insts/branch.isa
--- a/src/arch/arm/isa/insts/branch.isa Thu Mar 17 19:20:20 2011 -0500
+++ b/src/arch/arm/isa/insts/branch.isa Thu Mar 17 19:20:20 2011 -0500
@@ -48,6 +48,8 @@
 bCode = '''
 NPC = (uint32_t)(PC + imm);
 '''
+br_tgt_code = '''pcs.instNPC(branchPC.instPC() + imm);'''
+instFlags = ["IsDirectControl"]
 if (link):
 bCode += '''
 if (Thumb)
@@ -55,12 +57,15 @@
 else
 LR = PC - 4;
 '''
+instFlags += ["IsCall"]
+
 
 bIop = InstObjParams(mnem, mnem.capitalize(), "BranchImmCond",
- {"code": bCode,
-  "predicate_test": predicateTest})
+ {"code": bCode, "predicate_test": predicateTest,
+ "brTgtCode" : br_tgt_code}, instFlags)
 header_output += BranchImmCondDeclare.subst(bIop)
-decoder_output += BranchImmCondConstructor.subst(bIop)
+decoder_output += BranchImmCondConstructor.subst(bIop) + \
+   BranchTarget.subst(bIop)
 exec_output += PredOpExecute.subst(bIop)
 
 # BX, BLX
@@ -81,15 +86,22 @@
 # Since we're switching ISAs, the target ISA will be the opposite
 # of the current ISA. Thumb is whether the target is ARM.
 newPC = '(Thumb ? (roundDown(PC, 4) + imm) : (PC + imm))'
+br_tgt_code = '''
+pcs.instNPC((branchPC.thumb() ? (roundDown(branchPC.instPC(),4) + 
imm) :
+(branchPC.instPC() + imm)));
+'''
 base = "BranchImmCond"
 declare = BranchImmCondDeclare
 constructor = BranchImmCondConstructor
+instFlags = ["IsDirectControl"]
 else:
 Name += "Reg"
 newPC = 'Op1'
+br_tgt_code = ''
 base = "BranchRegCond"
 declare = BranchRegCondDeclare
 constructor = BranchRegCondConstructor
+instFlags = ["IsIndirectControl"]
 if link and imm:
 linkStr = '''
 // The immediate version of the blx thumb instruction
@@ -100,6 +112,7 @@
 else
 LR = PC - 4;
 '''
+instFlags += ["IsCall"]
 elif link:
 linkStr = '''
 if (Thumb)
@@ -107,14 +120,18 @@
 else
 LR = PC - 4;
 '''
+instFlags += ["IsCall"]
 else:
 linkStr = ""
+instFlags += ["IsReturn"]
 
 if imm and link: #blx with imm
 branchStr = '''
 NextThumb = !Thumb;
 NPC = %(newPC)s;
 '''
+br_tgt_code = '''pcs.nextThumb(!branchPC.thumb());\n''' + \
+  br_tgt_code
 else:
 branchStr = "IWNPC = %(newPC)s;"
 branchStr = branchStr % { "newPC" : newPC }
@@ -123,11 +140,13 @@
   "newPC": newPC,
   "branch": branchStr}
 blxIop = InstObjParams(mnem, Name, base,
-   {"code": code,
-"predicate_test": predicateTest})
+   {"code": code, "brTgtCode" : br_tgt_code,
+"predicate_test": predicateTest}, instFlags)
 header_output += declare.subst(blxIop)
 decoder_output += constructor.subst(blxIop)
 exec_output += PredOpExecute.subst(blxIop)
+if imm:
+decoder_output += BranchTarget.subst(blxIop)
 
 #Ignore BXJ for now
 
@@ -136,7 +155,8 @@
 code = 'NPC = (uint32_t)(PC + imm);\n'
 predTest = "Op1 %(test)s 0" % {"test": test}
 iop = InstObjParams(mnem, mnem.capitalize(), "BranchImmReg",
-{"code": code, "pred

[m5-dev] changeset in m5: ARM: Implement the Instruction Set Attribute Re...

[Ali Saidi]

changeset ac8ef72e9700 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=ac8ef72e9700
description:
ARM: Implement the Instruction Set Attribute Registers (ISAR).

The ISAR registers describe which features the processor supports.
Transcribe the values listed in section B5.2.5 of the ARM ARM
into the registers as read-only values

diffstat:

 src/arch/arm/isa.cc  |  10 ++
 src/arch/arm/miscregs.hh |  17 -
 2 files changed, 18 insertions(+), 9 deletions(-)

diffs (65 lines):

diff -r 18368caa8489 -r ac8ef72e9700 src/arch/arm/isa.cc
--- a/src/arch/arm/isa.cc   Thu Mar 17 19:20:20 2011 -0500
+++ b/src/arch/arm/isa.cc   Thu Mar 17 19:20:20 2011 -0500
@@ -143,6 +143,16 @@
 
 miscRegs[MISCREG_CPACR] = 0;
 miscRegs[MISCREG_FPSID] = 0x410430A0;
+
+// See section B4.1.84 of ARM ARM
+// All values are latest for ARMv7-A profile
+miscRegs[MISCREG_ID_ISAR0] = 0x0110;
+miscRegs[MISCREG_ID_ISAR1] = 0x02112111;
+miscRegs[MISCREG_ID_ISAR2] = 0x21232141;
+miscRegs[MISCREG_ID_ISAR3] = 0x01112131;
+miscRegs[MISCREG_ID_ISAR4] = 0x10010142;
+miscRegs[MISCREG_ID_ISAR5] = 0x;
+
 //XXX We need to initialize the rest of the state.
 }
 
diff -r 18368caa8489 -r ac8ef72e9700 src/arch/arm/miscregs.hh
--- a/src/arch/arm/miscregs.hh  Thu Mar 17 19:20:20 2011 -0500
+++ b/src/arch/arm/miscregs.hh  Thu Mar 17 19:20:20 2011 -0500
@@ -165,6 +165,12 @@
 MISCREG_PMUSERENR,
 MISCREG_PMINTENSET,
 MISCREG_PMINTENCLR,
+MISCREG_ID_ISAR0,
+MISCREG_ID_ISAR1,
+MISCREG_ID_ISAR2,
+MISCREG_ID_ISAR3,
+MISCREG_ID_ISAR4,
+MISCREG_ID_ISAR5,
 MISCREG_CP15_UNIMP_START,
 MISCREG_TCMTR = MISCREG_CP15_UNIMP_START,
 MISCREG_ID_PFR1,
@@ -173,12 +179,6 @@
 MISCREG_ID_MMFR1,
 MISCREG_ID_MMFR2,
 MISCREG_ID_MMFR3,
-MISCREG_ID_ISAR0,
-MISCREG_ID_ISAR1,
-MISCREG_ID_ISAR2,
-MISCREG_ID_ISAR3,
-MISCREG_ID_ISAR4,
-MISCREG_ID_ISAR5,
 MISCREG_AIDR,
 MISCREG_ADFSR,
 MISCREG_AIFSR,
@@ -233,13 +233,12 @@
 "pmswinc", "pmselr", "pmceid0",
 "pmceid1", "pmc_other", "pmxevcntr",
 "pmuserenr", "pmintenset", "pmintenclr",
+"id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
  // Unimplemented below
 "tcmtr",
 "id_pfr1", "id_dfr0", "id_afr0",
 "id_mmfr1", "id_mmfr2", "id_mmfr3",
-"id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
-"aidr",
-"adfsr", "aifsr",
+"aidr", "adfsr", "aifsr",
 "dcimvac", "dcisw", "mccsw",
 "dccmvau",
 "nsacr",
___
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[m5-dev] changeset in m5: ARM: Bare metal system should have 256MB of RAM.

[Ali Saidi]

changeset 21e4f3a569fb in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=21e4f3a569fb
description:
ARM: Bare metal system should have 256MB of RAM.

diffstat:

 configs/common/FSConfig.py |  11 ++-
 1 files changed, 6 insertions(+), 5 deletions(-)

diffs (37 lines):

diff -r db0663be3f31 -r 21e4f3a569fb configs/common/FSConfig.py
--- a/configs/common/FSConfig.pyThu Mar 17 19:20:20 2011 -0500
+++ b/configs/common/FSConfig.pyThu Mar 17 19:20:20 2011 -0500
@@ -201,13 +201,8 @@
 self.membus = MemBus(bus_id=1)
 self.membus.badaddr_responder.warn_access = "warn"
 self.bridge = Bridge(delay='50ns', nack_delay='4ns')
-self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()), zero = True)
-self.diskmem = PhysicalMemory(range = AddrRange(Addr('128MB'), size = 
'128MB'),
-  file = disk('ael-arm.ext2'))
 self.bridge.side_a = self.iobus.port
 self.bridge.side_b = self.membus.port
-self.physmem.port = self.membus.port
-self.diskmem.port = self.membus.port
 
 self.mem_mode = mem_mode
 
@@ -232,13 +227,19 @@
 if bare_metal:
 # EOT character on UART will end the simulation
 self.realview.uart.end_on_eot = True
+self.physmem = PhysicalMemory(range = AddrRange(Addr('256MB')), zero = 
True)
 else:
+self.physmem = PhysicalMemory(range = AddrRange(Addr('128MB')), zero = 
True)
+self.diskmem = PhysicalMemory(range = AddrRange(Addr('128MB'), size = 
'128MB'),
+  file = disk('ael-arm.ext2'))
+self.diskmem.port = self.membus.port
 self.machine_type = machine_type
 self.kernel = binary('vmlinux.arm')
 self.boot_osflags = 'earlyprintk mem=128MB console=ttyAMA0' +  
\
 ' lpj=19988480 norandmaps slram=slram0,0x800,+0x800' + 
\
 ' mtdparts=slram0:- rw loglevel=8 root=/dev/mtdblock0'
 
+self.physmem.port = self.membus.port
 self.realview.attachOnChipIO(self.membus)
 self.realview.attachIO(self.iobus)
 
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[m5-dev] changeset in m5: ARM: Fix small bug with VLDM/VSTM instructions.

[Ali Saidi]

changeset db0663be3f31 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=db0663be3f31
description:
ARM: Fix small bug with VLDM/VSTM instructions.

diffstat:

 src/arch/arm/isa/formats/fp.isa |  2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diffs (12 lines):

diff -r b0b94a7b7c1f -r db0663be3f31 src/arch/arm/isa/formats/fp.isa
--- a/src/arch/arm/isa/formats/fp.isa   Thu Mar 17 19:20:20 2011 -0500
+++ b/src/arch/arm/isa/formats/fp.isa   Thu Mar 17 19:20:20 2011 -0500
@@ -143,7 +143,7 @@
  bits(machInst, 22) << 4);
 const uint32_t type = bits(machInst, 11, 8);
 uint32_t size = 0;
-uint32_t align = 0;
+uint32_t align = TLB::MustBeOne;
 unsigned inc = 1;
 unsigned regs = 1;
 unsigned lane = 0;
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[m5-dev] changeset in m5: ARM: Detect and skip udelay() functions in linu...

[Ali Saidi]

changeset b0b94a7b7c1f in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=b0b94a7b7c1f
description:
ARM: Detect and skip udelay() functions in linux kernel.

This change speeds up booting, especially in MP cases, by not executing
udelay() on the core but instead skipping ahead tha amount of time that 
is being
delayed.

diffstat:

 src/arch/arm/linux/system.cc |  24 
 src/arch/arm/linux/system.hh |  13 +
 src/cpu/simple/atomic.cc |   3 +++
 src/cpu/simple/timing.cc |   4 
 src/kern/linux/events.cc |  25 +
 src/kern/linux/events.hh |  27 +++
 6 files changed, 96 insertions(+), 0 deletions(-)

diffs (183 lines):

diff -r e08035e1a1f6 -r b0b94a7b7c1f src/arch/arm/linux/system.cc
--- a/src/arch/arm/linux/system.cc  Thu Mar 17 19:20:20 2011 -0500
+++ b/src/arch/arm/linux/system.cc  Thu Mar 17 19:20:20 2011 -0500
@@ -47,9 +47,11 @@
 #include "base/loader/object_file.hh"
 #include "base/loader/symtab.hh"
 #include "cpu/thread_context.hh"
+#include "kern/linux/events.hh"
 #include "mem/physical.hh"
 
 using namespace ArmISA;
+using namespace Linux;
 
 LinuxArmSystem::LinuxArmSystem(Params *p)
 : ArmSystem(p)
@@ -96,6 +98,24 @@
 if (!kernelPanicEvent)
 panic("could not find kernel symbol \'panic\'");
 #endif
+
+// With ARM udelay() is #defined to __udelay
+Addr addr = 0;
+if (kernelSymtab->findAddress("__udelay", addr)) {
+uDelaySkipEvent = new UDelayEvent(&pcEventQueue, "__udelay",
+fixFuncEventAddr(addr), 1000, 0);
+} else {
+panic("couldn't find kernel symbol \'udelay\'");
+}
+
+// constant arguments to udelay() have some precomputation done ahead of
+// time. Constant comes from code.
+if (kernelSymtab->findAddress("__const_udelay", addr)) {
+constUDelaySkipEvent = new UDelayEvent(&pcEventQueue, "__const_udelay",
+fixFuncEventAddr(addr), 1000, 107374);
+} else {
+panic("couldn't find kernel symbol \'udelay\'");
+}
 }
 
 void
@@ -115,6 +135,10 @@
 
 LinuxArmSystem::~LinuxArmSystem()
 {
+if (uDelaySkipEvent)
+delete uDelaySkipEvent;
+if (constUDelaySkipEvent)
+delete constUDelaySkipEvent;
 }
 
 LinuxArmSystem *
diff -r e08035e1a1f6 -r b0b94a7b7c1f src/arch/arm/linux/system.hh
--- a/src/arch/arm/linux/system.hh  Thu Mar 17 19:20:20 2011 -0500
+++ b/src/arch/arm/linux/system.hh  Thu Mar 17 19:20:20 2011 -0500
@@ -74,6 +74,19 @@
 /** Event to halt the simulator if the kernel calls panic()  */
 BreakPCEvent *kernelPanicEvent;
 #endif
+/**
+ * PC based event to skip udelay() calls and quiesce the
+ * processor for the appropriate amount of time. This is not functionally
+ * required but does speed up simulation.
+ */
+Linux::UDelayEvent *uDelaySkipEvent;
+
+/** Another PC based skip event for const_udelay(). Similar to the udelay
+ * skip, but this function precomputes the first multiply that is done
+ * in the generic case since the parameter is known at compile time.
+ * Thus we need to do some division to get back to us.
+ */
+Linux::UDelayEvent *constUDelaySkipEvent;
 };
 
 #endif // __ARCH_ARM_LINUX_SYSTEM_HH__
diff -r e08035e1a1f6 -r b0b94a7b7c1f src/cpu/simple/atomic.cc
--- a/src/cpu/simple/atomic.cc  Thu Mar 17 19:20:20 2011 -0500
+++ b/src/cpu/simple/atomic.cc  Thu Mar 17 19:20:20 2011 -0500
@@ -641,6 +641,9 @@
 checkForInterrupts();
 
 checkPcEventQueue();
+// We must have just got suspended by a PC event
+if (_status == Idle)
+return;
 
 Fault fault = NoFault;
 
diff -r e08035e1a1f6 -r b0b94a7b7c1f src/cpu/simple/timing.cc
--- a/src/cpu/simple/timing.cc  Thu Mar 17 19:20:20 2011 -0500
+++ b/src/cpu/simple/timing.cc  Thu Mar 17 19:20:20 2011 -0500
@@ -714,6 +714,10 @@
 
 checkPcEventQueue();
 
+// We must have just got suspended by a PC event
+if (_status == Idle)
+return;
+
 TheISA::PCState pcState = thread->pcState();
 bool needToFetch = !isRomMicroPC(pcState.microPC()) && !curMacroStaticInst;
 
diff -r e08035e1a1f6 -r b0b94a7b7c1f src/kern/linux/events.cc
--- a/src/kern/linux/events.cc  Thu Mar 17 19:20:20 2011 -0500
+++ b/src/kern/linux/events.cc  Thu Mar 17 19:20:20 2011 -0500
@@ -44,11 +44,13 @@
 #include 
 
 #include "base/trace.hh"
+#include "arch/utility.hh"
 #include "cpu/thread_context.hh"
 #include "kern/linux/events.hh"
 #include "kern/linux/printk.hh"
 #include "kern/system_events.hh"
 #include "sim/arguments.hh"
+#include "sim/pseudo_inst.hh"
 #include "sim/system.hh"
 
 namespace Linux {
@@ -66,4 +68,27 @@
 SkipFuncEvent::process(tc);
 }
 
+void
+UDelayEvent::process(ThreadContext *tc)
+{
+int arg_num  = 0;
+
+// Get the time in native size
+uint64_t time = TheISA::getArgument(tc, arg_num,  (uint16_t)-1, false);
+
+// convert par

[m5-dev] changeset in m5: ARM: Allow conditional quiesce instructions.

[Ali Saidi]

changeset e08035e1a1f6 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=e08035e1a1f6
description:
ARM: Allow conditional quiesce instructions.

This patch prevents not executed conditional instructions marked as
IsQuiesce from stalling the pipeline indefinitely. If the instruction
is not executed the quiesceSkip psuedoinst is called which schedules a
wakes up call to the fetch stage.

diffstat:

 src/arch/arm/isa/insts/m5ops.isa|   6 +++---
 src/arch/arm/isa/insts/misc.isa |  20 +---
 src/arch/arm/isa/templates/pred.isa |  32 
 src/sim/pseudo_inst.cc  |  34 ++
 src/sim/pseudo_inst.hh  |   1 +
 5 files changed, 83 insertions(+), 10 deletions(-)

diffs (190 lines):

diff -r ce34f14c1f43 -r e08035e1a1f6 src/arch/arm/isa/insts/m5ops.isa
--- a/src/arch/arm/isa/insts/m5ops.isa  Thu Mar 17 19:20:20 2011 -0500
+++ b/src/arch/arm/isa/insts/m5ops.isa  Thu Mar 17 19:20:20 2011 -0500
@@ -66,7 +66,7 @@
  ["IsNonSpeculative", "IsQuiesce"])
 header_output += BasicDeclare.subst(quiesceIop)
 decoder_output += BasicConstructor.subst(quiesceIop)
-exec_output += PredOpExecute.subst(quiesceIop)
+exec_output += QuiescePredOpExecute.subst(quiesceIop)
 
 quiesceNsCode = '''
 #if FULL_SYSTEM
@@ -80,7 +80,7 @@
  ["IsNonSpeculative", "IsQuiesce"])
 header_output += BasicDeclare.subst(quiesceNsIop)
 decoder_output += BasicConstructor.subst(quiesceNsIop)
-exec_output += PredOpExecute.subst(quiesceNsIop)
+exec_output += QuiescePredOpExecute.subst(quiesceNsIop)
 
 quiesceCyclesCode = '''
 #if FULL_SYSTEM
@@ -94,7 +94,7 @@
  ["IsNonSpeculative", "IsQuiesce", 
"IsUnverifiable"])
 header_output += BasicDeclare.subst(quiesceCyclesIop)
 decoder_output += BasicConstructor.subst(quiesceCyclesIop)
-exec_output += PredOpExecute.subst(quiesceCyclesIop)
+exec_output += QuiescePredOpExecute.subst(quiesceCyclesIop)
 
 quiesceTimeCode = '''
 #if FULL_SYSTEM
diff -r ce34f14c1f43 -r e08035e1a1f6 src/arch/arm/isa/insts/misc.isa
--- a/src/arch/arm/isa/insts/misc.isa   Thu Mar 17 19:20:20 2011 -0500
+++ b/src/arch/arm/isa/insts/misc.isa   Thu Mar 17 19:20:20 2011 -0500
@@ -491,10 +491,13 @@
 
 wfeCode = '''
 #if FULL_SYSTEM
-if (SevMailbox)
+if (SevMailbox) {
 SevMailbox = 0;
-else
+PseudoInst::quiesceSkip(xc->tcBase());
+}
+else {
 PseudoInst::quiesce(xc->tcBase());
+}
 #endif
 '''
 wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \
@@ -502,7 +505,7 @@
 ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"])
 header_output += BasicDeclare.subst(wfeIop)
 decoder_output += BasicConstructor.subst(wfeIop)
-exec_output += PredOpExecute.subst(wfeIop)
+exec_output += QuiescePredOpExecute.subst(wfeIop)
 
 wfiCode = '''
 #if FULL_SYSTEM
@@ -511,22 +514,25 @@
 '''
 wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \
 { "code" : wfiCode, "predicate_test" : predicateTest },
-["IsNonSpeculative", "IsQuiesce"])
+["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"])
 header_output += BasicDeclare.subst(wfiIop)
 decoder_output += BasicConstructor.subst(wfiIop)
-exec_output += PredOpExecute.subst(wfiIop)
+exec_output += QuiescePredOpExecute.subst(wfiIop)
 
 sevCode = '''
 // Need a way for O3 to not scoreboard these accesses as pipe flushes.
+SevMailbox = 1;
 System *sys = xc->tcBase()->getSystemPtr();
 for (int x = 0; x < sys->numContexts(); x++) {
 ThreadContext *oc = sys->getThreadContext(x);
-oc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
+if (oc != xc->tcBase()) {
+oc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
+}
 }
 '''
 sevIop = InstObjParams("sev", "SevInst", "PredOp", \
 { "code" : sevCode, "predicate_test" : predicateTest },
-["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"])
+["IsNonSpeculative", "IsSquashAfter"])
 header_output += BasicDeclare.subst(sevIop)
 decoder_output += BasicConstructor.subst(sevIop)
 exec_output += PredOpExecute.subst(sevIop)
diff -r ce34f14c1f43 -r e08035e1a1f6 src/arch/arm/isa/templates/pred.isa
--- a/src/arch/arm/isa/templates/pred.isa   Thu Mar 17 19:20:20 2011 -0500
+++ b/src/arch/arm/isa/templates/pred.isa   Thu Mar 17 19:20:20 2011 -0500
@@ -170,6 +170,38 @@
 }
 }};
 
+def template QuiescePredOpExecute {{
+Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord 
*traceData) const
+{
+Fault fault = NoFault;
+uint64_t resTemp = 0;
+resTemp = resTemp;
+%(op_decl)s;
+%(op_rd)s;
+
+if (%(predicate_test)s)
+{
+%(code)s;
+if (fault == NoFault)
+  

[m5-dev] changeset in m5: ARM: Rename registers used as temporary state b...

[Matt Horsnell]

changeset 2b2efc67f6df in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=2b2efc67f6df
description:
ARM: Rename registers used as temporary state by microops.

diffstat:

 src/arch/arm/isa/insts/macromem.isa |  32 
 src/arch/arm/isa/operands.isa   |   6 +++---
 2 files changed, 19 insertions(+), 19 deletions(-)

diffs (156 lines):

diff -r f08692f2932e -r 2b2efc67f6df src/arch/arm/isa/insts/macromem.isa
--- a/src/arch/arm/isa/insts/macromem.isa   Thu Mar 17 19:20:19 2011 -0500
+++ b/src/arch/arm/isa/insts/macromem.isa   Thu Mar 17 19:20:19 2011 -0500
@@ -51,7 +51,7 @@
 microLdrUopIop = InstObjParams('ldr_uop', 'MicroLdrUop',
'MicroMemOp',
{'memacc_code': microLdrUopCode,
-'ea_code': 'EA = Rb + (up ? imm : -imm);',
+'ea_code': 'EA = URb + (up ? imm : -imm);',
 'predicate_test': predicateTest},
['IsMicroop'])
 
@@ -60,7 +60,7 @@
   'MicroMemOp',
   {'memacc_code': microLdrFpUopCode,
'ea_code': vfpEnabledCheckCode +
-   'EA = Rb + (up ? imm : -imm);',
+   'EA = URb + (up ? imm : -imm);',
'predicate_test': predicateTest},
   ['IsMicroop'])
 
@@ -69,7 +69,7 @@
   'MicroMemOp',
   {'memacc_code': microLdrFpUopCode,
'ea_code': vfpEnabledCheckCode + '''
-EA = Rb + (up ? imm : -imm) +
+EA = URb + (up ? imm : -imm) +
  (((CPSR)Cpsr).e ? 4 : 0);
 ''',
'predicate_test': predicateTest},
@@ -80,7 +80,7 @@
   'MicroMemOp',
   {'memacc_code': microLdrFpUopCode,
'ea_code': vfpEnabledCheckCode + '''
-EA = Rb + (up ? imm : -imm) -
+EA = URb + (up ? imm : -imm) -
  (((CPSR)Cpsr).e ? 4 : 0);
 ''',
'predicate_test': predicateTest},
@@ -101,16 +101,16 @@
   'MicroMemOp',
   {'memacc_code': microLdrRetUopCode,
'ea_code':
-  'EA = Rb + (up ? imm : -imm);',
+  'EA = URb + (up ? imm : -imm);',
'predicate_test': condPredicateTest},
   
['IsMicroop','IsNonSpeculative','IsSerializeAfter'])
 
-microStrUopCode = "Mem = cSwap(Ra.uw, ((CPSR)Cpsr).e);"
+microStrUopCode = "Mem = cSwap(URa.uw, ((CPSR)Cpsr).e);"
 microStrUopIop = InstObjParams('str_uop', 'MicroStrUop',
'MicroMemOp',
{'memacc_code': microStrUopCode,
 'postacc_code': "",
-'ea_code': 'EA = Rb + (up ? imm : -imm);',
+'ea_code': 'EA = URb + (up ? imm : -imm);',
 'predicate_test': predicateTest},
['IsMicroop'])
 
@@ -120,7 +120,7 @@
  {'memacc_code': microStrFpUopCode,
   'postacc_code': "",
   'ea_code': vfpEnabledCheckCode +
-   'EA = Rb + (up ? imm : -imm);',
+   'EA = URb + (up ? imm : -imm);',
   'predicate_test': predicateTest},
  ['IsMicroop'])
 
@@ -130,7 +130,7 @@
{'memacc_code': microStrFpUopCode,
 'postacc_code': "",
 'ea_code': vfpEnabledCheckCode + '''
- EA = Rb + (up ? imm : -imm) +
+ EA = URb + (up ? imm : -imm) +
   (((CPSR)Cpsr).e ? 4 : 0);
  ''',
 'predicate_test': predicateTest},
@@ -142,7 +142,7 @@
 

[m5-dev] changeset in m5: ARM: Fix RFE macrop.

[Matt Horsnell]

changeset 7449084b1612 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=7449084b1612
description:
ARM: Fix RFE macrop.

This changes the RFE macroop into 3 microops:

URa = [sp]; URb = [sp+4]; // load CPSR,PC values from stack
sp = sp + offset; // optionally auto-increment
PC = URa; CPSR = URb; // write to the PC and CPSR.

Importantly:
- writing to PC is handled in the last micro-op.
- loading occurs prior to state changes.

diffstat:

 src/arch/arm/insts/macromem.cc  |   9 
 src/arch/arm/insts/macromem.hh  |  21 +++
 src/arch/arm/insts/mem.hh   |   8 +-
 src/arch/arm/intregs.hh |   2 +
 src/arch/arm/isa/insts/ldr.isa  |  25 ---
 src/arch/arm/isa/insts/macromem.isa |  31 ++--
 src/arch/arm/isa/insts/mem.isa  |  25 +++---
 src/arch/arm/isa/templates/macromem.isa |  35 +
 src/arch/arm/isa/templates/mem.isa  |  24 ++
 9 files changed, 146 insertions(+), 34 deletions(-)

diffs (truncated from 339 to 300 lines):

diff -r 2b2efc67f6df -r 7449084b1612 src/arch/arm/insts/macromem.cc
--- a/src/arch/arm/insts/macromem.ccThu Mar 17 19:20:19 2011 -0500
+++ b/src/arch/arm/insts/macromem.ccThu Mar 17 19:20:19 2011 -0500
@@ -896,6 +896,15 @@
 }
 
 std::string
+MicroSetPCCPSR::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+std::stringstream ss;
+printMnemonic(ss);
+ss << "[PC,CPSR]";
+return ss.str();
+}
+
+std::string
 MicroIntMov::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
 std::stringstream ss;
diff -r 2b2efc67f6df -r 7449084b1612 src/arch/arm/insts/macromem.hh
--- a/src/arch/arm/insts/macromem.hhThu Mar 17 19:20:19 2011 -0500
+++ b/src/arch/arm/insts/macromem.hhThu Mar 17 19:20:19 2011 -0500
@@ -134,6 +134,27 @@
 {
 }
 };
+
+/**
+ * Microops of the form
+ * PC   = IntRegA
+ * CPSR = IntRegB
+ */
+class MicroSetPCCPSR : public MicroOp
+{
+protected:
+IntRegIndex ura, urb, urc;
+
+MicroSetPCCPSR(const char *mnem, ExtMachInst machInst, OpClass __opClass,
+   IntRegIndex _ura, IntRegIndex _urb, IntRegIndex _urc)
+: MicroOp(mnem, machInst, __opClass),
+  ura(_ura), urb(_urb), urc(_urc)
+{
+}
+
+std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
 /**
  * Microops of the form IntRegA = IntRegB
  */
diff -r 2b2efc67f6df -r 7449084b1612 src/arch/arm/insts/mem.hh
--- a/src/arch/arm/insts/mem.hh Thu Mar 17 19:20:19 2011 -0500
+++ b/src/arch/arm/insts/mem.hh Thu Mar 17 19:20:19 2011 -0500
@@ -97,14 +97,18 @@
 IntRegIndex base;
 AddrMode mode;
 bool wb;
-static const unsigned numMicroops = 2;
+IntRegIndex ura, urb, urc;
+static const unsigned numMicroops = 3;
 
 StaticInstPtr *uops;
 
 RfeOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
   IntRegIndex _base, AddrMode _mode, bool _wb)
 : MightBeMicro(mnem, _machInst, __opClass),
-  base(_base), mode(_mode), wb(_wb), uops(NULL)
+  base(_base), mode(_mode), wb(_wb),
+  ura(INTREG_UREG0), urb(INTREG_UREG1),
+  urc(INTREG_UREG2),
+  uops(NULL)
 {}
 
 virtual
diff -r 2b2efc67f6df -r 7449084b1612 src/arch/arm/intregs.hh
--- a/src/arch/arm/intregs.hh   Thu Mar 17 19:20:19 2011 -0500
+++ b/src/arch/arm/intregs.hh   Thu Mar 17 19:20:19 2011 -0500
@@ -110,6 +110,8 @@
 
 INTREG_ZERO, // Dummy zero reg since there has to be one.
 INTREG_UREG0,
+INTREG_UREG1,
+INTREG_UREG2,
 INTREG_CONDCODES,
 INTREG_FPCONDCODES,
 
diff -r 2b2efc67f6df -r 7449084b1612 src/arch/arm/isa/insts/ldr.isa
--- a/src/arch/arm/isa/insts/ldr.isaThu Mar 17 19:20:19 2011 -0500
+++ b/src/arch/arm/isa/insts/ldr.isaThu Mar 17 19:20:19 2011 -0500
@@ -67,7 +67,7 @@
 self.memFlags = ["ArmISA::TLB::MustBeOne"]
 self.codeBlobs = {"postacc_code" : ""}
 
-def emitHelper(self, base = 'Memory', wbDecl = None, instFlags = []):
+def emitHelper(self, base = 'Memory', wbDecl = None, instFlags = [], 
pcDecl = None):
 
 global header_output, decoder_output, exec_output
 
@@ -76,7 +76,8 @@
 (newHeader,
  newDecoder,
  newExec) = self.fillTemplates(self.name, self.Name, codeBlobs,
-   self.memFlags, instFlags, base, 
wbDecl)
+   self.memFlags, instFlags, base,
+   wbDecl, pcDecl)
 
 header_output += newHeader
 decoder_output += newDecoder
@@ -104,26 +105,18 @@
 wbDiff = 8
 accCode = '''
 CPSR cpsr = Cpsr;
-SCTLR sctlr = Sctlr;
-// Use the version of

[m5-dev] changeset in m5: Stats: Update the statistics for rfe patch.

[Ali Saidi]

changeset ce34f14c1f43 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=ce34f14c1f43
description:
Stats: Update the statistics for rfe patch.

diffstat:

 tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini|2 +-
 tests/long/00.gzip/ref/arm/linux/o3-timing/simout|8 +-
 tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt |   32 +-
 tests/long/20.parser/ref/arm/linux/o3-timing/config.ini  |4 +-
 tests/long/20.parser/ref/arm/linux/o3-timing/simout  |   10 +-
 tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt   |  150 +++---
 tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini |2 +-
 tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout |8 +-
 tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt  |   46 ++--
 tests/quick/00.hello/ref/arm/linux/o3-timing/simout  |8 +-
 tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt   |8 +-
 11 files changed, 139 insertions(+), 139 deletions(-)

diffs (truncated from 643 to 300 lines):

diff -r 7449084b1612 -r ce34f14c1f43 
tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini
--- a/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini Thu Mar 17 
19:20:19 2011 -0500
+++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini Thu Mar 17 
19:20:20 2011 -0500
@@ -493,7 +493,7 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/gzip
+executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/gzip
 gid=100
 input=cin
 max_stack_size=67108864
diff -r 7449084b1612 -r ce34f14c1f43 
tests/long/00.gzip/ref/arm/linux/o3-timing/simout
--- a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout Thu Mar 17 19:20:19 
2011 -0500
+++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout Thu Mar 17 19:20:20 
2011 -0500
@@ -5,11 +5,11 @@
 All Rights Reserved
 
 
-M5 compiled Feb 21 2011 14:34:16
-M5 revision b06fecbc6572 7972 default qtip tip ext/print_mem_more.patch
-M5 started Feb 21 2011 14:34:24
+M5 compiled Feb 22 2011 10:22:27
+M5 revision c70e4f3301ed 7980 default ext/rfe_stats_updates.patch qtip tip
+M5 started Feb 22 2011 10:22:49
 M5 executing on u200439-lin.austin.arm.com
-command line: build/ARM_SE/m5.opt -d 
build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing -re tests/run.py 
build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing
+command line: build/ARM_SE/m5.fast -d 
build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing -re tests/run.py 
build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing
 Global frequency set at 1 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
diff -r 7449084b1612 -r ce34f14c1f43 
tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt
--- a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt  Thu Mar 17 
19:20:19 2011 -0500
+++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt  Thu Mar 17 
19:20:20 2011 -0500
@@ -1,9 +1,9 @@
 
 -- Begin Simulation Statistics --
-host_inst_rate  84615   # 
Simulator instruction rate (inst/s)
-host_mem_usage 256696   # 
Number of bytes of host memory used
-host_seconds  7097.77   # 
Real time elapsed on the host
-host_tick_rate   30571310   # 
Simulator tick rate (ticks/s)
+host_inst_rate 123576   # 
Simulator instruction rate (inst/s)
+host_mem_usage 255024   # 
Number of bytes of host memory used
+host_seconds  4860.01   # 
Real time elapsed on the host
+host_tick_rate   44647688   # 
Simulator tick rate (ticks/s)
 sim_freq 1   # 
Frequency of simulated ticks
 sim_insts   600581343   # 
Number of instructions simulated
 sim_seconds  0.216988   # 
Number of seconds simulated
@@ -119,9 +119,9 @@
 system.cpu.dcache.total_refs208054728   # 
Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle   90723000   # 
Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks   394050   # 
number of writebacks
-system.cpu.decode.DECODE:BlockedCycles   84141897   # 
Number of cycles decode is blocked
-system.cpu.decode.DECODE:DecodedInsts   763381678   # 
Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 172755507   # 
Number of cycles decode is idle
+system.cpu.decode.DECODE:BlockedCycles   84141899

[m5-dev] changeset in m5: O3: Send instruction back to fetch on squash to...

[Ali Saidi]

changeset f08692f2932e in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=f08692f2932e
description:
O3: Send instruction back to fetch on squash to seed predecoder 
correctly.

diffstat:

 src/arch/alpha/predecoder.hh |   6 ++
 src/arch/arm/predecoder.hh   |   6 ++
 src/arch/mips/predecoder.hh  |   6 ++
 src/arch/power/predecoder.hh |   6 ++
 src/arch/sparc/predecoder.hh |   7 +++
 src/arch/x86/predecoder.hh   |   6 ++
 src/cpu/o3/cpu.cc|   5 +++--
 src/cpu/o3/fetch.hh  |   4 ++--
 src/cpu/o3/fetch_impl.hh |   5 -
 src/kern/linux/events.cc |  12 
 10 files changed, 58 insertions(+), 5 deletions(-)

diffs (171 lines):

diff -r 48371b9fb929 -r f08692f2932e src/arch/alpha/predecoder.hh
--- a/src/arch/alpha/predecoder.hh  Thu Mar 17 19:20:19 2011 -0500
+++ b/src/arch/alpha/predecoder.hh  Thu Mar 17 19:20:19 2011 -0500
@@ -76,6 +76,12 @@
 emiIsReady = false;
 }
 
+void
+reset(const ExtMachInst &old_emi)
+{
+reset();
+}
+
 // Use this to give data to the predecoder. This should be used
 // when there is control flow.
 void
diff -r 48371b9fb929 -r f08692f2932e src/arch/arm/predecoder.hh
--- a/src/arch/arm/predecoder.hhThu Mar 17 19:20:19 2011 -0500
+++ b/src/arch/arm/predecoder.hhThu Mar 17 19:20:19 2011 -0500
@@ -83,6 +83,12 @@
 predAddrValid = false;
 }
 
+void reset(const ExtMachInst &old_emi)
+{
+reset();
+itstate = old_emi.newItstate;
+}
+
 Predecoder(ThreadContext * _tc) :
 tc(_tc), data(0)
 {
diff -r 48371b9fb929 -r f08692f2932e src/arch/mips/predecoder.hh
--- a/src/arch/mips/predecoder.hh   Thu Mar 17 19:20:19 2011 -0500
+++ b/src/arch/mips/predecoder.hh   Thu Mar 17 19:20:19 2011 -0500
@@ -75,6 +75,12 @@
 emiIsReady = false;
 }
 
+void
+reset(const ExtMachInst &old_emi)
+{
+reset();
+}
+
 //Use this to give data to the predecoder. This should be used
 //when there is control flow.
 void
diff -r 48371b9fb929 -r f08692f2932e src/arch/power/predecoder.hh
--- a/src/arch/power/predecoder.hh  Thu Mar 17 19:20:19 2011 -0500
+++ b/src/arch/power/predecoder.hh  Thu Mar 17 19:20:19 2011 -0500
@@ -82,6 +82,12 @@
 emiIsReady = false;
 }
 
+void
+reset(const ExtMachInst &old_emi)
+{
+reset();
+}
+
 // Use this to give data to the predecoder. This should be used
 // when there is control flow.
 void
diff -r 48371b9fb929 -r f08692f2932e src/arch/sparc/predecoder.hh
--- a/src/arch/sparc/predecoder.hh  Thu Mar 17 19:20:19 2011 -0500
+++ b/src/arch/sparc/predecoder.hh  Thu Mar 17 19:20:19 2011 -0500
@@ -68,12 +68,19 @@
 }
 
 void process() {}
+
 void
 reset()
 {
 emiIsReady = false;
 }
 
+void
+reset(const ExtMachInst &old_emi)
+{
+reset();
+}
+
 // Use this to give data to the predecoder. This should be used
 // when there is control flow.
 void
diff -r 48371b9fb929 -r f08692f2932e src/arch/x86/predecoder.hh
--- a/src/arch/x86/predecoder.hhThu Mar 17 19:20:19 2011 -0500
+++ b/src/arch/x86/predecoder.hhThu Mar 17 19:20:19 2011 -0500
@@ -174,6 +174,12 @@
 state = ResetState;
 }
 
+void
+reset(const ExtMachInst &old_emi)
+{
+reset();
+}
+
 ThreadContext * getTC()
 {
 return tc;
diff -r 48371b9fb929 -r f08692f2932e src/cpu/o3/cpu.cc
--- a/src/cpu/o3/cpu.cc Thu Mar 17 19:20:19 2011 -0500
+++ b/src/cpu/o3/cpu.cc Thu Mar 17 19:20:19 2011 -0500
@@ -808,8 +808,9 @@
 }
 
 // Squash Throughout Pipeline
-InstSeqNum squash_seq_num = commit.rob->readHeadInst(tid)->seqNum;
-fetch.squash(0, squash_seq_num, tid);
+DynInstPtr inst = commit.rob->readHeadInst(tid);
+InstSeqNum squash_seq_num = inst->seqNum;
+fetch.squash(0, squash_seq_num, inst, tid);
 decode.squash(tid);
 rename.squash(squash_seq_num, tid);
 iew.squash(tid);
diff -r 48371b9fb929 -r f08692f2932e src/cpu/o3/fetch.hh
--- a/src/cpu/o3/fetch.hh   Thu Mar 17 19:20:19 2011 -0500
+++ b/src/cpu/o3/fetch.hh   Thu Mar 17 19:20:19 2011 -0500
@@ -312,8 +312,8 @@
  * remove any instructions that are not in the ROB. The source of this
  * squash should be the commit stage.
  */
-void squash(const TheISA::PCState &newPC,
-const InstSeqNum &seq_num, ThreadID tid);
+void squash(const TheISA::PCState &newPC, const InstSeqNum &seq_num,
+DynInstPtr &squashInst, ThreadID tid);
 
 /** Ticks the fetch stage, processing all inputs signals and fetching
  * as many instructions as possible.
diff -r 48371b9fb929 -r f08692f2932e src/cpu/o3/fetch_impl.hh
--- a/src/cpu/o3/fetch_impl.hh  Thu Mar 17 19:20:19 2011 -0500
+++ b/src/cpu/o3/fetch_impl.hh  Thu

[m5-dev] changeset in m5: O3: Cleanup the commitInfo comm struct.

[Ali Saidi]

changeset 48371b9fb929 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=48371b9fb929
description:
O3: Cleanup the commitInfo comm struct.

Get rid of unused members and use base types rather than derrived values
where possible to limit amount of state.

diffstat:

 src/cpu/o3/comm.hh|  57 +-
 src/cpu/o3/commit.hh  |   3 +-
 src/cpu/o3/commit_impl.hh |  28 ++-
 src/cpu/o3/fetch_impl.hh  |   7 +
 src/cpu/o3/iew_impl.hh|   6 +---
 5 files changed, 64 insertions(+), 37 deletions(-)

diffs (250 lines):

diff -r afcb66f4b964 -r 48371b9fb929 src/cpu/o3/comm.hh
--- a/src/cpu/o3/comm.hhThu Mar 17 19:20:19 2011 -0500
+++ b/src/cpu/o3/comm.hhThu Mar 17 19:20:19 2011 -0500
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2011 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2004-2006 The Regents of The University of Michigan
  * All rights reserved.
  *
@@ -123,7 +135,6 @@
 bool branchTaken;
 Addr mispredPC;
 TheISA::PCState nextPC;
-
 unsigned branchCount;
 };
 
@@ -151,29 +162,45 @@
 iewComm iewInfo[Impl::MaxThreads];
 
 struct commitComm {
-bool usedROB;
-unsigned freeROBEntries;
-bool emptyROB;
 
+/// For Decode, IEW, Rename, Fetch ///
 bool squash;
 bool robSquashing;
 
-bool branchMispredict;
-DynInstPtr mispredictInst;
-bool branchTaken;
-Addr mispredPC;
-TheISA::PCState pc;
-
+// For Fetch & IEW /
 // Represents the instruction that has either been retired or
 // squashed.  Similar to having a single bus that broadcasts the
 // retired or squashed sequence number.
 InstSeqNum doneSeqNum;
 
-//Just in case we want to do a commit/squash on a cycle
-//(necessary for multiple ROBs?)
-bool commitInsts;
-InstSeqNum squashSeqNum;
+// For Rename /
+// Rename should re-read number of free rob entries
+bool usedROB;
+// Notify Rename that the ROB is empty
+bool emptyROB;
+// Tell Rename how many free entries it has in the ROB
+unsigned freeROBEntries;
 
+
+/ For Fetch //
+// Provide fetch the instruction that mispredicted, if this
+// pointer is not-null a misprediction occured
+DynInstPtr mispredictInst;
+// Was the branch taken or not
+bool branchTaken;
+// The pc of the next instruction to execute. This is the next
+// instruction for a branch mispredict, but the same instruction for
+// order violation and the like
+TheISA::PCState pc;
+
+// Instruction that caused the a non-mispredict squash
+DynInstPtr squashInst;
+// If an interrupt is pending and fetch should stall
+bool interruptPending;
+// If the interrupt ended up being cleared before being handled
+bool clearInterrupt;
+
+ For IEW //
 // Communication specifically to the IQ to tell the IQ that it can
 // schedule a non-speculative instruction.
 InstSeqNum nonSpecSeqNum;
@@ -182,8 +209,6 @@
 bool uncached;
 DynInstPtr uncachedLoad;
 
-bool interruptPending;
-bool clearInterrupt;
 };
 
 commitComm commitInfo[Impl::MaxThreads];
diff -r afcb66f4b964 -r 48371b9fb929 src/cpu/o3/commit.hh
--- a/src/cpu/o3/commit.hh  Thu Mar 17 19:20:19 2011 -0500
+++ b/src/cpu/o3/commit.hh  Thu Mar 17 19:20:19 2011 -0500
@@ -262,7 +262,8 @@
  * instructions instead of the current instruction and doesn't
  * clean up various status bits about traps/tc writes pending.
  */
-void squashAfter(ThreadID tid, uint64_t squash_after_seq_num);
+void squashAfter(ThreadID tid, DynInstPtr &head_inst,
+uint64_t squash_after_seq_num);
 
 #if FULL_SYSTEM
 /** Handles processing an interrupt. */
diff -r afcb66f4b964 -r 48371b9fb929 src/cpu/o3/commit_impl.hh
--- a/src/cpu/o3/commit_impl.hh Thu Mar 17 19:20:19 2011 -0500
+++ b/src/cpu/o3/commit_impl.hh Thu Mar 17 19:20:19 2011 -0500
@@ -541,8 +541,8 @@
 // the ROB is in the process of squashing.
 toIEW->commitInfo[tid].robSquash

[m5-dev] changeset in m5: O3: Update regressions for mem block caching ch...

[Ali Saidi]

changeset bb2d04f0b8fb in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=bb2d04f0b8fb
description:
O3: Update regressions for mem block caching change.

diffstat:

 tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini |18 +-
 tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout |12 +-
 tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt  |  1732 
+-
 tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini  |16 +-
 tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout  |12 +-
 tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt   |   934 
++--
 6 files changed, 1367 insertions(+), 1357 deletions(-)

diffs (truncated from 3678 to 300 lines):

diff -r b01a51ff05fa -r bb2d04f0b8fb 
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini   
Thu Mar 17 19:20:19 2011 -0500
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini   
Thu Mar 17 19:20:19 2011 -0500
@@ -10,12 +10,12 @@
 children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus 
physmem simple_disk terminal toL2Bus tsunami
 boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
-console=/dist/m5/system/binaries/console
+console=/chips/pd/randd/dist/binaries/console
 init_param=0
-kernel=/dist/m5/system/binaries/vmlinux
+kernel=/chips/pd/randd/dist/binaries/vmlinux
 load_addr_mask=1099511627775
 mem_mode=timing
-pal=/dist/m5/system/binaries/ts_osfpal
+pal=/chips/pd/randd/dist/binaries/ts_osfpal
 physmem=system.physmem
 readfile=tests/halt.sh
 symbolfile=
@@ -142,6 +142,7 @@
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -440,6 +441,7 @@
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -573,6 +575,7 @@
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -871,6 +874,7 @@
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -922,7 +926,7 @@
 
 [system.disk0.image.child]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/chips/pd/randd/dist/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -942,7 +946,7 @@
 
 [system.disk2.image.child]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
+image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img
 read_only=true
 
 [system.intrctrl]
@@ -967,6 +971,7 @@
 block_size=64
 forward_snoops=false
 hash_delay=1
+is_top_level=true
 latency=5
 max_miss_count=0
 mshrs=20
@@ -998,6 +1003,7 @@
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=1
 max_miss_count=0
 mshrs=92
@@ -1068,7 +1074,7 @@
 
 [system.simple_disk.disk]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/chips/pd/randd/dist/disks/linux-latest.img
 read_only=true
 
 [system.terminal]
diff -r b01a51ff05fa -r bb2d04f0b8fb 
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout   Thu Mar 
17 19:20:19 2011 -0500
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout   Thu Mar 
17 19:20:19 2011 -0500
@@ -5,13 +5,13 @@
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 01:46:17
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 01:46:32
-M5 executing on burrito
+M5 compiled Mar 15 2011 18:10:57
+M5 revision ee89694ad8dc 8081 default 
ext/mem_block_transfer_O3_regressions.patch tip qtip
+M5 started Mar 15 2011 18:10:59
+M5 executing on u200439-lin.austin.arm.com
 command line: build/ALPHA_FS/m5.fast -d 
build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re 
tests/run.py 
build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual
 Global frequency set at 1 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux
+info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux
 info: Entering event queue @ 0.  Starting simulation...
 info: Launching CPU 1 @ 118370500
-Exiting @ tick 1900831034500 because m5_exit instruction encountered
+Exiting @ tick 1900831106500 because m5_exit instruction encountered
diff -r b01a51ff05fa -r bb2d04f0b8fb 
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
Thu Mar 17 19:20:19 2011 -0500
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
Thu Mar 17 19:20:19 2011 -0500
@@ -1,395 +1,395 @@
 
 -- Begin Simulation Statistics --
-host_inst_rate  67358   # 
Simulator instruction rate (inst/s)
-host_mem_usage   

[m5-dev] changeset in m5: ARM: Previous change didn't end up setting inst...

[Ali Saidi]

changeset afcb66f4b964 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=afcb66f4b964
description:
ARM: Previous change didn't end up setting instFlags, this does.

diffstat:

 src/arch/arm/isa/insts/str.isa |  14 --
 1 files changed, 8 insertions(+), 6 deletions(-)

diffs (38 lines):

diff -r bb2d04f0b8fb -r afcb66f4b964 src/arch/arm/isa/insts/str.isa
--- a/src/arch/arm/isa/insts/str.isaThu Mar 17 19:20:19 2011 -0500
+++ b/src/arch/arm/isa/insts/str.isaThu Mar 17 19:20:19 2011 -0500
@@ -222,7 +222,6 @@
 decConstBase = 'StoreExImm'
 basePrefix = 'MemoryExImm'
 nameFunc = staticmethod(storeImmClassName)
-instFlags = ['IsStoreConditional']
 
 def __init__(self, *args, **kargs):
 super(StoreImmEx, self).__init__(*args, **kargs)
@@ -302,7 +301,6 @@
 decConstBase = 'StoreExDImm'
 basePrefix = 'MemoryExDImm'
 nameFunc = staticmethod(storeDoubleImmClassName)
-instFlags = ['IsStoreConditional']
 
 def __init__(self, *args, **kargs):
 super(StoreDoubleImmEx, self).__init__(*args, **kargs)
@@ -370,10 +368,14 @@
 
 buildDoubleStores("strd")
 
-StoreImmEx("strex", False, True, False, size=4, flavor="exclusive").emit()
-StoreImmEx("strexh", False, True, False, size=2, flavor="exclusive").emit()
-StoreImmEx("strexb", False, True, False, size=1, flavor="exclusive").emit()
-StoreDoubleImmEx("strexd", False, True, False, flavor="exclusive").emit()
+StoreImmEx("strex", False, True, False, size=4, flavor="exclusive",
+   instFlags = ['IsStoreConditional']).emit()
+StoreImmEx("strexh", False, True, False, size=2, flavor="exclusive",
+   instFlags = ['IsStoreConditional']).emit()
+StoreImmEx("strexb", False, True, False, size=1, flavor="exclusive",
+   instFlags = ['IsStoreConditional']).emit()
+StoreDoubleImmEx("strexd", False, True, False, flavor="exclusive",
+   instFlags = ['IsStoreConditional']).emit()
 
 StoreImm("vstr", False, True, False, size=4, flavor="fp").emit()
 StoreImm("vstr", False, False, False, size=4, flavor="fp").emit()
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[m5-dev] changeset in m5: Mem: Fix issue with dirty block being lost when...

[Ali Saidi]

changeset b01a51ff05fa in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=b01a51ff05fa
description:
Mem: Fix issue with dirty block being lost when entire block 
transferred to non-cache.

This change fixes the problem for all the cases we actively use. If you 
want to try
more creative I/O device attachments (E.g. sharing an L2), this won't 
work. You
would need another level of caching between the I/O device and the cache
(which you actually need anyway with our current code to make sure 
writes
propagate). This is required so that you can mark the cache in between 
as
top level and it won't try to send ownership of a block to the I/O 
device.
Asserts have been added that should catch any issues.

diffstat:

 configs/common/Caches.py|  3 +++
 src/cpu/o3/fetch_impl.hh|  3 +++
 src/dev/io_device.cc|  3 +++
 src/mem/cache/BaseCache.py  |  1 +
 src/mem/cache/base.cc   |  1 +
 src/mem/cache/base.hh   |  5 +
 src/mem/cache/cache_impl.hh |  2 +-
 tests/configs/inorder-timing.py |  6 +-
 tests/configs/memtest.py|  1 +
 tests/configs/o3-timing-mp.py   |  1 +
 tests/configs/o3-timing.py  |  6 +-
 tests/configs/pc-simple-atomic.py   |  3 +++
 tests/configs/pc-simple-timing.py   |  1 +
 tests/configs/realview-simple-atomic.py |  1 +
 tests/configs/realview-simple-timing.py |  1 +
 tests/configs/simple-atomic-mp.py   |  1 +
 tests/configs/simple-timing-mp.py   |  1 +
 tests/configs/simple-timing.py  |  6 +-
 tests/configs/tsunami-o3-dual.py|  2 ++
 tests/configs/tsunami-o3.py |  2 ++
 tests/configs/tsunami-simple-atomic-dual.py |  2 ++
 tests/configs/tsunami-simple-atomic.py  |  2 ++
 tests/configs/tsunami-simple-timing-dual.py |  2 ++
 tests/configs/tsunami-simple-timing.py  |  2 ++
 24 files changed, 54 insertions(+), 4 deletions(-)

diffs (truncated from 368 to 300 lines):

diff -r 9f704aa10eb4 -r b01a51ff05fa configs/common/Caches.py
--- a/configs/common/Caches.py  Thu Mar 17 19:20:19 2011 -0500
+++ b/configs/common/Caches.py  Thu Mar 17 19:20:19 2011 -0500
@@ -34,6 +34,7 @@
 latency = '1ns'
 mshrs = 10
 tgts_per_mshr = 5
+is_top_level = True
 
 class L2Cache(BaseCache):
 assoc = 8
@@ -49,6 +50,7 @@
 mshrs = 10
 size = '1kB'
 tgts_per_mshr = 12
+is_top_level = True
 
 class IOCache(BaseCache):
 assoc = 8
@@ -58,3 +60,4 @@
 size = '1kB'
 tgts_per_mshr = 12
 forward_snoops = False
+is_top_level = True
diff -r 9f704aa10eb4 -r b01a51ff05fa src/cpu/o3/fetch_impl.hh
--- a/src/cpu/o3/fetch_impl.hh  Thu Mar 17 19:20:19 2011 -0500
+++ b/src/cpu/o3/fetch_impl.hh  Thu Mar 17 19:20:19 2011 -0500
@@ -112,6 +112,9 @@
 {
 DPRINTF(Fetch, "Received timing\n");
 if (pkt->isResponse()) {
+// We shouldn't ever get a block in ownership state
+assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted()));
+
 fetch->processCacheCompletion(pkt);
 }
 //else Snooped a coherence request, just return
diff -r 9f704aa10eb4 -r b01a51ff05fa src/dev/io_device.cc
--- a/src/dev/io_device.cc  Thu Mar 17 19:20:19 2011 -0500
+++ b/src/dev/io_device.cc  Thu Mar 17 19:20:19 2011 -0500
@@ -139,6 +139,9 @@
 assert(pendingCount >= 0);
 assert(state);
 
+// We shouldn't ever get a block in ownership state
+assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted()));
+
 state->numBytes += pkt->req->getSize();
 assert(state->totBytes >= state->numBytes);
 if (state->totBytes == state->numBytes) {
diff -r 9f704aa10eb4 -r b01a51ff05fa src/mem/cache/BaseCache.py
--- a/src/mem/cache/BaseCache.pyThu Mar 17 19:20:19 2011 -0500
+++ b/src/mem/cache/BaseCache.pyThu Mar 17 19:20:19 2011 -0500
@@ -48,6 +48,7 @@
 size = Param.MemorySize("capacity in bytes")
 forward_snoops = Param.Bool(True,
 "forward snoops from mem side to cpu side")
+is_top_level = Param.Bool(False, "Is this cache at the top level (e.g. 
L1)")
 subblock_size = Param.Int(0,
 "Size of subblock in IIC used for compression")
 tgts_per_mshr = Param.Int("max number of accesses per MSHR")
diff -r 9f704aa10eb4 -r b01a51ff05fa src/mem/cache/base.cc
--- a/src/mem/cache/base.cc Thu Mar 17 19:20:19 2011 -0500
+++ b/src/mem/cache/base.cc Thu Mar 17 19:20:19 2011 -0500
@@ -58,6 +58,7 @@
   hitLatency(p->latency),
   numTarget(p->tgts_per_mshr),
   forwardSnoops(p->forward_snoops),
+  isTopLevel(p->is_top_level),
   blocked(0),
   noTargetMSHR(NULL),
   missCount(p->max_miss_count),
diff -r 9f704aa10eb4 -r b01a51ff05fa src/mem/cache/base.hh
--- a/src/mem/cache/base.hh Thu Mar 17 19:20:19 201

[m5-dev] changeset in m5: O3: Fix unaligned stores when cache blocked

[Ali Saidi]

changeset 9f704aa10eb4 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=9f704aa10eb4
description:
O3: Fix unaligned stores when cache blocked

Without this change the a store can be issued to the cache multiple 
times.
If this case occurs when the l1 cache is out of mshrs (and thus blocked)
the processor will never make forward progress because each cycle it 
will
send a single request using the recently freed mshr and not completing 
the
multipart store. This will continue forever.

diffstat:

 src/cpu/o3/lsq_unit_impl.hh |  4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)

diffs (14 lines):

diff -r 2af262e73961 -r 9f704aa10eb4 src/cpu/o3/lsq_unit_impl.hh
--- a/src/cpu/o3/lsq_unit_impl.hh   Thu Mar 17 00:43:54 2011 -0400
+++ b/src/cpu/o3/lsq_unit_impl.hh   Thu Mar 17 19:20:19 2011 -0500
@@ -1103,7 +1103,9 @@
 dynamic_cast(retryPkt->senderState);
 
 // Don't finish the store unless this is the last packet.
-if (!TheISA::HasUnalignedMemAcc || !state->pktToSend) {
+if (!TheISA::HasUnalignedMemAcc || !state->pktToSend ||
+state->pendingPacket == retryPkt) {
+state->pktToSend = false;
 storePostSend(retryPkt);
 }
 retryPkt = NULL;
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[m5-dev] changeset in m5: Ruby: minor bugfix, line did not adhere to some...

[Lisa Hsu]

changeset b0ecadb07742 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=b0ecadb07742
description:
Ruby: minor bugfix, line did not adhere to some macro usage conventions.

diffstat:

 src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh |  2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diffs (12 lines):

diff -r 03f7df749b9d -r b0ecadb07742 
src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
--- a/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hhThu Mar 
17 17:01:41 2011 -0700
+++ b/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hhThu Mar 
17 17:08:35 2011 -0700
@@ -125,7 +125,7 @@
 inline NodeID
 L1CacheMachIDToProcessorNum(MachineID machID)
 {
-assert(machID.type == MachineType_L1Cache);
+assert(machID.type == MACHINETYPE_L1CACHE_ENUM);
 return machID.num;
 }
 
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[m5-dev] changeset in m5: Ruby: expose a simple mod function in slicc int...

[Lisa Hsu]

changeset 03f7df749b9d in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=03f7df749b9d
description:
Ruby: expose a simple mod function in slicc interface.

diffstat:

 src/mem/protocol/RubySlicc_Util.sm |  2 +-
 src/mem/ruby/slicc_interface/RubySlicc_Util.hh |  6 ++
 2 files changed, 7 insertions(+), 1 deletions(-)

diffs (23 lines):

diff -r 2af262e73961 -r 03f7df749b9d src/mem/protocol/RubySlicc_Util.sm
--- a/src/mem/protocol/RubySlicc_Util.smThu Mar 17 00:43:54 2011 -0400
+++ b/src/mem/protocol/RubySlicc_Util.smThu Mar 17 17:01:41 2011 -0700
@@ -55,4 +55,4 @@
 Address setOffset(Address addr, int offset);
 Address makeLineAddress(Address addr);
 int addressOffset(Address addr);
-
+int mod(int val, int mod);
diff -r 2af262e73961 -r 03f7df749b9d 
src/mem/ruby/slicc_interface/RubySlicc_Util.hh
--- a/src/mem/ruby/slicc_interface/RubySlicc_Util.hhThu Mar 17 00:43:54 
2011 -0400
+++ b/src/mem/ruby/slicc_interface/RubySlicc_Util.hhThu Mar 17 17:01:41 
2011 -0700
@@ -182,4 +182,10 @@
 return addr.getOffset();
 }
 
+inline int
+mod(int val, int mod)
+{
+return val % mod;
+}
+
 #endif // __MEM_RUBY_SLICC_INTERFACE_RUBYSLICCUTIL_HH__
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Re: [m5-dev] Ruby FS - DMA Controller problem?

[Beckmann, Brad]

Hi Malek/Korey,

The good news is that I've been able to dedicate a significant amount of time 
to this over the past  day or so and I've got a good handle on what is going on 
here.  

Why did it work before the block size patch?
- When the ChuckGenerator sees the block size is 0, it doesn't split up the 
request into multiple patches and sends the whole dma request at once.  That is 
fine because the DMASequencer splits the request into multiple requests and 
only responds to the dma port when the entire request is complete.

What is the current problem?
- When the ChuckGenerator sees the block size of 64, the dma port splits the 
request into 64-byte packets, effectively doing the same thing the dma 
sequencer does.  That in itself shouldn't break things...The DMA sequencer 
nacks all but the first 64-byte request of the dma transfer because it is 
designed to only handle one M5 packet at a time.  Eventually the first 64-byte 
packet completes and the RubyPort tells the dma port to retry the second 
packet.  The dma port does, but for some reason DMASequencer still nacks that 
second request.  I'm not quite sure why that is, but I'm sure I'll figure it 
out soon.  Once I do, I'll push a fix along with all the other fixes I've come 
across along this multi-day adventure.

Brad

> -Original Message-
> From: m5-dev-boun...@m5sim.org [mailto:m5-dev-boun...@m5sim.org]
> On Behalf Of Korey Sewell
> Sent: Thursday, March 17, 2011 3:10 PM
> To: Malek Musleh
> Cc: M5 Developer List
> Subject: Re: [m5-dev] Ruby FS - DMA Controller problem?
> 
> Hi Malek,
> Can you send your most recent trace showing what you described (if it isnt
> too big)? I havent observed the different request size errors, but I think I
> have observed the different PRD addresses on the first access (in the most
> recent changeset). I'll double check.
> 
> I was planning to post sometime soon what was the latest on my debugging
> efforts but a quick summary is that the PRD address gets set from a
> "BMI.DTP" register that eventually gets propagate through. I havent been
> able to verify if that is loaded from the kernel or some configuration
> parameter quite yet.
> 
> 
> I have a feeling it might be also linked with the timing simpleCpu
> > changes about handling split requests, although Alpha does not support
> > split requests, that is independent of the DMA transfers.
> >
> Are you sure it's a split request problem and not an uncacheable address
> thing? Or maybe it's some combo of both?
> 
> 
> >
> > Also, comparing Ruby Traces (with and without failing changeset) the
> > first PRD BaseAddr is consistent between them, but not consistent
> > between Ruby/M5. So the fact that the PRD BaseAddr is 'wrong' in the
> > one case does not prevent it from booting the Kernel.
> >
> That's an interesting observation. It would be nice to figure out why that
> address may or may not matter though.
> 
> 
> 
> >
> > Not really sure if that helps anymore.
> >
> > Malek
> >
> > On Tue, Mar 15, 2011 at 6:50 PM, Korey Sewell 
> wrote:
> > > Sorry for the confusion, I definitely "garbled up" some terminology.
> > >
> > > I meant that the M5 ran with the atomic model to compare with the
> > > timing Ruby model.
> > >
> > > M5-atomic maybe runs in 10-15 mins and then Ruby 20-30 mins.
> > >
> > > I am able to get the problem point in the Ruby simulation (bad DMA
> > access)
> > > in about 20 mins.
> > >
> > > I able to get to that same problem point in the M5-atomic mode in
> > > about
> > 10
> > > mins so as to see what to compare against and what values are being
> > > set/unset incorrectly.
> > >
> > >
> > >
> > > On Tue, Mar 15, 2011 at 6:22 PM, Beckmann, Brad
> > > > >wrote:
> > >
> > >> I'm confused.
> > >>
> > >> Korey, I thought this DMA problem only existed with Ruby?  If so,
> > >> how
> > were
> > >> you able to reproduce it using atomic mode?  Ruby does not work
> > >> with the atomic cpu model.
> > >>
> > >> Please clarify, thanks!
> > >>
> > >> Brad
> > >>
> > >> > -Original Message-
> > >> > From: m5-dev-boun...@m5sim.org [mailto:m5-dev-
> boun...@m5sim.org]
> > >> > On Behalf Of Korey Sewell
> > >> > Sent: Tuesday, March 15, 2011 12:09 PM
> > >> > To: M5 Developer List
> > >> > Subject: Re: [m5-dev] Ruby FS - DMA Controller problem?
> > >> >
> > >> > Hi Brad/Malek,
> > >> > I've been able to regenerate this error  in about 20mins now
> > >> > (instead
> > of
> > >> > hours) by running things in atomic mode. Not sure if that helps
> > >> > or
> > not...
> > >> >
> > >> > On Tue, Mar 15, 2011 at 3:03 PM, Beckmann, Brad
> > >> > wrote:
> > >> >
> > >> > > > How is that you are able to run the memtester in FS Mode?
> > >> > > > I see the ruby_mem_tester.py in /configs/example/ but it
> > >> > > > seems
> > that
> > >> > > > it is only configured for SE Mode as far as Ruby is concerned?
> > >> > >
> > >> > > I don't run it in FS mode.  Since the DMA bug manifests only
> > >> > > after hours of execution, I wanted to first verify that 

Re: [m5-dev] Review Request: X86 ioctl: Another patch from Vince Weaver

[Lisa Hsu]

Yes, you assume right.


On Thu, Mar 17, 2011 at 4:08 PM, nathan binkert  wrote:

> I assume that when you commit these, you'll put a proper message in and
> make the author vince (qref -u can set the username)
>
>   Nate
>
>
> On Thu, Mar 17, 2011 at 4:06 PM, Lisa Hsu  wrote:
>
>>This is an automatically generated e-mail. To reply, visit:
>> http://reviews.m5sim.org/r/589/
>>   Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and
>> Nathan Binkert.
>> By Lisa Hsu.
>> Description
>>
>> X86 ioctl:  Another patch from Vince Weaver
>>
>>   Diffs
>>
>>- src/arch/x86/linux/syscalls.cc (2e269d6fb3e6)
>>- src/sim/syscall_emul.hh (2e269d6fb3e6)
>>
>> View Diff 
>>
>
>
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Re: [m5-dev] Review Request: X86 ioctl: Another patch from Vince Weaver

[nathan binkert]

I assume that when you commit these, you'll put a proper message in and make
the author vince (qref -u can set the username)

  Nate

On Thu, Mar 17, 2011 at 4:06 PM, Lisa Hsu  wrote:

>This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/589/
>   Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and
> Nathan Binkert.
> By Lisa Hsu.
> Description
>
> X86 ioctl:  Another patch from Vince Weaver
>
>   Diffs
>
>- src/arch/x86/linux/syscalls.cc (2e269d6fb3e6)
>- src/sim/syscall_emul.hh (2e269d6fb3e6)
>
> View Diff 
>
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[m5-dev] Review Request: X86: fnstsw: Another patch from Vince Weaver

[Lisa Hsu]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/594/
---

Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan 
Binkert.


Summary
---

X86:  fnstsw: Another patch from Vince Weaver


Diffs
-

  src/arch/x86/isa/decoder/x87.isa 2e269d6fb3e6 
  src/arch/x86/isa/insts/x87/control/save_x87_status_word.py 2e269d6fb3e6 
  src/arch/x86/isa/operands.isa 2e269d6fb3e6 
  src/arch/x86/regs/misc.hh 2e269d6fb3e6 

Diff: http://reviews.m5sim.org/r/594/diff


Testing
---


Thanks,

Lisa

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[m5-dev] Review Request: X86: fsincos: Another patch from Vince Weaver

[Lisa Hsu]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/593/
---

Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan 
Binkert.


Summary
---

X86:  fsincos: Another patch from Vince Weaver


Diffs
-

  src/arch/x86/isa/decoder/x87.isa 2e269d6fb3e6 
  
src/arch/x86/isa/insts/x87/transcendental_functions/trigonometric_functions.py 
2e269d6fb3e6 
  src/arch/x86/isa/microops/fpop.isa 2e269d6fb3e6 

Diff: http://reviews.m5sim.org/r/593/diff


Testing
---


Thanks,

Lisa

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[m5-dev] Review Request: X86: haddps: Another patch from Vince Weaver

[Lisa Hsu]

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Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan 
Binkert.


Summary
---

X86:  haddps: Another patch from Vince Weaver


Diffs
-

  src/arch/x86/isa/decoder/two_byte_opcodes.isa 2e269d6fb3e6 
  
src/arch/x86/isa/insts/simd128/floating_point/arithmetic/horizontal_addition.py 
2e269d6fb3e6 

Diff: http://reviews.m5sim.org/r/592/diff


Testing
---


Thanks,

Lisa

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[m5-dev] Review Request: X86: rlimit: Another patch from Vince Weaver

[Lisa Hsu]

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Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan 
Binkert.


Summary
---

X86:  rlimit: Another patch from Vince Weaver


Diffs
-

  src/arch/x86/linux/linux.hh 2e269d6fb3e6 
  src/arch/x86/linux/syscalls.cc 2e269d6fb3e6 

Diff: http://reviews.m5sim.org/r/591/diff


Testing
---


Thanks,

Lisa

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[m5-dev] Review Request: X86: open flags: Another patch from Vince Weaver

[Lisa Hsu]

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Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan 
Binkert.


Summary
---

X86:  open flags: Another patch from Vince Weaver


Diffs
-

  src/arch/x86/linux/linux.hh 2e269d6fb3e6 

Diff: http://reviews.m5sim.org/r/590/diff


Testing
---


Thanks,

Lisa

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[m5-dev] Review Request: X86 ioctl: Another patch from Vince Weaver

[Lisa Hsu]

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Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan 
Binkert.


Summary
---

X86 ioctl:  Another patch from Vince Weaver


Diffs
-

  src/arch/x86/linux/syscalls.cc 2e269d6fb3e6 
  src/sim/syscall_emul.hh 2e269d6fb3e6 

Diff: http://reviews.m5sim.org/r/589/diff


Testing
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Thanks,

Lisa

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[m5-dev] Review Request: patch from Vince Weaver for review

[Lisa Hsu]

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Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan 
Binkert.


Summary
---

X86:  SE syscalls: patch from Vince Weaver for review


Diffs
-

  src/arch/x86/linux/syscalls.cc 2e269d6fb3e6 

Diff: http://reviews.m5sim.org/r/588/diff


Testing
---

I've done minimal testing on these, i.e. I've pushed them to a clean tree and 
run X86 SPEC2k6 binaries on them, some of which didn't work prior to the 
patches but now do.  Others remain broken.  Vince, however, has done lots of 
testing and basically needed these to run SPEC2K workloads to completion for 
his thesis.  In other words, I bet these patches are good, but not complete for 
the purposes of running SPEC2k6.


Thanks,

Lisa

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Re: [m5-dev] Ruby FS - DMA Controller problem?

[Korey Sewell]

Hi Malek,
Can you send your most recent trace showing what you described (if it isnt
too big)? I havent observed the different request size errors, but I think I
have observed the different PRD addresses on the first access (in the most
recent changeset). I'll double check.

I was planning to post sometime soon what was the latest on my debugging
efforts but a quick summary is that the PRD address gets set from a
"BMI.DTP" register that eventually gets propagate through. I havent been
able to verify if that is loaded from the kernel or some configuration
parameter quite yet.


I have a feeling it might be also linked with the timing simpleCpu
> changes about handling split requests, although Alpha does not support
> split requests, that is independent of the DMA transfers.
>
Are you sure it's a split request problem and not an uncacheable address
thing? Or maybe it's some combo of both?


>
> Also, comparing Ruby Traces (with and without failing changeset) the
> first PRD BaseAddr is consistent between them, but not consistent
> between Ruby/M5. So the fact that the PRD BaseAddr is 'wrong' in the
> one case does not prevent it from booting the Kernel.
>
That's an interesting observation. It would be nice to figure out why that
address may or may not matter though.



>
> Not really sure if that helps anymore.
>
> Malek
>
> On Tue, Mar 15, 2011 at 6:50 PM, Korey Sewell  wrote:
> > Sorry for the confusion, I definitely "garbled up" some terminology.
> >
> > I meant that the M5 ran with the atomic model to compare with the timing
> > Ruby model.
> >
> > M5-atomic maybe runs in 10-15 mins and then Ruby 20-30 mins.
> >
> > I am able to get the problem point in the Ruby simulation (bad DMA
> access)
> > in about 20 mins.
> >
> > I able to get to that same problem point in the M5-atomic mode in about
> 10
> > mins so as to see what to compare against and what values are being
> > set/unset incorrectly.
> >
> >
> >
> > On Tue, Mar 15, 2011 at 6:22 PM, Beckmann, Brad  >wrote:
> >
> >> I'm confused.
> >>
> >> Korey, I thought this DMA problem only existed with Ruby?  If so, how
> were
> >> you able to reproduce it using atomic mode?  Ruby does not work with the
> >> atomic cpu model.
> >>
> >> Please clarify, thanks!
> >>
> >> Brad
> >>
> >> > -Original Message-
> >> > From: m5-dev-boun...@m5sim.org [mailto:m5-dev-boun...@m5sim.org]
> >> > On Behalf Of Korey Sewell
> >> > Sent: Tuesday, March 15, 2011 12:09 PM
> >> > To: M5 Developer List
> >> > Subject: Re: [m5-dev] Ruby FS - DMA Controller problem?
> >> >
> >> > Hi Brad/Malek,
> >> > I've been able to regenerate this error  in about 20mins now (instead
> of
> >> > hours) by running things in atomic mode. Not sure if that helps or
> not...
> >> >
> >> > On Tue, Mar 15, 2011 at 3:03 PM, Beckmann, Brad
> >> > wrote:
> >> >
> >> > > > How is that you are able to run the memtester in FS Mode?
> >> > > > I see the ruby_mem_tester.py in /configs/example/ but it seems
> that
> >> > > > it is only configured for SE Mode as far as Ruby is concerned?
> >> > >
> >> > > I don't run it in FS mode.  Since the DMA bug manifests only after
> >> > > hours of execution, I wanted to first verify that the DMA protocol
> >> > > support was solid using the mem tester.  Somewhat surprisingly, I
> >> > > found several bugs in MOESI_CMP_directory's support of DMA.  It
> turns
> >> > > out that the initial DMA support in that protocol wasn't very well
> >> > > thought out.  Now I fixed those bugs, but since the DMA problem also
> >> > > arises with the MOESI_hammer protocol, I'm confident that my patches
> >> > don't fix the real problem.
> >> > >
> >> > > Brad
> >> > >
> >> > > ___
> >> > > m5-dev mailing list
> >> > > m5-dev@m5sim.org
> >> > > http://m5sim.org/mailman/listinfo/m5-dev
> >> > >
> >> >
> >> >
> >> >
> >> > --
> >> > - Korey
> >> > ___
> >> > m5-dev mailing list
> >> > m5-dev@m5sim.org
> >> > http://m5sim.org/mailman/listinfo/m5-dev
> >>
> >>
> >> ___
> >> m5-dev mailing list
> >> m5-dev@m5sim.org
> >> http://m5sim.org/mailman/listinfo/m5-dev
> >>
> >
> >
> >
> > --
> > - Korey
> > ___
> > m5-dev mailing list
> > m5-dev@m5sim.org
> > http://m5sim.org/mailman/listinfo/m5-dev
> >
>



-- 
- Korey
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[m5-dev] Review Request: ISA parser: Set up op_src_decl and op_dest_decl for pc operands.

[Gabe Black]

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Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan 
Binkert.


Summary
---

ISA parser: Set up op_src_decl and op_dest_decl for pc operands.


Diffs
-

  src/arch/isa_parser.py 5138d1e453f1 

Diff: http://reviews.m5sim.org/r/587/diff


Testing
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Thanks,

Gabe

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Re: [m5-dev] Ruby FS - DMA Controller problem?

[Malek Musleh]

Brad/Korey,

An Update of what I have seen.

I did notice that in the failing case, the DMASequencer would think
that the request is completed (length of request == 64) when in fact
it should be 8192. The 8192 reflects the byte sector size, but what is
interesting is that a DPRINTF(IdeIDisk) in ide_disk.cc right before it
fails indicates that the request length is 8192. So there is something
wrong with the transfer in the RubyPorts.

I have a feeling it might be also linked with the timing simpleCpu
changes about handling split requests, although Alpha does not support
split requests, that is independent of the DMA transfers.

Also, comparing Ruby Traces (with and without failing changeset) the
first PRD BaseAddr is consistent between them, but not consistent
between Ruby/M5. So the fact that the PRD BaseAddr is 'wrong' in the
one case does not prevent it from booting the Kernel.

Not really sure if that helps anymore.

Malek

On Tue, Mar 15, 2011 at 6:50 PM, Korey Sewell  wrote:
> Sorry for the confusion, I definitely "garbled up" some terminology.
>
> I meant that the M5 ran with the atomic model to compare with the timing
> Ruby model.
>
> M5-atomic maybe runs in 10-15 mins and then Ruby 20-30 mins.
>
> I am able to get the problem point in the Ruby simulation (bad DMA access)
> in about 20 mins.
>
> I able to get to that same problem point in the M5-atomic mode in about 10
> mins so as to see what to compare against and what values are being
> set/unset incorrectly.
>
>
>
> On Tue, Mar 15, 2011 at 6:22 PM, Beckmann, Brad wrote:
>
>> I'm confused.
>>
>> Korey, I thought this DMA problem only existed with Ruby?  If so, how were
>> you able to reproduce it using atomic mode?  Ruby does not work with the
>> atomic cpu model.
>>
>> Please clarify, thanks!
>>
>> Brad
>>
>> > -Original Message-
>> > From: m5-dev-boun...@m5sim.org [mailto:m5-dev-boun...@m5sim.org]
>> > On Behalf Of Korey Sewell
>> > Sent: Tuesday, March 15, 2011 12:09 PM
>> > To: M5 Developer List
>> > Subject: Re: [m5-dev] Ruby FS - DMA Controller problem?
>> >
>> > Hi Brad/Malek,
>> > I've been able to regenerate this error  in about 20mins now (instead of
>> > hours) by running things in atomic mode. Not sure if that helps or not...
>> >
>> > On Tue, Mar 15, 2011 at 3:03 PM, Beckmann, Brad
>> > wrote:
>> >
>> > > > How is that you are able to run the memtester in FS Mode?
>> > > > I see the ruby_mem_tester.py in /configs/example/ but it seems that
>> > > > it is only configured for SE Mode as far as Ruby is concerned?
>> > >
>> > > I don't run it in FS mode.  Since the DMA bug manifests only after
>> > > hours of execution, I wanted to first verify that the DMA protocol
>> > > support was solid using the mem tester.  Somewhat surprisingly, I
>> > > found several bugs in MOESI_CMP_directory's support of DMA.  It turns
>> > > out that the initial DMA support in that protocol wasn't very well
>> > > thought out.  Now I fixed those bugs, but since the DMA problem also
>> > > arises with the MOESI_hammer protocol, I'm confident that my patches
>> > don't fix the real problem.
>> > >
>> > > Brad
>> > >
>> > > ___
>> > > m5-dev mailing list
>> > > m5-dev@m5sim.org
>> > > http://m5sim.org/mailman/listinfo/m5-dev
>> > >
>> >
>> >
>> >
>> > --
>> > - Korey
>> > ___
>> > m5-dev mailing list
>> > m5-dev@m5sim.org
>> > http://m5sim.org/mailman/listinfo/m5-dev
>>
>>
>> ___
>> m5-dev mailing list
>> m5-dev@m5sim.org
>> http://m5sim.org/mailman/listinfo/m5-dev
>>
>
>
>
> --
> - Korey
> ___
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>
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Re: [m5-dev] get rid of swig/random.i?

[nathan binkert]

> In the short term, if all we want to expose is the seed function, could we
> rename it to something more specific (like seed_c_rand48()) and move it out
> of its own module to someplace like core.i?  I'd like to get this fixed ASAP
> and I really don't want to get bogged down in the internals of the
> auto-swigging code.

Sounds fine to me.  Though, I'd rather call it setRandomSeed or
something like that.

  Nate
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Re: [m5-dev] get rid of swig/random.i?

[Steve Reinhardt]

On Thu, Mar 17, 2011 at 9:58 AM, nathan binkert  wrote:

> We must at least keep a mechanism for seeding.  My guess is that the
> best thing to do is stop having an internal subpackage and prepending
> all internal stuff with _internal or _m5 or somethign like that. I
> could of course keep the old names by mucking with importer.py
>

In the short term, if all we want to expose is the seed function, could we
rename it to something more specific (like seed_c_rand48()) and move it out
of its own module to someplace like core.i?  I'd like to get this fixed ASAP
and I really don't want to get bogged down in the internals of the
auto-swigging code.

Steve
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Re: [m5-dev] get rid of swig/random.i?

[nathan binkert]

> The Python RNG is Mersenne Twister just like the one in src/base
> (http://docs.python.org/library/random.html).
Ok.  I'm alright with using the builtin one then, I just want a single
"m5" way to seed the RNG.  I was looking at random.i and all that it's
really there for is setting the seed.  I guess I mislead you in
previous conversations (since I hadn't gone back and looked at the
code before) and I never exposed the RNG itself.

> My issue right now is that the current random.i prevents you from using the
> official python random module, which is just plain broken.  I don't
> understand why it is broken; you'd think that having it in the m5.internal
> package would prevent them from interacting, but it doesn't.
I'm 99% sure that it's not random.py that is coliding but _random.so
is colliding with the C++ module that swig generates which is also
called _random.   My recollection is that there's no easy way to
change that.  We could try to figure out a way to change SWIG_name
(which we used to do), but I think that will break the automatically
generated random.py.  Another option is if we change all of the module
names from internal.foo to _m5_foo.  Those are much less likely to
collide.

> It could be fixed by renaming or (better) figuring out why the package
> isolation isn't working, but if all we have are hypotheses about possible
> scenarios where it might be useful in the future, and a recognition that
> even if the interference problem is fixed it might not be adequate, then I
> think we should just get rid of it now, and when someone actually has a need
> then we can put in something that addresses the actual problem at hand.
We must at least keep a mechanism for seeding.  My guess is that the
best thing to do is stop having an internal subpackage and prepending
all internal stuff with _internal or _m5 or somethign like that. I
could of course keep the old names by mucking with importer.py

  Nate
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Re: [m5-dev] get rid of swig/random.i?

[Steve Reinhardt]

On Wed, Mar 16, 2011 at 11:06 PM, nathan binkert  wrote:

> > Does anyone actually use it?
> In python, probably not.  I used it in EXTRAS at one point though for sure.
>
> > Would it really matter if we had two different
> > RNGs (one python and once C++) as long as we can seed both of them
> > reproducibly from a single input value?
> I don't know that the argument is overwhelming. The biggest concern is
> that we have a good RNG.  Bad RNGs are really bad to use.  The biggest
> problem is that we're already using several different RNGs.  Ruby and
> the testers don't use M5's RNG, but rather random()
>
> My reasoning for wanting to use only the RNG in src/base is that it's
> a proven, *very* good RNG and it would be the single canonical source
> for randomness.
>

The Python RNG is Mersenne Twister just like the one in src/base (
http://docs.python.org/library/random.html).

My issue right now is that the current random.i prevents you from using the
official python random module, which is just plain broken.  I don't
understand why it is broken; you'd think that having it in the m5.internal
package would prevent them from interacting, but it doesn't.

It could be fixed by renaming or (better) figuring out why the package
isolation isn't working, but if all we have are hypotheses about possible
scenarios where it might be useful in the future, and a recognition that
even if the interference problem is fixed it might not be adequate, then I
think we should just get rid of it now, and when someone actually has a need
then we can put in something that addresses the actual problem at hand.

Steve
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[m5-dev] Cron /z/m5/regression/do-regression quick

[Cron Daemon]

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 passed.
* 
build/SPA