# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1263536246 28800
# Node ID 01bab1b7fc3c1da1d60c386999ba940ed773bab5
# Parent b2581afcdf3c74326fb4f5732874fc2c9be252e3
ruby: Pass pc from the ruby tester
diff -r b2581afcdf3c -r 01bab1b7fc3c src/cpu/rubytest/Check.cc
--- a/src
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1263536247 28800
# Node ID c75f4c574f887fa9f03f74244508b802ec8ab085
# Parent 99684e867755307c35e3c61801a49352e2034e31
ruby: MI_example updates to use the new config system
diff -r 99684e867755 -r c75f4c574f88 configs/ruby
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1263536247 28800
# Node ID 69b0eb267a9b14f0b02e7114561e4c7de72c2785
# Parent f5f1581d5b7c5d3443cd0792ec20a8bddfc670d5
ruby: Made the RubyTester wakeup frequency configurable
diff -r f5f1581d5b7c -r 69b0eb267a9b configs
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1263536246 28800
# Node ID 4bacc747d0a2af5b86d133610118264837282987
# Parent 0cafcd0a9c15571a428675f50a6afe33c0277751
ruby: Added Cache and MemCntrl profiler calls
diff -r 0cafcd0a9c15 -r 4bacc747d0a2 src/mem/slicc/symbols
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1263536250 28800
# Node ID 69a46a488db7cd4dbcc6ec681c3dcd2ed549c225
# Parent c5104360b4a1dc8404138adbad93bb9d78b4bae5
ruby: Added a mesh topology
diff -r c5104360b4a1 -r 69a46a488db7 configs/common/Options.py
--- a/configs
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1263536245 28800
# Node ID 412eb04d0909c94debbe76e07665792e8a0a4a18
# Parent af3701615ac52dc6050d7898b83a2540400eac24
ruby: cleaned up ruby profilers
Cleaned up the ruby profilers by moving the memory controller profiling code
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1263536243 28800
# Node ID bedc07d1355b1d016e93c8a8831274895e5f3741
# Parent 00bb4cb54fa91a68709ce82a878d0b6a724c8950
ruby: Wrapped ruby events into m5 events
Wrapped ruby events using the m5 event object. Removed
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1263536244 28800
# Node ID a7113be39b6a4f7ec2398fd87518f49445b1e83f
# Parent bedc07d1355b1d016e93c8a8831274895e5f3741
ruby: Converted the sequencer deadlock event to m5 eventq
diff -r bedc07d1355b -r a7113be39b6a src/mem/ruby
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1263536248 28800
# Node ID 8f9794901524089b5b55ceb53f65545224228dfe
# Parent 09d89c2eddfe7d505233a4814e1f030917736ca9
ruby: MESI_CMP_directory updated to the new config system
diff -r 09d89c2eddfe -r 8f9794901524 configs/ruby
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1263536245 28800
# Node ID 5b8bb9745a6223711954bc629a514419d73cfa81
# Parent 908ff9da9c54903145f1fe5c97d791d590eb2066
ruby: added ruby stats print
Moved the previous rubymem stats print feature to ruby System so that ruby
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1263536247 28800
# Node ID 01c7f6873059e7daa8f7fd00e5c39cbf60c2e409
# Parent 061151fda49a35f2d8ba4a20d2ed159c9ed23493
ruby: fixed memory fetch bug for persistent requests
diff -r 061151fda49a -r 01c7f6873059 src/mem/protocol
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1263536245 28800
# Node ID af3701615ac52dc6050d7898b83a2540400eac24
# Parent 5b8bb9745a6223711954bc629a514419d73cfa81
ruby: Removed RubySystem::getNumberOfSequencers
removed the static function RubySystem
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1261412980 28800
# Node ID e1df8da6de6ac36ddcb421d7d88917c2d01d13db
# Parent 6171341ed54d519d97d1430049238e16d9e5d676
ruby: cleaned up ruby profilers
Cleaned up the ruby profilers by moving the memory controller profiling code
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1261412980 28800
# Node ID 72028d922af2e6b59d2ddde4004184dc1b6ea182
# Parent 16e1f3fa0e878080a2d2e6a22d313ced2518ea24
ruby: fixed MOESI_hammer data writebacks to the directory
diff -r 16e1f3fa0e87 -r 72028d922af2 src/mem
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1261413068 28800
# Node ID d2c75e1450a015d15032fe378b030509aabeb3df
# Parent 2bff56035b82240c99bf0db244d134100c40b8bf
m5: Added the function to set a request's Pc
diff -r 2bff56035b82 -r d2c75e1450a0 src/mem/request.hh
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1261413068 28800
# Node ID 54d3c8cb0b7a100769137d30256c3a9d2d9131d7
# Parent d2c75e1450a015d15032fe378b030509aabeb3df
ruby: added data print to ruby request
diff -r d2c75e1450a0 -r 54d3c8cb0b7a src/mem/ruby/libruby.cc
These patches include GEM5 fixes, RubyPort clean, and the addition of the
RubyTester.
Brad
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1261413067 28800
# Node ID 985b666fdbfc0b51ec4217d7e9b24c65a636413a
# Parent 2b2eb8881591bd418466cabcd2c855d9ea31dd7f
ruby: Fix for fucntional accesses by devices
Pio functional accesses from devices need direct access
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1261413068 28800
# Node ID 723e67a6cf3aef261c4bc800c5d21424d2371eef
# Parent 264849268ebbd0a50e121582fb184f97bc80438e
ruby: Added Cache and MemCntrl profiler calls
diff -r 264849268ebb -r 723e67a6cf3a src/mem/slicc/symbols
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1261412980 28800
# Node ID 2b2eb8881591bd418466cabcd2c855d9ea31dd7f
# Parent a69fcc6caa1ba560ded1c5cf86d0c6f419467f04
ruby: Cleaned up static members in RubyPort
Removed static members in RubyPort and removed the ruby request
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1261413068 28800
# Node ID 264849268ebbd0a50e121582fb184f97bc80438e
# Parent 54d3c8cb0b7a100769137d30256c3a9d2d9131d7
ruby: ruby request now copies data
Instead of just updating the data pointer, ruby request now copies
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1261412980 28800
# Node ID 39a01746c92648b1191135dfc3563f79a851aaa6
# Parent 72028d922af2e6b59d2ddde4004184dc1b6ea182
ruby: fixed dma_cntrl to dma_sequencer connection
Now the dma_cntrl/sequencer point to eachother similar
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1261412980 28800
# Node ID 16e1f3fa0e878080a2d2e6a22d313ced2518ea24
# Parent e1df8da6de6ac36ddcb421d7d88917c2d01d13db
ruby: Fix L1-L2 copying in MOESI_hammer
diff -r e1df8da6de6a -r 16e1f3fa0e87 src/mem/protocol/MOESI_hammer
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1261412980 28800
# Node ID a69fcc6caa1ba560ded1c5cf86d0c6f419467f04
# Parent 39a01746c92648b1191135dfc3563f79a851aaa6
ruby: Removed addLink print out from Topology.cc
diff -r 39a01746c926 -r a69fcc6caa1b src/mem/ruby/network
Here are the patches that will unify configuration and the event queue between
ruby and M5. Please let me know if you have any comments and/or suggestions
for improvement.
Brad
___
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m5-dev@m5sim.org
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1260657434 28800
# Node ID 5d3a90f0ef4c0f69f61fd262028a32fa5e632f8e
# Parent 8f73bf7c3c5e9d1cd8573b6db7975fefc9bda613
ruby: Make SLICC-generated objects SimObjects.
Add SLICC support for state-machine parameter defaults
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1260657436 28800
# Node ID d0e96be22141976017c9d11e942be11587b8e4e2
# Parent cae9a08951751d7556ee4cc37a29824e23848b65
ruby: cleaned up Ruby debug defaults
diff -r cae9a0895175 -r d0e96be22141 configs/example/memtest-ruby.py
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1260657437 28800
# Node ID 3c00a365603e5724aea9b87b4b730839ef78139a
# Parent efe0dabd91852d85b6301852dd9737fa5e8ee2f1
ruby: Removed the passing of dma sequencer
The dma sequencer doesn't need to be passed between ruby config
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1260657435 28800
# Node ID 1788fb1fa57c0b95f0ec58b991cbb503a98c276c
# Parent d5c731012d722a9b54373ed45600e9e978001ea9
ruby: Hook up network queues to SLICC-generated state machines.
diff -r d5c731012d72 -r 1788fb1fa57c
src
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1260657435 28800
# Node ID dcde9bc50b96aa1197e001486522a37cb18fd2f1
# Parent 05140b07714b6f591b3f511b7a3f076aae3d756b
ruby: Fixed the Sequencer init function
Removed the Sequencer init function so that the parent (RubyPort
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1260657435 28800
# Node ID e657fd802abe54b28a19e2c851e8b3f700b10293
# Parent f164db9baf4ad51cf790ea3b134fed28f4e3d026
ruby: Add support for generating topologies in Python.
diff -r f164db9baf4a -r e657fd802abe configs/example
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1260657435 28800
# Node ID 8b7cf38ad6de8a71ddcc3044abab28c7ec0d2599
# Parent dcde9bc50b96aa1197e001486522a37cb18fd2f1
ruby: Small fix to ruby debug defaults
diff -r dcde9bc50b96 -r 8b7cf38ad6de src/mem/ruby/common/Debug.py
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1260657437 28800
# Node ID 70be840d4d3d6c1e115c32379ff3c80068ef53f5
# Parent fa98d755bc7afb680785e9fb2cb711c42514b815
ruby: reorganized ruby python configuration
Reorganized ruby python configuration so that protocol and ruby
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1260657435 28800
# Node ID 1c05b3999b00f4bb3fc0558bf0304f8a5cf3a78a
# Parent c1b464b8baad8ab20030eb6b36859035c769122d
ruby: Wrapped ruby events into m5 events
Wrapped ruby events using the m5 event object. Removed
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1260657437 28800
# Node ID 2d19b51213922c91d5ca388835c8753750b73cbc
# Parent 3c00a365603e5724aea9b87b4b730839ef78139a
ruby: fixed Set.cc bug to allow zero sized sets
This is necessary for example when no dma sequencers
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1260657436 28800
# Node ID 20d225368dfe44492bde8b187f898311fb9b924e
# Parent 23ea85c0fc27eaa31f042bdc37238856ffc7769e
ruby: hit callback fix with the new config system
Made the static hit callback function public so
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1260657436 28800
# Node ID d9f2104b2c11b32657c6fd30623a2a881a6e93ed
# Parent 1e80abe5cdd5f3b768f040ed5b8f91bd65acf95e
ruby: Removed out_link_vec from Consumer
Removed the out_line_vec data structure from the Consumer. I'm
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1260657436 28800
# Node ID 9bc2d1989135d514762556074847b27e503eda04
# Parent d0e96be22141976017c9d11e942be11587b8e4e2
ruby: removed some commented out code
Removed some commented out code from the sequencer and system
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1260657437 28800
# Node ID efe0dabd91852d85b6301852dd9737fa5e8ee2f1
# Parent 70be840d4d3d6c1e115c32379ff3c80068ef53f5
ruby: FS support using the new configuration system
diff -r 70be840d4d3d -r efe0dabd9185 configs/common
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1260657437 28800
# Node ID fa98d755bc7afb680785e9fb2cb711c42514b815
# Parent d9f2104b2c11b32657c6fd30623a2a881a6e93ed
ruby: Added pio port support to Ruby Port
Added a pio port to RubyPort so that pio requests from the cpus
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1260657436 28800
# Node ID 1e80abe5cdd5f3b768f040ed5b8f91bd65acf95e
# Parent 9bc2d1989135d514762556074847b27e503eda04
ruby: Convered ruby tracing support usage of sequencer
Modified ruby's tracing support to no longer rely
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1260657437 28800
# Node ID d52040d526f6620587296985f441c824f6b352eb
# Parent a47f0bcef634e82f98f1f35f3aef3d08f8420d22
ruby: Removed RubySystem::getNumberOfSequencers
removed the static function RubySystem
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1260657435 28800
# Node ID 7cecf4257a724ff3ad529e48f2fd3f2c32872cf4
# Parent 1788fb1fa57c0b95f0ec58b991cbb503a98c276c
ruby: fixed dir_cntrl name in memtest-ruby.py
diff -r 1788fb1fa57c -r 7cecf4257a72 configs/example/memtest
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1260657435 28800
# Node ID 2811007a9adc2edc51fdd303909662a852186d52
# Parent 7cecf4257a724ff3ad529e48f2fd3f2c32872cf4
ruby: connects sm queues to the network
diff -r 7cecf4257a72 -r 2811007a9adc configs/example/memtest
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1260657436 28800
# Node ID 23ea85c0fc27eaa31f042bdc37238856ffc7769e
# Parent e68f680829daff5e16ea6d520c7302f7ed5055f9
ruby: Memory Controller Profiler with new config system
This patch includes a rather substantial change
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1260657435 28800
# Node ID f164db9baf4ad51cf790ea3b134fed28f4e3d026
# Parent 5d3a90f0ef4c0f69f61fd262028a32fa5e632f8e
ruby: Copy M5 Port code from RubyMemory to RubyPort.
diff -r 5d3a90f0ef4c -r f164db9baf4a src/mem/ruby
# HG changeset patch
# User Brad Beckmann brad.beckm...@amd.com
# Date 1258692765 28800
# Node ID 82a7e4e9aa90144a73d776264f21dcc49b64514b
# Parent 95c5697d202b33419c420096d8a74e3a8821a14e
Calls destructors on all M5 Sim Objects.
diff -r 95c5697d202b -r 82a7e4e9aa90 src/sim/main.cc
--- a/src/sim
IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Ron Dreslinski
+# Brad Beckmann
+
+import m5
+from m5.objects import *
+from m5.defines import buildEnv
+from m5.util import addToPath
+import os, optparse, sys
+addToPath('../common')
+addToPath('../../tests/configs/')
+import ruby_config
changeset 81e9d83f87c0 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=81e9d83f87c0
description:
ruby: Ruby debug print fixes.
diffstat:
2 files changed, 22 insertions(+), 10 deletions(-)
src/mem/ruby/common/Debug.cc | 31 +--
changeset a22a47e60c21 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=a22a47e60c21
description:
ruby: Ruby destruction fix.
diffstat:
5 files changed, 14 insertions(+), 6 deletions(-)
src/mem/ruby/common/DataBlock.hh |6 +-
changeset 5a879a3513dc in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=5a879a3513dc
description:
ruby: Ruby 64-bit address output fixes.
diffstat:
4 files changed, 16 insertions(+), 2 deletions(-)
src/mem/ruby/libruby.cc |6 ++
src/mem/ruby/libruby.hh
changeset 668d24eb6e0f in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=668d24eb6e0f
description:
ruby: Added more info to bridge error message
diffstat:
1 file changed, 3 insertions(+), 1 deletion(-)
src/mem/bridge.cc |4 +++-
diffs (14 lines):
diff -r
OF SUCH DAMAGE.
+#
+# Authors: Brad Beckmann
+
+#
+# Full system configuraiton for ruby
+#
+
+import os
+import optparse
+import sys
+from os.path import join as joinpath
+
+import m5
+from m5.defines import buildEnv
+from m5.objects import *
+from m5.util import addToPath, panic
+
+if not buildEnv
changeset 71b272bd988e in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=71b272bd988e
description:
ruby: included ruby config parameter ports per core
Slightly improved the major hack need to correctly assign the number of
ports
per core. CPUs have two
changeset c5401cb99aae in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=c5401cb99aae
description:
m5: Added isValidSrc and isValidDest calls to packet.hh
diffstat:
1 file changed, 2 insertions(+)
src/mem/packet.hh |2 ++
diffs (19 lines):
diff -r 71b272bd988e -r
changeset 630a3d0b7eb7 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=630a3d0b7eb7
description:
m5: Moved profile option since Simulation depends on it.
diffstat:
1 file changed, 1 insertion(+)
configs/common/Options.py |1 +
diffs (11 lines):
diff -r
changeset 5ea2e2b3b39f in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=5ea2e2b3b39f
description:
ruby: Fixed Directory memory destructor
diffstat:
1 file changed, 7 insertions(+), 4 deletions(-)
src/mem/ruby/system/DirectoryMemory.cc | 11 +++
diffs (22
changeset c2dfa12ea482 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=c2dfa12ea482
description:
ruby: getPort function fix
Fixed RubyMemory::getPort function to not pass in a -1 for the idx
parameter
diffstat:
1 file changed, 9 insertions(+)
changeset 01202c147598 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=01202c147598
description:
ruby: Added error check for openning the ruby config file
diffstat:
1 file changed, 7 insertions(+)
src/mem/rubymem.cc |7 +++
diffs (19 lines):
diff -r
changeset 788cdecedf9f in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=788cdecedf9f
description:
m5: fixed destructor to deschedule the tickEvent and event
diffstat:
1 file changed, 2 insertions(+)
src/dev/mc146818.cc |2 ++
diffs (12 lines):
diff -r c2dfa12ea482
changeset 554d84a850d6 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=554d84a850d6
description:
ruby: fixed dma mi example to work with multiple dma ports
diffstat:
4 files changed, 18 insertions(+), 11 deletions(-)
src/mem/protocol/MI_example-dir.sm | 24
changeset 62c628499cd4 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=62c628499cd4
description:
m5: removed master and slave deletions.
The unresolved destructor call caused a seg fault when called.
diffstat:
1 file changed, 2 deletions(-)
src/dev/ide_ctrl.cc
changeset db802ee94eb6 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=db802ee94eb6
description:
m5: Fixed bug in atomic cpu destructor
diffstat:
1 file changed, 3 insertions(+)
src/cpu/simple/atomic.cc |3 +++
diffs (13 lines):
diff -r 554d84a850d6 -r
changeset 463aab78c057 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=463aab78c057
description:
m5: Added option to take a checkpoint at the end of simulation
diffstat:
2 files changed, 6 insertions(+)
configs/common/Options.py|3 +++
changeset b3f2dfbe8006 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=b3f2dfbe8006
description:
ruby: slicc state machine error fixes
Added error messages when:
- a state does not exist in a machine's list of known states.
- an event does not
changeset 2d3fc2e6f368 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=2d3fc2e6f368
description:
ruby: slicc method error fix
Added error message when a method call is not supported by an object.
diffstat:
1 file changed, 3 insertions(+)
changeset 13387a838449 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=13387a838449
description:
ruby: cache configuration fix to use bytes
Changed cache size to be in bytes instead of kb so that testers can use
very
small caches and increase the chance
changeset bb675ba62c79 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=bb675ba62c79
description:
ruby: returns the number of LLC needed for broadcast
Added feature to CacheMemory to return the number of last level caches.
This count is need for broadcast
changeset 000fa68c57a9 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=000fa68c57a9
description:
ruby: added the original hammer protocols from old ruby
diffstat:
4 files changed, 1509 insertions(+)
src/mem/protocol/MOESI_hammer-cache.sm | 1104
OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * AMD's contributions to the MOESI hammer protocol do not constitute an
+ * endorsement of its similarity to any AMD products.
+ *
+ * Authors: Milo Martin
+ * Brad Beckmann
*/
-machine(L1Cache, AMD
changeset 53caf4b9186d in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=53caf4b9186d
description:
ruby: Added a memory controller feature to MOESI hammer
diffstat:
4 files changed, 224 insertions(+), 33 deletions(-)
src/mem/protocol/MOESI_hammer-dir.sm | 254
changeset 64b815f299c0 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=64b815f299c0
description:
m5: Added the default m5out directory to the hg ignore list
diffstat:
1 file changed, 1 insertion(+)
.hgignore |1 +
diffs (8 lines):
diff -r 71021368db4a -r
changeset bc8c8617c4f0 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=bc8c8617c4f0
description:
ruby: Added boolean to State Machine parameters
* * *
ruby: Removed primitive .hh includes
diffstat:
1 file changed, 6 insertions(+), 3 deletions(-)
changeset b431ec0ad43d in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=b431ec0ad43d
description:
ruby: added error message to isinstance check
Added error message when a symbol is not an instance of a particular
expected
type.
diffstat:
1 file changed,
changeset 394bc95d417b in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=394bc95d417b
description:
ruby: removed the chip pointer from MessageBuffer
The Chip object no longer exists and thus is removed from the
MessageBuffer
constructor.
diffstat:
3
changeset daf49a57df75 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=daf49a57df75
description:
m5: improvements to the ruby_fs.py file
diffstat:
1 file changed, 24 insertions(+), 5 deletions(-)
configs/example/ruby_fs.py | 29 -
diffs
changeset 7bf0a839c237 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=7bf0a839c237
description:
Resurrection of the CMP token protocol to GEM5
diffstat:
17 files changed, 1578 insertions(+), 336 deletions(-)
src/mem/protocol/MOESI_CMP_token-L1cache.sm | 351
changeset 289ac904233d in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=289ac904233d
description:
m5: refreshed the ruby memtest regression stats
diffstat:
6 files changed, 483 insertions(+), 556 deletions(-)
tests/configs/memtest-ruby.py
changeset 4dc4e494e4d8 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=4dc4e494e4d8
description:
fixed error message generation bug in SLICC ast files
diffstat:
7 files changed, 17 insertions(+), 17 deletions(-)
src/mem/slicc/ast/ChipComponentAccessAST.py |4 ++--
changeset a1d8c53d92b8 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=a1d8c53d92b8
description:
removed libruby file reference from ruby_se.py
diffstat:
1 file changed, 1 deletion(-)
configs/example/ruby_se.py |1 -
diffs (11 lines):
diff -r e93e6d7b48a0 -r
changeset b741b3e7164b in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=b741b3e7164b
description:
fixed MC146818 checkpointing bug and added isa serialization calls to
simple_thread
diffstat:
2 files changed, 28 insertions(+), 4 deletions(-)
src/cpu/simple_thread.cc |
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