* build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing passed.
* build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-atomic passed.
* build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/inorder-timing passed.
*
changeset 5a9a639ce16f in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=5a9a639ce16f
description:
debug: fix help output
diffstat:
src/base/debug.cc | 4 ++--
src/base/debug.hh | 16
src/python/m5/debug.py | 28
On 04/27/11 22:14, Gabe Black wrote:
My idea is to be able to inherit from the standard op types like
IntRegOperand and allow them to install more than one index and/or
change how they're declared, read, and written. So say for example you
had a 128 bit wide SIMD instruction operating on four
Note that running m5 --help still has the old names:
Trace Options
-
--trace-helpPrint help on trace flags
--trace-flags=FLAG[,FLAG]
Sets the flags for tracing (-FLAG disables a flag)
--trace-start=TIME Start tracing at TIME (must be in ticks)
I'm not sure. Something must have happened when I rebased my patch
queue. I believe all that needs to happen is delete the 4 lines
relating to --trace-help and --trace-flags. Can someone delete them
for me and make sure that M5 still runs correctly? I'm out of town
and I'm really not going to
On 2011-05-03 17:45:41, Brad Beckmann wrote:
Can we change the name of Time in base/time.hh instead of Time in Ruby?
Right now this patch touches 50+ Ruby files and a bunch of lines within
those files just to change Time to RTime. It seems that far fewer changes
would be required
On 2011-05-03 17:45:41, Brad Beckmann wrote:
Can we change the name of Time in base/time.hh instead of Time in Ruby?
Right now this patch touches 50+ Ruby files and a bunch of lines within
those files just to change Time to RTime. It seems that far fewer changes
would be required
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Ship it!
I'm surprised this wasn't fixed earlier. Thanks for do this
On 2011-05-03 17:45:41, Brad Beckmann wrote:
Can we change the name of Time in base/time.hh instead of Time in Ruby?
Right now this patch touches 50+ Ruby files and a bunch of lines within
those files just to change Time to RTime. It seems that far fewer changes
would be required
So --trace-start, --trace-ignore, and --trace-file didn't get renamed?
On Wed, May 4, 2011 at 4:21 PM, nathan binkert n...@binkert.org wrote:
I'm not sure. Something must have happened when I rebased my patch
queue. I believe all that needs to happen is delete the 4 lines
relating to
So --trace-start, --trace-ignore, and --trace-file didn't get renamed?
Yeah, the idea was that there was more to the flags than tracing, but
the start, ignore, and file things were specific to tracing.
Nate
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changeset 34d2cb97a7a8 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=34d2cb97a7a8
description:
ARM: Fix small bug with vcvt instruction
diffstat:
src/arch/arm/isa/formats/fp.isa | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diffs (14 lines):
diff -r
changeset 1d3733d3acee in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=1d3733d3acee
description:
ARM: Add vfpv3 support to native trace.
diffstat:
src/arch/arm/nativetrace.cc| 18 +++--
src/arch/arm/nativetrace.hh| 12 ++--
changeset a8c4b7a24d62 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=a8c4b7a24d62
description:
ARM: Add support for some more registers in the real view controller.
diffstat:
src/dev/arm/rv_ctrl.cc | 10 +-
src/dev/arm/rv_ctrl.hh | 7 +++
2 files
changeset 0cc4594abf28 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=0cc4594abf28
description:
ARM: Add snoop control unit device.
diffstat:
src/dev/arm/RealView.py |5 ++
src/dev/arm/SConscript |1 +
src/dev/arm/a9scu.cc| 102
changeset ea5a46abdcca in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=ea5a46abdcca
description:
ARM: Make GIC handle IPIs and multiple processors.
diffstat:
src/dev/arm/RealView.py |3 +-
src/dev/arm/gic.cc | 450
changeset 2fcad6253525 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=2fcad6253525
description:
ARM: Add support for MP misc regs and broadcast flushes.
diffstat:
src/arch/arm/isa.cc | 55 +++
src/arch/arm/miscregs.hh
changeset abc8ab4ddd93 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=abc8ab4ddd93
description:
ARM: Add support for loading the a bootloader and configuring
parameters for it
diffstat:
src/arch/arm/ArmSystem.py| 7 +
src/arch/arm/linux/system.cc | 13
changeset c38905a6fa32 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=c38905a6fa32
description:
ARM: Implement WFE/WFI/SEV semantics.
diffstat:
src/arch/arm/interrupts.hh | 13 +
src/arch/arm/isa/insts/data.isa | 1 +
changeset 45f3ac6b6a1c in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=45f3ac6b6a1c
description:
ARM: Configure bootloader parameters
diffstat:
configs/common/FSConfig.py | 8
1 files changed, 8 insertions(+), 0 deletions(-)
diffs (25 lines):
diff -r
changeset 3824fbc8ed9a in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=3824fbc8ed9a
description:
ARM: Update ARM_FS stats for mp changes
diffstat:
tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini |
25 +-
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Ship it!
looks reasonable to me. I assume that it works.
- Nathan
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src/cpu/exetrace.cc
http://reviews.m5sim.org/r/678/#comment1657
X86 doesn't have an ASID hardware feature to the best of my knowledge,
except related to the virtualization extensions when working with
guest memory spaces. Would it make sense to use root page table
pointers for this? I don't know specifically how page tables are
managed in Linux, so I
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src/cpu/SConscript
http://reviews.m5sim.org/r/678/#comment1658
On 2011-05-04 21:08:25, Gabe Black wrote:
CR3 might work. Does the kernel change it on every context switch (user
program)? The main reason for having it is when tracing user code the kernel
can context switch on you. If you want to see all the code that was executed in
a process and
On 2011-05-04 21:00:53, Gabe Black wrote:
src/cpu/exetrace.cc, line 65
http://reviews.m5sim.org/r/678/diff/1/?file=12419#file12419line65
Maybe put these ifs together with an or? It's not hugely better since
the body is so short, but it's something to consider.
It ends up being
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