[gem5-users] Re: Simulation of Hybrid Memory in Gem5

Hi Sadhana, In the screenshot you shared, the address ranges assigned to two memory devices are overlapping (0:1073741824 and 0:2147483648). You should modify the second range such that it does not start from 0 but starts from 1073741824 or some other address (such that the two ranges do not

[gem5-users] Re: How se mode implements system calls for riscv

Hi Srikanta, You can find the implementation of system calls in src/sim/syscall_emul.cc (and related files in the same directory). You can use the "strace" tool to find out the syscalls used by a binary. As far as multithreading is concerned, I think SE mode is not suitable for that purpose and

[gem5-users] Re: Analyzing instruction cycle count

Hi Nick, I wonder which optimization flag you are using while compiling your program? My guess is the the behavior you are observing is because the compiler is able to figure out that the x is a constant number that can be determined statically and the binary it is generating in both cases

[gem5-users] Re: recvAtomicLogic() in mem_ctrl.cc

Hi Eliot, Based on my understanding, when pkt->makeResponse() is called it updates the "cmd" of the pkt with the appropriate responseCommand (this line of code: cmd = cmd.responseCommand();) . If you look at "MemCmd::commandInfo[]" in packet.cc, the response command for a "WriteReq" command is

[gem5-users] Re: recvAtomicLogic() in mem_ctrl.cc

Hi John, If you are checking if the pkt is write when pkt->hasData() condition is true in recvAtomicLogic() function, the check (pkt_is_write) will always be false. The reason is that a write pkt would have already written its data to the memory (abstract memory) in the previous line of code

[gem5-users] Re: Regarding the recvAtomic() function in mem_ctrl.cc

Hi John, What's the exact stat you are looking at for AMAT? My guess is that it is not getting updated for Atomic mode memory accesses. interface. If I change the code to: > return mem_intr->accessLatency() + 100; > Does this mean that it will take 100 more ticks for the memory controller > to

[gem5-users] Re: Browsing the gem5 codebase

Hi John, You can open gem5 code base in Microsoft VS Code to use different code navigation options that work for any C/C++ project. -Ayaz On Wed, Jul 5, 2023 at 9:29 AM John Smith via gem5-users < gem5-users@gem5.org> wrote: > Is there a way to make browsing the gem5 codebase and performing >

[gem5-users] Re: How to port designs simulated on gem5 to real time FPGAs

Hi Saras, I don't think there is a way to convert your gem5 model to an FPGA board as gem5 models are cycle-level models and not not cycle-accurate/cycle-exact. The paper you have referred to, shows how to use gem5 performance numbers and pass them to McPAT, ArchFP, and HotSpot to get power,area,

[gem5-users] Re: Creating Checkpoint with KVM cpu and restore with Timing cpu

Hi Hansika, >1. Is there anything I'm doing wrong or missing or does checkpointing >usually take hours like this? > > I don't think there is anything wrong with how you are trying to create the checkpoint. If the cpt.tick_value directory is created and has contents in it, that means the

[gem5-users] Re: Simple Switchable Processor with checkpoint restoration

Hi Abdal, Assuming that you run into this problem when using different start and switch core types for SimpleSwitchable processor in your script, I think the main problem is that on restore the start core type is not the same as the core with which you took the checkpoint (which I am assuming was

[gem5-users] Re: Fatal error for when clflush is included in workload for O3 system simulation

Hi Shaikhul, I think clflush is not supported in Ruby caches at the moment. For reference, here is the original patch that added support for clflush instruction in gem5: arch-x86: Adding clflush, clflushopt, clwb instructions (7401) · Gerrit Code Review (googlesource.com)

[gem5-users] Re: Question about checkpoints

Hi, I've realised though I'm not sure this may work as intended. Do the > checkpoints gem5 generates include a memory dump of instructions loaded > from a binary as well as stack/heap working data too? I'm intending for all > instructions to be loaded out of the binary I pass on checkpoint

[gem5-users] Re: Writing a script to run multiple simulations at once

Hi Derek, I am not sure if I have understood your question correctly, but the gem5 interface is basically a Python run script in which you can add parameters as well (that can be set from the command line or in shell scripts). For example, you can look at the following link to see how `argparse`

[gem5-users] Re: Integrate mcpat to gem5 simulation

Hi Qian, Based on my understanding, people use scripts to convert gem5 statistics/configs to McPAT understandable statistics/configs and there are multiple scripts around to do that. You might find some help from the following resource: https://github.com/saideeptiku/Gem5McPatParser

[gem5-users] Re: Modeling DRAM memory latencies

Hi Vincent, I think the simplest way to add additional latency is to change the frontend/backend latency parameters of the memory controller (for reference: src/mem/MemCtrl.py). Though you can also try to change the DRAM timing parameters, but that can be much more complicated due to the relation

[gem5-users] Re: Possible bug between X86 processors?

Hi, The question is: Do I build the AMD system differently? gem5 does not need to be built differently on different host platforms. build/X86/base/loader/image_file_data.cc:54: panic: panic condition sz != 2 > occurred: Couldn't read magic bytes from object file This error usually shows up

[gem5-users] Re: Running gem5 with custom instructions

Hi Nick, One of the common reasons you might see the error you are noticing is if you somehow end up using the host compiler instead of the RISC-V compiler. I will recommend that you verify that riscv toolchain directory is added to your $PATH. See this for reference:

[gem5-users] Re: [EXT] Re: Question about running the hpca-2023 tutorial

Hi everyone, The examples from the tutorial repo ( https://github.com/gem5-hpca-2023/gem5-tutorial-codespace) seem to work for me with the gem5/gem5-resources versions checked out in that repo. I basically cloned the entire repo using the --recursive flag. If you are using a different version of

[gem5-users] Re: Run multiple instances of gem5 in FS mode on a single host operating system

Hi Lucas, You should be able to launch multiple instances of gem5 at the same time. What’s the issue that you are facing? -Ayaz > On May 31, 2023, at 9:33 AM, Lucas Zhang via gem5-users > wrote: > >  > I am a college student using gem5 for research.The performance of gem5's FS > mode is

[gem5-users] Re: How to create riscv mesi 3 level or ruby

Hi Srikanta, gem5 stdlib supports MESI_Three_Level ( https://gem5.googlesource.com/public/gem5/+/refs/heads/develop/src/python/gem5/components/cachehierarchies/ruby/mesi_three_level_cache_hierarchy.py) which you should be able to use with RISC-V. You might want to look at the examples in

[gem5-users] Re: Fail to bootup with KVM on X86 arch

Hi, It does not seem like there is anything wrong with your simulation from the terminal output you shared. Please, note that this example script will boot a system with KVM CPU, switch to Timing CPU and then exit the simulation (comment in the file might be useful:

[gem5-users] Re: Performance difference in full system (FS) and system emulation (SE) mode

Hi Vipin, In my opinion, 3% difference is probably not something to worry about. However, there could be many reasons for the difference. As SE mode will use predefined memory address mapping, and thread schedule, that might cause differences compared to the full-system mode. Can the difference

[gem5-users] Re: SMT in full system mode

Hi Ishita, Regarding SMT in FS mode, you might find the discussion in the comments of the following JIRA issue helpful: [GEM5-332] SMT simulation in x86 is not supported - Jira (atlassian.net) -Ayaz On Thu, May 18, 2023 at 10:22 PM Ishita Chaturvedi

[gem5-users] Re: How do I fix extraDataValid error while trying to run a test program on a gem5 simple ARM configuration with cache?

Hi Pedro, I tried this test and noticed the same problem. However, the test seems to work if you use example/se.py script. For example, following command worked: build/ARM/gem5.opt configs/example/se.py -c tests/test-progs/hello/bin/arm/linux/hello --cpu-type=TimingSimpleCPU --caches I would

[gem5-users] Re: (1 of 3) A start job is running for...twork interfaces (14s / 5min 1s)

Hi Xiang, >From the guest terminal output you shared, it seems like it is busy running systemd services after the kernel boot. Simulating those can take a long time. How long has it been running for? -Ayaz On Wed, May 10, 2023 at 5:07 PM Xiang Li via gem5-users wrote: > Hi, > I'm running a

[gem5-users] Re: gem5 won't exit when running 'riscv-tests' in bare metal mode

Hi Evangelos, The problem with these tests (in gem5) is discussed here ( https://gem5.atlassian.net/browse/GEM5-938) in detail. Since they get stuck in a loop after executing some instructions (and I think this happens when the useful part of the benchmark is done), probably using max insts is a

[gem5-users] Re: RISCVMatchedBoard FS

Hi Nikos, I think the simulation might take that long if "-i" flag is not used as the simulation will try to boot Ubuntu. If there is no progress even much later than 2 hours, something else might be going on there. -Ayaz On Tue, May 2, 2023 at 4:40 AM Νικόλαος Ταμπουρατζής via gem5-users <

[gem5-users] Re: How to stop running scipt when starting fs

automatically, I don't have chance to type > command. I mean I want to boot the OS and type command just like a normal > Ubuntu. I guess I can't have a "m5 exit" right? > > Best wish, > Xiang > ---- Replied Message > From Ayaz Akram via gem5-users > Date 05/01

[gem5-users] Re: GEM5 dcache dual-porting

Hi, Based on my understanding, I think if you configure multiple load functional units that would be equivalent to multiple dcache ports. However, using multiple LQs might require changes in the source code. -Ayaz On Mon, Apr 24, 2023 at 11:42 PM G via gem5-users wrote: > Hello, > > Seems

[gem5-users] Re: RISC-V full system simulation: adding benchmarks to disk image

You might find some useful things in these slides: PowerPoint Presentation (gem5.org) . But, mainly, you just need to change the following line in the fs script (assuming you are using riscv full system example from

[gem5-users] Re: RISC-V full system simulation: adding benchmarks to disk image

Hi Vladimir, You can modify the riscv fs script and use CustomResource for the disk image resource by passing the path to your modified disk image. This will ensure that gem5 is using your disk image and not redownloading a clean resource. -Ayaz On Sun, Apr 30, 2023 at 9:13 AM Vladimir

[gem5-users] Re: How to stop running scipt when starting fs

Hi Xiang Li, Based on your shared guest terminal output, OS has yet to boot fully. Your init script probably has not been executed yet. In case you don't care about systemd, you can also change the kernel arguments in the gem5 run script to directly run your init script once the kernel has

[gem5-users] Re: Question about gem5 tutorial

Hi Dr. Nick Beser, I am working my way through the tutorial and I have some questions. I > noticed that the tutorial at: > https://www.gem5.org/documentation/learning_gem5/part1/cache_config/ has > a section called Adding parameters to your script. It describes the parser > arguments that seem to

[gem5-users] Re: Running a machine learning model on gem5

Hi Saras, If you have a disk image with a machine learning model and relevant libraries installed, you should be able to use it with gem5. I would suggest looking at the examples of full-system simulation with gem5. Secondly, you might want to look at how to modify disk images with QEMU and test

[gem5-users] Re: SPEC2017 - Most of the metrics in m5.out/stats.txt are 0 or undefined

Hi Farbin, I think that change/fix is already merged. -Ayaz On Wed, Apr 12, 2023 at 1:47 PM Farbin Fayza wrote: > Hi everyone, thank you very much for co-operating. The stat file errors > were resolved by the change that Humza mentioned. The stat file now > contains non-zero metrics. Should I

[gem5-users] Re: Does Gem5 support arm64 SVE2?

Hi Shuo, If I am not mistaken, I think gem5 only supports SVE instructions. -Ayaz On Sun, Apr 9, 2023 at 7:44 PM Shuo via gem5-users wrote: > hello, > > Does Gem5 support arm64 SVE2(Scalable Vector Extension2)? > > Yours > Shuo > ___ > gem5-users

[gem5-users] Re: gem5

Hi, You can configure some aspects of functional units (including ALU) in detailed CPU models of gem5 (e.g., count, the particular type of operations the unit will perform, latency etc.). For reference, please look at src/cpu/o3/FuncUnitConfig.py. -Ayaz On Mon, Apr 10, 2023 at 8:32 PM 中国石油大学张天

[gem5-users] Re: SPEC2017 - Most of the metrics in m5.out/stats.txt are 0 or undefined

Hi, @Humza or @Farbin: Can you please push the spec-2017 change that worked for you to the mainline gem5 as well? Thanks, -Ayaz On Thu, Apr 6, 2023 at 9:03 PM Ayaz Akram wrote: > Hi Farbin, > > However, now they're taking so much time to run. I'm trying to run >> perlbench, gcc, bwaves, and

[gem5-users] Re: Pretending totalOps is equivalent to totalInsts()

Hi Kazi, If you are referring to the "Pretending totalOps is equivalent to totalInsts()", that is not really an error. It means that KVM CPU is approximating totalOps with totalInsts (as the KVM model cannot count the number of micro-ops that got executed on the native hardware) in the generated

[gem5-users] Re: SPEC2017 - Most of the metrics in m5.out/stats.txt are 0 or undefined

Hi Farbin, However, now they're taking so much time to run. I'm trying to run > perlbench, gcc, bwaves, and mcf with the "test" size, and they're running > for more than 10 hours and still, none of them aren't finished. Is this > normal? Could you tell me how long they usually take? I would

[gem5-users] Re: Running FS in example/gem5_library/x86-spec-cpu2017-benchmarks.py

Hi Manish, Can you provide more information about your test system? If you are running gem5 inside a virtual machine, you should ensure the KVM configuration change is also done on the host system. -Ayaz On Sun, Apr 2, 2023 at 5:24 PM Manish manchali via gem5-users < gem5-users@gem5.org> wrote:

[gem5-users] Re: Strange Behavior of checkpoint in multicore

Hi Abdlerhman, One possible explanation is as follows: You are running the same program on all cores with the m5 checkpoint call and then you take at maximum one checkpoint, which will be taken by whichever core hits the checkpoint call first. In the first two cases you mentioned (Atomic vs. O3

[gem5-users] Re: Demo problems

Hi Kofi, If you can list the specific problems you are running into, someone might be able to help. -Ayaz On Fri, Mar 24, 2023 at 10:41 AM Kofi AN via gem5-users wrote: > Hello all – > > > > I am trying to demonstrate effectiveness of cache replacement policies > against cache attacks such as

[gem5-users] Re: Question about setting up to use NVM

, but the change can also break existing gem5 run scripts. In any case, I will try to push a change to make it less confusing. -Ayaz On Sun, Mar 19, 2023 at 3:43 AM Eliot Moss wrote: > On 3/18/2023 10:40 PM, Ayaz Akram via gem5-users wrote: > > Hi Eliot, > > > > MemCtrl() memory c

[gem5-users] Re: Question about setting up to use NVM

Hi Eliot, MemCtrl() memory controller in gem5 can control a single DRAM interface or a single NVM interface at a time. I think one way to verify that things are set-up correctly is to confirm this from the "m5out/config.ini". If config.ini seems to be using 'MemCtrl' type for the memory

[gem5-users] Re: TLB Miss penalty in O3CPU and se.py

Hi Haseung, I am not sure if I have fully understood the question, but I will try to answer based on my understanding (please let me know if I misunderstood). SE mode, on a TLB miss, makes use of the gem5 managed page table for the simulated process instead of modeling a page table walk and I

[gem5-users] Re: Adding new X86 memory instruction for O3CPU

Hi Le Minh Son, In my opinion, if you are well aware of the ISA specs and know how your new instruction will fit in with the existing instructions, you might add a real instruction. Otherwise, adding a pseudo instruction might be a better option. Following are some of the references that you

[gem5-users] Re: connect 2 memory devices on SystemXBus

Hi Brian, Can you share the script/configuration that ran into the problem with the stable branch? I did a quick test with the traffic generator (with two different mem devices) and things seem to work ok on my end. Thanks, -Ayaz On Sat, Mar 11, 2023 at 9:33 AM Brian Chan via gem5-users <

[gem5-users] Re: Documentation / explanation on configuring memory (also: thoughts on offering cache flush patches)

Hi Eliot, gem5 splits the memory system modeling into two parts: 1) the memory controller and 2) the memory interface. The memory interface can be a DRAMInterface or NVMInterface and provides many parameters that are configured to achieve a specific memory device model (e.g., DDR4, GDDR5). The

[gem5-users] Re: Interactive simulation with statistics per executable

Hi Sebastian, I am not aware of an existing example which does what are you looking for. But, I think the best way to achieve this will be annotating your workloads using m5 ops (you might have to add special m5 ops to recognize what workload finished) to move control from the simulated system to

[gem5-users] Re: Retired instructions versus ticks

Hi Priyanka, By default, the dumped stats have the total number of instructions and cycles/ticks for a specific simulation. If you want to look at these stats over smaller time intervals, one possible option is to change your gem5 run script to simulate for a specific time, dump stats, and keep

[gem5-users] Re: Questions about using gem5

Hi, Is there a way to simulate using DDR5 memory in gem5? Currently, there is no DDR5 interface in gem5. I just pushed an in-progress change here ( https://gem5-review.googlesource.com/c/public/gem5/+/68257/1/src/mem/DRAMInterface.py) to support a single channel of DDR5. This configuration

[gem5-users] Re: Requestor ID of a Packet - How it is generated

Hi Abdlerhman, I think your understanding of different requestor IDs for a single core is correct i.e., these specify instruction and data requests. "dataRequestorId()" and "instRequestorId()" functions in src/cpu/base.hh verify this. I think prefetchers should also have their own requestor ids

[gem5-users] Re: Interactive simulation with statistics per executable

Hi Sebastian, I don't think you can collect per-binary statistics (at least without changes in gem5 and potentially the guest OS) while simulating them simultaneously in a full-system simulation. Also, I am assuming you want to study the interaction of multiple workloads, and that's why you do

[gem5-users] Re: Memory traces using CommMonitor

Hi Sadhana, SE mode, by default, uses a 4KB page size. You can convert the pkt addresses generated by the commMonitor to page addresses manually or change the commMonitor code to dump the page addresses. -Ayaz On Wed, Feb 15, 2023 at 9:08 PM Sadhana . wrote: > Hai Ayaz, > In addition to the

[gem5-users] Re: Memory traces using CommMonitor

Hi Sadhana, I think the first number is the requestor port id (IIRC). The above trace should have all requests to the main memory as your CommMonitor is connected between the membus and MemCtrl (and all memory traffic should go through it). -Ayaz On Mon, Feb 13, 2023 at 7:52 PM Sadhana . via

[gem5-users] Re: SE Mode DMA Engine

Hi Siddharth, There is an existing CopyEngine in gem5 (src/dev/pci/copy_engine.cc) which might be similar (and helpful) to what you are trying to do. -Ayaz On Thu, Feb 2, 2023 at 2:37 AM Siddharth Sahay via gem5-users < gem5-users@gem5.org> wrote: > Hi! > What would be the best strategy for

[gem5-users] Re: handle syscalls in FS (bare-metal) mode for RISCV

Hi Priyanka, If you want syscall handling you can use full-system simulation with Linux as the OS (instead of the bare metal full system). gem5 also provides a syscall emulation (SE) mode where you do not need to run any OS, and gem5 would emulate most of the system calls. -Ayaz On Wed, Feb 1,

[gem5-users] Re: RISC-V FS stuck at login

Hi Joao, I will suggest looking at the last part of the following README file to understand how this disk image should be used (I think your simulation is executing an m5 exit at the boot up) : https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/develop/src/riscv-ubuntu/README.md

[gem5-users] Re: gem5 always adds PCID to vaddr to lookup TLB

Another thing to notice is that the current PCID change is intended for SE mode only (as you might have seen in the comments of the JIRA issue: https://gem5.atlassian.net/browse/GEM5-332). So, the global bit probably would not be used anyways. -Ayaz On Wed, Feb 1, 2023 at 4:14 PM Ayaz Akram

[gem5-users] Re: gem5 always adds PCID to vaddr to lookup TLB

Hi Soramichi, I agree with the change you are proposing. May I open an issue on Jira on this and assign myself? Yes, please do that. -Ayaz On Tue, Jan 31, 2023 at 11:07 PM Soramichi Akiyama wrote: > Hi Ayaz, > > thank you for your reply and I really appreciate your effort for making > SMT

[gem5-users] Re: Interactive simulation with statistics per executable

Hi Sebastian, I use [2] as starting point but I can’t change workloads in the python > script and rerun the simulation because this would simulate another system > instead of simulating another executable in the same system. Going to python script should not simulate another system, rather once

[gem5-users] Re: gem5 always adds PCID to vaddr to lookup TLB

Hi Soramichi, We recently added the concatenation change to distinguish TLB entries of different processes to make SMT work. You can check more details here: https://gem5.atlassian.net/browse/GEM5-332 I am not sure what the behavior should be for global pages. From some discussion here:

[gem5-users] Re: cache line data based on memory accesses

[Copying my response from gem5 slack in case you don't see there] Hi Ghadeer, I think you should be able to dump packet data with your changes in abstract_mem.cc. access() function eventually calls getData() and writeData() of packet.hh which use getSize() which gives the size of the packet.

[gem5-users] Re: RISCV fs mode - code won't stop running

Hi Priyanka, I am assuming you don't see any new instructions in the "trace.out" after a specific time. My understanding is that since this program is run in full system mode (bare metal), even when the program finishes the simulation loop still keeps executing (simulating the bare metal system).

[gem5-users] Re: Accessing CPU cycles in Ruby components

Hi Ziyao, Based on my understanding, I guess for the Ruby stats that are not in Ticks, you can rely on the Ruby ClockDomain value from the configuration to convert the cycles to CPU cycles or ticks. -Ayaz On Tue, Jan 24, 2023 at 12:48 AM Ziyao Yan via gem5-users < gem5-users@gem5.org> wrote: >

[gem5-users] Re: Simulation error for hello world workload

Hi Ikram, It seems like your program is using a system call (#398) which has not been tested or implemented in gem5. This can be because of a newer version of the c library or compiler. One option is to ignore this system call and see if your program still works. As a reference you can look at

[gem5-users] Re: Limit FS memory through kernel args

Hi Joao, If you look at the source code here (in case you haven't previously): src/python/gem5/components/boards/kernel_disk_workload.py, I think the expectation is that the user-provided kernel arguments will replace the default ones. However, I agree that it might be useful to have the ability

[gem5-users] Re: Running gem5 RISCV in bare-metal mode

Hi Priyanka, I think adding something like the following line in your script should solve the problem you are running into: system.platform.pci_host.pio = system.iobus.mem_side_ports -Ayaz On Tue, Jan 24, 2023 at 6:48 AM Priyanka Ankolekar via gem5-users < gem5-users@gem5.org> wrote: > Hello,

[gem5-users] Re: Set number of register file read and write ports

Hi, Based on my understanding of O3CPU, I think your assumption is correct. However, probably parameters like issueWidth and wbWidth can be used to control maximum register read/writes indirectly. -Ayaz On Tue, Jan 17, 2023 at 3:32 AM pedro--- via gem5-users wrote: > Hi, > > I'm trying to

[gem5-users] Re: Running OpenMP version of SPEC CPU speed 2017 benchmarks

Hi Vipin, I guess that you will have to create a new disk image by changing the benchmark build and run scripts from https://gem5.googlesource.com/public/gem5-resources/+/refs/tags/v20.1.0.5/src/spec-2017/disk-image/spec-2017/ (install-spec2017.sh and runscript.sh). You will have to add openmp

[gem5-users] Re: PerfKvmCounter::attach failed (2)

Hi Atlas, I think the host machine means the bare metal host. I have not personally run KVM CPU of gem5 on a VM, but you might find this post on the mailing list relevant: https://www.mail-archive.com/gem5-users@gem5.org/msg20996.html -Ayaz On Tue, Jan 10, 2023 at 11:16 AM Atlas Kaan Yilmaz

[gem5-users] Re: Is there actual data in the DRAM?

Hi Daniel, The memory interfaces inherit from AbstractMemory, which is where the actual data is stored. I will suggest looking at src/mem/abstract_mem.cc to get a better understanding of this. -Ayaz On Mon, Dec 26, 2022 at 5:42 AM 李信德 via gem5-users wrote: > Hi everyone, > > I would like to

[gem5-users] Re: Not able to access webpage to run_npb.py

Hi David, Please find my response to your questions below: > >1. It seems like I don’t need to do the “Setting up the environment” >since I don’t plan to create or modify npb-tests. > > I thought the npb tests are already on the disk image from “Creating a > disk image” section. >

[gem5-users] Re: Implicit Register Dependencies in x86

Hi Mohit, I wonder if the number of Physical register file entries is becoming a bottleneck in the configuration you are using? Normally, I would expect that 'ProdLo' and 'ProdHi' registers will be renamed to some physical register and should not cause any dependency between two independent

[gem5-users] Re: Fwd: Making an address range uncacheable RISCV FS.

Hi Deepak, I guess, if you care about more accurate implementation you might have to add new instruction in the ISA or maybe adding a new gem5 pseudo instruction will be easier. Also, according to my understanding, you might be able to use the cache invalidation/flushing related functionality in

[gem5-users] Re: Making an address range uncacheable RISCV FS.

Hi Deepak, RISC-V PMA is supported in gem5. You can have a look at the source here: https://gem5.googlesource.com/public/gem5/+/refs/heads/develop/src/arch/riscv/PMAChecker.py Also, here is an example of how this can be used in the gem5 config script:

[gem5-users] Re: gem5 Intel SGX model

Hi Jared, Not SGX, but we recently did some work on running RISC-V-based TEEs (Keystone specifically) in gem5, which you might find useful. You can look at the documentation here: https://github.com/darchr/Keystone-experiments -Ayaz On Thu, Jun 10, 2021 at 11:41 AM Jared Nye wrote: > Hello, >

[gem5-users] Re: KVM patch for FS mode and PARSEC on gem5-21

Hi Rajesh, I think the error you are seeing is because tlbs are exposed through an mmu unit in gem5 now. I guess changing line 117 in caches.py as in this file ( https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/src/boot-exit/configs/system/caches.py) should work for you.

[gem5-users] Re: Copying/Writing data from one packet to another packet in gem5

Hi Aritra, As you might have already noticed that there is a ptr to the data being transferred (PacketDataPtr data) in the packet class: http://doxygen.gem5.org/release/current/classPacket.html I think you should be able to use methods like setData(), writeData() from the same class to copy

[gem5-users] Re: FS RISCV PCI

Hi Nikolaos, Thanks for bringing this to our attention. We are looking at this problem here at Davis and will try to respond soon. -Ayaz On Sat, Apr 10, 2021 at 4:42 AM Νικόλαος Ταμπουρατζής via gem5-users < gem5-users@gem5.org> wrote: > > Dear Gem5 community, > > I try to add PCI interface in

[gem5-users] Re: Creating a disk image for FS mode

Hi Ahmed, Did the scons command in the file you referred above not work for you? Btw, you might find more information on the m5 utility in this README inside the source: https://gem5.googlesource.com/public/gem5/+/refs/heads/develop/util/m5/README.md -Ayaz On Thu, Feb 4, 2021 at 2:40 AM

[gem5-users] Re: How to disable branch predictor in MinorCPU

Hi, In my opinion, you might not be able to disable a branch predictor using NULL assignment. A way to make this possible is to add your own (simple) branch predictor (or hack one of the existing branch predictors) which will always return not-taken. -Ayaz On Thu, Dec 24, 2020 at 6:00 AM -17

[gem5-users] Re: Run spec cpu 2006 on gem5

Hi, > does this mean that I have gone the right way and do I not need to > specify any arguments or input(ref,train) to run the "spec cpu 2006" on > gem5-fullsystem like what is said in the file "speccmds.cmd" that is in " >

[gem5-users] Re: Run spec cpu 2006 on gem5

Hi, The output you are seeing indicates a successful bzip run. As far as I remember bzip binary inside run folder (the one you referred to above) uses "data/all/input/input.combined" file by default and the output you are seeing definitely shows that bzip ran with input.combined. If you want to

[gem5-users] Re: PTE Flags

Hi, Based on my understanding of what you are trying to do, I would suggest looking into src/arch/x86/tlb.cc (assuming you want to use x86) around line 400, to see how to access page table entries from a process pointer. syscall_emul.hh already includes sim/process.hh, so you can follow what is

[gem5-users] Re: TLB in SE simulation

Hi Francisco, Based on my understanding, TLBs are modeled in SE mode for x86. With what accuracy and preciseness TLB timing is modeled is debatable though. However, it does not seem like that is the case for RISC-V. Specifically, if you take a look at the src/arch/riscv/tlb.cc (TLB::translate()),

[gem5-users] Re: how to add more than 1 ide disk in gem5 fullsystem

Hi, I think the config script (system.py) in boot tests on gem5-resources ( https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/develop/src/boot-exit/configs/) shows how to add two disks in your configuration. Specifically, looking into setDiskImages()might be helpful. -Ayaz On

[gem5-users] Re: Instruction execute stage clock cycles in MinorCPU

Yeah, it does not seem like m5ops are implemented in RISC-V yet. I did not see any RISC-V specific code in "util/m5/src/abi/". One workaround could be to stop simulation at a particular instruction count (e.g. if you know at what instruction number your function of interest starts and ends) from

[gem5-users] Re: Instruction execute stage clock cycles in MinorCPU

Hi Volkan, Following is my understanding of the issues you mentioned in your email (I hope someone with more RISCV experience can augment/correct this): 1. Each functional unit can be responsible for execution of multiple classes of instructions and you can configure the latency of each class of

[gem5-users] Re: How to use CommMonitor in gem5

Hi, 1. I remember using CommMonitor with DerivO3CPU for a small example and the output looked fine to me. Maybe someone else can point out if there is something fundamentally broken. 2. You should be able to use gem5/util/decode_packet_trace.py to convert the generated trace (after decompressing

[gem5-users] Re: How to simulate multithread, multicore and multiprocessor system ?

Hi Duc, By passing a list of CPUs to the system.cpu (as in the attached Python script), you are creating a multicore CPU (CPU here refers to a core). Secondly, if your CPU has SMT enabled, you should be able to pass multiple processes to the workload option. Btw, there is already a JIRA issue

[gem5-users] Re: A question regarding to VIPT/PIPT

Hi Leon, I think you can use lower than normal latency values (what would be reasonable for PIPT) to model VIPT cache in gem5. To understand how to configure cache latencies, have a look here (if you have not already): https://www.gem5.org/documentation/learning_gem5/part1/cache_config/ -Ayaz

[gem5-users] Re: Why are there still so many decoding-related operations when fetching instructions into the instruction queue?

Hi Yujiecui, The fetch stage in O3CPU fetches cache lines from instruction cache and also calls ISA specific decoder implementation to decode the raw bytes into instructions and access the corresponding micro-ops for these instructions (In other words, fetch stage outputs the micrco-ops). That's

[gem5-users] Re: A question regarding to VIPT/PIPT

Hi, I am not totally sure how easy would it be to modify the current implementation, but following pointers to understand the codebase and where to make modifications might be useful: to understand how virtual to physical address translation takes place look at: src/arch/[your ISA e.g.

[gem5-users] Re: A question regarding to VIPT/PIPT

Hi Leon, Since, gem5's caches are PIPT so there should not be an aliasing problem and you can change the latency of the cache to model a VIPT cache. Since, a VIPT cache should not have aliasing problem if all index bits come from the page offset (as far as I understand), maybe for a realistic

[gem5-users] Re: A question regarding to VIPT/PIPT

Hi Leon, In gem5, the caches are PIPT technically. But, you can model the timing of a VIPT cache by changing the latency of your cache. As far as the kernel boot log is concerned, I am not fully sure if "CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache" refers to the actual

[gem5-users] Re: X86KvmCPU fails -- reason code 0x80000021

Hello Ryan, I think, if you are using an Intel machine, you will still need to apply those patches. The conversation on this issue might be useful for you: https://github.com/darchr/gem5art-experiments/issues/60 -Ayaz On Thu, Oct 15, 2020 at 5:20 PM Gambord, Ryan via gem5-users <

[gem5-users] Re: CPU switching after booting system into FS mode.

Hi Vipin, You can boot Linux using KVM CPU in gem5 and then switch to a more detailed CPU model to simulate your workloads. Please, have a look at the gem5 run scripts for npb and parsec benchmarks in gem5 resources as examples:

[gem5-users] Re: An error occurred in i8237 DMA controller when running CPU SPEC 2017 benchmarks

Hi Jinpeng, First of all, you will have to recompile gem5 to use Ruby with MESI_Two_Level (the default protocol is MI_example): scons build/X86_MESI_Two_Level/gem5.opt --default=X86 PROTOCOL=MESI_Two_Level Secondly, I will suggest you to compile your kernel following the instructions here:

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