Zehan,
is your application in simulation making any progress? If not then you might
miss an update from someone handshaking with this core. It seems the memory
location is set to a non-zero value and then this core will wake up.
It might be that the core setting this memory location never
,
Stephan
Stephan Diestelhorst
Staff Engineer,
ARM Research - Systems
+44 (0)1223 405662
On Monday 01 June 2015 09:38:41 冰兲轌地 wrote:
Hello ，everyone！
I want to run a benchmark to evaluate DVFS in the gem5 fs mode. I have
finished the DVFS experiments.Now,I want to run a benchmark under it.What
,
Stephan
Stephan Diestelhorst
Staff Engineer
ARM Research - Systems
+44 (0)1223 405662
On Thursday 16 April 2015 14:50:17 Ruslan Bukin wrote:
This controls timer frequency in Linux ?
I've played with generic timer frequency in freebsd decreasing
the frequency from 100MHz (default) to 10MHz
ClockDomain without OS / simulated system
involvement, can either be a quick approximation of such a thing, or
modelling a *hardware* DVFS controller.
Hope that helps.
--
Thanks,
Stephan
Stephan Diestelhorst
Staff Engineer
ARM Research - Systems
+44 (0)1223 405662
On Thursday 16 April 2015 16:49
Hi Giorgos,
Am Samstag, 4. April 2015, 20:18:26 schrieb Giorgos Kopanas:
I am trying to make Gem5 work with the DVFS as explained in the
website. While running in Atomic Simple it is working as intended but
when I change the cpu type to arm_detailed the simulation crushes
during boot. The
Hi
On Monday 06 April 2015 15:55:01 Giorgos Kopanas wrote:
I was running through the developing branch. The stable version works.
Great news; the volatility regarding uncacheable in the main branch
should hopefully settle soon (with the patches mentioned).
Thanks,
Stephan
-- IMPORTANT
Lokesh,
from your config.ini and config.pdf, I see that you are only
initialising a *single* core. Can you please double check that you
initialise the right number of cores in your configuration files and
retry?
--
Many thanks,
Stephan
Stephan Diestelhorst
Staff Engineer
ARM RD Systems
/ the list know if you have further questions, and also
feel free to adapt the wiki.
--
Thanks,
Stephan
Stephan Diestelhorst
Staff Engineer
ARM RD Systems
-- IMPORTANT NOTICE: The contents of this email and any attachments are
confidential and may also be privileged. If you are not the intended
wrong, here. This looks like a genuine different
issue, but I will leave that to the x86 devs, here ;)
--
Hope that helps,
Stephan
Stephan Diestelhorst
Staff Engineer
ARM RD Systems
-- IMPORTANT NOTICE: The contents of this email and any attachments are
confidential and may also
Stephan Diestelhorst
Staff Engineer
ARM RD Systems
-- IMPORTANT NOTICE: The contents of this email and any attachments are
confidential and may also be privileged. If you are not the intended recipient,
please notify the sender immediately and do not disclose the contents to any
other person, use
Hi Rahul,
On 11.11.2014 07:20, rahul shrivastava
rshrivasta...@gmail.commailto:rshrivasta...@gmail.com wrote:
I am actually using a dtb file only and not dts, Sorry for a typo in my
previous mail. Please find attached config.ini and config.json file.
Thanks for these. I think what you need to
Hi Rahul,
On Monday 10 November 2014 09:08:46 rahul shrivastava via gem5-users wrote:
I am following the steps mentioned in the documentation to configure
per-core dvfs. I am trying to simulate four cores by giving the following
command
M5_PATH=$(pwd)/.. ./build/ARM/gem5.opt
On Monday 10 November 2014 11:43:39 Stephan Diestelhorst via gem5-users wrote:
Hi Rahul,
On Monday 10 November 2014 09:08:46 rahul shrivastava via gem5-users wrote:
I am following the steps mentioned in the documentation to configure
per-core dvfs. I am trying to simulate four cores
,
Stephan
Stephan Diestelhorst
Staff Engineer,
ARM RD Systems
+44 (0)1223 405662
-- IMPORTANT NOTICE: The contents of this email and any attachments are
confidential and may also be privileged. If you are not the intended recipient,
please notify the sender immediately and do not disclose
,
Stephan
Stephan Diestelhorst
Staff Engineer,
ARM RD Systems
+44 (0)1223 405662
-- IMPORTANT NOTICE: The contents of this email and any attachments are
confidential and may also be privileged. If you are not the intended recipient,
please notify the sender immediately and do not disclose
are currently getting a patch ready that
creates the proper interface between the DVFSHandler and Linux' cpufreq
world for ARM.
I hope that clarifies the scope of this patch.
--
Sincerely,
Stephan
Stephan Diestelhorst
Staff Engineer,
ARM RD Systems
+44 (0)1223 405662
-- IMPORTANT NOTICE
Srini,
kudos for making per-core DVFS work! A quick head¹s up: we are also
working on (per-core) DVFS support and are just polishing those patches
for consumption, should hopefully have them ready within a week or two.
On the main question, I have no hard opinion, but wonder what the
reasoning
Hi,
you need to properly order the lock acquisition with the counter
manipulations, for example as below (or see
http://lxr.free-electrons.com/source/arch/arm/include/asm/spinlock.h
or
http://blogs.arm.com/software-enablement/188-locks-swps-and-two-smoking-barriers-part-2/
)
On Monday 07
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