[gem5-users] m5_ops ROI

Hello, How do the functions m5_work_begin and m5_work_end operate? I've incorporated them into my code while running FS mode. Does it generate multiple statistics when my fs script includes m5 dumpresetstats after booting and utilizes m5_work_begin(0,0) before a function call, followed by

[gem5-users] Questions about classic cache prefetcher stat defination

Hello, Does anyone know why doesn't the prefetcher coverage statistic in the classic cache account for the pfUsefulButMiss metric? The existing definition of coverage and accuracy appears flawed, as it fails to incorporate pfUsefulButMiss in calculating the true useful prefetches (pfUseful -

[gem5-users] Branch Misprediction counters

.cpus.decode.branchMispred) is separate from the Commit counter (system.chips.clusters.cpu_groups0.cpus.commit.branchMispredicts)? 2. Are IEW branchMispredicts (system.chips.clusters.cpu_groups0.cpus.iew.branchMispredicts) included in the Commit counter? Thank you, Abhishek Singh

[gem5-users] Enable prefetcher for CHI protocol

Hello, Is it possible to use prefetcher with CHI protocol for a ruby memory system with the current CHI model implementation? I noticed that the CHI config file has an assertion condition on setting prefetcher. How does the prefetcher model in ruby interact with the coherence protocol?

[gem5-users] Ruby Prefetcher

Hello, I would like to know if anyone knows of a protocol implemented in Ruby with all the cache levels prefetcher modeling. I have been researching this topic and am still trying to find a clear answer. If anyone has any insights or knowledge on this matter, I would greatly appreciate your input.

[gem5-users] Re: To know about cpu switching in gem5

Hi Krishna, I hope you are doing well too. The experiment which you described, I think gem5art group has been successful to pull that off. Here is the link https://gem5art.readthedocs.io/en/latest/, you can see their SPEC benchmark example as the starting point On Sun, Nov 1, 2020 at 12:46 PM

[gem5-users] Re: Implementing Cache Replacement Policies

Hi, I think you should check already implemented policies in src/mem/cache/replacement_policies and then design yours taking that as an template/example. In order to get information which you mentioned, you might have to change/add arguments to accessBlock, findBlock, insertBlock, etc function

[gem5-users] Re: How to run Python code with TensorFlow in Gem5 syscall emulation mode?

Hi Hasan, I have been trying to run tensorflow on gem5, have you tried full system? I was able to run simple python code like hello on it. Let me know if it works On Fri, Oct 23, 2020 at 12:28 PM Hasan, S M Shamimul via gem5-users < gem5-users@gem5.org> wrote: > Hello, > > * I want to run

[gem5-users] Re: Cache level 1 miss rate is the same with and without level 2 cache

Hi, I do not think that making the cache hierarchy deeper will have any effect on 1'st level cache hit/miss rate. Best regards, Abhishek On Thu, Oct 22, 2020 at 1:03 PM Abhishek Singh < abhishek.singh199...@gmail.com> wrote: > Hi, > > Does this happen with O3 CPU or just t

[gem5-users] Re: Cache level 1 miss rate is the same with and without level 2 cache

Hi, Does this happen with O3 CPU or just the in order CPU? On Thu, Oct 22, 2020 at 1:01 PM Muhammad Aamir via gem5-users < gem5-users@gem5.org> wrote: > Hi everyone, > > I have noticed that the stat: "system.cpu.dcache.overall_miss_rate::total" > is the same if I only use 1 level of cache or

[gem5-users] Re: GDB debug help

backtrace On Fri, Oct 2, 2020 at 12:13 PM Shougang Yuan wrote: > Hi, Abhishek, > > Thanks for your help. Do you have any hints about gdb backtrace in gem5? I > am new to gdb debugging. > > Best regards. > > On Fri, Oct 2, 2020 at 12:03 PM Abhishek Singh < > abhishe

[gem5-users] Re: GDB debug help

Hi Yuan, Can you just backtrace using gdb, this will directly point the gem5 function which is giving the error? On Fri, Oct 2, 2020 at 12:01 PM Shougang Yuan via gem5-users < gem5-users@gem5.org> wrote: > Hi, Giacomo, > > Thanks for your help. I am currently suffering a new problem. I set the

[gem5-users] Re: panic: Tried to execute unmapped address 0x7ffff7ce2380.

Hi, Try including the same caches configuration when you take checkpoint. Your first step do not have caches. On Thu, Sep 17, 2020 at 11:31 AM Xuhao Chen via gem5-users < gem5-users@gem5.org> wrote: > Hi all, > I have a simple program: > #include > #include > #include > #include

[gem5-users] Re: [Error] Building gem5 in Ubuntu 18.04

ich I can verify that. It will help you to provide me the > required information. > > On Sat, Aug 29, 2020 at 12:19 AM Abhishek Singh via gem5-users < > gem5-users@gem5.org> wrote: > >> Hi, >> >> Is your memory full? >> >> On Fri, Aug 28, 2020 at 2:47 PM Dwai

[gem5-users] Re: [Error] Building gem5 in Ubuntu 18.04

Hi, Is your memory full? On Fri, Aug 28, 2020 at 2:47 PM Dwaipayan Ray via gem5-users < gem5-users@gem5.org> wrote: > Hi, > > I am getting the attached error while building gem5 in Ubuntu 18.04. > > Please help me. A prompt response is really appreciated. > > Thanks > Ray > > >

[gem5-users] Running CNN benchmarks on gem5

Hello Everyone, If anyone has run AlexNet or LeNet using gem5, please let me know how you did it (source of benchmark, which gem5 commit, which ISA)? Best regards, Abhishek ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an

[gem5-users] Running Tensorflow application on gem5

Hello Everyone, I am trying to run LeNet and AlexNet (tensor flow code) at this github (Link: https://github.com/iCAS-Lab/IMAC/tree/master/Tensorflow). I have made a disk image using Step 2 "Using gem5 utils and chroot to create a disk image" I am using Linux-4.8.13 kernel and ubuntu 16. I am

[gem5-users] Re: Full system files Makefile. missing

Email: chongzhizhao4 (at) gmail (dot) com > > > On Fri, Aug 21, 2020 at 12:44 PM Abhishek Singh via gem5-users < > gem5-users@gem5.org> wrote: > >> Hello Everyone, >> >> I am trying to build a Full system image using Step 2 "Using gem5 utils >

[gem5-users] Full system files Makefile. missing

Hello Everyone, I am trying to build a Full system image using Step 2 "Using gem5 utils and chroot to create a disk image" mentioned here ( https://www.gem5.org/documentation/general_docs/fullsystem/disks). I cannot locate "Makefile." in gem5_20 (util/m5) and develop branch. Is this method no

[gem5-users] Re: Unable to build ALPHA in the latest gem5

Hi, ALPHA ISA is no more supported in gem5-20 Best regards, Abhishek On Thu, Jul 23, 2020 at 10:15 AM Saideepak Bejawada via gem5-users < gem5-users@gem5.org> wrote: > Hi all, > > I am unable to build gem5.opt for ALPHA. > Error: Cannot find variables file >

[gem5-users] Re: gem5 functional mode simulation

Hi Yuan, You can use AtomicSimple CPU, it’s an in order CPU You can find more information here https://www.gem5.org//documentation/general_docs/cpu_models/SimpleCPU On Thu, Jul 2, 2020 at 5:23 PM Shougang Yuan via gem5-users < gem5-users@gem5.org> wrote: > Hi, All, > > I want to use the

[gem5-users] Re: Directly accessing certain regions of memory...

Hi Anuj, Method 1: If you already know the address range, for classic cache model, in the “src/mem/cache/base.cc” file see the recvTimingReq function. When the address lies in your desired address range turn the NonCacheable request flag high for that block. You can find information about this

[gem5-users] Re: Accessing cache stats during execution

Hi, For now the standard stats file from gem5 using classic cache model does not have MPKI. So you need to declare the stats and you can access the declared stats in cpu, see the how cpu calls LSQ (or cache) objects and using that you can access the MPKI stat from CPU On Fri, Jun 26, 2020 at

[gem5-users] Re: Bringing an additional block into cache

Hi, Can’t you just use prefetcher here? Just modify the next line (tagged) prefetcher to get the block you want On Wed, Jun 24, 2020 at 11:53 PM Saideepak Bejawada via gem5-users < gem5-users@gem5.org> wrote: > Hi all, > > I am trying to bring in another block into the cache in addition to the

[gem5-users] Running python based graph neural network application on gem5

Hello Everyone, I would like to run graph NN application on CPU based architecture, does gem5 support applications written in pytorch or tensorfow(python)? Also, if there is another benchmark suite that has Graph NN applications and can run on gem5, please do tell about it? PS: I had asked this

[gem5-users] Re: Gem5 will not exit when run Muti-process in se mode with O3CPU

Hi, It’s a known problem and there’s a Jira issue on it https://gem5.atlassian.net/plugins/servlet/mobile?originPath=%2Fbrowse%2FGEM5-332#issue/GEM5-332 On Sun, Jun 21, 2020 at 9:11 AM Taiyu Zhou via gem5-users < gem5-users@gem5.org> wrote: > I run > " > ./build/X86/gem5.opt

[gem5-users] Re: find miss types from stat.txt

Hi Ahmed, The stats file obtained will not be able to give you such detailed information, you will have to implement your own stats parameter to get different types of misses. On Sat, Jun 20, 2020 at 2:27 PM ahmed91khalil--- via gem5-users < gem5-users@gem5.org> wrote: > hi , > I am working on

[gem5-users] Re: Problem with gem5 memory latency

Hey. You can change those parameters for classic cache in config/common/Caches.py For main memory search for python files in src/mem/ directory, mostly it’s DRAMCtlr.py file On Wed, Jun 17, 2020 at 4:00 PM ahmed khalil via gem5-users < gem5-users@gem5.org> wrote: > Hi, I am a beginner in gem5

[gem5-users] gem5-users mailing list

Hi, Is there a problem with the mailing service? I do not get all the mails like before. I only get emails when someone replies to the question Currently, I have unsubscribed and subscribed to the list Also, I have already checked my spam but I miss all the first emails For example the email

[gem5-users] Re: encounter problems about cache options under SE mode

Hi, If this is gem5_19 then create a Jira issue for the bug. Also attach program binary or the link if the test is not part of gem5 repo, so people can reproduce issue again and see what breaks the behavior On Mon, Apr 27, 2020 at 3:17 AM yangyuqing--- via gem5-users < gem5-users@gem5.org>

Re: [gem5-users] Simulation OpenMP Applications with se.py

Hi, Before it was required to use m5 threads but now you are not required to use m5thread library On Tue, Mar 24, 2020 at 5:47 PM Muhammet Abdullah Soytürk < muhammetabdullahsoyt...@gmail.com> wrote: > Hi all, > > I am trying to simulate an openmp application with 4 cores in SE mode. It > seems

Re: [gem5-users] How to get the high-level architectural view of the system I am simulating?

Hi, Most accurate way is to read the code. O3CPU does have http://www.m5sim.org/Visualization but it will not give the diagram below. Also, learning gem5 tutorial is a great starting point to make your own architecture or the architecture shown below On Tue, Mar 24, 2020 at 1:13 PM Md Rubel

Re: [gem5-users] Resources about the x86 microops in gem5

Hi, You can refer Intel manual it gives you complete explanation Also somewhere in the code I don’t remember exactly but there was a reference to particular intel manual Also refer to older mail threads which tell about x86 instruction deciding On Sun, Mar 22, 2020 at 12:02 PM Anis Peysieux

Re: [gem5-users] Help with running backprop benchmark (Rodinia) on gem5-gpu

Hi, Can you paste your command line? On Fri, Mar 20, 2020 at 8:37 PM Anirudh wrote: > Hello, > > I would like some help running the backprop benchmark on AMD gem5-gpu. The > backprop benchmark is written in OpenCL. I am using g++ v 4.8. I have rocm > 1.6 installed. > > I am seeing this error: “

Re: [gem5-users] How can I make my custom x86 macro op be recognized from GCC

Hi, Instead macro op name use the opcode Eg __asm__(".byte 0xcc, 0x00, 0xcc"); You will need to have complete knowledge up on representing register names using opcode You can find it x86 intel manual On Thu, Mar 19, 2020 at 10:28 AM Muhammad Aamir wrote: > Hi everyone, > > I have made a

Re: [gem5-users] How to send write requests directly from Ruby L1 controllers?

Thanks ! On Sun, Mar 15, 2020 at 6:48 PM Kevin Dong wrote: > Hi everyone, > > I've solved this problem, and this is a note for the future readers: > > Instead of directly calling queueMemoryWrite() within the L1 controller, > though the type of its parent class, AbstractController, is as same

Re: [gem5-users] x86 multi-threaded test application behaviour

Hello Everyone, When I change the gcc/g++ version from 4.8 to 5.5, everything works fine! Best regards, Abhishek On Sat, Mar 14, 2020 at 6:01 PM Abhishek Singh < abhishek.singh199...@gmail.com> wrote: > Hello Everyone, > > I am using gem5-19, I tested > "tests/tes

Re: [gem5-users] Impact of using NonCachingSimpleCPU for profiling and creating checkpoints

:53 PM Ali Hajiabadi wrote: > Thanks for your reply. But se.py script checks that the CPU type is > non-caching. Is there a reason for that? Can I ignore those checks? > > On Sun, Mar 15, 2020 at 5:41 AM Abhishek Singh < > abhishek.singh199...@gmail.com> wrote: > >

[gem5-users] x86 multi-threaded test application behaviour

Hello Everyone, I am using gem5-19, I tested "tests/test-progs/threads/bin/x86/linux/threads" application, when I run the application using O3CPU and x86 using just one CPU, the application prints a statement specified in its source file which is "Validating...Success!" The source file can be

Re: [gem5-users] Impact of using NonCachingSimpleCPU for profiling and creating checkpoints

Hi, I would advise using Atomic Simple Cpu with “—caches” option to create Simpoints On Sat, Mar 14, 2020 at 5:35 PM Ali Hajiabadi wrote: > Hi everyone, > > What is the difference between using NonCachingSimpleCPU > and AtomicSimpleCPU in order to profile and taking simpoints and >

Re: [gem5-users] [Questions] how to use the new GEM5 website

Hi, Here is the ISCA 2011 gem5 slides http://pages.cs.wisc.edu/~markhill/cs757/Spring2012/includes/isca_pres_2011.pdf Best regards, Abhishek On Thu, Mar 5, 2020 at 4:43 PM chenboya wrote: > Hi, Everybody > > I found some difficulties in using the new gem5.org > For example, when I want to

Re: [gem5-users] 回复： Installing Shared Libraries to Image in Full Simulation

ain-doc/faq.html > > Even though using docker is also not required, it is highly recommended > since it is an easy way to deploy mongodb server. > > Regards, > Hoa Nguyen > > On Tue, Mar 3, 2020 at 10:02 PM Abhishek Singh < > abhishek.singh199...@gmail.com> wrote: >

Re: [gem5-users] 回复： Installing Shared Libraries to Image in Full Simulation

017-experiments$ git --version *git version 2.17.1* *How can I solve this error? * *Also, is it necessary to use docker and Celery and why? * Best regards, Abhishek On Wed, Mar 4, 2020 at 12:38 AM Abhishek Singh < abhishek.singh199...@gmail.com> wrote: > Hi Hao, > > I was able

Re: [gem5-users] 回复： Installing Shared Libraries to Image in Full Simulation

sr/. > > So, in install-spec2017.sh, we use a sed command to replace that default > path to /usr. > > In your case, the default path might be different, so you would need to > change the sed command in install-spec2017.sh to change the path to /usr. > > Regards, >

Re: [gem5-users] 回复： Installing Shared Libraries to Image in Full Simulation

uot; https://gem5art.readthedocs.io/en/latest/tutorials/spec2017-tutorial.html;? Best regards, Abhishek On Tue, Mar 3, 2020 at 8:52 PM Hoa Nguyen wrote: > Did you modify any file downloaded from gem5art repo? > > Regards, > Hoa Nguyen > > On Tue, Mar 3, 2020, 5:44 PM Abh

Re: [gem5-users] 回复： Installing Shared Libraries to Image in Full Simulation

n > > On Tue, Mar 3, 2020, 5:28 PM Abhishek Singh < > abhishek.singh199...@gmail.com> wrote: > >> Hi Hoa, >> >> For now, I will try to get a single-core. >> >> In Building the Disk Image Step, I get an error in compiling spec >> benchmarks in t

Re: [gem5-users] 回复： Installing Shared Libraries to Image in Full Simulation

at 7:53 PM Hoa Nguyen wrote: > Hi Abhishek, > > Yes, but the gem5 config only has one-core O3CPU. It could be tweaked to > multiple cores. > > Regards, > Hoa Nguyen > > On Tue, Mar 3, 2020, 3:48 PM Abhishek Singh < > abhishek.singh199...@gmail.com> wrote: >

Re: [gem5-users] 回复： Installing Shared Libraries to Image in Full Simulation

loads on O3CPU, and they ran successfully. > > We used gem5 19. > > Regards, > Hoa Nguyen > > On 3/3/20, Abhishek Singh wrote: > > Hi Hoa, > > Are you able to run on o3 cpu. > > Also, is it same gem5 commit as mentioned on the website? > > > &

Re: [gem5-users] gem5 X86 full system simulation with a recent version of ubuntu(18.04)

/npb/runscript.sh > > -Ayaz > > > On Tue, Mar 3, 2020 at 7:32 AM Abhishek Singh < > abhishek.singh199...@gmail.com> wrote: > >> Hello Ayaz, >> >> Can this image accept the rcS script provided using the Command line? >> >> For example in this way:

Re: [gem5-users] Question about CacheLoad/StorePorts

Hi, You are right about values of ports not being sensible. Set the values depending on the architecture (coffee lake, skylake, etc) Correct values of hardware components can be found in their manual On Tue, Mar 3, 2020 at 5:32 PM Chang Hyun Park wrote: > Thank you, Abhishek for your reply. >

[gem5-users] Tutorial on Porting Spec 2017 benchmarks to SE x86 cpu

Hello Everyone, Does anyone has ported spec 2017 benchmarks to SE gem5? If yes, can you share some steps? Currently, I am trying FS from gem5art but having some error with the scripts and I am trying to solve but FS mode according to gem5art, can be used only with 1 CPU in o3 CPU mode with the

Re: [gem5-users] gem5 X86 full system simulation with a recent version of ubuntu(18.04)

Hello Ayaz, Can this image accept the rcS script provided using the Command line? For example in this way: ./build/X86/gem5.opt --outdir=/home/abs218/whisper_gem5_setup/gem5_latest/scalibility_chkpt/ --stats-file=scalibility_chkpt.simout --dump-config=scalibility_chkpt.ini --redirect-stderr

Re: [gem5-users] 回复： Installing Shared Libraries to Image in Full Simulation

have been updated. > > Sorry about the confusion! > > Regards, > Hoa Nguyen > > > On Mon, Mar 2, 2020, 7:55 PM Abhishek Singh < > abhishek.singh199...@gmail.com> wrote: > >> Hi, >> >> This is the i got in past when I was trying to run SPEC in SE mod

Re: [gem5-users] 回复： Installing Shared Libraries to Image in Full Simulation

; of benchmarks didnt works. > It shown tha : > warn:instruction 'movntdq_Mo_Vo' unimplemented. >So,what I do for it? > And anyone can tell me how to deal with it? Thank you. > > -- 原始邮件 -- > *发件人:* "Abhi

Re: [gem5-users] Installing Shared Libraries to Image in Full Simulation

kernel with O3 clearly shows there exist some bugs > in gem5. We need to figure out those issues and fix them. > > Regards, > Ayaz > > On Sat, Feb 8, 2020 at 9:30 AM Abhishek Singh < > abhishek.singh199...@gmail.com> wrote: > >> Hi Ayaz, >> >> Thanks f

Re: [gem5-users] how to Run spec cpu 2006 on gem5-Fs

Hi, Follow this https://gem5art.readthedocs.io/en/latest/ On Mon, Mar 2, 2020 at 12:50 PM FARIDEH ZIAEE wrote: > Hi, > I need to run spec cpu 2006 on gem5-Fs mode but I don't know how to run it. > also ,according to site"" > https://yulistic.gitlab.io/2016/05/gem5-make-a-new-boot-image/"; I

Re: [gem5-users] Simulation does not stop, SE mode, 2 cpus, DerivO3CPU, ruby memory

Hi Arun, My bad the issue is still there Best regards, Abhishek On Mon, Mar 2, 2020 at 12:57 AM Abhishek Singh < abhishek.singh199...@gmail.com> wrote: > Hi Arun, > > I tested gem5_19 with classic cache x86 with O3CPU, both smt and multicore > simulations are workin

Re: [gem5-users] Simulation does not stop, SE mode, 2 cpus, DerivO3CPU, ruby memory

github.com/gem5/gem5/commit/bae0edb0d26dc6c4738855cf38e9a6a109ae8003 > I want to ask, whether this change ie *if (activeContexts ==0) *was a > bug or intentional for some other reason? > > Thanks > KP Arun > > On Tue, Feb 18, 2020 at 11:45 PM Abhishek Singh < > abhishek.singh199...@gmail

Re: [gem5-users] Question about CacheLoad/StorePorts

Hi, The configuration in source code are not decided depending on any specific architecture. One needs to change it depending on what architecture they are targeting. If you read papers who have used gem5, they always target a particular architecture (skylake, coffee lake, or any and or arm, etc)

Re: [gem5-users] Commit numbers/tags of previous stable version missing

t; If anyone else has any more information about this then it’d be much > appreciated. > > Kind regards > Bobby > > -- > Dr. Bobby R. Bruce > Room 2235, > Kemper Hall, UC Davis > Davis, > CA, 95616 > > On Mar 1, 2020, at 02:50, Abhishek Singh > wrote: &g

[gem5-users] Commit numbers/tags of previous stable version missing

Hello everyone, Can anyone provide me with the commit number of the previous stable version of gem5? This stable-tags has been removed recently like 3 days before. *Bobby and Jason*: Is there any reason for removing it? I am asking this because there are other simulators (mostly from Prof. Onur

Re: [gem5-users] Changing the "inParallelMode"

Hi, This work was started in past You can the progress information and steps required in this link http://www.m5sim.org/Parallel_M5 For now seeing the mailing I do not see anyone continuing this work, but there were people who had started working on this On Sun, Mar 1, 2020 at 2:25 AM YUCHEN

Re: [gem5-users] Develop branch on github

Bobby R. Bruce > Room 2235, > Kemper Hall, UC Davis > Davis, > CA, 95616 > > web: https://www.bobbybruce.net > > > On Fri, Feb 28, 2020 at 12:15 PM Abhishek Singh < > abhishek.singh199...@gmail.com> wrote: > >> Hello Bobby, >> >> Thank you for

Re: [gem5-users] Develop branch on github

ll, UC Davis > Davis, > CA, 95616 > > web: https://www.bobbybruce.net > > > On Fri, Feb 28, 2020 at 11:58 AM Abhishek Singh < > abhishek.singh199...@gmail.com> wrote: > >> Hello Everyone, >> >> Is there a way I can access develop branch

[gem5-users] Develop branch on github

Hello Everyone, Is there a way I can access develop branch on github? In the branches option and tag option, I can not find it. Also, on google what is this branch "feature-gcn3-model "? Best regards, Abhishek

Re: [gem5-users] Changing CPU type

Hi, What commit are you using? I got option 1 working on commit 2a98a994df296f818b05da90ba073d879562da04 You can find my commands here https://www.mail-archive.com/gem5-users@gem5.org/msg16795.html Best regards, Abhishek On Thu, Feb 27, 2020 at 12:50 PM niranjan soundararajan <

Re: [gem5-users] Linux boot

change the CPU to DeriveO3 after we boot > the system with kvm or timingsimple cou? > > Best regards. > > Yuan > > On Thu, Feb 27, 2020 at 1:10 AM Abhishek Singh < > abhishek.singh199...@gmail.com> wrote: > >> >> Hi, >> >> You can use KV

Re: [gem5-users] Linux boot

Hi, You can use KVM CPU, it will boot the system fast as it works on host machine speed. On Thu, Feb 27, 2020 at 1:00 AM niranjan soundararajan wrote: > Hello > > We are booting Ubuntu 18.0.4 and kernel 5.2.3 on x86_64 bit core. We are > running the following commandline > >

[gem5-users] Advise on Full System O3CPU support by gem5

Hello Everyone, I am looking to do Full System simulations that can support multithreaded applications. My only requirement is to use O3CPU (detailed/DerivO3CPU). I wanted to get advice from the community on which ISA and commit can support FULLY Full System simulations (multi-core,

Re: [gem5-users] Incorrect Result When Switching to Detailed CPU

Hey, Can you post details on commit number and ISA, so that we can reproduce the output and see On Wed, Feb 19, 2020 at 12:35 PM Muhammet Abdullah Soytürk < muhammetabdullahsoyt...@gmail.com> wrote: > Hi all, > > I am trying to simulate PageRank in full system simulation. The > application

Re: [gem5-users] Simulation does not stop, SE mode, 2 cpus, DerivO3CPU, ruby memory

Hi, A ticket is already opened about this at Jira https://gem5.atlassian.net/projects/GEM5/issues Arun: This repo (https://gem5.googlesource.com/amd/gem5/) will solve your problem On Tue, Feb 18, 2020 at 1:06 PM Ciro Santilli wrote: > Hi Arun, > > "I started using ruby memory model after

Re: [gem5-users] Multiprogrammed simulation in x86 SE in O3CPU is broken

/master/TESTING.md> > With this method, you can only run a single suite at a time. If you want > to run more than one uid, you must call ./main.py multiple times.. > Currently, you must specify --skip-build if you want to run a single suite > or run in batch mode. Otherwise, you will

[gem5-users] Multiprogrammed simulation in x86 SE in O3CPU is broken

Hello Everyone, The latest commit *135595a* is unable to support multi-core (multi-programmed) simulation on x86 O3CPU. I am pasting the terminal output showing a simple hello world program. The older commits of gem5 do support such multi-core (multi-programmed) simulation. Please note if we do

Re: [gem5-users] MultiProgrammed Workload X86 O3CPU error using SMT

With that said For x86 O3CPU, the multi program workload simulation is also broken. So basically one can not multi core simulation using x86 O3CPU with and without SMT. Also, to all developers who push commit to gem5, please do thorough testing as both of this support was working in older

Re: [gem5-users] Installing Shared Libraries to Image in Full Simulation

Hi Ayaz, Thanks for providing the image and kernel, I see on gem5art test results that the image can support at the most only one cpu for O3CPU model. Is that still the case ? I wanted to use this image for running multithreaded applications on x86 O3CPU FS mode. On Tue, Feb 4, 2020 at 4:12 PM

[gem5-users] Does KvmCPU gives timing information

Hello Everyone, Is there any notes or README that describes KvmCPU? Is it same as AtmoicCPU and the difference is, it is using the host computer's architectural resources? Also, can it be used to collect O3CPU timing information? Best regards, Abhishek

[gem5-users] Perform multithreaded simulation in x86 o3 cpu model

Hello Everyone, I want to simulate multithreaded application on gem5. I tried gem5 SE model using m5 threads. I tried simulating examples in m5threads using 2 threads, I used test_lock example particularly. The gem5 commit I used is *82f6d6e90* The simulation starts but exits on its own without

Re: [gem5-users] MultiProgrammed Workload X86 O3CPU error using SMT

0 at 10:46 AM Abhishek Singh < abhishek.singh199...@gmail.com> wrote: > Hi Giacomo, > > I tried your suggestion of using ( ";"), without SMT and trying > multi-programmed workload simulation. > I thought to test it using the hello world example, and I found some >

Re: [gem5-users] MultiProgrammed Workload X86 O3CPU error using SMT

ype=DerivO3CPU --mem-type=DDR4_2400_8x8 --mem-size=8GB > --sys-clock='2.6GHz' --cpu-clock='2.6GHz' --smt > -- > *From:* gem5-users on behalf of Abhishek > Singh > *Sent:* 05 February 2020 16:14 > *To:* gem5 users mailing list > *Subject:* [gem5-users]

[gem5-users] MultiProgrammed Workload X86 O3CPU error using SMT

Hello Everyone, I am using X86 ISA, Out of order CPU. I wanted to run a multi-programmed workload using SMT My command line 1 is: ./build/X86/gem5.opt configs/example/se.py -c tests/test-progs/hello/bin/x86/linux/hello;tests/test-progs/hello/bin/x86/linux/hello --caches --l2cache

Re: [gem5-users] [gem5-dev] Announcing the beta of gem5's new website

Hi Jason, Thanks for sharing the website. And a lot of thanks to all those who made this possible. I had one question: Is your tutorial updated to new function call names?for example to implement new cache replacement policy, your tutorial still use old format of defining function calls and its

Re: [gem5-users] ask for help about simulate with noncherentcahe

Hi yuan, In order to that, you need to call non-coherent cache instead of cache in config/common/Caches.py file. >From my experience I am able to use LLC as non coherent cache. Please note this is how I used in classic cache model. On Wed, Dec 18, 2019 at 11:54 AM 616653241 <616653...@qq.com>

Re: [gem5-users] [gem5-dev] gem5 stable release proposal [PLEASE VOTE!]

Hello Jason, Thanks for such a nice and detailed explanation. My votes are as follows: *I think master should be development* *I think gem5 should be released once per year* Best regards, Abhishek On Mon, Dec 16, 2019 at 2:50 PM Jason Lowe-Power wrote: > Hi all, > > As many of you have

Re: [gem5-users] What is the default coherence mechanism in gem5 for multicore systems?

- > *From:* gem5-users on behalf of Abhishek > Singh > *Sent:* 11 December 2019 16:32 > *To:* gem5 users mailing list > *Subject:* Re: [gem5-users] What is the default coherence mechanism in > gem5 for multicore systems? > > Hi, > The default is MI pr

Re: [gem5-users] What is the default coherence mechanism in gem5 for multicore systems?

Hi, The default is MI protocol in classic cache model, there are various protocols which you can find in build_opts directory. Also, you can find the build info by using —build-info flag. For example ./build/X86/gem5.opt —build-info On Wed, Dec 11, 2019 at 10:11 AM Francisco Carlos wrote: > Hi

Re: [gem5-users] Gem5 Cache

-- > *From: *"Abhishek Singh" > *To: *"gem5-users" > *Sent: *Wednesday, 11 December, 2019 10:03:25 > *Subject: *Re: [gem5-users] Gem5 Cache > > Check config/common/Caches.py > > On Tue, Dec 10, 2019 at 11:32 PM DURAIRAJ J <2016506...@annauniv.edu.in>

Re: [gem5-users] Disable pre-fetching in l2 cache

Hi, Prefetching will impact the replacement in a way it can bring non demand dead blocks which will not be referenced in the application and force evict a demand block. You can disable prefetchers by editing src/configs/common/Caches.py and setting the parameter “prefetcher” to NULL just for L2

Re: [gem5-users] How to suspend a packet in cache

Hi Majid, One way is the schedule the response of packet 1 to a later tick x( current tick + 1), when the tick x is the system time, you have some sort of a flag to check whether the packet 2 was serviced by L2 cache or not. If no packet 2 had arrived in that time frame, you again delay the

Re: [gem5-users] Stat of type Formula getting value from function

Hi Varun, Will this stat will be calculated on every tick? On Fri, Nov 29, 2019 at 7:01 PM Victor Kariofillis wrote: > Hi, > > I have created a Stat of type Formula. Since the formula is complicated, > instead of having it in the regStats file, I want to call another function > that returns

Re: [gem5-users] Running spec2000 benchmarks on se.py

There’s is no standard script provided by gem5 But u can search online or make your own On Wed, Nov 27, 2019 at 1:48 PM Charitha Saumya wrote: > Hi, > > How can I run the SPEC 2000 benchmarks with latest gem5? I can not find > any config script to do this. > I have SPEC 2000 binaries in alpha

Re: [gem5-users] Difference cpu clock and sys clock

s? > > > > I could not find the mechanism to set the [cpu, system] clocks separately. > > > > Regards > > > > JO > > > > > > *From:* gem5-users [mailto:gem5-users-boun...@gem5.org] *On Behalf Of > *Abhishek > Singh > *Sent:* 27 November 2019 00

Re: [gem5-users] X86 CLFLUSH Flush Cache Line Instruction

ason Lowe-Power had mentioned that > the same (secure bit) is used only for ARM ISA in GEM5 and not for X86 > ISA.. Am I missing something here? > > Bala > > On Mon, Nov 25, 2019 at 10:12 PM Abhishek Singh < > abhishek.singh199...@gmail.com> wrote: > >> Hey, &g

Re: [gem5-users] Difference cpu clock and sys clock

I always set it same System clock is for peripheral Most times we focus more on cpu clock On Mon, Nov 25, 2019 at 3:12 PM Nikos Giakoumoglou wrote: > What is the difference in cpu and sys clock? > Can’t figure it out from any file > > NG > ___ >

Re: [gem5-users] Warm up instructions in gem5

switching > > I am not sure fast forward can help me here. > > > > On Mon, Nov 25, 2019 at 9:55 PM Abhishek Singh < > abhishek.singh199...@gmail.com> wrote: > >> >> Is there any flag called “fast forward”? >> >> On Mon, Nov 25, 2019 at

Re: [gem5-users] Warm up instructions in gem5

of > But I am still not convinces all these flags are functional. Can someone > confirm gem5 supports this flag? and what CPU models are used before and > after switch? > > Thanks > > > > On Mon, Nov 25, 2019 at 9:50 PM Abhishek Singh < > abhishek.singh199...@gmai

Re: [gem5-users] Warm up instructions in gem5

If -s flag means fast forward then it’s correct. Check the correct flags using ./build/X86/gem5.opt config/example/se.py -h On Mon, Nov 25, 2019 at 9:46 PM Charitha Saumya wrote: > Hi, > > I want to run my x86 binary for 300M instructions from which 100M will be > for warming up the caches. I

Re: [gem5-users] X86 CLFLUSH Flush Cache Line Instruction

Hey, You can do that, just go to the decoder code and make the secure flag high The code should be located at src/arch/x86/isa/ On Mon, Nov 25, 2019 at 11:20 AM Muralidharan K wrote: > Hello, > > I am aware that the above instruction has been implemented in the latest > build of gem5, but

Re: [gem5-users] derivo3cpu issue

y.out > --benchmark_stderr=/home/abdkhail/aa/gem5/o1/povray.err > --cpu-type=DerivO3CPU --caches > -- > *From:* gem5-users on behalf of Abhishek > Singh > *Sent:* Friday, November 22, 2019 11:11:38 PM > *To:* gem5 users mailing list > *Cc:* gem5-us

Re: [gem5-users] derivo3cpu issue

Hey, What is the error and what is the command line? Can you run gdb and paste the back trace? Did you made any changes to baseline gem5? On Fri, Nov 22, 2019 at 5:54 PM ABD ALRHMAN ABO ALKHEEL < abdkeel...@hotmail.com> wrote: > Hello everyone, I am running the benchmark on gem5 and I got error

Re: [gem5-users] Assertion during full system emulation with checkpoint restore and standar switch option

Try January 2018 commit On Fri, Oct 18, 2019 at 2:10 PM Michail Mavropoulos < mavropo...@ceid.upatras.gr> wrote: > Hello all, > > I am using gem5 revision commit > 4c38c7c02aca9922d7f30f2f399bbe94c034eb59. > > I try to run a full system emulation, after restoring from a checkpoint > and using

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