of Rob
Schramm [rob.schr...@gmail.com]
Sent: Monday, November 28, 2022 7:29 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Storage protection keys
Cmg on the various codes
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.google.com%2Furl%3Fsa%3Dt%26source%3Dweb%26rct%3Dj%26url
SERV.UA.EDU] on behalf
> of Paul Gorlinsky [p...@atsmigrations.com]
> Sent: Friday, November 25, 2022 11:12 AM
> To: IBM-MAIN@LISTSERV.UA.EDU
> Subject: Re: Storage protection keys
>
> Would you consider that the applications were more like P-Code (
> ps
]
Sent: Friday, November 25, 2022 11:12 AM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Storage protection keys
Would you consider that the applications were more like P-Code ( pseudo-code )
... not that much different in principle to JAVA today
Would you consider that the applications were more like P-Code ( pseudo-code )
... not that much different in principle to JAVA today ?
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, November 25, 2022 10:28 AM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Storage protection keys
Thanks for the info Dana,
"For the record, there are no i-Server, or p-Servers any more. IBM Power
servers can run any combination of IBMi, AIX and Linux LPARS concurrently."
This reduc
Thanks for the info Dana,
"For the record, there are no i-Server, or p-Servers any more. IBM Power
servers can run any combination of IBMi, AIX and Linux LPARS concurrently."
This reduces the IBM "mainframe" product line to just two; Z and Power Servers.
( or is it one in reality ? The
On Thu, 24 Nov 2022 09:27:41 -0600, Paul Gorlinsky
wrote:
>
>It would also make good business sense that IBM would share as much tech as
>possible between the product lines of i-Server, p-Server and z-Server... in
>order to save costs.
>
For the record, there are no i-Server, or p-Servers
Apples and Oranges ... The final chip fab is usually the product of an
underlying chip designed set with additional customization.
Apple's M1 chip is a great example it is licensed ARM chip arch with lots
of enhancements. So it is the M1 built on an ARM.
The way chips have been designed
Monk
Sent: Wednesday, November 23, 2022 8:30 AM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Storage protection keys
I know this is super old information ... but given the discussion so far, it
seems reasonable to at least apply the same concept ...
"The storage-protect unit has a 6
This "Z is just Power" rumor has been around for quite a while, repeatedly
debunked, yet it persists. Anyone know where it came from? I've always
assumed that there were some gross similarities, and that some journo took
that and made it into "they're the same thing", but I have no real idea.
On Tue, 22 Nov 2022 11:36:34 -0600 Paul Gorlinsky
wrote:
:> there are also additional KEYS to manage the LPARs themselves and PREVENT
one LPAR from looking into the storage of another LPAR.
More likely thru shadow page tables as storage can be configured in
non-contiguous chunks.
--
Binyamin
On Wed, Nov 23, 2022 at 9:29 AM Paul Gorlinsky wrote:
> Engineers always think they can improve upon the works of others.
>
Sometimes they even succeed. :-)
--
Jay Maynard
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On 11/23/2022 9:29 AM, Paul Gorlinsky wrote:
Engineers always think they can improve upon the works of others.
so true, working for an airspace company many years ago I recall an off
the wall company called SCS, IIRC, Scientific computer Systems, that
sold us an engineering solution to
Seymour is correct. The POP or POO is the specification.
Any given processor could implement the specification differently. This
includes all the simulators and emulators that have been developed over the
years. When you add all the different hardware implementations, including GE,
Fujitsu,
[IBM-MAIN@LISTSERV.UA.EDU] on behalf of Joe
Monk [joemon...@gmail.com]
Sent: Wednesday, November 23, 2022 8:29 AM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Storage protection keys
I know this is super old information ... but given the discussion so far,
it seems reasonable to at least apply
@LISTSERV.UA.EDU
Subject: Re: Storage protection keys
Many thanks for that Jay. This would certainly seem the logical place to store
it.
I'm still a bit confused though. The pop section on Page-Table Entries (page
3-51 in the 13th edition...) does not mention this (though it does have a
unused byte
, 2022 at 05:04:08 PM GMT+1, Jay Maynard <
> > > jaymayn...@gmail.com> wrote:
> > >
> > > Each page table entry has a byte associated with it that stores the
> key,
> > > as
> > > well as the referenced and changed bits.
> > >
&
> >
> > Each page table entry has a byte associated with it that stores the key,
> > as
> > well as the referenced and changed bits.
> >
> > And yes, 4K page tables do soak up lots of memory, which is why later
> OSes
> > use 1M or 2M pages.
>
at stores the key,
> as
> well as the referenced and changed bits.
>
> And yes, 4K page tables do soak up lots of memory, which is why later OSes
> use 1M or 2M pages.
>
> On Tue, Nov 22, 2022 at 9:22 AM Ian Worthington <
> 047bb6801512-dmarc-requ...@listserv.ua.ed
ocode"
was still being used.
Jim Mulder z/OS Diagnosis, Design, Development, Test IBM Corp. Poughkeepsie NY
-Original Message-
From: Jim Mulder
Sent: Tuesday, November 22, 2022 10:01 PM
To: ibm-main@listserv.ua.edu
Subject: Re: Storage protection keys
My wife agrees with y
sday, November 22, 2022 8:54 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Storage protection keys
Interesting that you have to resort to a childish rant ... So totally
unprofessional ...
BTW if you read the documents you proved they actually prove my point ...
Dr. Gene Amdahl picked me to lead t
Interesting that you have to resort to a childish rant ... So totally
unprofessional ...
BTW if you read the documents you proved they actually prove my point ...
Dr. Gene Amdahl picked me to lead the design and build of his CMOS XA processor
for a reason ... My direct OS and hardware
of processor design.
Jim Mulder z/OS Diagnosis, Design, Development, Test IBM Corp. Poughkeepsie NY
-Original Message-
From: IBM Mainframe Discussion List On Behalf Of
Paul Gorlinsky
Sent: Tuesday, November 22, 2022 4:35 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Storage protection keys
On 11/22/2022 1:34 PM, Paul Gorlinsky wrote:
The BASIC CPU hardware for zServer is a collection of POWER PC processors with some
addition z Enhancements and the z is an EMULATOR because the last HARDWIRED CPU was
probably the S/360 & S/370 model 195.
The basic IBM Z hardware instructions
After doing more research, I will stand by my retort.
The BASIC CPU hardware for zServer is a collection of POWER PC processors with
some addition z Enhancements and the z is an EMULATOR because the last
HARDWIRED CPU was probably the S/360 & S/370 model 195.
Even Intel CPUs are Emulators
On Behalf Of
Paul Gorlinsky
Sent: Tuesday, November 22, 2022 12:37 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Storage protection keys
Present day z/Arch machines are the combination of several POWER PC chips
working together. With the inclusion of LPAR as the only mode to operate the
machine
Worthington [047bb6801512-dmarc-requ...@listserv.ua.edu]
Sent: Tuesday, November 22, 2022 11:22 AM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Storage protection keys
Yes, I understand that. What I do not understand is where they /are/ held. Is
a big chunk of storage partitioned off and made
The use of the word "KEYS" in caps to indicate a mechanism that protected
storage between the LPARs ...
As a stated, and you rightly corrected, It was more conjecture as I have no
insights into IBMs trade secrets.
I can only base my experience upon what we designed at Andor Systems, which was
Subject: Re: Storage protection keys
Present day z/Arch machines are the combination of several POWER PC chips
working together. With the inclusion of LPAR as the only mode to operate the
machine, logically, the storage management is more than just the old storage
keys, there are also
Present day z/Arch machines are the combination of several POWER PC chips
working together. With the inclusion of LPAR as the only mode to operate the
machine, logically, the storage management is more than just the old storage
keys, there are also additional KEYS to manage the LPARs themselves
r 2M pages.
>
> On Tue, Nov 22, 2022 at 9:22 AM Ian Worthington <
> 047bb6801512-dmarc-requ...@listserv.ua.edu> wrote:
>
> > Does anyone know where the storage protection keys are kept? It seems
> > that the processors maintain recent keys in the TLB to be accessed by the
&
the key, as
well as the referenced and changed bits.
And yes, 4K page tables do soak up lots of memory, which is why later OSes
use 1M or 2M pages.
On Tue, Nov 22, 2022 at 9:22 AM Ian Worthington <
047bb6801512-dmarc-requ...@listserv.ua.edu> wrote:
> Does anyone know where the storage p
22 at 9:22 AM Ian Worthington <
047bb6801512-dmarc-requ...@listserv.ua.edu> wrote:
> Does anyone know where the storage protection keys are kept? It seems
> that the processors maintain recent keys in the TLB to be accessed by the
> DAT, but where do they live when they're n
equ...@listserv.ua.edu> wrote:
> Does anyone know where the storage protection keys are kept? It seems
> that the processors maintain recent keys in the TLB to be accessed by the
> DAT, but where do they live when they're not in the TLB? Surely we need
> one byte per 4k page per address
"Storage keys are not part of addressable storage."
http://publibfp.dhe.ibm.com/epubs/pdf/a227832d.pdf page 3-9
Joe
On Tue, Nov 22, 2022 at 9:22 AM Ian Worthington <
047bb6801512-dmarc-requ...@listserv.ua.edu> wrote:
> Does anyone know where the storage protection keys
Does anyone know where the storage protection keys are kept? It seems that the
processors maintain recent keys in the TLB to be accessed by the DAT, but
where do they live when they're not in the TLB? Surely we need one byte per 4k
page per address space, which could be quite a bit
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