Peter
I am moving my code to the CBT shortly
The point of the code is the analysis of is when SDWAEC1 and SDWAEC2 are
different the relevant registers and PSW are those associated with SDWEC2 the
one that called SDWAEC1
I could not have done this without your help
Thank you
I know If you
Thanks
> On Apr 19, 2024, at 8:26 PM, Peter Relson wrote:
>
> The assertion of the subject is surely not correct. I do not choose to guess
> in just what way.
>
> Perhaps more important, the ALESERV is likely creating a system integrity
> violation in specifying access=public.
>
> Please
Peter
Thanks for help if I don’t find a RB in the RB chain I do a CSVQUERY in the
asid of SDWAPRIM if not I do NUCKLKUP
Moving my code to the CBT shortly
> On Apr 19, 2024, at 8:04 PM, Peter Relson wrote:
>
> I think the comment in SDWAEC1 is quite clear:
>
> Extended control PSW at time
> This approach seems riddled with system stability risks and I would advise
> against it.
>
> Rob Scott
> Rocket Software
>
> -----Original Message-
> From: IBM Mainframe Discussion List
> mailto:IBM-MAIN@LISTSERV.UA.EDU>> On Behalf Of
> Joseph Rei
Hi
Just tried to get access list token for the GRS Address space ASID 7
Got R15 = 0 and alet = 0, as well this was both on my zpdt system and on the
CBT real iron I believe z15 system
As well was running under TESTAUTH
Here is the code
*
I somehow made an assumption that SDWAEC1 was reflective of a value from an
RB namely an RBOPSW
Just go an abend with SDWARBAD and RBOPSW didn't match SDWAEC1 in fact
RBOPSW pointed to a WTO SVC 35 which was before execution of the ISGENQ
REQUEST=OBTAIN
Which caused the error ?
Thanks
ace terminates, which in the case of an
> INIT may be a while. For authorized batch jobs a TASK RESMGR on the job
> step task would be needed to clean up your resources.
> Wayne Driscoll
> Note: All opinions are strictly my own.
>
>> On Thu, Mar 14, 2024 at 9:12 AM Joseph
a "memory".
>
> It may or may not be due to a storage related problem.
>
> --
> Tom Marchant
>
>> On Wed, 13 Mar 2024 19:07:36 -0400, Joseph Reichman
>> wrote:
>>
>> Regarding the above message and I'll put down the entire text
>>
>>
So actually my code is ok its some clean up
I forgot at the end ?
Joe Reichman
On Thu, Mar 14, 2024 at 2:14 AM Brian Westerman <
brian_wester...@syzygyinc.com> wrote:
> The job that was running in that init had a memory related error, 878-10
> or worse, and the job and the initiator were both
Regarding the above message and I'll put down the entire text
$HASP311 JOER$RE-QUEUED AT END OF MEMORY AND HELD
Would any anyone know what causes it
Thanks
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icates the SVC number.
For a program check interrupt, RBINTCOD indicates the program interrupt code.
For other types of interrupts, RBINTCOD is not updated.
Jim Mulder
-Original Message-
From: IBM Mainframe Discussion List On Behalf Of
Joseph Reichman
Sent: Friday, March 8, 2024 12:02 PM
T
ְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר
>
>
> From: IBM Mainframe Discussion List on behalf
> of Joseph Reichman <05812645a43c-dmarc-requ...@listserv.ua.edu>
> Sent: Friday, March 8, 2024 12:02 PM
> To: IBM-MAIN@LISTSERV.UA.EDU
> Subject: Re: IRB interrupt code
> Jim Mulder
>
> -Original Message-
> From: IBM Mainframe Discussion List On Behalf Of
> Joseph Reichman
> Sent: Friday, March 8, 2024 11:09 AM
> To: IBM-MAIN@LISTSERV.UA.EDU
> Subject: IRB interrupt code
>
> I thought all list of all the interrupt codes wer
I thought all list of all the interrupt codes were in the z/os pops I looked
at chapter 6interruptions there was a description for a number of them
Just not a list with a code
Anyway for my IRB the previous RB which was my program PRB had RBINTCOD
value X'020008'
Where can I find out what
Peter thank you
I did a TESTAUTH ‘JOER.TEST.AUTHLIB(CESTAE)’
Then at the TESTAUTH prompt
Did LOAD ‘JOER.TEST.AUTHLIB(GRECOV)’
AT GRECOV.GRECOV.+0
Had a WAIT after the lock release
Grecov did get control
It had an SDWARBAD the X’40’ bit was on at the first status byte of the RB
RBSTAB1
Put wait after lock release my recovery got control
There is no SDWANAME only SDWAABRB RBCDE points to the IRB entry point +1
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ׁקֵּ֖ר
From: IBM Mainframe Discussion List on behalf of
Joseph Reichman <05812645a43c-dmarc-requ...@listserv.ua.edu>
Sent: Friday, March 1, 2024 11:23 AM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Recovery routine for IRB
Peter
Thanks for sugge
Rob
Think sterilization in this case is only for the purpose of putting the IRB on
the RB chain once thats don't the RB/IRB can run
Just have to have to make sure the TCB is still valid as Peter pointed out by
having a wait without being posted
Thanks
> On Mar 1, 2024, at 11:23 AM,
Peter
Thanks for suggesting that I put a wait after the release of the lock since
as Rob Scott pointed the estate will not run while the lock is held
I chose to use the CRIB because it returns an IRB or RB/IRB and I would like
to initialize the RB or IRB
Thank You
-Original Message-
t; נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר
>
> ____
> From: IBM Mainframe Discussion List
> mailto:IBM-MAIN@LISTSERV.UA.EDU>> on behalf of
> Joseph Reichman
> <05812645a43c-dmarc-requ...@listserv.ua.edu<mailto:05812645a43c-dmar
metz3<http://mason.gmu.edu/~smetz3>
> עַם יִשְׂרָאֵל חַי
> נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר
>
> ____
> From: IBM Mainframe Discussion List
> mailto:IBM-MAIN@LISTSERV.UA.EDU>> on behalf of
> Joseph Reichman
> <05812645a43
HI
I have tested my recovery routines in many different scenarios. My last step
was to test a asynchronous exit or an IRB. Since many people have told I
don't post my code I'll do so now.
I have tested the asynchronous exit or IRB and it has gotten control however
when I insert H'0' it abends
Tuesday, February 27, 2024, 6:30 PM, Joseph Reichman
> <05812645a43c-dmarc-requ...@listserv.ua.edu> wrote:
>
>
>
>
>
>
>
>
>
> I work for the IRS
>
>
>
> All the current production tax code is assembler they are trying to change t
What does my job
Have to do with the CBTTAPE
I will spell it out in clear cut letters
I WORK AS A TESTER FOR THE IRS
I have Zpdt personal edition license
> On Feb 27, 2024, at 6:39 PM, Tom Marchant
> <000a2a8c2020-dmarc-requ...@listserv.ua.edu> wrote:
>
> I very much doubt that he
updating shortly
Member Grecov was about 592 lines
It’s now over 2200
I added a lot
I look over my last posts in thread to see how I can improve my posts
Thanks all
On Feb 27, 2024, at 3:52 PM, Joseph Reichman mailto:reichman...@gmail.com> > wrote:
Perryman wrote:
> On Mon, 26 Feb 2024 20:24:09 -0500, Joseph Reichman
> wrote:
>
> > Thanks and I apologize if sone of my posts made it seem like I wasn’t
> listening to what you were telling me
>
> Joseph, you missed Peter's point. Clearly you don't understand this is
Peter
Thanks the history of this that Sam Golob asked me to update file 192 general
Recovery
As it was old and at the time it was written there were not any 64 bit
registers
I added a scenario of, if the abend occurred in a IBM service
Was this too much ?
Honestly couldn’t of done
Peter
My main objective of my posts were in regard to modifying file 192 general
recovery.
One of my modifications in the case where sdwaec1 and sdwaec2 have different
next address it is apparent that sdwaec1 ( PSW at time of error ) is not in the
users code but likely in a SVC or PC rtn (
This abend was caused by doing ISGENQ OBTAIN twice per Ed Jaffe suggestion
I’m now thinking if cannt get the info from the RB/CDE
I can try CSVQUERY
But truth is you right that still might not get me an answer
Because this particular module was in the NUCULES
I can do a NUCLKUP
That may
lin
> wrote:
>
> On 2024-02-23 07:32 AM, Joseph Reichman wrote:
>> Is this file copied from A RBOPSW if not the current TCB PSATOLD
>
> SDWAEC1 isn't a file.
>
>> Then from a TCB in the address space
>
> Then *what* from a TCB in the address space?
>
&
Is this file copied from A RBOPSW if not the current TCB PSATOLD
Then from a TCB in the address space
Then instead of starting at PSATOLD
I would be starting a ASXBFTCB
Thanks
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Almost finished my update to file 192 wonder if SETRP can retry in different
address space the doc says you can run it in AR mode
So if RETADDR=(RX) and access RX has an ALET ?
Just wondering ?
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Hi
What I was trying to do is that after you had helped me understand rb chain I
was trying to get the extents of the load module to ensure that SDWAEC1 and
SDWAEC2 fall in the range for the appropriate load module before I display the
offsets
thanks
-Original Message-
From: IBM
Hi
Would someone know what the above points to ? A double word size of an extent ?
Thank you
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Peter
Thank you for explaining it I really think I get it
I agree I can generalize a recovery I am changing file192 thinking of it as
estate
Including cases where there is abend in
1) SVC
2) PC
For these I am going to locate the user registers and off set
And include for all cases
the general
> registers. I havent checked how the top halves are handled.
>
> --
> Shmuel (Seymour J.) Metz
> http://mason.gmu.edu/~smetz3
> עַם יִשְׂרָאֵל חַי
> נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר
>
>
> From: IBM Mainframe Discus
gt; http://mason.gmu.edu/~smetz3
> עַם יִשְׂרָאֵל חַי
> נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר
>
>
> From: IBM Mainframe Discussion List on behalf of
> Joseph Reichman
> Sent: Sunday, February 4, 2024 11:45 AM
> To: IBM-MAIN@LI
ways IC04.
>
> --
> Shmuel (Seymour J.) Metz
> http://mason.gmu.edu/~smetz3
> עַם יִשְׂרָאֵל חַי
> נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר
>
>
> From: IBM Mainframe Discussion List on behalf of
> Joseph Reichman
> Sent: Sunday
Binyamin Dissen
wrote:
> On Sun, 4 Feb 2024 10:29:59 -0500 Joseph Reichman
> wrote:
>
> :>But thought S0C4 is a program check
>
> It is.
>
> It may be a pic-4,-10, or -11. If PIC-4, PSW was updated.
>
> An error recovery routine that messes up things is worse th
Can you for proposed that I understand differentiate between a program check
and abend
S0C1 is a program check S0C4 is not
I understand the abend SVC 13 is not a program check
But thought S0C4 is a program check
Thank you
> On Feb 4, 2024, at 10:27 AM, Joseph Reichman wr
on.gmu.edu/~smetz3
> עַם יִשְׂרָאֵל חַי
> נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר
>
>
> From: IBM Mainframe Discussion List on behalf of
> Michael Stein
> Sent: Sunday, February 4, 2024 4:06 AM
> To: IBM-MAIN@LISTSERV.UA.EDU
> Subject: Re:
It was my understanding probably erroneously that when a RB I guess I am
talking about a PRB gets interrupted and that can happen in one of two
instances
1) An SVC
2) A Program check e.g. S0C1,4,
Then if the interrupt is because of an SVC the program registers will be
saved in the new
Thanks
> On Jan 29, 2024, at 7:58 AM, Peter Relson wrote:
>
>
> Is there any way to know whether this is an SVC or abend
>
> I mean I know for SVC the length must be 2 but that doesn't mean it cannot
> be a abend
>
>
> Abend is an SVC. So you could conceivably look at RBINTCOD for
Hi
Is there any way to know whether this is an SVC or abend
I mean I know for SVC the length must be 2 but that doesn't mean it cannot
be a abend
Thanks
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A SYNCH/X being a PRB/RB would RBCDSYNC being on identify that RB from a
sync
thanks
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:38:10 -0500 Joseph Reichman
> wrote:
>
> :>Just wondering is there any recovery for a program running RMODE 64 don't
> :>see that with ESTAE or SETFRR
>
> CVTBSM0F
>
> :>As more and more services run above the bar
>
> :>More so SDWAEC1 and SDWAEC2 a
Just wondering is there any recovery for a program running RMODE 64 don't
see that with ESTAE or SETFRR
As more and more services run above the bar
More so SDWAEC1 and SDWAEC2 are only 8 bytes
thanks
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I had two main objectives in updating file 192
First in amode 64 display 64 gpr
Second when a abend occurs in a IBM service
Be it PC or SVC
Report on where in the user program this occurred
For SVC this would be in the RB
For PC ( which are normally space switching as well as stacking )
Thanks all
I’m trying to report where whitin the service it abended and where the service
was called I know most are space switching stacking routines
My SDWA should therefore contain different entries for SDWAEC1 and SDWAEC2
Thank you
> On Jan 19, 2024, at 8:46 AM, Peter Relson wrote:
>
>
Hi
I am looking to cause an abend in IBM Service that is invoked by a PC call
(bad parameters) so as to test out Estate Type Recovery for CBT file 192
If anyone has an example would appreciate it
Thanks
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I chain backward as its the only way to do it wrapping around tcbrbp and next
rb had the registers in the prefix it had SVC 12 maybe SVC 42 issued that
Thank you
> On Jan 17, 2024, at 4:02 PM, Peter Relson
> <056a472f7cb4-dmarc-requ...@listserv.ua.edu> wrote:
>
> sdawgrsv wasn’t in
Tom
You correct chasing all the way back I got to the next RB and the regs were
there
Thanks
> On Jan 16, 2024, at 2:50 PM, Joseph Reichman wrote:
>
>
> All
>
> I can say logic would dictate that If I matched the PSW ie SDWAEC1 == RBOPSW
>
> The error r
the next RB?
--
Tom Marchant
On Tue, 16 Jan 2024 09:43:16 -0500, Joseph Reichman wrote:
>I was running under TESTAUTH
>
>I produced an abend in a space switching pc stacking routine
>
>SDWAEC2 matched up with the linkage stack PSW
>
>SDWAEC1 matched up with RBOPSW of SDWARBAD
values in the SDWA,
but perhaps Peter can clarify.
--
Shmuel (Seymour J.) Metz
http://mason.gmu.edu/~smetz3
עַם יִשְׂרָאֵל חַי
נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר
From: IBM Mainframe Discussion List on behalf of
Joseph Reichman
Sent: Tuesday, January 16, 202
> --
> Shmuel (Seymour J.) Metz
> http://mason.gmu.edu/~smetz3
> עַם יִשְׂרָאֵל חַי
> נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר
>
>
> From: IBM Mainframe Discussion List on behalf of
> Joseph Reichman
> Sent: Tuesday, January 16, 202
>
> For SRB mode I'm not sure how much is GUPI.
>
> --
> Shmuel (Seymour J.) Metz
> http://mason.gmu.edu/~smetz3
> עַם יִשְׂרָאֵל חַי
> נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר
>
>
> From: IBM Mainframe Discussion List on behalf
Peter
By you pointing out that the entry descriptor
Was at the end of the linkage stack you were able to locate my error
As I assumed that STCBLSDP which points to the entry descriptor was also the
begging point of the linkage stack but it was not
Thank you for your help
> On Jan 15,
Peter
Its my understanding that everything in the SDWA is copied from another control
block somewhere in the case of SDWAEC2 you helped me locate that in the linkage
stack.
For SDWAEC1 I was able to locate that in the RBOPSW of SDWARBAD
My logic tells me that PSW and REGS go together but
Peter
Would you know where I could find that info
Thanks
> On Jan 15, 2024, at 2:32 PM, Peter Relson
> <056a472f7cb4-dmarc-requ...@listserv.ua.edu> wrote:
>
> Here is the SDWA as you can see the PSW matches how come the registers
> don't?
> Because the registers are not saved in the
Hi
Figure out my PSW problems but I would think that if SDWAEC1 equals RBPOSW
then SDWAGRSV should then match TBOPSW
Here is the SDWA as you can see the PSW matches how come the registers
don't?
thanks
L 3R? L(240) XC
7F6676D8. 7F667B0C 840F8000 FF84002A *".#.dd..*
Found it
Part of the problem was in TEST I was doing a list the SDWAEC2 had 0704
while the Linkage stack 070C
But the reason for that was bit 12 is on for 8 byte PSW and off as in the
linkage stack for 16 byte PSW
-Original Message-
From: IBM Mainframe Discussion List On
Thank you.
You are correct in my error however I do remember that I what I used as a
starting point was STCBLSDP and from memory it pointed to a X'8C' which is
branch state entry.
Regardless bumping down by X'128' I got to a X'89' is a header the doc say
that decrementing that would bring
e resulting SYSMDUMP.
> Look at the formatted linkage stack entries in the dump and compare that to
> storage.
>
> --
> Tom Marchant
>
>> On Wed, 10 Jan 2024 10:18:42 -0500, Joseph Reichman
>> wrote:
>>
>> Hi
>>
>> I am using a shar
Hi
I am using a share PDF as a guide "Dul Address Space & Linkage Stack" as
guide to looking thru a WU Linkage Stack
In the case of a TCB I believe the current is pointed to by STCBLSDP
This is I understand it points to the header of which there four different
types each of X'128' bytes in
IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Help Trying to determine where abend occurred / unable to find
linkage stack entry
On Mon, 8 Jan 2024 at 19:20, Joseph Reichman mailto:reichman...@gmail.com> > wrote:
> After getting an abend with SDWAEC2 (different from SDWAEC1) I
> observed SDW
Thanks all I did was decrement X’128’
> On Jan 8, 2024, at 10:08 PM, Tony Harminc wrote:
>
> On Mon, 8 Jan 2024 at 19:20, Joseph Reichman wrote:
>
>> After getting an abend with SDWAEC2 (different from SDWAEC1) I observed
>> SDWAXFLG to be X'92' that means SDWAEC2 p
After getting an abend with SDWAEC2 (different from SDWAEC1) I observed
SDWAXFLG to be X'92' that means SDWAEC2 psw came from the linkage stack
Looking at the STCB field STCBLSDP I started going back ward by X'128' a
linkage stack entry and was unable to find a marching PSW
THANKS
צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר
>
> ____
> From: IBM Mainframe Discussion List on behalf of
> Joseph Reichman
> Sent: Tuesday, January 2, 2024 11:36 AM
> To: IBM-MAIN@LISTSERV.UA.EDU
> Subject: Why do I have IEE159E MESSAGE WAITING
>
> HI
&g
HI
I have the following message on the console
IEE612I CN=C908 DEVNUM=0908 SYS=S0W1
IEE163I MODE= RD IEE159E MESSAGE
WAITING
Looking at my parmlib definition
I have CON(N) and DEL(RD)
Wondering why this happening
CONSOLE
Peter
I understand you are correct the only way to get that information if I ran the
CSVQUERY as an SRB
The documentation says Task or SRB
Thank you
> On Jan 2, 2024, at 10:12 AM, Peter Relson wrote:
>
>
>>
>> the doc says I can issue CSVQUERY in AR mode I might try to put SDWAPRIM
Peter thank you
Just thinking out loud if I wanted to get infoformation about the load module /
pc rtn
As the Estae recovery is now running in the home address space and when it is
running home=primary=secondary
I am thinking the doc says I can issue CSVQUERY in AR mode I might try to put
Hope sone corrects me if I am wrong
So If ESTAE is established before a stacking space switching PC rtn
And that pc RTN incurs abend then SDWAEC2 would contain the next seq inst in
the HOME address space following the PC instruction in the home address space
Correct ? while SDWAEC1 would
Thanks this was a stacking space switch pc rtn
> On Dec 31, 2023, at 1:36 PM, Walt Farrell wrote:
>
> Have you looked at the descriptions of the two fields?
>
> From https://www.ibm.com/docs/en/zos/2.1.0?topic=us-important-fields-in-sdwa
> I see:
>
>
> SDWAEC1
>This field contains the
kef>
From: IBM Mainframe Discussion List on behalf of
Binyamin Dissen
Sent: Sunday, December 31, 2023 12:46:51 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Help Trying to determine where abend occurred
Code would be in the primary address space.
On Sun, 31 Dec 2023 12:28:21 -0500
Hi
First, I want to apologize for spelling error for " detainee SDWAEC1" that
should be data name.
Just briefly looking at the SDWA SDWARC1 points to the control registers at
the time of error I guess I can interrogate 3 & 4 see if they are different
with control register 4 being primary.
Hi
I have a Space Switching PC routine which I caused an abend
This the code that caused it
LLILF 15,X'7000'
SVC 42
I don't have a ARR covering it However I do a estate in the program that
issued PC Instruction to a space switching routine where the above
R15 has bit 63 on I would assume
> On Dec 26, 2023, at 8:10 AM, Joseph Reichman wrote:
>
> Thank you
>
> Still working on CBT file 192 general recovery
>
> Routine
>
>> On Dec 26, 2023, at 8:08 AM, Peter Relson wrote:
>>
>>
>> when
Thank you
Still working on CBT file 192 general recovery
Routine
> On Dec 26, 2023, at 8:08 AM, Peter Relson wrote:
>
>
> when you say not every CDE is built by z/os are you referring to the
> IDENTIFY Macro...?
>
>
> No I am not. IDENTIFY is part of z/OS.
> I am referring to
RP
instruction
And have your recovery set it up before returning to RTM
Thanks
> On Dec 25, 2023, at 12:18 PM, Joseph Reichman wrote:
>
>
> Thank you
>
> Peter I started looking at it while trying to enhance the GRECOV
>
>>> On Dec 25, 2023, a
ָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר
>
>
> From: IBM Mainframe Discussion List on behalf
> of Joseph Reichman
> Sent: Sunday, December 24, 2023 6:34 PM
> To: IBM-MAIN@LISTSERV.UA.EDU
> Subject: CDE Extension for RMODE 64
>
> HI
>
> If bit CDCEX in the C
HI
If bit CDCEX in the CDE meaning there is an CDE extension would that imply
the module is RMODE 64 since CDXEntpt64 is a double word
thanks
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It seems to me that SDWA has values from the home address space such as
SDWARBAD
If you are looking for entry point modname if primary CSVQUERY would give you
that
> On Dec 19, 2023, at 6:35 PM, Binyamin Dissen
> wrote:
>
> Retry means retry the UOW, not (necessarily) the failed
Just let me point out the SDWA didn’t have SDWAEPA or SDWANAME I was able to
get that info from CSVQUERY using SDWANXT1 as the inaddr parm
Thanks
> On Dec 17, 2023, at 11:50 AM, Ed Jaffe wrote:
>
> On 12/17/2023 4:59 AM, Peter Relson wrote:
>> I'd make it "almost always".
>>
>> The case
Understood I look to do better
Thanks
> On Dec 17, 2023, at 7:59 AM, Peter Relson wrote:
>
> Ed J wrote
>
> Always code PLISTVER=MAX on the list form but (based on recent
> experience) *never* code it on the execute form of a macro unless you
> want to risk things not working as expected
parameter list
and GPR/AR values just prior to CSVQUERY being invoked?
Rob Scott
Rocket Software
-Original Message-
From: IBM Mainframe Discussion List On Behalf Of
Joseph Reichman
Sent: Friday, December 15, 2023 12:46 AM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: CSVQUERY in ARR routine ret
quot;) to ensure that you have the basic plumbing correct?
> (o) Have you dumped (or breakpointed) the module to examine the parameter
> list and GPR/AR values just prior to CSVQUERY being invoked?
>
> Rob Scott
> Rocket Software
>
> -Original Message-
> From: IBM M
Hi
I noticed a lot of the info regarding to the abending programs in a ARR
recovery routine( for a space switching pc rtn) point to the Home address
space such as SDWARBAD that address is from the home address space RB
Wanting to get info on the PC rtn running in Primary I coded a CSVQUERY
It’s the pc rtn not the code that sets up the oc rtn
Thanks
> On Dec 6, 2023, at 4:01 AM, Binyamin Dissen
> wrote:
>
> On Tue, 5 Dec 2023 20:23:47 GMT "esst...@juno.com" wrote:
>
> :>SET ETDEF has a parameter for an Associated Recovery Routine (ARR)
> :>If You develop an ARR, I would be
th now and some documentation.
> .
> -- Original Message --
> From: Joseph Reichman
> To: IBM-MAIN@LISTSERV.UA.EDU
> Subject: Parameters to ARR routine
> Date: Tue, 5 Dec 2023 14:36:06 -0500
>
> Doesn’t seem like ETDEF has a
Doesn’t seem like ETDEF has a param for the parameters list for ARR’s
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Sorry meant ETCRE
> On Dec 5, 2023, at 8:55 AM, Joseph Reichman wrote:
>
> Got it I have to pass the token from ETCON returned in register 0 some how
> to the client
>
> Thanks
>
>> On Dec 5, 2023, at 8:13 AM, Peter Relson wrote:
>>
>>
>> wher
Got it I have to pass the token from ETCON returned in register 0 some how to
the client
Thanks
> On Dec 5, 2023, at 8:13 AM, Peter Relson wrote:
>
>
> where you specify an asid indicating what address space you want to provide
> this service to
>
>
> You don't "specify". You provide a
Hi
I have been looking over syncrounes cross memory or PC rtn’s
What I seem to be missing is where you want to make that service available to
certain address spaces
So you code on the LXRES SYSTEM=NO
But I don’t see any where where you specify an asid indicating what address
space you
The reason it hung was when I started to debug the recovery I had NOT linked it
REUS
The way I debug I do a TEST command
For the driving code
LOAD the recovery module and do a breakpoint at +0
Thus everytime the module was invoked a new copy was loaded
Sorry
> On Nov 29, 2023, at 11:32 AM,
d by a length & eyecatcher. My recovery diagnostics find the reg
> (R12 for my programs) that is within 12K of the failing address and verify
> there is a J or B.
>
> A third option is to give sample code that requires user mods in the case
> they don't follow standard conventions.
&
y diagnostics find the
> reg (R12 for my programs) that is within 12K of the failing address and
> verify there is a J or B.
>
> A third option is to give sample code that requires user mods in the case
> they don't follow standard conventions.
>
> You should ask the group
> --
> Shmuel (Seymour J.) Metz
> http://mason.gmu.edu/~smetz3
> עַם יִשְׂרָאֵל חַי
> נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר
>
>
> From: IBM Mainframe Discussion List on behalf of
> Joseph Reichman
> Sent: Tuesday, November 28,
If then abend occurred while the user was in amode 64
That’s it
> On Nov 28, 2023, at 12:14 PM, Jon Perryman wrote:
>
> On Tue, 28 Nov 2023 08:48:23 -0500, Joseph Reichman
> wrote:
>
>> Let then be specific
>>
>> The first thing I do is get the low and high addr
.) Metz
> http://mason.gmu.edu/~smetz3
> עַם יִשְׂרָאֵל חַי
> נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר
>
>
> From: IBM Mainframe Discussion List on behalf
> of Joseph Reichman
> Sent: Tuesday, November 28, 2023 8:48 AM
> To: IBM-MAI
Peter
Let then be specific
The first thing I do is get the low and high address of the program The
program name is being passed as a parm to the Estae routine
The case of where the abend happened in the program is handled nicely by
file 192
The case of where the error PSW is not in the program
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