[Default] On 9 Sep 2020 16:16:01 -0700, in bit.listserv.ibm-main
dspiegel...@hotmail.com (David Spiegel) wrote:
>Hi Clark,
>Did you run MVS on a 4341?
>If yes, which version?
Headquarters normally did our MVT sysgens for us so this was the first
MVT sysgen I had done. After checking with Paul
e Bradshaw <032fff1be9b4-dmarc-requ...@listserv.ua.edu>
> Sent: Wednesday, September 9, 2020 4:56 PM
> To: IBM-MAIN@LISTSERV.UA.EDU
> Subject: Re: Architectural Level Sets
>
> I think this happened with the move to MVS/XA as XA does not recognise a
> BC mode PSW.
> So I
Hi Clark,
Did you run MVS on a 4341?
If yes, which version?
Thanks and regards,
David
On 2020-09-09 19:12, Clark Morris wrote:
[Default] On 9 Sep 2020 14:47:15 -0700, in bit.listserv.ibm-main
sme...@gmu.edu (Seymour J Metz) wrote:
In XA mode the problem is the SIO instruction. DOS.360,
[Default] On 9 Sep 2020 14:47:15 -0700, in bit.listserv.ibm-main
sme...@gmu.edu (Seymour J Metz) wrote:
>In XA mode the problem is the SIO instruction. DOS.360, OS/360, OS/VS, etc.
>don't support SSCH. Does OS/360 need BC when you sysgen for S/370? I'm
>certain;ly not aware of such a dependency
From: IBM Mainframe Discussion List on behalf of
Lennie Bradshaw <032fff1be9b4-dmarc-requ...@listserv.ua.edu>
Sent: Wednesday, September 9, 2020 4:56 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Architectural Level Sets
I think this happened with the move to MVS/XA as X
rse. Let's see what the IBM oracles tell us.
>
> Lennie Dymoke-Bradshaw
>
> -Original Message-
> From: IBM Mainframe Discussion List On Behalf
> Of Mark S Waterbury
> Sent: 09 September 2020 18:35
> To: IBM-MAIN@LISTSERV.UA.EDU
> Subject: Re: Architectural Level Sets
-Bradshaw
-Original Message-
From: IBM Mainframe Discussion List On Behalf Of
Mark S Waterbury
Sent: 09 September 2020 18:35
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Architectural Level Sets
To add to this thread ...
I would like to know at what point during the evolution from S/370 to S
.) Metz
http://mason.gmu.edu/~smetz3
From: IBM Mainframe Discussion List on behalf of
Mark S Waterbury <01c3f560aac1-dmarc-requ...@listserv.ua.edu>
Sent: Wednesday, September 9, 2020 1:35 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Architectural
z13 will IPL a 24 bit O/S. z14 will not support a 24 bit DAT.
ZZSA and non-virtual memory utilities should still run.
On Wed, Sep 9, 2020 at 12:35 PM Mark S Waterbury
<01c3f560aac1-dmarc-requ...@listserv.ua.edu> wrote:
>
> To add to this thread ...
>
> I would like to know at what point
To add to this thread ...
I would like to know at what point during the evolution from S/370 to S/370-XA
to S/390 to zSeries, did the architecture stop supporting IPL of any OS that
runs in "BC mode" or that starts out in BC mode, before setting up page and
segment tables and control registers
On 2020-09-05 2:11 AM, Jim Mulder wrote:
MVS had simulation for DAS in its program check handler, which
allowed SP1.2 and its successors to run on machines which did not
have DAS. DAS was first implemented via a microcode update
on the 3033. It was never implemented on 158 and 168.
Well,
0 19:40
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: [EXTERNAL] Re: Architectural Level Sets
It was probably some model of the 470V and MVS/SP 1.3.
--
Shmuel (Seymour J.) Metz
https://urldefense.proofpoint.com/v2/url?u=http-3A__mason.gmu.edu_-7Esmetz3=DwIGaQ=UrUhmHsiTVT5qkaA4d_oSzc
, Test IBM Corp.
Poughkeepsie NY
"IBM Mainframe Discussion List" wrote on
09/04/2020 06:47:52 AM:
> From: "Greg Price"
> To: IBM-MAIN@LISTSERV.UA.EDU
> Date: 09/04/2020 11:45 AM
> Subject: Re: Architectural Level Sets
> Sent by: "IBM Mainframe Discussion
[Default] On 4 Sep 2020 03:50:04 -0700, in bit.listserv.ibm-main
greg.pr...@optusnet.com.au (Greg Price) wrote:
>Hi - regarding several points in this thread...
>
>What I think I know:
>
>MVS 3.8 had:
>- MF/1 (component prefix IRB) writing the SMF type 7n records
>- physical swapping only
>-
I don't see my reply here, so I will post it again. Check out my page
https://jlelliotton.blogspot.com/p/cmos-processor-table.html
Regards, Jim
--
For IBM-MAIN subscribe / signoff / archive access instructions,
send email to
W dniu 03.09.2020 o 17:37, Jim Elliott pisze:
Tony,
Check my CMOS Processor Table page at
https://jlelliotton.blogspot.com/p/cmos-processor-table.html. I have the z/OS
and z/VM level sets listed there.
Comments to the table:
1. z/OS 1.1-1.5 were able to run on 9672 machines. z/OS 1.6 and
Hi - regarding several points in this thread...
What I think I know:
MVS 3.8 had:
- MF/1 (component prefix IRB) writing the SMF type 7n records
- physical swapping only
- sequential SMF data sets ("TCLOSE" anyone?)
SE1 and SE2 were free (as in zero dollars) but licensed.
MVS/SE2 had
- RMF
__
> From: IBM Mainframe Discussion List on
> behalf of Jesse 1 Robinson
> Sent: Thursday, September 3, 2020 1:56 PM
> To: IBM-MAIN@LISTSERV.UA.EDU
> Subject: Re: Architectural Level Sets
>
> It's almost Friday. Back in the day when IBM had competitors in the
>
Subject: Re: Architectural Level Sets
It's almost Friday. Back in the day when IBM had competitors in the hardware
game, I worked at TRW Credit Data, ancestor of Experian. We had an Amdahl
something-or-other. I was a baby sysprog at the time, so some details are
fuzzy. A new iteration of MVS
-Original Message-
From: IBM Mainframe Discussion List On Behalf Of
Peter Relson
Sent: Thursday, September 3, 2020 9:16 AM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: (External):Re: Architectural Level Sets
CAUTION EXTERNAL EMAIL
I was thinking more along the lines of things that prevented
I was thinking more along the lines of things that prevented earlier
operating systems from even IPLing on newer boxes. Such as z13 is the
last processor to have ESA/390 mode
It depends how much earlier you are thinking of. A z/OS prior to OS/390
R10 would not work on a machine that is
Tony,
Check my CMOS Processor Table page at
https://jlelliotton.blogspot.com/p/cmos-processor-table.html. I have the z/OS
and z/VM level sets listed there.
Regards, Jim
--
For IBM-MAIN subscribe / signoff / archive access
0 was also the first machine to mandate the use of LPARs.
Lennie Dymoke-Bradshaw
-Original Message-
From: IBM Mainframe Discussion List On Behalf Of R.S.
Sent: 02 September 2020 15:37
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: [EXTERNAL] Re: Architectural Level Sets
W dniu 02.09.2020 o 1
I think the z990 was also the first machine to mandate the use of LPARs.
Lennie Dymoke-Bradshaw
-Original Message-
From: IBM Mainframe Discussion List On Behalf Of R.S.
Sent: 02 September 2020 15:37
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: [EXTERNAL] Re: Architectural Level Sets
W dniu
W dniu 02.09.2020 o 15:08, Tony Thigpen pisze:
Peter, thanks.
But, my original question was not worded well. What I am really
looking for is:
What major feature change prevented older operating system versions
from running on the newer box.
For example: What changed on the z990 that forced
@LISTSERV.UA.EDU
Subject: Re: Architectural Level Sets
Page 7-31 says the only condition for XA is the "move-inverse facility"
has to be installed...
http://secure-web.cisco.com/1SPpJ14i6yPSxJtwCH2bDWOIflkX4XXef21JUr5kfop
Peter, thanks.
But, my original question was not worded well. What I am really looking
for is:
What major feature change prevented older operating system versions from
running on the newer box.
For example: What changed on the z990 that forced the use of the z990
compatability feature?
I
What CPU's were involved with each level, and what was the real
underlying item changed on the CPU that forced a new level?
No one seems to have answered Tony's question.
For z/OS V2R1 and onward, the information can be found in
z/OS Planning for Installation -> Preparing the target system
_
> From: IBM Mainframe Discussion List on behalf
> of Tony Thigpen
> Sent: Tuesday, September 1, 2020 10:28 PM
> To: IBM-MAIN@LISTSERV.UA.EDU
> Subject: Re: Architectural Level Sets
>
> And, to make matters worse, IBM reinstated the MVCIN on later processors
> after having
List on behalf of
Jesse 1 Robinson
Sent: Tuesday, September 1, 2020 9:36 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Architectural Level Sets
Instructions come and--believe it or not--instructions go. I once read some doc
on a newly introduced instruction. Don't remember the timeframe
Mainframe Discussion List on behalf of
Tony Thigpen
Sent: Tuesday, September 1, 2020 10:28 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Architectural Level Sets
And, to make matters worse, IBM reinstated the MVCIN on later processors
after having dropped it for at least one machine built after the 43xx
of
Mike Schwab
Sent: Tuesday, September 1, 2020 10:56 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Architectural Level Sets
Well, this is what confused me. OS/VS1 1.7 was released to run on the IBM 4300.
VS2 is multiple address spaces, vs VS1 is a single 16MB address space, correct?
https
, 2020 11:22 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Architectural Level Sets
On 9/1/2020 6:36 PM, Jesse 1 Robinson wrote:
> As for a vanishing instruction, I once wrote some code using the Move Inverse
> (MVCIN) instruction, which greatly simplified scanning data for a terminating
>
From: IBM Mainframe Discussion List on behalf of Joe
Monk
Sent: Wednesday, September 2, 2020 12:26 AM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Architectural Level Sets
"WTF? DAS requires MVS/SP."
Nope. :)
It is available via USERMOD in MVS 3.8J.
Joe
On Tue, S
Sent: Wednesday, September 2, 2020 12:27 AM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Architectural Level Sets
"MVS didn't use 2KiB pages,"
Yes, MVS 3.8J does use 2KB pages.
Joe
On Tue, Sep 1, 2020 at 7:20 PM Seymour J Metz wrote:
> MVS didn't use 2KiB pages, so I never paid
IBM's brief flirtation with extended real addressing (26-bit addressing)
in the IBM 3033, 3081, and a few models thereafter was quirky. IBM pretty
quickly dropped extended real addressing once XA debuted.
Back to Tony's original question, I think an "Architectural Level Set" is
difficult to
Diagnosis, Design, Development, Test IBM Corp.
Poughkeepsie NY
"IBM Mainframe Discussion List" wrote on
09/02/2020 12:26:37 AM:
> From: "Joe Monk"
> To: IBM-MAIN@LISTSERV.UA.EDU
> Date: 09/02/2020 01:38 AM
> Subject: Re: Architectural Level Sets
> Sent
ort for
>16MB of real stroage.
Jim Mulder z/OS Diagnosis, Design, Development, Test IBM Corp.
Poughkeepsie NY
"IBM Mainframe Discussion List" wrote on
09/02/2020 12:27:34 AM:
> From: "Joe Monk"
> To: IBM-MAIN@LISTSERV.UA.EDU
> Date: 09/02/2020 01:29 AM
>
M Mainframe Discussion List on behalf
> of Mike Schwab
> Sent: Tuesday, September 1, 2020 5:25 PM
> To: IBM-MAIN@LISTSERV.UA.EDU
> Subject: Re: Architectural Level Sets
>
> Well, XA+ machines only supported 4K pages / 1M segments and not 2K
> pages / 64K segments. Then D
> http://mason.gmu.edu/~smetz3
>
>
>
> From: IBM Mainframe Discussion List on behalf
> of Joe Monk
> Sent: Tuesday, September 1, 2020 5:55 PM
> To: IBM-MAIN@LISTSERV.UA.EDU
> Subject: Re: Architectural Level Sets
>
> 370 supported DAS (
Subject: Re: Architectural Level Sets
On 9/1/2020 6:36 PM, Jesse 1 Robinson wrote:
> As for a vanishing instruction, I once wrote some code using the Move Inverse
> (MVCIN) instruction, which greatly simplified scanning data for a terminating
> character. Apparently MVCIN was introduced on
Yes. I took care of VS1 1.7D with BPE (Basic Programming Extensions) on
a 4341.
On 2020-09-01 22:56, Mike Schwab wrote:
Well, this is what confused me. OS/VS1 1.7 was released to run on the IBM 4300.
VS2 is multiple address spaces, vs VS1 is a single 16MB address space, correct?
On 9/1/2020 6:36 PM, Jesse 1 Robinson wrote:
As for a vanishing instruction, I once wrote some code using the Move Inverse
(MVCIN) instruction, which greatly simplified scanning data for a terminating
character. Apparently MVCIN was introduced on the 4341 (?) but not carried
forward to
Well, this is what confused me. OS/VS1 1.7 was released to run on the IBM 4300.
VS2 is multiple address spaces, vs VS1 is a single 16MB address space, correct?
https://en.wikipedia.org/wiki/IBM_4300#Operating_systems
On Tue, Sep 1, 2020 at 6:27 PM Phil Smith III wrote:
>
>
-6132 Office ⇐=== NEW
robin...@sce.com
-Original Message-
From: IBM Mainframe Discussion List On Behalf Of
Seymour J Metz
Sent: Tuesday, September 1, 2020 5:27 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: (External):Re: Architectural Level Sets
CAUTION EXTERNAL EMAIL
Well, a S/360 program
-Manager
323-715-0595 Mobile
626-543-6132 Office ⇐=== NEW
robin...@sce.com
-Original Message-
From: IBM Mainframe Discussion List On Behalf Of
Seymour J Metz
Sent: Tuesday, September 1, 2020 5:27 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: (External):Re: Architectural Level Sets
CAUTION
From: IBM Mainframe Discussion List on behalf of
Tony Thigpen
Sent: Tuesday, September 1, 2020 5:20 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Architectural Level Sets
I was thinking more along the lines of things that prevented earlier
operating systems from even IPLing
(Seymour J.) Metz
http://mason.gmu.edu/~smetz3
From: IBM Mainframe Discussion List on behalf of
Mike Schwab
Sent: Tuesday, September 1, 2020 5:25 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Architectural Level Sets
Well, XA+ machines only supported 4K
@LISTSERV.UA.EDU
Subject: Re: Architectural Level Sets
370 supported DAS (the code is in MVS3.8J).
43XX running MVS supported DAS also. 4381 could have up to 64M of main
storage...
Joe
On Tue, Sep 1, 2020 at 4:26 PM Mike Schwab wrote:
> Well, XA+ machines only supported 4K pages / 1M segments and not
mike.a.sch...@gmail.com (Mike Schwab) wrote:
>Well, XA+ machines only supported 4K pages / 1M segments and not 2K
>pages / 64K segments. Then DAS and Access register additions. The
>43xx series only supported a single virtual address space, like
>DOS/VSE. 3090s were the only processors to
[Default] On 1 Sep 2020 14:26:32 -0700, in bit.listserv.ibm-main
mike.a.sch...@gmail.com (Mike Schwab) wrote:
>Well, XA+ machines only supported 4K pages / 1M segments and not 2K
>pages / 64K segments. Then DAS and Access register additions. The
>43xx series only supported a single virtual
370 supported DAS (the code is in MVS3.8J).
43XX running MVS supported DAS also. 4381 could have up to 64M of main
storage...
Joe
On Tue, Sep 1, 2020 at 4:26 PM Mike Schwab wrote:
> Well, XA+ machines only supported 4K pages / 1M segments and not 2K
> pages / 64K segments. Then DAS and
Well, XA+ machines only supported 4K pages / 1M segments and not 2K
pages / 64K segments. Then DAS and Access register additions. The
43xx series only supported a single virtual address space, like
DOS/VSE. 3090s were the only processors to support Vector
instructions, and op codes were re-used
I was thinking more along the lines of things that prevented earlier
operating systems from even IPLing on newer boxes. Such as z13 is the
last processor to have ESA/390 mode. I also have it in my head that at
some point there were changes to the page size and virtual storage
tables that
Typically the new features reqiured by a level set were added over several
generations, and each generation added more than one feature.
--
Shmuel (Seymour J.) Metz
http://mason.gmu.edu/~smetz3
From: IBM Mainframe Discussion List on behalf of
Tony
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