[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Record the current requests queue for execlists upon hang

[Patchwork]

== Series Details ==

Series: drm/i915: Record the current requests queue for execlists upon hang
URL   : https://patchwork.freedesktop.org/series/13660/
State : success

== Summary ==

Series 13660v1 drm/i915: Record the current requests queue for execlists upon 
hang
https://patchwork.freedesktop.org/api/1.0/series/13660/revisions/1/mbox/

Test drv_module_reload_basic:
skip   -> PASS   (fi-skl-6770hq)
Test kms_flip:
Subgroup basic-flip-vs-modeset:
dmesg-warn -> PASS   (fi-skl-6770hq)
Test kms_psr_sink_crc:
Subgroup psr_basic:
dmesg-warn -> PASS   (fi-skl-6700hq)
Test vgem_basic:
Subgroup unload:
skip   -> PASS   (fi-kbl-7200u)
skip   -> PASS   (fi-hsw-4770)

fi-bdw-5557u total:248  pass:232  dwarn:0   dfail:0   fail:0   skip:16 
fi-bsw-n3050 total:248  pass:205  dwarn:0   dfail:0   fail:0   skip:43 
fi-bxt-t5700 total:248  pass:217  dwarn:0   dfail:0   fail:0   skip:31 
fi-byt-j1900 total:248  pass:213  dwarn:2   dfail:0   fail:1   skip:32 
fi-byt-n2820 total:248  pass:211  dwarn:0   dfail:0   fail:1   skip:36 
fi-hsw-4770  total:248  pass:225  dwarn:0   dfail:0   fail:0   skip:23 
fi-hsw-4770r total:248  pass:225  dwarn:0   dfail:0   fail:0   skip:23 
fi-ivb-3520m total:248  pass:222  dwarn:0   dfail:0   fail:0   skip:26 
fi-ivb-3770  total:248  pass:222  dwarn:0   dfail:0   fail:0   skip:26 
fi-kbl-7200u total:248  pass:223  dwarn:0   dfail:0   fail:0   skip:25 
fi-skl-6260u total:248  pass:233  dwarn:0   dfail:0   fail:0   skip:15 
fi-skl-6700hqtotal:248  pass:225  dwarn:0   dfail:0   fail:0   skip:23 
fi-skl-6700k total:248  pass:222  dwarn:1   dfail:0   fail:0   skip:25 
fi-skl-6770hqtotal:248  pass:231  dwarn:1   dfail:0   fail:1   skip:15 
fi-snb-2520m total:248  pass:211  dwarn:0   dfail:0   fail:0   skip:37 
fi-snb-2600  total:248  pass:210  dwarn:0   dfail:0   fail:0   skip:38 

Results at /archive/results/CI_IGT_test/Patchwork_2692/

14740bb25ec36fe4ce8042af3eb48aeb45e5bc13 drm-intel-nightly: 
2016y-10m-12d-16h-18m-24s UTC integration manifest
988e045 drm/i915: Record the current requests queue for execlists upon hang

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Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Treat a framebuffer reference as an active reference whilst shrinking

[Saarinen, Jani]

> == Series Details ==
> 
> Series: drm/i915: Treat a framebuffer reference as an active reference whilst 
> shrinking
> URL   : https://patchwork.freedesktop.org/series/13648/
> State : failure
> 
> == Summary ==
> 
> Series 13648v1 drm/i915: Treat a framebuffer reference as an active
> reference whilst shrinking
> https://patchwork.freedesktop.org/api/1.0/series/13648/revisions/1/mbox/
> 
> Test kms_force_connector_basic:
> Subgroup force-connector-state:
> pass   -> DMESG-WARN (fi-ivb-3770)

 [drm:drm_edid_block_valid] *ERROR* EDID checksum is invalid, remainder is 114
 [drm:drm_edid_block_valid] *ERROR* EDID checksum is invalid, remainder is 114

> Test kms_pipe_crc_basic:
> Subgroup nonblocking-crc-pipe-c-frame-sequence:
> pass   -> DMESG-WARN (fi-skl-6770hq)

[drm:skl_set_cdclk [i915]] *ERROR* failed to inform PCU about cdclk change

> Subgroup suspend-read-crc-pipe-a:
> dmesg-warn -> PASS   (fi-ilk-650)

 [drm:intel_pch_fifo_underrun_irq_handler [i915]] *ERROR* PCH transcoder B FIFO 
underrun
 [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe B FIFO 
underrun


> Test pm_rps:
> Subgroup basic-api:
> pass   -> FAIL   (fi-hsw-4770r)

(pm_rps:11618) CRITICAL: Test assertion failure function checkit, file 
pm_rps.c:148:
(pm_rps:11618) CRITICAL: Failed assertion: freqs[CUR] <= freqs[MAX]
(pm_rps:11618) CRITICAL: Last errno: 22, Invalid argument
(pm_rps:11618) CRITICAL: error: 1300 > 750
Subtest basic-api failed.

> Test vgem_basic:
> Subgroup unload:
> skip   -> PASS   (fi-bdw-5557u)
> pass   -> SKIP   (fi-hsw-4770r)
> skip   -> PASS   (fi-hsw-4770)
> Test vgem_reload_basic:
> pass   -> FAIL   (fi-hsw-4770r)
> 
> fi-bdw-5557u total:248  pass:232  dwarn:0   dfail:0   fail:0   skip:16
> fi-bsw-n3050 total:248  pass:205  dwarn:0   dfail:0   fail:0   skip:43
> fi-bxt-t5700 total:248  pass:217  dwarn:0   dfail:0   fail:0   skip:31
> fi-byt-j1900 total:248  pass:213  dwarn:2   dfail:0   fail:1   skip:32
> fi-byt-n2820 total:248  pass:211  dwarn:0   dfail:0   fail:1   skip:36
> fi-hsw-4770  total:248  pass:225  dwarn:0   dfail:0   fail:0   skip:23
> fi-hsw-4770r total:248  pass:222  dwarn:0   dfail:0   fail:2   skip:24
> fi-ilk-650   total:248  pass:185  dwarn:0   dfail:0   fail:2   skip:61
> fi-ivb-3520m total:248  pass:222  dwarn:0   dfail:0   fail:0   skip:26
> fi-ivb-3770  total:248  pass:221  dwarn:1   dfail:0   fail:0   skip:26
> fi-kbl-7200u total:248  pass:223  dwarn:0   dfail:0   fail:0   skip:25
> fi-skl-6260u total:248  pass:233  dwarn:0   dfail:0   fail:0   skip:15
> fi-skl-6700hqtotal:248  pass:225  dwarn:0   dfail:0   fail:0   skip:23
> fi-skl-6700k total:248  pass:222  dwarn:1   dfail:0   fail:0   skip:25
> fi-skl-6770hqtotal:248  pass:230  dwarn:2   dfail:0   fail:1   skip:15
> fi-snb-2520m total:248  pass:211  dwarn:0   dfail:0   fail:0   skip:37
> fi-snb-2600  total:248  pass:210  dwarn:0   dfail:0   fail:0   skip:38
> 
> Results at /archive/results/CI_IGT_test/Patchwork_2688/
> 
> 4c3e00c4630b732518abf737580d927bb52346fa drm-intel-nightly: 2016y-10m-
> 12d-14h-36m-58s UTC integration manifest
> 2ac1007 drm/i915: Treat a framebuffer reference as an active reference
> whilst shrinking
> 
> ___
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx


Jani Saarinen
Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo



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Re: [Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915/hsw: Fix GPU hang during resume from S3-devices state

[Saarinen, Jani]

> == Series Details ==
> 
> Series: drm/i915/hsw: Fix GPU hang during resume from S3-devices state
> URL   : https://patchwork.freedesktop.org/series/13654/
> State : warning
> 
> == Summary ==
> 
> Series 13654v1 drm/i915/hsw: Fix GPU hang during resume from S3-devices
> state
> https://patchwork.freedesktop.org/api/1.0/series/13654/revisions/1/mbox/
> 
> Test drv_module_reload_basic:
> skip   -> PASS   (fi-skl-6770hq)
> Test kms_cursor_legacy:
> Subgroup basic-flip-after-cursor-legacy:
> pass   -> DMESG-WARN (fi-ivb-3770)

 [drm:drm_edid_block_valid] *ERROR* EDID checksum is invalid, remainder is 144
 [drm:drm_edid_block_valid] *ERROR* EDID checksum is invalid, remainder is 144

> Test kms_flip:
> Subgroup basic-flip-vs-modeset:
> dmesg-warn -> PASS   (fi-skl-6770hq)
> Test kms_pipe_crc_basic:
> Subgroup suspend-read-crc-pipe-b:
> dmesg-warn -> PASS   (fi-byt-j1900)
> Test kms_psr_sink_crc:
> Subgroup psr_basic:
> dmesg-warn -> PASS   (fi-skl-6700hq)
> Test vgem_basic:
> Subgroup unload:
> pass   -> SKIP   (fi-bdw-5557u)
> skip   -> PASS   (fi-hsw-4770)
> 
> fi-bdw-5557u total:248  pass:231  dwarn:0   dfail:0   fail:0   skip:17
> fi-bsw-n3050 total:248  pass:205  dwarn:0   dfail:0   fail:0   skip:43
> fi-bxt-t5700 total:248  pass:217  dwarn:0   dfail:0   fail:0   skip:31
> fi-byt-j1900 total:248  pass:214  dwarn:1   dfail:0   fail:1   skip:32
> fi-byt-n2820 total:248  pass:211  dwarn:0   dfail:0   fail:1   skip:36
> fi-hsw-4770  total:248  pass:225  dwarn:0   dfail:0   fail:0   skip:23
> fi-hsw-4770r total:248  pass:225  dwarn:0   dfail:0   fail:0   skip:23
> fi-ilk-650   total:248  pass:185  dwarn:0   dfail:0   fail:2   skip:61
> fi-ivb-3520m total:248  pass:222  dwarn:0   dfail:0   fail:0   skip:26
> fi-ivb-3770  total:248  pass:221  dwarn:1   dfail:0   fail:0   skip:26
> fi-kbl-7200u total:248  pass:222  dwarn:0   dfail:0   fail:0   skip:26
> fi-skl-6260u total:248  pass:233  dwarn:0   dfail:0   fail:0   skip:15
> fi-skl-6700hqtotal:248  pass:225  dwarn:0   dfail:0   fail:0   skip:23
> fi-skl-6700k total:248  pass:222  dwarn:1   dfail:0   fail:0   skip:25
> fi-skl-6770hqtotal:248  pass:231  dwarn:1   dfail:0   fail:1   skip:15
> fi-snb-2520m total:248  pass:211  dwarn:0   dfail:0   fail:0   skip:37
> fi-snb-2600  total:248  pass:210  dwarn:0   dfail:0   fail:0   skip:38
> 
> Results at /archive/results/CI_IGT_test/Patchwork_2690/
> 
> 14740bb25ec36fe4ce8042af3eb48aeb45e5bc13 drm-intel-nightly: 2016y-10m-
> 12d-16h-18m-24s UTC integration manifest
> 78a5d29 drm/i915/hsw: Fix GPU hang during resume from S3-devices state
> 
> ___
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Jani Saarinen
Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo
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Re: [Intel-gfx] ✗ Fi.CI.BAT: warning for Support for sustained capturing of GuC firmware logs (rev11)

[Saarinen, Jani]

> == Series Details ==
> 
> Series: Support for sustained capturing of GuC firmware logs (rev11)
> URL   : https://patchwork.freedesktop.org/series/7910/
> State : warning
> 
> == Summary ==
> 
> Series 7910v11 Support for sustained capturing of GuC firmware logs
> https://patchwork.freedesktop.org/api/1.0/series/7910/revisions/11/mbox/
> 
> Test drv_module_reload_basic:
> skip   -> PASS   (fi-skl-6770hq)
> Test kms_flip:
> Subgroup basic-flip-vs-modeset:
> dmesg-warn -> PASS   (fi-skl-6770hq)
> Test kms_pipe_crc_basic:
> Subgroup nonblocking-crc-pipe-c:
> pass   -> DMESG-WARN (fi-ivb-3770)
 [drm:drm_edid_block_valid] *ERROR* EDID checksum is invalid, remainder is 215
 [drm:drm_edid_block_valid] *ERROR* EDID checksum is invalid, remainder is 215

> Test kms_psr_sink_crc:
> Subgroup psr_basic:
> dmesg-warn -> PASS   (fi-skl-6700hq)
> Test vgem_basic:
> Subgroup unload:
> skip   -> PASS   (fi-kbl-7200u)
> skip   -> PASS   (fi-hsw-4770)
> 
> fi-bdw-5557u total:248  pass:232  dwarn:0   dfail:0   fail:0   skip:16
> fi-bsw-n3050 total:248  pass:205  dwarn:0   dfail:0   fail:0   skip:43
> fi-bxt-t5700 total:248  pass:217  dwarn:0   dfail:0   fail:0   skip:31
> fi-byt-j1900 total:248  pass:213  dwarn:2   dfail:0   fail:1   skip:32
> fi-byt-n2820 total:248  pass:211  dwarn:0   dfail:0   fail:1   skip:36
> fi-hsw-4770  total:248  pass:225  dwarn:0   dfail:0   fail:0   skip:23
> fi-hsw-4770r total:248  pass:225  dwarn:0   dfail:0   fail:0   skip:23
> fi-ivb-3520m total:248  pass:222  dwarn:0   dfail:0   fail:0   skip:26
> fi-ivb-3770  total:248  pass:221  dwarn:1   dfail:0   fail:0   skip:26
> fi-kbl-7200u total:248  pass:223  dwarn:0   dfail:0   fail:0   skip:25
> fi-skl-6260u total:248  pass:233  dwarn:0   dfail:0   fail:0   skip:15
> fi-skl-6700hqtotal:248  pass:225  dwarn:0   dfail:0   fail:0   skip:23
> fi-skl-6700k total:248  pass:222  dwarn:1   dfail:0   fail:0   skip:25
> fi-skl-6770hqtotal:248  pass:231  dwarn:1   dfail:0   fail:1   skip:15
> fi-snb-2520m total:248  pass:211  dwarn:0   dfail:0   fail:0   skip:37
> fi-snb-2600  total:248  pass:210  dwarn:0   dfail:0   fail:0   skip:38
> 
> Results at /archive/results/CI_IGT_test/Patchwork_2691/
> 
> 14740bb25ec36fe4ce8042af3eb48aeb45e5bc13 drm-intel-nightly: 2016y-10m-
> 12d-16h-18m-24s UTC integration manifest a590f8c drm/i915: Mark the GuC
> log buffer flush interrupts handling WQ as freezable a001c3d drm/i915: Early
> creation of relay channel for capturing boot time logs af3ee1c drm/i915: Use
> SSE4.1 movntdqa based memcpy for sampling GuC log buffer
> fbbd457 drm/i915: Debugfs support for GuC logging control 656513f
> drm/i915: Support for forceful flush of GuC log buffer a68d17f drm/i915:
> Augment i915 error state to include the dump of GuC log buffer da8274a
> drm/i915: Increase GuC log buffer size to reduce flush interrupts
> 4f24c12 drm/i915: Optimization to reduce the sampling time of GuC log
> buffer
> 4739ad8 drm/i915: Add stats for GuC log buffer flush interrupts
> 2e8c052 drm/i915: New lock to serialize the Host2GuC actions 954e48b
> drm/i915: Add a relay backed debugfs interface for capturing GuC logs
> 23a81bb relay: Use per CPU constructs for the relay channel buffer pointers
> 8fd01d3 drm/i915: Handle log buffer flush interrupt event from GuC
> 44610d4 drm/i915: Support for GuC interrupts
> 05ede72 drm/i915: Add low level set of routines for programming PM
> IER/IIR/IMR register set ffbd48f drm/i915: New structure to contain GuC
> logging related fields 317ba9e drm/i915: Add GuC ukernel logging related
> fields to fw interface file
> 4832507 drm/i915: Decouple GuC log setup from verbosity parameter
> 
> ___
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Jani Saarinen
Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo
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Re: [Intel-gfx] drm/i915: WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock)

[Paul Bolle]

On Wed, 2016-10-12 at 14:06 +0200, Paul Bolle wrote:
> That might take some time. Because bisecting always takes a long time
> and especially since hitting this WARNING sometimes takes over an hour.
> Anyhow, please prod me if I stay silent for too long.

For the record: I just had to power cycle this laptop because it got
into that lovely state where it just locks without accepting any input
(no, I don't have netconsole enabled).

Assuming this lockup is related: this could be more urgent than I
thought.


Paul Bolle
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[Intel-gfx] ✗ Fi.CI.BAT: warning for Add support for Legacy Hdmi audio

[Patchwork]

== Series Details ==

Series: Add support for Legacy Hdmi audio
URL   : https://patchwork.freedesktop.org/series/13661/
State : warning

== Summary ==

Series 13661v1 Add support for Legacy Hdmi audio
https://patchwork.freedesktop.org/api/1.0/series/13661/revisions/1/mbox/

Test drv_module_reload_basic:
skip   -> PASS   (fi-skl-6770hq)
Test kms_flip:
Subgroup basic-flip-vs-dpms:
pass   -> DMESG-WARN (fi-snb-2520m)
Subgroup basic-flip-vs-modeset:
dmesg-warn -> PASS   (fi-skl-6770hq)
Test kms_pipe_crc_basic:
Subgroup nonblocking-crc-pipe-a:
pass   -> DMESG-WARN (fi-ilk-650)
Test kms_psr_sink_crc:
Subgroup psr_basic:
dmesg-warn -> PASS   (fi-skl-6700hq)
Test vgem_basic:
Subgroup unload:
skip   -> PASS   (fi-hsw-4770)
skip   -> PASS   (fi-kbl-7200u)

fi-bdw-5557u total:248  pass:232  dwarn:0   dfail:0   fail:0   skip:16 
fi-bsw-n3050 total:248  pass:205  dwarn:0   dfail:0   fail:0   skip:43 
fi-byt-j1900 total:248  pass:213  dwarn:2   dfail:0   fail:1   skip:32 
fi-byt-n2820 total:248  pass:211  dwarn:0   dfail:0   fail:1   skip:36 
fi-hsw-4770  total:248  pass:225  dwarn:0   dfail:0   fail:0   skip:23 
fi-hsw-4770r total:248  pass:225  dwarn:0   dfail:0   fail:0   skip:23 
fi-ilk-650   total:248  pass:184  dwarn:1   dfail:0   fail:2   skip:61 
fi-ivb-3520m total:248  pass:222  dwarn:0   dfail:0   fail:0   skip:26 
fi-ivb-3770  total:248  pass:222  dwarn:0   dfail:0   fail:0   skip:26 
fi-kbl-7200u total:248  pass:223  dwarn:0   dfail:0   fail:0   skip:25 
fi-skl-6260u total:248  pass:233  dwarn:0   dfail:0   fail:0   skip:15 
fi-skl-6700hqtotal:248  pass:225  dwarn:0   dfail:0   fail:0   skip:23 
fi-skl-6700k total:248  pass:222  dwarn:1   dfail:0   fail:0   skip:25 
fi-skl-6770hqtotal:248  pass:231  dwarn:1   dfail:0   fail:1   skip:15 
fi-snb-2520m total:248  pass:210  dwarn:1   dfail:0   fail:0   skip:37 
fi-snb-2600  total:248  pass:210  dwarn:0   dfail:0   fail:0   skip:38 
fi-bxt-t5700 failed to collect. IGT log at Patchwork_2693/fi-bxt-t5700/igt.log

Results at /archive/results/CI_IGT_test/Patchwork_2693/

14740bb25ec36fe4ce8042af3eb48aeb45e5bc13 drm-intel-nightly: 
2016y-10m-12d-16h-18m-24s UTC integration manifest
f326d3c hdmi_audio: continue audio playback even when display resolution changes
4a31c16 hdmi_audio: Fixup some monitor
0f6f765 hdmi_audio: Improve position reporting Using a hw register to calculate 
sub-period position reports.
98ed9c5 drm/i915: Add support for audio driver notifications
f5a7592 drm/i915: Add support for enabling/disabling hdmi audio interrupts
c8bed7a ALSA: Add support for hdmi audio driver
d8bab54 ALSA: add shell for Intel HDMI LPE audio driver
daa4014 drm/i915: setup bridge for HDMI LPE audio driver

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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,1/3] drm/i915: Remove unused "valid" parameter from pte_encode

[Patchwork]

== Series Details ==

Series: series starting with [CI,1/3] drm/i915: Remove unused "valid" parameter 
from pte_encode
URL   : https://patchwork.freedesktop.org/series/13663/
State : failure

== Summary ==

Series 13663v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/13663/revisions/1/mbox/

Test core_auth:
Subgroup basic-auth:
pass   -> INCOMPLETE (fi-bsw-n3050)
Test drv_module_reload_basic:
pass   -> SKIP   (fi-skl-6260u)
skip   -> PASS   (fi-skl-6770hq)
Test kms_flip:
Subgroup basic-flip-vs-modeset:
dmesg-warn -> PASS   (fi-skl-6770hq)
Test kms_psr_sink_crc:
Subgroup psr_basic:
dmesg-warn -> PASS   (fi-skl-6700hq)
Test vgem_basic:
Subgroup unload:
skip   -> PASS   (fi-hsw-4770)
pass   -> SKIP   (fi-skl-6260u)
skip   -> PASS   (fi-kbl-7200u)

fi-bdw-5557u total:248  pass:232  dwarn:0   dfail:0   fail:0   skip:16 
fi-bsw-n3050 total:1pass:0dwarn:0   dfail:0   fail:0   skip:0  
fi-bxt-t5700 total:248  pass:217  dwarn:0   dfail:0   fail:0   skip:31 
fi-byt-j1900 total:248  pass:213  dwarn:2   dfail:0   fail:1   skip:32 
fi-byt-n2820 total:248  pass:211  dwarn:0   dfail:0   fail:1   skip:36 
fi-hsw-4770  total:248  pass:225  dwarn:0   dfail:0   fail:0   skip:23 
fi-hsw-4770r total:248  pass:225  dwarn:0   dfail:0   fail:0   skip:23 
fi-ilk-650   total:248  pass:185  dwarn:0   dfail:0   fail:2   skip:61 
fi-ivb-3520m total:248  pass:222  dwarn:0   dfail:0   fail:0   skip:26 
fi-ivb-3770  total:248  pass:222  dwarn:0   dfail:0   fail:0   skip:26 
fi-kbl-7200u total:248  pass:223  dwarn:0   dfail:0   fail:0   skip:25 
fi-skl-6260u total:248  pass:231  dwarn:0   dfail:0   fail:0   skip:17 
fi-skl-6700hqtotal:248  pass:225  dwarn:0   dfail:0   fail:0   skip:23 
fi-skl-6700k total:248  pass:222  dwarn:1   dfail:0   fail:0   skip:25 
fi-skl-6770hqtotal:248  pass:231  dwarn:1   dfail:0   fail:1   skip:15 
fi-snb-2520m total:248  pass:211  dwarn:0   dfail:0   fail:0   skip:37 
fi-snb-2600  total:248  pass:210  dwarn:0   dfail:0   fail:0   skip:38 

Results at /archive/results/CI_IGT_test/Patchwork_2694/

14740bb25ec36fe4ce8042af3eb48aeb45e5bc13 drm-intel-nightly: 
2016y-10m-12d-16h-18m-24s UTC integration manifest
944860b drm/i915/gtt: Free unused lower-level page tables
c6b70f4 drm/i915/gtt: Split gen8_ppgtt_clear_pte_range
8d6718d drm/i915: Remove unused "valid" parameter from pte_encode

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Re: [Intel-gfx] [PATCH v2] drm/i915: Allow compaction upto SWIOTLB max segment size

[Konrad Rzeszutek Wilk]

On Mon, Oct 10, 2016 at 11:27:00PM +0100, Chris Wilson wrote:
> commit 1625e7e549c5 ("drm/i915: make compact dma scatter lists creation
> work with SWIOTLB backend") took a heavy handed approach to undo the
> scatterlist compaction in the face of SWIOTLB. (The compaction hit a bug
> whereby we tried to pass a segment larger than SWIOTLB could handle.) We
> can be a little more intelligent and try compacting the scatterlist up
> to the maximum SWIOTLB segment size (when using SWIOTLB).
> 

Won't this cause a bigger usage of the SWIOTLB bounce buffer ?

> v2: Tidy sg_mark_end() and cpp
> 
> Signed-off-by: Chris Wilson 
> CC: Imre Deak 
> CC: Daniel Vetter 
> Cc: Konrad Rzeszutek Wilk 
> Cc: Tvrtko Ursulin 
> ---
>  drivers/gpu/drm/i915/i915_gem.c | 30 ++
>  1 file changed, 18 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index dff8d05d80ee..50fd611926cb 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -2201,6 +2201,15 @@ unlock:
>   mutex_unlock(>mm.lock);
>  }
>  
> +static unsigned long swiotlb_max_size(void)
> +{
> +#if IS_ENABLED(CONFIG_SWIOTLB)
> + return swiotlb_nr_tbl() << IO_TLB_SHIFT;
> +#else
> + return 0;
> +#endif
> +}
> +
>  static struct sg_table *
>  i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
>  {
> @@ -2212,6 +2221,7 @@ i915_gem_object_get_pages_gtt(struct 
> drm_i915_gem_object *obj)
>   struct sgt_iter sgt_iter;
>   struct page *page;
>   unsigned long last_pfn = 0; /* suppress gcc warning */
> + unsigned long max_segment;
>   int ret;
>   gfp_t gfp;
>  
> @@ -,6 +2232,10 @@ i915_gem_object_get_pages_gtt(struct 
> drm_i915_gem_object *obj)
>   GEM_BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
>   GEM_BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
>  
> + max_segment = swiotlb_max_size();
> + if (!max_segment)
> + max_segment = obj->base.size;
> +
>   st = kmalloc(sizeof(*st), GFP_KERNEL);
>   if (st == NULL)
>   return ERR_PTR(-ENOMEM);
> @@ -2263,15 +2277,9 @@ i915_gem_object_get_pages_gtt(struct 
> drm_i915_gem_object *obj)
>   goto err_pages;
>   }
>   }
> -#ifdef CONFIG_SWIOTLB
> - if (swiotlb_nr_tbl()) {
> - st->nents++;
> - sg_set_page(sg, page, PAGE_SIZE, 0);
> - sg = sg_next(sg);
> - continue;
> - }
> -#endif
> - if (!i || page_to_pfn(page) != last_pfn + 1) {
> + if (!i ||
> + sg->length >= max_segment ||
> + page_to_pfn(page) != last_pfn + 1) {
>   if (i)
>   sg = sg_next(sg);
>   st->nents++;
> @@ -2284,9 +2292,7 @@ i915_gem_object_get_pages_gtt(struct 
> drm_i915_gem_object *obj)
>   /* Check that the i965g/gm workaround works. */
>   WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x0010UL));
>   }
> -#ifdef CONFIG_SWIOTLB
> - if (!swiotlb_nr_tbl())
> -#endif
> + if (sg) /* loop terminated early; short sg table */
>   sg_mark_end(sg);
>  
>   ret = i915_gem_gtt_prepare_pages(obj, st);
> -- 
> 2.9.3
> 
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Re: [Intel-gfx] [CI 3/3] drm/i915/gtt: Free unused lower-level page tables

[Chris Wilson]

On Wed, Oct 12, 2016 at 06:47:38PM +0200, Michał Winiarski wrote:
> +static bool gen8_ppgtt_clear_pd(struct i915_address_space *vm,
>   struct i915_page_directory *pd,
>   uint64_t start,
>   uint64_t length)
>  {
> + struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
>   struct i915_page_table *pt;
>   uint64_t pde;
> + gen8_pde_t *pde_vaddr;
> + gen8_pde_t scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt),
> +  I915_CACHE_LLC);
> + bool reduce;
>  
>   gen8_for_each_pde(pt, pd, start, length, pde) {
>   if (WARN_ON(!pd->page_table[pde]))
>   break;
>  
> - gen8_ppgtt_clear_pt(vm, pt, start, length);
> + reduce = gen8_ppgtt_clear_pt(vm, pt, start, length);
> +
> + if (reduce) {
> + __clear_bit(pde, pd->used_pdes);
> + pde_vaddr = kmap_px(pd);
> + pde_vaddr[pde] = scratch_pde;
> + kunmap_px(ppgtt, pde_vaddr);

On !48b (bsw), the pd is only partially set up, it is not backed by a
page, but i915_page_dir_dma_addr() converts the empty bit into the
scratch address instead.
Obnoxiously this requires another if (USES_FULL_48BIT_PPGTT(0)) {}
-Chris

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Re: [Intel-gfx] [PATCH v2] drm/i915: Allow compaction upto SWIOTLB max segment size

[Chris Wilson]

On Wed, Oct 12, 2016 at 05:19:14PM -0400, Konrad Rzeszutek Wilk wrote:
> On Mon, Oct 10, 2016 at 11:27:00PM +0100, Chris Wilson wrote:
> > commit 1625e7e549c5 ("drm/i915: make compact dma scatter lists creation
> > work with SWIOTLB backend") took a heavy handed approach to undo the
> > scatterlist compaction in the face of SWIOTLB. (The compaction hit a bug
> > whereby we tried to pass a segment larger than SWIOTLB could handle.) We
> > can be a little more intelligent and try compacting the scatterlist up
> > to the maximum SWIOTLB segment size (when using SWIOTLB).
> > 
> 
> Won't this cause a bigger usage of the SWIOTLB bounce buffer ?

It won't change the frequency of the usage of the bounce buffer, if that
is what you mean. Either you have intel-iommu and so will not go through
swiotlb, or you are forced to use swiotlb even though the hw doesn't
require it (swiotlb config is byzantium and always enabled unless you
hack it out and can rejoice at the lower cpu usage).
-Chris

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Re: [Intel-gfx] [PATCH RESEND 9/9] drm/i915: set proper N/M in modeset

[Yang, Libin]

> -Original Message-
> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
> Lin, Mengdong
> Sent: Wednesday, October 12, 2016 10:46 AM
> To: Nikula, Jani ; intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani ; libin.y...@linux.intel.com;
> Pandiyan, Dhinakaran 
> Subject: Re: [Intel-gfx] [PATCH RESEND 9/9] drm/i915: set proper N/M in
> modeset
> 
> 
> 
> > -Original Message-
> > From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On
> > Behalf Of Jani Nikula
> > Sent: Monday, October 10, 2016 11:04 PM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Nikula, Jani ; libin.y...@linux.intel.com;
> > Pandiyan, Dhinakaran 
> > Subject: [Intel-gfx] [PATCH RESEND 9/9] drm/i915: set proper N/M in
> > modeset
> >
> > When modeset occurs and the LS_CLK is set to some special values in DP
> > mode, the N/M need to be set manually if audio is playing. Otherwise
> > the first several seconds may be silent in audio playback.
> >
> > The relationship of Maud and Naud is expressed in the following equation:
> > Maud/Naud = 512 * fs / f_LS_Clk
> >
> > Please refer VESA DisplayPort Standard spec for details.
> >
> > Signed-off-by: Libin Yang 
> > Signed-off-by: Jani Nikula 
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h|   7 +++
> >  drivers/gpu/drm/i915/intel_audio.c | 100
> > -
> >  2 files changed, 105 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index 595d196f753f..8d9dbc7d5b32
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7359,6 +7359,13 @@ enum {
> >  #define _HSW_AUD_MISC_CTRL_B   0x65110
> >  #define HSW_AUD_MISC_CTRL(pipe)_MMIO_PIPE(pipe,
> > _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
> >
> > +#define _HSW_AUD_M_CTS_ENABLE_A0x65028
> > +#define _HSW_AUD_M_CTS_ENABLE_B0x65128
> > +#define HSW_AUD_M_CTS_ENABLE(pipe) _MMIO_PIPE(pipe,
> > _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
> > +#define   AUD_M_CTS_M_VALUE_INDEX  (1 << 21)
> > +#define   AUD_M_CTS_M_PROG_ENABLE  (1 << 20)
> > +#define   AUD_CONFIG_M_MASK0xf
> 
> The last line cause misalignment after applying the patch.
> 
> > +
> >  #define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4
> >  #define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4
> >  #define HSW_AUD_DIP_ELD_CTRL(pipe) _MMIO_PIPE(pipe,
> > _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B) diff --
> git
> > a/drivers/gpu/drm/i915/intel_audio.c
> > b/drivers/gpu/drm/i915/intel_audio.c
> > index 81df29ca4947..0bc2701b6c9c 100644
> > --- a/drivers/gpu/drm/i915/intel_audio.c
> > +++ b/drivers/gpu/drm/i915/intel_audio.c
> > @@ -57,6 +57,70 @@
> >   * struct _audio_component_audio_ops @audio_ops is called from
> > i915 driver.
> >   */
> >
> > +/* DP N/M table */
> > +#define LC_540M 54
> > +#define LC_270M 27
> > +#define LC_162M 162000
> > +
> > +struct dp_aud_n_m {
> > +   int sample_rate;
> > +   int clock;
> > +   u16 n;
> > +   u16 m;
> > +};
> > +
> > +static const struct dp_aud_n_m dp_aud_n_m[] = {
> > +   { 192000, LC_540M, 5625, 1024 },
> > +   { 176400, LC_540M, 9375, 1568 },
> > +   { 96000, LC_540M, 5625, 512 },
> > +   { 88200, LC_540M, 9375, 784 },
> > +   { 48000, LC_540M, 5625, 256 },
> > +   { 44100, LC_540M, 9375, 392 },
> > +   { 32000, LC_540M, 16875, 512 },
> > +   { 192000, LC_270M, 5625, 2048 },
> > +   { 176400, LC_270M, 9375, 3136 },
> > +   { 96000, LC_270M, 5625, 1024 },
> > +   { 88200, LC_270M, 9375, 1568 },
> > +   { 48000, LC_270M, 5625, 512 },
> > +   { 44100, LC_270M, 9375, 784 },
> > +   { 32000, LC_270M, 16875, 1024 },
> > +   { 192000, LC_162M, 3375, 2048 },
> > +   { 176400, LC_162M, 5625, 3136 },
> > +   { 96000, LC_162M, 3375, 1024 },
> > +   { 88200, LC_162M, 5625, 1568 },
> > +   { 48000, LC_162M, 3375, 512 },
> > +   { 44100, LC_162M, 5625, 784 },
> > +   { 32000, LC_162M, 10125, 1024 },
> > +};
> > +
> > +static const struct dp_aud_n_m *
> > +audio_config_dp_get_n_m(struct intel_crtc *intel_crtc, int rate) {
> > +   int i;
> > +
> > +   for (i = 0; i < ARRAY_SIZE(dp_aud_n_m); i++) {
> > +   if (rate == dp_aud_n_m[i].sample_rate &&
> > +   intel_crtc->config->port_clock == dp_aud_n_m[i].clock)
> > +   return _aud_n_m[i];
> > +   }
> > +
> > +   return NULL;
> > +}
> > +
> > +static int audio_config_dp_get_m(struct intel_crtc *intel_crtc, int
> > +rate) {
> > +   const struct dp_aud_n_m *nm =
> > audio_config_dp_get_n_m(intel_crtc,
> > +rate);
> > +
> > +   return nm ? nm->m : 0;
> > +}
> > +
> > +static int audio_config_dp_get_n(struct intel_crtc *intel_crtc, int
> > +rate) {
> > +   const struct dp_aud_n_m *nm =
> > audio_config_dp_get_n_m(intel_crtc,
> > 

Re: [Intel-gfx] [PATCH 04/19] drm/i915: Make HAS_RUNTIME_PM only take dev_priv

[David Weinehall]

On Tue, Oct 11, 2016 at 02:21:37PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin 
> 
> Saves 960 bytes of .rodata strings.
> 
> v2: Add parantheses around dev_priv. (Ville Syrjala)
> 
> Signed-off-by: Tvrtko Ursulin 

Reviewed-by: David Weinehall 

> ---
>  drivers/gpu/drm/i915/i915_drv.c | 4 ++--
>  drivers/gpu/drm/i915/i915_drv.h | 2 +-
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +--
>  3 files changed, 4 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 89d322215c84..fbb4e2e0d124 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -2308,7 +2308,7 @@ static int intel_runtime_suspend(struct device *kdev)
>   if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(
>   return -ENODEV;
>  
> - if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
> + if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
>   return -ENODEV;
>  
>   DRM_DEBUG_KMS("Suspending device\n");
> @@ -2412,7 +2412,7 @@ static int intel_runtime_resume(struct device *kdev)
>   struct drm_i915_private *dev_priv = to_i915(dev);
>   int ret = 0;
>  
> - if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
> + if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
>   return -ENODEV;
>  
>   DRM_DEBUG_KMS("Resuming device\n");
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 1a4698e665be..aac9375cccb3 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2818,12 +2818,12 @@ struct drm_i915_cmd_table {
>  #define HAS_DDI(dev_priv)((dev_priv)->info.has_ddi)
>  #define HAS_FPGA_DBG_UNCLAIMED(dev)  (INTEL_INFO(dev)->has_fpga_dbg)
>  #define HAS_PSR(dev) (INTEL_INFO(dev)->has_psr)
> -#define HAS_RUNTIME_PM(dev)  (INTEL_INFO(dev)->has_runtime_pm)
>  #define HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6)
>  #define HAS_RC6p(dev)(INTEL_INFO(dev)->has_rc6p)
>  
>  #define HAS_CSR(dev) (INTEL_INFO(dev)->has_csr)
>  
> +#define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
>  /*
>   * For now, anything with a GuC requires uCode loading, and then supports
>   * command submission once loaded. But these are logically independent
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c 
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 6c11168facd6..ed1faf14f777 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -2758,7 +2758,6 @@ void intel_runtime_pm_put(struct drm_i915_private 
> *dev_priv)
>  void intel_runtime_pm_enable(struct drm_i915_private *dev_priv)
>  {
>   struct pci_dev *pdev = dev_priv->drm.pdev;
> - struct drm_device *dev = _priv->drm;
>   struct device *kdev = >dev;
>  
>   pm_runtime_set_autosuspend_delay(kdev, 1); /* 10s */
> @@ -2770,7 +2769,7 @@ void intel_runtime_pm_enable(struct drm_i915_private 
> *dev_priv)
>* so the driver's own RPM reference tracking asserts also work on
>* platforms without RPM support.
>*/
> - if (!HAS_RUNTIME_PM(dev)) {
> + if (!HAS_RUNTIME_PM(dev_priv)) {
>   pm_runtime_dont_use_autosuspend(kdev);
>   pm_runtime_get_sync(kdev);
>   } else {
> -- 
> 2.7.4
> 
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Re: [Intel-gfx] [PATCH 02/19] drm/i915: Make INTEL_PCH_TYPE & co only take dev_priv

[David Weinehall]

On Tue, Oct 11, 2016 at 02:21:35PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin 
> 
> This saves 1872 bytes of .rodata strings.
> 
> v2:
>  * Rebase.
>  * Add parantheses around dev_priv. (Ville Syrjala)
> 
> Signed-off-by: Tvrtko Ursulin 

Reviewed-by: David Weinehall 

> ---
>  drivers/gpu/drm/i915/i915_drv.h   | 16 ++--
>  drivers/gpu/drm/i915/i915_gem.c   |  2 +-
>  drivers/gpu/drm/i915/i915_gpu_error.c |  4 +--
>  drivers/gpu/drm/i915/i915_irq.c   | 20 +++
>  drivers/gpu/drm/i915/intel_audio.c|  2 +-
>  drivers/gpu/drm/i915/intel_crt.c  | 25 +-
>  drivers/gpu/drm/i915/intel_display.c  | 48 
> ++-
>  drivers/gpu/drm/i915/intel_dp.c   | 27 ++--
>  drivers/gpu/drm/i915/intel_dpll_mgr.c |  2 +-
>  drivers/gpu/drm/i915/intel_hdmi.c | 19 +++---
>  drivers/gpu/drm/i915/intel_i2c.c  |  2 +-
>  drivers/gpu/drm/i915/intel_lvds.c | 22 
>  drivers/gpu/drm/i915/intel_pm.c   |  6 ++---
>  drivers/gpu/drm/i915/intel_sdvo.c | 12 -
>  14 files changed, 107 insertions(+), 100 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 51dd10f25f59..3caa1c767512 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2850,18 +2850,18 @@ struct drm_i915_cmd_table {
>  #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
>  #define INTEL_PCH_QEMU_DEVICE_ID_TYPE0x2900 /* qemu q35 has 
> 2918 */
>  
> -#define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
> -#define HAS_PCH_KBP(dev) (INTEL_PCH_TYPE(dev) == PCH_KBP)
> -#define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
> -#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
> +#define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
> +#define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
> +#define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
> +#define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
>  #define HAS_PCH_LPT_LP(dev_priv) \
>   ((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
>  #define HAS_PCH_LPT_H(dev_priv) \
>   ((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
> -#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
> -#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
> -#define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
> -#define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
> +#define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
> +#define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
> +#define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
> +#define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
>  
>  #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->has_gmch_display)
>  
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index fdd496e6c081..6b099f0198cc 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -4365,7 +4365,7 @@ i915_gem_init_hw(struct drm_device *dev)
>   I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
>  LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
>  
> - if (HAS_PCH_NOP(dev)) {
> + if (HAS_PCH_NOP(dev_priv)) {
>   if (IS_IVYBRIDGE(dev)) {
>   u32 temp = I915_READ(GEN7_MSG_CTL);
>   temp &= ~(WAIT_FOR_PCH_FLR_ACK | 
> WAIT_FOR_PCH_RESET_ACK);
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
> b/drivers/gpu/drm/i915/i915_gpu_error.c
> index b5b58692ac5a..d41517e11978 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -421,7 +421,7 @@ int i915_error_state_to_str(struct 
> drm_i915_error_state_buf *m,
>   for (i = 0; i < 4; i++)
>   err_printf(m, "GTIER gt %d: 0x%08x\n", i,
>  error->gtier[i]);
> - } else if (HAS_PCH_SPLIT(dev) || IS_VALLEYVIEW(dev))
> + } else if (HAS_PCH_SPLIT(dev_priv) || IS_VALLEYVIEW(dev_priv))
>   err_printf(m, "GTIER: 0x%08x\n", error->gtier[0]);
>   err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
>   err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
> @@ -1393,7 +1393,7 @@ static void i915_capture_reg_state(struct 
> drm_i915_private *dev_priv,
>   error->ier = I915_READ(GEN8_DE_MISC_IER);
>   for (i = 0; i < 4; i++)
>   error->gtier[i] = I915_READ(GEN8_GT_IER(i));
> - } else if (HAS_PCH_SPLIT(dev)) {
> + } else if (HAS_PCH_SPLIT(dev_priv)) {
>   error->ier = I915_READ(DEIER);
>   error->gtier[0] = I915_READ(GTIER);
>   } else if (IS_GEN2(dev)) {
> diff --git a/drivers/gpu/drm/i915/i915_irq.c 

Re: [Intel-gfx] [PATCH 12/19] drm/i915: Make IS_SKYLAKE only take dev_priv

[David Weinehall]

On Tue, Oct 11, 2016 at 02:21:45PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin 
> 
> Saves 1016 bytes of .rodata strings and couple hundred of .text.
> 
> v2: Add parantheses around dev_priv. (Ville Syrjala)
> 
> Signed-off-by: Tvrtko Ursulin 

Reviewed-by: David Weinehall 

> ---
>  drivers/gpu/drm/i915/i915_drv.h | 2 +-
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
>  drivers/gpu/drm/i915/intel_guc_loader.c | 2 +-
>  3 files changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 3c72ed08a5d2..9784e61400e5 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2663,7 +2663,7 @@ struct drm_i915_cmd_table {
>  #define IS_CHERRYVIEW(dev)   (INTEL_INFO(dev)->is_cherryview)
>  #define IS_HASWELL(dev_priv) ((dev_priv)->info.is_haswell)
>  #define IS_BROADWELL(dev_priv)   ((dev_priv)->info.is_broadwell)
> -#define IS_SKYLAKE(dev)  (INTEL_INFO(dev)->is_skylake)
> +#define IS_SKYLAKE(dev_priv) ((dev_priv)->info.is_skylake)
>  #define IS_BROXTON(dev)  (INTEL_INFO(dev)->is_broxton)
>  #define IS_KABYLAKE(dev_priv)((dev_priv)->info.is_kabylake)
>  #define IS_MOBILE(dev)   (INTEL_INFO(dev)->is_mobile)
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 3246d51c7b8e..cf43a5632961 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -2133,7 +2133,7 @@ static void gtt_write_workarounds(struct drm_device 
> *dev)
>   I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
> GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
>   else if (IS_CHERRYVIEW(dev))
>   I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
> GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
> - else if (IS_SKYLAKE(dev))
> + else if (IS_SKYLAKE(dev_priv))
>   I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
> GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
>   else if (IS_BROXTON(dev))
>   I915_WRITE(GEN8_L3_LRA_1_GPGPU, 
> GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c 
> b/drivers/gpu/drm/i915/intel_guc_loader.c
> index 3c46605b58e7..182204373931 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -726,7 +726,7 @@ void intel_guc_init(struct drm_device *dev)
>  
>   if (!HAS_GUC_UCODE(dev)) {
>   fw_path = NULL;
> - } else if (IS_SKYLAKE(dev)) {
> + } else if (IS_SKYLAKE(dev_priv)) {
>   fw_path = I915_SKL_GUC_UCODE;
>   guc_fw->guc_fw_major_wanted = SKL_FW_MAJOR;
>   guc_fw->guc_fw_minor_wanted = SKL_FW_MINOR;
> -- 
> 2.7.4
> 
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Re: [Intel-gfx] [PATCH 19/19] drm/i915: Make IS_GEN macros only take dev_priv

[David Weinehall]

On Tue, Oct 11, 2016 at 02:21:52PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin 
> 
> Saves 1416 bytes of .rodata strings.
> 
> v2: Add parantheses around dev_priv. (Ville Syrjala)
> 
> Signed-off-by: Tvrtko Ursulin 

Reviewed-by: David Weinehall 

Do note though, that this is a *very* large patch, and I suspect that
you'll have trouble getting it merged...

> ---
>  drivers/gpu/drm/i915/i915_debugfs.c|  4 +-
>  drivers/gpu/drm/i915/i915_drv.c|  6 +--
>  drivers/gpu/drm/i915/i915_drv.h| 16 +++---
>  drivers/gpu/drm/i915/i915_gem.c|  8 +--
>  drivers/gpu/drm/i915/i915_gem_execbuffer.c |  4 +-
>  drivers/gpu/drm/i915/i915_gem_fence.c  |  9 ++--
>  drivers/gpu/drm/i915/i915_gem_gtt.c| 10 ++--
>  drivers/gpu/drm/i915/i915_gem_stolen.c |  4 +-
>  drivers/gpu/drm/i915/i915_gem_tiling.c |  4 +-
>  drivers/gpu/drm/i915/i915_gpu_error.c  | 10 ++--
>  drivers/gpu/drm/i915/i915_irq.c|  4 +-
>  drivers/gpu/drm/i915/i915_suspend.c|  4 +-
>  drivers/gpu/drm/i915/intel_crt.c   |  6 +--
>  drivers/gpu/drm/i915/intel_display.c   | 41 ---
>  drivers/gpu/drm/i915/intel_dp.c| 20 +++
>  drivers/gpu/drm/i915/intel_drv.h   |  2 +-
>  drivers/gpu/drm/i915/intel_fifo_underrun.c |  6 +--
>  drivers/gpu/drm/i915/intel_guc_loader.c|  3 +-
>  drivers/gpu/drm/i915/intel_lvds.c  |  2 +-
>  drivers/gpu/drm/i915/intel_pm.c| 83 
> +++---
>  drivers/gpu/drm/i915/intel_sprite.c|  4 +-
>  21 files changed, 126 insertions(+), 124 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 20689f1cd719..3a42df3a29e5 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -4552,7 +4552,7 @@ static void wm_latency_show(struct seq_file *m, const 
> uint16_t wm[8])
>   else if (IS_VALLEYVIEW(dev_priv))
>   num_levels = 1;
>   else
> - num_levels = ilk_wm_max_level(dev) + 1;
> + num_levels = ilk_wm_max_level(dev_priv) + 1;
>  
>   drm_modeset_lock_all(dev);
>  
> @@ -4668,7 +4668,7 @@ static ssize_t wm_latency_write(struct file *file, 
> const char __user *ubuf,
>   else if (IS_VALLEYVIEW(dev_priv))
>   num_levels = 1;
>   else
> - num_levels = ilk_wm_max_level(dev) + 1;
> + num_levels = ilk_wm_max_level(dev_priv) + 1;
>  
>   if (len >= sizeof(tmp))
>   return -EINVAL;
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 5e7b6a1cb2c8..c1956855feb6 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -174,7 +174,7 @@ static void intel_detect_pch(struct drm_device *dev)
>   if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
>   dev_priv->pch_type = PCH_IBX;
>   DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
> - WARN_ON(!IS_GEN5(dev));
> + WARN_ON(!IS_GEN5(dev_priv));
>   } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
>   dev_priv->pch_type = PCH_CPT;
>   DRM_DEBUG_KMS("Found CougarPoint PCH\n");
> @@ -884,7 +884,7 @@ static int i915_mmio_setup(struct drm_device *dev)
>   int mmio_bar;
>   int mmio_size;
>  
> - mmio_bar = IS_GEN2(dev) ? 1 : 0;
> + mmio_bar = IS_GEN2(dev_priv) ? 1 : 0;
>   /*
>* Before gen4, the registers and the GTT are behind different BARs.
>* However, from gen4 onwards, the registers and the GTT are shared
> @@ -1037,7 +1037,7 @@ static int i915_driver_init_hw(struct drm_i915_private 
> *dev_priv)
>   pci_set_master(pdev);
>  
>   /* overlay on gen2 is broken and can't address above 1G */
> - if (IS_GEN2(dev)) {
> + if (IS_GEN2(dev_priv)) {
>   ret = dma_set_coherent_mask(>dev, DMA_BIT_MASK(30));
>   if (ret) {
>   DRM_ERROR("failed to set DMA mask\n");
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 3f38b9755763..a05665af31be 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2742,14 +2742,14 @@ struct drm_i915_cmd_table {
>   * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
>   * chips, etc.).
>   */
> -#define IS_GEN2(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(1)))
> -#define IS_GEN3(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(2)))
> -#define IS_GEN4(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(3)))
> -#define IS_GEN5(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(4)))
> -#define IS_GEN6(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(5)))
> -#define IS_GEN7(dev) (!!(INTEL_INFO(dev)->gen_mask & 

Re: [Intel-gfx] [PATCH i-g-t 1/5] tests: Use bash for debugfs_wedged and drm_lib.sh

[David Weinehall]

On Fri, Oct 07, 2016 at 12:54:03PM +0300, Joonas Lahtinen wrote:
> On pe, 2016-10-07 at 10:38 +0300, Jani Nikula wrote:
> > The "change" to use bash just reflects current reality. All the changes
> > here look simple and sane, and immediately improve the results. The work
> > is already done, no use blocking them because someone might eventually
> > rewrite them in C. (And it will be a PITA to write the module reload
> > test in C, so I wouldn't hold my breath.)
> > 
> 
> The scripts are really simple, most of the scripts even use POSIX sh
> compliant constructs but just the wrong shebang. And sometimes some a
> advanced bash feature here and there which could be replaced easily.
> 
> > For the series,
> > 
> > Reviewed-by: Jani Nikula 
> > 
> > 
> > PS. When I look at IGT and the macro/setjmp/longjmp magic to create the
> > test/subtest/fixture infrastructure, making the tests look like they've
> > been written in some extended version of C, I have to question whether C
> > really is the right language for the tests. libdrm python bindings and
> > python, anyone?
> 
> My patches to convert away from bash were to allow running the tests in
> minimal initramfs environment where the kernel + IGT would be a
> standalone bzImage suitable for netbooting, but we can go to another
> direction too, and lets add Java as runtime requirement for I-G-T!
> 
> Regards, Joonas
> 
> I'm against converting to bash/python for no
> benefit.

+1, Insightful.

Most of the bashisms seem to be simple cases of the superfluous
"function" in front of functions...


Kind regards, David
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Re: [Intel-gfx] [PATCH i-g-t 1/5] tests: Use bash for debugfs_wedged and drm_lib.sh

[Joonas Lahtinen]

On ke, 2016-10-12 at 13:12 +0300, David Weinehall wrote:
> On Fri, Oct 07, 2016 at 12:54:03PM +0300, Joonas Lahtinen wrote:
> > I'm against converting to bash/python for no
> > benefit.
> 
> +1, Insightful.
> 
> Most of the bashisms seem to be simple cases of the superfluous
> "function" in front of functions...
> 

Indeed. I'm still all in for converting all scripts under tests
directory to POSIX. Last time it was Nack due to intent to convert over
to C, but if we reflect to reality, we could now do the next best
option and convert to POSIX?

Regards, Joonas
-- 
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Open Source Technology Center
Intel Corporation
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Re: [Intel-gfx] [PATCH] drm/i915: Add i915 perf infrastructure

[Joonas Lahtinen]

On ti, 2016-10-11 at 12:03 -0700, Robert Bragg wrote:
> > > +               case DRM_I915_PERF_PROP_MAX:
> > > +                       BUG();
> > 
> > We already handle this case above, but I guess we still need this in
> > order to silence gcc...
> 
> right, and preferable to having a default: case, for the future compiler 
> warning to handle any new properties here.

Please, do use MISSING_CASE instead. Daniel is known to get upset for
far less ;)

Generally consensus is that BUG() is used only when there're no other options 
to back out.

Regards, Joonas
-- 
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Open Source Technology Center
Intel Corporation
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Re: [Intel-gfx] [PATCH 11/19] drm/i915: Make IS_KABYLAKE only take dev_priv

[David Weinehall]

On Tue, Oct 11, 2016 at 02:21:44PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin 
> 
> Saves 1320 bytes of .rodata strings.
> 
> v2: Add parantheses around dev_priv. (Ville Syrjala)
> 
> Signed-off-by: Tvrtko Ursulin 

Reviewed-by: David Weinehall 

> ---
>  drivers/gpu/drm/i915/i915_drv.c | 10 +-
>  drivers/gpu/drm/i915/i915_drv.h |  6 +++---
>  drivers/gpu/drm/i915/i915_gem_stolen.c  |  2 +-
>  drivers/gpu/drm/i915/intel_ddi.c| 16 
>  drivers/gpu/drm/i915/intel_display.c| 10 +-
>  drivers/gpu/drm/i915/intel_dpll_mgr.c   |  2 +-
>  drivers/gpu/drm/i915/intel_guc_loader.c |  2 +-
>  drivers/gpu/drm/i915/intel_runtime_pm.c |  2 +-
>  8 files changed, 25 insertions(+), 25 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 8899835fffab..d854ea4a7e92 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -203,17 +203,17 @@ static void intel_detect_pch(struct drm_device *dev)
>   } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
>   dev_priv->pch_type = PCH_SPT;
>   DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
> - WARN_ON(!IS_SKYLAKE(dev) &&
> - !IS_KABYLAKE(dev));
> + WARN_ON(!IS_SKYLAKE(dev_priv) &&
> + !IS_KABYLAKE(dev_priv));
>   } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
>   dev_priv->pch_type = PCH_SPT;
>   DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
> - WARN_ON(!IS_SKYLAKE(dev) &&
> - !IS_KABYLAKE(dev));
> + WARN_ON(!IS_SKYLAKE(dev_priv) &&
> + !IS_KABYLAKE(dev_priv));
>   } else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) {
>   dev_priv->pch_type = PCH_KBP;
>   DRM_DEBUG_KMS("Found KabyPoint PCH\n");
> - WARN_ON(!IS_KABYLAKE(dev));
> + WARN_ON(!IS_KABYLAKE(dev_priv));
>   } else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
>  (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
>  ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index d6c3a4bb29aa..3c72ed08a5d2 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2665,7 +2665,7 @@ struct drm_i915_cmd_table {
>  #define IS_BROADWELL(dev_priv)   ((dev_priv)->info.is_broadwell)
>  #define IS_SKYLAKE(dev)  (INTEL_INFO(dev)->is_skylake)
>  #define IS_BROXTON(dev)  (INTEL_INFO(dev)->is_broxton)
> -#define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake)
> +#define IS_KABYLAKE(dev_priv)((dev_priv)->info.is_kabylake)
>  #define IS_MOBILE(dev)   (INTEL_INFO(dev)->is_mobile)
>  #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
>   (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
> @@ -2732,8 +2732,8 @@ struct drm_i915_cmd_table {
>  #define KBL_REVID_D0 0x3
>  #define KBL_REVID_E0 0x4
>  
> -#define IS_KBL_REVID(p, since, until) \
> - (IS_KABYLAKE(p) && IS_REVID(p, since, until))
> +#define IS_KBL_REVID(dev_priv, since, until) \
> + (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
>  
>  /*
>   * The genX designation typically refers to the render engine, so render
> diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c 
> b/drivers/gpu/drm/i915/i915_gem_stolen.c
> index cbea6fb83ce5..3508120b8c90 100644
> --- a/drivers/gpu/drm/i915/i915_gem_stolen.c
> +++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
> @@ -456,7 +456,7 @@ int i915_gem_init_stolen(struct drm_device *dev)
>   break;
>   default:
>   if (IS_BROADWELL(dev_priv) ||
> - IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev))
> + IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
>   bdw_get_stolen_reserved(dev_priv, _base,
>   _size);
>   else
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> b/drivers/gpu/drm/i915/intel_ddi.c
> index cd7128b89b4d..07164e250adf 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1020,13 +1020,13 @@ static void bxt_ddi_clock_get(struct intel_encoder 
> *encoder,
>  void intel_ddi_clock_get(struct intel_encoder *encoder,
>struct intel_crtc_state *pipe_config)
>  {
> - struct drm_device *dev = encoder->base.dev;
> + 

[Intel-gfx] [PATCH 1/5] drm/i915: Use fence_write() from rpm resume

[Chris Wilson]

During rpm resume we restore the fences, but we do not have the
protection of struct_mutex. This rules out updating the activity
tracking on the fences, and requires us to rely on the rpm as the
serialisation barrier instead.

[  350.298052] [drm:intel_runtime_resume [i915]] Resuming device
[  350.308606]
[  350.310520] ===
[  350.315560] [ INFO: suspicious RCU usage. ]
[  350.320554] 4.8.0-rc8-bsw-rapl+ #3133 Tainted: G U  W
[  350.327208] ---
[  350.331977] ../drivers/gpu/drm/i915/i915_gem_request.h:371 suspicious 
rcu_dereference_protected() usage!
[  350.342619]
[  350.342619] other info that might help us debug this:
[  350.342619]
[  350.351593]
[  350.351593] rcu_scheduler_active = 1, debug_locks = 0
[  350.358952] 3 locks held by Xorg/320:
[  350.363077]  #0:  (>mode_config.mutex){+.+.+.}, at: 
[] drm_modeset_lock_all+0x3c/0xd0 [drm]
[  350.375162]  #1:  (crtc_ww_class_acquire){+.+.+.}, at: [] 
drm_modeset_lock_all+0x46/0xd0 [drm]
[  350.387022]  #2:  (crtc_ww_class_mutex){+.+.+.}, at: [] 
drm_modeset_lock+0x36/0x110 [drm]
[  350.398236]
[  350.398236] stack backtrace:
[  350.403196] CPU: 1 PID: 320 Comm: Xorg Tainted: G U  W   
4.8.0-rc8-bsw-rapl+ #3133
[  350.412457] Hardware name: Intel Corporation CHERRYVIEW C0 PLATFORM/Braswell 
CRB, BIOS BRAS.X64.X088.R00.1510270350 10/27/2015
[  350.425212]   8801680a78c8 81332187 
88016c5c5000
[  350.433611]  0001 8801680a78f8 810ca6da 
88016cc8b0f0
[  350.442012]  88016cc8 88016cc8 880177ad 
8801680a7948
[  350.450409] Call Trace:
[  350.453165]  [] dump_stack+0x67/0x90
[  350.458931]  [] lockdep_rcu_suspicious+0xea/0x120
[  350.466002]  [] fence_update+0xbd/0x670 [i915]
[  350.472766]  [] i915_gem_restore_fences+0x52/0x70 [i915]
[  350.480496]  [] vlv_resume_prepare+0x72/0x570 [i915]
[  350.487839]  [] intel_runtime_resume+0x102/0x210 [i915]
[  350.495442]  [] pci_pm_runtime_resume+0x7f/0xb0
[  350.502274]  [] ? pci_restore_standard_config+0x40/0x40
[  350.509883]  [] __rpm_callback+0x35/0x70
[  350.516037]  [] ? pci_restore_standard_config+0x40/0x40
[  350.523646]  [] rpm_callback+0x24/0x80
[  350.529604]  [] ? pci_restore_standard_config+0x40/0x40
[  350.537212]  [] rpm_resume+0x4ad/0x740
[  350.543161]  [] __pm_runtime_resume+0x51/0x80
[  350.549824]  [] intel_runtime_pm_get+0x28/0x90 [i915]
[  350.557265]  [] intel_display_power_get+0x23/0x50 [i915]
[  350.565001]  [] intel_atomic_commit_tail+0xdfd/0x10b0 
[i915]
[  350.573106]  [] ? drm_atomic_helper_swap_state+0x159/0x300 
[drm_kms_helper]
[  350.582659]  [] ? _raw_spin_unlock+0x31/0x50
[  350.589205]  [] ? drm_atomic_helper_swap_state+0x159/0x300 
[drm_kms_helper]
[  350.598787]  [] intel_atomic_commit+0x3b5/0x500 [i915]
[  350.606319]  [] ? 
drm_atomic_set_crtc_for_connector+0xcc/0x100 [drm]
[  350.615209]  [] drm_atomic_commit+0x49/0x50 [drm]
[  350.622242]  [] drm_atomic_helper_set_config+0x88/0xc0 
[drm_kms_helper]
[  350.631419]  [] drm_mode_set_config_internal+0x6c/0x120 
[drm]
[  350.639623]  [] drm_mode_setcrtc+0x22c/0x4d0 [drm]
[  350.646760]  [] drm_ioctl+0x209/0x460 [drm]
[  350.653217]  [] ? drm_mode_getcrtc+0x150/0x150 [drm]
[  350.660536]  [] ? __lock_is_held+0x4a/0x70
[  350.666885]  [] do_vfs_ioctl+0x93/0x6b0
[  350.672939]  [] ? __fget+0x113/0x200
[  350.678797]  [] ? __fget+0x5/0x200
[  350.684361]  [] SyS_ioctl+0x44/0x80
[  350.690030]  [] do_syscall_64+0x5b/0x120
[  350.696184]  [] entry_SYSCALL64_slow_path+0x25/0x25

Note we also have to remember the lesson from commit 4fc788f5ee3d
("drm/i915: Flush delayed fence releases after reset") where we have to
flush any changes to the fence on restore.

v2: Replace call to release user mmaps with an assertion that they have
already been zapped.

Fixes: 49ef5294cda2 ("drm/i915: Move fence tracking from object to vma")
Reported-by: Ville Syrjälä 
Signed-off-by: Chris Wilson 
Cc: Ville Syrjälä 
Cc: Joonas Lahtinen 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_gem_fence.c | 21 +++--
 1 file changed, 19 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_fence.c 
b/drivers/gpu/drm/i915/i915_gem_fence.c
index 8df1fa7234e8..f7081f4b5d22 100644
--- a/drivers/gpu/drm/i915/i915_gem_fence.c
+++ b/drivers/gpu/drm/i915/i915_gem_fence.c
@@ -290,6 +290,8 @@ i915_vma_put_fence(struct i915_vma *vma)
 {
struct drm_i915_fence_reg *fence = vma->fence;
 
+   assert_rpm_wakelock_held(to_i915(vma->vm->dev));
+
if (!fence)
return 0;
 
@@ -341,6 +343,8 @@ i915_vma_get_fence(struct i915_vma *vma)
struct drm_i915_fence_reg *fence;
struct i915_vma *set = i915_gem_object_is_tiled(vma->obj) ? vma : NULL;
 
+   assert_rpm_wakelock_held(to_i915(vma->vm->dev));
+
/* 

Re: [Intel-gfx] [PATCH 2/5] drm/i915: Update debugfs describe_obj() to show fault-mappable

[Joonas Lahtinen]

On ke, 2016-10-12 at 12:16 +0100, Chris Wilson wrote:
> The current meaning of whether an object has a GGTT vma is very
> ill-defined (and note we don't check for any partials either), it just
> means that at some point it was in the GGTT but it may not be now. The
> information we really care about here is whether it is taking up
> precious mappable aperture space. This is the obj->fault_mappable flag.
> We have a redundant long form reprinting of this information, so remove
> that in favour of the compact flag.
> 
> Signed-off-by: Chris Wilson 

I'm sure I already reviewed this as a part of another patch, but better
as a separate one!

Reviewed-by: Joonas Lahtinen 

Regards, Joonas
-- 
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Open Source Technology Center
Intel Corporation
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Re: [Intel-gfx] [PATCH 15/19] drm/i915: Make IS_G4X only take dev_priv

[David Weinehall]

On Tue, Oct 11, 2016 at 02:21:48PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin 
> 
> Saves 472 bytes of .rodata strings.
> 
> v2: Add parantheses around dev_priv. (Ville Syrjala)
> 
> Signed-off-by: Tvrtko Ursulin 

Reviewed-by: David Weinehall 

> ---
>  drivers/gpu/drm/i915/i915_drv.h|  2 +-
>  drivers/gpu/drm/i915/i915_gem_stolen.c |  5 +++--
>  drivers/gpu/drm/i915/i915_suspend.c|  4 ++--
>  drivers/gpu/drm/i915/intel_crt.c   |  2 +-
>  drivers/gpu/drm/i915/intel_display.c   | 40 
> ++
>  drivers/gpu/drm/i915/intel_dp.c|  2 +-
>  drivers/gpu/drm/i915/intel_hdmi.c  |  4 ++--
>  drivers/gpu/drm/i915/intel_pm.c|  4 ++--
>  8 files changed, 33 insertions(+), 30 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index c264e703b686..f54465ea2f44 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2649,7 +2649,7 @@ struct drm_i915_cmd_table {
>  #define IS_BROADWATER(dev)   (INTEL_INFO(dev)->is_broadwater)
>  #define IS_CRESTLINE(dev)(INTEL_INFO(dev)->is_crestline)
>  #define IS_GM45(dev_priv)(INTEL_DEVID(dev_priv) == 0x2A42)
> -#define IS_G4X(dev)  (INTEL_INFO(dev)->is_g4x)
> +#define IS_G4X(dev_priv) ((dev_priv)->info.is_g4x)
>  #define IS_PINEVIEW_G(dev_priv)  (INTEL_DEVID(dev_priv) == 0xa001)
>  #define IS_PINEVIEW_M(dev_priv)  (INTEL_DEVID(dev_priv) == 0xa011)
>  #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
> diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c 
> b/drivers/gpu/drm/i915/i915_gem_stolen.c
> index 3508120b8c90..d1b40bce0249 100644
> --- a/drivers/gpu/drm/i915/i915_gem_stolen.c
> +++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
> @@ -204,7 +204,8 @@ static unsigned long i915_stolen_to_physical(struct 
> drm_device *dev)
>   return 0;
>  
>   /* make sure we don't clobber the GTT if it's within stolen memory */
> - if (INTEL_INFO(dev)->gen <= 4 && !IS_G33(dev) && !IS_G4X(dev)) {
> + if (INTEL_GEN(dev_priv) <= 4 && !IS_G33(dev_priv) &&
> + !IS_G4X(dev_priv)) {
>   struct {
>   u32 start, end;
>   } stolen[2] = {
> @@ -437,7 +438,7 @@ int i915_gem_init_stolen(struct drm_device *dev)
>   case 3:
>   break;
>   case 4:
> - if (IS_G4X(dev))
> + if (IS_G4X(dev_priv))
>   g4x_get_stolen_reserved(dev_priv, _base,
>   _size);
>   break;
> diff --git a/drivers/gpu/drm/i915/i915_suspend.c 
> b/drivers/gpu/drm/i915/i915_suspend.c
> index a0af170062b1..7870856fccd0 100644
> --- a/drivers/gpu/drm/i915/i915_suspend.c
> +++ b/drivers/gpu/drm/i915/i915_suspend.c
> @@ -38,7 +38,7 @@ static void i915_save_display(struct drm_device *dev)
>   dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);
>  
>   /* save FBC interval */
> - if (HAS_FBC(dev) && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev))
> + if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv))
>   dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);
>  }
>  
> @@ -54,7 +54,7 @@ static void i915_restore_display(struct drm_device *dev)
>   intel_fbc_global_disable(dev_priv);
>  
>   /* restore FBC interval */
> - if (HAS_FBC(dev) && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev))
> + if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv))
>   I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL);
>  
>   i915_redisable_vga(dev);
> diff --git a/drivers/gpu/drm/i915/intel_crt.c 
> b/drivers/gpu/drm/i915/intel_crt.c
> index d4388c03b4da..d456786f5813 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -771,7 +771,7 @@ static int intel_crt_get_modes(struct drm_connector 
> *connector)
>  
>   i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
>   ret = intel_crt_ddc_get_modes(connector, i2c);
> - if (ret || !IS_G4X(dev))
> + if (ret || !IS_G4X(dev_priv))
>   goto out;
>  
>   /* Try to probe digital port for output in DVI-I -> VGA mode. */
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index 636e5572b996..bf871b565549 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3071,7 +3071,7 @@ static void i9xx_update_primary_plane(struct drm_plane 
> *primary,
>   fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
>   dspcntr |= DISPPLANE_TILED;
>  
> - if (IS_G4X(dev))
> + if (IS_G4X(dev_priv))
>   dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
>  
>   intel_add_fb_offsets(, , plane_state, 0);
> @@ -7226,7 +7226,7 @@ static int intel_crtc_compute_config(struct 

Re: [Intel-gfx] [PATCH 18/19] drm/i915: Make INTEL_GEN only take dev_priv

[David Weinehall]

On Tue, Oct 11, 2016 at 02:21:51PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin 
> 
> Saves 968 bytes of .rodata strings.
> 
> v2: Add parantheses around dev_priv. (Ville Syrjala)
> 
> Signed-off-by: Tvrtko Ursulin 

Reviewed-by: David Weinehall 

> ---
>  drivers/gpu/drm/i915/i915_drv.h  | 2 +-
>  drivers/gpu/drm/i915/i915_gem_render_state.c | 6 +++---
>  drivers/gpu/drm/i915/intel_display.c | 2 +-
>  drivers/gpu/drm/i915/intel_sprite.c  | 8 
>  4 files changed, 9 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index f9f9a218d5fe..3f38b9755763 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2604,8 +2604,8 @@ struct drm_i915_cmd_table {
>   __p; \
>  })
>  #define INTEL_INFO(p)(&__I915__(p)->info)
> -#define INTEL_GEN(p) (INTEL_INFO(p)->gen)
>  
> +#define INTEL_GEN(dev_priv)  ((dev_priv)->info.gen)
>  #define INTEL_DEVID(dev_priv)((dev_priv)->info.device_id)
>  
>  #define REVID_FOREVER0xff
> diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c 
> b/drivers/gpu/drm/i915/i915_gem_render_state.c
> index 95b7e9afd5f8..a98c0f42badd 100644
> --- a/drivers/gpu/drm/i915/i915_gem_render_state.c
> +++ b/drivers/gpu/drm/i915/i915_gem_render_state.c
> @@ -72,9 +72,9 @@ render_state_get_rodata(const struct drm_i915_gem_request 
> *req)
>  
>  static int render_state_setup(struct render_state *so)
>  {
> - struct drm_device *dev = so->vma->vm->dev;
> + struct drm_i915_private *dev_priv = to_i915(so->vma->vm->dev);
>   const struct intel_renderstate_rodata *rodata = so->rodata;
> - const bool has_64bit_reloc = INTEL_GEN(dev) >= 8;
> + const bool has_64bit_reloc = INTEL_GEN(dev_priv) >= 8;
>   unsigned int i = 0, reloc_index = 0;
>   struct page *page;
>   u32 *d;
> @@ -115,7 +115,7 @@ static int render_state_setup(struct render_state *so)
>  
>   so->aux_batch_offset = i * sizeof(u32);
>  
> - if (HAS_POOLED_EU(dev)) {
> + if (HAS_POOLED_EU(dev_priv)) {
>   /*
>* We always program 3x6 pool config but depending upon which
>* subslice is disabled HW drops down to appropriate config
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index c3fb9f700c7a..eda38e53f68a 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -12452,7 +12452,7 @@ int intel_plane_atomic_calc_changes(struct 
> drm_crtc_state *crtc_state,
>   struct drm_framebuffer *fb = plane_state->fb;
>   int ret;
>  
> - if (INTEL_GEN(dev) >= 9 && plane->type != DRM_PLANE_TYPE_CURSOR) {
> + if (INTEL_GEN(dev_priv) >= 9 && plane->type != DRM_PLANE_TYPE_CURSOR) {
>   ret = skl_update_scaler_plane(
>   to_intel_crtc_state(crtc_state),
>   to_intel_plane_state(plane_state));
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c 
> b/drivers/gpu/drm/i915/intel_sprite.c
> index f760d5fcbe48..8b4748839c07 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -753,7 +753,7 @@ intel_check_sprite_plane(struct drm_plane *plane,
>struct intel_crtc_state *crtc_state,
>struct intel_plane_state *state)
>  {
> - struct drm_device *dev = plane->dev;
> + struct drm_i915_private *dev_priv = to_i915(plane->dev);
>   struct drm_crtc *crtc = state->base.crtc;
>   struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>   struct intel_plane *intel_plane = to_intel_plane(plane);
> @@ -797,7 +797,7 @@ intel_check_sprite_plane(struct drm_plane *plane,
>   }
>  
>   /* setup can_scale, min_scale, max_scale */
> - if (INTEL_INFO(dev)->gen >= 9) {
> + if (INTEL_GEN(dev_priv) >= 9) {
>   /* use scaler when colorkey is not required */
>   if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
>   can_scale = 1;
> @@ -913,7 +913,7 @@ intel_check_sprite_plane(struct drm_plane *plane,
>  
>   width_bytes = ((src_x * cpp) & 63) + src_w * cpp;
>  
> - if (INTEL_INFO(dev)->gen < 9 && (src_w > 2048 || src_h > 2048 ||
> + if (INTEL_GEN(dev_priv) < 9 && (src_w > 2048 || src_h > 2048 ||
>   width_bytes > 4096 || fb->pitches[0] > 4096)) {
>   DRM_DEBUG_KMS("Source dimensions exceed hardware 
> limits\n");
>   return -EINVAL;
> @@ -932,7 +932,7 @@ intel_check_sprite_plane(struct drm_plane *plane,
>   dst->y1 = crtc_y;
>   dst->y2 = crtc_y + crtc_h;
>  
> - if (INTEL_GEN(dev) >= 9) {
> + if (INTEL_GEN(dev_priv) >= 9) {
>   ret = skl_check_plane_surface(state);
>   if (ret)
>   

Re: [Intel-gfx] [PATCH 1/5] drm/i915: Use fence_write() from rpm resume

[Joonas Lahtinen]

This was already;

Reviewed-by: Joonas Lahtinen 

Regards, Joonas
-- 
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Open Source Technology Center
Intel Corporation
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[Intel-gfx] [PATCH] drm/i915/dp: Debug log MST active links explicitly

[Dhinakaran Pandiyan]

No functional change. Just printing the number of active links without
stating what the number means is not very useful. So, add relevant text.

Signed-off-by: Dhinakaran Pandiyan 
---
 drivers/gpu/drm/i915/intel_dp_mst.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c 
b/drivers/gpu/drm/i915/intel_dp_mst.c
index 3ffbd69..62a69b5 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -86,7 +86,7 @@ static void intel_mst_disable_dp(struct intel_encoder 
*encoder,
to_intel_connector(old_conn_state->connector);
int ret;
 
-   DRM_DEBUG_KMS("%d\n", intel_dp->active_mst_links);
+   DRM_DEBUG_KMS("active MST links: %d\n", intel_dp->active_mst_links);
 
drm_dp_mst_reset_vcpi_slots(_dp->mst_mgr, connector->port);
 
@@ -106,7 +106,7 @@ static void intel_mst_post_disable_dp(struct intel_encoder 
*encoder,
struct intel_connector *connector =
to_intel_connector(old_conn_state->connector);
 
-   DRM_DEBUG_KMS("%d\n", intel_dp->active_mst_links);
+   DRM_DEBUG_KMS("active MST links: %d\n", intel_dp->active_mst_links);
 
/* this can fail */
drm_dp_check_act_status(_dp->mst_mgr);
@@ -147,7 +147,7 @@ static void intel_mst_pre_enable_dp(struct intel_encoder 
*encoder,
connector->encoder = encoder;
intel_mst->connector = connector;
 
-   DRM_DEBUG_KMS("%d\n", intel_dp->active_mst_links);
+   DRM_DEBUG_KMS("active MST links: %d\n", intel_dp->active_mst_links);
 
if (intel_dp->active_mst_links == 0) {
intel_ddi_clk_select(_dig_port->base,
@@ -194,7 +194,7 @@ static void intel_mst_enable_dp(struct intel_encoder 
*encoder,
enum port port = intel_dig_port->port;
int ret;
 
-   DRM_DEBUG_KMS("%d\n", intel_dp->active_mst_links);
+   DRM_DEBUG_KMS("active MST links: %d\n", intel_dp->active_mst_links);
 
if (intel_wait_for_register(dev_priv,
DP_TP_STATUS(port),
-- 
2.7.4

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Re: [Intel-gfx] [PATCH 13/19] drm/i915: Make IS_BROXTON only take dev_priv

[David Weinehall]

On Tue, Oct 11, 2016 at 02:21:46PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin 
> 
> Saves 1392 bytes of .rodata strings.
> 
> v2: Add parantheses around dev_priv. (Ville Syrjala)
> 
> Signed-off-by: Tvrtko Ursulin 

This patch does quite a bit more than just change IS_BROXTON to use
dev_priv...

> ---
>  drivers/gpu/drm/i915/i915_drv.c |  2 +-
>  drivers/gpu/drm/i915/i915_drv.h |  5 +++--
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 40 
> +
>  drivers/gpu/drm/i915/i915_irq.c |  2 +-
>  drivers/gpu/drm/i915/intel_ddi.c|  4 ++--
>  drivers/gpu/drm/i915/intel_display.c| 31 ++---
>  drivers/gpu/drm/i915/intel_dp.c | 16 ++---
>  drivers/gpu/drm/i915/intel_dpll_mgr.c   |  2 +-
>  drivers/gpu/drm/i915/intel_dsi.c| 27 +++---
>  drivers/gpu/drm/i915/intel_dsi_pll.c| 26 ++---
>  drivers/gpu/drm/i915/intel_guc_loader.c |  8 +++
>  drivers/gpu/drm/i915/intel_hdmi.c   |  6 ++---
>  drivers/gpu/drm/i915/intel_runtime_pm.c |  2 +-
>  13 files changed, 89 insertions(+), 82 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index d854ea4a7e92..18af6d1ccec9 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -2437,7 +2437,7 @@ static int intel_runtime_resume(struct device *kdev)
>   if (IS_GEN6(dev_priv))
>   intel_init_pch_refclk(dev);
>  
> - if (IS_BROXTON(dev)) {
> + if (IS_BROXTON(dev_priv)) {
>   bxt_disable_dc9(dev_priv);
>   bxt_display_core_init(dev_priv, true);
>   if (dev_priv->csr.dmc_payload &&
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 9784e61400e5..ad9299196d13 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2664,7 +2664,7 @@ struct drm_i915_cmd_table {
>  #define IS_HASWELL(dev_priv) ((dev_priv)->info.is_haswell)
>  #define IS_BROADWELL(dev_priv)   ((dev_priv)->info.is_broadwell)
>  #define IS_SKYLAKE(dev_priv) ((dev_priv)->info.is_skylake)
> -#define IS_BROXTON(dev)  (INTEL_INFO(dev)->is_broxton)
> +#define IS_BROXTON(dev_priv) ((dev_priv)->info.is_broxton)
>  #define IS_KABYLAKE(dev_priv)((dev_priv)->info.is_kabylake)
>  #define IS_MOBILE(dev)   (INTEL_INFO(dev)->is_mobile)
>  #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
> @@ -2724,7 +2724,8 @@ struct drm_i915_cmd_table {
>  #define BXT_REVID_B0 0x3
>  #define BXT_REVID_C0 0x9
>  
> -#define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, 
> until))
> +#define IS_BXT_REVID(dev_priv, since, until) \
> + (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
>  
>  #define KBL_REVID_A0 0x0
>  #define KBL_REVID_B0 0x1
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index cf43a5632961..e628691fe97e 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -373,27 +373,29 @@ static void *kmap_page_dma(struct i915_page_dma *p)
>  /* We use the flushing unmap only with ppgtt structures:
>   * page directories, page tables and scratch pages.
>   */
> -static void kunmap_page_dma(struct drm_device *dev, void *vaddr)
> +static void kunmap_page_dma(struct drm_i915_private *dev_priv, void *vaddr)
>  {
>   /* There are only few exceptions for gen >=6. chv and bxt.
>* And we are not sure about the latter so play safe for now.
>*/
> - if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
> + if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
>   drm_clflush_virt_range(vaddr, PAGE_SIZE);
>  
>   kunmap_atomic(vaddr);
>  }
>  
>  #define kmap_px(px) kmap_page_dma(px_base(px))
> -#define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, (vaddr))
> +#define kunmap_px(ppgtt, vaddr) \
> + kunmap_page_dma(to_i915((ppgtt)->base.dev), (vaddr))
>  
>  #define setup_px(dev, px) setup_page_dma((dev), px_base(px))
>  #define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px))
> -#define fill_px(dev, px, v) fill_page_dma((dev), px_base(px), (v))
> -#define fill32_px(dev, px, v) fill_page_dma_32((dev), px_base(px), (v))
> +#define fill_px(dev_priv, px, v) fill_page_dma((dev_priv), px_base(px), (v))
> +#define fill32_px(dev_priv, px, v) \
> + fill_page_dma_32((dev_priv), px_base(px), (v))
>  
> -static void fill_page_dma(struct drm_device *dev, struct i915_page_dma *p,
> -   const uint64_t val)
> +static void fill_page_dma(struct drm_i915_private *dev_priv,
> +   struct i915_page_dma *p, const uint64_t val)
>  {
>   int i;
>   uint64_t * const vaddr = kmap_page_dma(p);
> @@ -401,17 +403,17 @@ static void 

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Move common code out of i915_gpu_error.c

[Joonas Lahtinen]

On ti, 2016-10-11 at 14:32 +0100, Chris Wilson wrote:
> In the next patch, I want to conditionally compile i915_gpu_error.c and
> that requires moving the functions used by debug out of
> i915_gpu_error.c!
> 
> Signed-off-by: Chris Wilson 

Reviewed-by: Joonas Lahtinen 

Regards, Joonas
-- 
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Open Source Technology Center
Intel Corporation
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Re: [Intel-gfx] [PATCH 07/19] drm/i915: Make INTEL_DEVID only take dev_priv

[David Weinehall]

On Tue, Oct 11, 2016 at 02:21:40PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin 
> 
> Saves 4472 bytes of .rodata strings.
> 
> v2: Add parantheses around dev_priv. (Ville Syrjala)

Reviewed-by: David Weinehall 

> 
> Signed-off-by: Tvrtko Ursulin 
> ---
>  drivers/gpu/drm/i915/i915_drv.c|  14 +++--
>  drivers/gpu/drm/i915/i915_drv.h| 111 
> +
>  drivers/gpu/drm/i915/i915_gem.c|  36 +--
>  drivers/gpu/drm/i915/i915_gem_stolen.c |   6 +-
>  drivers/gpu/drm/i915/i915_gem_tiling.c |   3 +-
>  drivers/gpu/drm/i915/i915_irq.c|   2 +-
>  drivers/gpu/drm/i915/intel_crt.c   |   4 +-
>  drivers/gpu/drm/i915/intel_display.c   |  58 +
>  drivers/gpu/drm/i915/intel_dp.c|   2 +-
>  drivers/gpu/drm/i915/intel_hdmi.c  |   2 +-
>  drivers/gpu/drm/i915/intel_i2c.c   |   5 +-
>  drivers/gpu/drm/i915/intel_lvds.c  |   9 ++-
>  drivers/gpu/drm/i915/intel_pm.c|  26 
>  drivers/gpu/drm/i915/intel_sdvo.c  |  11 ++--
>  drivers/gpu/drm/i915/intel_tv.c|   4 +-
>  15 files changed, 151 insertions(+), 142 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index fbb4e2e0d124..bfdbbb745939 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -188,12 +188,14 @@ static void intel_detect_pch(struct drm_device *dev)
>   dev_priv->pch_type = PCH_LPT;
>   DRM_DEBUG_KMS("Found LynxPoint PCH\n");
>   WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
> - WARN_ON(IS_HSW_ULT(dev) || IS_BDW_ULT(dev));
> + WARN_ON(IS_HSW_ULT(dev_priv) ||
> + IS_BDW_ULT(dev_priv));
>   } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
>   dev_priv->pch_type = PCH_LPT;
>   DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
>   WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
> - WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev));
> + WARN_ON(!IS_HSW_ULT(dev_priv) &&
> + !IS_BDW_ULT(dev_priv));
>   } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
>   dev_priv->pch_type = PCH_SPT;
>   DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
> @@ -422,7 +424,7 @@ intel_setup_mchbar(struct drm_device *dev)
>  
>   dev_priv->mchbar_need_disable = false;
>  
> - if (IS_I915G(dev) || IS_I915GM(dev)) {
> + if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
>   pci_read_config_dword(dev_priv->bridge_dev, DEVEN, );
>   enabled = !!(temp & DEVEN_MCHBAR_EN);
>   } else {
> @@ -440,7 +442,7 @@ intel_setup_mchbar(struct drm_device *dev)
>   dev_priv->mchbar_need_disable = true;
>  
>   /* Space is allocated or reserved, so enable it. */
> - if (IS_I915G(dev) || IS_I915GM(dev)) {
> + if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
>   pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
>  temp | DEVEN_MCHBAR_EN);
>   } else {
> @@ -456,7 +458,7 @@ intel_teardown_mchbar(struct drm_device *dev)
>   int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
>  
>   if (dev_priv->mchbar_need_disable) {
> - if (IS_I915G(dev) || IS_I915GM(dev)) {
> + if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
>   u32 deven_val;
>  
>   pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
> @@ -1077,7 +1079,7 @@ static int i915_driver_init_hw(struct drm_i915_private 
> *dev_priv)
>* be lost or delayed, but we use them anyways to avoid
>* stuck interrupts on some machines.
>*/
> - if (!IS_I945G(dev) && !IS_I945GM(dev)) {
> + if (!IS_I945G(dev_priv) && !IS_I945GM(dev_priv)) {
>   if (pci_enable_msi(pdev) < 0)
>   DRM_DEBUG_DRIVER("can't enable MSI");
>   }
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 58045cd7a087..7a40dfa830e7 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2605,7 +2605,8 @@ struct drm_i915_cmd_table {
>  })
>  #define INTEL_INFO(p)(&__I915__(p)->info)
>  #define INTEL_GEN(p) (INTEL_INFO(p)->gen)
> -#define INTEL_DEVID(p)   (INTEL_INFO(p)->device_id)
> +
> +#define INTEL_DEVID(dev_priv)((dev_priv)->info.device_id)
>  
>  #define REVID_FOREVER0xff
>  #define INTEL_REVID(p)   (__I915__(p)->drm.pdev->revision)
> @@ -2637,27 +2638,27 @@ struct drm_i915_cmd_table {
>  #define 

Re: [Intel-gfx] [PATCH i-g-t 1/5] tests: Use bash for debugfs_wedged and drm_lib.sh

[Joonas Lahtinen]

On ke, 2016-10-12 at 14:16 +0300, Jani Nikula wrote:
> If you really care, go ahead and send the patches to make these Bourne
> shell compatible, but then do also sign up for testing them on non-bash
> shells. The CI won't. I don't think it's worth the trouble, but YMMV.

If they're re-written using POSIX sh constructs only, I don't think
they need to be tested outside of POSIX sh? That's what standards are
for.

I also remember FreeBSD guys being all for letting bash dependency go.
So there'd be actual gains too.

./scripts/run-tests.sh:Bourne-Again shell script, UTF-8 Unicode 
text executable
./scripts/who.sh:  Bourne-Again shell script, ASCII text 
executable
./tests/vgem_reload_basic: Bourne-Again shell script, ASCII text 
executable
./tests/debugfs_emon_crash:Bourne-Again shell script, ASCII text 
executable
./tests/drv_module_reload_basic:   Bourne-Again shell script, ASCII text 
executable
./tests/ddx_intel_after_fbdev: Bourne-Again shell script, ASCII text 
executable
./tests/test_rte_check:Bourne-Again shell script, ASCII text 
executable
./tests/tools_test:Bourne-Again shell script, ASCII text 
executable
./tests/check_drm_clients: Bourne-Again shell script, ASCII text 
executable
./tests/sysfs_l3_parity:   Bourne-Again shell script, ASCII text 
executable
./tests/drv_debugfs_reader:Bourne-Again shell script, ASCII text 
executable
./tests/kms_sysfs_edid_timing: Bourne-Again shell script, ASCII text 
executable
./tools/intel_aubdump.in:  Bourne-Again shell script, ASCII text 
executable

All are easily convertible. So let's do this.

Regards, Joonas
-- 
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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[Intel-gfx] [PATCH] drm/i915: GMBUS don't need no forcewake

[ville . syrjala]

From: Ville Syrjälä 

GMBUS is part of the display engine, and thus has no need for
forcewake. Let's not bother trying to grab it then.

I don't recall if the display engine suffers from system hangs
due to multiple accesses to the same "cacheline" in mmio space.
I hope not since we're no longer protected by the uncore lock
since commit 4e6c2d58ba86 ("drm/i915: Take forcewake once for
the entire GMBUS transaction")

Cc: Chris Wilson 
Cc: David Weinehall 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_i2c.c | 5 -
 1 file changed, 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index 79aab9ad6faa..49c7824a4c29 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -468,13 +468,9 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg 
*msgs, int num)
   struct intel_gmbus,
   adapter);
struct drm_i915_private *dev_priv = bus->dev_priv;
-   const unsigned int fw =
-   intel_uncore_forcewake_for_reg(dev_priv, GMBUS0,
-  FW_REG_READ | FW_REG_WRITE);
int i = 0, inc, try = 0;
int ret = 0;
 
-   intel_uncore_forcewake_get(dev_priv, fw);
 retry:
I915_WRITE_FW(GMBUS0, bus->reg0);
 
@@ -576,7 +572,6 @@ timeout:
ret = -EAGAIN;
 
 out:
-   intel_uncore_forcewake_put(dev_priv, fw);
return ret;
 }
 
-- 
2.7.4

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Re: [Intel-gfx] [PATCH 10/19] drm/i915: Make IS_HASWELL only take dev_priv

[David Weinehall]

On Tue, Oct 11, 2016 at 02:21:43PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin 
> 
> Saves 2432 bytes of .rodata strings.
> 
> v2: Add parantheses around dev_priv. (Ville Syrjala)
> 
> Signed-off-by: Tvrtko Ursulin 

Reviewed-by: David Weinehall 

> ---
>  drivers/gpu/drm/i915/i915_drv.h  |  2 +-
>  drivers/gpu/drm/i915/i915_gem.c  |  2 +-
>  drivers/gpu/drm/i915/i915_gem_gtt.c  |  4 ++--
>  drivers/gpu/drm/i915/i915_irq.c  |  4 ++--
>  drivers/gpu/drm/i915/i915_reg.h  |  4 ++--
>  drivers/gpu/drm/i915/intel_color.c   |  4 ++--
>  drivers/gpu/drm/i915/intel_ddi.c |  2 +-
>  drivers/gpu/drm/i915/intel_display.c | 23 ++-
>  drivers/gpu/drm/i915/intel_psr.c |  6 +++---
>  9 files changed, 24 insertions(+), 27 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 13e409554fcc..d6c3a4bb29aa 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2661,7 +2661,7 @@ struct drm_i915_cmd_table {
>INTEL_DEVID(dev_priv) == 0x015a)
>  #define IS_VALLEYVIEW(dev)   (INTEL_INFO(dev)->is_valleyview)
>  #define IS_CHERRYVIEW(dev)   (INTEL_INFO(dev)->is_cherryview)
> -#define IS_HASWELL(dev)  (INTEL_INFO(dev)->is_haswell)
> +#define IS_HASWELL(dev_priv) ((dev_priv)->info.is_haswell)
>  #define IS_BROADWELL(dev_priv)   ((dev_priv)->info.is_broadwell)
>  #define IS_SKYLAKE(dev)  (INTEL_INFO(dev)->is_skylake)
>  #define IS_BROXTON(dev)  (INTEL_INFO(dev)->is_broxton)
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index aefb88f987b2..8c362899674a 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -4360,7 +4360,7 @@ i915_gem_init_hw(struct drm_device *dev)
>   if (HAS_EDRAM(dev) && INTEL_GEN(dev_priv) < 9)
>   I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
>  
> - if (IS_HASWELL(dev))
> + if (IS_HASWELL(dev_priv))
>   I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ?
>  LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
>  
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 0f8f073c589c..3246d51c7b8e 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -1746,7 +1746,7 @@ static void gen7_ppgtt_enable(struct drm_device *dev)
>   I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
>  
>   ecochk = I915_READ(GAM_ECOCHK);
> - if (IS_HASWELL(dev)) {
> + if (IS_HASWELL(dev_priv)) {
>   ecochk |= ECOCHK_PPGTT_WB_HSW;
>   } else {
>   ecochk |= ECOCHK_PPGTT_LLC_IVB;
> @@ -2058,7 +2058,7 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
>   ppgtt->base.pte_encode = ggtt->base.pte_encode;
>   if (intel_vgpu_active(dev_priv) || IS_GEN6(dev))
>   ppgtt->switch_mm = gen6_mm_switch;
> - else if (IS_HASWELL(dev))
> + else if (IS_HASWELL(dev_priv))
>   ppgtt->switch_mm = hsw_mm_switch;
>   else if (IS_GEN7(dev))
>   ppgtt->switch_mm = gen7_mm_switch;
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 5fb3b1c9a52c..47337aabc326 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3594,8 +3594,8 @@ static void gen5_gt_irq_postinstall(struct drm_device 
> *dev)
>   dev_priv->gt_irq_mask = ~0;
>   if (HAS_L3_DPF(dev)) {
>   /* L3 parity interrupt is always unmasked. */
> - dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
> - gt_irqs |= GT_PARITY_ERROR(dev);
> + dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev_priv);
> + gt_irqs |= GT_PARITY_ERROR(dev_priv);
>   }
>  
>   gt_irqs |= GT_RENDER_USER_INTERRUPT;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index acc767a52d8e..8b61669af628 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2094,9 +2094,9 @@ enum skl_disp_power_wells {
>  #define PM_VEBOX_CS_ERROR_INTERRUPT  (1 << 12) /* hsw+ */
>  #define PM_VEBOX_USER_INTERRUPT  (1 << 10) /* hsw+ */
>  
> -#define GT_PARITY_ERROR(dev) \
> +#define GT_PARITY_ERROR(dev_priv) \
>   (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \
> -  (IS_HASWELL(dev) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
> +  (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
>  
>  /* These are all the "old" interrupts */
>  #define ILK_BSD_USER_INTERRUPT   (1<<5)
> diff --git a/drivers/gpu/drm/i915/intel_color.c 
> b/drivers/gpu/drm/i915/intel_color.c
> index be76ef88678c..da76a799411a 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ 

Re: [Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915: Trust VBT aux/ddc information

[Ville Syrjälä]

On Tue, Oct 11, 2016 at 06:49:46PM -, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915: Trust VBT aux/ddc information
> URL   : https://patchwork.freedesktop.org/series/13600/
> State : warning
> 
> == Summary ==
> 
> Series 13600v1 drm/i915: Trust VBT aux/ddc information
> https://patchwork.freedesktop.org/api/1.0/series/13600/revisions/1/mbox/
> 
> Test kms_pipe_crc_basic:
> Subgroup suspend-read-crc-pipe-b:
> dmesg-warn -> PASS   (fi-byt-j1900)
> Subgroup suspend-read-crc-pipe-c:
> pass   -> DMESG-WARN (fi-skl-6700k)

[  631.216836] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU 
pipe C FIFO underrun

moar SKL underruns

> Test kms_psr_sink_crc:
> Subgroup psr_basic:
> pass   -> DMESG-WARN (fi-skl-6700hq)

[  647.478464] [drm:intel_pipe_update_start [i915]] *ERROR* Potential atomic 
update failure on pipe A

DMC making life difficult for vblank irqs I guess.

> Test pm_backlight:
> Subgroup basic-brightness:
> skip   -> PASS   (fi-skl-6700k)
> Test vgem_basic:
> Subgroup unload:
> pass   -> SKIP   (fi-ivb-3770)
> pass   -> SKIP   (fi-byt-n2820)
> skip   -> PASS   (fi-bsw-n3050)
> skip   -> PASS   (fi-skl-6700k)
> skip   -> PASS   (fi-bdw-5557u)
> 
> fi-bdw-5557u total:248  pass:232  dwarn:0   dfail:0   fail:0   skip:16 
> fi-bsw-n3050 total:248  pass:205  dwarn:0   dfail:0   fail:0   skip:43 
> fi-bxt-t5700 total:248  pass:217  dwarn:0   dfail:0   fail:0   skip:31 
> fi-byt-j1900 total:248  pass:215  dwarn:0   dfail:0   fail:1   skip:32 
> fi-byt-n2820 total:248  pass:210  dwarn:0   dfail:0   fail:1   skip:37 
> fi-hsw-4770  total:248  pass:224  dwarn:0   dfail:0   fail:0   skip:24 
> fi-hsw-4770r total:248  pass:224  dwarn:0   dfail:0   fail:0   skip:24 
> fi-ilk-650   total:248  pass:185  dwarn:0   dfail:0   fail:2   skip:61 
> fi-ivb-3520m total:248  pass:221  dwarn:0   dfail:0   fail:0   skip:27 
> fi-ivb-3770  total:248  pass:221  dwarn:0   dfail:0   fail:0   skip:27 
> fi-kbl-7200u total:248  pass:222  dwarn:0   dfail:0   fail:0   skip:26 
> fi-skl-6700hqtotal:248  pass:223  dwarn:1   dfail:0   fail:0   skip:24 
> fi-skl-6700k total:248  pass:222  dwarn:2   dfail:0   fail:0   skip:24 
> fi-snb-2520m total:248  pass:211  dwarn:0   dfail:0   fail:0   skip:37 
> fi-snb-2600  total:248  pass:209  dwarn:0   dfail:0   fail:0   skip:39 
> 
> Results at /archive/results/CI_IGT_test/Patchwork_2676/
> 
> 41409515b7b3365bcb2c2e9239fdfaa286a51333 drm-intel-nightly: 
> 2016y-10m-11d-17h-55m-34s UTC integration manifest
> 8e39dff drm/i915: Fix whitespace issues
> 536a3b5 drm/i915: Clean up DDI DDC/AUX CH sanitation
> a01faf4 drm/i915: Respect alternate_ddc_pin for all DDI ports
> 8e81858 drm/i915: Respect alternate_aux_channel for all DDI ports

-- 
Ville Syrjälä
Intel OTC
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Re: [Intel-gfx] [PATCH 14/19] drm/i915: Make HAS_L3_DPF only take dev_priv

[David Weinehall]

On Tue, Oct 11, 2016 at 02:21:47PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin 
> 
> Saves 472 bytes of .rodata strings.
> 
> v2: Add parantheses around dev_priv. (Ville Syrjala)
> 
> Signed-off-by: Tvrtko Ursulin 

Reviewed-by: David Weinehall 

> ---
>  drivers/gpu/drm/i915/i915_drv.h | 2 +-
>  drivers/gpu/drm/i915/i915_irq.c | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index ad9299196d13..c264e703b686 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2869,7 +2869,7 @@ struct drm_i915_cmd_table {
>  #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
>  
>  /* DPF == dynamic parity feature */
> -#define HAS_L3_DPF(dev) (INTEL_INFO(dev)->has_l3_dpf)
> +#define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
>  #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
>2 : HAS_L3_DPF(dev_priv))
>  
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 75f4ba935ebc..079ba7cfc971 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3592,7 +3592,7 @@ static void gen5_gt_irq_postinstall(struct drm_device 
> *dev)
>   pm_irqs = gt_irqs = 0;
>  
>   dev_priv->gt_irq_mask = ~0;
> - if (HAS_L3_DPF(dev)) {
> + if (HAS_L3_DPF(dev_priv)) {
>   /* L3 parity interrupt is always unmasked. */
>   dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev_priv);
>   gt_irqs |= GT_PARITY_ERROR(dev_priv);
> -- 
> 2.7.4
> 
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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,1/6] drm/i915: Move common code out of i915_gpu_error.c

[Patchwork]

== Series Details ==

Series: series starting with [CI,1/6] drm/i915: Move common code out of 
i915_gpu_error.c
URL   : https://patchwork.freedesktop.org/series/13630/
State : failure

== Summary ==

Series 13630v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/13630/revisions/1/mbox/

Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass   -> DMESG-WARN (fi-byt-j1900)
Test kms_psr_sink_crc:
Subgroup psr_basic:
pass   -> DMESG-WARN (fi-skl-6700hq)
Test vgem_basic:
Subgroup unload:
pass   -> SKIP   (fi-hsw-4770)
skip   -> PASS   (fi-kbl-7200u)
Test vgem_reload_basic:
pass   -> FAIL   (fi-hsw-4770)

fi-bdw-5557u total:248  pass:232  dwarn:0   dfail:0   fail:0   skip:16 
fi-bsw-n3050 total:248  pass:205  dwarn:0   dfail:0   fail:0   skip:43 
fi-bxt-t5700 total:248  pass:217  dwarn:0   dfail:0   fail:0   skip:31 
fi-byt-j1900 total:248  pass:213  dwarn:2   dfail:0   fail:1   skip:32 
fi-byt-n2820 total:248  pass:211  dwarn:0   dfail:0   fail:1   skip:36 
fi-hsw-4770  total:248  pass:223  dwarn:0   dfail:0   fail:1   skip:24 
fi-hsw-4770r total:248  pass:225  dwarn:0   dfail:0   fail:0   skip:23 
fi-ilk-650   total:248  pass:185  dwarn:0   dfail:0   fail:2   skip:61 
fi-ivb-3520m total:248  pass:222  dwarn:0   dfail:0   fail:0   skip:26 
fi-ivb-3770  total:248  pass:222  dwarn:0   dfail:0   fail:0   skip:26 
fi-kbl-7200u total:248  pass:223  dwarn:0   dfail:0   fail:0   skip:25 
fi-skl-6260u total:248  pass:233  dwarn:0   dfail:0   fail:0   skip:15 
fi-skl-6700hqtotal:248  pass:224  dwarn:1   dfail:0   fail:0   skip:23 
fi-skl-6700k total:248  pass:222  dwarn:1   dfail:0   fail:0   skip:25 
fi-skl-6770hqtotal:248  pass:231  dwarn:1   dfail:0   fail:1   skip:15 
fi-snb-2520m total:248  pass:211  dwarn:0   dfail:0   fail:0   skip:37 
fi-snb-2600  total:248  pass:210  dwarn:0   dfail:0   fail:0   skip:38 

Results at /archive/results/CI_IGT_test/Patchwork_2680/

f766f3683894b41737352df7e0c0b7aaddd739e3 drm-intel-nightly: 
2016y-10m-12d-08h-02m-34s UTC integration manifest
c9a5e10 drm/i915: Compress GPU objects in error state
a70a22b drm/i915: Consolidate error object printing
b34f237 drm/i915: Always use the GTT for error capture
e9ac889 drm/i915: Stop the machine whilst capturing the GPU crash dump
c3d6a7a drm/i915: Allow disabling error capture
1d727df drm/i915: Move common code out of i915_gpu_error.c

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[Intel-gfx] [PATCH] drm/i915: Make sure the base lives at offset 0 of all kms objects

[ville . syrjala]

From: Ville Syrjälä 

We occasionally depend on eg. to_intel_crtc(NULL) being NULL as
well. Sprinkle in some BUILD_BUG_ON()s to make sure we don't
accidentally change things in a way that would violate this
assumption.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_display.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index e4bdd3a6a6e3..724a982bbb05 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -16331,6 +16331,15 @@ void intel_modeset_init(struct drm_device *dev)
enum pipe pipe;
struct intel_crtc *crtc;
 
+   BUILD_BUG_ON(to_intel_plane(NULL) != NULL);
+   BUILD_BUG_ON(to_intel_crtc(NULL) != NULL);
+   BUILD_BUG_ON(to_intel_encoder(NULL) != NULL);
+   BUILD_BUG_ON(to_intel_connector(NULL) != NULL);
+
+   BUILD_BUG_ON(to_intel_plane_state(NULL) != NULL);
+   BUILD_BUG_ON(to_intel_crtc_state(NULL) != NULL);
+   BUILD_BUG_ON(to_intel_atomic_state(NULL) != NULL);
+
drm_mode_config_init(dev);
 
dev->mode_config.min_width = 0;
-- 
2.7.4

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Re: [Intel-gfx] [PATCH 03/19] drm/i915: Make HAS_GMCH_DISPLAY only take dev_priv

[Tvrtko Ursulin]

On 12/10/2016 09:17, David Weinehall wrote:

On Tue, Oct 11, 2016 at 02:21:36PM +0100, Tvrtko Ursulin wrote:

From: Tvrtko Ursulin

More .rodata string saving by avoid __I915__ magic inside WARNs.

v2: Add parantheses around dev_priv. (Ville Syrjala)

Signed-off-by: Tvrtko Ursulin

Reviewed-by: David Weinehall

Note that once this patch series goes in (or before),
we should have a patch that turns intel_hdmi_to_dev() into
intel_hdmi_to_dev_priv().  If you look at the code in
intel_hdmi.c, almost every (after the dev -> dev_priv transition
I think it's every) instance where it's used converts
dev immediately further to dev_priv.


Agreed, but best left for later I think. And there is more of those 
opportunities throughout the code which I spotted while doing this.


Regards,

Tvrtko

P.S. For some reason reply to all from thunderbird keeps dropping you 
from the recipients. I might forget to manually add you.



---
  drivers/gpu/drm/i915/i915_drv.h| 2 +-
  drivers/gpu/drm/i915/intel_color.c | 6 +++---
  drivers/gpu/drm/i915/intel_display.c   | 8 
  drivers/gpu/drm/i915/intel_dp.c| 2 +-
  drivers/gpu/drm/i915/intel_dsi.c   | 2 +-
  drivers/gpu/drm/i915/intel_fifo_underrun.c | 2 +-
  drivers/gpu/drm/i915/intel_hdmi.c  | 5 +++--
  7 files changed, 14 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3caa1c767512..1a4698e665be 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2863,7 +2863,7 @@ struct drm_i915_cmd_table {
  #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
  #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
  
-#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->has_gmch_display)

+#define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
  
  /* DPF == dynamic parity feature */

  #define HAS_L3_DPF(dev) (INTEL_INFO(dev)->has_l3_dpf)
diff --git a/drivers/gpu/drm/i915/intel_color.c 
b/drivers/gpu/drm/i915/intel_color.c
index 95a72771eea6..5362c07932d3 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -273,7 +273,7 @@ static void i9xx_load_luts_internal(struct drm_crtc *crtc,
enum pipe pipe = intel_crtc->pipe;
int i;
  
-	if (HAS_GMCH_DISPLAY(dev)) {

+   if (HAS_GMCH_DISPLAY(dev_priv)) {
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
assert_dsi_pll_enabled(dev_priv);
else
@@ -288,7 +288,7 @@ static void i9xx_load_luts_internal(struct drm_crtc *crtc,
(drm_color_lut_extract(lut[i].green, 8) << 8) |
drm_color_lut_extract(lut[i].blue, 8);
  
-			if (HAS_GMCH_DISPLAY(dev))

+   if (HAS_GMCH_DISPLAY(dev_priv))
I915_WRITE(PALETTE(pipe, i), word);
else
I915_WRITE(LGC_PALETTE(pipe, i), word);
@@ -297,7 +297,7 @@ static void i9xx_load_luts_internal(struct drm_crtc *crtc,
for (i = 0; i < 256; i++) {
uint32_t word = (i << 16) | (i << 8) | i;
  
-			if (HAS_GMCH_DISPLAY(dev))

+   if (HAS_GMCH_DISPLAY(dev_priv))
I915_WRITE(PALETTE(pipe, i), word);
else
I915_WRITE(LGC_PALETTE(pipe, i), word);
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 0a69e80821ee..b7685936d324 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5036,7 +5036,7 @@ intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
 * event which is after the vblank start event, so we need to have a
 * wait-for-vblank between disabling the plane and the pipe.
 */
-   if (HAS_GMCH_DISPLAY(dev)) {
+   if (HAS_GMCH_DISPLAY(dev_priv)) {
intel_set_memory_cxsr(dev_priv, false);
dev_priv->wm.vlv.cxsr = false;
intel_wait_for_vblank(dev, pipe);
@@ -5101,7 +5101,7 @@ static void intel_pre_plane_update(struct 
intel_crtc_state *old_crtc_state)
intel_pre_disable_primary(>base);
}
  
-	if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev)) {

+   if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev_priv)) {
crtc->wm.cxsr_allowed = false;
  
  		/*

@@ -10895,7 +10895,7 @@ static void intel_crtc_update_cursor(struct drm_crtc 
*crtc,
pos |= y << CURSOR_Y_SHIFT;
  
  		/* ILK+ do this automagically */

-   if (HAS_GMCH_DISPLAY(dev) &&
+   if (HAS_GMCH_DISPLAY(dev_priv) &&
plane_state->base.rotation == DRM_ROTATE_180) {
base += 

[Intel-gfx] [PATCH] drm/i915: Fix misplaced '\n' in printing the GPU error's RING_HEAD

[Chris Wilson]

'\n' is supposed to be at the end of the line, not in the middle.

Fixes: cdb324bde570 ("drm/i915: Show bounds of active request in the ring...")
Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 2df4bc2af0bb..673750fc0d5b 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -368,7 +368,7 @@ static void error_print_engine(struct 
drm_i915_error_state_buf *m,
 {
err_printf(m, "%s command stream:\n", engine_str(ee->engine_id));
err_printf(m, "  START: 0x%08x\n", ee->start);
-   err_printf(m, "  HEAD:  0x%08x\n [0x%08x]", ee->head, ee->rq_head);
+   err_printf(m, "  HEAD:  0x%08x [0x%08x]\n", ee->head, ee->rq_head);
err_printf(m, "  TAIL:  0x%08x [0x%08x, 0x%08x]\n",
   ee->tail, ee->rq_post, ee->rq_tail);
err_printf(m, "  CTL:   0x%08x\n", ee->ctl);
-- 
2.9.3

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Re: [Intel-gfx] [PATCH] drm/i915: Remove unused BSM_MASK causing warning

[Joonas Lahtinen]

On ke, 2016-10-12 at 08:42 +0100, Chris Wilson wrote:
> greps ok.
> Reviewed-by: Chris Wilson 

Merged, thanks for the review.

Regards, Joonas
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[Intel-gfx] [CI 1/6] drm/i915: Move common code out of i915_gpu_error.c

[Chris Wilson]

In the next patch, I want to conditionally compile i915_gpu_error.c and
that requires moving the functions used by debug out of
i915_gpu_error.c!

Signed-off-by: Chris Wilson 
Reviewed-by: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_debugfs.c |   2 +-
 drivers/gpu/drm/i915/i915_drv.h |   3 -
 drivers/gpu/drm/i915/i915_gpu_error.c   | 106 +---
 drivers/gpu/drm/i915/i915_irq.c |   4 +-
 drivers/gpu/drm/i915/intel_engine_cs.c  | 104 +++
 drivers/gpu/drm/i915/intel_ringbuffer.h |   3 +
 6 files changed, 111 insertions(+), 111 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 20689f1cd719..f6762e00f872 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1339,7 +1339,7 @@ static int i915_hangcheck_info(struct seq_file *m, void 
*unused)
seqno[id] = intel_engine_get_seqno(engine);
}
 
-   i915_get_engine_instdone(dev_priv, RCS, );
+   intel_engine_get_instdone(_priv->engine[RCS], );
 
intel_runtime_pm_put(dev_priv);
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 54d860e1c0fc..4553a5372008 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3564,9 +3564,6 @@ void i915_error_state_get(struct drm_device *dev,
 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
 void i915_destroy_error_state(struct drm_device *dev);
 
-void i915_get_engine_instdone(struct drm_i915_private *dev_priv,
- enum intel_engine_id engine_id,
- struct intel_instdone *instdone);
 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
 
 /* i915_cmd_parser.c */
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
b/drivers/gpu/drm/i915/i915_gpu_error.c
index b5b58692ac5a..04205c82f0c9 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1038,7 +1038,7 @@ static void error_record_engine_registers(struct 
drm_i915_error_state *error,
ee->ipehr = I915_READ(IPEHR);
}
 
-   i915_get_engine_instdone(dev_priv, engine->id, >instdone);
+   intel_engine_get_instdone(engine, >instdone);
 
ee->waiting = intel_engine_has_waiter(engine);
ee->instpm = I915_READ(RING_INSTPM(engine->mmio_base));
@@ -1548,107 +1548,3 @@ void i915_destroy_error_state(struct drm_device *dev)
if (error)
kref_put(>ref, i915_error_state_free);
 }
-
-const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
-{
-   switch (type) {
-   case I915_CACHE_NONE: return " uncached";
-   case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped";
-   case I915_CACHE_L3_LLC: return " L3+LLC";
-   case I915_CACHE_WT: return " WT";
-   default: return "";
-   }
-}
-
-static inline uint32_t
-read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
- int subslice, i915_reg_t reg)
-{
-   uint32_t mcr;
-   uint32_t ret;
-   enum forcewake_domains fw_domains;
-
-   fw_domains = intel_uncore_forcewake_for_reg(dev_priv, reg,
-   FW_REG_READ);
-   fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
-GEN8_MCR_SELECTOR,
-FW_REG_READ | 
FW_REG_WRITE);
-
-   spin_lock_irq(_priv->uncore.lock);
-   intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
-
-   mcr = I915_READ_FW(GEN8_MCR_SELECTOR);
-   /*
-* The HW expects the slice and sublice selectors to be reset to 0
-* after reading out the registers.
-*/
-   WARN_ON_ONCE(mcr & (GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK));
-   mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
-   mcr |= GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
-   I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
-
-   ret = I915_READ_FW(reg);
-
-   mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
-   I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
-
-   intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
-   spin_unlock_irq(_priv->uncore.lock);
-
-   return ret;
-}
-
-/* NB: please notice the memset */
-void i915_get_engine_instdone(struct drm_i915_private *dev_priv,
- enum intel_engine_id engine_id,
- struct intel_instdone *instdone)
-{
-   u32 mmio_base = dev_priv->engine[engine_id].mmio_base;
-   int slice;
-   int subslice;
-
-   memset(instdone, 0, sizeof(*instdone));
-
-   switch (INTEL_GEN(dev_priv)) {
-   default:
-   instdone->instdone = I915_READ(RING_INSTDONE(mmio_base));
-
-   

[Intel-gfx] [CI 6/6] drm/i915: Compress GPU objects in error state

[Chris Wilson]

Our error states are quickly growing, pinning kernel memory with them.
The majority of the space is taken up by the error objects. These
compress well using zlib and without decode are mostly meaningless, so
encoding them does not hinder quickly parsing the error state for
familiarity.

v2: Make the zlib dependency optional

Signed-off-by: Chris Wilson 
Reviewed-by: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/Kconfig  |  12 +++
 drivers/gpu/drm/i915/i915_drv.h   |   3 +-
 drivers/gpu/drm/i915/i915_gpu_error.c | 176 ++
 3 files changed, 169 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index 3eff42e4a441..6aedc96aa412 100644
--- a/drivers/gpu/drm/i915/Kconfig
+++ b/drivers/gpu/drm/i915/Kconfig
@@ -60,6 +60,18 @@ config DRM_I915_CAPTURE_ERROR
 
  If in doubt, say "Y".
 
+config DRM_I915_COMPRESS_ERROR
+   bool "Compress GPU error state"
+   depends on DRM_I915_CAPTURE_ERROR
+   select ZLIB_DEFLATE
+   default y
+   help
+ This option selects ZLIB_DEFLATE if it isn't already
+ selected and causes any error state captured upon a GPU hang
+ to be compressed using zlib.
+
+ If in doubt, say "Y".
+
 config DRM_I915_USERPTR
bool "Always enable userptr support"
depends on DRM_I915
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4199e8aa436a..bf397b643cc0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -820,9 +820,10 @@ struct drm_i915_error_state {
struct intel_instdone instdone;
 
struct drm_i915_error_object {
-   int page_count;
u64 gtt_offset;
u64 gtt_size;
+   int page_count;
+   int unused;
u32 *pages[0];
} *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
 
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 22bd2187ea37..78cc13b9b2a5 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -29,6 +29,7 @@
 
 #include 
 #include 
+#include 
 #include "i915_drv.h"
 
 static const char *engine_str(int engine)
@@ -173,6 +174,110 @@ static void i915_error_puts(struct 
drm_i915_error_state_buf *e,
 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
 #define err_puts(e, s) i915_error_puts(e, s)
 
+#ifdef CONFIG_DRM_I915_COMPRESS_ERROR
+
+static bool compress_init(struct z_stream_s *zstream)
+{
+   memset(zstream, 0, sizeof(*zstream));
+
+   zstream->workspace =
+   kmalloc(zlib_deflate_workspacesize(MAX_WBITS, MAX_MEM_LEVEL),
+   GFP_ATOMIC | __GFP_NOWARN);
+   if (!zstream->workspace)
+   return false;
+
+   if (zlib_deflateInit(zstream, Z_DEFAULT_COMPRESSION) != Z_OK) {
+   kfree(zstream->workspace);
+   return false;
+   }
+
+   return true;
+}
+
+static int compress_page(struct z_stream_s *zstream,
+void *src,
+struct drm_i915_error_object *dst)
+{
+   zstream->next_in = src;
+   zstream->avail_in = PAGE_SIZE;
+
+   do {
+   if (zstream->avail_out == 0) {
+   unsigned long page;
+
+   page = __get_free_page(GFP_ATOMIC | __GFP_NOWARN);
+   if (!page)
+   return -ENOMEM;
+
+   dst->pages[dst->page_count++] = (void *)page;
+
+   zstream->next_out = (void *)page;
+   zstream->avail_out = PAGE_SIZE;
+   }
+
+   if (zlib_deflate(zstream, Z_SYNC_FLUSH) != Z_OK)
+   return -EIO;
+   } while (zstream->avail_in);
+
+   /* Fallback to uncompressed if we increase size? */
+   if (0 && zstream->total_out > zstream->total_in)
+   return -E2BIG;
+
+   return 0;
+}
+
+static void compress_fini(struct z_stream_s *zstream,
+ struct drm_i915_error_object *dst)
+{
+   if (dst) {
+   zlib_deflate(zstream, Z_FINISH);
+   dst->unused = zstream->avail_out;
+   }
+
+   zlib_deflateEnd(zstream);
+   kfree(zstream->workspace);
+}
+
+static void err_compression_marker(struct drm_i915_error_state_buf *m)
+{
+   err_puts(m, ":");
+}
+
+#else
+
+static bool compress_init(struct z_stream_s *zstream)
+{
+   return true;
+}
+
+static int compress_page(struct z_stream_s *zstream,
+void *src,
+struct drm_i915_error_object *dst)
+{
+   unsigned long page;
+
+   page = __get_free_page(GFP_ATOMIC | __GFP_NOWARN);
+   if (!page)
+   return 

[Intel-gfx] [CI 4/6] drm/i915: Always use the GTT for error capture

[Chris Wilson]

Since the GTT provides universal access to any GPU page, we can use it
to reduce our plethora of read methods to just one. It also has the
important characteristic of being exactly what the GPU sees - if there
are incoherency problems, seeing the batch as executed (rather than as
trapped inside the cpu cache) is important.

Signed-off-by: Chris Wilson 
Reviewed-by: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_gem_gtt.c   |  43 
 drivers/gpu/drm/i915/i915_gem_gtt.h   |   2 +
 drivers/gpu/drm/i915/i915_gpu_error.c | 120 --
 3 files changed, 74 insertions(+), 91 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 0bb4232f66bc..2d846aa39ca5 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2717,6 +2717,7 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
 */
struct i915_ggtt *ggtt = _priv->ggtt;
unsigned long hole_start, hole_end;
+   struct i915_hw_ppgtt *ppgtt;
struct drm_mm_node *entry;
int ret;
 
@@ -2724,6 +2725,15 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
if (ret)
return ret;
 
+   /* Reserve a mappable slot for our lockless error capture */
+   ret = drm_mm_insert_node_in_range_generic(>base.mm,
+ >error_capture,
+ 4096, 0, -1,
+ 0, ggtt->mappable_end,
+ 0, 0);
+   if (ret)
+   return ret;
+
/* Clear any non-preallocated blocks */
drm_mm_for_each_hole(entry, >base.mm, hole_start, hole_end) {
DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
@@ -2738,25 +2748,21 @@ int i915_gem_init_ggtt(struct drm_i915_private 
*dev_priv)
   true);
 
if (USES_PPGTT(dev_priv) && !USES_FULL_PPGTT(dev_priv)) {
-   struct i915_hw_ppgtt *ppgtt;
-
ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
-   if (!ppgtt)
-   return -ENOMEM;
+   if (!ppgtt) {
+   ret = -ENOMEM;
+   goto err;
+   }
 
ret = __hw_ppgtt_init(ppgtt, dev_priv);
-   if (ret) {
-   kfree(ppgtt);
-   return ret;
-   }
+   if (ret)
+   goto err_ppgtt;
 
-   if (ppgtt->base.allocate_va_range)
+   if (ppgtt->base.allocate_va_range) {
ret = ppgtt->base.allocate_va_range(>base, 0,
ppgtt->base.total);
-   if (ret) {
-   ppgtt->base.cleanup(>base);
-   kfree(ppgtt);
-   return ret;
+   if (ret)
+   goto err_ppgtt_cleanup;
}
 
ppgtt->base.clear_range(>base,
@@ -2770,6 +2776,14 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
}
 
return 0;
+
+err_ppgtt_cleanup:
+   ppgtt->base.cleanup(>base);
+err_ppgtt:
+   kfree(ppgtt);
+err:
+   drm_mm_remove_node(>error_capture);
+   return ret;
 }
 
 /**
@@ -2788,6 +2802,9 @@ void i915_ggtt_cleanup_hw(struct drm_i915_private 
*dev_priv)
 
i915_gem_cleanup_stolen(_priv->drm);
 
+   if (drm_mm_node_allocated(>error_capture))
+   drm_mm_remove_node(>error_capture);
+
if (drm_mm_initialized(>base.mm)) {
intel_vgt_deballoon(dev_priv);
 
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h 
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index ec78be2f8c77..bd93fb8f99d2 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -450,6 +450,8 @@ struct i915_ggtt {
bool do_idle_maps;
 
int mtrr;
+
+   struct drm_mm_node error_capture;
 };
 
 struct i915_hw_ppgtt {
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 159d6d7e0cee..b3b2e6c1c6c6 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -656,7 +656,7 @@ static void i915_error_object_free(struct 
drm_i915_error_object *obj)
return;
 
for (page = 0; page < obj->page_count; page++)
-   kfree(obj->pages[page]);
+   free_page((unsigned long)obj->pages[page]);
 
kfree(obj);
 }
@@ -693,98 +693,69 @@ static void i915_error_state_free(struct kref *error_ref)
kfree(error);
 }
 
+static int compress_page(void *src, struct drm_i915_error_object *dst)
+{
+   unsigned long page;
+
+   page = __get_free_page(GFP_ATOMIC | __GFP_NOWARN);
+ 

[Intel-gfx] [CI 3/6] drm/i915: Stop the machine whilst capturing the GPU crash dump

[Chris Wilson]

The error state is purposefully racy as we expect it to be called at any
time and so have avoided any locking whilst capturing the crash dump.
However, with multi-engine GPUs and multiple CPUs, those races can
manifest into OOPSes as we attempt to chase dangling pointers freed on
other CPUs. Under discussion are lots of ways to slow down normal
operation in order to protect the post-mortem error capture, but what it
we take the opposite approach and freeze the machine whilst the error
capture runs (note the GPU may still running, but as long as we don't
process any of the results the driver's bookkeeping will be static).

Note that by of itself, this is not a complete fix. It also depends on
the compiler barriers in list_add/list_del to prevent traversing the
lists into the void. We also depend that we only require state from
carefully controlled sources - i.e. all the state we require for
post-mortem debugging should be reachable from the request itself so
that we only have to worry about retrieving the request carefully. Once
we have the request, we know that all pointers from it are intact.

v2: Avoid drm_clflush_pages() inside stop_machine() as it may use
stop_machine() itself for its wbinvd fallback.

Signed-off-by: Chris Wilson 
Acked-by: Daniel Vetter 
---
 drivers/gpu/drm/i915/Kconfig  |  1 +
 drivers/gpu/drm/i915/i915_drv.h   |  2 ++
 drivers/gpu/drm/i915/i915_gpu_error.c | 46 +--
 3 files changed, 31 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index 8844b99bd760..3eff42e4a441 100644
--- a/drivers/gpu/drm/i915/Kconfig
+++ b/drivers/gpu/drm/i915/Kconfig
@@ -4,6 +4,7 @@ config DRM_I915
depends on X86 && PCI
select INTEL_GTT
select INTERVAL_TREE
+   select STOP_MACHINE
# we need shmfs for the swappable backing store, and in particular
# the shmem_readpage() which depends upon tmpfs
select SHMEM
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 380590b30bbf..4199e8aa436a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -746,6 +746,8 @@ struct drm_i915_error_state {
struct kref ref;
struct timeval time;
 
+   struct drm_i915_private *i915;
+
char error_msg[128];
bool simulated;
int iommu;
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
b/drivers/gpu/drm/i915/i915_gpu_error.c
index c88c0d192a60..159d6d7e0cee 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -28,6 +28,7 @@
  */
 
 #include 
+#include 
 #include "i915_drv.h"
 
 static const char *engine_str(int engine)
@@ -744,14 +745,12 @@ i915_error_object_create(struct drm_i915_private 
*dev_priv,
 
dst->page_count = num_pages;
while (num_pages--) {
-   unsigned long flags;
void *d;
 
d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
if (d == NULL)
goto unwind;
 
-   local_irq_save(flags);
if (use_ggtt) {
void __iomem *s;
 
@@ -770,15 +769,10 @@ i915_error_object_create(struct drm_i915_private 
*dev_priv,
 
page = i915_gem_object_get_page(src, i);
 
-   drm_clflush_pages(, 1);
-
s = kmap_atomic(page);
memcpy(d, s, PAGE_SIZE);
kunmap_atomic(s);
-
-   drm_clflush_pages(, 1);
}
-   local_irq_restore(flags);
 
dst->pages[i++] = d;
reloc_offset += PAGE_SIZE;
@@ -1447,6 +1441,31 @@ static void i915_capture_gen_state(struct 
drm_i915_private *dev_priv,
   sizeof(error->device_info));
 }
 
+static int capture(void *data)
+{
+   struct drm_i915_error_state *error = data;
+
+   /* Ensure that what we readback from memory matches what the GPU sees */
+   wbinvd();
+
+   i915_capture_gen_state(error->i915, error);
+   i915_capture_reg_state(error->i915, error);
+   i915_gem_record_fences(error->i915, error);
+   i915_gem_record_rings(error->i915, error);
+   i915_capture_active_buffers(error->i915, error);
+   i915_capture_pinned_buffers(error->i915, error);
+
+   do_gettimeofday(>time);
+
+   error->overlay = intel_overlay_capture_error_state(error->i915);
+   error->display = intel_display_capture_error_state(error->i915);
+
+   /* And make sure we don't leave trash in the CPU cache */
+   wbinvd();
+
+   return 0;
+}
+
 /**
  * i915_capture_error_state - capture an error record for later analysis
  * @dev: drm device
@@ -1478,18 +1497,9 @@ void i915_capture_error_state(struct drm_i915_private 
*dev_priv,
}
 
kref_init(>ref);
+   error->i915 = dev_priv;
 
-   

[Intel-gfx] [CI 5/6] drm/i915: Consolidate error object printing

[Chris Wilson]

Leave all the pretty printing to userspace and simplify the error
capture to only have a single common object printer. It makes the kernel
code more compact, and the refactoring allows us to apply more complex
transformations like compressing the output.

Signed-off-by: Chris Wilson 
Reviewed-by: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_gpu_error.c | 100 +-
 1 file changed, 25 insertions(+), 75 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
b/drivers/gpu/drm/i915/i915_gpu_error.c
index b3b2e6c1c6c6..22bd2187ea37 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -341,10 +341,22 @@ void i915_error_printf(struct drm_i915_error_state_buf 
*e, const char *f, ...)
 }
 
 static void print_error_obj(struct drm_i915_error_state_buf *m,
+   struct intel_engine_cs *engine,
+   const char *name,
struct drm_i915_error_object *obj)
 {
int page, offset, elt;
 
+   if (!obj)
+   return;
+
+   if (name) {
+   err_printf(m, "%s --- %s = 0x%08x %08x\n",
+  engine ? engine->name : "global", name,
+  upper_32_bits(obj->gtt_offset),
+  lower_32_bits(obj->gtt_offset));
+   }
+
for (page = offset = 0; page < obj->page_count; page++) {
for (elt = 0; elt < PAGE_SIZE/4; elt++) {
err_printf(m, "%08x :  %08x\n", offset,
@@ -370,8 +382,8 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf 
*m,
struct pci_dev *pdev = dev_priv->drm.pdev;
struct drm_i915_error_state *error = error_priv->error;
struct drm_i915_error_object *obj;
-   int i, j, offset, elt;
int max_hangcheck_score;
+   int i, j;
 
if (!error) {
err_printf(m, "no error state collected\n");
@@ -491,15 +503,7 @@ int i915_error_state_to_str(struct 
drm_i915_error_state_buf *m,
err_printf(m, " --- gtt_offset = 0x%08x %08x\n",
   upper_32_bits(obj->gtt_offset),
   lower_32_bits(obj->gtt_offset));
-   print_error_obj(m, obj);
-   }
-
-   obj = ee->wa_batchbuffer;
-   if (obj) {
-   err_printf(m, "%s (w/a) --- gtt_offset = 0x%08x\n",
-  dev_priv->engine[i].name,
-  lower_32_bits(obj->gtt_offset));
-   print_error_obj(m, obj);
+   print_error_obj(m, _priv->engine[i], NULL, obj);
}
 
if (ee->num_requests) {
@@ -531,77 +535,23 @@ int i915_error_state_to_str(struct 
drm_i915_error_state_buf *m,
}
}
 
-   if ((obj = ee->ringbuffer)) {
-   err_printf(m, "%s --- ringbuffer = 0x%08x\n",
-  dev_priv->engine[i].name,
-  lower_32_bits(obj->gtt_offset));
-   print_error_obj(m, obj);
-   }
+   print_error_obj(m, _priv->engine[i],
+   "ringbuffer", ee->ringbuffer);
 
-   if ((obj = ee->hws_page)) {
-   u64 hws_offset = obj->gtt_offset;
-   u32 *hws_page = >pages[0][0];
+   print_error_obj(m, _priv->engine[i],
+   "HW Status", ee->hws_page);
 
-   if (i915.enable_execlists) {
-   hws_offset += LRC_PPHWSP_PN * PAGE_SIZE;
-   hws_page = >pages[LRC_PPHWSP_PN][0];
-   }
-   err_printf(m, "%s --- HW Status = 0x%08llx\n",
-  dev_priv->engine[i].name, hws_offset);
-   offset = 0;
-   for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
-   err_printf(m, "[%04x] %08x %08x %08x %08x\n",
-  offset,
-  hws_page[elt],
-  hws_page[elt+1],
-  hws_page[elt+2],
-  hws_page[elt+3]);
-   offset += 16;
-   }
-   }
+   print_error_obj(m, _priv->engine[i],
+   "HW context", ee->ctx);
 
-   obj = ee->wa_ctx;
-   if (obj) {
-   u64 wa_ctx_offset = obj->gtt_offset;
-   u32 *wa_ctx_page = >pages[0][0];
-   struct intel_engine_cs *engine = _priv->engine[RCS];
-  

[Intel-gfx] [CI 2/6] drm/i915: Allow disabling error capture

[Chris Wilson]

We currently capture the GPU state after we detect a hang. This is vital
for us to both triage and debug hangs in the wild (post-mortem
debugging). However, it comes at the cost of running some potentially
dangerous code (since it has to make very few assumption about the state
of the driver) that is quite resource intensive.

This patch introduces both a method to disable error capture at runtime
(for users who hit bugs at runtime and need a workaround) and to disable
error capture at compiletime (for realtime users who want to minimise
any possible latency, and never require error capture, saving ~30k of
code). The cost is that we now have to be wary of (and test!) a kconfig
flag and a module parameter. The effect of the module parameter is easy
to verify through code inspection and runtime testing, but a kconfig flag
needs regular compile checking.

Signed-off-by: Chris Wilson 
Reviewed-by: Joonas Lahtinen 
Acked-by: Jani Nikula 
Acked-by: Daniel Vetter 

Re: [Intel-gfx] [PATCH 03/19] drm/i915: Make HAS_GMCH_DISPLAY only take dev_priv

[David Weinehall]

On Wed, Oct 12, 2016 at 09:43:02AM +0100, Tvrtko Ursulin wrote:
> 
> On 12/10/2016 09:17, David Weinehall wrote:
> > On Tue, Oct 11, 2016 at 02:21:36PM +0100, Tvrtko Ursulin wrote:
> > > From: Tvrtko Ursulin
> > > 
> > > More .rodata string saving by avoid __I915__ magic inside WARNs.
> > > 
> > > v2: Add parantheses around dev_priv. (Ville Syrjala)
> > > 
> > > Signed-off-by: Tvrtko Ursulin
> > Reviewed-by: David Weinehall
> > 
> > Note that once this patch series goes in (or before),
> > we should have a patch that turns intel_hdmi_to_dev() into
> > intel_hdmi_to_dev_priv().  If you look at the code in
> > intel_hdmi.c, almost every (after the dev -> dev_priv transition
> > I think it's every) instance where it's used converts
> > dev immediately further to dev_priv.
> 
> Agreed, but best left for later I think. And there is more of those
> opportunities throughout the code which I spotted while doing this.
> 
> Regards,
> 
> Tvrtko
> 
> P.S. For some reason reply to all from thunderbird keeps dropping you from
> the recipients. I might forget to manually add you.

That's because my e-mail client sets the Mail-Followup-To header;
I'm subscribed to the list -- I don't need duplicate copies addressed
directly to me.


Regards, David
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[Intel-gfx] drm/i915: WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock)

[Paul Bolle]

On a laptop that tracks the latest stable release (Ie, it now runs
v4.8.1) I see this WARNING
    WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock)

Full trace pasted below. I never saw this WARNING before v4.8. Since
v4.8 I've had it in all (four, actually) boots.

What am I expected to do about this WARNING?

Thanks,


Paul Bolle

WARNING: CPU: 3 PID: 1368 at drivers/gpu/drm/i915/intel_display.c:14178 
skl_max_scale.part.120+0x75/0x80 [i915]
WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock)
Modules linked in:
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ip6t_REJECT nf_reject_ipv6 xt_conntrack ip_set nfnetlink ebtable_nat 
ebtable_broute bridge stp llc ip6table_nat nf_conntrack_ipv6 cmac 
nf_defrag_ipv6 nf_nat_ipv6 ip6table_mangle ip6table_raw ip6table_security 
iptable_nat nf_conntrack_ipv4 nf_defrag_ipv4 nf_nat_ipv4 nf_nat nf_conntrack 
iptable_mangle iptable_raw iptable_security ebtable_filter ebtables 
ip6table_filter ip6_tables bnep vfat fat arc4 snd_hda_codec_hdmi snd_soc_skl 
dell_led snd_soc_skl_ipc snd_soc_sst_ipc snd_soc_sst_dsp snd_hda_ext_core 
snd_soc_sst_match snd_soc_core intel_rapl snd_hda_codec_realtek 
snd_hda_codec_generic x86_pkg_temp_thermal coretemp kvm_intel snd_compress 
snd_pcm_dmaengine ac97_bus kvm snd_hda_intel iwlmvm snd_hda_codec mac80211 
iTCO_wdt
 iTCO_vendor_support uvcvideo snd_hda_core snd_hwdep snd_seq irqbypass 
dell_laptop i2c_designware_platform i2c_designware_core dell_wmi 
crct10dif_pclmul dell_smbios dcdbas crc32_pclmul snd_seq_device iwlwifi 
videobuf2_vmalloc videobuf2_memops ghash_clmulni_intel snd_pcm videobuf2_v4l2 
videobuf2_core cfg80211 videodev media joydev pcspkr mei_me rtsx_pci_ms 
memstick snd_timer i2c_i801 i2c_smbus mei snd btusb soundcore shpchp hci_uart 
btrtl btbcm btqca idma64 btintel bluetooth intel_pch_thermal 
processor_thermal_device intel_lpss_pci intel_soc_dts_iosf wmi 
pinctrl_sunrisepoint intel_lpss_acpi rfkill pinctrl_intel intel_lpss 
int3400_thermal acpi_als int3403_thermal int340x_thermal_zone kfifo_buf 
acpi_thermal_rel intel_hid industrialio sparse_keymap acpi_pad tpm_tis 
tpm_tis_core tpm nfsd auth_rpcgss
 nfs_acl lockd grace sunrpc hid_multitouch i915 rtsx_pci_sdmmc mmc_core 
i2c_algo_bit drm_kms_helper crc32c_intel drm serio_raw nvme rtsx_pci nvme_core 
i2c_hid video fjes
CPU: 3 PID: 1368 Comm: Xorg Not tainted 4.8.1-1.local1.fc24.x86_64 #1
Hardware name: Dell Inc. XPS 13 9350/09JHRY, BIOS 1.4.4 06/14/2016
 0286 df2f374c a31528d53910 b83e5cfd
 a31528d53960  a31528d53950 b80a7d5b
 3762c72b3010 a3151e4d8cc0 a31526c23800 a31526e6
Call Trace:
 [] dump_stack+0x63/0x86
 [] __warn+0xcb/0xf0
 [] warn_slowpath_fmt+0x5f/0x80
 [] ? sort+0x147/0x220
 [] ? drm_atomic_helper_normalize_zpos+0x264/0x300 
[drm_kms_helper]
 [] skl_max_scale.part.120+0x75/0x80 [i915]
 [] intel_check_primary_plane+0xc6/0xe0 [i915]
 [] ? drm_atomic_helper_normalize_zpos+0x264/0x300 
[drm_kms_helper]
 [] intel_plane_atomic_check+0x132/0x1f0 [i915]
 [] drm_atomic_helper_check_planes+0x84/0x200 [drm_kms_helper]
 [] intel_atomic_check+0x9a7/0x11a0 [i915]
 [] ? __kmalloc_track_caller+0x17a/0x210
 [] drm_atomic_check_only+0x187/0x610 [drm]
 [] ? drm_atomic_get_crtc_state+0x88/0x100 [drm]
 [] drm_atomic_commit+0x17/0x60 [drm]
 [] drm_atomic_helper_update_plane+0xec/0x130 [drm_kms_helper]
 [] __setplane_internal+0x22b/0x270 [drm]
 [] drm_mode_cursor_universal+0x139/0x240 [drm]
 [] drm_mode_cursor_common+0x7e/0x180 [drm]
 [] drm_mode_cursor2_ioctl+0xe/0x10 [drm]
 [] drm_ioctl+0x1da/0x4b0 [drm]
 [] ? drm_mode_cursor_ioctl+0x70/0x70 [drm]
 [] ? enqueue_hrtimer+0x3d/0x80
 [] do_vfs_ioctl+0xa3/0x5e0
 [] ? __sys_recvmsg+0x51/0x90
 [] SyS_ioctl+0x79/0x90
 [] entry_SYSCALL_64_fastpath+0x1a/0xa4
___
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Re: [Intel-gfx] [PATCH 01/19] drm/i915: Make HAS_DDI and HAS_PCH_LPT_LP only take dev_priv

[David Weinehall]

On Tue, Oct 11, 2016 at 02:21:34PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin 
> 
> This saves 3248 bytes of .rodata strings.
> 
> v2: Add parantheses around dev_priv. (Ville Syrjala)

Reviewed-by: David Weinehall 

How come you didn't do HAS_PCH_LPT_{LP,H} together with
the rest of the PCH-macros, BTW?

> 
> Signed-off-by: Tvrtko Ursulin 
> ---
>  drivers/gpu/drm/i915/i915_drv.h   |  8 +++---
>  drivers/gpu/drm/i915/intel_crt.c  | 10 +++
>  drivers/gpu/drm/i915/intel_display.c  | 49 
> ++-
>  drivers/gpu/drm/i915/intel_dp.c   | 16 ++--
>  drivers/gpu/drm/i915/intel_dpll_mgr.c |  4 +--
>  drivers/gpu/drm/i915/intel_hdmi.c | 10 +++
>  drivers/gpu/drm/i915/intel_pm.c   |  4 +--
>  drivers/gpu/drm/i915/intel_psr.c  |  8 +++---
>  8 files changed, 56 insertions(+), 53 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 54d860e1c0fc..51dd10f25f59 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2815,7 +2815,7 @@ struct drm_i915_cmd_table {
>  
>  #define HAS_DP_MST(dev)  (INTEL_INFO(dev)->has_dp_mst)
>  
> -#define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
> +#define HAS_DDI(dev_priv)((dev_priv)->info.has_ddi)
>  #define HAS_FPGA_DBG_UNCLAIMED(dev)  (INTEL_INFO(dev)->has_fpga_dbg)
>  #define HAS_PSR(dev) (INTEL_INFO(dev)->has_psr)
>  #define HAS_RUNTIME_PM(dev)  (INTEL_INFO(dev)->has_runtime_pm)
> @@ -2854,8 +2854,10 @@ struct drm_i915_cmd_table {
>  #define HAS_PCH_KBP(dev) (INTEL_PCH_TYPE(dev) == PCH_KBP)
>  #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
>  #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
> -#define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == 
> INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
> -#define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == 
> INTEL_PCH_LPT_DEVICE_ID_TYPE)
> +#define HAS_PCH_LPT_LP(dev_priv) \
> + ((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
> +#define HAS_PCH_LPT_H(dev_priv) \
> + ((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
>  #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
>  #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
>  #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
> diff --git a/drivers/gpu/drm/i915/intel_crt.c 
> b/drivers/gpu/drm/i915/intel_crt.c
> index 4a7b6c595ec2..d4b9b166de5d 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -280,13 +280,13 @@ static bool intel_crt_compute_config(struct 
> intel_encoder *encoder,
>struct intel_crtc_state *pipe_config,
>struct drm_connector_state *conn_state)
>  {
> - struct drm_device *dev = encoder->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  
> - if (HAS_PCH_SPLIT(dev))
> + if (HAS_PCH_SPLIT(dev_priv))
>   pipe_config->has_pch_encoder = true;
>  
>   /* LPT FDI RX only supports 8bpc. */
> - if (HAS_PCH_LPT(dev)) {
> + if (HAS_PCH_LPT(dev_priv)) {
>   if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) {
>   DRM_DEBUG_KMS("LPT only supports 24bpp\n");
>   return false;
> @@ -296,7 +296,7 @@ static bool intel_crt_compute_config(struct intel_encoder 
> *encoder,
>   }
>  
>   /* FDI must always be 2.7 GHz */
> - if (HAS_DDI(dev))
> + if (HAS_DDI(dev_priv))
>   pipe_config->port_clock = 135000 * 2;
>  
>   return true;
> @@ -917,7 +917,7 @@ void intel_crt_init(struct drm_device *dev)
>   if (I915_HAS_HOTPLUG(dev) &&
>   !dmi_check_system(intel_spurious_crt_detect))
>   crt->base.hpd_pin = HPD_CRT;
> - if (HAS_DDI(dev)) {
> + if (HAS_DDI(dev_priv)) {
>   crt->base.port = PORT_E;
>   crt->base.get_config = hsw_crt_get_config;
>   crt->base.get_hw_state = intel_ddi_get_hw_state;
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index 23a6c7213eca..6e447b575413 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1187,19 +1187,17 @@ void assert_fdi_rx_pll(struct drm_i915_private 
> *dev_priv,
>   onoff(state), onoff(cur_state));
>  }
>  
> -void assert_panel_unlocked(struct drm_i915_private *dev_priv,
> -enum pipe pipe)
> +void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
>  {
> - struct drm_device *dev = _priv->drm;
>   i915_reg_t pp_reg;
>   u32 val;
>   enum pipe panel_pipe = PIPE_A;
>   bool locked = true;
>  
> - if (WARN_ON(HAS_DDI(dev)))
> + if (WARN_ON(HAS_DDI(dev_priv)))
>   return;
>  
> - if (HAS_PCH_SPLIT(dev)) 

Re: [Intel-gfx] [PATCH 08/19] drm/i915: Make IS_IVYBRIDGE only take dev_priv

[David Weinehall]

On Tue, Oct 11, 2016 at 02:21:41PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin 
> 
> Saves 848 bytes of .rodata strings.
> 
> v2: Add parantheses around dev_priv. (Ville Syrjala)
> 
> Signed-off-by: Tvrtko Ursulin 

Reviewed-by: David Weinehall 

> ---
>  drivers/gpu/drm/i915/i915_drv.c | 19 +++
>  drivers/gpu/drm/i915/i915_drv.h |  2 +-
>  drivers/gpu/drm/i915/i915_gem.c |  2 +-
>  drivers/gpu/drm/i915/i915_gem_context.c |  2 +-
>  drivers/gpu/drm/i915/intel_display.c| 12 ++--
>  drivers/gpu/drm/i915/intel_pm.c | 13 +++--
>  drivers/gpu/drm/i915/intel_sprite.c |  2 +-
>  7 files changed, 28 insertions(+), 24 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index bfdbbb745939..f6ba8f262238 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -114,7 +114,7 @@ static bool i915_error_injected(struct drm_i915_private 
> *dev_priv)
> fmt, ##__VA_ARGS__)
>  
>  
> -static enum intel_pch intel_virt_detect_pch(struct drm_device *dev)
> +static enum intel_pch intel_virt_detect_pch(struct drm_i915_private 
> *dev_priv)
>  {
>   enum intel_pch ret = PCH_NOP;
>  
> @@ -125,16 +125,16 @@ static enum intel_pch intel_virt_detect_pch(struct 
> drm_device *dev)
>* make an educated guess as to which PCH is really there.
>*/
>  
> - if (IS_GEN5(dev)) {
> + if (IS_GEN5(dev_priv)) {
>   ret = PCH_IBX;
>   DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
> - } else if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
> + } else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
>   ret = PCH_CPT;
>   DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
> - } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
> + } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
>   ret = PCH_LPT;
>   DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
> - } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
> + } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
>   ret = PCH_SPT;
>   DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
>   }
> @@ -178,12 +178,14 @@ static void intel_detect_pch(struct drm_device *dev)
>   } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
>   dev_priv->pch_type = PCH_CPT;
>   DRM_DEBUG_KMS("Found CougarPoint PCH\n");
> - WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
> + WARN_ON(!(IS_GEN6(dev_priv) ||
> + IS_IVYBRIDGE(dev_priv)));
>   } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
>   /* PantherPoint is CPT compatible */
>   dev_priv->pch_type = PCH_CPT;
>   DRM_DEBUG_KMS("Found PantherPoint PCH\n");
> - WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
> + WARN_ON(!(IS_GEN6(dev_priv) ||
> + IS_IVYBRIDGE(dev_priv)));
>   } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
>   dev_priv->pch_type = PCH_LPT;
>   DRM_DEBUG_KMS("Found LynxPoint PCH\n");
> @@ -217,7 +219,8 @@ static void intel_detect_pch(struct drm_device *dev)
>   PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
>   pch->subsystem_device ==
>   PCI_SUBDEVICE_ID_QEMU)) {
> - dev_priv->pch_type = intel_virt_detect_pch(dev);
> + dev_priv->pch_type =
> + intel_virt_detect_pch(dev_priv);
>   } else
>   continue;
>  
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 7a40dfa830e7..3f321932d18a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2655,7 +2655,7 @@ struct drm_i915_cmd_table {
>  #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
>  #define IS_G33(dev)  (INTEL_INFO(dev)->is_g33)
>  #define IS_IRONLAKE_M(dev_priv)  (INTEL_DEVID(dev_priv) == 0x0046)
> -#define IS_IVYBRIDGE(dev)(INTEL_INFO(dev)->is_ivybridge)
> +#define IS_IVYBRIDGE(dev_priv)   ((dev_priv)->info.is_ivybridge)
>  #define IS_IVB_GT1(dev_priv) (INTEL_DEVID(dev_priv) == 0x0156 || \
>INTEL_DEVID(dev_priv) == 0x0152 || \
>INTEL_DEVID(dev_priv) == 0x015a)
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 

Re: [Intel-gfx] drm/i915: WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock)

[Joonas Lahtinen]

On ke, 2016-10-12 at 11:56 +0200, Paul Bolle wrote:
> On a laptop that tracks the latest stable release (Ie, it now runs
> v4.8.1) I see this WARNING
>     WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock)
> 
> Full trace pasted below. I never saw this WARNING before v4.8. Since
> v4.8 I've had it in all (four, actually) boots.
> 
> What am I expected to do about this WARNING?
> 

Bisecting the offending commit between v4.8 and v4.8.1 would be a good
start.

Regards, Joonas
-- 
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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Re: [Intel-gfx] [PATCH 17/19] drm/i915: Make IS_VALLEYVIEW only take dev_priv

[David Weinehall]

On Tue, Oct 11, 2016 at 02:21:50PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin 
> 
> Saves 944 bytes of .rodata strings and 128 bytes of .text.
> 
> v2: Add parantheses around dev_priv. (Ville Syrjala)
> 
> Signed-off-by: Tvrtko Ursulin 

Reviewed-by: David Weinehall 

> ---
>  drivers/gpu/drm/i915/i915_drv.h | 2 +-
>  drivers/gpu/drm/i915/i915_gem_fence.c   | 2 +-
>  drivers/gpu/drm/i915/i915_gpu_error.c   | 4 ++--
>  drivers/gpu/drm/i915/intel_crt.c| 6 +++---
>  drivers/gpu/drm/i915/intel_display.c| 6 +++---
>  drivers/gpu/drm/i915/intel_dp.c | 8 
>  drivers/gpu/drm/i915/intel_hdmi.c   | 2 +-
>  drivers/gpu/drm/i915/intel_pm.c | 2 +-
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +--
>  9 files changed, 17 insertions(+), 18 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 96846ecfc224..f9f9a218d5fe 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2659,7 +2659,7 @@ struct drm_i915_cmd_table {
>  #define IS_IVB_GT1(dev_priv) (INTEL_DEVID(dev_priv) == 0x0156 || \
>INTEL_DEVID(dev_priv) == 0x0152 || \
>INTEL_DEVID(dev_priv) == 0x015a)
> -#define IS_VALLEYVIEW(dev)   (INTEL_INFO(dev)->is_valleyview)
> +#define IS_VALLEYVIEW(dev_priv)  ((dev_priv)->info.is_valleyview)
>  #define IS_CHERRYVIEW(dev_priv)  ((dev_priv)->info.is_cherryview)
>  #define IS_HASWELL(dev_priv) ((dev_priv)->info.is_haswell)
>  #define IS_BROADWELL(dev_priv)   ((dev_priv)->info.is_broadwell)
> diff --git a/drivers/gpu/drm/i915/i915_gem_fence.c 
> b/drivers/gpu/drm/i915/i915_gem_fence.c
> index 8df1fa7234e8..d26768567252 100644
> --- a/drivers/gpu/drm/i915/i915_gem_fence.c
> +++ b/drivers/gpu/drm/i915/i915_gem_fence.c
> @@ -448,7 +448,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
>   uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
>   uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
>  
> - if (INTEL_INFO(dev)->gen >= 8 || IS_VALLEYVIEW(dev)) {
> + if (INTEL_GEN(dev_priv) >= 8 || IS_VALLEYVIEW(dev_priv)) {
>   /*
>* On BDW+, swizzling is not used. We leave the CPU memory
>* controller in charge of optimizing memory accesses without
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
> b/drivers/gpu/drm/i915/i915_gpu_error.c
> index d41517e11978..6eb11fd326fd 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -1349,7 +1349,7 @@ static void i915_capture_reg_state(struct 
> drm_i915_private *dev_priv,
>*/
>  
>   /* 1: Registers specific to a single generation */
> - if (IS_VALLEYVIEW(dev)) {
> + if (IS_VALLEYVIEW(dev_priv)) {
>   error->gtier[0] = I915_READ(GTIER);
>   error->ier = I915_READ(VLV_IER);
>   error->forcewake = I915_READ_FW(FORCEWAKE_VLV);
> @@ -1398,7 +1398,7 @@ static void i915_capture_reg_state(struct 
> drm_i915_private *dev_priv,
>   error->gtier[0] = I915_READ(GTIER);
>   } else if (IS_GEN2(dev)) {
>   error->ier = I915_READ16(IER);
> - } else if (!IS_VALLEYVIEW(dev)) {
> + } else if (!IS_VALLEYVIEW(dev_priv)) {
>   error->ier = I915_READ(IER);
>   }
>   error->eir = I915_READ(EIR);
> diff --git a/drivers/gpu/drm/i915/intel_crt.c 
> b/drivers/gpu/drm/i915/intel_crt.c
> index d456786f5813..d92c3edf10ff 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -253,7 +253,7 @@ intel_crt_mode_valid(struct drm_connector *connector,
>  
>   if (HAS_PCH_LPT(dev_priv))
>   max_clock = 18;
> - else if (IS_VALLEYVIEW(dev))
> + else if (IS_VALLEYVIEW(dev_priv))
>   /*
>* 270 MHz due to current DPLL limits,
>* DAC limit supposedly 355 MHz.
> @@ -423,7 +423,7 @@ static bool intel_crt_detect_hotplug(struct drm_connector 
> *connector)
>   if (HAS_PCH_SPLIT(dev_priv))
>   return intel_ironlake_crt_detect_hotplug(connector);
>  
> - if (IS_VALLEYVIEW(dev))
> + if (IS_VALLEYVIEW(dev_priv))
>   return valleyview_crt_detect_hotplug(connector);
>  
>   /*
> @@ -850,7 +850,7 @@ void intel_crt_init(struct drm_device *dev)
>  
>   if (HAS_PCH_SPLIT(dev_priv))
>   adpa_reg = PCH_ADPA;
> - else if (IS_VALLEYVIEW(dev))
> + else if (IS_VALLEYVIEW(dev_priv))
>   adpa_reg = VLV_ADPA;
>   else
>   adpa_reg = ADPA;
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index d61a12dbbd72..c3fb9f700c7a 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5876,7 +5876,7 @@ static void intel_update_max_cdclk(struct 

Re: [Intel-gfx] [PATCH] drm/i915: Remove unused BSM_MASK causing warning

[Chris Wilson]

On Wed, Oct 12, 2016 at 10:18:54AM +0300, Joonas Lahtinen wrote:
> Remove never used BSM{,_MASK}. BSM_MASK #define also causes a warning.
> 
> include/drm/i915_drm.h:96:34: warning: result of ‘65535 << 20’
> requires 37 bits to represent, but ‘int’ only has 32 bits
> [-Wshiftoverflow=]
>#define   INTEL_BSM_MASK (0x << 20)
> 
> Reported-by: Linus Torvalds 
> Signed-off-by: Joonas Lahtinen 
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index acc767a..3105872 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -86,8 +86,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>  #define DEVEN 0x54
>  #define   DEVEN_MCHBAR_EN (1 << 28)
>  
> -#define BSM 0x5c
> -#define   BSM_MASK (0x << 20)
> +/* BSM in include/drm/i915_drm.h */

greps ok.
Reviewed-by: Chris Wilson 
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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Re: [Intel-gfx] [PATCH 03/19] drm/i915: Make HAS_GMCH_DISPLAY only take dev_priv

[David Weinehall]

On Tue, Oct 11, 2016 at 02:21:36PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin 
> 
> More .rodata string saving by avoid __I915__ magic inside WARNs.
> 
> v2: Add parantheses around dev_priv. (Ville Syrjala)
> 
> Signed-off-by: Tvrtko Ursulin 

Reviewed-by: David Weinehall 

Note that once this patch series goes in (or before),
we should have a patch that turns intel_hdmi_to_dev() into
intel_hdmi_to_dev_priv().  If you look at the code in
intel_hdmi.c, almost every (after the dev -> dev_priv transition
I think it's every) instance where it's used converts
dev immediately further to dev_priv.

> ---
>  drivers/gpu/drm/i915/i915_drv.h| 2 +-
>  drivers/gpu/drm/i915/intel_color.c | 6 +++---
>  drivers/gpu/drm/i915/intel_display.c   | 8 
>  drivers/gpu/drm/i915/intel_dp.c| 2 +-
>  drivers/gpu/drm/i915/intel_dsi.c   | 2 +-
>  drivers/gpu/drm/i915/intel_fifo_underrun.c | 2 +-
>  drivers/gpu/drm/i915/intel_hdmi.c  | 5 +++--
>  7 files changed, 14 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 3caa1c767512..1a4698e665be 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2863,7 +2863,7 @@ struct drm_i915_cmd_table {
>  #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
>  #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
>  
> -#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->has_gmch_display)
> +#define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
>  
>  /* DPF == dynamic parity feature */
>  #define HAS_L3_DPF(dev) (INTEL_INFO(dev)->has_l3_dpf)
> diff --git a/drivers/gpu/drm/i915/intel_color.c 
> b/drivers/gpu/drm/i915/intel_color.c
> index 95a72771eea6..5362c07932d3 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -273,7 +273,7 @@ static void i9xx_load_luts_internal(struct drm_crtc *crtc,
>   enum pipe pipe = intel_crtc->pipe;
>   int i;
>  
> - if (HAS_GMCH_DISPLAY(dev)) {
> + if (HAS_GMCH_DISPLAY(dev_priv)) {
>   if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
>   assert_dsi_pll_enabled(dev_priv);
>   else
> @@ -288,7 +288,7 @@ static void i9xx_load_luts_internal(struct drm_crtc *crtc,
>   (drm_color_lut_extract(lut[i].green, 8) << 8) |
>   drm_color_lut_extract(lut[i].blue, 8);
>  
> - if (HAS_GMCH_DISPLAY(dev))
> + if (HAS_GMCH_DISPLAY(dev_priv))
>   I915_WRITE(PALETTE(pipe, i), word);
>   else
>   I915_WRITE(LGC_PALETTE(pipe, i), word);
> @@ -297,7 +297,7 @@ static void i9xx_load_luts_internal(struct drm_crtc *crtc,
>   for (i = 0; i < 256; i++) {
>   uint32_t word = (i << 16) | (i << 8) | i;
>  
> - if (HAS_GMCH_DISPLAY(dev))
> + if (HAS_GMCH_DISPLAY(dev_priv))
>   I915_WRITE(PALETTE(pipe, i), word);
>   else
>   I915_WRITE(LGC_PALETTE(pipe, i), word);
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index 0a69e80821ee..b7685936d324 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5036,7 +5036,7 @@ intel_pre_disable_primary_noatomic(struct drm_crtc 
> *crtc)
>* event which is after the vblank start event, so we need to have a
>* wait-for-vblank between disabling the plane and the pipe.
>*/
> - if (HAS_GMCH_DISPLAY(dev)) {
> + if (HAS_GMCH_DISPLAY(dev_priv)) {
>   intel_set_memory_cxsr(dev_priv, false);
>   dev_priv->wm.vlv.cxsr = false;
>   intel_wait_for_vblank(dev, pipe);
> @@ -5101,7 +5101,7 @@ static void intel_pre_plane_update(struct 
> intel_crtc_state *old_crtc_state)
>   intel_pre_disable_primary(>base);
>   }
>  
> - if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev)) {
> + if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev_priv)) {
>   crtc->wm.cxsr_allowed = false;
>  
>   /*
> @@ -10895,7 +10895,7 @@ static void intel_crtc_update_cursor(struct drm_crtc 
> *crtc,
>   pos |= y << CURSOR_Y_SHIFT;
>  
>   /* ILK+ do this automagically */
> - if (HAS_GMCH_DISPLAY(dev) &&
> + if (HAS_GMCH_DISPLAY(dev_priv) &&
>   plane_state->base.rotation == DRM_ROTATE_180) {
>   base += (plane_state->base.crtc_h *
>plane_state->base.crtc_w - 1) * 4;
> @@ -16593,7 +16593,7 @@ static void intel_sanitize_crtc(struct intel_crtc 
> 

[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915/dp: Debug log MST active links explicitly

[Patchwork]

== Series Details ==

Series: drm/i915/dp: Debug log MST active links explicitly
URL   : https://patchwork.freedesktop.org/series/13627/
State : warning

== Summary ==

Series 13627v1 drm/i915/dp: Debug log MST active links explicitly
https://patchwork.freedesktop.org/api/1.0/series/13627/revisions/1/mbox/

Test kms_force_connector_basic:
Subgroup prune-stale-modes:
pass   -> SKIP   (fi-snb-2600)
Test kms_pipe_crc_basic:
Subgroup nonblocking-crc-pipe-a:
pass   -> DMESG-WARN (fi-ilk-650)
Subgroup read-crc-pipe-c:
pass   -> DMESG-WARN (fi-skl-6770hq)
Subgroup suspend-read-crc-pipe-a:
pass   -> DMESG-WARN (fi-ivb-3770)
Subgroup suspend-read-crc-pipe-b:
pass   -> DMESG-WARN (fi-byt-j1900)
Test vgem_basic:
Subgroup unload:
pass   -> SKIP   (fi-skl-6260u)
skip   -> PASS   (fi-kbl-7200u)

fi-bdw-5557u total:248  pass:232  dwarn:0   dfail:0   fail:0   skip:16 
fi-bsw-n3050 total:248  pass:205  dwarn:0   dfail:0   fail:0   skip:43 
fi-bxt-t5700 total:248  pass:217  dwarn:0   dfail:0   fail:0   skip:31 
fi-byt-j1900 total:248  pass:213  dwarn:2   dfail:0   fail:1   skip:32 
fi-byt-n2820 total:248  pass:211  dwarn:0   dfail:0   fail:1   skip:36 
fi-hsw-4770  total:248  pass:225  dwarn:0   dfail:0   fail:0   skip:23 
fi-hsw-4770r total:248  pass:225  dwarn:0   dfail:0   fail:0   skip:23 
fi-ilk-650   total:248  pass:184  dwarn:1   dfail:0   fail:2   skip:61 
fi-ivb-3520m total:248  pass:222  dwarn:0   dfail:0   fail:0   skip:26 
fi-ivb-3770  total:248  pass:221  dwarn:1   dfail:0   fail:0   skip:26 
fi-kbl-7200u total:248  pass:223  dwarn:0   dfail:0   fail:0   skip:25 
fi-skl-6260u total:248  pass:232  dwarn:0   dfail:0   fail:0   skip:16 
fi-skl-6700hqtotal:248  pass:225  dwarn:0   dfail:0   fail:0   skip:23 
fi-skl-6700k total:248  pass:222  dwarn:1   dfail:0   fail:0   skip:25 
fi-skl-6770hqtotal:248  pass:230  dwarn:2   dfail:0   fail:1   skip:15 
fi-snb-2520m total:248  pass:211  dwarn:0   dfail:0   fail:0   skip:37 
fi-snb-2600  total:248  pass:209  dwarn:0   dfail:0   fail:0   skip:39 

Results at /archive/results/CI_IGT_test/Patchwork_2679/

f766f3683894b41737352df7e0c0b7aaddd739e3 drm-intel-nightly: 
2016y-10m-12d-08h-02m-34s UTC integration manifest
fc9a842 drm/i915/dp: Debug log MST active links explicitly

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[Intel-gfx] [PATCH] kernel/cpu: Distinct name for cpu_hotplug.dep_map

[Joonas Lahtinen]

Hi Linus/Andrew,

This patch has been waiting for feedback or merging for ~8 months now.
It was posted to linux-ker...@vger.kernel.org initially and got an
immediate Acked-by. After no other feedback, I revised the assumed
maintainers and still no reactions. Next I changed over to
triv...@kernel.org and it was reviewed by Chris in the meanwhile,
but still no other feedback or merge (now 2 months).

I don't think sending the patch around endlessly is very productive,
or hammering same mailing lists/people repeatedly for that matter. So
I'd like to hear what's the correct channel for getting the patch in?

It has been dragged in a i915 testing branch to make CI lockdep splats
more readable.

Regards, Joonas
8<---
Use distinctive name for cpu_hotplug.dep_map to avoid the actual
cpu_hotplug.lock appearing as cpu_hotplug.lock#2 in lockdep splats.

Cc: Ingo Molnar 
Cc: Peter Zijlstra 
Cc: Gautham R. Shenoy 
Cc: intel-gfx@lists.freedesktop.org
Cc: triv...@kernel.org
Acked-by: Gautham R. Shenoy 
Reviewed-by: Chris Wilson 
Signed-off-by: Joonas Lahtinen 
---
 kernel/cpu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/kernel/cpu.c b/kernel/cpu.c
index 5df20d6..29de1a9 100644
--- a/kernel/cpu.c
+++ b/kernel/cpu.c
@@ -228,7 +228,7 @@ static struct {
.wq = __WAIT_QUEUE_HEAD_INITIALIZER(cpu_hotplug.wq),
.lock = __MUTEX_INITIALIZER(cpu_hotplug.lock),
 #ifdef CONFIG_DEBUG_LOCK_ALLOC
-   .dep_map = {.name = "cpu_hotplug.lock" },
+   .dep_map = STATIC_LOCKDEP_MAP_INIT("cpu_hotplug.dep_map", 
_hotplug.dep_map),
 #endif
 };
 
-- 
2.7.4

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[Intel-gfx] [PATCH 5/5] drm/i915: Remove superfluous locking around userfault_list

[Chris Wilson]

Now that we have reduced the access to the list to either (a) under the
struct_mutex whilst holding the RPM wakeref (so that concurrent writers to
the list are serialised by struct_mutex) and (b) under the atomic
runtime suspend (which cannot run concurrently with any other accessor due
to the atomic nature of the runtime suspend) we can remove the extra
locking around the list itself.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_drv.h |  3 ---
 drivers/gpu/drm/i915/i915_gem.c | 33 -
 2 files changed, 12 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 72b3126c6c74..13ca968a760a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1359,9 +1359,6 @@ struct i915_gem_mm {
 */
struct list_head unbound_list;
 
-   /** Protects access to the userfault_list */
-   spinlock_t userfault_lock;
-
/** List of all objects in gtt_space, currently mmaped by userspace.
 * All objects within this list must also be on bound_list.
 */
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 318501bb268c..b573a50148cb 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1853,10 +1853,8 @@ int i915_gem_fault(struct vm_area_struct *area, struct 
vm_fault *vmf)
goto err_unpin;
 
assert_rpm_wakelock_held(dev_priv);
-   spin_lock(_priv->mm.userfault_lock);
if (list_empty(>userfault_link))
list_add(>userfault_link, _priv->mm.userfault_list);
-   spin_unlock(_priv->mm.userfault_lock);
 
 err_unpin:
__i915_vma_unpin(vma);
@@ -1926,7 +1924,6 @@ void
 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
 {
struct drm_i915_private *i915 = to_i915(obj->base.dev);
-   bool zap = false;
 
/* Serialisation between user GTT access and our code depends upon
 * revoking the CPU's PTE whilst the mutex is held. The next user
@@ -1939,15 +1936,10 @@ i915_gem_release_mmap(struct drm_i915_gem_object *obj)
lockdep_assert_held(>drm.struct_mutex);
intel_runtime_pm_get(i915);
 
-   spin_lock(>mm.userfault_lock);
-   if (!list_empty(>userfault_link)) {
-   list_del_init(>userfault_link);
-   zap = true;
-   }
-   spin_unlock(>mm.userfault_lock);
-   if (!zap)
+   if (list_empty(>userfault_link))
goto out;
 
+   list_del_init(>userfault_link);
drm_vma_node_unmap(>base.vma_node,
   obj->base.dev->anon_inode->i_mapping);
 
@@ -1967,21 +1959,21 @@ out:
 void
 i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
 {
-   struct drm_i915_gem_object *obj;
+   struct drm_i915_gem_object *obj, *on;
 
-   spin_lock(_priv->mm.userfault_lock);
-   while ((obj = list_first_entry_or_null(_priv->mm.userfault_list,
-  struct drm_i915_gem_object,
-  userfault_link))) {
-   list_del_init(>userfault_link);
-   spin_unlock(_priv->mm.userfault_lock);
+   /*
+* Only called during RPM suspend. All users of the userfault_list
+* must be holding an RPM wakeref to ensure that this can not
+* run concurrently with themselves (and use the struct_mutex for
+* protection between themselves).
+*/
 
+   list_for_each_entry_safe(obj, on,
+_priv->mm.userfault_list, userfault_link) {
+   list_del_init(>userfault_link);
drm_vma_node_unmap(>base.vma_node,
   obj->base.dev->anon_inode->i_mapping);
-
-   spin_lock(_priv->mm.userfault_lock);
}
-   spin_unlock(_priv->mm.userfault_lock);
 }
 
 /**
@@ -4468,7 +4460,6 @@ int i915_gem_init(struct drm_device *dev)
int ret;
 
mutex_lock(>struct_mutex);
-   spin_lock_init(_priv->mm.userfault_lock);
 
if (!i915.enable_execlists) {
dev_priv->gt.resume = intel_legacy_submission_resume;
-- 
2.9.3

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[Intel-gfx] [PATCH 3/5] drm/i915: Move user fault tracking to a separate list

[Chris Wilson]

We want to decouple RPM and struct_mutex, but currently RPM has to walk
the list of bound objects and remove userspace mmapping before we
suspend (otherwise userspace may continue to access the GTT whilst it is
powered down). This currently requires the struct_mutex to walk the
bound_list, but if we move that to a separate list and lock we can take
the first step towards removing the struct_mutex.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_debugfs.c   |  2 +-
 drivers/gpu/drm/i915/i915_drv.h   | 20 +++---
 drivers/gpu/drm/i915/i915_gem.c   | 39 ---
 drivers/gpu/drm/i915/i915_gem_evict.c |  2 +-
 4 files changed, 47 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 2e312e0f2670..0ce135dd80fb 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -107,7 +107,7 @@ static char get_tiling_flag(struct drm_i915_gem_object *obj)
 
 static char get_global_flag(struct drm_i915_gem_object *obj)
 {
-   return obj->fault_mappable ? 'g' : ' ';
+   return !list_empty(>userfault_link) ? 'g' : ' ';
 }
 
 static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index bf397b643cc0..72b3126c6c74 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1359,6 +1359,14 @@ struct i915_gem_mm {
 */
struct list_head unbound_list;
 
+   /** Protects access to the userfault_list */
+   spinlock_t userfault_lock;
+
+   /** List of all objects in gtt_space, currently mmaped by userspace.
+* All objects within this list must also be on bound_list.
+*/
+   struct list_head userfault_list;
+
/** Usable portion of the GTT for GEM */
unsigned long stolen_base; /* limited to low memory (32-bit) */
 
@@ -2215,6 +2223,11 @@ struct drm_i915_gem_object {
struct drm_mm_node *stolen;
struct list_head global_list;
 
+   /**
+* Whether the object is currently in the GGTT mmap.
+*/
+   struct list_head userfault_link;
+
/** Used in execbuf to temporarily hold a ref */
struct list_head obj_exec_link;
 
@@ -2242,13 +2255,6 @@ struct drm_i915_gem_object {
 */
unsigned int madv:2;
 
-   /**
-* Whether the current gtt mapping needs to be mappable (and isn't just
-* mappable by accident). Track pin and fault separate for a more
-* accurate mappable working set.
-*/
-   unsigned int fault_mappable:1;
-
/*
 * Is the object to be mapped as read-only to the GPU
 * Only honoured if hardware has relevant pte bit
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index fdd496e6c081..82e05ff6295d 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1850,7 +1850,11 @@ int i915_gem_fault(struct vm_area_struct *area, struct 
vm_fault *vmf)
if (ret)
goto err_unpin;
 
-   obj->fault_mappable = true;
+   spin_lock(_priv->mm.userfault_lock);
+   if (list_empty(>userfault_link))
+   list_add(>userfault_link, _priv->mm.userfault_list);
+   spin_unlock(_priv->mm.userfault_lock);
+
 err_unpin:
__i915_vma_unpin(vma);
 err_unlock:
@@ -1918,13 +1922,22 @@ err:
 void
 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
 {
+   struct drm_i915_private *i915 = to_i915(obj->base.dev);
+   bool zap = false;
+
/* Serialisation between user GTT access and our code depends upon
 * revoking the CPU's PTE whilst the mutex is held. The next user
 * pagefault then has to wait until we release the mutex.
 */
-   lockdep_assert_held(>base.dev->struct_mutex);
+   lockdep_assert_held(>drm.struct_mutex);
 
-   if (!obj->fault_mappable)
+   spin_lock(>mm.userfault_lock);
+   if (!list_empty(>userfault_link)) {
+   list_del_init(>userfault_link);
+   zap = true;
+   }
+   spin_unlock(>mm.userfault_lock);
+   if (!zap)
return;
 
drm_vma_node_unmap(>base.vma_node,
@@ -1938,8 +1951,6 @@ i915_gem_release_mmap(struct drm_i915_gem_object *obj)
 * memory writes before touching registers / GSM.
 */
wmb();
-
-   obj->fault_mappable = false;
 }
 
 void
@@ -1947,8 +1958,19 @@ i915_gem_release_all_mmaps(struct drm_i915_private 
*dev_priv)
 {
struct drm_i915_gem_object *obj;
 
-   list_for_each_entry(obj, _priv->mm.bound_list, global_list)
-   i915_gem_release_mmap(obj);
+   spin_lock(_priv->mm.userfault_lock);
+   while ((obj = list_first_entry_or_null(_priv->mm.userfault_list,
+  struct drm_i915_gem_object,
+   

[Intel-gfx] [PATCH 2/5] drm/i915: Update debugfs describe_obj() to show fault-mappable

[Chris Wilson]

The current meaning of whether an object has a GGTT vma is very
ill-defined (and note we don't check for any partials either), it just
means that at some point it was in the GGTT but it may not be now. The
information we really care about here is whether it is taking up
precious mappable aperture space. This is the obj->fault_mappable flag.
We have a redundant long form reprinting of this information, so remove
that in favour of the compact flag.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 11 +--
 1 file changed, 1 insertion(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 358663e833d6..2e312e0f2670 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -107,7 +107,7 @@ static char get_tiling_flag(struct drm_i915_gem_object *obj)
 
 static char get_global_flag(struct drm_i915_gem_object *obj)
 {
-   return i915_gem_object_to_ggtt(obj, NULL) ?  'g' : ' ';
+   return obj->fault_mappable ? 'g' : ' ';
 }
 
 static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
@@ -186,15 +186,6 @@ describe_obj(struct seq_file *m, struct 
drm_i915_gem_object *obj)
}
if (obj->stolen)
seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
-   if (obj->pin_display || obj->fault_mappable) {
-   char s[3], *t = s;
-   if (obj->pin_display)
-   *t++ = 'p';
-   if (obj->fault_mappable)
-   *t++ = 'f';
-   *t = '\0';
-   seq_printf(m, " (%s mappable)", s);
-   }
 
engine = i915_gem_active_get_engine(>last_write,
_priv->drm.struct_mutex);
-- 
2.9.3

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Re: [Intel-gfx] [PATCH i-g-t 1/5] tests: Use bash for debugfs_wedged and drm_lib.sh

[Jani Nikula]

On Wed, 12 Oct 2016, David Weinehall  wrote:
> On Fri, Oct 07, 2016 at 12:54:03PM +0300, Joonas Lahtinen wrote:
>> On pe, 2016-10-07 at 10:38 +0300, Jani Nikula wrote:
>> > The "change" to use bash just reflects current reality. All the changes
>> > here look simple and sane, and immediately improve the results. The work
>> > is already done, no use blocking them because someone might eventually
>> > rewrite them in C. (And it will be a PITA to write the module reload
>> > test in C, so I wouldn't hold my breath.)
>> > 
>> 
>> The scripts are really simple, most of the scripts even use POSIX sh
>> compliant constructs but just the wrong shebang. And sometimes some a
>> advanced bash feature here and there which could be replaced easily.
>> 
>> > For the series,
>> > 
>> > Reviewed-by: Jani Nikula 
>> > 
>> > 
>> > PS. When I look at IGT and the macro/setjmp/longjmp magic to create the
>> > test/subtest/fixture infrastructure, making the tests look like they've
>> > been written in some extended version of C, I have to question whether C
>> > really is the right language for the tests. libdrm python bindings and
>> > python, anyone?
>> 
>> My patches to convert away from bash were to allow running the tests in
>> minimal initramfs environment where the kernel + IGT would be a
>> standalone bzImage suitable for netbooting, but we can go to another
>> direction too, and lets add Java as runtime requirement for I-G-T!
>> 
>> Regards, Joonas
>> 
>> I'm against converting to bash/python for no
>> benefit.
>
> +1, Insightful.
>
> Most of the bashisms seem to be simple cases of the superfluous
> "function" in front of functions...

The point here was that the scripts were *already* de-facto bash scripts
and would not have worked on a pure Bourne shell /bin/sh.

For generic scripts I'm fine with striving to keep them free of
bashisms, but at the same time for rather dedicated scripts which
already have a set of specific/non-trivial dependencies, I really can't
be bothered.

If you really care, go ahead and send the patches to make these Bourne
shell compatible, but then do also sign up for testing them on non-bash
shells. The CI won't. I don't think it's worth the trouble, but YMMV.

BR,
Jani.


-- 
Jani Nikula, Intel Open Source Technology Center
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[Intel-gfx] [PATCH 4/5] drm/i915: Use RPM as the barrier for controlling user mmap access

[Chris Wilson]

We can remove the false coupling between RPM and struct mutex by the
observation that we can use the RPM wakeref as the barrier around user
mmap access. That is as we tear down the user's PTE atomically from
within rpm suspend and then to fault in new PTE requires the rpm
wakeref, means that no user access is possible through those PTE without
RPM being awake. Having made that observation, we can then remove the
presumption of having to take rpm outside of struct_mutex and so allow
fine grained acquisition of a wakeref around hw access rather than
having to remember to acquire the wakeref early on.

Signed-off-by: Chris Wilson 
Cc: Imre Deak 
Cc: Daniel Vetter 
Cc: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_debugfs.c| 22 --
 drivers/gpu/drm/i915/i915_drv.c| 19 ---
 drivers/gpu/drm/i915/i915_gem.c| 22 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c| 17 +
 drivers/gpu/drm/i915/i915_gem_tiling.c |  4 
 drivers/gpu/drm/i915/intel_uncore.c|  6 +++---
 6 files changed, 29 insertions(+), 61 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 0ce135dd80fb..503d56b6faef 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1391,14 +1391,9 @@ static int i915_hangcheck_info(struct seq_file *m, void 
*unused)
 static int ironlake_drpc_info(struct seq_file *m)
 {
struct drm_i915_private *dev_priv = node_to_i915(m->private);
-   struct drm_device *dev = _priv->drm;
u32 rgvmodectl, rstdbyctl;
u16 crstandvid;
-   int ret;
 
-   ret = mutex_lock_interruptible(>struct_mutex);
-   if (ret)
-   return ret;
intel_runtime_pm_get(dev_priv);
 
rgvmodectl = I915_READ(MEMMODECTL);
@@ -1406,7 +1401,6 @@ static int ironlake_drpc_info(struct seq_file *m)
crstandvid = I915_READ16(CRSTANDVID);
 
intel_runtime_pm_put(dev_priv);
-   mutex_unlock(>struct_mutex);
 
seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
seq_printf(m, "Boost freq: %d\n",
@@ -2084,12 +2078,7 @@ static const char *swizzle_string(unsigned swizzle)
 static int i915_swizzle_info(struct seq_file *m, void *data)
 {
struct drm_i915_private *dev_priv = node_to_i915(m->private);
-   struct drm_device *dev = _priv->drm;
-   int ret;
 
-   ret = mutex_lock_interruptible(>struct_mutex);
-   if (ret)
-   return ret;
intel_runtime_pm_get(dev_priv);
 
seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
@@ -2129,7 +2118,6 @@ static int i915_swizzle_info(struct seq_file *m, void 
*data)
seq_puts(m, "L-shaped memory detected\n");
 
intel_runtime_pm_put(dev_priv);
-   mutex_unlock(>struct_mutex);
 
return 0;
 }
@@ -4788,13 +4776,9 @@ i915_wedged_set(void *data, u64 val)
if (i915_reset_in_progress(_priv->gpu_error))
return -EAGAIN;
 
-   intel_runtime_pm_get(dev_priv);
-
i915_handle_error(dev_priv, val,
  "Manually setting wedged to %llu", val);
 
-   intel_runtime_pm_put(dev_priv);
-
return 0;
 }
 
@@ -5029,22 +5013,16 @@ static int
 i915_cache_sharing_get(void *data, u64 *val)
 {
struct drm_i915_private *dev_priv = data;
-   struct drm_device *dev = _priv->drm;
u32 snpcr;
-   int ret;
 
if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
return -ENODEV;
 
-   ret = mutex_lock_interruptible(>struct_mutex);
-   if (ret)
-   return ret;
intel_runtime_pm_get(dev_priv);
 
snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
 
intel_runtime_pm_put(dev_priv);
-   mutex_unlock(>struct_mutex);
 
*val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
 
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 89d322215c84..31eee32fcf6d 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2313,24 +2313,6 @@ static int intel_runtime_suspend(struct device *kdev)
 
DRM_DEBUG_KMS("Suspending device\n");
 
-   /*
-* We could deadlock here in case another thread holding struct_mutex
-* calls RPM suspend concurrently, since the RPM suspend will wait
-* first for this RPM suspend to finish. In this case the concurrent
-* RPM resume will be followed by its RPM suspend counterpart. Still
-* for consistency return -EAGAIN, which will reschedule this suspend.
-*/
-   if (!mutex_trylock(>struct_mutex)) {
-   DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
-   /*
-* Bump the expiration timestamp, otherwise the suspend won't
-* be rescheduled.
-*/

[Intel-gfx] [CI 2/2] drm/i915: Update debugfs describe_obj() to show fault-mappable

[Chris Wilson]

The current meaning of whether an object has a GGTT vma is very
ill-defined (and note we don't check for any partials either), it just
means that at some point it was in the GGTT but it may not be now. The
information we really care about here is whether it is taking up
precious mappable aperture space. This is the obj->fault_mappable flag.
We have a redundant long form reprinting of this information, so remove
that in favour of the compact flag.

Signed-off-by: Chris Wilson 
Reviewed-by: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 11 +--
 1 file changed, 1 insertion(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 358663e833d6..2e312e0f2670 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -107,7 +107,7 @@ static char get_tiling_flag(struct drm_i915_gem_object *obj)
 
 static char get_global_flag(struct drm_i915_gem_object *obj)
 {
-   return i915_gem_object_to_ggtt(obj, NULL) ?  'g' : ' ';
+   return obj->fault_mappable ? 'g' : ' ';
 }
 
 static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
@@ -186,15 +186,6 @@ describe_obj(struct seq_file *m, struct 
drm_i915_gem_object *obj)
}
if (obj->stolen)
seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
-   if (obj->pin_display || obj->fault_mappable) {
-   char s[3], *t = s;
-   if (obj->pin_display)
-   *t++ = 'p';
-   if (obj->fault_mappable)
-   *t++ = 'f';
-   *t = '\0';
-   seq_printf(m, " (%s mappable)", s);
-   }
 
engine = i915_gem_active_get_engine(>last_write,
_priv->drm.struct_mutex);
-- 
2.9.3

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[Intel-gfx] [CI 1/2] drm/i915: Use fence_write() from rpm resume

[Chris Wilson]

During rpm resume we restore the fences, but we do not have the
protection of struct_mutex. This rules out updating the activity
tracking on the fences, and requires us to rely on the rpm as the
serialisation barrier instead.

[  350.298052] [drm:intel_runtime_resume [i915]] Resuming device
[  350.308606]
[  350.310520] ===
[  350.315560] [ INFO: suspicious RCU usage. ]
[  350.320554] 4.8.0-rc8-bsw-rapl+ #3133 Tainted: G U  W
[  350.327208] ---
[  350.331977] ../drivers/gpu/drm/i915/i915_gem_request.h:371 suspicious 
rcu_dereference_protected() usage!
[  350.342619]
[  350.342619] other info that might help us debug this:
[  350.342619]
[  350.351593]
[  350.351593] rcu_scheduler_active = 1, debug_locks = 0
[  350.358952] 3 locks held by Xorg/320:
[  350.363077]  #0:  (>mode_config.mutex){+.+.+.}, at: 
[] drm_modeset_lock_all+0x3c/0xd0 [drm]
[  350.375162]  #1:  (crtc_ww_class_acquire){+.+.+.}, at: [] 
drm_modeset_lock_all+0x46/0xd0 [drm]
[  350.387022]  #2:  (crtc_ww_class_mutex){+.+.+.}, at: [] 
drm_modeset_lock+0x36/0x110 [drm]
[  350.398236]
[  350.398236] stack backtrace:
[  350.403196] CPU: 1 PID: 320 Comm: Xorg Tainted: G U  W   
4.8.0-rc8-bsw-rapl+ #3133
[  350.412457] Hardware name: Intel Corporation CHERRYVIEW C0 PLATFORM/Braswell 
CRB, BIOS BRAS.X64.X088.R00.1510270350 10/27/2015
[  350.425212]   8801680a78c8 81332187 
88016c5c5000
[  350.433611]  0001 8801680a78f8 810ca6da 
88016cc8b0f0
[  350.442012]  88016cc8 88016cc8 880177ad 
8801680a7948
[  350.450409] Call Trace:
[  350.453165]  [] dump_stack+0x67/0x90
[  350.458931]  [] lockdep_rcu_suspicious+0xea/0x120
[  350.466002]  [] fence_update+0xbd/0x670 [i915]
[  350.472766]  [] i915_gem_restore_fences+0x52/0x70 [i915]
[  350.480496]  [] vlv_resume_prepare+0x72/0x570 [i915]
[  350.487839]  [] intel_runtime_resume+0x102/0x210 [i915]
[  350.495442]  [] pci_pm_runtime_resume+0x7f/0xb0
[  350.502274]  [] ? pci_restore_standard_config+0x40/0x40
[  350.509883]  [] __rpm_callback+0x35/0x70
[  350.516037]  [] ? pci_restore_standard_config+0x40/0x40
[  350.523646]  [] rpm_callback+0x24/0x80
[  350.529604]  [] ? pci_restore_standard_config+0x40/0x40
[  350.537212]  [] rpm_resume+0x4ad/0x740
[  350.543161]  [] __pm_runtime_resume+0x51/0x80
[  350.549824]  [] intel_runtime_pm_get+0x28/0x90 [i915]
[  350.557265]  [] intel_display_power_get+0x23/0x50 [i915]
[  350.565001]  [] intel_atomic_commit_tail+0xdfd/0x10b0 
[i915]
[  350.573106]  [] ? drm_atomic_helper_swap_state+0x159/0x300 
[drm_kms_helper]
[  350.582659]  [] ? _raw_spin_unlock+0x31/0x50
[  350.589205]  [] ? drm_atomic_helper_swap_state+0x159/0x300 
[drm_kms_helper]
[  350.598787]  [] intel_atomic_commit+0x3b5/0x500 [i915]
[  350.606319]  [] ? 
drm_atomic_set_crtc_for_connector+0xcc/0x100 [drm]
[  350.615209]  [] drm_atomic_commit+0x49/0x50 [drm]
[  350.622242]  [] drm_atomic_helper_set_config+0x88/0xc0 
[drm_kms_helper]
[  350.631419]  [] drm_mode_set_config_internal+0x6c/0x120 
[drm]
[  350.639623]  [] drm_mode_setcrtc+0x22c/0x4d0 [drm]
[  350.646760]  [] drm_ioctl+0x209/0x460 [drm]
[  350.653217]  [] ? drm_mode_getcrtc+0x150/0x150 [drm]
[  350.660536]  [] ? __lock_is_held+0x4a/0x70
[  350.666885]  [] do_vfs_ioctl+0x93/0x6b0
[  350.672939]  [] ? __fget+0x113/0x200
[  350.678797]  [] ? __fget+0x5/0x200
[  350.684361]  [] SyS_ioctl+0x44/0x80
[  350.690030]  [] do_syscall_64+0x5b/0x120
[  350.696184]  [] entry_SYSCALL64_slow_path+0x25/0x25

Note we also have to remember the lesson from commit 4fc788f5ee3d
("drm/i915: Flush delayed fence releases after reset") where we have to
flush any changes to the fence on restore.

v2: Replace call to release user mmaps with an assertion that they have
already been zapped.

Fixes: 49ef5294cda2 ("drm/i915: Move fence tracking from object to vma")
Reported-by: Ville Syrjälä 
Signed-off-by: Chris Wilson 
Cc: Ville Syrjälä 
Cc: Joonas Lahtinen 
Cc: Mika Kuoppala 
Reviewed-by: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_gem_fence.c | 21 +++--
 1 file changed, 19 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_fence.c 
b/drivers/gpu/drm/i915/i915_gem_fence.c
index 8df1fa7234e8..2c7ba0ee127c 100644
--- a/drivers/gpu/drm/i915/i915_gem_fence.c
+++ b/drivers/gpu/drm/i915/i915_gem_fence.c
@@ -290,6 +290,8 @@ i915_vma_put_fence(struct i915_vma *vma)
 {
struct drm_i915_fence_reg *fence = vma->fence;
 
+   assert_rpm_wakelock_held(to_i915(vma->vm->dev));
+
if (!fence)
return 0;
 
@@ -341,6 +343,8 @@ i915_vma_get_fence(struct i915_vma *vma)
struct drm_i915_fence_reg *fence;
struct i915_vma *set = i915_gem_object_is_tiled(vma->obj) ? vma : NULL;
 
+  

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,1/2] drm/i915: Use fence_write() from rpm resume

[Patchwork]

== Series Details ==

Series: series starting with [CI,1/2] drm/i915: Use fence_write() from rpm 
resume
URL   : https://patchwork.freedesktop.org/series/13642/
State : failure

== Summary ==

Series 13642v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/13642/revisions/1/mbox/

Test kms_pipe_crc_basic:
Subgroup bad-nb-words-1:
pass   -> DMESG-WARN (fi-ilk-650)
Subgroup suspend-read-crc-pipe-b:
dmesg-warn -> PASS   (fi-byt-j1900)
Test vgem_reload_basic:
pass   -> FAIL   (fi-hsw-4770)

fi-bdw-5557u total:248  pass:232  dwarn:0   dfail:0   fail:0   skip:16 
fi-bsw-n3050 total:248  pass:205  dwarn:0   dfail:0   fail:0   skip:43 
fi-bxt-t5700 total:248  pass:217  dwarn:0   dfail:0   fail:0   skip:31 
fi-byt-j1900 total:248  pass:214  dwarn:1   dfail:0   fail:1   skip:32 
fi-byt-n2820 total:248  pass:211  dwarn:0   dfail:0   fail:1   skip:36 
fi-hsw-4770  total:248  pass:223  dwarn:0   dfail:0   fail:1   skip:24 
fi-hsw-4770r total:248  pass:225  dwarn:0   dfail:0   fail:0   skip:23 
fi-ilk-650   total:248  pass:184  dwarn:1   dfail:0   fail:2   skip:61 
fi-ivb-3520m total:248  pass:222  dwarn:0   dfail:0   fail:0   skip:26 
fi-ivb-3770  total:248  pass:222  dwarn:0   dfail:0   fail:0   skip:26 
fi-kbl-7200u total:248  pass:223  dwarn:0   dfail:0   fail:0   skip:25 
fi-skl-6260u total:248  pass:233  dwarn:0   dfail:0   fail:0   skip:15 
fi-skl-6700hqtotal:248  pass:225  dwarn:0   dfail:0   fail:0   skip:23 
fi-skl-6700k total:248  pass:222  dwarn:1   dfail:0   fail:0   skip:25 
fi-skl-6770hqtotal:248  pass:231  dwarn:1   dfail:0   fail:1   skip:15 
fi-snb-2520m total:248  pass:211  dwarn:0   dfail:0   fail:0   skip:37 
fi-snb-2600  total:248  pass:210  dwarn:0   dfail:0   fail:0   skip:38 

Results at /archive/results/CI_IGT_test/Patchwork_2686/

46271d41e30090d7fc996e8f5abde6a59f51038b drm-intel-nightly: 
2016y-10m-12d-11h-06m-41s UTC integration manifest
3556a2e drm/i915: Update debugfs describe_obj() to show fault-mappable
652a473 drm/i915: Use fence_write() from rpm resume

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[Intel-gfx] [PATCH igt] igt/gem_wait: Use explicit timers

[Chris Wilson]

Rather than guestimating a workload that should take a certain amount of
time, use a sigitimer to terminate a batch (and so complete the wait)
after an exact amount of time. And in the process expand testing to
cover multiple rings and hangcheck.

Signed-off-by: Chris Wilson 
---
 lib/igt_core.h   |  27 
 tests/gem_wait.c | 443 +++
 2 files changed, 277 insertions(+), 193 deletions(-)

diff --git a/lib/igt_core.h b/lib/igt_core.h
index 433b88c..03be757 100644
--- a/lib/igt_core.h
+++ b/lib/igt_core.h
@@ -403,6 +403,24 @@ static inline void igt_ignore_warn(bool value)
} while (0)
 
 /**
+ * igt_assert_cmps64:
+ * @n1: first value
+ * @cmp: compare operator
+ * @ncmp: negated version of @cmp
+ * @n2: second value
+ *
+ * Like igt_assert_cmpuint(), but for larger signed ints.
+ */
+#define igt_assert_cmps64(n1, cmp, ncmp, n2) \
+   do { \
+   int64_t __n1 = (n1), __n2 = (n2); \
+   if (__n1 cmp __n2) ; else \
+   __igt_fail_assert(IGT_LOG_DOMAIN, __FILE__, __LINE__, __func__, 
\
+ #n1 " " #cmp " " #n2, \
+ "error: %lld " #ncmp " %lld\n", (long 
long)__n1, (long long)__n2); \
+   } while (0)
+
+/**
  * igt_assert_cmpu64:
  * @n1: first value
  * @cmp: compare operator
@@ -461,6 +479,15 @@ static inline void igt_ignore_warn(bool value)
 #define igt_assert_eq_u32(n1, n2) igt_assert_cmpuint(n1, ==, !=, n2)
 
 /**
+ * igt_assert_eq_s64:
+ * @n1: first integer
+ * @n2: second integer
+ *
+ * Like igt_assert_eq_u32(), but for int64_t.
+ */
+#define igt_assert_eq_s64(n1, n2) igt_assert_cmps64(n1, ==, !=, n2)
+
+/**
  * igt_assert_eq_u64:
  * @n1: first integer
  * @n2: second integer
diff --git a/tests/gem_wait.c b/tests/gem_wait.c
index 461efdb..0ecb92f 100644
--- a/tests/gem_wait.c
+++ b/tests/gem_wait.c
@@ -26,233 +26,290 @@
  */
 
 #include "igt.h"
-#include 
+
+#include 
 #include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-
-#include 
-
-#include "intel_bufmgr.h"
-
-#define MSEC_PER_SEC   1000L
-#define USEC_PER_MSEC  1000L
-#define NSEC_PER_USEC  1000L
-#define NSEC_PER_MSEC  100L
-#define USEC_PER_SEC   100L
-#define NSEC_PER_SEC   10L
-
-#define ENOUGH_WORK_IN_SECONDS 2
-#define BUF_SIZE (8<<20)
-#define BUF_PAGES ((8<<20)>>12)
-drm_intel_bo *dst, *dst2;
-
-/* returns time diff in milliseconds */
-static int64_t
-do_time_diff(struct timespec *end, struct timespec *start)
-{
-   int64_t ret;
-   ret = (MSEC_PER_SEC * difftime(end->tv_sec, start->tv_sec)) +
- ((end->tv_nsec/NSEC_PER_MSEC) - (start->tv_nsec/NSEC_PER_MSEC));
-   return ret;
-}
+#include 
 
-static void blt_color_fill(struct intel_batchbuffer *batch,
-  drm_intel_bo *buf,
-  const unsigned int pages)
-{
-   const unsigned short height = pages/4;
-   const unsigned short width =  4096;
-
-   COLOR_BLIT_COPY_BATCH_START(COLOR_BLT_WRITE_ALPHA |
-   XY_COLOR_BLT_WRITE_RGB);
-   OUT_BATCH((3 << 24) | /* 32 Bit Color */
- (0xF0 << 16)  | /* Raster OP copy background register */
- 0); /* Dest pitch is 0 */
-   OUT_BATCH(0);
-   OUT_BATCH(width << 16   |
- height);
-   OUT_RELOC_FENCED(buf, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 
0);
-   OUT_BATCH(rand()); /* random pattern */
-   ADVANCE_BATCH();
-}
+#define gettid() syscall(__NR_gettid)
+#define sigev_notify_thread_id _sigev_un._tid
 
-static void render_timeout(int fd)
+#define LOCAL_I915_EXEC_BSD_SHIFT  (13)
+#define LOCAL_I915_EXEC_BSD_MASK   (3 << LOCAL_I915_EXEC_BSD_SHIFT)
+
+#define ENGINE_MASK  (I915_EXEC_RING_MASK | LOCAL_I915_EXEC_BSD_MASK)
+
+static int __gem_wait(int fd, struct drm_i915_gem_wait *w)
 {
-   drm_intel_bufmgr *bufmgr;
-   struct intel_batchbuffer *batch;
-   int64_t timeout = ENOUGH_WORK_IN_SECONDS * NSEC_PER_SEC;
-   int64_t negative_timeout = -1;
-   int ret;
-   const bool do_signals = true; /* signals will seem to make the operation
-  * use less process CPU time */
-   bool done = false;
-   int i, iter = 1;
+   int err;
 
-   igt_skip_on_simulation();
+   err = 0;
+   if (igt_ioctl(fd, DRM_IOCTL_I915_GEM_WAIT, w))
+   err = -errno;
 
-   bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
-   drm_intel_bufmgr_gem_enable_reuse(bufmgr);
-   batch = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
-
-   dst = drm_intel_bo_alloc(bufmgr, "dst", BUF_SIZE, 4096);
-   dst2 = drm_intel_bo_alloc(bufmgr, "dst2", BUF_SIZE, 4096);
-
-   igt_skip_on_f(gem_wait(fd, dst->handle, ) == -EINVAL,
- "kernel doesn't support wait_timeout, skipping test\n");
-   

Re: [Intel-gfx] [PATCH 06/19] drm/i915: Make IS_GEN-range macro only take dev_priv

[David Weinehall]

On Tue, Oct 11, 2016 at 02:21:39PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin 
> 
> Saves 944 bytes of .rodata strings.
> 
> v2: Add parantheses around dev_priv. (Ville Syrjala)
> 
> Signed-off-by: Tvrtko Ursulin 

Reviewed-by: David Weinehall 

> ---
>  drivers/gpu/drm/i915/i915_drv.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index aac9375cccb3..58045cd7a087 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2616,7 +2616,7 @@ struct drm_i915_cmd_table {
>   *
>   * Use GEN_FOREVER for unbound start and or end.
>   */
> -#define IS_GEN(p, s, e) ({ \
> +#define IS_GEN(dev_priv, s, e) ({ \
>   unsigned int __s = (s), __e = (e); \
>   BUILD_BUG_ON(!__builtin_constant_p(s)); \
>   BUILD_BUG_ON(!__builtin_constant_p(e)); \
> @@ -2626,7 +2626,7 @@ struct drm_i915_cmd_table {
>   __e = BITS_PER_LONG - 1; \
>   else \
>   __e = (e) - 1; \
> - !!(INTEL_INFO(p)->gen_mask & GENMASK((__e), (__s))); \
> + !!((dev_priv)->info.gen_mask & GENMASK((__e), (__s))); \
>  })
>  
>  /*
> -- 
> 2.7.4
> 
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Re: [Intel-gfx] [PATCH i-g-t] tests/kms_plane_multiple: CRC based atomic correctness test

[Maarten Lankhorst]

Op 07-10-16 om 13:45 schreef Mika Kahola:
> This is a testcase with multiple planes. The idea here is the following
>
>  - draw a uniform frame with blue color
>  - grab crc for reference
>  - put planes randomly on top with the same blue color
>  - punch holes with black color into the primary framebuffer
>  - ideally the planes should cover these holes so that the output is the
>identical to reference crc
>  - composite all with one ioctl call
>  - grab crc and verify that the reference crc is equal
>  - repeat this for dozen iterations to maximize coverage
>
> Signed-off-by: Mika Kahola 
> ---
>  tests/Makefile.sources |   1 +
>  tests/kms_plane_multiple.c | 332 
> +
>  2 files changed, 333 insertions(+)
>  create mode 100644 tests/kms_plane_multiple.c
>
> diff --git a/tests/Makefile.sources b/tests/Makefile.sources
> index 598ec6f..aed0f3a 100644
> --- a/tests/Makefile.sources
> +++ b/tests/Makefile.sources
> @@ -105,6 +105,7 @@ TESTS_progs_M = \
>   kms_pipe_color \
>   kms_pipe_crc_basic \
>   kms_plane \
> + kms_plane_multiple \
>   kms_properties \
>   kms_psr_sink_crc \
>   kms_render \
> diff --git a/tests/kms_plane_multiple.c b/tests/kms_plane_multiple.c
> new file mode 100644
> index 000..153d6d1
> --- /dev/null
> +++ b/tests/kms_plane_multiple.c
> @@ -0,0 +1,332 @@
> +/*
> + * Copyright © 2016 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 
> DEALINGS
> + * IN THE SOFTWARE.
> + *
> + */
> +
> +#include "igt.h"
> +#include "drmtest.h"
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#define SIZE 128
> +
> +typedef struct {
> + float red;
> + float green;
> + float blue;
> +} color_t;
> +
> +typedef struct {
> + int drm_fd;
> + igt_display_t display;
> + igt_pipe_crc_t *pipe_crc;
> + igt_plane_t *primary;
> + igt_plane_t *sprite[IGT_MAX_PLANES-1];
> + struct igt_fb primary_fb;
> + struct igt_fb sprite_fb[IGT_MAX_PLANES-1];
Single array, instead of primary/sprite separate? See also below for index 
change..
> +} data_t;
> +
> +typedef struct {
> + data_t *data;
> + igt_crc_t reference_crc;
> +} test_position_t;
> +
> +/*
> + * Common code across all tests, acting on data_t
> + */
> +static void test_init(data_t *data, enum pipe pipe)
> +{
> + data->pipe_crc = igt_pipe_crc_new(pipe, INTEL_PIPE_CRC_SOURCE_AUTO);
> +}
> +
> +static void test_fini(data_t *data, igt_output_t *output, int nplanes)
> +{
> + igt_plane_set_fb(data->primary, NULL);
> +
> + for (int i = 0; i < nplanes; i++)
> + igt_plane_set_fb(data->sprite[i], NULL);
> +
> + /* reset the constraint on the pipe */
> + igt_output_set_pipe(output, PIPE_ANY);
> +
> + igt_pipe_crc_free(data->pipe_crc);
> +}
> +
> +static void
> +test_grab_crc(data_t *data, igt_output_t *output, enum pipe pipe,
> +   color_t *color, uint64_t tiling, int commit,
> +   igt_crc_t *crc /* out */)
> +{
> + struct igt_fb fb;
> + drmModeModeInfo *mode;
> + igt_plane_t *primary;
> +
> + igt_output_set_pipe(output, pipe);
> +
> + primary = igt_output_get_plane(output, IGT_PLANE_PRIMARY);
> +
> + mode = igt_output_get_mode(output);
> +
> + igt_create_color_fb(data->drm_fd, mode->hdisplay, mode->vdisplay,
> + DRM_FORMAT_XRGB,
> + LOCAL_DRM_FORMAT_MOD_NONE,
> + color->red, color->green, color->blue,
> + );
> +
> + igt_plane_set_fb(primary, );
> +
> + igt_display_commit2(>display, commit);
> +
> + igt_wait_for_vblank(data->drm_fd, pipe);
> +
> + igt_pipe_crc_collect_crc(data->pipe_crc, crc);
> +
> + igt_plane_set_fb(primary, NULL);
> +
> + igt_display_commit2(>display, commit);
> +
> + 

Re: [Intel-gfx] drm/i915: WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock)

[Jani Nikula]

On Wed, 12 Oct 2016, Paul Bolle  wrote:
> On Wed, 2016-10-12 at 14:08 +0300, Joonas Lahtinen wrote:
>> Bisecting the offending commit between v4.8 and v4.8.1 would be a good
>> start.
>
> That would be between v4.7 and v4.8. (I guess my report was ambiguous.)
>
> That might take some time. Because bisecting always takes a long time
> and especially since hitting this WARNING sometimes takes over an hour.
> Anyhow, please prod me if I stay silent for too long.

In the mean time, please file a bug over at [1] so we don't lose track.

BR,
Jani.

[1] https://bugs.freedesktop.org/enter_bug.cgi?product=DRI=DRM/Intel

-- 
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[Intel-gfx] [PATCH igt] igt: Add exerciser for execbuf fence-out <-> fence-in

[Chris Wilson]

When execbuf2 supports explicit fencing with sync_file in/out fences
(via a fence-fd), we can control execution via the fence.

Signed-off-by: Chris Wilson 
---
 tests/Makefile.sources |   1 +
 tests/gem_exec_fence.c | 377 +
 2 files changed, 378 insertions(+)
 create mode 100644 tests/gem_exec_fence.c

diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index ddd8d7a..1938944 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -36,6 +36,7 @@ TESTS_progs_M = \
gem_exec_basic \
gem_exec_create \
gem_exec_faulting_reloc \
+   gem_exec_fence \
gem_exec_flush \
gem_exec_gttfill \
gem_exec_latency \
diff --git a/tests/gem_exec_fence.c b/tests/gem_exec_fence.c
new file mode 100644
index 000..815b666
--- /dev/null
+++ b/tests/gem_exec_fence.c
@@ -0,0 +1,377 @@
+/*
+ * Copyright © 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "igt.h"
+
+#include 
+#include 
+
+IGT_TEST_DESCRIPTION("Check that execbuf waits for explicit fences");
+
+#define LOCAL_PARAM_HAS_EXEC_FENCE 42
+#define LOCAL_EXEC_FENCE_IN (1 << 16)
+#define LOCAL_EXEC_FENCE_OUT (1 << 17)
+#define LOCAL_IOCTL_I915_GEM_EXECBUFFER2_WR   DRM_IOWR(DRM_COMMAND_BASE + 
DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
+
+static bool can_mi_store_dword(int gen, unsigned engine)
+{
+   return !(gen == 6 && (engine & ~(3<<13)) == I915_EXEC_BSD);
+}
+
+static void store(int fd, unsigned ring, int fence, uint32_t target, unsigned 
offset_value)
+{
+   const int SCRATCH = 0;
+   const int BATCH = 1;
+   const int gen = intel_gen(intel_get_drm_devid(fd));
+   struct drm_i915_gem_exec_object2 obj[2];
+   struct drm_i915_gem_relocation_entry reloc;
+   struct drm_i915_gem_execbuffer2 execbuf;
+   uint32_t batch[16];
+   int i;
+
+   memset(, 0, sizeof(execbuf));
+   execbuf.buffers_ptr = (uintptr_t)obj;
+   execbuf.buffer_count = 2;
+   execbuf.flags = ring | LOCAL_EXEC_FENCE_IN;
+   execbuf.rsvd2 = fence;
+   if (gen < 6)
+   execbuf.flags |= I915_EXEC_SECURE;
+
+   memset(obj, 0, sizeof(obj));
+   obj[SCRATCH].handle = target;
+
+   obj[BATCH].handle = gem_create(fd, 4096);
+   obj[BATCH].relocs_ptr = (uintptr_t)
+   obj[BATCH].relocation_count = 1;
+   memset(, 0, sizeof(reloc));
+
+   i = 0;
+   reloc.target_handle = obj[SCRATCH].handle;
+   reloc.presumed_offset = -1;
+   reloc.offset = sizeof(uint32_t) * (i + 1);
+   reloc.delta = sizeof(uint32_t) * offset_value;
+   reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
+   reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION;
+   batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
+   if (gen >= 8) {
+   batch[++i] = reloc.delta;
+   batch[++i] = 0;
+   } else if (gen >= 4) {
+   batch[++i] = 0;
+   batch[++i] = reloc.delta;
+   reloc.offset += sizeof(uint32_t);
+   } else {
+   batch[i]--;
+   batch[++i] = reloc.delta;
+   }
+   batch[++i] = offset_value;
+   batch[++i] = MI_BATCH_BUFFER_END;
+   gem_write(fd, obj[BATCH].handle, 0, batch, sizeof(batch));
+   gem_execbuf(fd, );
+   gem_close(fd, obj[BATCH].handle);
+}
+
+static int __gem_execbuf_wr(int fd, struct drm_i915_gem_execbuffer2 *execbuf)
+{
+   int err = 0;
+   if (igt_ioctl(fd, LOCAL_IOCTL_I915_GEM_EXECBUFFER2_WR, execbuf))
+   err = -errno;
+   errno = 0;
+   return err;
+}
+
+static void gem_execbuf_wr(int fd, struct drm_i915_gem_execbuffer2 *execbuf)
+{
+   igt_assert_eq(__gem_execbuf_wr(fd, execbuf), 0);
+}
+
+static bool fence_busy(int fence)
+{
+   return poll(&(struct pollfd){fence, POLLIN}, 1, 0) == 0;

Re: [Intel-gfx] [PATCH] drm/i915/hsw: Fix GPU hang during resume from S3-devices state

[Chris Wilson]

On Wed, Oct 12, 2016 at 05:46:37PM +0300, Imre Deak wrote:
> Currently resuming on HSW from S3 pm_test/devices state leads to an
> unrecoverable GPU hang. Resetting the GPU during suspend fixes this. For
> a full S3 cycle this change only means the reset happens earlier (before
> reaching S3). For S4 the reset will happen now both during the freeze
> and quiesce phases, which is a benefit since it will guarantee that the
> GPU is idle before creating and loading the hibernation image.
> 
> Cc: Mika Kuoppala 
> Cc: Chris Wilson 
> Suggested-by: Chris Wilson 
> Signed-off-by: Imre Deak 

Makes sense, we should treat the transition to suspend just like unload.
We should do the symmetric reset on load/resume as well.

Reviewed-by: Chris Wilson 
-Chris

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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,1/3] drm/i915: Remove unused "valid" parameter from pte_encode

[Patchwork]

== Series Details ==

Series: series starting with [CI,1/3] drm/i915: Remove unused "valid" parameter 
from pte_encode
URL   : https://patchwork.freedesktop.org/series/13646/
State : failure

== Summary ==

  LD  fs/btrfs/built-in.o
  LD  arch/x86/kernel/cpu/built-in.o
  LD  arch/x86/kernel/built-in.o
  LD  net/ipv4/built-in.o
  LD  drivers/usb/host/xhci-hcd.o
  LD  drivers/tty/vt/built-in.o
  LD  arch/x86/built-in.o
  LD  drivers/tty/built-in.o
  LD  drivers/usb/host/built-in.o
  LD  drivers/usb/built-in.o
  LD [M]  drivers/net/ethernet/intel/e1000/e1000.o
  LD  fs/ext4/ext4.o
  LD  fs/ext4/built-in.o
  LD  fs/built-in.o
  LD  drivers/md/md-mod.o
  LD  drivers/md/built-in.o
  LD  net/core/built-in.o
  LD  net/built-in.o
  LD [M]  drivers/net/ethernet/intel/igb/igb.o
  LD [M]  drivers/net/ethernet/intel/e1000e/e1000e.o
  LD  drivers/net/ethernet/built-in.o
  LD  drivers/net/built-in.o
scripts/Makefile.build:440: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:440: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:440: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:968: recipe for target 'drivers' failed
make: *** [drivers] Error 2

Full logs at /archive/deploy/logs/Patchwork_2687

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[Intel-gfx] [PATCH] drm/i915/hsw: Fix GPU hang during resume from S3-devices state

[Imre Deak]

Currently resuming on HSW from S3 pm_test/devices state leads to an
unrecoverable GPU hang. Resetting the GPU during suspend fixes this. For
a full S3 cycle this change only means the reset happens earlier (before
reaching S3). For S4 the reset will happen now both during the freeze
and quiesce phases, which is a benefit since it will guarantee that the
GPU is idle before creating and loading the hibernation image.

Cc: Mika Kuoppala 
Cc: Chris Wilson 
Suggested-by: Chris Wilson 
Signed-off-by: Imre Deak 
---
 drivers/gpu/drm/i915/i915_drv.c | 28 ++--
 drivers/gpu/drm/i915/i915_gem.c | 24 
 2 files changed, 26 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 89d3222..e9b3bfc 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -532,32 +532,6 @@ static const struct vga_switcheroo_client_ops 
i915_switcheroo_ops = {
 
 static void i915_gem_fini(struct drm_device *dev)
 {
-   struct drm_i915_private *dev_priv = to_i915(dev);
-
-   /*
-* Neither the BIOS, ourselves or any other kernel
-* expects the system to be in execlists mode on startup,
-* so we need to reset the GPU back to legacy mode. And the only
-* known way to disable logical contexts is through a GPU reset.
-*
-* So in order to leave the system in a known default configuration,
-* always reset the GPU upon unload. Afterwards we then clean up the
-* GEM state tracking, flushing off the requests and leaving the
-* system in a known idle state.
-*
-* Note that is of the upmost importance that the GPU is idle and
-* all stray writes are flushed *before* we dismantle the backing
-* storage for the pinned objects.
-*
-* However, since we are uncertain that reseting the GPU on older
-* machines is a good idea, we don't - just in case it leaves the
-* machine in an unusable condition.
-*/
-   if (HAS_HW_CONTEXTS(dev)) {
-   int reset = intel_gpu_reset(dev_priv, ALL_ENGINES);
-   WARN_ON(reset && reset != -ENODEV);
-   }
-
mutex_lock(>struct_mutex);
i915_gem_cleanup_engines(dev);
i915_gem_context_fini(dev);
@@ -636,6 +610,8 @@ static int i915_load_modeset_init(struct drm_device *dev)
return 0;
 
 cleanup_gem:
+   if (i915_gem_suspend(dev))
+   DRM_ERROR("failed to idle hardware; continuing to unload!\n");
i915_gem_fini(dev);
 cleanup_irq:
intel_guc_fini(dev);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index fdd496e..a86bc8f 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4273,6 +4273,30 @@ int i915_gem_suspend(struct drm_device *dev)
 */
WARN_ON(dev_priv->gt.awake);
 
+   /*
+* Neither the BIOS, ourselves or any other kernel
+* expects the system to be in execlists mode on startup,
+* so we need to reset the GPU back to legacy mode. And the only
+* known way to disable logical contexts is through a GPU reset.
+*
+* So in order to leave the system in a known default configuration,
+* always reset the GPU upon unload and suspend. Afterwards we then
+* clean up the GEM state tracking, flushing off the requests and
+* leaving the system in a known idle state.
+*
+* Note that is of the upmost importance that the GPU is idle and
+* all stray writes are flushed *before* we dismantle the backing
+* storage for the pinned objects.
+*
+* However, since we are uncertain that reseting the GPU on older
+* machines is a good idea, we don't - just in case it leaves the
+* machine in an unusable condition.
+*/
+   if (HAS_HW_CONTEXTS(dev)) {
+   int reset = intel_gpu_reset(dev_priv, ALL_ENGINES);
+   WARN_ON(reset && reset != -ENODEV);
+   }
+
return 0;
 
 err:
-- 
2.5.0

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Re: [Intel-gfx] drm/i915: WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock)

[Paul Bolle]

On Wed, 2016-10-12 at 17:34 +0300, Jani Nikula wrote:
> In the mean time, please file a bug over at [1] so we don't lose
> track.

Done:  https://bugs.freedesktop.org/show_bug.cgi?id=98214


Paul Bolle
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[Intel-gfx] [PATCH i-g-t] intel-ci: Remove kms_psr_sink_crc@psr_basic from BAT

[Petri Latvala]

The test is producing a lot of CI noise.

Signed-off-by: Petri Latvala 
---

Will be pushed shortly. Visible in CI results tomorrow-ish.


tests/intel-ci/fast-feedback.testlist | 1 -
 1 file changed, 1 deletion(-)

diff --git a/tests/intel-ci/fast-feedback.testlist 
b/tests/intel-ci/fast-feedback.testlist
index ae94381..e2fc9ac 100644
--- a/tests/intel-ci/fast-feedback.testlist
+++ b/tests/intel-ci/fast-feedback.testlist
@@ -208,7 +208,6 @@ igt@kms_pipe_crc_basic@read-crc-pipe-c-frame-sequence
 igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a
 igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b
 igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c
-igt@kms_psr_sink_crc@psr_basic
 igt@kms_setmode@basic-clone-single-crtc
 igt@kms_sink_crc_basic
 igt@pm_backlight@basic-brightness
-- 
2.9.3

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[Intel-gfx] [CI] drm/i915: Treat a framebuffer reference as an active reference whilst shrinking

[Chris Wilson]

Treat a framebuffer reference with the same priority as an active
reference whilst shrinking. Framebuffers are likely to be reused and
typically cost more to migrate to and from GPU memory (on LLC
architectures we need to clflush), so defer the temptation to purge them
during a kswapd run until we have run out of cheap buffers.

Signed-off-by: Chris Wilson 
Reviewed-by: John Harrison 
---
 drivers/gpu/drm/i915/i915_gem_shrinker.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_shrinker.c 
b/drivers/gpu/drm/i915/i915_gem_shrinker.c
index 1c237d02f30b..de25b6e0a101 100644
--- a/drivers/gpu/drm/i915/i915_gem_shrinker.c
+++ b/drivers/gpu/drm/i915/i915_gem_shrinker.c
@@ -182,8 +182,9 @@ i915_gem_shrink(struct drm_i915_private *dev_priv,
!is_vmalloc_addr(obj->mapping))
continue;
 
-   if ((flags & I915_SHRINK_ACTIVE) == 0 &&
-   i915_gem_object_is_active(obj))
+   if (!(flags & I915_SHRINK_ACTIVE) &&
+   (i915_gem_object_is_active(obj) ||
+obj->framebuffer_references))
continue;
 
if (!can_release_pages(obj))
-- 
2.9.3

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Re: [Intel-gfx] [PATCH i-g-t 1/5] tests: Use bash for debugfs_wedged and drm_lib.sh

[Jani Nikula]

On Wed, 12 Oct 2016, Joonas Lahtinen  wrote:
> On ke, 2016-10-12 at 14:16 +0300, Jani Nikula wrote:
>> If you really care, go ahead and send the patches to make these Bourne
>> shell compatible, but then do also sign up for testing them on non-bash
>> shells. The CI won't. I don't think it's worth the trouble, but YMMV.
>
> If they're re-written using POSIX sh constructs only, I don't think
> they need to be tested outside of POSIX sh? That's what standards are
> for.

It's just that if the majority of folks and the CI have bash as /bin/sh,
we won't notice when we accidentally add bashisms, and it'll eventually
break. Maybe you could keep running shellcheck [1] on them, or
something.

[1] https://www.shellcheck.net/

> I also remember FreeBSD guys being all for letting bash dependency go.
> So there'd be actual gains too.

I'm biting my lips not to quip on that.

> All are easily convertible. So let's do this.

If you have the time, go ahead. But don't break *any* functionality, no
compromises.


BR,
Jani.

-- 
Jani Nikula, Intel Open Source Technology Center
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Re: [Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915: Fix misplaced '\n' in printing the GPU error's RING_HEAD

[Saarinen, Jani]

> Test kms_flip:
> Subgroup basic-flip-vs-modeset:
> pass   -> DMESG-WARN (fi-skl-6770hq)
[  468.807117] [drm:skl_set_cdclk [i915]] *ERROR* failed to inform PCU about 
cdclk change
[  468.816844] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU 
pipe C FIFO underrun

> Test kms_pipe_crc_basic:
> Subgroup nonblocking-crc-pipe-b-frame-sequence:
> pass   -> DMESG-WARN (fi-ilk-650)
[  445.727655] [drm:intel_pch_fifo_underrun_irq_handler [i915]] *ERROR* PCH 
transcoder B FIFO underrun
[  445.727682] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU 
pipe B FIFO underrun

> Test vgem_basic:
> Subgroup unload:
> skip   -> PASS   (fi-hsw-4770)
> 
> fi-bdw-5557u total:248  pass:232  dwarn:0   dfail:0   fail:0   skip:16
> fi-bsw-n3050 total:248  pass:205  dwarn:0   dfail:0   fail:0   skip:43
> fi-bxt-t5700 total:248  pass:217  dwarn:0   dfail:0   fail:0   skip:31
> fi-byt-j1900 total:248  pass:213  dwarn:2   dfail:0   fail:1   skip:32
> fi-byt-n2820 total:248  pass:211  dwarn:0   dfail:0   fail:1   skip:36
> fi-hsw-4770  total:248  pass:225  dwarn:0   dfail:0   fail:0   skip:23
> fi-hsw-4770r total:248  pass:225  dwarn:0   dfail:0   fail:0   skip:23
> fi-ilk-650   total:248  pass:184  dwarn:1   dfail:0   fail:2   skip:61
> fi-ivb-3520m total:248  pass:222  dwarn:0   dfail:0   fail:0   skip:26
> fi-ivb-3770  total:248  pass:222  dwarn:0   dfail:0   fail:0   skip:26
> fi-kbl-7200u total:248  pass:223  dwarn:0   dfail:0   fail:0   skip:25
> fi-skl-6260u total:248  pass:233  dwarn:0   dfail:0   fail:0   skip:15
> fi-skl-6700hqtotal:248  pass:225  dwarn:0   dfail:0   fail:0   skip:23
> fi-skl-6700k total:248  pass:222  dwarn:1   dfail:0   fail:0   skip:25
> fi-skl-6770hqtotal:248  pass:230  dwarn:2   dfail:0   fail:1   skip:15
> fi-snb-2520m total:248  pass:211  dwarn:0   dfail:0   fail:0   skip:37
> fi-snb-2600  total:248  pass:210  dwarn:0   dfail:0   fail:0   skip:38
> 
> Results at /archive/results/CI_IGT_test/Patchwork_2683/
> 
> 46271d41e30090d7fc996e8f5abde6a59f51038b drm-intel-nightly: 2016y-10m-
> 12d-11h-06m-41s UTC integration manifest
> 35edc31 drm/i915: Fix misplaced '\n' in printing the GPU error's RING_HEAD
> 
> ___
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx


Jani Saarinen
Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo


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[Intel-gfx] [PATCH 1/8] drm/i915/skl+: Prepare for removing data rate from skl watermark state

[Maarten Lankhorst]

Caching is not required, drm_atomic_crtc_state_for_each_plane_state
can be used to inspect all plane_states that are assigned to the
current crtc_state, so we can just recalculate every time.

Signed-off-by: Maarten Lankhorst 
---
 drivers/gpu/drm/i915/intel_pm.c | 27 ---
 1 file changed, 12 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6af1587e9d84..b96a899c899d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -31,6 +31,7 @@
 #include "intel_drv.h"
 #include "../../../platform/x86/intel_ips.h"
 #include 
+#include 
 
 /**
  * DOC: RC6
@@ -3242,18 +3243,17 @@ skl_get_total_relative_data_rate(struct 
intel_crtc_state *intel_cstate)
struct drm_crtc *crtc = cstate->crtc;
struct drm_device *dev = crtc->dev;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-   const struct drm_plane *plane;
+   struct drm_plane *plane;
const struct intel_plane *intel_plane;
-   struct drm_plane_state *pstate;
+   const struct drm_plane_state *pstate;
unsigned int rate, total_data_rate = 0;
int id;
-   int i;
 
if (WARN_ON(!state))
return 0;
 
/* Calculate and cache data rate for each plane */
-   for_each_plane_in_state(state, plane, pstate, i) {
+   drm_atomic_crtc_state_for_each_plane_state(plane, pstate, cstate) {
id = skl_wm_plane_id(to_intel_plane(plane));
intel_plane = to_intel_plane(plane);
 
@@ -3356,7 +3356,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct intel_plane *intel_plane;
struct drm_plane *plane;
-   struct drm_plane_state *pstate;
+   const struct drm_plane_state *pstate;
enum pipe pipe = intel_crtc->pipe;
struct skl_ddb_entry *alloc = >wm.skl.ddb;
uint16_t alloc_size, start, cursor_blocks;
@@ -3392,14 +3392,14 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
alloc_size -= cursor_blocks;
 
/* 1. Allocate the mininum required blocks for each active plane */
-   for_each_plane_in_state(state, plane, pstate, i) {
+   drm_atomic_crtc_state_for_each_plane_state(plane, pstate, 
>base) {
intel_plane = to_intel_plane(plane);
id = skl_wm_plane_id(intel_plane);
 
if (intel_plane->pipe != pipe)
continue;
 
-   if (!to_intel_plane_state(pstate)->base.visible) {
+   if (!pstate->visible) {
minimum[id] = 0;
y_minimum[id] = 0;
continue;
@@ -3948,7 +3948,7 @@ skl_ddb_add_affected_planes(struct intel_crtc_state 
*cstate)
 
WARN_ON(!drm_atomic_get_existing_crtc_state(state, crtc));
 
-   drm_for_each_plane_mask(plane, dev, crtc->state->plane_mask) {
+   drm_for_each_plane_mask(plane, dev, cstate->base.plane_mask) {
id = skl_wm_plane_id(to_intel_plane(plane));
 
if (skl_ddb_entry_equal(_ddb->plane[pipe][id],
@@ -4063,14 +4063,12 @@ skl_print_wm_changes(const struct drm_atomic_state 
*state)
to_intel_atomic_state(state);
const struct drm_crtc *crtc;
const struct drm_crtc_state *cstate;
-   const struct drm_plane *plane;
const struct intel_plane *intel_plane;
-   const struct drm_plane_state *pstate;
const struct skl_ddb_allocation *old_ddb = _priv->wm.skl_hw.ddb;
const struct skl_ddb_allocation *new_ddb = _state->wm_results.ddb;
enum pipe pipe;
int id;
-   int i, j;
+   int i;
 
for_each_crtc_in_state(state, crtc, cstate, i) {
if (!crtc->state)
@@ -4078,10 +4076,9 @@ skl_print_wm_changes(const struct drm_atomic_state 
*state)
 
pipe = to_intel_crtc(crtc)->pipe;
 
-   for_each_plane_in_state(state, plane, pstate, j) {
+   for_each_intel_plane_on_crtc(dev, to_intel_crtc(crtc), 
intel_plane) {
const struct skl_ddb_entry *old, *new;
 
-   intel_plane = to_intel_plane(plane);
id = skl_wm_plane_id(intel_plane);
old = _ddb->plane[pipe][id];
new = _ddb->plane[pipe][id];
@@ -4094,13 +4091,13 @@ skl_print_wm_changes(const struct drm_atomic_state 
*state)
 
if (id != PLANE_CURSOR) {
DRM_DEBUG_ATOMIC("[PLANE:%d:plane %d%c] ddb (%d 
- %d) -> (%d - %d)\n",
-plane->base.id, id + 1,
+intel_plane->base.base.id, id 
+ 1,
 pipe_name(pipe),
 old->start, old->end,
 

[Intel-gfx] [PATCH 2/8] drm/i915/skl+: Remove data_rate from watermark struct.

[Maarten Lankhorst]

It's only used in one function, and can be calculated without caching it
in the global struct by using drm_atomic_crtc_state_for_each_plane_state.

Signed-off-by: Maarten Lankhorst 
---
 drivers/gpu/drm/i915/intel_drv.h |  4 
 drivers/gpu/drm/i915/intel_pm.c  | 44 +++-
 2 files changed, 21 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index bb468c974e14..888054518f3c 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -502,10 +502,6 @@ struct intel_crtc_wm_state {
struct skl_pipe_wm optimal;
struct skl_ddb_entry ddb;
 
-   /* cached plane data rate */
-   unsigned plane_data_rate[I915_MAX_PLANES];
-   unsigned plane_y_data_rate[I915_MAX_PLANES];
-
/* minimum block allocation */
uint16_t minimum_blocks[I915_MAX_PLANES];
uint16_t minimum_y_blocks[I915_MAX_PLANES];
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b96a899c899d..97b6202c4097 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3236,12 +3236,13 @@ skl_plane_relative_data_rate(const struct 
intel_crtc_state *cstate,
  *   3 * 4096 * 8192  * 4 < 2^32
  */
 static unsigned int
-skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate)
+skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
+unsigned *plane_data_rate,
+unsigned *plane_y_data_rate)
 {
struct drm_crtc_state *cstate = _cstate->base;
struct drm_atomic_state *state = cstate->state;
struct drm_crtc *crtc = cstate->crtc;
-   struct drm_device *dev = crtc->dev;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct drm_plane *plane;
const struct intel_plane *intel_plane;
@@ -3263,21 +3264,16 @@ skl_get_total_relative_data_rate(struct 
intel_crtc_state *intel_cstate)
/* packed/uv */
rate = skl_plane_relative_data_rate(intel_cstate,
pstate, 0);
-   intel_cstate->wm.skl.plane_data_rate[id] = rate;
+   plane_data_rate[id] = rate;
+
+   total_data_rate += rate;
 
/* y-plane */
rate = skl_plane_relative_data_rate(intel_cstate,
pstate, 1);
-   intel_cstate->wm.skl.plane_y_data_rate[id] = rate;
-   }
-
-   /* Calculate CRTC's total data rate from cached values */
-   for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
-   int id = skl_wm_plane_id(intel_plane);
+   plane_y_data_rate[id] = rate;
 
-   /* packed/uv */
-   total_data_rate += intel_cstate->wm.skl.plane_data_rate[id];
-   total_data_rate += intel_cstate->wm.skl.plane_y_data_rate[id];
+   total_data_rate += rate;
}
 
return total_data_rate;
@@ -3366,6 +3362,9 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
int num_active;
int id, i;
 
+   unsigned data_rate[I915_MAX_PLANES] = {};
+   unsigned y_data_rate[I915_MAX_PLANES] = {};
+
/* Clear the partitioning for disabled planes. */
memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
@@ -3425,29 +3424,28 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
 *
 * FIXME: we may not allocate every single block here.
 */
-   total_data_rate = skl_get_total_relative_data_rate(cstate);
+   total_data_rate = skl_get_total_relative_data_rate(cstate, data_rate, 
y_data_rate);
if (total_data_rate == 0)
return 0;
 
start = alloc->start;
-   for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
-   unsigned int data_rate, y_data_rate;
+   for (id = 0; id < I915_MAX_PLANES; id++) {
+   unsigned rate;
uint16_t plane_blocks, y_plane_blocks = 0;
-   int id = skl_wm_plane_id(intel_plane);
 
-   data_rate = cstate->wm.skl.plane_data_rate[id];
+   rate = data_rate[id];
 
/*
 * allocation for (packed formats) or (uv-plane part of planar 
format):
 * promote the expression to 64 bits to avoid overflowing, the
-* result is < available as data_rate / total_data_rate < 1
+* result is < available as rate / total_data_rate < 1
 */
plane_blocks = minimum[id];
-   plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
+   

[Intel-gfx] [PATCH 0/8] drm/i915/gen9+: Atomic wm fixes.

[Maarten Lankhorst]

This patch series applies on top of Lyude's patches.
They clean up the remainder of SKL style wm's, and finally makes
SKL watermarks ready for nonblocking modeset by using the crtc_state
for watermarks as much as possible.

Maarten Lankhorst (8):
  drm/i915/skl+: Prepare for removing data rate from skl watermark state
  drm/i915/skl+: Remove data_rate from watermark struct.
  drm/i915/skl+: Remove minimum block allocation from crtc state.
  drm/i915/skl+: Clean up minimum allocations.
  drm/i915: Add a atomic evasion step to watermark programming.
  drm/i915/gen9+: Use the watermarks from crtc_state for everything.
  drm/i915/gen9+: Program watermarks as a separate step during evasion
  drm/i915/gen9+: Preserve old allocation from crtc_state.

 drivers/gpu/drm/i915/i915_drv.h  |  13 +--
 drivers/gpu/drm/i915/intel_display.c |  58 --
 drivers/gpu/drm/i915/intel_drv.h |  16 ---
 drivers/gpu/drm/i915/intel_pm.c  | 206 +++
 drivers/gpu/drm/i915/intel_sprite.c  |  18 ---
 5 files changed, 136 insertions(+), 175 deletions(-)

-- 
2.7.4

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[Intel-gfx] [PATCH 5/8] drm/i915: Add a atomic evasion step to watermark programming.

[Maarten Lankhorst]

Allow the driver to write watermarks during atomic evasion.
This will make it possible to write the watermarks in a cleaner
way on gen9+.

Signed-off-by: Maarten Lankhorst 
---
 drivers/gpu/drm/i915/i915_drv.h  |  6 --
 drivers/gpu/drm/i915/intel_display.c | 18 --
 drivers/gpu/drm/i915/intel_pm.c  | 19 +--
 3 files changed, 29 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f65ccf9b0bea..09588c58148f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -484,6 +484,7 @@ struct sdvo_device_mapping {
 
 struct intel_connector;
 struct intel_encoder;
+struct intel_atomic_state;
 struct intel_crtc_state;
 struct intel_initial_plane_config;
 struct intel_crtc;
@@ -497,8 +498,9 @@ struct drm_i915_display_funcs {
int (*compute_intermediate_wm)(struct drm_device *dev,
   struct intel_crtc *intel_crtc,
   struct intel_crtc_state *newstate);
-   void (*initial_watermarks)(struct intel_crtc_state *cstate);
-   void (*optimize_watermarks)(struct intel_crtc_state *cstate);
+   void (*initial_watermarks)(struct intel_atomic_state *state, struct 
intel_crtc_state *cstate);
+   void (*atomic_evade_watermarks)(struct intel_atomic_state *state, 
struct intel_crtc_state *cstate);
+   void (*optimize_watermarks)(struct intel_atomic_state *state, struct 
intel_crtc_state *cstate);
int (*compute_global_watermarks)(struct drm_atomic_state *state);
void (*update_wm)(struct drm_crtc *crtc);
int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 55f8ec8c76ae..23d8c72dade3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5160,7 +5160,7 @@ static void intel_pre_plane_update(struct 
intel_crtc_state *old_crtc_state)
 * us to.
 */
if (dev_priv->display.initial_watermarks != NULL)
-   dev_priv->display.initial_watermarks(pipe_config);
+   
dev_priv->display.initial_watermarks(to_intel_atomic_state(old_state), 
pipe_config);
else if (pipe_config->update_wm_pre)
intel_update_watermarks(>base);
 }
@@ -5374,7 +5374,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state 
*pipe_config,
intel_color_load_luts(_config->base);
 
if (dev_priv->display.initial_watermarks != NULL)
-   dev_priv->display.initial_watermarks(intel_crtc->config);
+   
dev_priv->display.initial_watermarks(to_intel_atomic_state(old_state), 
intel_crtc->config);
intel_enable_pipe(intel_crtc);
 
if (intel_crtc->config->has_pch_encoder)
@@ -5480,7 +5480,7 @@ static void haswell_crtc_enable(struct intel_crtc_state 
*pipe_config,
intel_ddi_enable_transcoder_func(crtc);
 
if (dev_priv->display.initial_watermarks != NULL)
-   dev_priv->display.initial_watermarks(pipe_config);
+   
dev_priv->display.initial_watermarks(to_intel_atomic_state(old_state), 
pipe_config);
else
intel_update_watermarks(crtc);
 
@@ -14503,7 +14503,7 @@ static void intel_atomic_commit_tail(struct 
drm_atomic_state *state)
intel_cstate = to_intel_crtc_state(crtc->state);
 
if (dev_priv->display.optimize_watermarks)
-   dev_priv->display.optimize_watermarks(intel_cstate);
+   dev_priv->display.optimize_watermarks(intel_state, 
intel_cstate);
}
 
for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
@@ -14908,7 +14908,6 @@ static void intel_begin_crtc_commit(struct drm_crtc 
*crtc,
struct intel_crtc_state *old_intel_state =
to_intel_crtc_state(old_crtc_state);
bool modeset = needs_modeset(crtc->state);
-   enum pipe pipe = intel_crtc->pipe;
 
/* Perform vblank evasion around commit operation */
intel_pipe_update_start(intel_crtc);
@@ -14923,12 +14922,11 @@ static void intel_begin_crtc_commit(struct drm_crtc 
*crtc,
 
if (intel_cstate->update_pipe)
intel_update_pipe_config(intel_crtc, old_intel_state);
-   else if (INTEL_GEN(dev_priv) >= 9) {
+   else if (INTEL_GEN(dev_priv) >= 9)
skl_detach_scalers(intel_crtc);
 
-   I915_WRITE(PIPE_WM_LINETIME(pipe),
-  intel_cstate->wm.skl.optimal.linetime);
-   }
+   if (dev_priv->display.atomic_evade_watermarks)
+   
dev_priv->display.atomic_evade_watermarks(to_intel_atomic_state(old_crtc_state->state),
 intel_cstate);
 }
 
 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
@@ -16388,7 +16386,7 @@ retry:
struct intel_crtc_state *cs = 

[Intel-gfx] [PATCH 6/8] drm/i915/gen9+: Use the watermarks from crtc_state for everything.

[Maarten Lankhorst]

There's no need to keep a duplicate skl_pipe_wm around any more,
everything can be discovered from crtc_state, which we pass around
correctly now even in case of plane disable.

Signed-off-by: Maarten Lankhorst 
---
 drivers/gpu/drm/i915/intel_display.c |  2 +-
 drivers/gpu/drm/i915/intel_drv.h |  1 -
 drivers/gpu/drm/i915/intel_pm.c  | 11 +--
 3 files changed, 6 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 23d8c72dade3..340861826c46 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13455,7 +13455,7 @@ static void verify_wm_state(struct drm_crtc *crtc,
return;
 
skl_pipe_wm_get_hw_state(crtc, _wm);
-   sw_wm = _crtc->wm.active.skl;
+   sw_wm = _intel_crtc_state(new_state)->wm.skl.optimal;
 
skl_ddb_get_hw_state(dev_priv, _ddb);
sw_ddb = _priv->wm.skl_hw.ddb;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index a176e6cebab3..9f04e26c4365 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -723,7 +723,6 @@ struct intel_crtc {
/* watermarks currently being used  */
union {
struct intel_pipe_wm ilk;
-   struct skl_pipe_wm skl;
} active;
 
/* allow CxSR on this pipe */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 05ccd253fd7a..be3dd8cdc7ae 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3904,9 +3904,9 @@ bool skl_ddb_allocation_overlaps(struct drm_atomic_state 
*state,
 static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
  struct skl_ddb_allocation *ddb, /* out */
  struct skl_pipe_wm *pipe_wm, /* out */
+ const struct skl_pipe_wm *old_pipe_wm,
  bool *changed /* out */)
 {
-   struct intel_crtc *intel_crtc = to_intel_crtc(cstate->crtc);
struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
int ret;
 
@@ -3914,7 +3914,7 @@ static int skl_update_pipe_wm(struct drm_crtc_state 
*cstate,
if (ret)
return ret;
 
-   if (!memcmp(_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
+   if (!memcmp(old_pipe_wm, pipe_wm, sizeof(*pipe_wm)))
*changed = false;
else
*changed = true;
@@ -4155,10 +4155,12 @@ skl_compute_wm(struct drm_atomic_state *state)
for_each_crtc_in_state(state, crtc, cstate, i) {
struct intel_crtc_state *intel_cstate =
to_intel_crtc_state(cstate);
+   const struct skl_pipe_wm *old_pipe_wm =
+   _intel_crtc_state(crtc->state)->wm.skl.optimal;
 
pipe_wm = _cstate->wm.skl.optimal;
ret = skl_update_pipe_wm(cstate, >ddb, pipe_wm,
-);
+old_pipe_wm, );
if (ret)
return ret;
 
@@ -4203,8 +4205,6 @@ static void skl_update_wm(struct drm_crtc *crtc)
if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
return;
 
-   intel_crtc->wm.active.skl = *pipe_wm;
-
mutex_lock(_priv->wm.wm_mutex);
 
/*
@@ -4371,7 +4371,6 @@ void skl_wm_get_hw_state(struct drm_device *dev)
cstate = to_intel_crtc_state(crtc->state);
 
skl_pipe_wm_get_hw_state(crtc, >wm.skl.optimal);
-   intel_crtc->wm.active.skl = cstate->wm.skl.optimal;
 
if (!intel_crtc->active)
hw->dirty_pipes |= drm_crtc_mask(crtc);
-- 
2.7.4

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[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915: GMBUS don't need no forcewake

[Patchwork]

== Series Details ==

Series: drm/i915: GMBUS don't need no forcewake
URL   : https://patchwork.freedesktop.org/series/13641/
State : warning

== Summary ==

Series 13641v1 drm/i915: GMBUS don't need no forcewake
https://patchwork.freedesktop.org/api/1.0/series/13641/revisions/1/mbox/

Test drv_module_reload_basic:
pass   -> DMESG-WARN (fi-ilk-650)
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
dmesg-warn -> PASS   (fi-byt-j1900)
Test vgem_basic:
Subgroup unload:
skip   -> PASS   (fi-hsw-4770)

fi-bdw-5557u total:248  pass:232  dwarn:0   dfail:0   fail:0   skip:16 
fi-bsw-n3050 total:248  pass:205  dwarn:0   dfail:0   fail:0   skip:43 
fi-bxt-t5700 total:248  pass:217  dwarn:0   dfail:0   fail:0   skip:31 
fi-byt-j1900 total:248  pass:214  dwarn:1   dfail:0   fail:1   skip:32 
fi-byt-n2820 total:248  pass:211  dwarn:0   dfail:0   fail:1   skip:36 
fi-hsw-4770  total:248  pass:225  dwarn:0   dfail:0   fail:0   skip:23 
fi-hsw-4770r total:248  pass:225  dwarn:0   dfail:0   fail:0   skip:23 
fi-ilk-650   total:248  pass:184  dwarn:1   dfail:0   fail:2   skip:61 
fi-ivb-3520m total:248  pass:222  dwarn:0   dfail:0   fail:0   skip:26 
fi-ivb-3770  total:248  pass:222  dwarn:0   dfail:0   fail:0   skip:26 
fi-kbl-7200u total:248  pass:223  dwarn:0   dfail:0   fail:0   skip:25 
fi-skl-6260u total:248  pass:233  dwarn:0   dfail:0   fail:0   skip:15 
fi-skl-6700hqtotal:248  pass:225  dwarn:0   dfail:0   fail:0   skip:23 
fi-skl-6700k total:248  pass:222  dwarn:1   dfail:0   fail:0   skip:25 
fi-skl-6770hqtotal:248  pass:231  dwarn:1   dfail:0   fail:1   skip:15 
fi-snb-2520m total:248  pass:211  dwarn:0   dfail:0   fail:0   skip:37 
fi-snb-2600  total:248  pass:210  dwarn:0   dfail:0   fail:0   skip:38 

Results at /archive/results/CI_IGT_test/Patchwork_2685/

46271d41e30090d7fc996e8f5abde6a59f51038b drm-intel-nightly: 
2016y-10m-12d-11h-06m-41s UTC integration manifest
3d9fd0b drm/i915: GMBUS don't need no forcewake

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Re: [Intel-gfx] [PATCH 09/19] drm/i915: Make IS_BROADWELL only take dev_priv

[David Weinehall]

On Tue, Oct 11, 2016 at 02:21:42PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin 
> 
> Saves 1808 bytes of .rodata strings.
> 
> v2: Add parantheses around dev_priv. (Ville Syrjala)
> 
> Signed-off-by: Tvrtko Ursulin 

Reviewed-by: David Weinehall 

> ---
>  drivers/gpu/drm/i915/i915_drv.c |  6 --
>  drivers/gpu/drm/i915/i915_drv.h |  6 +++---
>  drivers/gpu/drm/i915/i915_gem.c |  5 +++--
>  drivers/gpu/drm/i915/i915_gem_gtt.c |  2 +-
>  drivers/gpu/drm/i915/intel_color.c  |  4 ++--
>  drivers/gpu/drm/i915/intel_display.c| 21 +++--
>  drivers/gpu/drm/i915/intel_dp.c | 19 ++-
>  drivers/gpu/drm/i915/intel_pm.c | 20 +++-
>  drivers/gpu/drm/i915/intel_psr.c|  4 ++--
>  drivers/gpu/drm/i915/intel_runtime_pm.c |  3 +--
>  drivers/gpu/drm/i915/intel_sprite.c |  8 
>  11 files changed, 52 insertions(+), 46 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index f6ba8f262238..8899835fffab 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -189,13 +189,15 @@ static void intel_detect_pch(struct drm_device *dev)
>   } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
>   dev_priv->pch_type = PCH_LPT;
>   DRM_DEBUG_KMS("Found LynxPoint PCH\n");
> - WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
> + WARN_ON(!IS_HASWELL(dev_priv) &&
> + !IS_BROADWELL(dev_priv));
>   WARN_ON(IS_HSW_ULT(dev_priv) ||
>   IS_BDW_ULT(dev_priv));
>   } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
>   dev_priv->pch_type = PCH_LPT;
>   DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
> - WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
> + WARN_ON(!IS_HASWELL(dev_priv) &&
> + !IS_BROADWELL(dev_priv));
>   WARN_ON(!IS_HSW_ULT(dev_priv) &&
>   !IS_BDW_ULT(dev_priv));
>   } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 3f321932d18a..13e409554fcc 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2662,7 +2662,7 @@ struct drm_i915_cmd_table {
>  #define IS_VALLEYVIEW(dev)   (INTEL_INFO(dev)->is_valleyview)
>  #define IS_CHERRYVIEW(dev)   (INTEL_INFO(dev)->is_cherryview)
>  #define IS_HASWELL(dev)  (INTEL_INFO(dev)->is_haswell)
> -#define IS_BROADWELL(dev)(INTEL_INFO(dev)->is_broadwell)
> +#define IS_BROADWELL(dev_priv)   ((dev_priv)->info.is_broadwell)
>  #define IS_SKYLAKE(dev)  (INTEL_INFO(dev)->is_skylake)
>  #define IS_BROXTON(dev)  (INTEL_INFO(dev)->is_broxton)
>  #define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake)
> @@ -2769,8 +2769,8 @@ struct drm_i915_cmd_table {
>  #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
>  #define HAS_SNOOP(dev)   (INTEL_INFO(dev)->has_snoop)
>  #define HAS_EDRAM(dev)   (!!(__I915__(dev)->edram_cap & 
> EDRAM_ENABLED))
> -#define HAS_WT(dev)  ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
> -  HAS_EDRAM(dev))
> +#define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
> +  IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
>  #define HWS_NEEDS_PHYSICAL(dev)  (INTEL_INFO(dev)->hws_needs_physical)
>  
>  #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->has_hw_contexts)
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 6da841500510..aefb88f987b2 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -3473,7 +3473,7 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev, 
> void *data,
>   level = I915_CACHE_LLC;
>   break;
>   case I915_CACHING_DISPLAY:
> - level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
> + level = HAS_WT(dev_priv) ? I915_CACHE_WT : I915_CACHE_NONE;
>   break;
>   default:
>   return -EINVAL;
> @@ -3531,7 +3531,8 @@ i915_gem_object_pin_to_display_plane(struct 
> drm_i915_gem_object *obj,
>* with that bit in the PTE to main memory with just one PIPE_CONTROL.
>*/
>   ret = i915_gem_object_set_cache_level(obj,
> -   HAS_WT(obj->base.dev) ? 
> I915_CACHE_WT : I915_CACHE_NONE);
> +   HAS_WT(to_i915(obj->base.dev)) ?

Re: [Intel-gfx] [RFC i-g-t PATCH 2/3] igt/gem_wait: Use new igt_dummyload api

[Chris Wilson]

On Wed, Oct 12, 2016 at 02:59:53PM +0300, Abdiel Janulgue wrote:
> Signed-off-by: Abdiel Janulgue 
> ---
>  tests/gem_wait.c | 77 
> +---
>  1 file changed, 12 insertions(+), 65 deletions(-)

We can do so much better than a dummy load here. We can precisely
control how long we want the object to be busy by using a recursive
batch buffer (and terminating that batch at the exact moment we require).
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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[Intel-gfx] [RFC i-g-t PATCH 2/3] igt/gem_wait: Use new igt_dummyload api

[Abdiel Janulgue]

Signed-off-by: Abdiel Janulgue 
---
 tests/gem_wait.c | 77 +---
 1 file changed, 12 insertions(+), 65 deletions(-)

diff --git a/tests/gem_wait.c b/tests/gem_wait.c
index 461efdb..24a5f5e 100644
--- a/tests/gem_wait.c
+++ b/tests/gem_wait.c
@@ -54,36 +54,6 @@
 #define BUF_PAGES ((8<<20)>>12)
 drm_intel_bo *dst, *dst2;
 
-/* returns time diff in milliseconds */
-static int64_t
-do_time_diff(struct timespec *end, struct timespec *start)
-{
-   int64_t ret;
-   ret = (MSEC_PER_SEC * difftime(end->tv_sec, start->tv_sec)) +
- ((end->tv_nsec/NSEC_PER_MSEC) - (start->tv_nsec/NSEC_PER_MSEC));
-   return ret;
-}
-
-static void blt_color_fill(struct intel_batchbuffer *batch,
-  drm_intel_bo *buf,
-  const unsigned int pages)
-{
-   const unsigned short height = pages/4;
-   const unsigned short width =  4096;
-
-   COLOR_BLIT_COPY_BATCH_START(COLOR_BLT_WRITE_ALPHA |
-   XY_COLOR_BLT_WRITE_RGB);
-   OUT_BATCH((3 << 24) | /* 32 Bit Color */
- (0xF0 << 16)  | /* Raster OP copy background register */
- 0); /* Dest pitch is 0 */
-   OUT_BATCH(0);
-   OUT_BATCH(width << 16   |
- height);
-   OUT_RELOC_FENCED(buf, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 
0);
-   OUT_BATCH(rand()); /* random pattern */
-   ADVANCE_BATCH();
-}
-
 static void render_timeout(int fd)
 {
drm_intel_bufmgr *bufmgr;
@@ -91,10 +61,11 @@ static void render_timeout(int fd)
int64_t timeout = ENOUGH_WORK_IN_SECONDS * NSEC_PER_SEC;
int64_t negative_timeout = -1;
int ret;
+   const unsigned short height = BUF_PAGES/4;
+   const unsigned short width =  4096;
const bool do_signals = true; /* signals will seem to make the operation
   * use less process CPU time */
-   bool done = false;
-   int i, iter = 1;
+   int iter = 1;
 
igt_skip_on_simulation();
 
@@ -112,30 +83,9 @@ static void render_timeout(int fd)
/* Figure out a rough number of fills required to consume 1 second of
 * GPU work.
 */
-   do {
-   struct timespec start, end;
-   long diff;
-
-#ifndef CLOCK_MONOTONIC_RAW
-#define CLOCK_MONOTONIC_RAW CLOCK_MONOTONIC
-#endif
-
-   igt_assert(clock_gettime(CLOCK_MONOTONIC_RAW, ) == 0);
-   for (i = 0; i < iter; i++)
-   blt_color_fill(batch, dst, BUF_PAGES);
-   intel_batchbuffer_flush(batch);
-   drm_intel_bo_wait_rendering(dst);
-   igt_assert(clock_gettime(CLOCK_MONOTONIC_RAW, ) == 0);
-
-   diff = do_time_diff(, );
-   igt_assert(diff >= 0);
-
-   if ((diff / MSEC_PER_SEC) > ENOUGH_WORK_IN_SECONDS)
-   done = true;
-   else
-   iter <<= 1;
-   } while (!done && iter < 100);
-
+   iter = igt_calibrate_dummy_load(bufmgr, batch, fd,
+   dst->handle, 0,
+   width, height, 1, IGT_DUMMY_BLIT_FILL);
igt_assert_lt(iter, 100);
 
igt_debug("%d iters is enough work\n", iter);
@@ -146,10 +96,9 @@ static void render_timeout(int fd)
/* We should be able to do half as much work in the same amount of time,
 * but because we might schedule almost twice as much as required, we
 * might accidentally time out. Hence add some fudge. */
-   for (i = 0; i < iter/3; i++)
-   blt_color_fill(batch, dst2, BUF_PAGES);
 
-   intel_batchbuffer_flush(batch);
+   igt_emit_dummy_load(bufmgr, batch, fd, dst2->handle, 0,
+   width, height, iter/3, 0, IGT_DUMMY_BLIT_FILL);
igt_assert(gem_bo_busy(fd, dst2->handle) == true);
 
igt_assert_eq(gem_wait(fd, dst2->handle, ), 0);
@@ -168,10 +117,9 @@ static void render_timeout(int fd)
/* Now check that we correctly time out, twice the auto-tune load should
 * be good enough. */
timeout = ENOUGH_WORK_IN_SECONDS * NSEC_PER_SEC;
-   for (i = 0; i < iter*2; i++)
-   blt_color_fill(batch, dst2, BUF_PAGES);
 
-   intel_batchbuffer_flush(batch);
+   igt_emit_dummy_load(bufmgr, batch, fd, dst2->handle, 0,
+   width, height, iter*2, 0, IGT_DUMMY_BLIT_FILL);
 
ret = gem_wait(fd, dst2->handle, );
igt_assert_eq(ret, -ETIME);
@@ -186,10 +134,9 @@ static void render_timeout(int fd)
 
/* Now check that we can pass negative (infinite) timeouts. */
negative_timeout = -1;
-   for (i = 0; i < iter; i++)
-   blt_color_fill(batch, dst2, BUF_PAGES);
 
-   intel_batchbuffer_flush(batch);
+   igt_emit_dummy_load(bufmgr, batch, fd, 

[Intel-gfx] [RFC i-g-t PATCH 1/3] lib: add igt_dummyload

[Abdiel Janulgue]

Generalized from auto-tuned GPU dummy workload in gem_wait and kms_flip

Signed-off-by: Abdiel Janulgue 
---
 lib/Makefile.sources |   2 +
 lib/igt.h|   1 +
 lib/igt_dummyload.c  | 419 +++
 lib/igt_dummyload.h  |  63 
 4 files changed, 485 insertions(+)
 create mode 100644 lib/igt_dummyload.c
 create mode 100644 lib/igt_dummyload.h

diff --git a/lib/Makefile.sources b/lib/Makefile.sources
index e8e277b..7fc5ec2 100644
--- a/lib/Makefile.sources
+++ b/lib/Makefile.sources
@@ -75,6 +75,8 @@ lib_source_list = \
igt_draw.h  \
igt_pm.c\
igt_pm.h\
+   igt_dummyload.c \
+   igt_dummyload.h \
uwildmat/uwildmat.h \
uwildmat/uwildmat.c \
$(NULL)
diff --git a/lib/igt.h b/lib/igt.h
index d751f24..a0028d5 100644
--- a/lib/igt.h
+++ b/lib/igt.h
@@ -32,6 +32,7 @@
 #include "igt_core.h"
 #include "igt_debugfs.h"
 #include "igt_draw.h"
+#include "igt_dummyload.h"
 #include "igt_fb.h"
 #include "igt_gt.h"
 #include "igt_kms.h"
diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c
new file mode 100644
index 000..908d839
--- /dev/null
+++ b/lib/igt_dummyload.c
@@ -0,0 +1,419 @@
+/*
+ * Copyright © 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "igt.h"
+#include "igt_dummyload.h"
+#include 
+
+/**
+ * SECTION:igt_dummyload
+ * @short_description: Library for submitting auto-tuned dummy GPU workloads
+ * @title: Dummyload
+ * @include: igt.h
+ *
+ * A lot of igt testcases need some dummy load to make sure a race window is
+ * big enough. Unfortunately having a fixed amount of workload leads to
+ * spurious test failures or overtly long runtimes on some fast/slow platforms.
+ * This library contains functionality to submit GPU workloads that is
+ * dynamically tuned to consume a specific amount of time.
+ */
+
+#define USEC_PER_SEC 100L
+#define NSEC_PER_SEC 10L
+
+/* Internal data structures to avoid having to pass tons of parameters
+ * around. */
+struct dummy_info {
+   drm_intel_bufmgr *bufmgr;
+   struct intel_batchbuffer *batch;
+   int drm_fd;
+   uint32_t buf_handle;
+   uint32_t buf_stride;
+   uint32_t buf_tiling;
+   int fb_width;
+   int fb_height;
+};
+
+static void blit_copy(struct intel_batchbuffer *batch,
+ drm_intel_bo *dst, drm_intel_bo *src,
+ unsigned int width, unsigned int height,
+ unsigned int dst_pitch, unsigned int src_pitch)
+{
+   BLIT_COPY_BATCH_START(0);
+   OUT_BATCH((3 << 24) | /* 32 bits */
+ (0xcc << 16) | /* copy ROP */
+ dst_pitch);
+   OUT_BATCH(0 << 16 | 0);
+   OUT_BATCH(height << 16 | width);
+   OUT_RELOC_FENCED(dst, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 
0);
+   OUT_BATCH(0 << 16 | 0);
+   OUT_BATCH(src_pitch);
+   OUT_RELOC_FENCED(src, I915_GEM_DOMAIN_RENDER, 0, 0);
+   ADVANCE_BATCH();
+
+   if (batch->gen >= 6) {
+   BEGIN_BATCH(3, 0);
+   OUT_BATCH(XY_SETUP_CLIP_BLT_CMD);
+   OUT_BATCH(0);
+   OUT_BATCH(0);
+   ADVANCE_BATCH();
+   }
+}
+
+static void blit_fill(struct intel_batchbuffer *batch, drm_intel_bo *dst,
+ unsigned int width, unsigned int height)
+{
+   COLOR_BLIT_COPY_BATCH_START(COLOR_BLT_WRITE_ALPHA |
+   XY_COLOR_BLT_WRITE_RGB);
+   OUT_BATCH((3 << 24) | /* 32 Bit Color */
+ (0xF0 << 16)  | /* Raster OP copy background register */
+ 0); /* Dest pitch is 0 */
+   OUT_BATCH(0);
+   OUT_BATCH(width << 16   |
+ height);
+   OUT_RELOC_FENCED(dst, 

[Intel-gfx] [RFC i-g-t PATCH 3/3] igt/kms_flip: Use new igt_dummyload api

[Abdiel Janulgue]

Signed-off-by: Abdiel Janulgue 
---
 tests/kms_flip.c | 191 +++
 1 file changed, 10 insertions(+), 181 deletions(-)

diff --git a/tests/kms_flip.c b/tests/kms_flip.c
index 065ad66..93cf391 100644
--- a/tests/kms_flip.c
+++ b/tests/kms_flip.c
@@ -187,109 +187,6 @@ static unsigned long gettime_us(void)
return ts.tv_sec * 100 + ts.tv_nsec / 1000;
 }
 
-static int calibrate_dummy_load(struct test_output *o,
-   const char *ring_name,
-   int (*emit)(struct test_output *o, int limit, 
int timeout))
-{
-   unsigned long start;
-   int ops = 1;
-
-   start = gettime_us();
-
-   do {
-   unsigned long diff;
-   int ret;
-
-   ret = emit(o, (ops+1)/2, 10);
-   diff = gettime_us() - start;
-
-   if (ret || diff / USEC_PER_SEC >= 1)
-   break;
-
-   ops += ops;
-   } while (ops < 10);
-
-   igt_debug("%s dummy load calibrated: %d operations / second\n",
- ring_name, ops);
-
-   return ops;
-}
-
-static void blit_copy(drm_intel_bo *dst, drm_intel_bo *src,
- unsigned int width, unsigned int height,
- unsigned int dst_pitch, unsigned int src_pitch)
-{
-   BLIT_COPY_BATCH_START(0);
-   OUT_BATCH((3 << 24) | /* 32 bits */
- (0xcc << 16) | /* copy ROP */
- dst_pitch);
-   OUT_BATCH(0 << 16 | 0);
-   OUT_BATCH(height << 16 | width);
-   OUT_RELOC_FENCED(dst, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 
0);
-   OUT_BATCH(0 << 16 | 0);
-   OUT_BATCH(src_pitch);
-   OUT_RELOC_FENCED(src, I915_GEM_DOMAIN_RENDER, 0, 0);
-   ADVANCE_BATCH();
-
-   if (batch->gen >= 6) {
-   BEGIN_BATCH(3, 0);
-   OUT_BATCH(XY_SETUP_CLIP_BLT_CMD);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   ADVANCE_BATCH();
-   }
-}
-
-static int _emit_dummy_load__bcs(struct test_output *o, int limit, int timeout)
-{
-   int i, ret = 0;
-   drm_intel_bo *src_bo, *dst_bo, *fb_bo;
-   struct igt_fb *fb_info = >fb_info[o->current_fb_id];
-
-   igt_require(bufmgr);
-
-   src_bo = drm_intel_bo_alloc(bufmgr, "dummy_bo", 2048*2048*4, 4096);
-   igt_assert(src_bo);
-
-   dst_bo = drm_intel_bo_alloc(bufmgr, "dummy_bo", 2048*2048*4, 4096);
-   igt_assert(dst_bo);
-
-   fb_bo = gem_handle_to_libdrm_bo(bufmgr, drm_fd, "imported", 
fb_info->gem_handle);
-   igt_assert(fb_bo);
-
-   for (i = 0; i < limit; i++) {
-   blit_copy(dst_bo, src_bo,
- 2048, 2048,
- 2048*4, 2048*4);
-
-   igt_swap(src_bo, dst_bo);
-   }
-   blit_copy(fb_bo, src_bo,
- min(o->fb_width, 2048), min(o->fb_height, 2048),
- fb_info->stride, 2048*4);
-   intel_batchbuffer_flush(batch);
-
-   if (timeout > 0)
-   ret = drm_intel_gem_bo_wait(fb_bo, timeout * NSEC_PER_SEC);
-
-   drm_intel_bo_unreference(src_bo);
-   drm_intel_bo_unreference(dst_bo);
-   drm_intel_bo_unreference(fb_bo);
-
-   return ret;
-}
-
-static void emit_dummy_load__bcs(struct test_output *o, int seconds)
-{
-   static int ops_per_sec;
-
-   if (ops_per_sec == 0)
-   ops_per_sec = calibrate_dummy_load(o, "bcs",
-  _emit_dummy_load__bcs);
-
-   _emit_dummy_load__bcs(o, seconds * ops_per_sec, 0);
-}
-
 static void emit_fence_stress(struct test_output *o)
 {
const int num_fences = gem_available_fences(drm_fd);
@@ -334,82 +231,6 @@ static void emit_fence_stress(struct test_output *o)
free(exec);
 }
 
-static int _emit_dummy_load__rcs(struct test_output *o, int limit, int timeout)
-{
-   const struct igt_fb *fb_info = >fb_info[o->current_fb_id];
-   igt_render_copyfunc_t copyfunc;
-   struct igt_buf sb[3], *src, *dst, *fb;
-   int i, ret = 0;
-
-   igt_require(bufmgr);
-
-   copyfunc = igt_get_render_copyfunc(devid);
-   if (copyfunc == NULL)
-   return _emit_dummy_load__bcs(o, limit, timeout);
-
-   sb[0].bo = drm_intel_bo_alloc(bufmgr, "dummy_bo", 2048*2048*4, 4096);
-   igt_assert(sb[0].bo);
-   sb[0].size = sb[0].bo->size;
-   sb[0].tiling = I915_TILING_NONE;
-   sb[0].data = NULL;
-   sb[0].num_tiles = sb[0].bo->size;
-   sb[0].stride = 4 * 2048;
-
-   sb[1].bo = drm_intel_bo_alloc(bufmgr, "dummy_bo", 2048*2048*4, 4096);
-   igt_assert(sb[1].bo);
-   sb[1].size = sb[1].bo->size;
-   sb[1].tiling = I915_TILING_NONE;
-   sb[1].data = NULL;
-   sb[1].num_tiles = sb[1].bo->size;
-   sb[1].stride = 4 * 2048;
-
-   sb[2].bo = gem_handle_to_libdrm_bo(bufmgr, drm_fd, "imported", 
fb_info->gem_handle);
-   

[Intel-gfx] [RFC i-g-t] Extract autotuned dummy load into lib

[Abdiel Janulgue]

A lot of igt testcases need some dummy load to make sure a race
window is big enough. Unfortunately having a fixed amount of
workload leads to spurious test failures or overtly long runtimes
on some fast/slow platforms. This library contains functionality
to submit GPU workloads that is dynamically tuned to consume a
specific amount of time.

This functionality is generalized to lib from existing features in
gem_wait and kms_flip. In the future, we could update test cases
that could benefit from auto-tuned dummy workloads to use this
new api.

Abdiel Janulgue (3):
  lib: add igt_dummyload
  igt/gem_wait: Use new igt_dummyload api
  igt/kms_flip: Use new igt_dummyload api

 lib/Makefile.sources |   2 +
 lib/igt.h|   1 +
 lib/igt_dummyload.c  | 419 +++
 lib/igt_dummyload.h  |  63 ++
 tests/gem_wait.c |  77 ++-
 tests/kms_flip.c | 191 +-
 6 files changed, 507 insertions(+), 246 deletions(-)

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Re: [Intel-gfx] [PATCH 13/19] drm/i915: Make IS_BROXTON only take dev_priv

[Tvrtko Ursulin]

On 12/10/2016 12:52, David Weinehall wrote:

On Tue, Oct 11, 2016 at 02:21:46PM +0100, Tvrtko Ursulin wrote:

From: Tvrtko Ursulin 

Saves 1392 bytes of .rodata strings.

v2: Add parantheses around dev_priv. (Ville Syrjala)

Signed-off-by: Tvrtko Ursulin 

This patch does quite a bit more than just change IS_BROXTON to use
dev_priv...


Some cascade effects on function prototypes here and there - if you find 
it objectionable I can try to eliminate or at least minimise?


Regards,

Tvrtko


---
  drivers/gpu/drm/i915/i915_drv.c |  2 +-
  drivers/gpu/drm/i915/i915_drv.h |  5 +++--
  drivers/gpu/drm/i915/i915_gem_gtt.c | 40 +
  drivers/gpu/drm/i915/i915_irq.c |  2 +-
  drivers/gpu/drm/i915/intel_ddi.c|  4 ++--
  drivers/gpu/drm/i915/intel_display.c| 31 ++---
  drivers/gpu/drm/i915/intel_dp.c | 16 ++---
  drivers/gpu/drm/i915/intel_dpll_mgr.c   |  2 +-
  drivers/gpu/drm/i915/intel_dsi.c| 27 +++---
  drivers/gpu/drm/i915/intel_dsi_pll.c| 26 ++---
  drivers/gpu/drm/i915/intel_guc_loader.c |  8 +++
  drivers/gpu/drm/i915/intel_hdmi.c   |  6 ++---
  drivers/gpu/drm/i915/intel_runtime_pm.c |  2 +-
  13 files changed, 89 insertions(+), 82 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index d854ea4a7e92..18af6d1ccec9 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2437,7 +2437,7 @@ static int intel_runtime_resume(struct device *kdev)
if (IS_GEN6(dev_priv))
intel_init_pch_refclk(dev);
  
-	if (IS_BROXTON(dev)) {

+   if (IS_BROXTON(dev_priv)) {
bxt_disable_dc9(dev_priv);
bxt_display_core_init(dev_priv, true);
if (dev_priv->csr.dmc_payload &&
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9784e61400e5..ad9299196d13 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2664,7 +2664,7 @@ struct drm_i915_cmd_table {
  #define IS_HASWELL(dev_priv)  ((dev_priv)->info.is_haswell)
  #define IS_BROADWELL(dev_priv)((dev_priv)->info.is_broadwell)
  #define IS_SKYLAKE(dev_priv)  ((dev_priv)->info.is_skylake)
-#define IS_BROXTON(dev)(INTEL_INFO(dev)->is_broxton)
+#define IS_BROXTON(dev_priv)   ((dev_priv)->info.is_broxton)
  #define IS_KABYLAKE(dev_priv) ((dev_priv)->info.is_kabylake)
  #define IS_MOBILE(dev)(INTEL_INFO(dev)->is_mobile)
  #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
@@ -2724,7 +2724,8 @@ struct drm_i915_cmd_table {
  #define BXT_REVID_B0  0x3
  #define BXT_REVID_C0  0x9
  
-#define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))

+#define IS_BXT_REVID(dev_priv, since, until) \
+   (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
  
  #define KBL_REVID_A0		0x0

  #define KBL_REVID_B0  0x1
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index cf43a5632961..e628691fe97e 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -373,27 +373,29 @@ static void *kmap_page_dma(struct i915_page_dma *p)
  /* We use the flushing unmap only with ppgtt structures:
   * page directories, page tables and scratch pages.
   */
-static void kunmap_page_dma(struct drm_device *dev, void *vaddr)
+static void kunmap_page_dma(struct drm_i915_private *dev_priv, void *vaddr)
  {
/* There are only few exceptions for gen >=6. chv and bxt.
 * And we are not sure about the latter so play safe for now.
 */
-   if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
+   if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
drm_clflush_virt_range(vaddr, PAGE_SIZE);
  
  	kunmap_atomic(vaddr);

  }
  
  #define kmap_px(px) kmap_page_dma(px_base(px))

-#define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, (vaddr))
+#define kunmap_px(ppgtt, vaddr) \
+   kunmap_page_dma(to_i915((ppgtt)->base.dev), (vaddr))
  
  #define setup_px(dev, px) setup_page_dma((dev), px_base(px))

  #define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px))
-#define fill_px(dev, px, v) fill_page_dma((dev), px_base(px), (v))
-#define fill32_px(dev, px, v) fill_page_dma_32((dev), px_base(px), (v))
+#define fill_px(dev_priv, px, v) fill_page_dma((dev_priv), px_base(px), (v))
+#define fill32_px(dev_priv, px, v) \
+   fill_page_dma_32((dev_priv), px_base(px), (v))
  
-static void fill_page_dma(struct drm_device *dev, struct i915_page_dma *p,

- const uint64_t val)
+static void fill_page_dma(struct drm_i915_private *dev_priv,
+ struct i915_page_dma *p, const uint64_t val)
  {
int i;
uint64_t * const vaddr = 

Re: [Intel-gfx] [PATCH] drm/i915: GMBUS don't need no forcewake

[Chris Wilson]

On Wed, Oct 12, 2016 at 02:44:47PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä 
> 
> GMBUS is part of the display engine, and thus has no need for
> forcewake. Let's not bother trying to grab it then.
> 
> I don't recall if the display engine suffers from system hangs
> due to multiple accesses to the same "cacheline" in mmio space.
> I hope not since we're no longer protected by the uncore lock
> since commit 4e6c2d58ba86 ("drm/i915: Take forcewake once for
> the entire GMBUS transaction")

Only applies to concurrent access to the same cacheline, in this case
should be serialised by the mutex around the gmbus xfer.
 
> Cc: Chris Wilson 
> Cc: David Weinehall 
> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/intel_i2c.c | 5 -
>  1 file changed, 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_i2c.c 
> b/drivers/gpu/drm/i915/intel_i2c.c
> index 79aab9ad6faa..49c7824a4c29 100644
> --- a/drivers/gpu/drm/i915/intel_i2c.c
> +++ b/drivers/gpu/drm/i915/intel_i2c.c
> @@ -468,13 +468,9 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct 
> i2c_msg *msgs, int num)
>  struct intel_gmbus,
>  adapter);
>   struct drm_i915_private *dev_priv = bus->dev_priv;
> - const unsigned int fw =
> - intel_uncore_forcewake_for_reg(dev_priv, GMBUS0,
> -FW_REG_READ | FW_REG_WRITE);
>   int i = 0, inc, try = 0;
>   int ret = 0;

I915_WARN_ON(intel_uncore_forcewake_for_reg(dev_priv, GMBUS0,
FW_REG_READ |
FW_REG_WRITE));

? Would be good to test the fw handling as well.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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[Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [1/5] drm/i915: Use fence_write() from rpm resume

[Patchwork]

== Series Details ==

Series: series starting with [1/5] drm/i915: Use fence_write() from rpm resume
URL   : https://patchwork.freedesktop.org/series/13636/
State : warning

== Summary ==

Series 13636v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/13636/revisions/1/mbox/

Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
pass   -> DMESG-WARN (fi-skl-6700k)
Subgroup suspend-read-crc-pipe-b:
dmesg-warn -> PASS   (fi-byt-j1900)
Test vgem_basic:
Subgroup unload:
skip   -> PASS   (fi-hsw-4770)

fi-bdw-5557u total:248  pass:232  dwarn:0   dfail:0   fail:0   skip:16 
fi-bsw-n3050 total:248  pass:205  dwarn:0   dfail:0   fail:0   skip:43 
fi-bxt-t5700 total:248  pass:217  dwarn:0   dfail:0   fail:0   skip:31 
fi-byt-j1900 total:248  pass:214  dwarn:1   dfail:0   fail:1   skip:32 
fi-byt-n2820 total:248  pass:211  dwarn:0   dfail:0   fail:1   skip:36 
fi-hsw-4770  total:248  pass:225  dwarn:0   dfail:0   fail:0   skip:23 
fi-hsw-4770r total:248  pass:225  dwarn:0   dfail:0   fail:0   skip:23 
fi-ilk-650   total:248  pass:185  dwarn:0   dfail:0   fail:2   skip:61 
fi-ivb-3520m total:248  pass:222  dwarn:0   dfail:0   fail:0   skip:26 
fi-ivb-3770  total:248  pass:222  dwarn:0   dfail:0   fail:0   skip:26 
fi-kbl-7200u total:248  pass:223  dwarn:0   dfail:0   fail:0   skip:25 
fi-skl-6260u total:248  pass:233  dwarn:0   dfail:0   fail:0   skip:15 
fi-skl-6700hqtotal:248  pass:225  dwarn:0   dfail:0   fail:0   skip:23 
fi-skl-6700k total:248  pass:221  dwarn:2   dfail:0   fail:0   skip:25 
fi-skl-6770hqtotal:248  pass:231  dwarn:1   dfail:0   fail:1   skip:15 
fi-snb-2520m total:248  pass:211  dwarn:0   dfail:0   fail:0   skip:37 
fi-snb-2600  total:248  pass:210  dwarn:0   dfail:0   fail:0   skip:38 

Results at /archive/results/CI_IGT_test/Patchwork_2682/

46271d41e30090d7fc996e8f5abde6a59f51038b drm-intel-nightly: 
2016y-10m-12d-11h-06m-41s UTC integration manifest
e4a3f83 drm/i915: Remove superfluous locking around userfault_list
1cacb0e drm/i915: Use RPM as the barrier for controlling user mmap access
8092cc0 drm/i915: Move user fault tracking to a separate list
9b29980 drm/i915: Update debugfs describe_obj() to show fault-mappable
42b8e6b drm/i915: Use fence_write() from rpm resume

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Re: [Intel-gfx] [PATCH 20/42] drm/i915: Implement pread without struct-mutex

[Joonas Lahtinen]

On pe, 2016-10-07 at 10:46 +0100, Chris Wilson wrote:
> @@ -871,7 +845,7 @@ shmem_clflush_swizzled_range(char *addr, unsigned long 
> length,
>  /* Only difference to the fast-path function is that this can handle bit17
>   * and uses non-atomic copy and kmap functions. */
>  static int
> -shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
> +shmem_pread_slow(struct page *page, int offset, int length,

Lets maybe call this shmem_pread_cpu? I understand it's been faster on
recent generations even for swizzling. Can be added as follow-up.

> +static int
> +i915_gem_shmem_pread(struct drm_i915_gem_object *obj,
> +  struct drm_i915_gem_pread *args)
> +{
> + char __user *user_data;
> + u64 remain;
> + unsigned int obj_do_bit17_swizzling;
> + unsigned int needs_clflush;
> + unsigned int idx, offset;
> + int ret;
> +
> + obj_do_bit17_swizzling = 0;
> + if (i915_gem_object_needs_bit17_swizzle(obj))
> + obj_do_bit17_swizzling = 1 << 17;

Could use BIT(17) to make it super explicit.

Reviewed-by: Joonas Lahtinen 

Regards, Joonas

PS. Something like C context-aware diff would be super, would make
reading these much more fun. Or maybe patchwork 2-way diff view.
-- 
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915: Fix misplaced '\n' in printing the GPU error's RING_HEAD

[Patchwork]

== Series Details ==

Series: drm/i915: Fix misplaced '\n' in printing the GPU error's RING_HEAD
URL   : https://patchwork.freedesktop.org/series/13639/
State : warning

== Summary ==

Series 13639v1 drm/i915: Fix misplaced '
' in printing the GPU error's RING_HEAD
https://patchwork.freedesktop.org/api/1.0/series/13639/revisions/1/mbox/

Test kms_flip:
Subgroup basic-flip-vs-modeset:
pass   -> DMESG-WARN (fi-skl-6770hq)
Test kms_pipe_crc_basic:
Subgroup nonblocking-crc-pipe-b-frame-sequence:
pass   -> DMESG-WARN (fi-ilk-650)
Test vgem_basic:
Subgroup unload:
skip   -> PASS   (fi-hsw-4770)

fi-bdw-5557u total:248  pass:232  dwarn:0   dfail:0   fail:0   skip:16 
fi-bsw-n3050 total:248  pass:205  dwarn:0   dfail:0   fail:0   skip:43 
fi-bxt-t5700 total:248  pass:217  dwarn:0   dfail:0   fail:0   skip:31 
fi-byt-j1900 total:248  pass:213  dwarn:2   dfail:0   fail:1   skip:32 
fi-byt-n2820 total:248  pass:211  dwarn:0   dfail:0   fail:1   skip:36 
fi-hsw-4770  total:248  pass:225  dwarn:0   dfail:0   fail:0   skip:23 
fi-hsw-4770r total:248  pass:225  dwarn:0   dfail:0   fail:0   skip:23 
fi-ilk-650   total:248  pass:184  dwarn:1   dfail:0   fail:2   skip:61 
fi-ivb-3520m total:248  pass:222  dwarn:0   dfail:0   fail:0   skip:26 
fi-ivb-3770  total:248  pass:222  dwarn:0   dfail:0   fail:0   skip:26 
fi-kbl-7200u total:248  pass:223  dwarn:0   dfail:0   fail:0   skip:25 
fi-skl-6260u total:248  pass:233  dwarn:0   dfail:0   fail:0   skip:15 
fi-skl-6700hqtotal:248  pass:225  dwarn:0   dfail:0   fail:0   skip:23 
fi-skl-6700k total:248  pass:222  dwarn:1   dfail:0   fail:0   skip:25 
fi-skl-6770hqtotal:248  pass:230  dwarn:2   dfail:0   fail:1   skip:15 
fi-snb-2520m total:248  pass:211  dwarn:0   dfail:0   fail:0   skip:37 
fi-snb-2600  total:248  pass:210  dwarn:0   dfail:0   fail:0   skip:38 

Results at /archive/results/CI_IGT_test/Patchwork_2683/

46271d41e30090d7fc996e8f5abde6a59f51038b drm-intel-nightly: 
2016y-10m-12d-11h-06m-41s UTC integration manifest
35edc31 drm/i915: Fix misplaced '\n' in printing the GPU error's RING_HEAD

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Re: [Intel-gfx] [PATCH i-g-t 1/5] tests: Use bash for debugfs_wedged and drm_lib.sh

[David Weinehall]

On Wed, Oct 12, 2016 at 04:04:34PM +0300, Jani Nikula wrote:
> On Wed, 12 Oct 2016, Joonas Lahtinen  wrote:
> > On ke, 2016-10-12 at 14:16 +0300, Jani Nikula wrote:
> >> If you really care, go ahead and send the patches to make these Bourne
> >> shell compatible, but then do also sign up for testing them on non-bash
> >> shells. The CI won't. I don't think it's worth the trouble, but YMMV.
> >
> > If they're re-written using POSIX sh constructs only, I don't think
> > they need to be tested outside of POSIX sh? That's what standards are
> > for.
> 
> It's just that if the majority of folks and the CI have bash as /bin/sh,
> we won't notice when we accidentally add bashisms, and it'll eventually
> break. Maybe you could keep running shellcheck [1] on them, or
> something.

At the very least most/all Debian and Ubuntu systems use dash as /bin/sh.

It supports a very small subset of the bashisms (most notably local),
and is faster than bash.

> [1] https://www.shellcheck.net/
> 
> > I also remember FreeBSD guys being all for letting bash dependency go.
> > So there'd be actual gains too.
> 
> I'm biting my lips not to quip on that.
> 
> > All are easily convertible. So let's do this.
> 
> If you have the time, go ahead. But don't break *any* functionality, no
> compromises.


Kind regards, David
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[Intel-gfx] [CI 3/3] drm/i915/gtt: Free unused lower-level page tables

[Michał Winiarski]

Since "Dynamic page table allocations" were introduced, our page tables
can grow (being dynamically allocated) with address space range usage.
Unfortunately, their lifetime is bound to vm. This is not a huge problem
when we're not using softpin - drm_mm is creating an upper bound on used
range by causing addresses for our VMAs to eventually be reused.

With softpin, long lived contexts can drain the system out of memory
even with a single "small" object. For example:

bo = bo_alloc(size);
while(true)
offset += size;
exec(bo, offset);

Will cause us to create new allocations until all memory in the system
is used for tracking GPU pages (even though almost all PTEs in this vm
are pointing to scratch).

Let's free unused page tables in clear_range to prevent this - if no
entries are used, we can safely free it and return this information to
the caller (so that higher-level entry is pointing to scratch).

v2: Document return value and free semantics (Joonas)
v3: No newlines in vars block (Joonas)

Cc: Chris Wilson 
Cc: Joonas Lahtinen 
Cc: Michel Thierry 
Cc: Mika Kuoppala 
Signed-off-by: Michał Winiarski 
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 84 +
 1 file changed, 76 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index c284d8d..e733657 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -704,13 +704,14 @@ static int gen8_48b_mm_switch(struct i915_hw_ppgtt *ppgtt,
return gen8_write_pdp(req, 0, px_dma(>pml4));
 }
 
-static void gen8_ppgtt_clear_pt(struct i915_address_space *vm,
+/* Removes entries from a single page table, releasing it if it's empty.
+ * Caller can use the return value to update higher-level entries */
+static bool gen8_ppgtt_clear_pt(struct i915_address_space *vm,
struct i915_page_table *pt,
uint64_t start,
uint64_t length)
 {
struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
-
unsigned int pte_start = gen8_pte_index(start);
unsigned int num_entries = gen8_pte_count(start, length);
uint64_t pte;
@@ -719,63 +720,130 @@ static void gen8_ppgtt_clear_pt(struct 
i915_address_space *vm,
 I915_CACHE_LLC);
 
if (WARN_ON(!px_page(pt)))
-   return;
+   return false;
 
bitmap_clear(pt->used_ptes, pte_start, num_entries);
 
+   if (bitmap_empty(pt->used_ptes, GEN8_PTES)) {
+   free_pt(vm->dev, pt);
+   return true;
+   }
+
pt_vaddr = kmap_px(pt);
 
for (pte = pte_start; pte < num_entries; pte++)
pt_vaddr[pte] = scratch_pte;
 
kunmap_px(ppgtt, pt_vaddr);
+
+   return false;
 }
 
-static void gen8_ppgtt_clear_pd(struct i915_address_space *vm,
+/* Removes entries from a single page dir, releasing it if it's empty.
+ * Caller can use the return value to update higher-level entries
+ */
+static bool gen8_ppgtt_clear_pd(struct i915_address_space *vm,
struct i915_page_directory *pd,
uint64_t start,
uint64_t length)
 {
+   struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
struct i915_page_table *pt;
uint64_t pde;
+   gen8_pde_t *pde_vaddr;
+   gen8_pde_t scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt),
+I915_CACHE_LLC);
+   bool reduce;
 
gen8_for_each_pde(pt, pd, start, length, pde) {
if (WARN_ON(!pd->page_table[pde]))
break;
 
-   gen8_ppgtt_clear_pt(vm, pt, start, length);
+   reduce = gen8_ppgtt_clear_pt(vm, pt, start, length);
+
+   if (reduce) {
+   __clear_bit(pde, pd->used_pdes);
+   pde_vaddr = kmap_px(pd);
+   pde_vaddr[pde] = scratch_pde;
+   kunmap_px(ppgtt, pde_vaddr);
+   }
+   }
+
+   if (bitmap_empty(pd->used_pdes, I915_PDES)) {
+   free_pd(vm->dev, pd);
+   return true;
}
+
+   return false;
 }
 
-static void gen8_ppgtt_clear_pdp(struct i915_address_space *vm,
+/* Removes entries from a single page dir pointer, releasing it if it's empty.
+ * Caller can use the return value to update higher-level entries
+ */
+static bool gen8_ppgtt_clear_pdp(struct i915_address_space *vm,
 struct i915_page_directory_pointer *pdp,
 uint64_t start,
 uint64_t length)
 {
+   struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
 

[Intel-gfx] [CI 1/3] drm/i915: Remove unused "valid" parameter from pte_encode

[Michał Winiarski]

We never used any invalid ptes, those were put in place for
a possibility of doing gpu faults. However our batchbuffers are not
restricted in length, so everything needs to be pointing to something
and thus out-of-bounds is pointing to scratch.

Remove the valid flag as it is always true.

v2: Expand commit msg, patch reorder (Mika)

Cc: Chris Wilson 
Cc: Michel Thierry 
Reviewed-by: Joonas Lahtinen 
Reviewed-by: Mika Kuoppala 
Signed-off-by: Michał Winiarski 
---
 drivers/gpu/drm/i915/i915_gem.c|  6 +-
 drivers/gpu/drm/i915/i915_gem_execbuffer.c |  3 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c| 98 --
 drivers/gpu/drm/i915/i915_gem_gtt.h|  5 +-
 4 files changed, 45 insertions(+), 67 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index fdd496e..ec2335c 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -919,8 +919,7 @@ out_unpin:
if (node.allocated) {
wmb();
ggtt->base.clear_range(>base,
-  node.start, node.size,
-  true);
+  node.start, node.size);
i915_gem_object_unpin_pages(obj);
remove_mappable_node();
} else {
@@ -1228,8 +1227,7 @@ out_unpin:
if (node.allocated) {
wmb();
ggtt->base.clear_range(>base,
-  node.start, node.size,
-  true);
+  node.start, node.size);
i915_gem_object_unpin_pages(obj);
remove_mappable_node();
} else {
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c 
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 72c7c18..6835074 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -370,8 +370,7 @@ static void reloc_cache_fini(struct reloc_cache *cache)
 
ggtt->base.clear_range(>base,
   cache->node.start,
-  cache->node.size,
-  true);
+  cache->node.size);
drm_mm_remove_node(>node);
} else {
i915_vma_unpin((struct i915_vma *)cache->node.mm);
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 2d846aa..48ec9c5 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -191,15 +191,13 @@ static void ppgtt_unbind_vma(struct i915_vma *vma)
 {
vma->vm->clear_range(vma->vm,
 vma->node.start,
-vma->size,
-true);
+vma->size);
 }
 
 static gen8_pte_t gen8_pte_encode(dma_addr_t addr,
- enum i915_cache_level level,
- bool valid)
+ enum i915_cache_level level)
 {
-   gen8_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
+   gen8_pte_t pte = _PAGE_PRESENT | _PAGE_RW;
pte |= addr;
 
switch (level) {
@@ -234,9 +232,9 @@ static gen8_pde_t gen8_pde_encode(const dma_addr_t addr,
 
 static gen6_pte_t snb_pte_encode(dma_addr_t addr,
 enum i915_cache_level level,
-bool valid, u32 unused)
+u32 unused)
 {
-   gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
+   gen6_pte_t pte = GEN6_PTE_VALID;
pte |= GEN6_PTE_ADDR_ENCODE(addr);
 
switch (level) {
@@ -256,9 +254,9 @@ static gen6_pte_t snb_pte_encode(dma_addr_t addr,
 
 static gen6_pte_t ivb_pte_encode(dma_addr_t addr,
 enum i915_cache_level level,
-bool valid, u32 unused)
+u32 unused)
 {
-   gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
+   gen6_pte_t pte = GEN6_PTE_VALID;
pte |= GEN6_PTE_ADDR_ENCODE(addr);
 
switch (level) {
@@ -280,9 +278,9 @@ static gen6_pte_t ivb_pte_encode(dma_addr_t addr,
 
 static gen6_pte_t byt_pte_encode(dma_addr_t addr,
 enum i915_cache_level level,
-bool valid, u32 flags)
+u32 flags)
 {
-   gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
+   gen6_pte_t pte = GEN6_PTE_VALID;
pte |= GEN6_PTE_ADDR_ENCODE(addr);
 
if (!(flags & PTE_READ_ONLY))
@@ -296,9 +294,9 @@ static gen6_pte_t byt_pte_encode(dma_addr_t addr,
 
 static 

[Intel-gfx] [CI 2/3] drm/i915/gtt: Split gen8_ppgtt_clear_pte_range

[Michał Winiarski]

Let's use more top-down approach, where each gen8_ppgtt_clear_* function
is responsible for clearing the struct passed as an argument and calling
relevant clear_range functions on lower-level tables.
Doing this rather than operating on PTE ranges makes the implementation
of shrinking page tables quite simple.

v2: Drop min when calculating num_entries, no negation in 48b ppgtt
check, no newlines in vars block (Joonas)

Cc: Chris Wilson 
Cc: Joonas Lahtinen 
Cc: Michel Thierry 
Cc: Mika Kuoppala 
Signed-off-by: Michał Winiarski 
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 107 +++-
 1 file changed, 58 insertions(+), 49 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 48ec9c5..c284d8d 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -704,59 +704,78 @@ static int gen8_48b_mm_switch(struct i915_hw_ppgtt *ppgtt,
return gen8_write_pdp(req, 0, px_dma(>pml4));
 }
 
-static void gen8_ppgtt_clear_pte_range(struct i915_address_space *vm,
-  struct i915_page_directory_pointer *pdp,
-  uint64_t start,
-  uint64_t length,
-  gen8_pte_t scratch_pte)
+static void gen8_ppgtt_clear_pt(struct i915_address_space *vm,
+   struct i915_page_table *pt,
+   uint64_t start,
+   uint64_t length)
 {
struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
+
+   unsigned int pte_start = gen8_pte_index(start);
+   unsigned int num_entries = gen8_pte_count(start, length);
+   uint64_t pte;
gen8_pte_t *pt_vaddr;
-   unsigned pdpe = gen8_pdpe_index(start);
-   unsigned pde = gen8_pde_index(start);
-   unsigned pte = gen8_pte_index(start);
-   unsigned num_entries = length >> PAGE_SHIFT;
-   unsigned last_pte, i;
+   gen8_pte_t scratch_pte = gen8_pte_encode(vm->scratch_page.daddr,
+I915_CACHE_LLC);
 
-   if (WARN_ON(!pdp))
+   if (WARN_ON(!px_page(pt)))
return;
 
-   while (num_entries) {
-   struct i915_page_directory *pd;
-   struct i915_page_table *pt;
+   bitmap_clear(pt->used_ptes, pte_start, num_entries);
 
-   if (WARN_ON(!pdp->page_directory[pdpe]))
-   break;
+   pt_vaddr = kmap_px(pt);
+
+   for (pte = pte_start; pte < num_entries; pte++)
+   pt_vaddr[pte] = scratch_pte;
 
-   pd = pdp->page_directory[pdpe];
+   kunmap_px(ppgtt, pt_vaddr);
+}
+
+static void gen8_ppgtt_clear_pd(struct i915_address_space *vm,
+   struct i915_page_directory *pd,
+   uint64_t start,
+   uint64_t length)
+{
+   struct i915_page_table *pt;
+   uint64_t pde;
 
+   gen8_for_each_pde(pt, pd, start, length, pde) {
if (WARN_ON(!pd->page_table[pde]))
break;
 
-   pt = pd->page_table[pde];
+   gen8_ppgtt_clear_pt(vm, pt, start, length);
+   }
+}
 
-   if (WARN_ON(!px_page(pt)))
-   break;
+static void gen8_ppgtt_clear_pdp(struct i915_address_space *vm,
+struct i915_page_directory_pointer *pdp,
+uint64_t start,
+uint64_t length)
+{
+   struct i915_page_directory *pd;
+   uint64_t pdpe;
 
-   last_pte = pte + num_entries;
-   if (last_pte > GEN8_PTES)
-   last_pte = GEN8_PTES;
+   gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
+   if (WARN_ON(!pdp->page_directory[pdpe]))
+   break;
 
-   pt_vaddr = kmap_px(pt);
+   gen8_ppgtt_clear_pd(vm, pd, start, length);
+   }
+}
 
-   for (i = pte; i < last_pte; i++) {
-   pt_vaddr[i] = scratch_pte;
-   num_entries--;
-   }
+static void gen8_ppgtt_clear_pml4(struct i915_address_space *vm,
+ struct i915_pml4 *pml4,
+ uint64_t start,
+ uint64_t length)
+{
+   struct i915_page_directory_pointer *pdp;
+   uint64_t pml4e;
 
-   kunmap_px(ppgtt, pt_vaddr);
+   gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) {
+   if (WARN_ON(!pml4->pdps[pml4e]))
+   break;
 
-   pte = 0;
-   if (++pde == I915_PDES) {
-   if (++pdpe == I915_PDPES_PER_PDP(vm->dev))
-

Re: [Intel-gfx] [PATCH] drm/i915: GMBUS don't need no forcewake

[Ville Syrjälä]

On Wed, Oct 12, 2016 at 12:58:34PM +0100, Chris Wilson wrote:
> On Wed, Oct 12, 2016 at 02:44:47PM +0300, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä 
> > 
> > GMBUS is part of the display engine, and thus has no need for
> > forcewake. Let's not bother trying to grab it then.
> > 
> > I don't recall if the display engine suffers from system hangs
> > due to multiple accesses to the same "cacheline" in mmio space.
> > I hope not since we're no longer protected by the uncore lock
> > since commit 4e6c2d58ba86 ("drm/i915: Take forcewake once for
> > the entire GMBUS transaction")
> 
> Only applies to concurrent access to the same cacheline, in this case
> should be serialised by the mutex around the gmbus xfer.

Hmm. Yeah, I suppose there shouldn't be unrelated stuff nearby. Haven't
double checked though.

>  
> > Cc: Chris Wilson 
> > Cc: David Weinehall 
> > Signed-off-by: Ville Syrjälä 
> > ---
> >  drivers/gpu/drm/i915/intel_i2c.c | 5 -
> >  1 file changed, 5 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_i2c.c 
> > b/drivers/gpu/drm/i915/intel_i2c.c
> > index 79aab9ad6faa..49c7824a4c29 100644
> > --- a/drivers/gpu/drm/i915/intel_i2c.c
> > +++ b/drivers/gpu/drm/i915/intel_i2c.c
> > @@ -468,13 +468,9 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct 
> > i2c_msg *msgs, int num)
> >struct intel_gmbus,
> >adapter);
> > struct drm_i915_private *dev_priv = bus->dev_priv;
> > -   const unsigned int fw =
> > -   intel_uncore_forcewake_for_reg(dev_priv, GMBUS0,
> > -  FW_REG_READ | FW_REG_WRITE);
> > int i = 0, inc, try = 0;
> > int ret = 0;
> 
> I915_WARN_ON(intel_uncore_forcewake_for_reg(dev_priv, GMBUS0,
>   FW_REG_READ |
>   FW_REG_WRITE));
> 
> ? Would be good to test the fw handling as well.

Not sure I'd want to sprinkle forcewake testing into modeset code.

-- 
Ville Syrjälä
Intel OTC
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Re: [Intel-gfx] [PATCH 13/19] drm/i915: Make IS_BROXTON only take dev_priv

[David Weinehall]

On Wed, Oct 12, 2016 at 01:06:51PM +0100, Tvrtko Ursulin wrote:
> 
> On 12/10/2016 12:52, David Weinehall wrote:
> > On Tue, Oct 11, 2016 at 02:21:46PM +0100, Tvrtko Ursulin wrote:
> > > From: Tvrtko Ursulin 
> > > 
> > > Saves 1392 bytes of .rodata strings.
> > > 
> > > v2: Add parantheses around dev_priv. (Ville Syrjala)
> > > 
> > > Signed-off-by: Tvrtko Ursulin 
> > This patch does quite a bit more than just change IS_BROXTON to use
> > dev_priv...
> 
> Some cascade effects on function prototypes here and there - if you find it
> objectionable I can try to eliminate or at least minimise?

I don't find the changes objectionable -- they are, as you say, cascade
effects. It might, however, be worth explaining in the patch description
that the patch does a bit more than just more than IS_BROXTON(). Doing
so for just minor differences is overkill, but in this case it feels
justified.

> > > ---
> > >   drivers/gpu/drm/i915/i915_drv.c |  2 +-
> > >   drivers/gpu/drm/i915/i915_drv.h |  5 +++--
> > >   drivers/gpu/drm/i915/i915_gem_gtt.c | 40 
> > > +
> > >   drivers/gpu/drm/i915/i915_irq.c |  2 +-
> > >   drivers/gpu/drm/i915/intel_ddi.c|  4 ++--
> > >   drivers/gpu/drm/i915/intel_display.c| 31 ++---
> > >   drivers/gpu/drm/i915/intel_dp.c | 16 ++---
> > >   drivers/gpu/drm/i915/intel_dpll_mgr.c   |  2 +-
> > >   drivers/gpu/drm/i915/intel_dsi.c| 27 +++---
> > >   drivers/gpu/drm/i915/intel_dsi_pll.c| 26 ++---
> > >   drivers/gpu/drm/i915/intel_guc_loader.c |  8 +++
> > >   drivers/gpu/drm/i915/intel_hdmi.c   |  6 ++---
> > >   drivers/gpu/drm/i915/intel_runtime_pm.c |  2 +-
> > >   13 files changed, 89 insertions(+), 82 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.c 
> > > b/drivers/gpu/drm/i915/i915_drv.c
> > > index d854ea4a7e92..18af6d1ccec9 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.c
> > > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > > @@ -2437,7 +2437,7 @@ static int intel_runtime_resume(struct device *kdev)
> > >   if (IS_GEN6(dev_priv))
> > >   intel_init_pch_refclk(dev);
> > > - if (IS_BROXTON(dev)) {
> > > + if (IS_BROXTON(dev_priv)) {
> > >   bxt_disable_dc9(dev_priv);
> > >   bxt_display_core_init(dev_priv, true);
> > >   if (dev_priv->csr.dmc_payload &&
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.h 
> > > b/drivers/gpu/drm/i915/i915_drv.h
> > > index 9784e61400e5..ad9299196d13 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > @@ -2664,7 +2664,7 @@ struct drm_i915_cmd_table {
> > >   #define IS_HASWELL(dev_priv)((dev_priv)->info.is_haswell)
> > >   #define IS_BROADWELL(dev_priv)  ((dev_priv)->info.is_broadwell)
> > >   #define IS_SKYLAKE(dev_priv)((dev_priv)->info.is_skylake)
> > > -#define IS_BROXTON(dev)  (INTEL_INFO(dev)->is_broxton)
> > > +#define IS_BROXTON(dev_priv) ((dev_priv)->info.is_broxton)
> > >   #define IS_KABYLAKE(dev_priv)   ((dev_priv)->info.is_kabylake)
> > >   #define IS_MOBILE(dev)  (INTEL_INFO(dev)->is_mobile)
> > >   #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
> > > @@ -2724,7 +2724,8 @@ struct drm_i915_cmd_table {
> > >   #define BXT_REVID_B00x3
> > >   #define BXT_REVID_C00x9
> > > -#define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, 
> > > since, until))
> > > +#define IS_BXT_REVID(dev_priv, since, until) \
> > > + (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
> > >   #define KBL_REVID_A00x0
> > >   #define KBL_REVID_B00x1
> > > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
> > > b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > > index cf43a5632961..e628691fe97e 100644
> > > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> > > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > > @@ -373,27 +373,29 @@ static void *kmap_page_dma(struct i915_page_dma *p)
> > >   /* We use the flushing unmap only with ppgtt structures:
> > >* page directories, page tables and scratch pages.
> > >*/
> > > -static void kunmap_page_dma(struct drm_device *dev, void *vaddr)
> > > +static void kunmap_page_dma(struct drm_i915_private *dev_priv, void 
> > > *vaddr)
> > >   {
> > >   /* There are only few exceptions for gen >=6. chv and bxt.
> > >* And we are not sure about the latter so play safe for now.
> > >*/
> > > - if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
> > > + if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
> > >   drm_clflush_virt_range(vaddr, PAGE_SIZE);
> > >   kunmap_atomic(vaddr);
> > >   }
> > >   #define kmap_px(px) kmap_page_dma(px_base(px))
> > > -#define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, 
> > > (vaddr))
> > > +#define 

Re: [Intel-gfx] [PATCH] drm/i915: GMBUS don't need no forcewake

[Chris Wilson]

On Wed, Oct 12, 2016 at 03:39:47PM +0300, Ville Syrjälä wrote:
> On Wed, Oct 12, 2016 at 12:58:34PM +0100, Chris Wilson wrote:
> > On Wed, Oct 12, 2016 at 02:44:47PM +0300, ville.syrj...@linux.intel.com 
> > wrote:
> > > From: Ville Syrjälä 
> > > 
> > > GMBUS is part of the display engine, and thus has no need for
> > > forcewake. Let's not bother trying to grab it then.
> > > 
> > > I don't recall if the display engine suffers from system hangs
> > > due to multiple accesses to the same "cacheline" in mmio space.
> > > I hope not since we're no longer protected by the uncore lock
> > > since commit 4e6c2d58ba86 ("drm/i915: Take forcewake once for
> > > the entire GMBUS transaction")
> > 
> > Only applies to concurrent access to the same cacheline, in this case
> > should be serialised by the mutex around the gmbus xfer.
> 
> Hmm. Yeah, I suppose there shouldn't be unrelated stuff nearby. Haven't
> double checked though.
> 
> >  
> > > Cc: Chris Wilson 
> > > Cc: David Weinehall 
> > > Signed-off-by: Ville Syrjälä 
> > > ---
> > >  drivers/gpu/drm/i915/intel_i2c.c | 5 -
> > >  1 file changed, 5 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_i2c.c 
> > > b/drivers/gpu/drm/i915/intel_i2c.c
> > > index 79aab9ad6faa..49c7824a4c29 100644
> > > --- a/drivers/gpu/drm/i915/intel_i2c.c
> > > +++ b/drivers/gpu/drm/i915/intel_i2c.c
> > > @@ -468,13 +468,9 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct 
> > > i2c_msg *msgs, int num)
> > >  struct intel_gmbus,
> > >  adapter);
> > >   struct drm_i915_private *dev_priv = bus->dev_priv;
> > > - const unsigned int fw =
> > > - intel_uncore_forcewake_for_reg(dev_priv, GMBUS0,
> > > -FW_REG_READ | FW_REG_WRITE);
> > >   int i = 0, inc, try = 0;
> > >   int ret = 0;
> > 
> > I915_WARN_ON(intel_uncore_forcewake_for_reg(dev_priv, GMBUS0,
> > FW_REG_READ |
> > FW_REG_WRITE));
> > 
> > ? Would be good to test the fw handling as well.
> 
> Not sure I'd want to sprinkle forcewake testing into modeset code.

You never use registers here? ;)

Reviewed-by: Chris Wilson 
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Make sure the base lives at offset 0 of all kms objects

[Patchwork]

== Series Details ==

Series: drm/i915: Make sure the base lives at offset 0 of all kms objects
URL   : https://patchwork.freedesktop.org/series/13640/
State : failure

== Summary ==

Series 13640v1 drm/i915: Make sure the base lives at offset 0 of all kms objects
https://patchwork.freedesktop.org/api/1.0/series/13640/revisions/1/mbox/

Test kms_psr_sink_crc:
Subgroup psr_basic:
pass   -> DMESG-WARN (fi-skl-6700hq)
Test vgem_basic:
Subgroup unload:
pass   -> SKIP   (fi-kbl-7200u)
pass   -> SKIP   (fi-bdw-5557u)
Test vgem_reload_basic:
pass   -> FAIL   (fi-bdw-5557u)

fi-bdw-5557u total:248  pass:230  dwarn:0   dfail:0   fail:1   skip:17 
fi-bsw-n3050 total:248  pass:205  dwarn:0   dfail:0   fail:0   skip:43 
fi-bxt-t5700 total:248  pass:217  dwarn:0   dfail:0   fail:0   skip:31 
fi-byt-j1900 total:248  pass:213  dwarn:2   dfail:0   fail:1   skip:32 
fi-byt-n2820 total:248  pass:211  dwarn:0   dfail:0   fail:1   skip:36 
fi-hsw-4770  total:248  pass:224  dwarn:0   dfail:0   fail:0   skip:24 
fi-hsw-4770r total:248  pass:225  dwarn:0   dfail:0   fail:0   skip:23 
fi-ilk-650   total:248  pass:185  dwarn:0   dfail:0   fail:2   skip:61 
fi-ivb-3520m total:248  pass:222  dwarn:0   dfail:0   fail:0   skip:26 
fi-ivb-3770  total:248  pass:222  dwarn:0   dfail:0   fail:0   skip:26 
fi-kbl-7200u total:248  pass:222  dwarn:0   dfail:0   fail:0   skip:26 
fi-skl-6260u total:248  pass:233  dwarn:0   dfail:0   fail:0   skip:15 
fi-skl-6700hqtotal:248  pass:224  dwarn:1   dfail:0   fail:0   skip:23 
fi-skl-6700k total:248  pass:222  dwarn:1   dfail:0   fail:0   skip:25 
fi-skl-6770hqtotal:248  pass:231  dwarn:1   dfail:0   fail:1   skip:15 
fi-snb-2520m total:248  pass:211  dwarn:0   dfail:0   fail:0   skip:37 
fi-snb-2600  total:248  pass:210  dwarn:0   dfail:0   fail:0   skip:38 

Results at /archive/results/CI_IGT_test/Patchwork_2684/

46271d41e30090d7fc996e8f5abde6a59f51038b drm-intel-nightly: 
2016y-10m-12d-11h-06m-41s UTC integration manifest
6c56c1c drm/i915: Make sure the base lives at offset 0 of all kms objects

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