On Tue, 22 Jul 2014 13:48:45 -0700
Jesse Barnes jbar...@virtuousgeek.org wrote:
On Tue, 22 Jul 2014 08:41:11 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Mon, Jul 14, 2014 at 12:10:35PM -0700, Todd Previte wrote:
This patch set adds the foundational support for Displayport compliance
On Tue, 22 Jul 2014 22:44:54 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Jul 22, 2014 at 10:40 PM, Jesse Barnes jbar...@virtuousgeek.org
wrote:
+ /* Set link rate directly */
+ intel_dp-link_bw = rxdata[0];
+ /* Preserve 7:5 when setting lane count */
+ intel_dp
On Tue, 22 Jul 2014 22:53:44 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Jul 22, 2014 at 10:48 PM, Jesse Barnes jbar...@virtuousgeek.org
wrote:
Are you saying
you'll reject this approach entirely?
I'm saying that I don't see terrible lot of value in adding a bunch of
code
On Mon, 30 Jun 2014 08:05:34 -0700
Jesse Barnes jesse.bar...@intel.com wrote:
On Sat, 28 Jun 2014 16:45:03 +0300
Jani Nikula jani.nik...@intel.com wrote:
+/* Scale user_level in range [0..user_max] to [0..hw_max], clamping the
result
+ * to [hw_min..hw_max]. */
+static inline u32
On Tue, 24 Jun 2014 18:27:39 +0300
Jani Nikula jani.nik...@intel.com wrote:
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_bios.c | 3 ++-
2 files changed, 3
On Wed, 23 Jul 2014 16:10:32 +0100
John Harrison john.c.harri...@intel.com wrote:
On 02/07/2014 19:20, Jesse Barnes wrote:
On Thu, 26 Jun 2014 18:24:04 +0100
john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
The scheduler decouples the submission of batch
--
Jesse Barnes, Intel Open Source Technology Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
;
+ return 0;
}
Makes me wonder if we should have our own slab for the objs. Might
save a bit of mem and/or perf? But then could reduce our cache hit
rate, dunno.
Overall this gets my:
Fatigued-reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
given its size and with the changes/comments
On Tue, 29 Jul 2014 12:41:26 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Jul 29, 2014 at 08:29:53AM +0100, Chris Wilson wrote:
On Mon, Jul 28, 2014 at 01:44:12PM -0700, Jesse Barnes wrote:
@@ -3038,44 +3203,35 @@ out:
*/
int
i915_gem_object_sync(struct
);
+ }
+
modeset_update_crtc_power_domains(dev);
}
Which doc has these Punit commands? I'm assuming you have them
correct, but a ref would be good if we don't already have one.
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
There should probably be a JIRA for this too so QA can verify once we
have updated
ready yet */
+ if (IS_CHERRYVIEW(dev))
+ return 40;
+
mutex_lock(dev_priv-dpio_lock);
val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
mutex_unlock(dev_priv-dpio_lock);
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
--
Jesse Barnes, Intel Open
| DPLL_REFA_CLK_ENABLE_VLV;
if (pipe != PIPE_A)
val |= DPLL_INTEGRATED_CRI_CLK_VLV;
I915_WRITE(DPLL(pipe), val);
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
--
Jesse Barnes, Intel Open Source Technology Center
___
Intel-gfx
-config.dpll.m2 0x3f;
bestm1 = crtc-config.dpll.m1;
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
--
Jesse Barnes, Intel Open Source Technology Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman
distribution */
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
--
Jesse Barnes, Intel Open Source Technology Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
;
+ val |= 102 DPIO_SWING_MARGIN000_SHIFT;
vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
}
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
--
Jesse Barnes, Intel Open Source Technology Center
___
Intel-gfx
guys on this and update our docs...
--
Jesse Barnes, Intel Open Source Technology Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
, cursor=%d,
+ B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n,
planea_wm, cursora_wm,
planeb_wm, cursorb_wm,
plane_sr, cursor_sr);
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
--
Jesse Barnes, Intel Open Source
);
- intel_ring_advance(ring);
-
- return 0;
-
+ return gen8_emit_pipe_control(ring, flags, scratch_addr);
}
static void ring_write_tail(struct intel_engine_cs *ring,
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
--
Jesse Barnes, Intel Open Source Technology Center
;
I915_WRITE(intel_dp-output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
}
POSTING_READ(intel_dp-output_reg);
I guess we could have a whole IS_CHV block, but that would probably add
more code than it saved...
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
--
Jesse Barnes
On Tue, 29 Jul 2014 19:59:26 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Jul 29, 2014 at 09:51:03AM -0700, Jesse Barnes wrote:
On Sat, 28 Jun 2014 02:03:57 +0300
ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Looks like the Punit
patch, when applied to the
current tree, procduces a WARN.
Related commits:
commit daa390e5ee45cc051d6bf37b296901f2f92b002d
Author: Jesse Barnes jbar...@virtuousgeek.org
drm/i915: don't warn if IRQs are disabled when shutting down display IRQs
commit
This hasn't seen any testing yet, but I'm still interested in any bugs
people see in review, I'll fix them up.
If there are no major objections, I'll add some tests and a man page to
libdrm for this and we can move forward into the brave new world of
fences, giving userspace a lot more rope to
On Fri, 01 Aug 2014 10:04:55 +0100
Tvrtko Ursulin tvrtko.ursu...@linux.intel.com wrote:
Hi Jesse,
On 07/31/2014 07:58 PM, Jesse Barnes wrote:
Expose an ioctl to create Android fences based on the Android sync point
infrastructure (which in turn is based on DMA-buf fences). Just
that don't exist
with the execlist path if we stick with the legacy submission path (we
may have already hit one in fact).
--
Jesse Barnes, Intel Open Source Technology Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http
it after our first mode set.
Can you file a bug or JIRA for that to make sure we don't lose track of
the fastboot boot corruption issues after this fix lands?
Thanks,
--
Jesse Barnes, Intel Open Source Technology Center
___
Intel-gfx mailing list
Intel-gfx
Maarten's new interface
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/Kconfig | 2 +
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/i915_dma.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 10 ++
drivers/gpu/drm/i915/i915_gem.c | 15 +-
drivers
On Tue, 5 Aug 2014 09:44:00 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Aug 5, 2014 at 1:18 AM, Jesse Barnes jbar...@virtuousgeek.org wrote:
+#define DRM_IOCTL_I915_GEM_FENCE DRM_IOWR
(DRM_COMMAND_BASE + DRM_I915_GEM_FENCE, struct drm_i915_gem_fence
On Tue, 05 Aug 2014 10:09:56 +0200
Maarten Lankhorst maarten.lankho...@canonical.com wrote:
op 05-08-14 01:18, Jesse Barnes schreef:
Expose an ioctl to create Android fences based on the Android sync point
infrastructure (which in turn is based on DMA-buf fences). Just a
sketch
On Tue, 5 Aug 2014 17:08:22 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Aug 5, 2014 at 4:59 PM, Jesse Barnes jbar...@virtuousgeek.org wrote:
This doesn't really look like the interface I'd expected. Imo we just
need to add a flag to execbuf so that userspace can tell the kernel
On Tue, 5 Aug 2014 18:08:16 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Aug 5, 2014 at 6:05 PM, Jesse Barnes jbar...@virtuousgeek.org wrote:
But yes, I want the Android guys to try this out too. I've already
pinged them internally to check things out. Probably the biggest
On Tue, 5 Aug 2014 18:08:16 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Aug 5, 2014 at 6:05 PM, Jesse Barnes jbar...@virtuousgeek.org wrote:
On Tue, 5 Aug 2014 17:08:22 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Aug 5, 2014 at 4:59 PM, Jesse Barnes jbar...@virtuousgeek.org
On Tue, 5 Aug 2014 19:43:22 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Aug 5, 2014 at 7:09 PM, Jesse Barnes jbar...@virtuousgeek.org wrote:
Then we need similar flags for vblank events and pageflips to do the
same (obviously those are drm core patches) and it's all
-by: Vandana Kannan vandana.kan...@intel.com
Cc: Daniel Vetter daniel.vet...@ffwll.ch
Cc: Jesse Barnes jbar...@virtuousgeek.org
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 28 +---
drivers/gpu/drm/i915/intel_dp.c
behavior if we detect a hard coded connector
config that tries to enable a connector (disabling is easy!).
Based on earlier patches by Jesse Barnes.
v2: Remove Jesse's patch
Reported-by: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Cc
with your work you'll move them and
make them a bit more opaque? If so, we'll still want a way to get at
them directly, or access your mapping functions for generating PTE bits
for the GPU MMU.
Thanks,
--
Jesse Barnes, Intel Open Source Technology Center
universally bad.
Unless someone wants to pick up the additional work and testing of
using a timer scheme, making sure we don't have needless wakeups, and
generally improve power/perf across even more cases than this patch.
--
Jesse Barnes, Intel Open Source Technology Center
On Mon, 25 Aug 2014 20:29:27 +0200
Oliver Hartkopp socket...@hartkopp.net wrote:
Hi Jesse,
since the i915 stuff for 3.17 was merged I always get this
warning on my core i7 with internal Intel HD graphics.
Intel(R) Core(TM) i7 CPU M 640 @ 2.80GHz
As this warning is triggered by
the kernel GPU driver will be involved in all allocations.
I'm not sure whether this is BDW only either, so don't shoot it down or
discount it based on that.
--
Jesse Barnes, Intel Open Source Technology Center
___
Intel-gfx mailing list
Intel-gfx
This happens in irq_postinstall before we've set the pm._irqs_disabled flag,
but shouldn't warn. So add a nowarn variant to allow this to happen w/o
a backtrace and keep the rest of the IRQ tracking code happy.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915
On Tue, 26 Aug 2014 09:23:54 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Mon, Aug 25, 2014 at 04:24:55PM -0700, Jesse Barnes wrote:
This happens in irq_postinstall before we've set the pm._irqs_disabled flag,
but shouldn't warn. So add a nowarn variant to allow this to happen w/o
On Tue, 26 Aug 2014 21:03:11 +0200
Oliver Hartkopp socket...@hartkopp.net wrote:
On 26.08.2014 20:52, Jesse Barnes wrote:
On Tue, 26 Aug 2014 09:23:54 +0200
Daniel Vetter dan...@ffwll.ch wrote:
This happens in irq_postinstall before we've set the pm._irqs_disabled
flag
On Tue, 26 Aug 2014 22:51:13 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Aug 26, 2014 at 8:52 PM, Jesse Barnes jbar...@virtuousgeek.org
wrote:
On Tue, 26 Aug 2014 09:23:54 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Mon, Aug 25, 2014 at 04:24:55PM -0700, Jesse Barnes wrote
, Jesse Barnes jbar...@virtuousgeek.org
wrote:
On Tue, 26 Aug 2014 09:23:54 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Mon, Aug 25, 2014 at 04:24:55PM -0700, Jesse Barnes wrote:
This happens in irq_postinstall before we've set the pm._irqs_disabled
flag,
but shouldn't warn. So
On Wed, 27 Aug 2014 23:33:05 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Wed, Aug 27, 2014 at 9:59 PM, Jesse Barnes jbar...@virtuousgeek.org
wrote:
Yi, can you get this one run through testing on multiple platforms? We
just want to make sure there's not some path we missed that's gonna
...@intel.com
Cc: Jesse Barnes jbar...@virtuousgeek.org
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/i915/i915_irq.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 9eb303c1b621
Maarten's new interface
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/Kconfig | 2 +
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/i915_dma.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 10 ++
drivers/gpu/drm/i915/i915_gem.c | 15 +-
drivers
This set includes a sketch of how we might allow fences to be emitted
directly within a batch buffer. This gets rid of the need for flushing
around fence operations, which can be a win, and lets userspace more
finely control things.
If it looks reasonable, we could drop the separate ioctl and
Use a new reloc type to allow userspace to insert sync points within
batches before they're submitted. The corresponding fence fds are
returned in the offset field of the returned reloc tree, and can be
operated on with the sync fence APIs.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
On Wed, 3 Sep 2014 08:01:55 +0100
Chris Wilson ch...@chris-wilson.co.uk wrote:
On Tue, Sep 02, 2014 at 02:32:41PM -0700, Jesse Barnes wrote:
Use a new reloc type to allow userspace to insert sync points within
batches before they're submitted. The corresponding fence fds are
returned
On Wed, 3 Sep 2014 21:41:02 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Wed, Sep 3, 2014 at 9:01 PM, Jesse Barnes jbar...@virtuousgeek.org wrote:
On Wed, 3 Sep 2014 17:08:53 +0100
Chris Wilson ch...@chris-wilson.co.uk wrote:
On Wed, Sep 03, 2014 at 08:41:06AM -0700, Jesse Barnes wrote
at these bits.
So there's no good answer here... :/
--
Jesse Barnes, Intel Open Source Technology Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
I915_WRITE(CACHE_MODE_1,
_MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
Seems ok, though it would be nice to get some power numbers for it. Is
this a win, lose, or wash wrt power?
Reviewed-by: Jesse Barnes jbar
? For gen4+ we don't need the
fences for scanout since we have a bit in the plane control...
Or are we failing to fault on a previously mapped scanout too? If so,
we'd need to cover more than just scanout here.
--
Jesse Barnes, Intel Open Source Technology Center
),
0x005f0021);
I think it's ok, but can you specify the doc title in the commit
message? Should make things easier to find in the rat's nest of files
later. :)
--
Jesse Barnes, Intel Open Source Technology Center
___
Intel-gfx mailing list
? Is it possible that others have the same problem ?
Ouch, so a BIOS that uses the other forcewake mechanism seems to have
escaped. Is there a newer one available for your system? I'm hoping
it'll fix the issue, otherwise we may have to introduce both methods
for IVB again...
--
Jesse Barnes, Intel Open
cover those ... Disallowing is cheaper ;-)
Do we have a good use case for allowing the tiling and/or caching
requests? If not, yeah I'd just say punt on it for now.
So, any chance we can land this for 3.12? Would be nice to have a text
file or something describing usage too...
--
Jesse Barnes
= dev_priv-rps.cur_delay - 1;
/* sysfs frequency interfaces may have snuck in while servicing the
Yeah, seems reasonable. Going to RP1 on other platforms might be a
good approximation of this.
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
--
Jesse Barnes, Intel Open Source
(GEN6_PMIER, GEN6_PM_RPS_EVENTS);
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
--
Jesse Barnes, Intel Open Source Technology Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
getting the timer interrupts
when the GPU went idle. But that could be explained by punit fw
differences.
So this change looks ok to me.
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
--
Jesse Barnes, Intel Open Source Technology Center
___
Intel-gfx
= val;
trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv-mem_freq, val));
}
Hiding some of the Punit latency is nice...
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
--
Jesse Barnes, Intel Open Source Technology Center
___
Intel-gfx
for Punit\n);
pval = 8;
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
--
Jesse Barnes, Intel Open Source Technology Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
+ msecs_to_jiffies_timeout(10);
u32 pval;
WARN_ON(!mutex_is_locked(dev_priv-rps.hw_lock));
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
--
Jesse Barnes, Intel Open Source Technology Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
= dev_priv-rps.max_delay) {
if (IS_VALLEYVIEW(dev_priv-dev))
valleyview_set_rps(dev_priv-dev, new_delay);
else
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
--
Jesse Barnes, Intel Open Source Technology Center
;
trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv-mem_freq, val));
I don't see it anymore either... so Reviewed-by: Jesse Barnes
jbar...@virtuosugeek.org
--
Jesse Barnes, Intel Open Source Technology Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
actually work ok aside from
the warning? I *think* it's harmless in this case, but does indicate a
real bug in our state tracking... trying to come up with a patch now.
Thanks,
--
Jesse Barnes, Intel Open Source Technology Center
___
Intel-gfx mailing list
On Tue, 25 Jun 2013 19:59:28 +
Shuah Khan shuah...@samsung.com wrote:
On 06/25/2013 01:52 PM, Jesse Barnes wrote:
On Tue, 25 Jun 2013 21:37:37 +0200
Daniel Vetter daniel.vet...@ffwll.ch wrote:
Adding more lists to cc + Jesse since he's the guilty one for the
vt-switchless state
On Tue, 25 Jun 2013 20:51:27 +
Shuah Khan shuah...@samsung.com wrote:
On 06/25/2013 02:06 PM, Jesse Barnes wrote:
On Tue, 25 Jun 2013 19:59:28 +
Shuah Khan shuah...@samsung.com wrote:
On 06/25/2013 01:52 PM, Jesse Barnes wrote:
On Tue, 25 Jun 2013 21:37:37 +0200
Daniel Vetter
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/i915_drv.c |5 +
drivers/gpu/drm/i915/i915_drv.h |1 +
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 4a4ec86..226d4d7 100644
Down to 5 patches, rebased on top of today's dinq and with changes
requested by Daniel.
This series is activated through the i915.fastboot=1 boot argument, and
works here on my SNB laptop. We still have some prettying of userspace
to do, but at least we avoid the panel power sequence so things
use port_clock field rather than a new CPU eDP clock field in crtc_config
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/i915_drv.h |1 +
drivers/gpu/drm/i915/intel_crt.c |1 +
drivers/gpu/drm/i915/intel_display.c | 109
-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/intel_display.c | 37 ++
1 file changed, 37 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index e75ce2f..8a7da45 100644
--- a/drivers
Need better pfit tracking to do this right.
v2: use fastboot param around this hack
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/intel_display.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers
flip behavior
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/intel_display.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index a55e1e5..0e7324d 100644
)
#define SPCNTR(pipe, plane) _PIPE(pipe * 2 + plane, _SPACNTR, _SPBCNTR)
#define SPLINOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPALINOFF, _SPBLINOFF)
QA needs to get their VLV system set up to catch stuff like this...
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
--
Jesse Barnes, Intel
(dev_priv, DPIO_LFP_COEFF(pipe),
0x005f0021);
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
--
Jesse Barnes, Intel Open Source Technology Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http
: rename function to intel_crtc_mode_from_pipe_config for consistency (Chris)
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/intel_display.c | 37 ++
1 file changed, 37 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b
use port_clock field rather than a new CPU eDP clock field in crtc_config
v8: remove stale pixel_multiplier sets (Daniel)
multiply by pixel_multiplier in 9xx clock get too (Daniel)
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/i915_drv.h |1 +
drivers
On Sat, 22 Jun 2013 13:04:09 -0700
Guenter Roeck li...@roeck-us.net wrote:
On Sat, Jun 22, 2013 at 12:16:46PM -0700, Jesse Barnes wrote:
On Fri, 21 Jun 2013 23:58:08 -0700
Guenter Roeck li...@roeck-us.net wrote:
Hi all,
after upgrading one of my servers to 3.8, then 3.9.7
|
+ DPLL_PORTB_READY_MASK);
}
return true;
As a rule I'd like to see comments explaining this too, so we don't
have to dig through the changelog to figure it out. But that's no
biggie here, so:
Reviewed-by: Jesse Barnes jbar...@virtuosugeek.org
--
Jesse Barnes, Intel Open Source Technology
);
- } while (pval 1);
+ if (wait_for(((pval = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
GENFREQSTATUS) == 0, 10))
+ DRM_DEBUG_DRIVER(timed out waiting for Punit\n);
pval = 8;
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
--
Jesse Barnes, Intel Open
;
hdmi_val = SDVO_ENCODING_HDMI;
- if (!HAS_PCH_SPLIT(dev) !IS_VALLEYVIEW(dev))
+ if (!HAS_PCH_SPLIT(dev))
hdmi_val |= intel_hdmi-color_range;
if (adjusted_mode-flags DRM_MODE_FLAG_PVSYNC)
hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
Reviewed-by: Jesse Barnes
(crtc-base, INTEL_OUTPUT_EDP) ||
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
--
Jesse Barnes, Intel Open Source Technology Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/i915_drv.h |1 +
drivers/gpu/drm/i915/intel_display.c | 120 +++---
drivers/gpu/drm/i915/intel_dp.c |7 ++
drivers/gpu/drm/i915/intel_sdvo.c|5 ++
4 files changed, 123 insertions
...@anholt.net
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/i915_drv.c |4 +++
drivers/gpu/drm/i915/i915_drv.h |1 +
drivers/gpu/drm/i915/intel_pm.c | 54 +++
3 files changed, 37 insertions(+), 22 deletions(-)
diff --git
.
Cc: Imre Deak imre.d...@intel.com
Cc: Jesse Barnes jbar...@virtuousgeek.org
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/i915/intel_display.c | 12 ++--
drivers/gpu/drm/i915/intel_sdvo.c| 3 ---
2 files changed, 6 insertions(+), 9 deletions
agree: I'd rather see the WARN_ON made a BUG_ON when checking that the
guard_size is a multiple of PAGE_SIZE (which, incidentally, is the
wrong value to use, but that's also for another cleanup).
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
--
Jesse Barnes, Intel Open Source Technology Center
idleness elsewhere. I'm
also unsure about the cpufreq calls; I don't really know if this will do
what I want...
Requested-by: Owen Taylor otay...@gtk.org
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 24
drivers/gpu/drm
On Fri, 28 Jun 2013 19:37:01 +0100
Chris Wilson ch...@chris-wilson.co.uk wrote:
On Fri, Jun 28, 2013 at 09:54:32AM -0700, Jesse Barnes wrote:
Coming out of idle is usually due to some sort of user input (swiping a
screen, clicking a button) and often results in some sort of graphical
page prior
to this patch. (Ben)
Cc: Chris Wilson ch...@chris-wilson.co.uk
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_gem_gtt.c | 45
On Fri, 28 Jun 2013 12:10:51 -0700
Arjan van de Ven ar...@linux.intel.com wrote:
On 6/28/2013 11:37 AM, Chris Wilson wrote:
On Fri, Jun 28, 2013 at 09:54:32AM -0700, Jesse Barnes wrote:
Coming out of idle is usually due to some sort of user input (swiping a
screen, clicking a button
Print out the flag that failed and fix up a mismatched paren.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/intel_display.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915
We need to get the current hw state so we can compare against the
expected state.
References: https://bugs.freedesktop.org/show_bug.cgi?id=66444
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/intel_display.c |6 +-
1 file changed, 5 insertions(+), 1
On Mon, 1 Jul 2013 19:36:32 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Mon, Jul 01, 2013 at 10:19:10AM -0700, Jesse Barnes wrote:
We need to get the current hw state so we can compare against the
expected state.
References: https://bugs.freedesktop.org/show_bug.cgi?id=66444
This should help on HSW, where we don't currently have a get_clock call.
Reported-by: Paulo Zanoni przan...@gmail.com
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/intel_display.c | 24 ++--
1 file changed, 14 insertions(+), 10 deletions
(dev_priv, DPIO_LPF_COEFF(pipe),
- 0x005f0021);
+ 0x009f0003);
else
vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
0x00df);
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
On Tue, 09 Jul 2013 14:46:28 -0700
Christian Kreibich christ...@whoop.org wrote:
On 07/09/2013 02:27 PM, Jesse Barnes wrote:
Sounds like our pixel clock is probably out of the range your monitor
wants. If you can get that mode running with the VESA driver you could
collect a register dump
switchless resume shouldn't work...
--
Jesse Barnes, Intel Open Source Technology Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
pretty hard to get things out and tested on time...
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/i915_drv.c |5 -
drivers/gpu/drm/i915/i915_drv.h |1 -
2 files changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915
On Fri, 12 Jul 2013 08:07:30 +0200
Daniel Vetter daniel.vet...@ffwll.ch wrote:
I.e. for letter/pillarboxing. For those cases we need to adjust the
mode a bit, but Jesse gmch pfit refactoring in
commit 2dd24552cab40ea829ba3fda890eeafd2c4816d8
Author: Jesse Barnes jbar...@virtuousgeek.org
, the above problem is a regression caused by your commit:
commit 24576d23976746cb52e7700c4cadbf4bc1bc3472
Author: Jesse Barnes jbar...@virtuousgeek.org
Date: Tue Mar 26 09:25:45 2013 -0700
drm/i915: enable VT switchless resume v3
In your patch, you delete
701 - 800 of 2916 matches
Mail list logo
