[EDT] oom_killer: find bulkiest task based on pss value

[Yogesh Narayan Gaur]

EP-2DAD0AFA905A4ACB804C4F82A001242F
Hi Andrew,

Presently in oom_kill.c we calculate badness score of the victim task as per 
the present RSS counter value of the task.
RSS counter value for any task is usually '[Private (Dirty/Clean)] + [Shared 
(Dirty/Clean)]' of the task.
We have encountered a situation where values for Private fields are less but 
value for Shared fields are more and hence make total RSS counter value large. 
Later on oom situation killing task with highest RSS value but as Private field 
values are not large hence memory gain after killing this process is not as per 
the expectation.

For e.g. take below use-case scenario, in which 3 process are running in 
system. 
All these process done mmap for file exist in present directory and then 
copying data from this file to local allocated pointers in while(1) loop with 
some sleep. Out of 3 process, 2 process has mmaped file with MAP_SHARED setting 
and one has mapped file with MAP_PRIVATE setting.
I have all 3 processes in background and checks RSS/PSS value from user space 
utility (utility over cat /proc/pid/smaps)
Before OOM, below is the consumed memory status for these 3 process (all 
processes run with oom_score_adj = 0)

Comm : 1prg,  Pid : 213 (values in kB)
  Rss Shared  Private  Pss
  Process :  375764194596181168 278460

Comm : 3prg,  Pid : 217 (values in kB)
  RssShared   Private Pss
  Process :  305760  32 305728305738

Comm : 2prg,  Pid : 218 (values in kB)
  Rss  Shared   Private Pss
  Process :  389980 194596 195384292676


Thus as per present code design, first it would select process [2prg : 218] as 
bulkiest process as its RSS value is highest to kill. But if we kill this 
process then only ~195MB would be free as compare to expected ~389MB.
Thus identifying the task based on RSS value is not accurate design and killing 
that identified process didn’t release expected memory back to system.

We need to calculate victim task based on PSS instead of RSS as PSS value 
calculates as
PSS value = [Private (Dirty/Clean)] + [Shared (Dirty/Clean) / no. of shared 
task]
For above use-case scenario also, it can be checked that process [3prg : 217] 
is having largest PSS value and by killing this process we can gain maximum 
memory (~305MB) as compare to killing process identified based on RSS value.

--
Regards,
Yogesh Gaur.N‹§²æìr¸›yúèšØb²X¬¶Ç§vØ^–)Þº{.nÇ+‰·¥Š{±‘êçzX§¶›¡Ü¨}©ž²Æ 
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Re: Re: [EDT] oom_killer: find bulkiest task based on pss value

[Yogesh Narayan Gaur]

EP-2DAD0AFA905A4ACB804C4F82A001242F

--- Original Message ---
Sender : yalin wangyalin.wang2...@gmail.com
Date : May 08, 2015 13:17 (GMT+05:30)
Title : Re: [EDT] oom_killer: find bulkiest task based on pss value

2015-05-08 13:29 GMT+08:00 Yogesh Narayan Gaur :

 EP-2DAD0AFA905A4ACB804C4F82A001242F
 Hi Andrew,

 Presently in oom_kill.c we calculate badness score of the victim task as per 
 the present RSS counter value of the task.
 RSS counter value for any task is usually '[Private (Dirty/Clean)] + [Shared 
 (Dirty/Clean)]' of the task.
 We have encountered a situation where values for Private fields are less but 
 value for Shared fields are more and hence make total RSS counter value 
 large. Later on oom situation killing task with highest RSS value but as 
 Private field values are not large hence memory gain after killing this 
 process is not as per the expectation.

 For e.g. take below use-case scenario, in which 3 process are running in 
 system.
 All these process done mmap for file exist in present directory and then 
 copying data from this file to local allocated pointers in while(1) loop 
 with some sleep. Out of 3 process, 2 process has mmaped file with MAP_SHARED 
 setting and one has mapped file with MAP_PRIVATE setting.
 I have all 3 processes in background and checks RSS/PSS value from user 
 space utility (utility over cat /proc/pid/smaps)
 Before OOM, below is the consumed memory status for these 3 process (all 
 processes run with oom_score_adj = 0)
 
 Comm : 1prg,  Pid : 213 (values in kB)
   Rss Shared  Private  Pss
   Process :  375764194596181168 278460
 
 Comm : 3prg,  Pid : 217 (values in kB)
   RssShared   Private Pss
   Process :  305760  32 305728305738
 
 Comm : 2prg,  Pid : 218 (values in kB)
   Rss  Shared   Private Pss
   Process :  389980 194596 195384292676
 

 Thus as per present code design, first it would select process [2prg : 218] 
 as bulkiest process as its RSS value is highest to kill. But if we kill this 
 process then only ~195MB would be free as compare to expected ~389MB.
 Thus identifying the task based on RSS value is not accurate design and 
 killing that identified process didn’t release expected memory back to 
 system.

 We need to calculate victim task based on PSS instead of RSS as PSS value 
 calculates as
 PSS value = [Private (Dirty/Clean)] + [Shared (Dirty/Clean) / no. of shared 
 task]
 For above use-case scenario also, it can be checked that process [3prg : 
 217] is having largest PSS value and by killing this process we can gain 
 maximum memory (~305MB) as compare to killing process identified based on 
 RSS value.

 --
 Regards,
 Yogesh Gaur.


Great,

 in fact, i also encounter this scenario,
 I  use USS (page map counter == 1) pages
 to decide which process should be killed,
 seems have the same result as you use PSS,
 but PSS is better , it also consider shared pages,
 in case some process have large shared pages mapping
 but little Private page mapping

 BRs,
 Yalin

I have made patch which identifies bulkiest task on basis of PSS value. Please 
check below patch.
This patch is correcting the way victim task gets identified in oom condition. 

==

From 1c3d7f552f696bdbc0126c8e23beabedbd80e423 Mon Sep 17 00:00:00 2001
From: Yogesh Gaur yn.g...@samsung.com
Date: Thu, 7 May 2015 01:52:13 +0530
Subject: [PATCH] oom: find victim task based on pss

This patch is identifying bulkiest task to kill by OOM on the basis of PSS value
instead of present RSS values.
There can be scenario where task with highest RSS counter is consuming lot of 
shared
memory and killing that task didn't release expected amount of memory to system.
PSS value = [Private (Dirty/Clean)] + [Shared (Dirty/Clean) / no. of shared 
task]
RSS value = [Private (Dirty/Clean)] + [Shared (Dirty/Clean)]
Thus, using PSS value instead of RSS value as PSS value closely matches with 
actual
memory usage by the task.
This patch is using smaps_pte_range() interface defined in 
CONFIG_PROC_PAGE_MONITOR.
For case when CONFIG_PROC_PAGE_MONITOR disabled, this simply returns RSS value 
count.

Signed-off-by: Yogesh Gaur yn.g...@samsung.com
Signed-off-by: Amit Arora amit.ar...@samsung.com
Reviewed-by: Ajeet Yadav ajee...@samsung.com
---
 fs/proc/task_mmu.c |   47 +++
 include/linux/mm.h |9 +
 mm/oom_kill.c  |9 +++--
 3 files changed, 63 insertions(+), 2 deletions(-)

diff --git a/fs/proc/task_mmu.c b/fs/proc/task_mmu.c
index 956b75d..dd962ff 100644
--- a/fs/proc/task_mmu.c
+++ b/fs/proc/task_mmu.c
@@ -964,6 +964,53 @@ struct pagemapread {
bool

RE: [PATCH 03/11] spi: Add a driver for the Freescale/NXP QuadSPI controller

[Yogesh Narayan Gaur]

Hi Boris,

-Original Message-
From: linux-mtd [mailto:linux-mtd-boun...@lists.infradead.org] On Behalf Of 
Yogesh Narayan Gaur
Sent: Monday, June 11, 2018 3:51 PM
To: Boris Brezillon 
Cc: rich...@nod.at; Prabhakar Kushwaha ; Han Xu 
; linux-kernel@vger.kernel.org; linux-...@vger.kernel.org; 
marek.va...@gmail.com; Frieder Schrempf ; 
broo...@kernel.org; linux-...@lists.infradead.org; miquel.ray...@bootlin.com; 
Fabio Estevam ; David Wolfe ; 
computersforpe...@gmail.com; dw...@infradead.org
Subject: RE: [PATCH 03/11] spi: Add a driver for the Freescale/NXP QuadSPI 
controller

Hi Boris,

-Original Message-
From: Boris Brezillon [mailto:boris.brezil...@bootlin.com] 
Sent: Monday, June 11, 2018 3:46 PM
To: Yogesh Narayan Gaur 
Cc: marek.va...@gmail.com; Frieder Schrempf ; 
linux-...@lists.infradead.org; linux-...@vger.kernel.org; dw...@infradead.org; 
computersforpe...@gmail.com; rich...@nod.at; miquel.ray...@bootlin.com; 
broo...@kernel.org; David Wolfe ; Fabio Estevam 
; Prabhakar Kushwaha ; Han 
Xu ; linux-kernel@vger.kernel.org
Subject: Re: [PATCH 03/11] spi: Add a driver for the Freescale/NXP QuadSPI 
controller

On Mon, 11 Jun 2018 09:38:14 +
Yogesh Narayan Gaur  wrote:

> > > Observation 3:
> > > As we can support JFFS2 filesystem on NOR flash, so we can expect JFFS2 
> > > commands should work fine on NOR flash.
> > > But with this driver change my mount command is not working.
> > > 
> > > In my target there are 2 flash slave devices connected, and I have given 
> > > argument to create MTD partition like 
> > > "mtdparts=20c.quadspi-1:5M(rcw),10M(test),46M(rootfs) " for 2nd flash.
> > > Below is output for /proc/mtd commands
> > > root@ls1012ardb:~# cat /proc/mtd
> > > dev:size   erasesize  name
> > > mtd0: 0400 0004 "20c.quadspi-0"   --> First 64MB flash
> > > mtd1: 0050 0004 "rcw"   --> 
> > > Second 64 MB flash device, 3 MTD partition are created for it.
> > > mtd2: 00a0 0004 "test"
> > > mtd3: 02e0 0004 "rootfs"

When I do mtd1 + mtd2 + mtd3, I end up with 0x3d0 instead of 0x400. Is 
that normal? Do you reserve a bit of space at the end or is it that rcw is not 
starting at 0?

I have given partition size n bootargs as 
mtdparts=20c.quadspi-1:5M(rcw),10M(test),46M(rootfs)
5 + 10 + 46 ==> 61M i.e. 0x3d0.
I have just reserve the bit at the end, we can modify these settings also.

> > > 
> > > root@ls1012ardb:~# mkdir /media/ram ; flash_eraseall /dev/mtd3
> > > flash_eraseall has been replaced by `flash_erase  0 0`; 
> > > please use it
> > > Erasing 256 Kibyte @ 0 --  0 % complete [   18.299929] random: crng 
> > > init done
> > > Erasing 256 Kibyte @ 2dc -- 100 % complete
> > > root@ls1012ardb:~# mount -t jffs2 /dev/mtdblock3 /media/ram/
> > > 
> > > This command didn't finish successfully and there are lot of messages 
> > > coming on console mentioning failure in jffs2_scan_eraseblock()
> > > [  187.118677] jffs2: jffs2_scan_eraseblock(): Magic bitmask 
> > > 0x1985 not found at 0x013c: 0x2886 instead

>> Did you try to create a smaller partition? Maybe we have a problem when 
>> accessing addresses higher than X with the new driver (X to be determined).

> Would try and update you.

I have tried JFFS2 mounting with smaller partition size but still getting 
failure.
For partition size equal or less than 1MB, getting errors as
[   25.044930] jffs2: Too few erase blocks (4)
Thus, need to have size more than 1MB.

For 2MB partition size getting error message from jffs2_scan_eraseblock().
root@ls1012ardb:~# cat /proc/mtd
dev:size   erasesize  name
mtd0: 0400 0004 "20c.quadspi-0"
mtd1: 0050 0004 "rcw"
mtd2: 00a0 0004 "test"
mtd3: 0020 0004 "rootfs"
root@ls1012ardb:~#  mkdir /media/ram ; flash_eraseall /dev/mtd3
flash_eraseall has been replaced by `flash_erase  0 0`; please use 
it
Erasing 256 Kibyte @ 1c -- 100 % complete
root@ls1012ardb:~# mount -t jffs2 /dev/mtdblock3 /media/ram/
[   26.380989] jffs2: jffs2_scan_eraseblock(): Magic bitmask 0x1985 not 
found at 0x: 0x0dd0 instead
[   26.390509] jffs2: jffs2_scan_eraseblock(): Magic bitmask 0x1985 not 
found at 0x004c: 0x7366 instead
[   26.39] jffs2: jffs2_scan_eraseblock(): Magic bitmask 0x1985 not 
found at 0x0050: 0x736c instead

--
Regards
Yogesh Gaur

> > > [  187.128159] jffs2: jffs2_scan_eraseblock(): Magic bitmask 0x1985 
> > > not found at 0x013c0004: 0x7a3

RE: [PATCH 03/11] spi: Add a driver for the Freescale/NXP QuadSPI controller

[Yogesh Narayan Gaur]

Hi Boris,

-Original Message-
From: Boris Brezillon [mailto:boris.brezil...@bootlin.com] 
Sent: Tuesday, June 12, 2018 12:43 PM
To: Yogesh Narayan Gaur 
Cc: rich...@nod.at; Prabhakar Kushwaha ; Han Xu 
; linux-kernel@vger.kernel.org; linux-...@vger.kernel.org; 
marek.va...@gmail.com; Frieder Schrempf ; 
broo...@kernel.org; linux-...@lists.infradead.org; miquel.ray...@bootlin.com; 
Fabio Estevam ; David Wolfe ; 
computersforpe...@gmail.com; dw...@infradead.org
Subject: Re: [PATCH 03/11] spi: Add a driver for the Freescale/NXP QuadSPI 
controller

On Tue, 12 Jun 2018 06:42:42 +
Yogesh Narayan Gaur  wrote:

> I have tried JFFS2 mounting with smaller partition size but still getting 
> failure.
> For partition size equal or less than 1MB, getting errors as
> [   25.044930] jffs2: Too few erase blocks (4)
> Thus, need to have size more than 1MB.
> 
> For 2MB partition size getting error message from jffs2_scan_eraseblock().
> root@ls1012ardb:~# cat /proc/mtd
> dev:size   erasesize  name
> mtd0: 0400 0004 "20c.quadspi-0"
> mtd1: 0050 0004 "rcw"
> mtd2: 00a0 0004 "test"
> mtd3: 0020 0004 "rootfs"
> root@ls1012ardb:~#  mkdir /media/ram ; flash_eraseall /dev/mtd3
> flash_eraseall has been replaced by `flash_erase  0 0`; please 
> use it
> Erasing 256 Kibyte @ 1c -- 100 % complete
> root@ls1012ardb:~# mount -t jffs2 /dev/mtdblock3 /media/ram/
> [   26.380989] jffs2: jffs2_scan_eraseblock(): Magic bitmask 0x1985 not 
> found at 0x: 0x0dd0 instead
> [   26.390509] jffs2: jffs2_scan_eraseblock(): Magic bitmask 0x1985 not 
> found at 0x004c: 0x7366 instead
> [   26.39] jffs2: jffs2_scan_eraseblock(): Magic bitmask 0x1985 not 
> found at 0x0050: 0x736c instead

That's weird. Can you tell me on which platform you're testing?
lsxxx or vf610? Can you dump the NOR after the erase to make sure the memory is 
actually erased (filled with 0xff)?

I am working on lsxxx platform. With further debugging, I found that my erase 
operation for second flash device is not working properly.
Need to have debugging for this in Frieder Patch.

When I have created multiple partition for First flash device, then JFFS2 
mounting and booting of Linux kernel from rootfstype=jffs2 is successful.
root@ls1012ardb:~# cat /proc/mtd
dev:size   erasesize  name
mtd0: 0050 0004 "rcw"
mtd1: 00a0 0004 "test"
mtd2: 02e0 0004 "rootfs"
mtd3: 0400 0004 "20c.quadspi-1"
In above list, for MTD2 partition, able to perform JFFS2 mounting.

Below is logs of erase for both flashes:
root@ls1012ardb:~# cat /proc/mtd
dev:size   erasesize  name
mtd0: 0400 0004 "20c.quadspi-0"
mtd1: 0400 0004 "20c.quadspi-1"
root@ls1012ardb:~# mtd_debug erase /dev/mtd0 0x100 0x200
Erased 33554432 bytes from address 0x0100 in flash
root@ls1012ardb:~#
root@ls1012ardb:~# mtd_debug read /dev/mtd0 0x100 0xa0 rp
Copied 10485760 bytes from address 0x0100 in flash to rp
root@ls1012ardb:~# hexdump rp
000        
*
0a0
root@ls1012ardb:~#
root@ls1012ardb:~# mtd_debug erase /dev/mtd1 0x100 0x200
 [   25.023027] random: crng init done
Erased 33554432 bytes from address 0x0100 in flash
root@ls1012ardb:~# mtd_debug read /dev/mtd1 0x100 0xa0 rp
Copied 10485760 bytes from address 0x0100 in flash to rp
root@ls1012ardb:~#
root@ls1012ardb:~# hexdump rp
000 1985 2003 000c  b0b1 e41e  
010        
*
004 1985 2003 000c  b0b1 e41e  
0040010        

--
Yogesh Gaur

RE: [PATCH 03/11] spi: Add a driver for the Freescale/NXP QuadSPI controller

[Yogesh Narayan Gaur]

.@bootlin.com; 
linux-...@vger.kernel.org
Cc: dw...@infradead.org; computersforpe...@gmail.com; marek.va...@gmail.com; 
rich...@nod.at; miquel.ray...@bootlin.com; broo...@kernel.org; David Wolfe 
; Fabio Estevam ; Prabhakar 
Kushwaha ; Yogesh Narayan Gaur 
; Han Xu ; Frieder Schrempf 
; linux-kernel@vger.kernel.org
Subject: [PATCH 03/11] spi: Add a driver for the Freescale/NXP QuadSPI 
controller

This driver is derived from the SPI NOR driver at mtd/spi-nor/fsl-quadspi.c. It 
uses the new SPI memory interface of the SPI framework to issue flash memory 
operations to up to four connected flash chips (2 buses with 2 CS each).

The controller does not support generic SPI messages.

Signed-off-by: Frieder Schrempf 
---
 drivers/spi/Kconfig|  11 +
 drivers/spi/Makefile   |   1 +
 drivers/spi/spi-fsl-qspi.c | 929 
 3 files changed, 941 insertions(+)

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index e62ac32..6de0df5 
100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -251,6 +251,17 @@ config SPI_FSL_LPSPI
help
  This enables Freescale i.MX LPSPI controllers in master mode.
 
+config SPI_FSL_QSPI
+   tristate "Freescale QSPI controller"
+   depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE || COMPILE_TEST
+   depends on HAS_IOMEM
+   help
+ This enables support for the Quad SPI controller in master mode.
+ Up to four flash chips can be connected on two buses with two
+ chipselects each.
+ This controller does not support generic SPI messages. It only
+ supports the high-level SPI memory interface.
+
 config SPI_GPIO
tristate "GPIO-based bitbanging SPI Master"
depends on GPIOLIB || COMPILE_TEST
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index cb1f437..a8f7fda 
100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -43,6 +43,7 @@ obj-$(CONFIG_SPI_FSL_DSPI)+= spi-fsl-dspi.o
 obj-$(CONFIG_SPI_FSL_LIB)  += spi-fsl-lib.o
 obj-$(CONFIG_SPI_FSL_ESPI) += spi-fsl-espi.o
 obj-$(CONFIG_SPI_FSL_LPSPI)+= spi-fsl-lpspi.o
+obj-$(CONFIG_SPI_FSL_QSPI) += spi-fsl-qspi.o
 obj-$(CONFIG_SPI_FSL_SPI)  += spi-fsl-spi.o
 obj-$(CONFIG_SPI_GPIO) += spi-gpio.o
 obj-$(CONFIG_SPI_IMG_SPFI) += spi-img-spfi.o
diff --git a/drivers/spi/spi-fsl-qspi.c b/drivers/spi/spi-fsl-qspi.c new file 
mode 100644 index 000..c16d070
--- /dev/null
+++ b/drivers/spi/spi-fsl-qspi.c
@@ -0,0 +1,929 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * Freescale QuadSPI driver.
+ *
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2018 Bootlin
+ * Copyright (C) 2018 Exceet Electronics GmbH
+ *
+ * Transition to SPI MEM interface:
+ * Author:
+ * Boris Brezillion 
+ * Frieder Schrempf 
+ *
+ * Based on the original fsl-quadspi.c spi-nor driver:
+ * Author: Freescale Semiconductor, Inc.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+/*
+ * The driver only uses one single LUT entry, that is updated on
+ * each call of exec_op(). Index 0 is preset at boot with a basic
+ * read operation, so let's use the last entry (15).
+ */
+#defineSEQID_LUT   15
+
+/* Registers used by the driver */
+#define QUADSPI_MCR0x00
+#define QUADSPI_MCR_RESERVED_MASK  (0xF << 16)
+#define QUADSPI_MCR_MDIS_MASK  BIT(14)
+#define QUADSPI_MCR_CLR_TXF_MASK   BIT(11)
+#define QUADSPI_MCR_CLR_RXF_MASK   BIT(10)
+#define QUADSPI_MCR_DDR_EN_MASKBIT(7)
+#define QUADSPI_MCR_END_CFG_MASK   (0x3 << 2)
+#define QUADSPI_MCR_SWRSTHD_MASK   BIT(1)
+#define QUADSPI_MCR_SWRSTSD_MASK   BIT(0)
+
+#define QUADSPI_IPCR   0x08
+#define QUADSPI_IPCR_SEQID_SHIFT   24
+
+#define QUADSPI_BUF3CR 0x1c
+#define QUADSPI_BUF3CR_ALLMST_MASK BIT(31)
+#define QUADSPI_BUF3CR_ADATSZ_SHIFT8
+#define QUADSPI_BUF3CR_ADATSZ_MASK (0xFF << QUADSPI_BUF3CR_ADATSZ_SHIFT)
+
+#define QUADSPI_BFGENCR0x20
+#define QUADSPI_BFGENCR_SEQID_SHIFT12
+
+#define QUADSPI_BUF0IND0x30
+#define QUADSPI_BUF1IND0x34
+#define QUADSPI_BUF2IND0x38
+#define QUADSPI_SFAR   0x100
+
+#define QUADSPI_SMPR   0x108
+#define QUADSPI_SMPR_DDRSMP_MASK   (7 << 16)
+#define QUADSPI_SMPR_FSDLY_MASKBIT(6)
+#define QUADSPI_SMPR_FSPHS_MASKBIT(5)
+#define QUADSPI_SMPR_HSENA_MASKBIT(0)
+
+#define QUADSPI_RBCT   0x110
+#define QUADSPI_RBCT_WMRK_MASK 0x1F
+#define QUADSPI_RBCT_RXBRD_USEIPS  BIT(8)
+

RE: [PATCH 03/11] spi: Add a driver for the Freescale/NXP QuadSPI controller

[Yogesh Narayan Gaur]

-Original Message-
From: Boris Brezillon [mailto:boris.brezil...@bootlin.com] 
Sent: Friday, June 15, 2018 7:26 PM
To: Yogesh Narayan Gaur ; Fabio Estevam 
; David Wolfe ; dw...@infradead.org
Cc: rich...@nod.at; Prabhakar Kushwaha ; Han Xu 
; linux-kernel@vger.kernel.org; linux-...@vger.kernel.org; 
marek.va...@gmail.com; Frieder Schrempf ; 
broo...@kernel.org; linux-...@lists.infradead.org; miquel.ray...@bootlin.com; 
computersforpe...@gmail.com
Subject: Re: [PATCH 03/11] spi: Add a driver for the Freescale/NXP QuadSPI 
controller

On Fri, 15 Jun 2018 13:42:12 +
Yogesh Narayan Gaur  wrote:

> Hi Boris,
> 
> I am still debugging the issue.
> With some analysis, able to check that proper values are not being written 
> for QUADSPI_SFA2AD/ QUADSPI_SFB1AD/ QUADSPI_SFB2AD register.
> 
> In current code, value of map_addr are being assigned to these register.
>  map_addr = q->memmap_phy +
> 2 * q->devtype_data->ahb_buf_size;
> 
>  qspi_writel(q, map_addr, q->iobase + QUADSPI_SFA1AD + (i * 4));
> 
> But instead of "q->devtype_data->ahb_buf_size" it should be flash size.

No, because we're only using 2 * ->ahb_buf_size in the direct mapping for each 
device, and we're modifying the mapping dynamically based on the selected 
device. Maybe we got the logic wrong though.

Yes, for register QUADSPI_SFA2AD/ QUADSPI_SFB1AD/ QUADSPI_SFB2AD, we need to 
save starting actual address from where this flash is getting started.
Thus, if my first flash size is 64MB, then register QUADSPI_SFA2AD would have 
value of q->memmap_phy + 0x400 i.e. (QUADSPI_SFA1AD + sizeof First Flash)
If second flash is of size 32MB, then register QUADSPI_SFB1AD would have value 
of value of QUADSPI_SFA2AD + sizeof second flash.

> For my case flash size is 0x400 and with this hard coded value I am able 
> to perform Write and Erase operation.
> One more change, I have to do is adding the flash_size when writing the 
> base_address in SFAR register for case when "mem->spi->chip_select == 1"
>   qspi_writel(q, q->memmap_phy + 0x400, base + QUADSPI_SFAR);

I don't want to expose the full device in the direct mapping yet (that's part 
of the direct-mapping API I posted here [1]). What this version of the driver 
does is, map only 2 time the ahb_size so that we can bypass the internal cache 
of the QSPI engine.

To perform any operation on second flash, we need to provide it's base address 
should be saved in SFAR register for this particular operation.
Exposing only 2 time of ahb_size is design decision but value in SFAR register 
should be correct.

> 
> Thus, there should be mechanism or the entry in structure where we can have 
> the information of the size of the connected slave device.

Because that's exactly the kind of thing I'd like to avoid. What if the device 
is bigger than the reserved memory region? What if the sum of all devices does 
not fit in there? Here I tried to support all cases by just mapping the portion 
of memory we need.

So IMO, there should be mechanism to have value of start address of each slave 
device. This might can be done from DTS entry of each slave device connected to 
the controller.

RE: [PATCH] mtd: spi-nor: honour max_data_size for spi-nor writes

[Yogesh Narayan Gaur]

Hi Boris,


-Original Message-
From: Boris Brezillon [mailto:boris.brezil...@bootlin.com] 
Sent: Monday, June 11, 2018 3:19 PM
To: Yogesh Narayan Gaur 
Cc: linux-...@lists.infradead.org; boris.brezil...@free-electrons.com; 
frieder.schre...@exceet.de; computersforpe...@gmail.com; David Wolfe 
; Han Xu ; feste...@gmail.com; 
marek.va...@gmail.com; Prabhakar Kushwaha ; 
linux-...@vger.kernel.org; linux-kernel@vger.kernel.org; NeilBrown 

Subject: Re: [PATCH] mtd: spi-nor: honour max_data_size for spi-nor writes

Hi Yogesh,

Unrelated note: no need to send your patches to both 
boris.brezi...@free-electrons.com and boris.brezi...@bootlin.com, just use the 
latter.

Ok, Sure.

On Mon, 11 Jun 2018 14:48:14 +0530
Yogesh Gaur  wrote:

> Honour max_data_size for spi-nor writes

^ This is no longer relevant.

> In new spi-mem framework, data size to be written is being calculated 
> using spi_mem_adjust_op_size().
> This can return value less than nor->page_size.
> 
> Add check value of data size return from API spi_mem_adjust_op_size() 
> with the actual requested data size and write, max, only supported 
> data size.

This part is not clear.

Also, I'd prefer to have this patch split in 2:
1/ one patch removing the check in spi_nor_write() 2/ and the second patch 
removing the while() loop in m25p80_write()

How about the following commit messages for those 2 patches:

1:
"
mtd: spi-nor: Support controllers with limited TX FIFO size

Some SPI controllers can't write nor->page_size bytes in a single step because 
their TX FIFO is too small.

Allow nor->write() to return a size that is smaller than the requested write 
size to gracefully handle this case.
"

2:
"
mtd: devices: m25p80: Make sure WRITE_EN is issued before each write

Some SPI controllers can't write nor->page_size bytes in a single step because 
their TX FIFO is too small, but when that happens we should make sure a 
WRITE_EN command is issued before each write access.

The core is already taking care of that, so all we have to do here is return 
the actual number of bytes that were written during the
spi_mem_exec_op() operation.
"

Both patches send [1][2]

--
Regards
Yogesh Gaur.

> 
> Signed-off-by: NeilBrown 
> Signed-off-by: Yogesh Gaur 
> ---
>  drivers/mtd/devices/m25p80.c  | 23 ---  
> drivers/mtd/spi-nor/spi-nor.c |  7 ---
>  2 files changed, 8 insertions(+), 22 deletions(-)
> 
> diff --git a/drivers/mtd/devices/m25p80.c 
> b/drivers/mtd/devices/m25p80.c index e84563d..60224fe 100644
> --- a/drivers/mtd/devices/m25p80.c
> +++ b/drivers/mtd/devices/m25p80.c
> @@ -72,7 +72,6 @@ static ssize_t m25p80_write(struct spi_nor *nor, loff_t to, 
> size_t len,
>  SPI_MEM_OP_ADDR(nor->addr_width, to, 1),
>  SPI_MEM_OP_DUMMY(0, 1),
>  SPI_MEM_OP_DATA_OUT(len, buf, 1));
> - size_t remaining = len;
>   int ret;
>  
>   /* get transfer protocols. */
> @@ -84,22 +83,16 @@ static ssize_t m25p80_write(struct spi_nor *nor, loff_t 
> to, size_t len,
>   if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
>   op.addr.nbytes = 0;
>  
> - while (remaining) {
> - op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX;
> - ret = spi_mem_adjust_op_size(flash->spimem, );
> - if (ret)
> - return ret;
> -
> - ret = spi_mem_exec_op(flash->spimem, );
> - if (ret)
> - return ret;
> + ret = spi_mem_adjust_op_size(flash->spimem, );
> + if (ret)
> + return ret;
> + op.data.nbytes = len < op.data.nbytes ? len : op.data.nbytes;
>  
> - op.addr.val += op.data.nbytes;
> - remaining -= op.data.nbytes;
> - op.data.buf.out += op.data.nbytes;
> - }
> + ret = spi_mem_exec_op(flash->spimem, );
> + if (ret)
> + return ret;
>  
> - return len;
> + return op.data.nbytes;
>  }
>  
>  /*
> diff --git a/drivers/mtd/spi-nor/spi-nor.c 
> b/drivers/mtd/spi-nor/spi-nor.c index 5bfa36e..3e63543 100644
> --- a/drivers/mtd/spi-nor/spi-nor.c
> +++ b/drivers/mtd/spi-nor/spi-nor.c
> @@ -1431,13 +1431,6 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t 
> to, size_t len,
>   goto write_err;
>   *retlen += written;
>   i += written;
> - if (written != page_remain) {
> - dev_err(nor->dev,
> - "While writing %zu bytes written %zd bytes\n",
> - page_remain, written);
> - ret = -EIO;
> - goto write_err;
> - }
>   }
>  
>  write_err:

[1] https://patchwork.ozlabs.org/patch/928677/
[2] https://patchwork.ozlabs.org/patch/928678/

RE: [PATCH 03/11] spi: Add a driver for the Freescale/NXP QuadSPI controller

[Yogesh Narayan Gaur]

Hi Boris,

I am still debugging the issue.
With some analysis, able to check that proper values are not being written for 
QUADSPI_SFA2AD/ QUADSPI_SFB1AD/ QUADSPI_SFB2AD register.

In current code, value of map_addr are being assigned to these register.
 map_addr = q->memmap_phy +
2 * q->devtype_data->ahb_buf_size;

 qspi_writel(q, map_addr, q->iobase + QUADSPI_SFA1AD + (i * 4));

But instead of "q->devtype_data->ahb_buf_size" it should be flash size. 
For my case flash size is 0x400 and with this hard coded value I am able to 
perform Write and Erase operation.
One more change, I have to do is adding the flash_size when writing the 
base_address in SFAR register for case when "mem->spi->chip_select == 1"
qspi_writel(q, q->memmap_phy + 0x400, base + QUADSPI_SFAR);

Thus, there should be mechanism or the entry in structure where we can have the 
information of the size of the connected slave device.

With both of above hardcoded changes, I am able to perform Write and Erase 
operation on my second flash device but still facing issue in Read operation, 
debugging in progress for that.

--
Regards
Yogesh Gaur


-Original Message-
From: Boris Brezillon [mailto:boris.brezil...@bootlin.com] 
Sent: Friday, June 15, 2018 6:20 PM
To: Yogesh Narayan Gaur 
Cc: rich...@nod.at; Prabhakar Kushwaha ; Han Xu 
; linux-kernel@vger.kernel.org; linux-...@vger.kernel.org; 
marek.va...@gmail.com; Frieder Schrempf ; 
broo...@kernel.org; linux-...@lists.infradead.org; miquel.ray...@bootlin.com; 
Fabio Estevam ; David Wolfe ; 
computersforpe...@gmail.com; dw...@infradead.org
Subject: Re: [PATCH 03/11] spi: Add a driver for the Freescale/NXP QuadSPI 
controller

On Tue, 12 Jun 2018 08:51:25 +
Yogesh Narayan Gaur  wrote:

> 
> I am working on lsxxx platform. With further debugging, I found that my erase 
> operation for second flash device is not working properly.
> Need to have debugging for this in Frieder Patch.

Did you find the problem? Could it be a wrong "reg = <>" definition in your DT 
(Frieder changed the CS numbering scheme in the new driver)?

RE: [PATCH 03/11] spi: Add a driver for the Freescale/NXP QuadSPI controller

[Yogesh Narayan Gaur]

Hi Boris,


-Original Message-
From: Boris Brezillon [mailto:boris.brezil...@bootlin.com] 
Sent: Friday, June 8, 2018 6:22 PM
To: Yogesh Narayan Gaur 
Cc: Frieder Schrempf ; 
linux-...@lists.infradead.org; linux-...@vger.kernel.org; dw...@infradead.org; 
computersforpe...@gmail.com; marek.va...@gmail.com; rich...@nod.at; 
miquel.ray...@bootlin.com; broo...@kernel.org; David Wolfe 
; Fabio Estevam ; Prabhakar 
Kushwaha ; Han Xu ; 
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 03/11] spi: Add a driver for the Freescale/NXP QuadSPI 
controller

Hi Yogesh,

On Fri, 8 Jun 2018 11:54:12 +
Yogesh Narayan Gaur  wrote:

> Hi Frieder,
> 
> I have tried to validate your patch on fsl,ls2080a target having 2 Spansion 
> NOR flash, S25FS512S, as slave device.
> Below are my observations:
> 
> Observation 1:
> In Linux boot logs after driver probing is successful, getting below log 
> messages
> [1.435986] m25p80 spi0.0: found s25fl512s, expected m25p80
> [1.441564] m25p80 spi0.0: s25fl512s (65536 Kbytes)
> [1.446972] m25p80 spi0.1: found s25fl512s, expected m25p80
> [1.452548] m25p80 spi0.1: s25fl512s (65536 Kbytes)
> 
> IMHO, we need to correct message as 'found s25fl512s, expected m25p80' as 
> final underlying connected flash device is s25fl512s.

Not sure what you mean here. What would you like us to fix exactly?

> 
> Observation 2:
> I have observed data sanity issue after performing read/write 
> operations using MTD interface. Explained below
> 
> root:~# mtd_debug erase /dev/mtd0 0x100 0x4
> Erased 262144 bytes from address 0x0100 in flash  --> 
> Erase at address 0x100 of erase size 0x4
> root:~# mtd_debug read /dev/mtd0 0x0 0x100 rp
> Copied 256 bytes from address 0x in flash to rp   --> 
> Read 0x100 bytes from flash from address 0x0 in file rp
> root:~# mtd_debug write /dev/mtd0 0x100 0x100 rp
> Copied 256 bytes from rp to address 0x0100 in flash   --> 
> Write 0x100 bytes to flash address 0x100 from file rp
> root:~# mtd_debug read /dev/mtd0 0x100 0x100 wp
> Copied 256 bytes from address 0x0100 in flash to wp  --> 
> Read 0x100 bytes from flash from address 0x100 in file wp
> root:~# diff rp wp
>--> compare both rp and wp files, if they are 
> different output comes on console stating file are different
> Files rp and wp differ
> root:~# hexdump wp
> 000 aa55 aa55  8010 541c 4000 0040 
> 010        000a
> 020  0030   11a0 00a0 2580 
> 030   0040  005b   
> 040        
> *
> 100
> root:~# hexdump rp
> 000 aa55 aa55  8010 541c 4000 0040 
> 010        000a
> 020  0030   11a0 00a0 2580 
> 030   0040  005b   
> 040 2403       
> 050        
> *
> 070 0011  09e7   4411 9555 0050
> 080     f9bc afa1 0404 31e0
> 090   0400 31e0  2010 08dc 31eb
> 0a0 2880 0050 1300 31eb 4e20 8010  80ff
> 0b0   beef dead beef dead beef dead
> 0c0 beef dead beef dead beef dead beef dead
> *
> 100
> root:~#
> 
> In hexdump output of the file which being read from address 0x100,wp, it 
> can be observed that only first 64 bytes (0x40) are written on the flash.
> 
> Observation 3:
> As we can support JFFS2 filesystem on NOR flash, so we can expect JFFS2 
> commands should work fine on NOR flash.
> But with this driver change my mount command is not working.
> 
> In my target there are 2 flash slave devices connected, and I have given 
> argument to create MTD partition like 
> "mtdparts=20c.quadspi-1:5M(rcw),10M(test),46M(rootfs) " for 2nd flash.
> Below is output for /proc/mtd commands
> root@ls1012ardb:~# cat /proc/mtd
> dev:size   erasesize  name
> mtd0: 0400 0004 "20c.quadspi-0"   --> First 64MB flash
> mtd1: 0050 0004 "rcw"   --> Second 64 
> MB flash device, 3 MTD partition are created for it.
> mtd2: 00a0 0004 "test"
> mtd3: 02e0 0004 "rootfs"
> 
> root@ls1012ardb:~# mkdir /media/ram ; flash_eraseall /dev/mtd3
> flash_eraseall has been replaced by `flash_erase  0 0`; please 
> use it
> Erasing 256 Kibyte @ 0 --  0 % complete [   18.299929] random: crng init 
> done
> Eras

RE: [PATCH 03/11] spi: Add a driver for the Freescale/NXP QuadSPI controller

[Yogesh Narayan Gaur]

Hi Boris,

-Original Message-
From: Boris Brezillon [mailto:boris.brezil...@bootlin.com] 
Sent: Monday, June 11, 2018 1:16 PM
To: Yogesh Narayan Gaur ; marek.va...@gmail.com
Cc: Frieder Schrempf ; 
linux-...@lists.infradead.org; linux-...@vger.kernel.org; dw...@infradead.org; 
computersforpe...@gmail.com; rich...@nod.at; miquel.ray...@bootlin.com; 
broo...@kernel.org; David Wolfe ; Fabio Estevam 
; Prabhakar Kushwaha ; Han 
Xu ; linux-kernel@vger.kernel.org
Subject: Re: [PATCH 03/11] spi: Add a driver for the Freescale/NXP QuadSPI 
controller

Hi Yogesh,

On Mon, 11 Jun 2018 06:31:00 +
Yogesh Narayan Gaur  wrote:

> 
> > 
> > Observation 2:
> > I have observed data sanity issue after performing read/write 
> > operations using MTD interface. Explained below
> > 
> > root:~# mtd_debug erase /dev/mtd0 0x100 0x4
> > Erased 262144 bytes from address 0x0100 in flash  
> > --> Erase at address 0x100 of erase size 0x4
> > root:~# mtd_debug read /dev/mtd0 0x0 0x100 rp
> > Copied 256 bytes from address 0x in flash to rp   
> > --> Read 0x100 bytes from flash from address 0x0 in file rp
> > root:~# mtd_debug write /dev/mtd0 0x100 0x100 rp
> > Copied 256 bytes from rp to address 0x0100 in flash   
> > --> Write 0x100 bytes to flash address 0x100 from file rp
> > root:~# mtd_debug read /dev/mtd0 0x100 0x100 wp
> > Copied 256 bytes from address 0x0100 in flash to wp  
> > --> Read 0x100 bytes from flash from address 0x100 in file wp
> > root:~# diff rp wp  
> >  --> compare both rp and wp files, if they 
> > are different output comes on console stating file are different
> > Files rp and wp differ
> > root:~# hexdump wp
> > 000 aa55 aa55  8010 541c 4000 0040 
> > 010        000a
> > 020  0030   11a0 00a0 2580 
> > 030   0040  005b   
> > 040        
> > *
> > 100
> > root:~# hexdump rp
> > 000 aa55 aa55  8010 541c 4000 0040 
> > 010        000a
> > 020  0030   11a0 00a0 2580 
> > 030   0040  005b   
> > 040 2403       
> > 050        
> > *
> > 070 0011  09e7   4411 9555 0050
> > 080     f9bc afa1 0404 31e0
> > 090   0400 31e0  2010 08dc 31eb
> > 0a0 2880 0050 1300 31eb 4e20 8010  80ff
> > 0b0   beef dead beef dead beef dead
> > 0c0 beef dead beef dead beef dead beef dead
> > *
> > 100
> > root:~#
> > 
> > In hexdump output of the file which being read from address 0x100,wp, 
> > it can be observed that only first 64 bytes (0x40) are written on the flash.
> > 
> > Observation 3:
> > As we can support JFFS2 filesystem on NOR flash, so we can expect JFFS2 
> > commands should work fine on NOR flash.
> > But with this driver change my mount command is not working.
> > 
> > In my target there are 2 flash slave devices connected, and I have given 
> > argument to create MTD partition like 
> > "mtdparts=20c.quadspi-1:5M(rcw),10M(test),46M(rootfs) " for 2nd flash.
> > Below is output for /proc/mtd commands
> > root@ls1012ardb:~# cat /proc/mtd
> > dev:size   erasesize  name
> > mtd0: 0400 0004 "20c.quadspi-0"   --> First 64MB flash
> > mtd1: 0050 0004 "rcw"   --> Second 
> > 64 MB flash device, 3 MTD partition are created for it.
> > mtd2: 00a0 0004 "test"
> > mtd3: 02e0 0004 "rootfs"
> > 
> > root@ls1012ardb:~# mkdir /media/ram ; flash_eraseall /dev/mtd3
> > flash_eraseall has been replaced by `flash_erase  0 0`; please 
> > use it
> > Erasing 256 Kibyte @ 0 --  0 % complete [   18.299929] random: crng 
> > init done
> > Erasing 256 Kibyte @ 2dc -- 100 % complete
> > root@ls1012ardb:~# mount -t jffs2 /dev/mtdblock3 /media/ram/
> > 
> > This command didn't finish successfully and there are lot of messages 
> > coming on console mentioning failure in jffs2_scan_eraseblock()
> > [  187.118677] jffs2: jffs2_scan_eraseblock(): Magic bitmask 0x1985 not 
> > found at 0x013c: 0x2886

RE: [PATCH 03/11] spi: Add a driver for the Freescale/NXP QuadSPI controller

[Yogesh Narayan Gaur]

Hi Boris,

-Original Message-
From: Boris Brezillon [mailto:boris.brezil...@bootlin.com] 
Sent: Monday, June 11, 2018 3:46 PM
To: Yogesh Narayan Gaur 
Cc: marek.va...@gmail.com; Frieder Schrempf ; 
linux-...@lists.infradead.org; linux-...@vger.kernel.org; dw...@infradead.org; 
computersforpe...@gmail.com; rich...@nod.at; miquel.ray...@bootlin.com; 
broo...@kernel.org; David Wolfe ; Fabio Estevam 
; Prabhakar Kushwaha ; Han 
Xu ; linux-kernel@vger.kernel.org
Subject: Re: [PATCH 03/11] spi: Add a driver for the Freescale/NXP QuadSPI 
controller

On Mon, 11 Jun 2018 09:38:14 +
Yogesh Narayan Gaur  wrote:

> > > Observation 3:
> > > As we can support JFFS2 filesystem on NOR flash, so we can expect JFFS2 
> > > commands should work fine on NOR flash.
> > > But with this driver change my mount command is not working.
> > > 
> > > In my target there are 2 flash slave devices connected, and I have given 
> > > argument to create MTD partition like 
> > > "mtdparts=20c.quadspi-1:5M(rcw),10M(test),46M(rootfs) " for 2nd flash.
> > > Below is output for /proc/mtd commands
> > > root@ls1012ardb:~# cat /proc/mtd
> > > dev:size   erasesize  name
> > > mtd0: 0400 0004 "20c.quadspi-0"   --> First 64MB flash
> > > mtd1: 0050 0004 "rcw"   --> 
> > > Second 64 MB flash device, 3 MTD partition are created for it.
> > > mtd2: 00a0 0004 "test"
> > > mtd3: 02e0 0004 "rootfs"

When I do mtd1 + mtd2 + mtd3, I end up with 0x3d0 instead of 0x400. Is 
that normal? Do you reserve a bit of space at the end or is it that rcw is not 
starting at 0?

I have given partition size n bootargs as 
mtdparts=20c.quadspi-1:5M(rcw),10M(test),46M(rootfs)
5 + 10 + 46 ==> 61M i.e. 0x3d0.
I have just reserve the bit at the end, we can modify these settings also.

> > > 
> > > root@ls1012ardb:~# mkdir /media/ram ; flash_eraseall /dev/mtd3
> > > flash_eraseall has been replaced by `flash_erase  0 0`; 
> > > please use it
> > > Erasing 256 Kibyte @ 0 --  0 % complete [   18.299929] random: crng 
> > > init done
> > > Erasing 256 Kibyte @ 2dc -- 100 % complete
> > > root@ls1012ardb:~# mount -t jffs2 /dev/mtdblock3 /media/ram/
> > > 
> > > This command didn't finish successfully and there are lot of messages 
> > > coming on console mentioning failure in jffs2_scan_eraseblock()
> > > [  187.118677] jffs2: jffs2_scan_eraseblock(): Magic bitmask 
> > > 0x1985 not found at 0x013c: 0x2886 instead

Did you try to create a smaller partition? Maybe we have a problem when 
accessing addresses higher than X with the new driver (X to be determined).

Would try and update you.

--
Regards
Yogesh Gaur

> > > [  187.128159] jffs2: jffs2_scan_eraseblock(): Magic bitmask 0x1985 
> > > not found at 0x013c0004: 0x7a3b instead
> > > [  187.137641] jffs2: jffs2_scan_eraseblock(): Magic bitmask
> > > 0x1985 not found at 0x013c0008: 0xb10f instead
> > > 

RE: [PATCH 03/11] spi: Add a driver for the Freescale/NXP QuadSPI controller

[Yogesh Narayan Gaur]

Hi Frieder,

Thanks for migrating the fsl-quadspi.c driver on the new SPI framework. 
This patch is using dynamic LUT approach to create the LUT at run time instead 
of fixed static LUT as being used in current driver present at 
mtd/spi-nor/fsl-quadspi.c.
I have pushed the changes for dynamic LUT on mtd/spi-nor/fsl-quadspi.c and v10 
has been in review stage.

Request you to please add 'signed-off' mentioned in those patches in this 
patch, patchwork link is https://patchwork.ozlabs.org/patch/896534/

Thanks
Yogesh Gaur

-Original Message-
From: Frieder Schrempf [mailto:frieder.schre...@exceet.de] 
Sent: Wednesday, May 30, 2018 6:45 PM
To: linux-...@lists.infradead.org; boris.brezil...@bootlin.com; 
linux-...@vger.kernel.org
Cc: dw...@infradead.org; computersforpe...@gmail.com; marek.va...@gmail.com; 
rich...@nod.at; miquel.ray...@bootlin.com; broo...@kernel.org; David Wolfe 
; Fabio Estevam ; Prabhakar 
Kushwaha ; Yogesh Narayan Gaur 
; Han Xu ; Frieder Schrempf 
; linux-kernel@vger.kernel.org
Subject: [PATCH 03/11] spi: Add a driver for the Freescale/NXP QuadSPI 
controller

This driver is derived from the SPI NOR driver at mtd/spi-nor/fsl-quadspi.c. It 
uses the new SPI memory interface of the SPI framework to issue flash memory 
operations to up to four connected flash chips (2 buses with 2 CS each).

The controller does not support generic SPI messages.

Signed-off-by: Frieder Schrempf 
---
 drivers/spi/Kconfig|  11 +
 drivers/spi/Makefile   |   1 +
 drivers/spi/spi-fsl-qspi.c | 929 
 3 files changed, 941 insertions(+)

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index e62ac32..6de0df5 
100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -251,6 +251,17 @@ config SPI_FSL_LPSPI
help
  This enables Freescale i.MX LPSPI controllers in master mode.
 
+config SPI_FSL_QSPI
+   tristate "Freescale QSPI controller"
+   depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE || COMPILE_TEST
+   depends on HAS_IOMEM
+   help
+ This enables support for the Quad SPI controller in master mode.
+ Up to four flash chips can be connected on two buses with two
+ chipselects each.
+ This controller does not support generic SPI messages. It only
+ supports the high-level SPI memory interface.
+
 config SPI_GPIO
tristate "GPIO-based bitbanging SPI Master"
depends on GPIOLIB || COMPILE_TEST
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index cb1f437..a8f7fda 
100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -43,6 +43,7 @@ obj-$(CONFIG_SPI_FSL_DSPI)+= spi-fsl-dspi.o
 obj-$(CONFIG_SPI_FSL_LIB)  += spi-fsl-lib.o
 obj-$(CONFIG_SPI_FSL_ESPI) += spi-fsl-espi.o
 obj-$(CONFIG_SPI_FSL_LPSPI)+= spi-fsl-lpspi.o
+obj-$(CONFIG_SPI_FSL_QSPI) += spi-fsl-qspi.o
 obj-$(CONFIG_SPI_FSL_SPI)  += spi-fsl-spi.o
 obj-$(CONFIG_SPI_GPIO) += spi-gpio.o
 obj-$(CONFIG_SPI_IMG_SPFI) += spi-img-spfi.o
diff --git a/drivers/spi/spi-fsl-qspi.c b/drivers/spi/spi-fsl-qspi.c new file 
mode 100644 index 000..c16d070
--- /dev/null
+++ b/drivers/spi/spi-fsl-qspi.c
@@ -0,0 +1,929 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * Freescale QuadSPI driver.
+ *
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2018 Bootlin
+ * Copyright (C) 2018 Exceet Electronics GmbH
+ *
+ * Transition to SPI MEM interface:
+ * Author:
+ * Boris Brezillion 
+ * Frieder Schrempf 
+ *
+ * Based on the original fsl-quadspi.c spi-nor driver:
+ * Author: Freescale Semiconductor, Inc.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+/*
+ * The driver only uses one single LUT entry, that is updated on
+ * each call of exec_op(). Index 0 is preset at boot with a basic
+ * read operation, so let's use the last entry (15).
+ */
+#defineSEQID_LUT   15
+
+/* Registers used by the driver */
+#define QUADSPI_MCR0x00
+#define QUADSPI_MCR_RESERVED_MASK  (0xF << 16)
+#define QUADSPI_MCR_MDIS_MASK  BIT(14)
+#define QUADSPI_MCR_CLR_TXF_MASK   BIT(11)
+#define QUADSPI_MCR_CLR_RXF_MASK   BIT(10)
+#define QUADSPI_MCR_DDR_EN_MASKBIT(7)
+#define QUADSPI_MCR_END_CFG_MASK   (0x3 << 2)
+#define QUADSPI_MCR_SWRSTHD_MASK   BIT(1)
+#define QUADSPI_MCR_SWRSTSD_MASK   BIT(0)
+
+#define QUADSPI_IPCR   0x08
+#define QUADSPI_IPCR_SEQID_SHIFT   24
+
+#define QUADSPI_BUF3CR 0x1c
+#define QUADSPI_BUF3CR_ALLMST_MASK BIT(31)
+#define QUADSPI_BUF3CR_ADATSZ_SHIFT8
+#define QUADSPI_BUF3CR_ADATSZ_MASK (0xFF << QUADSPI_BUF3CR_AD

RE: [PATCH 03/11] spi: Add a driver for the Freescale/NXP QuadSPI controller

[Yogesh Narayan Gaur]

Hi Boris,

-Original Message-
From: Boris Brezillon [mailto:boris.brezil...@bootlin.com] 
Sent: Tuesday, June 19, 2018 12:46 AM
To: Yogesh Narayan Gaur 
Cc: Fabio Estevam ; David Wolfe ; 
dw...@infradead.org; rich...@nod.at; Prabhakar Kushwaha 
; Han Xu ; 
linux-kernel@vger.kernel.org; linux-...@vger.kernel.org; marek.va...@gmail.com; 
Frieder Schrempf ; broo...@kernel.org; 
linux-...@lists.infradead.org; miquel.ray...@bootlin.com; 
computersforpe...@gmail.com
Subject: Re: [PATCH 03/11] spi: Add a driver for the Freescale/NXP QuadSPI 
controller

Hi Yogesh,

On Mon, 18 Jun 2018 13:32:27 +
Yogesh Narayan Gaur  wrote:

> -Original Message-
> From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> Sent: Friday, June 15, 2018 7:26 PM
> To: Yogesh Narayan Gaur ; Fabio Estevam 
> ; David Wolfe ; 
> dw...@infradead.org
> Cc: rich...@nod.at; Prabhakar Kushwaha ; 
> Han Xu ; linux-kernel@vger.kernel.org; 
> linux-...@vger.kernel.org; marek.va...@gmail.com; Frieder Schrempf 
> ; broo...@kernel.org; 
> linux-...@lists.infradead.org; miquel.ray...@bootlin.com; 
> computersforpe...@gmail.com
> Subject: Re: [PATCH 03/11] spi: Add a driver for the Freescale/NXP 
> QuadSPI controller
> 
> On Fri, 15 Jun 2018 13:42:12 +
> Yogesh Narayan Gaur  wrote:
> 
> > Hi Boris,
> > 
> > I am still debugging the issue.
> > With some analysis, able to check that proper values are not being written 
> > for QUADSPI_SFA2AD/ QUADSPI_SFB1AD/ QUADSPI_SFB2AD register.
> > 
> > In current code, value of map_addr are being assigned to these register.
> >  map_addr = q->memmap_phy +
> > 2 * q->devtype_data->ahb_buf_size;
> > 
> >  qspi_writel(q, map_addr, q->iobase + QUADSPI_SFA1AD + (i * 4));
> > 
> > But instead of "q->devtype_data->ahb_buf_size" it should be flash size.  
> 
> No, because we're only using 2 * ->ahb_buf_size in the direct mapping for 
> each device, and we're modifying the mapping dynamically based on the 
> selected device. Maybe we got the logic wrong though.
> 
> Yes, for register QUADSPI_SFA2AD/ QUADSPI_SFB1AD/ QUADSPI_SFB2AD, we need to 
> save starting actual address from where this flash is getting started.
> Thus, if my first flash size is 64MB, then register QUADSPI_SFA2AD 
> would have value of q->memmap_phy + 0x400 i.e. (QUADSPI_SFA1AD + sizeof 
> First Flash) If second flash is of size 32MB, then register QUADSPI_SFB1AD 
> would have value of value of QUADSPI_SFA2AD + sizeof second flash.

Again, no, that's not what I'm trying to do, and the fact that it worked fine 
with CS0 makes me think you don't need to map the whole device to get it to 
work, just 2 * ->ahb_buf_size per device.

> 
> > For my case flash size is 0x400 and with this hard coded value I am 
> > able to perform Write and Erase operation.
> > One more change, I have to do is adding the flash_size when writing the 
> > base_address in SFAR register for case when "mem->spi->chip_select == 1"
> > qspi_writel(q, q->memmap_phy + 0x400, base + QUADSPI_SFAR);
> 
> I don't want to expose the full device in the direct mapping yet (that's part 
> of the direct-mapping API I posted here [1]). What this version of the driver 
> does is, map only 2 time the ahb_size so that we can bypass the internal 
> cache of the QSPI engine.
> 
> To perform any operation on second flash, we need to provide it's base 
> address should be saved in SFAR register for this particular operation.

That's what we tried to do, we tried to make all CS start at 0 when they are 
used and declare unused CS at having a size of 0.

So, say you're trying to access CS1, you should have the following
ranges:

CS0: 0 -> 0 (size = 0)
CS1: 0 -> 2 * ->ahb_buf_size (size = 2 * ->ahb_buf_size)
CS2: 2 * ->ahb_buf_size -> 2 * ->ahb_buf_size (size = 0)
CS3: 2 * ->ahb_buf_size -> 2 * ->ahb_buf_size (size = 0)

now, if you're trying to access CS3:

CS0: 0 -> 0 (size = 0)
CS1: 0 -> 0 (size = 0)
CS2: 0 -> 0 (size = 0)
CS3: 0 -> 2 * ->ahb_buf_size (size = 2 * ->ahb_buf_size)

maybe this approach does not work, but that's not clearly stated as 'not 
supported' in the datasheet.

> Exposing only 2 time of ahb_size is design decision but value in SFAR 
> register should be correct.
> 
> > 
> > Thus, there should be mechanism or the entry in structure where we can have 
> > the information of the size of the connected slave device.  
> 
> Because that's exactly the kind of thing I'd like to avoid. What if the 
> device is bigger than the reserved memory region? What if the sum of all 
> devices does not fit in there? Here I tried to support all cases by j

RE: [PATCH 03/11] spi: Add a driver for the Freescale/NXP QuadSPI controller

[Yogesh Narayan Gaur]

Hi Boris,

> -Original Message-
> From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> Sent: Tuesday, June 19, 2018 12:59 PM
> To: Yogesh Narayan Gaur ;
> marek.va...@gmail.com; Frieder Schrempf ;
> broo...@kernel.org
> Cc: Fabio Estevam ; David Wolfe
> ; dw...@infradead.org; rich...@nod.at; Prabhakar
> Kushwaha ; Han Xu ; linux-
> ker...@vger.kernel.org; linux-...@vger.kernel.org; linux-
> m...@lists.infradead.org; miquel.ray...@bootlin.com;
> computersforpe...@gmail.com
> Subject: Re: [PATCH 03/11] spi: Add a driver for the Freescale/NXP QuadSPI
> controller
> 
> Hi Yogesh,
> 
> Could you please use a mailer that is quoting things correctly. I have a hard 
> time
> differentiating your replies from mine.

Sorry for this, have changed my mailer settings.

> 
> On Tue, 19 Jun 2018 07:10:37 +
> Yogesh Narayan Gaur  wrote:
> 
> > Let us take below layout of memory address space map.
> > QuadSPI Controller can access range from 0x2000_ - 0x2FFF_ i.e. 256
> MB address space reserved and it is having 4 slave devices connected.
> > These slave devices[of size 64MB, 64MB, 32MB and 64MB ] are connected
> > at below address 0x2000_, 0x2400_, 0x2A00_, 0x2C00_
> > i.e. there is gap of 32MB from 0x2800_ to 0x29FF_.
> 
> Okay, I'm fine with pre-reserving 32MB per chip select.
> 
> >
> > As per my understanding of the controller, flash XX top address, register 
> > should
> have below values:
> >   QUADSPI_SFA1AD - 0x0
> >   QUADSPI_SFA2AD - 0x400_
> >   QUADSPI_SFB1AD - 0xA00_
> >   QUADSPI_SFB2AD - 0xC00_
> > And Register QUADSPI_SFAR should point to the range for the flash in which
> operation is happening.

My mistake values of these register would be for said case are:
QUADSPI_SFA1AD - 0x400_
QUADSPI_SFA2AD - 0x800_
QUADSPI_SFB1AD - 0xC00_
QUADSPI_SFB2AD - 0x1000_

i.e. as per controller each register is having the Top address for serial flash 
connected at A1/A2/B1/B2 respectively.

> 
> Wait, I thought it was supposed to be an absolute address, not one relative to
> the 0x2000 offset.
> 
> >
> > Please check Table10-32, page 1657, in [1] for more details on flash address
> assignment.
> 
> Yes, I still don't see where it says that having one of the range with a zero 
> size is
> forbidden, or anything mentioning a required alignment.
> 
> >
> > But say if I assign address to register QUADSPI_SFA2AD as "0 + 2 * -
> >ahb_buf_size" then this address value is not correct as per the value range
> explained in above mentioned table.
> 
> Why? If the SFA1AD is set to zero, that should not, right?
What this table says that for TOP_ADDR_MEMA1 defines the top address for flash 
connected at A1 and any address space between TOP_ADDR_MEMA1 and QSPI_AMBA_BASE 
will be routed to Serial Flash A1.
In my example case TOP_ADDR_MEMA1 is 0x400_
If assign value to SFAR register is "0 + 2 * ->ahb_buf_size", then this would 
lie in access range of Serial Flash A1 and access happens to A1 flash whereas 
we want access to A2 flash.

For access of serial flash A2, any address space access between TOP_ADDR_MEMA2 
and TOP_ADDR_MEMA1 would be routed to serial flash A2.
Thus to access A2 flash, SFAR would be in range from 0x400_ and 0x800_

--
Regards
Yogesh Gaur

RE: [PATCH 3/7] spi: spi-mem: Add a driver for NXP FlexSPI controller

[Yogesh Narayan Gaur]

Hi Boris,

> -Original Message-
> From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> Sent: Thursday, September 6, 2018 5:14 PM
> To: Yogesh Narayan Gaur 
> Cc: Frieder Schrempf ; linux-
> m...@lists.infradead.org; marek.va...@gmail.com; linux-...@vger.kernel.org;
> devicet...@vger.kernel.org; r...@kernel.org; mark.rutl...@arm.com;
> shawn...@kernel.org; linux-arm-ker...@lists.infradead.org;
> computersforpe...@gmail.com; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH 3/7] spi: spi-mem: Add a driver for NXP FlexSPI controller
> 
> On Thu, 6 Sep 2018 11:35:13 +
> Yogesh Narayan Gaur  wrote:
> 
> > Hi Frieder,
> >
> > > -Original Message-
> > > From: Frieder Schrempf [mailto:frieder.schre...@exceet.de]
> > > Sent: Thursday, September 6, 2018 1:56 PM
> > > To: Yogesh Narayan Gaur ; Boris
> > > Brezillon 
> > > Cc: linux-...@lists.infradead.org; marek.va...@gmail.com; linux-
> > > s...@vger.kernel.org; devicet...@vger.kernel.org; r...@kernel.org;
> > > mark.rutl...@arm.com; shawn...@kernel.org; linux-arm-
> > > ker...@lists.infradead.org; computersforpe...@gmail.com; linux-
> > > ker...@vger.kernel.org
> > > Subject: Re: [PATCH 3/7] spi: spi-mem: Add a driver for NXP FlexSPI
> > > controller
> > > >> Hi Yogesh,
> > > >>
> > > >> On Fri, 31 Aug 2018 16:00:00 +0530 Yogesh Gaur
> > > >>  wrote:
> > > >>
> > > >>> - Add a driver for NXP FlexSPI host controller
> > > >>>
> > > >>
> > > >> Yep, I had a quick look at the code and they really look similar.
> > > >> Why not extending the existing driver instead of creating a new
> > > >> one from scratch?
> > > >
> > > > FlexSPI is different controller not related to the QuadSPI
> > > > controller in its working behavior Both these controller are
> > > > having
> > > > * Different registers name, registers address, registers
> > > > functionality etc, section 30.5.2[1]
> > > > * Different programming sequence for initialization of the
> > > > controller, section 30.8.1[1]
> > > > * Different programming sequence for performing Read and Write
> > > > operation using IP, section 30.7.9[1] and AHB mode
> > > > * Different programming sequence for checking controller current
> > > > state like busy or not
> > > > * New mechanism to program for the connected slave device i.e.
> > > > flash access mode and flash memory map 30.7.4[1] and 30.7.5[1]
> > > > * New entries added for FlexSPI controller for LUT_XX mode for
> > > > various commands, section 30.7.8[1]
> > > >
> > > > There are few similarities between these two like LUT programming
> > > > logic is same i.e. LUT needs to be programmed in same sequence of
> > > > 'INSTR
> > > PAD  OPCODE', but again LUT register address and LUT command mode
> > > values are different.
> > > >
> > > > Creating common driver for both FlexSPI and QuadSPI controller,
> > > > would
> > > involve creation of one more layer between driver/spi/spi-xxx and
> > > the actual controller driver, this layer would going to have less
> > > functionality like doing LUT creation programming and then would
> > > re-direct calls to the respective controller driver functionality to
> > > perform desired programming sequence.
> > > >
> > > >>>
> > > >>> (1) The FlexSPI controller is driven by the LUT(Look-up Table)
> > > >>> registers.
> > > >>>   The LUT registers are a look-up-table for sequences of
> > > >>> instructions. A valid sequence consists of four LUT registers.
> > > >>>   Maximum 32 LUT sequences can be programmed simultaneously.
> > > >>>
> > > >>
> > > >> Do we really want to have this level of details in the commit
> > > >> message? I mean, this is something you can document in the
> > > >> driver, but not here.
> > > >>
> > > >> BTW, you might want to have a look at [1]. I think we can get rid
> > > >> of the ->size field you're adding if this driver implements the
> > > >> dirmap hooks.
> > > >
> > > > I need size information for the connected device to program the
> > > > controller
> > > register FLSHXXCRO as Flash Chip select is determined 

RE: [PATCH 3/7] spi: spi-mem: Add a driver for NXP FlexSPI controller

[Yogesh Narayan Gaur]

Hi Frieder,

> -Original Message-
> From: Frieder Schrempf [mailto:frieder.schre...@exceet.de]
> Sent: Thursday, September 6, 2018 1:56 PM
> To: Yogesh Narayan Gaur ; Boris Brezillon
> 
> Cc: linux-...@lists.infradead.org; marek.va...@gmail.com; linux-
> s...@vger.kernel.org; devicet...@vger.kernel.org; r...@kernel.org;
> mark.rutl...@arm.com; shawn...@kernel.org; linux-arm-
> ker...@lists.infradead.org; computersforpe...@gmail.com; linux-
> ker...@vger.kernel.org
> Subject: Re: [PATCH 3/7] spi: spi-mem: Add a driver for NXP FlexSPI controller
> 
> >> Hi Yogesh,
> >>
> >> On Fri, 31 Aug 2018 16:00:00 +0530
> >> Yogesh Gaur  wrote:
> >>
> >>> - Add a driver for NXP FlexSPI host controller
> >>>
> >>
> >> Yep, I had a quick look at the code and they really look similar. Why
> >> not extending the existing driver instead of creating a new one from 
> >> scratch?
> >>
> >
> > FlexSPI is different controller not related to the QuadSPI controller
> > in its working behavior Both these controller are having
> > * Different registers name, registers address, registers functionality
> > etc, section 30.5.2[1]
> > * Different programming sequence for initialization of the controller,
> > section 30.8.1[1]
> > * Different programming sequence for performing Read and Write
> > operation using IP, section 30.7.9[1] and AHB mode
> > * Different programming sequence for checking controller current state
> > like busy or not
> > * New mechanism to program for the connected slave device i.e. flash
> > access mode and flash memory map 30.7.4[1] and 30.7.5[1]
> > * New entries added for FlexSPI controller for LUT_XX mode for various
> > commands, section 30.7.8[1]
> >
> > There are few similarities between these two like LUT programming
> > logic is same i.e. LUT needs to be programmed in same sequence of 'INSTR
> PAD  OPCODE', but again LUT register address and LUT command mode values
> are different.
> >
> > Creating common driver for both FlexSPI and QuadSPI controller, would
> involve creation of one more layer between driver/spi/spi-xxx and the actual
> controller driver, this layer would going to have less functionality like 
> doing LUT
> creation programming and then would re-direct calls to the respective 
> controller
> driver functionality to perform desired programming sequence.
> >
> >>>
> >>> (1) The FlexSPI controller is driven by the LUT(Look-up Table)
> >>> registers.
> >>>   The LUT registers are a look-up-table for sequences of instructions.
> >>>   A valid sequence consists of four LUT registers.
> >>>   Maximum 32 LUT sequences can be programmed simultaneously.
> >>>
> >>
> >> Do we really want to have this level of details in the commit message?
> >> I mean, this is something you can document in the driver, but not here.
> >>
> >> BTW, you might want to have a look at [1]. I think we can get rid of
> >> the ->size field you're adding if this driver implements the dirmap hooks.
> >>
> >
> > I need size information for the connected device to program the controller
> register FLSHXXCRO as Flash Chip select is determined by flash access address
> and Flash size setting in register FLSHXXCR0[FLSHz], section 30.7.9[1].
> 
> It's the same situation we had with the QSPI driver before. We decided to
> **not** pass information about flash size directly to the controller for now.
> That's why we currently don't support mapping the flash device in the
> implementation of the QSPI driver.
> 
> I think we should not start this discussion all over again for the FlexSPI 
> driver, but
> stick to what we decided for QSPI.
> 

There is difference between FlexSPI and QuadSPI controller functionality in 
detecting the current CS.

As per table-10.32[1] for QuadSPI controller, access to flash is being assigned 
as per the address values provided i.e. it would be CS0 if address is between 
TOP_ADDR_MEMXX and QSPI_AMBA_BASE and CS1 if access is in between 
TOP_ADDR_MEMA2 and TOP_ADDR_MEMA1.

But for case of FlexSPI controller, section 30.7.5[2],  CS is being defined as 
per the address value lies in below range
- Flash A1 address range: 0x ~ FA1_SIZE
- Flash A2 address range: FA1_SIZE ~ (FA1_SIZE + FA2_SIZE)
- Flash B1 address range: (FA1_SIZE + FA2_SIZE) ~ (FA1_SIZE + FA2_SIZE + 
FB1_SIZE)
- Flash B2 address range: FA1_SIZE + FA2_SIZE + FB1_SIZE) ~ (FA1_SIZE + 
FA2_SIZE + FB1_SIZE + FB2_SIZE)
and FAx_SIZE is determined from register FLSHxxCR0[FLASHSZ]

Thus, for QuadSPI controller we can actually go away with the fla

RE: [PATCH 3/7] spi: spi-mem: Add a driver for NXP FlexSPI controller

[Yogesh Narayan Gaur]

Hi Boris,

> -Original Message-
> From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> Sent: Tuesday, September 4, 2018 8:29 PM
> To: Yogesh Narayan Gaur 
> Cc: linux-...@lists.infradead.org; marek.va...@gmail.com; linux-
> s...@vger.kernel.org; devicet...@vger.kernel.org; r...@kernel.org;
> mark.rutl...@arm.com; shawn...@kernel.org; linux-arm-
> ker...@lists.infradead.org; computersforpe...@gmail.com;
> frieder.schre...@exceet.de; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH 3/7] spi: spi-mem: Add a driver for NXP FlexSPI controller
> 
> Hi Yogesh,
> 
> On Fri, 31 Aug 2018 16:00:00 +0530
> Yogesh Gaur  wrote:
> 
> > - Add a driver for NXP FlexSPI host controller
> >
> > (0) What is the FlexSPI controller?
> >  FlexSPI is a flexsible SPI host controller which supports two SPI
> > channels and up to 4 external devices.
> >  Each channel supports Single/Dual/Quad/Octal mode data  transfer
> > (1/2/4/8 bidirectional data lines)  i.e. FlexSPI acts as an interface
> > to external devices,  maximum 4, each with up to 8 bidirectional data
> > lines.
> >
> >  It uses new SPI memory interface of the SPI framework to issue flash
> > memory operations to up to four connected flash chips (2 buses with
> >  2 CS each).
> >  Chipselect for each flash can be selected as per address assigned in
> > controller specific registers.
> >
> >  FlexSPI controller is similar to the existing Freescale/NXP QuadSPI
> > controller with advanced features.
> 
> Yep, I had a quick look at the code and they really look similar. Why not
> extending the existing driver instead of creating a new one from scratch?
> 

FlexSPI is different controller not related to the QuadSPI controller in its 
working behavior
Both these controller are having
* Different registers name, registers address, registers functionality etc, 
section 30.5.2[1]
* Different programming sequence for initialization of the controller, section 
30.8.1[1]
* Different programming sequence for performing Read and Write operation using 
IP, section 30.7.9[1] and AHB mode
* Different programming sequence for checking controller current state like 
busy or not 
* New mechanism to program for the connected slave device i.e. flash access 
mode and flash memory map 30.7.4[1] and 30.7.5[1]
* New entries added for FlexSPI controller for LUT_XX mode for various 
commands, section 30.7.8[1]

There are few similarities between these two like LUT programming logic is same
i.e. LUT needs to be programmed in same sequence of 'INSTR  PAD  OPCODE', but 
again LUT register address and LUT command mode values are different.

Creating common driver for both FlexSPI and QuadSPI controller, would involve 
creation of one more layer between driver/spi/spi-xxx and the actual controller 
driver, this layer would going to have less functionality like doing LUT 
creation programming and then would re-direct calls to the respective 
controller driver functionality to perform desired programming sequence.

> >
> > (1) The FlexSPI controller is driven by the LUT(Look-up Table)
> > registers.
> >  The LUT registers are a look-up-table for sequences of instructions.
> >  A valid sequence consists of four LUT registers.
> >  Maximum 32 LUT sequences can be programmed simultaneously.
> >
> > (2) The definition of the LUT register shows below:
> >  ---
> >  | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
> >  ---
> >
> >  There are several types of INSTRx, such as:
> >  CMD : the SPI NOR command.
> >  ADDR: the address for the SPI NOR command.
> >  DUMMY   : the dummy cycles needed by the SPI NOR command.
> >  
> >
> >  There are several types of PADx, such as:
> >  PAD1: use a singe I/O line.
> >  PAD2: use two I/O lines.
> >  PAD4: use quad I/O lines.
> >  PAD8: use octal I/O lines.
> >  
> >
> > (3) LUTs are being created at run-time based on the commands passed
> > from the spi-mem framework. Thus, using single LUT index.
> >
> > (4) Software triggered Flash read/write access by IP Bus.
> >
> > (5) Memory mapped read access by AHB Bus.
> 
> Do we really want to have this level of details in the commit message?
> I mean, this is something you can document in the driver, but not here.
> 
> BTW, you might want to have a look at [1]. I think we can get rid of the 
> ->size
> field you're adding if this driver implements the dirmap hooks.
> 

I need size information for the connected device to program the controller 
register FLSHXXCRO as Flash Chip select is determined by flash

RE: [PATCH v3 1/5] spi: spi-mem: Add driver for NXP FlexSPI controller

[Yogesh Narayan Gaur]

Hi Boris,

> -Original Message-
> From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> Sent: Saturday, September 29, 2018 9:10 PM
> To: Yogesh Narayan Gaur 
> Cc: linux-...@lists.infradead.org; marek.va...@gmail.com; linux-
> s...@vger.kernel.org; devicet...@vger.kernel.org; r...@kernel.org;
> mark.rutl...@arm.com; shawn...@kernel.org; linux-arm-
> ker...@lists.infradead.org; computersforpe...@gmail.com;
> frieder.schre...@exceet.de; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH v3 1/5] spi: spi-mem: Add driver for NXP FlexSPI 
> controller
> 
> Hi Yogesh,
> 
> On Fri, 21 Sep 2018 15:51:59 +0530
> Yogesh Gaur  wrote:
> 
> > +/* Registers used by the driver */
> > +#define FSPI_MCR0  0x00
> > +#define FSPI_MCR0_AHB_TIMEOUT_SHIFT24
> > +#define FSPI_MCR0_AHB_TIMEOUT_MASK (0xFF <<
> FSPI_MCR0_AHB_TIMEOUT_SHIFT)
> > +#define FSPI_MCR0_IP_TIMEOUT_SHIFT 16
> > +#define FSPI_MCR0_IP_TIMEOUT_MASK  (0xFF <<
> FSPI_MCR0_IP_TIMEOUT_SHIFT)
> > +#define FSPI_MCR0_LEARN_EN_SHIFT   15
> > +#define FSPI_MCR0_LEARN_EN_MASK(1 <<
> FSPI_MCR0_LEARN_EN_SHIFT)
> > +#define FSPI_MCR0_SCRFRUN_EN_SHIFT 14
> > +#define FSPI_MCR0_SCRFRUN_EN_MASK  (1 <<
> FSPI_MCR0_SCRFRUN_EN_SHIFT)
> > +#define FSPI_MCR0_OCTCOMB_EN_SHIFT 13
> > +#define FSPI_MCR0_OCTCOMB_EN_MASK  (1 <<
> FSPI_MCR0_OCTCOMB_EN_SHIFT)
> > +#define FSPI_MCR0_DOZE_EN_SHIFT12
> > +#define FSPI_MCR0_DOZE_EN_MASK (1 <<
> FSPI_MCR0_DOZE_EN_SHIFT)
> > +#define FSPI_MCR0_HSEN_SHIFT   11
> > +#define FSPI_MCR0_HSEN_MASK(1 << FSPI_MCR0_HSEN_SHIFT)
> > +#define FSPI_MCR0_SERCLKDIV_SHIFT  8
> > +#define FSPI_MCR0_SERCLKDIV_MASK   (7 <<
> FSPI_MCR0_SERCLKDIV_SHIFT)
> > +#define FSPI_MCR0_ATDF_EN_SHIFT7
> > +#define FSPI_MCR0_ATDF_EN_MASK (1 <<
> FSPI_MCR0_ATDF_EN_SHIFT)
> > +#define FSPI_MCR0_ARDF_EN_SHIFT6
> > +#define FSPI_MCR0_ARDF_EN_MASK (1 <<
> FSPI_MCR0_ARDF_EN_SHIFT)
> > +#define FSPI_MCR0_RXCLKSRC_SHIFT   4
> > +#define FSPI_MCR0_RXCLKSRC_MASK(3 <<
> FSPI_MCR0_RXCLKSRC_SHIFT)
> > +#define FSPI_MCR0_END_CFG_SHIFT2
> > +#define FSPI_MCR0_END_CFG_MASK (3 <<
> FSPI_MCR0_END_CFG_SHIFT)
> > +#define FSPI_MCR0_MDIS_SHIFT   1
> > +#define FSPI_MCR0_MDIS_MASK(1 << FSPI_MCR0_MDIS_SHIFT)
> > +#define FSPI_MCR0_SWRST_SHIFT  0
> > +#define FSPI_MCR0_SWRST_MASK   (1 <<
> FSPI_MCR0_SWRST_SHIFT)
> 
> Do we really need all those _SHIFT/_MASK defs? I mean
> 

Changes done in next version of the patch series, v4 [1].

> #define FSPI_MCR0_SWRST   BIT(0)
> 
> or
> 
> #define FSPI_MCR0_AHB_TIMEOUT(x)  ((x) << 24)
> #define FSPI_MCR0_AHB_TIMEOUT_MASKGENMASK(31, 24)
> 
> are just fine.
> 
> > +
> > +enum nxp_fspi_devtype {
> > +   NXP_FSPI_LX2160A,
> > +};
> 
> I'm pretty sure you don't need this enum if you describe all dev caps in the
> nxp_fspi_devtype_data struct.

Done, in v4.

> 
> > +
> > +struct nxp_fspi_devtype_data {
> > +   enum nxp_fspi_devtype devtype;
> > +   unsigned int rxfifo;
> > +   unsigned int txfifo;
> > +   unsigned int ahb_buf_size;
> > +   unsigned int quirks;
> > +   bool endianness;
> 
> How about renaming this variable big_endian and dropping the {L,B}_ENDIAN
> macros?
> 
Done in v4, default make as little_endian to reduce indirect branch checking.

> > +};
> 
> [...]
> 
> > +struct nxp_fspi {
> > +   void __iomem *iobase;
> > +   void __iomem *ahb_addr;
> > +   u32 memmap_phy;
> > +   u32 memmap_phy_size;
> > +   struct clk *clk, *clk_en;
> > +   struct device *dev;
> > +   struct completion c;
> > +   const struct nxp_fspi_devtype_data *devtype_data;
> > +   struct mutex lock;
> > +   struct pm_qos_request pm_qos_req;
> > +   int selected;
> > +   void (*write)(u32 val, void __iomem *addr);
> > +   u32 (*read)(void __iomem *addr);
> > +};
> > +
> > +static void fspi_writel_be(u32 val, void __iomem *addr) {
> > +   iowrite32be(val, addr);
> > +}
> > +
> > +static void fspi_writel(u32 val, void __iomem *addr) {
> > +   iowrite32(val, addr);
> > +}
> > +
> > +static u32 fspi_readl_be(void __iomem *addr) {
> > +   return ioread32be(addr);
> > +}
> > +
> > +static u32 fspi_readl(void __iomem *addr) {
> > +   return ioread32(addr);
> >

RE: [PATCH v2 2/2] mtd: spi-nor: add entry for mt35xu512aba flash

[Yogesh Narayan Gaur]

Hi Tudor,

> -Original Message-
> From: Tudor Ambarus [mailto:tudor.amba...@microchip.com]
> Sent: Thursday, October 11, 2018 9:33 PM
> To: Yogesh Narayan Gaur ; linux-
> m...@lists.infradead.org; linux-...@vger.kernel.org
> Cc: marek.va...@gmail.com; cyrille.pitc...@wedev4u.fr;
> boris.brezil...@bootlin.com; computersforpe...@gmail.com;
> frieder.schre...@exceet.de; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH v2 2/2] mtd: spi-nor: add entry for mt35xu512aba flash
> 
> 
> 
> On 10/11/2018 11:15 AM, Yogesh Narayan Gaur wrote:
> > Add entry for mt35xu512aba Micron NOR flash.
> > This flash is having uniform sector erase size of 128KB, have support
> > of FSR(flag status register), flash size is 64MB and supports 4-byte
> > commands.
> >
> > Signed-off-by: Yogesh Gaur 
> > ---
> > Changes for v2:
> > - Removed checkpatch warning, 80 character limit.
> >
> >  drivers/mtd/spi-nor/spi-nor.c | 4 
> >  1 file changed, 4 insertions(+)
> >
> > diff --git a/drivers/mtd/spi-nor/spi-nor.c
> > b/drivers/mtd/spi-nor/spi-nor.c index b8b494f..e0d95ac 100644
> > --- a/drivers/mtd/spi-nor/spi-nor.c
> > +++ b/drivers/mtd/spi-nor/spi-nor.c
> > @@ -1405,6 +1405,10 @@ static const struct flash_info spi_nor_ids[] = {
> > { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR
> | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
> > { "mt25qu02g",   INFO(0x20bb22, 0, 64 * 1024, 4096, SECT_4K |
> USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
> >
> > +   /* Micron */
> > +   { "mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512,
> > +   SECT_4K | USE_FSR | SPI_NOR_4B_OPCODES) },
> > +
> 
> The style is slightly different from what Brian proposed back in
> 9648388fc7737365be7a8092e77df78ccc2cd1a4. For consistency reasons, I think
> we should use the same style in all entries.
> 

Ok, I have send the next version of the patches with the style changes as 
proposed by Brian.

--
Regards
Yogesh Gaur.

> Since I verified the correctness of the patch and my comment targets just a
> cosmetic change, I'll let the maintainers decide:
> 
> Reviewed-by: Tudor Ambarus 

[PATCH v3 2/2] mtd: spi-nor: add entry for mt35xu512aba flash

[Yogesh Narayan Gaur]

Add entry for mt35xu512aba Micron NOR flash.
This flash is having uniform sector erase size of 128KB, have
support of FSR(flag status register), flash size is 64MB and
supports 4-byte commands.

Signed-off-by: Yogesh Gaur 
Reviewed-by: Tudor Ambarus 
---
Changes for v3:
- Modified flash node style as suggested by Tudor.
Changes for v2:
- Removed checkpatch warning, 80 character limit.
 drivers/mtd/spi-nor/spi-nor.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index b8b494f..0b8a6e0 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -1405,6 +1405,12 @@ static int spi_nor_is_locked(struct mtd_info *mtd, 
loff_t ofs, uint64_t len)
{ "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | 
SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
{ "mt25qu02g",   INFO(0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | 
SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
 
+   /* Micron */
+   {
+   "mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512,
+   SECT_4K | USE_FSR | SPI_NOR_4B_OPCODES)
+   },
+
/* PMC */
{ "pm25lv512",   INFO(0,0, 32 * 1024,2, SECT_4K_PMC) },
{ "pm25lv010",   INFO(0,0, 32 * 1024,4, SECT_4K_PMC) },
-- 
1.9.1

[PATCH v3 1/2] mtd: spi-nor: add macros related to MICRON flash

[Yogesh Narayan Gaur]

Some MICRON related macros in spi-nor domain were ST.
Rename entries related to STMicroelectronics under macro SNOR_MFR_ST.

Added entry of MFR Id for Micron flashes, 0x002C.

Signed-off-by: Yogesh Gaur 
Reviewed-by: Tudor Ambarus 
---
Changes for v3:
- None
Changes for v2:
- None

 drivers/mtd/spi-nor/spi-nor.c | 9 ++---
 include/linux/mtd/cfi.h   | 1 +
 include/linux/mtd/spi-nor.h   | 3 ++-
 3 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 9407ca5..b8b494f 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -284,6 +284,7 @@ static inline int set_4byte(struct spi_nor *nor, const 
struct flash_info *info,
u8 cmd;
 
switch (JEDEC_MFR(info)) {
+   case SNOR_MFR_ST:
case SNOR_MFR_MICRON:
/* Some Micron need WREN command; all will accept it */
need_wren = true;
@@ -1388,7 +1389,7 @@ static int spi_nor_is_locked(struct mtd_info *mtd, loff_t 
ofs, uint64_t len)
{ "mx66l1g45g",  INFO(0xc2201b, 0, 64 * 1024, 2048, SECT_4K | 
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ "mx66l1g55g",  INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) 
},
 
-   /* Micron */
+   /* Micron <--> ST Micro */
{ "n25q016a",INFO(0x20bb15, 0, 64 * 1024,   32, SECT_4K | 
SPI_NOR_QUAD_READ) },
{ "n25q032", INFO(0x20ba16, 0, 64 * 1024,   64, SPI_NOR_QUAD_READ) 
},
{ "n25q032a",INFO(0x20bb16, 0, 64 * 1024,   64, SPI_NOR_QUAD_READ) 
},
@@ -3223,6 +3224,7 @@ static int spi_nor_init_params(struct spi_nor *nor,
params->quad_enable = macronix_quad_enable;
break;
 
+   case SNOR_MFR_ST:
case SNOR_MFR_MICRON:
break;
 
@@ -3671,8 +3673,9 @@ int spi_nor_scan(struct spi_nor *nor, const char *name,
mtd->_resume = spi_nor_resume;
 
/* NOR protection support for STmicro/Micron chips and similar */
-   if (JEDEC_MFR(info) == SNOR_MFR_MICRON ||
-   info->flags & SPI_NOR_HAS_LOCK) {
+   if (JEDEC_MFR(info) == SNOR_MFR_ST ||
+   JEDEC_MFR(info) == SNOR_MFR_MICRON ||
+   info->flags & SPI_NOR_HAS_LOCK) {
nor->flash_lock = stm_lock;
nor->flash_unlock = stm_unlock;
nor->flash_is_locked = stm_is_locked;
diff --git a/include/linux/mtd/cfi.h b/include/linux/mtd/cfi.h
index 9b57a9b..cbf7716 100644
--- a/include/linux/mtd/cfi.h
+++ b/include/linux/mtd/cfi.h
@@ -377,6 +377,7 @@ struct cfi_fixup {
 #define CFI_MFR_SHARP  0x00B0
 #define CFI_MFR_SST0x00BF
 #define CFI_MFR_ST 0x0020 /* STMicroelectronics */
+#define CFI_MFR_MICRON 0x002C /* Micron */
 #define CFI_MFR_TOSHIBA0x0098
 #define CFI_MFR_WINBOND0x00DA
 
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index 7f0c730..8b1acf6 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -23,7 +23,8 @@
 #define SNOR_MFR_ATMEL CFI_MFR_ATMEL
 #define SNOR_MFR_GIGADEVICE0xc8
 #define SNOR_MFR_INTEL CFI_MFR_INTEL
-#define SNOR_MFR_MICRONCFI_MFR_ST /* ST Micro <--> Micron */
+#define SNOR_MFR_STCFI_MFR_ST  /* ST Micro */
+#define SNOR_MFR_MICRONCFI_MFR_MICRON  /* Micron */
 #define SNOR_MFR_MACRONIX  CFI_MFR_MACRONIX
 #define SNOR_MFR_SPANSION  CFI_MFR_AMD
 #define SNOR_MFR_SST   CFI_MFR_SST
-- 
1.9.1

[PATCH v3 0/2] mtd: spi-nor: add entry for mt35xu512aba flash

[Yogesh Narayan Gaur]

Add MFR_ID information, 0x002C, related to the Micron flash.
Currently, MFR_ID 0x0020 is being specified as Micron flash ID but
these are actually CFI ID of STMicro flashes.

Rename SNOR_MFR_MICRON to SNOR_MFR_ST and add entry for
SNOR_MFR_MICRON having CFI ID value of Micron flash.
Add entry of mt35xu512aba [1] flash in spi_nor_ids table.

[1] https://www.micron.com/resource-details/0b74b806-bbf1-4c24-b07b-35e2799bb6ff

Yogesh Gaur (2):
  mtd: spi-nor: add macros related to MICRON flash
  mtd: spi-nor: add entry for mt35xu512aba flash

Changes for v3:
- Modified flash node style as suggested by Tudor.
Changes for v2:
- Removed checkpatch warning, 80 character limit, in patch
 'mtd: spi-nor: add entry for mt35xu512aba flash'.

 drivers/mtd/spi-nor/spi-nor.c | 15 ---
 include/linux/mtd/cfi.h   |  1 +
 include/linux/mtd/spi-nor.h   |  3 ++-
 3 files changed, 15 insertions(+), 4 deletions(-)

-- 
1.9.1

RE: [PATCH v2 0/7] spi: add support for octal mode

[Yogesh Narayan Gaur]

Hi Boris,

> -Original Message-
> From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> Sent: Monday, October 15, 2018 5:24 PM
> To: Yogesh Narayan Gaur 
> Cc: linux-...@lists.infradead.org; marek.va...@gmail.com; vigne...@ti.com;
> linux-...@vger.kernel.org; devicet...@vger.kernel.org; r...@kernel.org;
> mark.rutl...@arm.com; shawn...@kernel.org; linux-arm-
> ker...@lists.infradead.org; computersforpe...@gmail.com;
> frieder.schre...@exceet.de; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH v2 0/7] spi: add support for octal mode
> 
> Hi Yogesh,
> 
> On Mon, 15 Oct 2018 11:47:55 +
> Yogesh Narayan Gaur  wrote:
> 
> > Add support for octal mode IO data transfer.
> > Micron flash, mt35xu512aba, supports octal mode data transfer and NXP
> > FlexSPI controller supports 8 data lines for data transfer (Rx/Tx).
> >
> > Patch series
> > * Add support for octal mode flags and parsing of same in spi driver.
> > * Add opcodes for octal I/O commands in spi-nor framework, Read and Write
> proto for (1-1-8/1-8-8) mode.
> >   Opcodes are added as per octal data IO commands required for
> mt35xu512aba [1] flash.
> > * Add parsing logic for spi-mem framework and m25p80.c device file.
> > * Add mode bit required for octal mode in nxp-fspi driver [2].
> > * Define binding property 'spi-rx/tx-bus-width' for LX2160ARDB target [2].
> >
> > Cherry pick below 2 patches (from:
> https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.ker
> nel.org%2Fpub%2Fscm%2Flinux%2Fkernel%2Fgit%2Fbroonie%2Fspi.gitda
> ta=02%7C01%7Cyogeshnarayan.gaur%40nxp.com%7C9af69996cae344b6e7b70
> 8d63294eaf5%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C6367520
> 12521352025sdata=euwK9X2tael3Q69QO%2BirRznB%2BHKazDbumdAOp
> eZvxCc%3Dreserved=0):
> > c639f871febe6667d9afce28108c634e5636c735 spi: spi-mem: Fix inverted
> logic in op sanity check
> > db122eb8a749a1eff038f9a282c620ab16c4be1d spi: spi-mem: Add extra
> > sanity checks on the op param
> >
> > Tested on LX2160ARDB target with nxp-fspi driver, below are Read
> > performance number of 1-1-1 and 1-1-8 read protocol.
> >
> >  root@lxxx:~# cat /proc/mtd
> >  dev:size   erasesize  name
> >  mtd0: 0400 1000 "spi0.0"
> >  mtd1: 0400 1000 "spi0.1"
> >  root@lxxx:~# time mtd_debug read /dev/mtd0 0x0 0x100 0read
> > Copied 16777216 bytes from address 0x in flash to 0read
> >
> >  real0m2.792s
> >  user0m0.000s
> >  sys 0m2.790s
> >  root@lxxx:~# time mtd_debug read /dev/mtd1 0x0 0x100 0read
> > Copied 16777216 bytes from address 0x in flash to 0read
> >
> >  real0m0.441s
> >  user0m0.000s
> >  sys 0m0.440s
> >  root@ls1012ardb:~#
> >
> >  Flash device MTD0 configured in 1-1-1 protocol.
> >  Flash device MTD1 configured in 1-1-8 protocol.
> >
> > [1]
> > https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpat
> > chwork.ozlabs.org%2Fproject%2Flinux-
> mtd%2Flist%2F%3Fseries%3D70384
> > ;data=02%7C01%7Cyogeshnarayan.gaur%40nxp.com%7C9af69996cae344b6e
> 7b708d
> >
> 63294eaf5%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C636752012
> 521352
> >
> 025sdata=ldk0ny8vksO%2FayIsYX26M4akFUojtaP1YyOtpMEGJZA%3D
> mp;res
> > erved=0 [2]
> > https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpat
> > chwork.ozlabs.org%2Fproject%2Flinux-
> mtd%2Flist%2F%3Fseries%3D70210
> > ;data=02%7C01%7Cyogeshnarayan.gaur%40nxp.com%7C9af69996cae344b6e
> 7b708d
> >
> 63294eaf5%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C636752012
> 521352
> >
> 025sdata=wq%2BCnrk4Ovx4itHrZfv%2FGH5raStF91hfjHBQmO9Sjq0%3D&
> amp;r
> > eserved=0
> >
> > Yogesh Gaur (7):
> >   spi: add support for octal I/O data transfer
> >   mtd: spi-nor: add opcodes for octal Read/Write commands
> >   mtd: spi-nor: add octal read flag for flash mt35xu512aba
> >   mtd: m25p80: add support of octal I/O transfer
> >   spi: spi-mem: add support for octal I/O data transfer
> 
> Patch 5 should be moved before patch 4 (ideally in 2nd position) if you want 
> this
> series to be bisectable.
> 

Ok.
For now, order which I have selected is as per the comments from Vignesh. Would 
resend again with the suggested order.

--
Regards
Yogesh Gaur

> Regards,
> 
> Boris
> 
> >   spi: nxp-fspi: add mode flag bit for octal support
> >   arm64: dts: lx2160a: update fspi node
> >
> > Changes for v2:
> >  Incorporated review comments of Boris and Vignesh.
> >
> >  arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts |  4 
> >  drivers/mtd/devices/m25p80.c  |  9 -
> >  drivers/mtd/spi-nor/spi-nor.c | 15 ++-
> >  drivers/spi/spi-mem.c |  9 -
> >  drivers/spi/spi-nxp-fspi.c|  4 ++--
> >  drivers/spi/spi.c |  6 ++
> >  include/linux/mtd/spi-nor.h   |  8 
> >  include/linux/spi/spi.h   |  2 ++
> >  8 files changed, 52 insertions(+), 5 deletions(-)
> >

[PATCH v2 3/7] mtd: spi-nor: add octal read flag for flash mt35xu512aba

[Yogesh Narayan Gaur]

Add octal read flag for flash mt35xu512aba.
This flash, mt35xu512aba, is only complaint to SFDP JESD216B and does
not seem to support newer JESD216C standard that provides auto
detection of Octal mode capabilities and opcodes. Therefore, this
capability is manually added using new SPI_NOR_OCTAL_READ flag.

Signed-off-by: Vignesh R 
Signed-off-by: Yogesh Gaur 
---
Changes for v2:
 Incorporated review comments of Boris and Vignesh

 drivers/mtd/spi-nor/spi-nor.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 7c64ff0..574f3e6 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -1413,7 +1413,8 @@ static const struct flash_info spi_nor_ids[] = {
/* Micron */
{
"mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512,
-   SECT_4K | USE_FSR | SPI_NOR_4B_OPCODES)
+   SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ |
+   SPI_NOR_4B_OPCODES)
},
 
/* PMC */
-- 
2.7.4

[PATCH v2 2/7] mtd: spi-nor: add opcodes for octal Read/Write commands

[Yogesh Narayan Gaur]

- Add opcodes for octal I/O commands
  * Read  : 1-1-8 and 1-8-8 protocol
  * Write : 1-1-8 and 1-8-8 protocol
  * opcodes for 4-byte address mode command

- Entry of macros in _convert_3to4_xxx function

- Add flag specifying flash support octal read commands.

Signed-off-by: Vignesh R 
Signed-off-by: Yogesh Gaur 
---
Changes for v2:
 Incorporated review comments of Boris and Vignesh

 drivers/mtd/spi-nor/spi-nor.c | 12 
 include/linux/mtd/spi-nor.h   |  8 
 2 files changed, 20 insertions(+)

diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 0b8a6e0..7c64ff0 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -90,6 +90,7 @@ struct flash_info {
 #define NO_CHIP_ERASE  BIT(12) /* Chip does not support chip erase */
 #define SPI_NOR_SKIP_SFDP  BIT(13) /* Skip parsing of SFDP tables */
 #define USE_CLSR   BIT(14) /* use CLSR command */
+#define SPI_NOR_OCTAL_READ BIT(15) /* Flash supports Octal Read */
 
int (*quad_enable)(struct spi_nor *nor);
 };
@@ -209,6 +210,8 @@ static inline u8 spi_nor_convert_3to4_read(u8 opcode)
{ SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B },
{ SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },
{ SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },
+   { SPINOR_OP_READ_1_1_8, SPINOR_OP_READ_1_1_8_4B },
+   { SPINOR_OP_READ_1_8_8, SPINOR_OP_READ_1_8_8_4B },
 
{ SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B },
{ SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B },
@@ -225,6 +228,8 @@ static inline u8 spi_nor_convert_3to4_program(u8 opcode)
{ SPINOR_OP_PP, SPINOR_OP_PP_4B },
{ SPINOR_OP_PP_1_1_4,   SPINOR_OP_PP_1_1_4_4B },
{ SPINOR_OP_PP_1_4_4,   SPINOR_OP_PP_1_4_4_4B },
+   { SPINOR_OP_PP_1_1_8,   SPINOR_OP_PP_1_1_8_4B },
+   { SPINOR_OP_PP_1_8_8,   SPINOR_OP_PP_1_8_8_4B },
};
 
return spi_nor_convert_opcode(opcode, spi_nor_3to4_program,
@@ -3195,6 +3200,13 @@ static int spi_nor_init_params(struct spi_nor *nor,
  SNOR_PROTO_1_1_4);
}
 
+   if (info->flags & SPI_NOR_OCTAL_READ) {
+   params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
+   spi_nor_set_read_settings(>reads[SNOR_CMD_READ_1_1_8],
+ 0, 8, SPINOR_OP_READ_1_1_8,
+ SNOR_PROTO_1_1_8);
+   }
+
/* Page Program settings. */
params->hwcaps.mask |= SNOR_HWCAPS_PP;
spi_nor_set_pp_settings(>page_programs[SNOR_CMD_PP],
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index 8b1acf6..019f534 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -50,9 +50,13 @@
 #define SPINOR_OP_READ_1_2_2   0xbb/* Read data bytes (Dual I/O SPI) */
 #define SPINOR_OP_READ_1_1_4   0x6b/* Read data bytes (Quad Output SPI) */
 #define SPINOR_OP_READ_1_4_4   0xeb/* Read data bytes (Quad I/O SPI) */
+#define SPINOR_OP_READ_1_1_8   0x8b/* Read data bytes (Octal Output SPI) */
+#define SPINOR_OP_READ_1_8_8   0xcb/* Read data bytes (Octal I/O SPI) */
 #define SPINOR_OP_PP   0x02/* Page program (up to 256 bytes) */
 #define SPINOR_OP_PP_1_1_4 0x32/* Quad page program */
 #define SPINOR_OP_PP_1_4_4 0x38/* Quad page program */
+#define SPINOR_OP_PP_1_1_8 0x82/* Octal page program */
+#define SPINOR_OP_PP_1_8_8 0xc2/* Octal page program */
 #define SPINOR_OP_BE_4K0x20/* Erase 4KiB block */
 #define SPINOR_OP_BE_4K_PMC0xd7/* Erase 4KiB block on PMC chips */
 #define SPINOR_OP_BE_32K   0x52/* Erase 32KiB block */
@@ -73,9 +77,13 @@
 #define SPINOR_OP_READ_1_2_2_4B0xbc/* Read data bytes (Dual I/O 
SPI) */
 #define SPINOR_OP_READ_1_1_4_4B0x6c/* Read data bytes (Quad Output 
SPI) */
 #define SPINOR_OP_READ_1_4_4_4B0xec/* Read data bytes (Quad I/O 
SPI) */
+#define SPINOR_OP_READ_1_1_8_4B0x7c/* Read data bytes (Octal 
Output SPI) */
+#define SPINOR_OP_READ_1_8_8_4B0xcc/* Read data bytes (Octal I/O 
SPI) */
 #define SPINOR_OP_PP_4B0x12/* Page program (up to 256 
bytes) */
 #define SPINOR_OP_PP_1_1_4_4B  0x34/* Quad page program */
 #define SPINOR_OP_PP_1_4_4_4B  0x3e/* Quad page program */
+#define SPINOR_OP_PP_1_1_8_4B  0x84/* Octal page program */
+#define SPINOR_OP_PP_1_8_8_4B  0x8e/* Octal page program */
 #define SPINOR_OP_BE_4K_4B 0x21/* Erase 4KiB block */
 #define SPINOR_OP_BE_32K_4B0x5c/* Erase 32KiB block */
 #define SPINOR_OP_SE_4B0xdc/* Sector erase (usually 64KiB) 
*/
-- 
2.7.4

[PATCH v2 0/7] spi: add support for octal mode

[Yogesh Narayan Gaur]

Add support for octal mode IO data transfer.
Micron flash, mt35xu512aba, supports octal mode data transfer and
NXP FlexSPI controller supports 8 data lines for data transfer (Rx/Tx).

Patch series
* Add support for octal mode flags and parsing of same in spi driver.
* Add opcodes for octal I/O commands in spi-nor framework, Read and Write proto 
for (1-1-8/1-8-8) mode.
  Opcodes are added as per octal data IO commands required for mt35xu512aba [1] 
flash.
* Add parsing logic for spi-mem framework and m25p80.c device file.
* Add mode bit required for octal mode in nxp-fspi driver [2].
* Define binding property 'spi-rx/tx-bus-width' for LX2160ARDB target [2].

Cherry pick below 2 patches (from: 
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git):
c639f871febe6667d9afce28108c634e5636c735 spi: spi-mem: Fix inverted logic 
in op sanity check
db122eb8a749a1eff038f9a282c620ab16c4be1d spi: spi-mem: Add extra sanity 
checks on the op param

Tested on LX2160ARDB target with nxp-fspi driver, below are
Read performance number of 1-1-1 and 1-1-8 read protocol.

 root@lxxx:~# cat /proc/mtd
 dev:size   erasesize  name
 mtd0: 0400 1000 "spi0.0"
 mtd1: 0400 1000 "spi0.1"
 root@lxxx:~# time mtd_debug read /dev/mtd0 0x0 0x100 0read
 Copied 16777216 bytes from address 0x in flash to 0read

 real0m2.792s
 user0m0.000s
 sys 0m2.790s
 root@lxxx:~# time mtd_debug read /dev/mtd1 0x0 0x100 0read
 Copied 16777216 bytes from address 0x in flash to 0read

 real0m0.441s
 user0m0.000s
 sys 0m0.440s
 root@ls1012ardb:~#

 Flash device MTD0 configured in 1-1-1 protocol.
 Flash device MTD1 configured in 1-1-8 protocol.

[1] https://patchwork.ozlabs.org/project/linux-mtd/list/?series=70384
[2] https://patchwork.ozlabs.org/project/linux-mtd/list/?series=70210

Yogesh Gaur (7):
  spi: add support for octal I/O data transfer
  mtd: spi-nor: add opcodes for octal Read/Write commands
  mtd: spi-nor: add octal read flag for flash mt35xu512aba
  mtd: m25p80: add support of octal I/O transfer
  spi: spi-mem: add support for octal I/O data transfer
  spi: nxp-fspi: add mode flag bit for octal support
  arm64: dts: lx2160a: update fspi node

Changes for v2:
 Incorporated review comments of Boris and Vignesh.

 arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts |  4 
 drivers/mtd/devices/m25p80.c  |  9 -
 drivers/mtd/spi-nor/spi-nor.c | 15 ++-
 drivers/spi/spi-mem.c |  9 -
 drivers/spi/spi-nxp-fspi.c|  4 ++--
 drivers/spi/spi.c |  6 ++
 include/linux/mtd/spi-nor.h   |  8 
 include/linux/spi/spi.h   |  2 ++
 8 files changed, 52 insertions(+), 5 deletions(-)

-- 
2.7.4

[PATCH v2 1/7] spi: add support for octal I/O data transfer

[Yogesh Narayan Gaur]

Add flags for Octal I/O data transfer
Required for the SPI controller which can do the data transfer (TX/RX)
on 8 data lines e.g. NXP FlexSPI controller.
 SPI_TX_OCTAL: transmit with 8 wires
 SPI_RX_OCTAL: receive with 8 wires

Signed-off-by: Yogesh Gaur 
---
Changes for v2:
 Incorporated review comments of Boris.

 drivers/spi/spi.c   | 6 ++
 include/linux/spi/spi.h | 2 ++
 2 files changed, 8 insertions(+)

diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index ec395a6..80f672f 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -1573,6 +1573,9 @@ static int of_spi_parse_dt(struct spi_controller *ctlr, 
struct spi_device *spi,
case 4:
spi->mode |= SPI_TX_QUAD;
break;
+   case 8:
+   spi->mode |= SPI_TX_OCTAL;
+   break;
default:
dev_warn(>dev,
"spi-tx-bus-width %d not supported\n",
@@ -1591,6 +1594,9 @@ static int of_spi_parse_dt(struct spi_controller *ctlr, 
struct spi_device *spi,
case 4:
spi->mode |= SPI_RX_QUAD;
break;
+   case 8:
+   spi->mode |= SPI_RX_OCTAL;
+   break;
default:
dev_warn(>dev,
"spi-rx-bus-width %d not supported\n",
diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index a64235e..2d21307 100644
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -163,6 +163,8 @@ struct spi_device {
 #defineSPI_TX_QUAD 0x200   /* transmit with 4 
wires */
 #defineSPI_RX_DUAL 0x400   /* receive with 2 wires 
*/
 #defineSPI_RX_QUAD 0x800   /* receive with 4 wires 
*/
+#defineSPI_TX_OCTAL0x1000  /* transmit with 8 
wires */
+#defineSPI_RX_OCTAL0x2000  /* receive with 8 wires 
*/
int irq;
void*controller_state;
void*controller_data;
-- 
2.7.4

[PATCH v2 5/7] spi: spi-mem: add support for octal I/O data transfer

[Yogesh Narayan Gaur]

Add support for octal I/O data transfer in spi-mem framework.

Signed-off-by: Yogesh Gaur 
---
Changes for v2:
 Patch added in v2 version.

 drivers/spi/spi-mem.c | 9 -
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index c6bdea7..6fa95f8 100644
--- a/drivers/spi/spi-mem.c
+++ b/drivers/spi/spi-mem.c
@@ -12,7 +12,7 @@
 
 #include "internals.h"
 
-#define SPI_MEM_MAX_BUSWIDTH   4
+#define SPI_MEM_MAX_BUSWIDTH   8
 
 /**
  * spi_controller_dma_map_mem_op_data() - DMA-map the buffer attached to a
@@ -121,6 +121,13 @@ static int spi_check_buswidth_req(struct spi_mem *mem, u8 
buswidth, bool tx)
 
break;
 
+   case 8:
+   if ((tx && (mode & SPI_TX_OCTAL)) ||
+   (!tx && (mode & SPI_RX_OCTAL)))
+   return 0;
+
+   break;
+
default:
break;
}
-- 
2.7.4

[PATCH v2 6/7] spi: nxp-fspi: add mode flag bit for octal support

[Yogesh Narayan Gaur]

Add mode flags for octal I/O data transfer support.
NXP FlexSPI controller supports octal mode data transfer.

Signed-off-by: Yogesh Gaur 
---
Changes for v2:
 None

 drivers/spi/spi-nxp-fspi.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c
index 67eea88..c48ca94 100644
--- a/drivers/spi/spi-nxp-fspi.c
+++ b/drivers/spi/spi-nxp-fspi.c
@@ -993,8 +993,8 @@ static int nxp_fspi_probe(struct platform_device *pdev)
if (!ctlr)
return -ENOMEM;
 
-   ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD |
- SPI_TX_DUAL | SPI_TX_QUAD;
+   ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_RX_OCTAL |
+ SPI_TX_DUAL | SPI_TX_QUAD | SPI_TX_OCTAL;
 
f = spi_controller_get_devdata(ctlr);
f->dev = dev;
-- 
2.7.4

[PATCH v2 4/7] mtd: m25p80: add support of octal I/O transfer

[Yogesh Narayan Gaur]

Add support for octal I/O data transfer based on the controller (spi)
mode.
Assign hw-capability mask bits for octal transfer.

Signed-off-by: Yogesh Gaur 
---
Changes for v2:
 Incorporated review comments of Boris.

 drivers/mtd/devices/m25p80.c | 9 -
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
index cb14cf9..e5e632c 100644
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -175,7 +175,14 @@ static int m25p_probe(struct spi_mem *spimem)
spi_mem_set_drvdata(spimem, flash);
flash->spimem = spimem;
 
-   if (spi->mode & SPI_RX_QUAD) {
+   if (spi->mode & SPI_RX_OCTAL) {
+   hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
+
+   if (spi->mode & SPI_TX_OCTAL)
+   hwcaps.mask |= (SNOR_HWCAPS_READ_1_8_8 |
+   SNOR_HWCAPS_PP_1_1_8 |
+   SNOR_HWCAPS_PP_1_8_8);
+   } else if (spi->mode & SPI_RX_QUAD) {
hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
 
if (spi->mode & SPI_TX_QUAD)
-- 
2.7.4

[PATCH v2 7/7] arm64: dts: lx2160a: update fspi node

[Yogesh Narayan Gaur]

Flash mt35xu512aba connected to FlexSPI controller supports
1-1-8/1-8-8 protocol.
Added flag spi-rx-bus-width and spi-tx-bus-width with values as
8 and 8 respectively for both flashes connected at CS0 and CS1.

Signed-off-by: Yogesh Gaur 
---
Changes for v2:
 None

 arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts 
b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
index 3b20c97..24cc41c 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -45,6 +45,8 @@
m25p,fast-read;
spi-max-frequency = <2000>;
reg = <0>;
+   spi-rx-bus-width = <8>;
+   spi-tx-bus-width = <8>;
};
 
mt35xu512aba1: flash@1 {
@@ -54,6 +56,8 @@
m25p,fast-read;
spi-max-frequency = <2000>;
reg = <1>;
+   spi-rx-bus-width = <8>;
+   spi-tx-bus-width = <8>;
};
 };
 
-- 
2.7.4

[PATCH v2 4/7] mtd: spi-nor: add octal read flag for flash mt35xu512aba

[Yogesh Narayan Gaur]

Add octal read flag for flash mt35xu512aba.
This flash, mt35xu512aba, is only complaint to SFDP JESD216B and does
not seem to support newer JESD216C standard that provides auto
detection of Octal mode capabilities and opcodes. Therefore, this
capability is manually added using new SPI_NOR_OCTAL_READ flag.

Signed-off-by: Vignesh R 
Signed-off-by: Yogesh Gaur 
---
Changes for v2:
 Incorporated review comments of Boris and Vignesh

 drivers/mtd/spi-nor/spi-nor.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 7c64ff0..574f3e6 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -1413,7 +1413,8 @@ static const struct flash_info spi_nor_ids[] = {
/* Micron */
{
"mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512,
-   SECT_4K | USE_FSR | SPI_NOR_4B_OPCODES)
+   SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ |
+   SPI_NOR_4B_OPCODES)
},
 
/* PMC */
-- 
2.7.4

[PATCH v2 3/7] mtd: spi-nor: add opcodes for octal Read/Write commands

[Yogesh Narayan Gaur]

- Add opcodes for octal I/O commands
  * Read  : 1-1-8 and 1-8-8 protocol
  * Write : 1-1-8 and 1-8-8 protocol
  * opcodes for 4-byte address mode command

- Entry of macros in _convert_3to4_xxx function

- Add flag specifying flash support octal read commands.

Signed-off-by: Vignesh R 
Signed-off-by: Yogesh Gaur 
---
Changes for v2:
 Incorporated review comments of Boris and Vignesh

 drivers/mtd/spi-nor/spi-nor.c | 12 
 include/linux/mtd/spi-nor.h   |  8 
 2 files changed, 20 insertions(+)

diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 0b8a6e0..7c64ff0 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -90,6 +90,7 @@ struct flash_info {
 #define NO_CHIP_ERASE  BIT(12) /* Chip does not support chip erase */
 #define SPI_NOR_SKIP_SFDP  BIT(13) /* Skip parsing of SFDP tables */
 #define USE_CLSR   BIT(14) /* use CLSR command */
+#define SPI_NOR_OCTAL_READ BIT(15) /* Flash supports Octal Read */
 
int (*quad_enable)(struct spi_nor *nor);
 };
@@ -209,6 +210,8 @@ static inline u8 spi_nor_convert_3to4_read(u8 opcode)
{ SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B },
{ SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },
{ SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },
+   { SPINOR_OP_READ_1_1_8, SPINOR_OP_READ_1_1_8_4B },
+   { SPINOR_OP_READ_1_8_8, SPINOR_OP_READ_1_8_8_4B },
 
{ SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B },
{ SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B },
@@ -225,6 +228,8 @@ static inline u8 spi_nor_convert_3to4_program(u8 opcode)
{ SPINOR_OP_PP, SPINOR_OP_PP_4B },
{ SPINOR_OP_PP_1_1_4,   SPINOR_OP_PP_1_1_4_4B },
{ SPINOR_OP_PP_1_4_4,   SPINOR_OP_PP_1_4_4_4B },
+   { SPINOR_OP_PP_1_1_8,   SPINOR_OP_PP_1_1_8_4B },
+   { SPINOR_OP_PP_1_8_8,   SPINOR_OP_PP_1_8_8_4B },
};
 
return spi_nor_convert_opcode(opcode, spi_nor_3to4_program,
@@ -3195,6 +3200,13 @@ static int spi_nor_init_params(struct spi_nor *nor,
  SNOR_PROTO_1_1_4);
}
 
+   if (info->flags & SPI_NOR_OCTAL_READ) {
+   params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
+   spi_nor_set_read_settings(>reads[SNOR_CMD_READ_1_1_8],
+ 0, 8, SPINOR_OP_READ_1_1_8,
+ SNOR_PROTO_1_1_8);
+   }
+
/* Page Program settings. */
params->hwcaps.mask |= SNOR_HWCAPS_PP;
spi_nor_set_pp_settings(>page_programs[SNOR_CMD_PP],
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index 8b1acf6..019f534 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -50,9 +50,13 @@
 #define SPINOR_OP_READ_1_2_2   0xbb/* Read data bytes (Dual I/O SPI) */
 #define SPINOR_OP_READ_1_1_4   0x6b/* Read data bytes (Quad Output SPI) */
 #define SPINOR_OP_READ_1_4_4   0xeb/* Read data bytes (Quad I/O SPI) */
+#define SPINOR_OP_READ_1_1_8   0x8b/* Read data bytes (Octal Output SPI) */
+#define SPINOR_OP_READ_1_8_8   0xcb/* Read data bytes (Octal I/O SPI) */
 #define SPINOR_OP_PP   0x02/* Page program (up to 256 bytes) */
 #define SPINOR_OP_PP_1_1_4 0x32/* Quad page program */
 #define SPINOR_OP_PP_1_4_4 0x38/* Quad page program */
+#define SPINOR_OP_PP_1_1_8 0x82/* Octal page program */
+#define SPINOR_OP_PP_1_8_8 0xc2/* Octal page program */
 #define SPINOR_OP_BE_4K0x20/* Erase 4KiB block */
 #define SPINOR_OP_BE_4K_PMC0xd7/* Erase 4KiB block on PMC chips */
 #define SPINOR_OP_BE_32K   0x52/* Erase 32KiB block */
@@ -73,9 +77,13 @@
 #define SPINOR_OP_READ_1_2_2_4B0xbc/* Read data bytes (Dual I/O 
SPI) */
 #define SPINOR_OP_READ_1_1_4_4B0x6c/* Read data bytes (Quad Output 
SPI) */
 #define SPINOR_OP_READ_1_4_4_4B0xec/* Read data bytes (Quad I/O 
SPI) */
+#define SPINOR_OP_READ_1_1_8_4B0x7c/* Read data bytes (Octal 
Output SPI) */
+#define SPINOR_OP_READ_1_8_8_4B0xcc/* Read data bytes (Octal I/O 
SPI) */
 #define SPINOR_OP_PP_4B0x12/* Page program (up to 256 
bytes) */
 #define SPINOR_OP_PP_1_1_4_4B  0x34/* Quad page program */
 #define SPINOR_OP_PP_1_4_4_4B  0x3e/* Quad page program */
+#define SPINOR_OP_PP_1_1_8_4B  0x84/* Octal page program */
+#define SPINOR_OP_PP_1_8_8_4B  0x8e/* Octal page program */
 #define SPINOR_OP_BE_4K_4B 0x21/* Erase 4KiB block */
 #define SPINOR_OP_BE_32K_4B0x5c/* Erase 32KiB block */
 #define SPINOR_OP_SE_4B0xdc/* Sector erase (usually 64KiB) 
*/
-- 
2.7.4

[PATCH v2 7/7] arm64: dts: lx2160a: update fspi node

[Yogesh Narayan Gaur]

Flash mt35xu512aba connected to FlexSPI controller supports
1-1-8/1-8-8 protocol.
Added flag spi-rx-bus-width and spi-tx-bus-width with values as
8 and 8 respectively for both flashes connected at CS0 and CS1.

Signed-off-by: Yogesh Gaur 
---
Changes for v2:
 Make spi-tx-bus-width as 8.

 arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts 
b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
index 3b20c97..24cc41c 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -45,6 +45,8 @@
m25p,fast-read;
spi-max-frequency = <2000>;
reg = <0>;
+   spi-rx-bus-width = <8>;
+   spi-tx-bus-width = <8>;
};
 
mt35xu512aba1: flash@1 {
@@ -54,6 +56,8 @@
m25p,fast-read;
spi-max-frequency = <2000>;
reg = <1>;
+   spi-rx-bus-width = <8>;
+   spi-tx-bus-width = <8>;
};
 };
 
-- 
2.7.4

[PATCH v2 6/7] spi: nxp-fspi: add mode flag bit for octal support

[Yogesh Narayan Gaur]

Add mode flags for octal I/O data transfer support.
NXP FlexSPI controller supports octal mode data transfer.

Signed-off-by: Yogesh Gaur 
---
Changes for v2:
 None

 drivers/spi/spi-nxp-fspi.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c
index 67eea88..c48ca94 100644
--- a/drivers/spi/spi-nxp-fspi.c
+++ b/drivers/spi/spi-nxp-fspi.c
@@ -993,8 +993,8 @@ static int nxp_fspi_probe(struct platform_device *pdev)
if (!ctlr)
return -ENOMEM;
 
-   ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD |
- SPI_TX_DUAL | SPI_TX_QUAD;
+   ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_RX_OCTAL |
+ SPI_TX_DUAL | SPI_TX_QUAD | SPI_TX_OCTAL;
 
f = spi_controller_get_devdata(ctlr);
f->dev = dev;
-- 
2.7.4

[PATCH v2 0/7] spi: add support for octal mode

[Yogesh Narayan Gaur]

Add support for octal mode IO data transfer.
Micron flash, mt35xu512aba, supports octal mode data transfer and
NXP FlexSPI controller supports 8 data lines for data transfer (Rx/Tx).

Patch series
* Add support for octal mode flags and parsing of same in spi driver.
* Add parsing logic for spi-mem framework and m25p80.c device file.
* Add opcodes for octal I/O commands in spi-nor framework, Read and Write proto 
for (1-1-8/1-8-8) mode.
  Opcodes are added as per octal data IO commands required for mt35xu512aba [1] 
flash.
* Add mode bit required for octal mode in nxp-fspi driver [2].
* Define binding property 'spi-rx/tx-bus-width' for LX2160ARDB target [2].

Cherry pick below 2 patches (from: 
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git):
c639f871febe6667d9afce28108c634e5636c735 spi: spi-mem: Fix inverted logic 
in op sanity check
db122eb8a749a1eff038f9a282c620ab16c4be1d spi: spi-mem: Add extra sanity 
checks on the op param

Tested on LX2160ARDB target with nxp-fspi driver, below are
Read performance number of 1-1-1 and 1-1-8 read protocol.

 root@lxxx:~# cat /proc/mtd
 dev:size   erasesize  name
 mtd0: 0400 1000 "spi0.0"
 mtd1: 0400 1000 "spi0.1"
 root@lxxx:~# time mtd_debug read /dev/mtd0 0x0 0x100 0read
 Copied 16777216 bytes from address 0x in flash to 0read

 real0m2.792s
 user0m0.000s
 sys 0m2.790s
 root@lxxx:~# time mtd_debug read /dev/mtd1 0x0 0x100 0read
 Copied 16777216 bytes from address 0x in flash to 0read

 real0m0.441s
 user0m0.000s
 sys 0m0.440s
 root@ls1012ardb:~#

 Flash device MTD0 configured in 1-1-1 protocol.
 Flash device MTD1 configured in 1-1-8 protocol.

[1] https://patchwork.ozlabs.org/project/linux-mtd/list/?series=70384
[2] https://patchwork.ozlabs.org/project/linux-mtd/list/?series=70210

Yogesh Gaur (7):
  spi: add support for octal I/O data transfer
  spi: spi-mem: add support for octal I/O data transfer
  mtd: spi-nor: add opcodes for octal Read/Write commands
  mtd: spi-nor: add octal read flag for flash mt35xu512aba
  mtd: m25p80: add support of octal I/O transfer
  spi: nxp-fspi: add mode flag bit for octal support
  arm64: dts: lx2160a: update fspi node

Changes for v2:
 Incorporated review comments of Boris and Vignesh.

 arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts |  4 
 drivers/mtd/devices/m25p80.c  |  9 -
 drivers/mtd/spi-nor/spi-nor.c | 15 ++-
 drivers/spi/spi-mem.c |  9 -
 drivers/spi/spi-nxp-fspi.c|  4 ++--
 drivers/spi/spi.c |  6 ++
 include/linux/mtd/spi-nor.h   |  8 
 include/linux/spi/spi.h   |  2 ++
 8 files changed, 52 insertions(+), 5 deletions(-)

-- 
2.7.4

[PATCH v2 5/7] mtd: m25p80: add support of octal I/O transfer

[Yogesh Narayan Gaur]

Add support for octal I/O data transfer based on the controller (spi)
mode.
Assign hw-capability mask bits for octal transfer.

Signed-off-by: Yogesh Gaur 
---
Changes for v2:
 Incorporated review comments of Boris.

 drivers/mtd/devices/m25p80.c | 9 -
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
index cb14cf9..e5e632c 100644
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -175,7 +175,14 @@ static int m25p_probe(struct spi_mem *spimem)
spi_mem_set_drvdata(spimem, flash);
flash->spimem = spimem;
 
-   if (spi->mode & SPI_RX_QUAD) {
+   if (spi->mode & SPI_RX_OCTAL) {
+   hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
+
+   if (spi->mode & SPI_TX_OCTAL)
+   hwcaps.mask |= (SNOR_HWCAPS_READ_1_8_8 |
+   SNOR_HWCAPS_PP_1_1_8 |
+   SNOR_HWCAPS_PP_1_8_8);
+   } else if (spi->mode & SPI_RX_QUAD) {
hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
 
if (spi->mode & SPI_TX_QUAD)
-- 
2.7.4

[PATCH v2 2/7] spi: spi-mem: add support for octal I/O data transfer

[Yogesh Narayan Gaur]

Add support for octal I/O data transfer in spi-mem framework.

Signed-off-by: Yogesh Gaur 
---
Changes for v2:
 Patch added in v2 version.

 drivers/spi/spi-mem.c | 9 -
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index c6bdea7..6fa95f8 100644
--- a/drivers/spi/spi-mem.c
+++ b/drivers/spi/spi-mem.c
@@ -12,7 +12,7 @@
 
 #include "internals.h"
 
-#define SPI_MEM_MAX_BUSWIDTH   4
+#define SPI_MEM_MAX_BUSWIDTH   8
 
 /**
  * spi_controller_dma_map_mem_op_data() - DMA-map the buffer attached to a
@@ -121,6 +121,13 @@ static int spi_check_buswidth_req(struct spi_mem *mem, u8 
buswidth, bool tx)
 
break;
 
+   case 8:
+   if ((tx && (mode & SPI_TX_OCTAL)) ||
+   (!tx && (mode & SPI_RX_OCTAL)))
+   return 0;
+
+   break;
+
default:
break;
}
-- 
2.7.4

[PATCH v2 1/7] spi: add support for octal I/O data transfer

[Yogesh Narayan Gaur]

Add flags for Octal I/O data transfer
Required for the SPI controller which can do the data transfer (TX/RX)
on 8 data lines e.g. NXP FlexSPI controller.
 SPI_TX_OCTAL: transmit with 8 wires
 SPI_RX_OCTAL: receive with 8 wires

Signed-off-by: Yogesh Gaur 
---
Changes for v2:
 Incorporated review comments of Boris.

 drivers/spi/spi.c   | 6 ++
 include/linux/spi/spi.h | 2 ++
 2 files changed, 8 insertions(+)

diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index ec395a6..80f672f 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -1573,6 +1573,9 @@ static int of_spi_parse_dt(struct spi_controller *ctlr, 
struct spi_device *spi,
case 4:
spi->mode |= SPI_TX_QUAD;
break;
+   case 8:
+   spi->mode |= SPI_TX_OCTAL;
+   break;
default:
dev_warn(>dev,
"spi-tx-bus-width %d not supported\n",
@@ -1591,6 +1594,9 @@ static int of_spi_parse_dt(struct spi_controller *ctlr, 
struct spi_device *spi,
case 4:
spi->mode |= SPI_RX_QUAD;
break;
+   case 8:
+   spi->mode |= SPI_RX_OCTAL;
+   break;
default:
dev_warn(>dev,
"spi-rx-bus-width %d not supported\n",
diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index a64235e..2d21307 100644
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -163,6 +163,8 @@ struct spi_device {
 #defineSPI_TX_QUAD 0x200   /* transmit with 4 
wires */
 #defineSPI_RX_DUAL 0x400   /* receive with 2 wires 
*/
 #defineSPI_RX_QUAD 0x800   /* receive with 4 wires 
*/
+#defineSPI_TX_OCTAL0x1000  /* transmit with 8 
wires */
+#defineSPI_RX_OCTAL0x2000  /* receive with 8 wires 
*/
int irq;
void*controller_state;
void*controller_data;
-- 
2.7.4

RE: [PATCH v3 1/2] mtd: spi-nor: add support to non-uniform SFDP SPI NOR flash memories

[Yogesh Narayan Gaur]

Hi Tudor,

This patch is breaking the 1-4-4 Read protocol for the spansion flash 
"s25fl512s".

Without this patch read request command for Quad mode, 4-byte enable, is coming 
as 0xEC i.e. SPINOR_OP_READ_1_4_4_4B.
But after applying this patch, read request command for Quad mode is coming as 
0x6C i.e. SPINOR_OP_READ_1_1_4_4B.

This flash also supports non-uniform erase.
Can you please check and provide some suggestion?

--
Regards
Yogesh Gaur

> -Original Message-
> From: linux-mtd [mailto:linux-mtd-boun...@lists.infradead.org] On Behalf Of
> Tudor Ambarus
> Sent: Tuesday, September 11, 2018 9:10 PM
> To: marek.va...@gmail.com; dw...@infradead.org;
> computersforpe...@gmail.com; boris.brezil...@bootlin.com; rich...@nod.at
> Cc: Tudor Ambarus ; linux-
> ker...@vger.kernel.org; nicolas.fe...@microchip.com;
> cyrille.pitc...@microchip.com; linux-...@lists.infradead.org; linux-arm-
> ker...@lists.infradead.org; cristian.bir...@microchip.com
> Subject: [PATCH v3 1/2] mtd: spi-nor: add support to non-uniform SFDP SPI NOR
> flash memories
> 
> Based on Cyrille Pitchen's patch
> https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flkml.or
> g%2Flkml%2F2017%2F3%2F22%2F935data=02%7C01%7Cyogeshnarayan.
> gaur%40nxp.com%7C3c782e52b7fd4a8b9af008d617fd5154%7C686ea1d3bc2b4
> c6fa92cd99c5c301635%7C0%7C0%7C636722774108718782sdata=szyc%
> 2FTumG6eYAmBd0oW3IL7v1yLh9E1SAZqL%2BCWczOA%3Dreserved=0.
> 
> This patch is a transitional patch in introducing  the support of SFDP SPI
> memories with non-uniform erase sizes like Spansion s25fs512s.
> Non-uniform erase maps will be used later when initialized based on the SFDP
> data.
> 
> Introduce the memory erase map which splits the memory array into one or
> many erase regions. Each erase region supports up to 4 erase types, as defined
> by the JEDEC JESD216B (SFDP) specification.
> 
> To be backward compatible, the erase map of uniform SPI NOR flash memories
> is initialized so it contains only one erase region and this erase region 
> supports
> only one erase command. Hence a single size is used to erase any sector/block
> of the memory.
> 
> Besides, since the algorithm used to erase sectors on non-uniform SPI NOR 
> flash
> memories is quite expensive, when possible, the erase map is tuned to come
> back to the uniform case.
> 
> The 'erase with the best command, move forward and repeat' approach was
> suggested by Cristian Birsan in a brainstorm session, so:
> 
> Suggested-by: Cristian Birsan 
> Signed-off-by: Tudor Ambarus 
> ---
>  drivers/mtd/spi-nor/spi-nor.c | 594
> +++---
>  include/linux/mtd/spi-nor.h   | 107 
>  2 files changed, 659 insertions(+), 42 deletions(-)
> 
> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c 
> index
> dc8757e..4687345 100644
> --- a/drivers/mtd/spi-nor/spi-nor.c
> +++ b/drivers/mtd/spi-nor/spi-nor.c
> @@ -18,6 +18,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
> 
>  #include 
>  #include 
> @@ -261,6 +262,18 @@ static void spi_nor_set_4byte_opcodes(struct spi_nor
> *nor,
>   nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode);
>   nor->program_opcode = spi_nor_convert_3to4_program(nor-
> >program_opcode);
>   nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode);
> +
> + if (!spi_nor_has_uniform_erase(nor)) {
> + struct spi_nor_erase_map *map = >erase_map;
> + struct spi_nor_erase_type *erase;
> + int i;
> +
> + for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) {
> + erase = >erase_type[i];
> + erase->opcode =
> + spi_nor_convert_3to4_erase(erase->opcode);
> + }
> + }
>  }
> 
>  /* Enable/disable 4-byte addressing mode. */ @@ -499,6 +512,275 @@ static
> int spi_nor_erase_sector(struct spi_nor *nor, u32 addr)  }
> 
>  /*
> + * spi_nor_div_by_erase_size() - calculate remainder and update new dividend
> + * @erase:   pointer to a structure that describes a SPI NOR erase type
> + * @dividend:dividend value
> + * @remainder:   pointer to u32 remainder (will be updated)
> + *
> + * Returns two values: remainder and the new dividend  */ static u64
> +spi_nor_div_by_erase_size(const struct spi_nor_erase_type *erase,
> +  u64 dividend, u32 *remainder)
> +{
> + /* JEDEC JESD216B Standard imposes erase sizes to be power of 2. */
> + *remainder = (u32)dividend & erase->size_mask;
> + return dividend >> erase->size_shift;
> +}
> +
> +/*
> + * spi_nor_find_best_erase_type() - find the best erase type for the
> +given
> + * offset in the serial flash memory and the number of bytes to erase.
> +The
> + * region in which the address fits is expected to be provided.
> + * @map: the erase map of the SPI NOR
> + * @region:  pointer to a structure that describes a SPI NOR erase region
> + * @addr:offset in the serial flash memory
> + * 

RE: [PATCH v3 1/2] mtd: spi-nor: add support to non-uniform SFDP SPI NOR flash memories

[Yogesh Narayan Gaur]

Hi Boris,

> -Original Message-
> From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> Sent: Tuesday, October 16, 2018 5:48 PM
> To: Yogesh Narayan Gaur 
> Cc: Tudor Ambarus ; marek.va...@gmail.com;
> dw...@infradead.org; computersforpe...@gmail.com; rich...@nod.at;
> linux-kernel@vger.kernel.org; nicolas.fe...@microchip.com;
> cyrille.pitc...@microchip.com; linux-...@lists.infradead.org; linux-arm-
> ker...@lists.infradead.org; cristian.bir...@microchip.com
> Subject: Re: [PATCH v3 1/2] mtd: spi-nor: add support to non-uniform SFDP SPI
> NOR flash memories
> 
> On Tue, 16 Oct 2018 14:04:11 +0200
> Boris Brezillon  wrote:
> 
> > On Tue, 16 Oct 2018 09:51:47 +
> > Yogesh Narayan Gaur  wrote:
> >
> > > Hi Tudor,
> > >
> > > This patch is breaking the 1-4-4 Read protocol for the spansion flash
> "s25fl512s".
> > >
> > > Without this patch read request command for Quad mode, 4-byte enable, is
> coming as 0xEC i.e. SPINOR_OP_READ_1_4_4_4B.
> > > But after applying this patch, read request command for Quad mode is
> coming as 0x6C i.e. SPINOR_OP_READ_1_1_4_4B.
> > >
> > > This flash also supports non-uniform erase.
> > > Can you please check and provide some suggestion?
> >
> > Are you sure the regression comes from this patch? I suspect your bug
> > comes from 41fe242979e4 ("mtd: spi-nor: fsl-quadspi: fix read error
> > for flash size larger than 16MB").
> 
> I guess you're testing with an fsl-qspi controller, right? Can you try with 
> this
> patch?

I am testing nxp-flexspi controller and doing just read of small size 0x200.
Also 1-1-1 protocol i.e. spi-rx/tx-bus-width as 1 is working fine for this 
flash.

Without this patch read from 1-4-4 protocol is working correctly.

--
Regards
Yogesh Gaur

> 
> --->8---
> 
> diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c 
> b/drivers/mtd/spi-nor/fsl-quadspi.c
> index 1ff3430f82c8..c47fe70c9f98 100644
> --- a/drivers/mtd/spi-nor/fsl-quadspi.c
> +++ b/drivers/mtd/spi-nor/fsl-quadspi.c
> @@ -477,9 +477,6 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)  static 
> int
> fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd)  {
> switch (cmd) {
> -   case SPINOR_OP_READ_1_1_4:
> -   case SPINOR_OP_READ_1_1_4_4B:
> -   return SEQID_READ;
> case SPINOR_OP_WREN:
> return SEQID_WREN;
> case SPINOR_OP_WRDI:
> @@ -490,8 +487,6 @@ static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd)
> return SEQID_SE;
> case SPINOR_OP_CHIP_ERASE:
> return SEQID_CHIP_ERASE;
> -   case SPINOR_OP_PP:
> -   return SEQID_PP;
> case SPINOR_OP_RDID:
> return SEQID_RDID;
> case SPINOR_OP_WRSR:
> @@ -503,7 +498,11 @@ static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd)
> case SPINOR_OP_BRWR:
> return SEQID_BRWR;
> default:
> -   if (cmd == q->nor[0].erase_opcode)
> +   if (cmd == q->nor[0].read_opcode)
> +   return SEQID_READ;
> +   else if (cmd == q->nor[0].program_opcode)
> +   return SEQID_PP;
> +   else if (cmd == q->nor[0].erase_opcode)
> return SEQID_SE;
> dev_err(q->dev, "Unsupported cmd 0x%.2x\n", cmd);
> break;

RE: [PATCH v3 1/2] mtd: spi-nor: add support to non-uniform SFDP SPI NOR flash memories

[Yogesh Narayan Gaur]

Hi Tudor,

> -Original Message-
> From: Yogesh Narayan Gaur
> Sent: Wednesday, October 17, 2018 7:38 AM
> To: 'Cyrille Pitchen' ; Tudor Ambarus
> ; marek.va...@gmail.com;
> dw...@infradead.org; computersforpe...@gmail.com;
> boris.brezil...@bootlin.com; rich...@nod.at
> Cc: linux-kernel@vger.kernel.org; nicolas.fe...@microchip.com;
> cyrille.pitc...@microchip.com; linux-...@lists.infradead.org; linux-arm-
> ker...@lists.infradead.org; cristian.bir...@microchip.com
> Subject: RE: [PATCH v3 1/2] mtd: spi-nor: add support to non-uniform SFDP SPI
> NOR flash memories
> 
> Hi Tudor,
> 
> > -Original Message-
> > From: Cyrille Pitchen [mailto:cyrille.pitc...@wedev4u.fr]
> > Sent: Tuesday, October 16, 2018 10:04 PM
> > To: Tudor Ambarus ; Yogesh Narayan Gaur
> > ; marek.va...@gmail.com;
> > dw...@infradead.org; computersforpe...@gmail.com;
> > boris.brezil...@bootlin.com; rich...@nod.at
> > Cc: linux-kernel@vger.kernel.org; nicolas.fe...@microchip.com;
> > cyrille.pitc...@microchip.com; linux-...@lists.infradead.org;
> > linux-arm- ker...@lists.infradead.org; cristian.bir...@microchip.com
> > Subject: Re: [PATCH v3 1/2] mtd: spi-nor: add support to non-uniform
> > SFDP SPI NOR flash memories
> >
> > Hi Tudor,
> >
> > Le 16/10/2018 à 17:14, Tudor Ambarus a écrit :
> > > Hi, Yogesh,
> > >
> > > On 10/16/2018 12:51 PM, Yogesh Narayan Gaur wrote:
> > >> Hi Tudor,
> > >>
> > >> This patch is breaking the 1-4-4 Read protocol for the spansion
> > >> flash
> > "s25fl512s".
> > >>
> > >> Without this patch read request command for Quad mode, 4-byte
> > >> enable, is
> > coming as 0xEC i.e. SPINOR_OP_READ_1_4_4_4B.
> > >> But after applying this patch, read request command for Quad mode
> > >> is
> > coming as 0x6C i.e. SPINOR_OP_READ_1_1_4_4B.
> > >>
> > >> This flash also supports non-uniform erase.
> > >> Can you please check and provide some suggestion?
> > >
> > > I don't have this memory to test it, but I'll try to help.
> > >
> > > Does s25fl512s support non-uniform erase? I'm looking in
> > > datasheet[1] at JEDEC BFPT table, dwords 8 and 9, page 132/146 and
> > > it looks like it supports just 256KB uniform erase.
> > >
> >
> Actually there is no entry of s25fs512s in current spi-nor.c file.
> For my connected flash part, jedec ID read points to s25fl512s. I have asked 
> my
> board team to confirm the name of exact connected flash part.

Cypress connected flash part on my target is S25FS512SAGBHV210.

--
Regards
Yogesh Gaur

> When I check the data sheet of s25fs512s, it also points to the same Jedec ID
> information.
>   { "s25fl512s",  INFO(0x010220, 0x4d00, 256 * 1024, 256, }
> 
> But as stated earlier, if I skip reading SFDP or read using 1-1-1 protocol 
> then read
> are always correct.
> For 1-4-4 protocol read are wrong and on further debugging found that Read
> code of 0x6C is being send as opcode instead of 0xEC.
> 
> If I revert this patch, reads are working fine.
> 
> --
> Regards
> Yogesh Gaur
> 
> > s25fS512s supports both uniform and non uniform erase options but
> > s25fL512s is always uniform. L is an old memory part, S is newer.
> >
> > Also, the 8th and 9th WORDs of the Basic Flash Parameter Table alone
> > can't tell you whether or not the memory part can be non uniform.
> > If the memory can be non uniform then the sector erase map table is
> > mandatory, hence when the table is missing you know that your memory
> > part is always uniform.
> >
> > Best regards,
> >
> > Cyrille
> >
> > > Thanks,
> > > ta
> > >
> > > [1]
> > >
> https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fwww.
> > >
> >
> cypress.com%2Ffile%2F177971%2Fdownloaddata=02%7C01%7Cyogeshn
> > araya
> > >
> >
> n.gaur%40nxp.com%7C76e7e1555f4a4cda378008d63385480b%7C686ea1d3bc2
> > b4c6f
> > >
> >
> a92cd99c5c301635%7C0%7C0%7C636753044876199155sdata=cioC98EH
> > OGlFbg
> > > XPhoIIJ72K3JrNUnzA1pYhSB9jDwg%3Dreserved=0
> > >
> > >>
> > >> --
> > >> Regards
> > >> Yogesh Gaur
> > >>
> > >>> -Original Message-
> > >>> From: linux-mtd [mailto:linux-mtd-boun...@lists.infradead.org] On
> > >>> Behalf Of Tudor Ambarus
> > >>> Sent: Tuesday, September 11, 2018 9:10 PM
> > >>> To

RE: [PATCH v3 1/2] mtd: spi-nor: add support to non-uniform SFDP SPI NOR flash memories

[Yogesh Narayan Gaur]

Hi Tudor,

> -Original Message-
> From: Cyrille Pitchen [mailto:cyrille.pitc...@wedev4u.fr]
> Sent: Tuesday, October 16, 2018 10:04 PM
> To: Tudor Ambarus ; Yogesh Narayan Gaur
> ; marek.va...@gmail.com;
> dw...@infradead.org; computersforpe...@gmail.com;
> boris.brezil...@bootlin.com; rich...@nod.at
> Cc: linux-kernel@vger.kernel.org; nicolas.fe...@microchip.com;
> cyrille.pitc...@microchip.com; linux-...@lists.infradead.org; linux-arm-
> ker...@lists.infradead.org; cristian.bir...@microchip.com
> Subject: Re: [PATCH v3 1/2] mtd: spi-nor: add support to non-uniform SFDP SPI
> NOR flash memories
> 
> Hi Tudor,
> 
> Le 16/10/2018 à 17:14, Tudor Ambarus a écrit :
> > Hi, Yogesh,
> >
> > On 10/16/2018 12:51 PM, Yogesh Narayan Gaur wrote:
> >> Hi Tudor,
> >>
> >> This patch is breaking the 1-4-4 Read protocol for the spansion flash
> "s25fl512s".
> >>
> >> Without this patch read request command for Quad mode, 4-byte enable, is
> coming as 0xEC i.e. SPINOR_OP_READ_1_4_4_4B.
> >> But after applying this patch, read request command for Quad mode is
> coming as 0x6C i.e. SPINOR_OP_READ_1_1_4_4B.
> >>
> >> This flash also supports non-uniform erase.
> >> Can you please check and provide some suggestion?
> >
> > I don't have this memory to test it, but I'll try to help.
> >
> > Does s25fl512s support non-uniform erase? I'm looking in datasheet[1]
> > at JEDEC BFPT table, dwords 8 and 9, page 132/146 and it looks like it
> > supports just 256KB uniform erase.
> >
> 
Actually there is no entry of s25fs512s in current spi-nor.c file.
For my connected flash part, jedec ID read points to s25fl512s. I have asked my 
board team to confirm the name of exact connected flash part.
When I check the data sheet of s25fs512s, it also points to the same Jedec ID 
information.
  { "s25fl512s",  INFO(0x010220, 0x4d00, 256 * 1024, 256, }

But as stated earlier, if I skip reading SFDP or read using 1-1-1 protocol then 
read are always correct.
For 1-4-4 protocol read are wrong and on further debugging found that Read code 
of 0x6C is being send as opcode instead of 0xEC.

If I revert this patch, reads are working fine.

--
Regards
Yogesh Gaur

> s25fS512s supports both uniform and non uniform erase options but s25fL512s is
> always uniform. L is an old memory part, S is newer.
>
> Also, the 8th and 9th WORDs of the Basic Flash Parameter Table alone can't 
> tell
> you whether or not the memory part can be non uniform.
> If the memory can be non uniform then the sector erase map table is mandatory,
> hence when the table is missing you know that your memory part is always
> uniform.
> 
> Best regards,
> 
> Cyrille
> 
> > Thanks,
> > ta
> >
> > [1]
> > https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fwww.
> >
> cypress.com%2Ffile%2F177971%2Fdownloaddata=02%7C01%7Cyogeshn
> araya
> >
> n.gaur%40nxp.com%7C76e7e1555f4a4cda378008d63385480b%7C686ea1d3bc2
> b4c6f
> >
> a92cd99c5c301635%7C0%7C0%7C636753044876199155sdata=cioC98EH
> OGlFbg
> > XPhoIIJ72K3JrNUnzA1pYhSB9jDwg%3Dreserved=0
> >
> >>
> >> --
> >> Regards
> >> Yogesh Gaur
> >>
> >>> -Original Message-
> >>> From: linux-mtd [mailto:linux-mtd-boun...@lists.infradead.org] On
> >>> Behalf Of Tudor Ambarus
> >>> Sent: Tuesday, September 11, 2018 9:10 PM
> >>> To: marek.va...@gmail.com; dw...@infradead.org;
> >>> computersforpe...@gmail.com; boris.brezil...@bootlin.com;
> >>> rich...@nod.at
> >>> Cc: Tudor Ambarus ; linux-
> >>> ker...@vger.kernel.org; nicolas.fe...@microchip.com;
> >>> cyrille.pitc...@microchip.com; linux-...@lists.infradead.org;
> >>> linux-arm- ker...@lists.infradead.org; cristian.bir...@microchip.com
> >>> Subject: [PATCH v3 1/2] mtd: spi-nor: add support to non-uniform
> >>> SFDP SPI NOR flash memories
> >>>
> >>> Based on Cyrille Pitchen's patch
> >>> https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fl
> >>> kml.or
> >>>
> g%2Flkml%2F2017%2F3%2F22%2F935data=02%7C01%7Cyogeshnarayan.
> >>>
> gaur%40nxp.com%7C3c782e52b7fd4a8b9af008d617fd5154%7C686ea1d3bc2b4
> >>>
> c6fa92cd99c5c301635%7C0%7C0%7C636722774108718782sdata=szyc%
> >>>
> 2FTumG6eYAmBd0oW3IL7v1yLh9E1SAZqL%2BCWczOA%3Dreserved=0.
> >>>
> >>> This patch is a transitional patch in introducing  the support of
> >>> SFDP SPI memories with non-uniform erase sizes like Spansion s25fs512

RE: [PATCH v3 1/2] mtd: spi-nor: add support to non-uniform SFDP SPI NOR flash memories

[Yogesh Narayan Gaur]

HI,


> -Original Message-
> From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> Sent: Monday, October 22, 2018 1:32 PM
> To: Yogesh Narayan Gaur 
> Cc: Cyrille Pitchen ; Tudor Ambarus
> ; marek.va...@gmail.com;
> dw...@infradead.org; computersforpe...@gmail.com; rich...@nod.at;
> linux-kernel@vger.kernel.org; nicolas.fe...@microchip.com;
> cyrille.pitc...@microchip.com; linux-...@lists.infradead.org; linux-arm-
> ker...@lists.infradead.org; cristian.bir...@microchip.com; Mark Brown
> 
> Subject: Re: [PATCH v3 1/2] mtd: spi-nor: add support to non-uniform SFDP SPI
> NOR flash memories
> 
> On Mon, 22 Oct 2018 06:04:13 +
> Yogesh Narayan Gaur  wrote:
> 
> > -static const u32 *spi_nor_get_map_in_use(struct spi_nor *nor, const
> > u32 *smpt)
> > +static const u32 *spi_nor_get_map_in_use(struct spi_nor *nor, const
> > +u32 *smpt, u32 smpt_len)
> >  {
> > const u32 *ret = NULL;
> > -   u32 i, addr;
> > +   u32 i, addr, nmaps;
> > int err;
> > u8 addr_width, read_opcode, read_dummy;
> > u8 read_data_mask, data_byte, map_id;
> > +   bool map_id_is_valid = false;
> >
> > addr_width = nor->addr_width;
> > read_dummy = nor->read_dummy;
> > read_opcode = nor->read_opcode;
> >
> > +   for (i = 0; i > +   pr_info("%s:%i smpt[%d]=%08x\n", __func__, __LINE__,
> > + i, smpt[i]);
> > +
> > map_id = 0;
> > -   i = 0;
> > /* Determine if there are any optional Detection Command 
> > Descriptors */
> > -   while (!(smpt[i] & SMPT_DESC_TYPE_MAP)) {
> > +   for (i = 0; i< smpt_len; i++) {
> > +   if (!(smpt[i] & SMPT_DESC_TYPE_MAP))
> > +   break;
> > +
> > read_data_mask = SMPT_CMD_READ_DATA(smpt[i]);
> > nor->addr_width = spi_nor_smpt_addr_width(nor, smpt[i]);
> > nor->read_dummy = spi_nor_smpt_read_dummy(nor,
> > smpt[i]);
> 
> Could you also print the ->addr_width, ->read_dummy and ->read_opcode here?
> 
It didn't showing any print messages here, did above line " if 
(!(smpt[i] & SMPT_DESC_TYPE_MAP))" also needs to be changes to "if 
((smpt[i] & SMPT_DESC_TYPE_MAP))"?

Below is the log, with the suggested change of modifying as
> +   for (nmaps = 0; nmaps< smpt_len; nmaps++) {
> +   if((smpt[nmaps] & SMPT_DESC_TYPE_MAP))

[1.625992] m25p80 spi0.0: found s25fl512s, expected m25p80  
 
[1.631681] spi_nor_get_map_in_use:2880 smpt[0]=08ff65fc 
 
[1.636988] spi_nor_get_map_in_use:2880 smpt[1]=0004 
 
[1.642292] spi_nor_get_map_in_use:2880 smpt[2]=04ff65fc 
 
[1.647596] spi_nor_get_map_in_use:2880 smpt[3]=0002 
 
[1.652898] spi_nor_get_map_in_use:2880 smpt[4]=02ff65fd 
 
[1.658200] spi_nor_get_map_in_use:2880 smpt[5]=0004 
 
[1.663503] spi_nor_get_map_in_use:2880 smpt[6]=ff0201fe 
 
[1.668806] spi_nor_get_map_in_use:2880 smpt[7]=7ff1 
 
[1.674108] spi_nor_get_map_in_use:2880 smpt[8]=00037ff4 
 
[1.679412] spi_nor_get_map_in_use:2880 smpt[9]=03fbfff4 
 
[1.684715] spi_nor_get_map_in_use:2880 smpt[10]=ff0203fe
 
[1.690105] spi_nor_get_map_in_use:2880 smpt[11]=03fbfff4
 
[1.695495] spi_nor_get_map_in_use:2880 smpt[12]=00037ff4
 
[1.700886] spi_nor_get_map_in_use:2880 smpt[13]=7ff1
 
[1.706275] spi_nor_get_map_in_use:2880 smpt[14]=ff0005ff
 
[1.711664] spi_nor_get_map_in_use:2880 smpt[15]=03f4
 
[1.717053] spi_no

RE: [PATCH v3 1/2] mtd: spi-nor: add support to non-uniform SFDP SPI NOR flash memories

[Yogesh Narayan Gaur]

Hi Boris, Tudor,

> -Original Message-
> From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> Sent: Wednesday, October 17, 2018 3:23 PM
> To: Yogesh Narayan Gaur 
> Cc: Cyrille Pitchen ; Tudor Ambarus
> ; marek.va...@gmail.com;
> dw...@infradead.org; computersforpe...@gmail.com; rich...@nod.at;
> linux-kernel@vger.kernel.org; nicolas.fe...@microchip.com;
> cyrille.pitc...@microchip.com; linux-...@lists.infradead.org; linux-arm-
> ker...@lists.infradead.org; cristian.bir...@microchip.com
> Subject: Re: [PATCH v3 1/2] mtd: spi-nor: add support to non-uniform SFDP SPI
> NOR flash memories
> 
> On Wed, 17 Oct 2018 07:46:30 +
> Yogesh Narayan Gaur  wrote:
> 
> > Hi Boris,
> >
> > > -Original Message-
> > > From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> > > Sent: Wednesday, October 17, 2018 1:00 PM
> > > To: Yogesh Narayan Gaur 
> > > Cc: Cyrille Pitchen ; Tudor Ambarus
> > > ; marek.va...@gmail.com;
> > > dw...@infradead.org; computersforpe...@gmail.com; rich...@nod.at;
> > > linux-kernel@vger.kernel.org; nicolas.fe...@microchip.com;
> > > cyrille.pitc...@microchip.com; linux-...@lists.infradead.org;
> > > linux-arm- ker...@lists.infradead.org; cristian.bir...@microchip.com
> > > Subject: Re: [PATCH v3 1/2] mtd: spi-nor: add support to non-uniform
> > > SFDP SPI NOR flash memories
> > >
> > > On Wed, 17 Oct 2018 09:10:45 +0200
> > > Boris Brezillon  wrote:
> > >
> > > > On Wed, 17 Oct 2018 09:07:24 +0200 Boris Brezillon
> > > >  wrote:
> > > >
> > > > > On Wed, 17 Oct 2018 02:07:43 + Yogesh Narayan Gaur
> > > > >  wrote:
> > > > >
> > > > > > >
> > > > > > Actually there is no entry of s25fs512s in current spi-nor.c file.
> > > > > > For my connected flash part, jedec ID read points to
> > > > > > s25fl512s. I have asked my board team to confirm the name of
> > > > > > exact connected flash part. When I check the data sheet of
> > > > > > s25fs512s, it also points to the same Jedec ID information. {
> > > > > > "s25fl512s", INFO(0x010220, 0x4d00, 256
> > > > > > * 1024, 256, }
> > > > > >
> > > > > > But as stated earlier, if I skip reading SFDP or read using
> > > > > > 1-1-1 protocol then read are always correct. For 1-4-4
> > > > > > protocol read are wrong and on further debugging found that
> > > > > > Read code of 0x6C is being send as opcode instead of 0xEC.
> > > > > >
> > > > > > If I revert this patch, reads are working fine.
> > > > >
> > > > > Can you try with the following patch?
> > > > >
> > > >
> > > > Hm, nevermind. The problem is actually not related to 4B vs non-4B
> > > > mode but 1-1-4 vs 1-4-4 modes.
> > Yes, that's only I have stated in my first mail that instead of 1-4-4 mode 
> > read
> opcode is being sent for 1-1-4 mode.
> > > >
> > >
> > > Can you try with this patch applied?
> > >
> > With suggested patch, read for protocol 1-4-4 working correctly.
> >
> > [1.625360] m25p80 spi0.0: found s25fl512s, expected m25p80
> > [1.631094] m25p80 spi0.0: failed to parse SMPT (err = -22)
> > [1.636661] 261 8c4c780 opcode(read:eb, pp:2, erase:d8)
> > [1.641878] 266 8c4c780 opcode(read:ec, pp:12, erase:dc)
> > [1.647200] m25p80 spi0.0: s25fl512s (65536 Kbytes)
> >
> 
> Okay, let's try this one to see why the SMPT parsing fails.
> 

Please find the below info for the SMPT table read from the flash
[1.631085] spi_nor_get_map_in_use:2880 smpt[0]=08ff65fc   
[1.636393] spi_nor_get_map_in_use:2880 smpt[1]=0004   
[1.641696] spi_nor_get_map_in_use:2880 smpt[2]=04ff65fc   
[1.646998] spi_nor_get_map_in_use:2880 smpt[3]=0002   
[1.652302] spi_nor_get_map_in_use:2880 smpt[4]=02ff65fd   
[1.657606] spi_nor_get_map_in_use:2880 smpt[5]=0004   
[1.662911] spi_nor_get_map_in_use:2880 smpt[6]=ff0201fe   
[1.668215] spi_nor_get_map_in_use:2880 smpt[7]=7ff1   
[1.673520] spi_nor_get_map_in_use:2880 smpt[8]=00037ff4   
[1.678825] spi_nor_get_map_in_use:2880 smpt[9]=03fbfff4   
[1.684128] spi_nor_get_map_in_use:2880 smpt[10]=ff0203fe   
[1.689519] spi_nor_get_map_in_use:2880 smpt[11]=03fbfff4   
[1.694911] spi_nor_get_map_in_use:2880 smpt[12]=00037ff4   
[1.700303] spi_nor_get_map_in_use:2880 smpt[13]=7f

RE: [PATCH v3 1/2] mtd: spi-nor: add support to non-uniform SFDP SPI NOR flash memories

[Yogesh Narayan Gaur]

Hi,

> -Original Message-
> From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> Sent: Monday, October 22, 2018 5:22 PM
> To: Yogesh Narayan Gaur 
> Cc: cristian.bir...@microchip.com; Tudor Ambarus
> ; rich...@nod.at; Mark Brown
> ; linux-kernel@vger.kernel.org;
> nicolas.fe...@microchip.com; marek.va...@gmail.com;
> cyrille.pitc...@microchip.com; linux-...@lists.infradead.org; Cyrille Pitchen
> ; computersforpe...@gmail.com;
> dw...@infradead.org; linux-arm-ker...@lists.infradead.org
> Subject: Re: [PATCH v3 1/2] mtd: spi-nor: add support to non-uniform SFDP SPI
> NOR flash memories
> 
> On Mon, 22 Oct 2018 11:46:55 +
> Yogesh Narayan Gaur  wrote:
> 
> > Hi,
> >
> > > -Original Message-
> > > From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> > > Sent: Monday, October 22, 2018 5:13 PM
> > > To: Yogesh Narayan Gaur 
> > > Cc: cristian.bir...@microchip.com; Tudor Ambarus
> > > ; rich...@nod.at; Mark Brown
> > > ; linux-kernel@vger.kernel.org;
> > > nicolas.fe...@microchip.com; marek.va...@gmail.com;
> > > cyrille.pitc...@microchip.com; linux-...@lists.infradead.org;
> > > Cyrille Pitchen ;
> > > computersforpe...@gmail.com; dw...@infradead.org;
> > > linux-arm-ker...@lists.infradead.org
> > > Subject: Re: [PATCH v3 1/2] mtd: spi-nor: add support to non-uniform
> > > SFDP SPI NOR flash memories
> > >
> > > On Mon, 22 Oct 2018 11:03:09 +
> > > Yogesh Narayan Gaur  wrote:
> > >
> > > > Hi,
> > > >
> > > > > -Original Message-
> > > > > From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> > > > > Sent: Monday, October 22, 2018 4:23 PM
> > > > > To: Yogesh Narayan Gaur ;
> > > > > cristian.bir...@microchip.com
> > > > > Cc: Tudor Ambarus ; rich...@nod.at;
> > > > > Mark Brown ; linux-kernel@vger.kernel.org;
> > > > > nicolas.fe...@microchip.com; marek.va...@gmail.com;
> > > > > cyrille.pitc...@microchip.com; linux-...@lists.infradead.org;
> > > > > Cyrille Pitchen ;
> > > > > computersforpe...@gmail.com; dw...@infradead.org;
> > > > > linux-arm-ker...@lists.infradead.org
> > > > > Subject: Re: [PATCH v3 1/2] mtd: spi-nor: add support to
> > > > > non-uniform SFDP SPI NOR flash memories
> > > > >
> > > > > On Mon, 22 Oct 2018 12:46:27 +0200 Boris Brezillon
> > > > >  wrote:
> > > > >
> > > > > > On Mon, 22 Oct 2018 10:39:48 + Yogesh Narayan Gaur
> > > > > >  wrote:
> > > > > >
> > Patch used
> >
> > --- a/drivers/mtd/spi-nor/spi-nor.c
> > +++ b/drivers/mtd/spi-nor/spi-nor.c
> > @@ -2863,26 +2863,39 @@ static u8 spi_nor_smpt_read_dummy(const struct
> > spi_nor *nor, const u32 settings)
> 
> > /* Determine if there are any optional Detection Command 
> > Descriptors */
> > -   while (!(smpt[i] & SMPT_DESC_TYPE_MAP)) {
> > +   for (i = 0; i< smpt_len; i++) {
> 
> See, you should have i += 2 here, not i++.

Ok
> 
> > +   if ((smpt[i] & SMPT_DESC_TYPE_MAP))
> > +   break;
> > +
> > read_data_mask = SMPT_CMD_READ_DATA(smpt[i]);
> > nor->addr_width = spi_nor_smpt_addr_width(nor, smpt[i]);
> > -   nor->read_dummy = spi_nor_smpt_read_dummy(nor, smpt[i]);
> > +   if (!nor->addr_width)
> > +   nor->addr_width = 3;
> > +
> > +   nor->read_dummy = 8; //spi_nor_smpt_read_dummy(nor,
> > + smpt[i]);
> > nor->read_opcode = SMPT_CMD_OPCODE(smpt[i]);
> > +   pr_info("smpt[%d]=[addr_width:%08x, read_dumy:%08x,
> > + read_opcode:%08x]\n", i, nor->addr_width, nor->read_dummy,
> > + nor->read_opcode);
> > +
> > addr = smpt[i + 1];
> >
> > err = spi_nor_read_raw(nor, addr, 1, _byte);
> 
> And add a trace here to print data_byte and addr.
> 
Logs:
[1.625840] m25p80 spi0.0: found s25fl512s, expected m25p80  
 
[1.631536] Start [addr_width:, read_dumy:, 
read_opcode:] 
[1.639013] spi_nor_get_map_in_use:2882 smpt[0]=08ff65fc 
 
[1.644317] spi_nor_get_ma

RE: [PATCH v3 1/2] mtd: spi-nor: add support to non-uniform SFDP SPI NOR flash memories

[Yogesh Narayan Gaur]

Hi,

> -Original Message-
> From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> Sent: Monday, October 22, 2018 3:41 PM
> To: Yogesh Narayan Gaur 
> Cc: Tudor Ambarus ; rich...@nod.at; Mark
> Brown ; linux-kernel@vger.kernel.org;
> nicolas.fe...@microchip.com; marek.va...@gmail.com;
> cyrille.pitc...@microchip.com; linux-...@lists.infradead.org;
> cristian.bir...@microchip.com; Cyrille Pitchen ;
> computersforpe...@gmail.com; dw...@infradead.org; linux-arm-
> ker...@lists.infradead.org
> Subject: Re: [PATCH v3 1/2] mtd: spi-nor: add support to non-uniform SFDP SPI
> NOR flash memories
> 
> On Mon, 22 Oct 2018 10:03:55 +
> Yogesh Narayan Gaur  wrote:
> 
> > Hi,
> >
> >
> > > -Original Message-
> > > From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> > > Sent: Monday, October 22, 2018 2:46 PM
> > > To: Yogesh Narayan Gaur 
> > > Cc: Tudor Ambarus ; rich...@nod.at;
> > > Mark Brown ; linux-kernel@vger.kernel.org;
> > > nicolas.fe...@microchip.com; marek.va...@gmail.com;
> > > cyrille.pitc...@microchip.com; linux-...@lists.infradead.org;
> > > cristian.bir...@microchip.com; Cyrille Pitchen
> > > ; computersforpe...@gmail.com;
> > > dw...@infradead.org; linux-arm- ker...@lists.infradead.org
> > > Subject: Re: [PATCH v3 1/2] mtd: spi-nor: add support to non-uniform
> > > SFDP SPI NOR flash memories
> > >
> > > On Mon, 22 Oct 2018 06:04:13 +
> > > Yogesh Narayan Gaur  wrote:
> > >
> > >
> > With below patch, it gets stuck in for loop of "+   for (nmaps = 0; i< 
> > smpt_len;
> nmaps++) {".
> >
> > [1.624684] m25p80 spi0.0: found s25fl512s, expected m25p80
> > [1.630377] Start [addr_width:, read_dumy:08,
> read_opcode:]
> > [1.637335] spi_nor_get_map_in_use:2882 smpt[0]=08ff65fc
> > [1.642641] spi_nor_get_map_in_use:2882 smpt[1]=0004
> > [1.647945] spi_nor_get_map_in_use:2882 smpt[2]=04ff65fc
> > [1.653248] spi_nor_get_map_in_use:2882 smpt[3]=0002
> > [1.658551] spi_nor_get_map_in_use:2882 smpt[4]=02ff65fd
> > [1.663855] spi_nor_get_map_in_use:2882 smpt[5]=0004
> > [1.669158] spi_nor_get_map_in_use:2882 smpt[6]=ff0201fe
> > [1.674461] spi_nor_get_map_in_use:2882 smpt[7]=7ff1
> > [1.679766] spi_nor_get_map_in_use:2882 smpt[8]=00037ff4
> > [1.685070] spi_nor_get_map_in_use:2882 smpt[9]=03fbfff4
> > [1.690375] spi_nor_get_map_in_use:2882 smpt[10]=ff0203fe
> > [1.695768] spi_nor_get_map_in_use:2882 smpt[11]=03fbfff4
> > [1.701158] spi_nor_get_map_in_use:2882 smpt[12]=00037ff4
> > [1.706550] spi_nor_get_map_in_use:2882 smpt[13]=7ff1
> > [1.711940] spi_nor_get_map_in_use:2882 smpt[14]=ff0005ff
> > [1.717330] spi_nor_get_map_in_use:2882 smpt[15]=03f4
> > [1.722720] smpt[0]=[addr_width:, read_dumy:08,
> read_opcode:0065]
> > [1.729861] spi_nor_get_map_in_use:2912 map_id=1
> >
> >
> > --- a/drivers/mtd/spi-nor/spi-nor.c
> > +++ b/drivers/mtd/spi-nor/spi-nor.c
> > @@ -2863,26 +2863,36 @@ static u8 spi_nor_smpt_read_dummy(const struct
> spi_nor *nor, const u32 settings)
> >   * @nor:   pointer to a 'struct spi_nor'
> >   * @smpt:  pointer to the sector map parameter table
> >   */
> > -static const u32 *spi_nor_get_map_in_use(struct spi_nor *nor, const
> > u32 *smpt)
> > +static const u32 *spi_nor_get_map_in_use(struct spi_nor *nor, const
> > +u32 *smpt, u32 smpt_len)
> >  {
> > const u32 *ret = NULL;
> > -   u32 i, addr;
> > +   u32 i, addr, nmaps;
> > int err;
> > u8 addr_width, read_opcode, read_dummy;
> > u8 read_data_mask, data_byte, map_id;
> > +   bool map_id_is_valid = false;
> >
> > addr_width = nor->addr_width;
> > read_dummy = nor->read_dummy;
> > read_opcode = nor->read_opcode;
> >
> > +   pr_info("Start [addr_width:%08x, read_dumy:%0x8,
> > + read_opcode:%08x]\n", nor->addr_width, nor->read_dummy,
> > + nor->read_opcode);
> > +
> > +   for (i = 0; i > +   pr_info("%s:%i smpt[%d]=%08x\n", __func__, __LINE__,
> > + i, smpt[i]);
> > +
> > map_id = 0;
> > -   i = 0;
> > /* Determine if there are any optional Detection Command 
> > Descriptors */
> > -   while (!(smpt[i] & SMPT_DESC_TYPE_MAP)) {
> > +   for (i = 0; i< smpt_len; i++) {
> > +

RE: [PATCH v4 0/5] spi: spi-mem: Add driver for NXP FlexSPI controller

[Yogesh Narayan Gaur]

+ Mark Brown

Complete patch series[1]
[1] https://patchwork.ozlabs.org/project/linux-mtd/list/?series=70210

--
Regards,
Yogesh Gaur

> -Original Message-
> From: Yogesh Narayan Gaur [mailto:yogeshnarayan.g...@nxp.com]
> Sent: Thursday, October 11, 2018 4:30 PM
> To: linux-...@lists.infradead.org; boris.brezil...@bootlin.com;
> marek.va...@gmail.com; linux-...@vger.kernel.org;
> devicet...@vger.kernel.org
> Cc: r...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org; linux-
> arm-ker...@lists.infradead.org; computersforpe...@gmail.com;
> frieder.schre...@exceet.de; linux-kernel@vger.kernel.org; Yogesh Narayan
> Gaur 
> Subject: [PATCH v4 0/5] spi: spi-mem: Add driver for NXP FlexSPI controller
> 
> - Add driver for NXP FlexSPI host controller
> 
>  FlexSPI is a flexsible SPI host controller [1], Chapter 30 page 1475,  which
> supports two SPI channels and up to 4 external devices.
>  Each channel supports Single/Dual/Quad/Octal mode data transfer (1/2/4/8
> bidirectional data lines)  i.e. FlexSPI acts as an interface to external 
> devices,
> maximum 4, each with up to 8  bidirectional data lines.
> 
> - Tested this driver with mtd_debug(Erase/Write/Read) utility and JFFS2
> filesystem mounting and booting on NXP LX2160ARDB[2] and LX2160AQDS
> targets.
>  LX2160ARDB is having two NOR slave device connected on single bus A  i.e. A0
> and A1 (CS0 and CS1).
>  LX2160AQDS is having two NOR slave device connected on separate buses  one
> flash on A0 and second on B1 i.e. (CS0 and CS3).
>  Verified this driver on following SPI NOR flashes:
>Micron, mt35xu512aba[3], [Read - 1 bit mode]
>Cypress, s25fl512s, [Read - 1/2/4 bit mode]
> 
> [1] https://www.nxp.com/docs/en/reference-manual/IMXRT1050RM.pdf
> [2] https://patchwork.kernel.org/project/linux-arm-kernel/list/?series=26689
> [3] https://patchwork.ozlabs.org/project/linux-mtd/list/?series=70179
> 
> Yogesh Gaur (5):
>   spi: spi-mem: Add driver for NXP FlexSPI controller
>   dt-bindings: spi: add binding file for NXP FlexSPI controller
>   arm64: dts: lx2160a: add FlexSPI node property
>   arm64: defconfig: enable NXP FlexSPI driver
>   MAINTAINERS: add maintainers for the NXP FlexSPI driver
> 
> Changes for v4:
> - Incorporated review comments for
>   patch 'spi: spi-mem: Add driver for NXP FlexSPI controller'.
> - Incorporated binding file review comments.
> Changes for v3:
> - Incorporated review comments for
>   patch 'spi: spi-mem: Add driver for NXP FlexSPI controller'.
> Changes for v2:
> - Incorporated Boris review comments and drop below patches as per the
> comments.
>  - Patch 'spi: add slave device size in spi_device struct'
>  - Patch 'spi: add flags for octal I/O data transfer'
> - Incorporated DTS and Binding file review comments of Shawn Guo and Rob
> Herring.
> 
>  .../devicetree/bindings/spi/spi-nxp-fspi.txt   |   39 +
>  MAINTAINERS|6 +
>  arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts  |   22 +
>  arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi |   12 +
>  arch/arm64/configs/defconfig   |1 +
>  drivers/spi/Kconfig|   10 +
>  drivers/spi/Makefile   |1 +
>  drivers/spi/spi-nxp-fspi.c | 1158 
> 
>  8 files changed, 1249 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/spi/spi-nxp-fspi.txt
>  create mode 100644 drivers/spi/spi-nxp-fspi.c
> 
> --
> 2.7.4

RE: [PATCH v3 1/2] mtd: spi-nor: add support to non-uniform SFDP SPI NOR flash memories

[Yogesh Narayan Gaur]

Hi,


> -Original Message-
> From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> Sent: Monday, October 22, 2018 2:46 PM
> To: Yogesh Narayan Gaur 
> Cc: Tudor Ambarus ; rich...@nod.at; Mark
> Brown ; linux-kernel@vger.kernel.org;
> nicolas.fe...@microchip.com; marek.va...@gmail.com;
> cyrille.pitc...@microchip.com; linux-...@lists.infradead.org;
> cristian.bir...@microchip.com; Cyrille Pitchen ;
> computersforpe...@gmail.com; dw...@infradead.org; linux-arm-
> ker...@lists.infradead.org
> Subject: Re: [PATCH v3 1/2] mtd: spi-nor: add support to non-uniform SFDP SPI
> NOR flash memories
> 
> On Mon, 22 Oct 2018 06:04:13 +
> Yogesh Narayan Gaur  wrote:
> 
> 
With below patch, it gets stuck in for loop of "+   for (nmaps = 0; i< 
smpt_len; nmaps++) {".

[1.624684] m25p80 spi0.0: found s25fl512s, expected m25p80
[1.630377] Start [addr_width:, read_dumy:08, read_opcode:]
[1.637335] spi_nor_get_map_in_use:2882 smpt[0]=08ff65fc
[1.642641] spi_nor_get_map_in_use:2882 smpt[1]=0004
[1.647945] spi_nor_get_map_in_use:2882 smpt[2]=04ff65fc
[1.653248] spi_nor_get_map_in_use:2882 smpt[3]=0002
[1.658551] spi_nor_get_map_in_use:2882 smpt[4]=02ff65fd
[1.663855] spi_nor_get_map_in_use:2882 smpt[5]=0004
[1.669158] spi_nor_get_map_in_use:2882 smpt[6]=ff0201fe
[1.674461] spi_nor_get_map_in_use:2882 smpt[7]=7ff1
[1.679766] spi_nor_get_map_in_use:2882 smpt[8]=00037ff4
[1.685070] spi_nor_get_map_in_use:2882 smpt[9]=03fbfff4
[1.690375] spi_nor_get_map_in_use:2882 smpt[10]=ff0203fe
[1.695768] spi_nor_get_map_in_use:2882 smpt[11]=03fbfff4
[1.701158] spi_nor_get_map_in_use:2882 smpt[12]=00037ff4
[1.706550] spi_nor_get_map_in_use:2882 smpt[13]=7ff1
[1.711940] spi_nor_get_map_in_use:2882 smpt[14]=ff0005ff
[1.717330] spi_nor_get_map_in_use:2882 smpt[15]=03f4
[1.722720] smpt[0]=[addr_width:, read_dumy:08, read_opcode:0065]
[1.729861] spi_nor_get_map_in_use:2912 map_id=1


--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -2863,26 +2863,36 @@ static u8 spi_nor_smpt_read_dummy(const struct spi_nor 
*nor, const u32 settings)
  * @nor:   pointer to a 'struct spi_nor'
  * @smpt:  pointer to the sector map parameter table
  */
-static const u32 *spi_nor_get_map_in_use(struct spi_nor *nor, const u32 *smpt)
+static const u32 *spi_nor_get_map_in_use(struct spi_nor *nor, const u32 *smpt, 
u32 smpt_len)
 {
const u32 *ret = NULL;
-   u32 i, addr;
+   u32 i, addr, nmaps;
int err;
u8 addr_width, read_opcode, read_dummy;
u8 read_data_mask, data_byte, map_id;
+   bool map_id_is_valid = false;

addr_width = nor->addr_width;
read_dummy = nor->read_dummy;
read_opcode = nor->read_opcode;

+   pr_info("Start [addr_width:%08x, read_dumy:%0x8, read_opcode:%08x]\n", 
nor->addr_width, nor->read_dummy, nor->read_opcode);
+
+   for (i = 0; iaddr_width = spi_nor_smpt_addr_width(nor, smpt[i]);
nor->read_dummy = spi_nor_smpt_read_dummy(nor, smpt[i]);
nor->read_opcode = SMPT_CMD_OPCODE(smpt[i]);
+   pr_info("smpt[%d]=[addr_width:%08x, read_dumy:%0x8, 
read_opcode:%08x]\n", i, nor->addr_width, nor->read_dummy, nor->read_opcode);
+
addr = smpt[i + 1];

err = spi_nor_read_raw(nor, addr, 1, _byte);
@@ -2894,18 +2904,36 @@ static const u32 *spi_nor_get_map_in_use(struct spi_nor 
*nor, const u32 *smpt)
 * Configuration that is currently in use.
 */
map_id = map_id << 1 | !!(data_byte & read_data_mask);
+   map_id_is_valid = true;
i = i + 2;
}

-   /* Find the matching configuration map */
-   while (SMPT_MAP_ID(smpt[i]) != map_id) {
-   if (smpt[i] & SMPT_DESC_END)
-   goto out;
+   if (map_id_is_valid)
+   pr_info("%s:%i map_id=%d\n", __func__, __LINE__, map_id);
+   else
+   pr_info("%s:%i NO map_id\n", __func__, __LINE__);
+
+   for (nmaps = 0; i< smpt_len; nmaps++) {
+   if((smpt[i] & SMPT_DESC_TYPE_MAP))
+   continue;
+
+   if(!map_id_is_valid) {
+   if (nmaps) {
+   ret = NULL;
+   break;
+   }
+
+   ret = smpt+i;
+   } else if (map_id == SMPT_MAP_ID(smpt[i])) {
+   ret = smpt+i;
+   break;
+   }
+
/* increment the table index to the next map */
i += SMPT_MAP_REGION_COUNT(smpt[i]) + 1;
}

-   ret = smpt + i;
+   pr_info("End [addr_width:%08x, read_dumy:%0x8, read_opcode:%08x]\n", 
nor->addr_width, nor->read_dummy, nor->read_opcode);
/* fall through */
 out:
nor->addr_width = addr_width;

RE: [PATCH v3 1/2] mtd: spi-nor: add support to non-uniform SFDP SPI NOR flash memories

[Yogesh Narayan Gaur]

Hi,

> -Original Message-
> From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> Sent: Monday, October 22, 2018 3:57 PM
> To: Yogesh Narayan Gaur 
> Cc: Tudor Ambarus ; rich...@nod.at; Mark
> Brown ; linux-kernel@vger.kernel.org;
> nicolas.fe...@microchip.com; marek.va...@gmail.com;
> cyrille.pitc...@microchip.com; linux-...@lists.infradead.org;
> cristian.bir...@microchip.com; Cyrille Pitchen ;
> computersforpe...@gmail.com; dw...@infradead.org; linux-arm-
> ker...@lists.infradead.org
> Subject: Re: [PATCH v3 1/2] mtd: spi-nor: add support to non-uniform SFDP SPI
> NOR flash memories
> 
> On Mon, 22 Oct 2018 10:03:55 +
> Yogesh Narayan Gaur  wrote:
> 
> > --- a/drivers/mtd/spi-nor/spi-nor.c
> > +++ b/drivers/mtd/spi-nor/spi-nor.c
> > @@ -2863,26 +2863,36 @@ static u8 spi_nor_smpt_read_dummy(const struct
> spi_nor *nor, const u32 settings)
> >   * @nor:   pointer to a 'struct spi_nor'
> >   * @smpt:  pointer to the sector map parameter table
> >   */
> > -static const u32 *spi_nor_get_map_in_use(struct spi_nor *nor, const
> > u32 *smpt)
> > +static const u32 *spi_nor_get_map_in_use(struct spi_nor *nor, const
> > +u32 *smpt, u32 smpt_len)
> >  {
> > const u32 *ret = NULL;
> > -   u32 i, addr;
> > +   u32 i, addr, nmaps;
> > int err;
> > u8 addr_width, read_opcode, read_dummy;
> > u8 read_data_mask, data_byte, map_id;
> > +   bool map_id_is_valid = false;
> >
> > addr_width = nor->addr_width;
> > read_dummy = nor->read_dummy;
> > read_opcode = nor->read_opcode;
> >
> > +   pr_info("Start [addr_width:%08x, read_dumy:%0x8,
> > + read_opcode:%08x]\n", nor->addr_width, nor->read_dummy,
> > + nor->read_opcode);
> > +
> > +   for (i = 0; i > +   pr_info("%s:%i smpt[%d]=%08x\n", __func__, __LINE__,
> > + i, smpt[i]);
> > +
> > map_id = 0;
> > -   i = 0;
> > /* Determine if there are any optional Detection Command 
> > Descriptors */
> > -   while (!(smpt[i] & SMPT_DESC_TYPE_MAP)) {
> > +   for (i = 0; i< smpt_len; i++) {
> 
>  ^ i += 2) {
> 
> > +   if ((smpt[i] & SMPT_DESC_TYPE_MAP))
> > +   break;
> > +
> > read_data_mask = SMPT_CMD_READ_DATA(smpt[i]);
> > nor->addr_width = spi_nor_smpt_addr_width(nor, smpt[i]);
> > nor->read_dummy = spi_nor_smpt_read_dummy(nor, smpt[i]);
> > nor->read_opcode = SMPT_CMD_OPCODE(smpt[i]);
> > +   pr_info("smpt[%d]=[addr_width:%08x, read_dumy:%0x8,
> > + read_opcode:%08x]\n", i, nor->addr_width, nor->read_dummy,
> > + nor->read_opcode);
> > +
> > addr = smpt[i + 1];
> >
> > err = spi_nor_read_raw(nor, addr, 1, _byte); @@
> > -2894,18 +2904,36 @@ static const u32 *spi_nor_get_map_in_use(struct
> spi_nor *nor, const u32 *smpt)
> >  * Configuration that is currently in use.
> >  */
> > map_id = map_id << 1 | !!(data_byte & read_data_mask);
> > +   map_id_is_valid = true;
> > i = i + 2;
> 
> Drop the above line (i = i + 2).
> 

[1.632190] Start [addr_width:, read_dumy:08, read_opcode:]  
 
[1.639148] spi_nor_get_map_in_use:2882 smpt[0]=08ff65fc 
 
[1.644451] spi_nor_get_map_in_use:2882 smpt[1]=0004 
 
[1.649755] spi_nor_get_map_in_use:2882 smpt[2]=04ff65fc 
 
[1.655057] spi_nor_get_map_in_use:2882 smpt[3]=0002 
 
[1.660360] spi_nor_get_map_in_use:2882 smpt[4]=02ff65fd 
 
[1.665662] spi_nor_get_map_in_use:2882 smpt[5]=0004 
 
[1.670965] spi_nor_get_map_in_use:2882 smpt[6]=ff0201fe 
 
[1.676267] spi_nor_get_map_in_use:2882 smpt[7]=7ff1 
 
[1.681571] spi_nor_get_map_in_use:2882 smpt[8]=00037ff4 
  

RE: [PATCH v3 1/2] mtd: spi-nor: add support to non-uniform SFDP SPI NOR flash memories

[Yogesh Narayan Gaur]

Hi,

> -Original Message-
> From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> Sent: Monday, October 22, 2018 4:23 PM
> To: Yogesh Narayan Gaur ;
> cristian.bir...@microchip.com
> Cc: Tudor Ambarus ; rich...@nod.at; Mark
> Brown ; linux-kernel@vger.kernel.org;
> nicolas.fe...@microchip.com; marek.va...@gmail.com;
> cyrille.pitc...@microchip.com; linux-...@lists.infradead.org; Cyrille Pitchen
> ; computersforpe...@gmail.com;
> dw...@infradead.org; linux-arm-ker...@lists.infradead.org
> Subject: Re: [PATCH v3 1/2] mtd: spi-nor: add support to non-uniform SFDP SPI
> NOR flash memories
> 
> On Mon, 22 Oct 2018 12:46:27 +0200
> Boris Brezillon  wrote:
> 
> > On Mon, 22 Oct 2018 10:39:48 +
> > Yogesh Narayan Gaur  wrote:
> >
> > >
> > > [1.632190] Start [addr_width:, read_dumy:08,
> read_opcode:]
> > > [1.639148] spi_nor_get_map_in_use:2882 smpt[0]=08ff65fc
> > > [1.644451] spi_nor_get_map_in_use:2882 smpt[1]=0004
> > > [1.649755] spi_nor_get_map_in_use:2882 smpt[2]=04ff65fc
> > > [1.655057] spi_nor_get_map_in_use:2882 smpt[3]=0002
> > > [1.660360] spi_nor_get_map_in_use:2882 smpt[4]=02ff65fd
> > > [1.665662] spi_nor_get_map_in_use:2882 smpt[5]=0004
> > > [1.670965] spi_nor_get_map_in_use:2882 smpt[6]=ff0201fe
> > > [1.676267] spi_nor_get_map_in_use:2882 smpt[7]=7ff1
> > > [1.681571] spi_nor_get_map_in_use:2882 smpt[8]=00037ff4
> > > [1.686874] spi_nor_get_map_in_use:2882 smpt[9]=03fbfff4
> > > [1.692176] spi_nor_get_map_in_use:2882 smpt[10]=ff0203fe
> > > [1.697566] spi_nor_get_map_in_use:2882 smpt[11]=03fbfff4
> > > [1.702954] spi_nor_get_map_in_use:2882 smpt[12]=00037ff4
> > > [1.708343] spi_nor_get_map_in_use:2882 smpt[13]=7ff1
> > > [1.713732] spi_nor_get_map_in_use:2882 smpt[14]=ff0005ff
> > > [1.719120] spi_nor_get_map_in_use:2882 smpt[15]=03f4
> > > [1.724509] smpt[0]=[addr_width:, read_dumy:08,
> read_opcode:0065]
> > > [1.731650] smpt[1]=[addr_width:, read_dumy:08,
> read_opcode:]
> > > [1.738791] smpt[2]=[addr_width:, read_dumy:08,
> read_opcode:0065]
> >
> > You still don't print read_dummy correctly: %0x8 -> %08x.
> >
> > Can you add
> >
> > if (!nor->addr_width)
> > nor->addr_width = 3;
> >
> > After the
> >
> > nor->addr_width = spi_nor_smpt_addr_width(nor, smpt[i]);
> >
> > line.
> 
> And you should also try to force ->read_dummy to 8, because according to the
> spec, the default read_latency is 8 for this chip. With that in place, you 
> should
> get an map_id of 1, 3 or 5.
> 

Below is the log output.
I have forced the read_dummy as 8 and addr_width is programmed as 3.

[1.625176] m25p80 spi0.0: found s25fl512s, expected m25p80  
 
[1.630875] Start [addr_width:, read_dumy:, 
read_opcode:] 
[1.638352] spi_nor_get_map_in_use:2882 smpt[0]=08ff65fc 
 
[1.643658] spi_nor_get_map_in_use:2882 smpt[1]=0004 
 
[1.648963] spi_nor_get_map_in_use:2882 smpt[2]=04ff65fc 
 
[1.654266] spi_nor_get_map_in_use:2882 smpt[3]=0002 
 
[1.659569] spi_nor_get_map_in_use:2882 smpt[4]=02ff65fd 
 
[1.664872] spi_nor_get_map_in_use:2882 smpt[5]=0004 
 
[1.670175] spi_nor_get_map_in_use:2882 smpt[6]=ff0201fe 
 
[1.675477] spi_nor_get_map_in_use:2882 smpt[7]=7ff1 
 
[1.680782] spi_nor_get_map_in_use:2882 smpt[8]=00037ff4 
 
[1.686084] spi_nor_get_map_in_use:2882 smpt[9]=03fbfff4 
 
[1.691391] spi_nor_get_map_in_use:2882 smpt[10]=ff0203fe
 
[1.696782] spi_nor_get_map_in_use:2882 smpt[11]=03fbfff4
 
[1.702171] spi_nor_get_map_in_use:2882 smpt[12]=00

RE: [PATCH v3 1/2] mtd: spi-nor: add support to non-uniform SFDP SPI NOR flash memories

[Yogesh Narayan Gaur]

Hi,

> -Original Message-
> From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> Sent: Monday, October 22, 2018 5:13 PM
> To: Yogesh Narayan Gaur 
> Cc: cristian.bir...@microchip.com; Tudor Ambarus
> ; rich...@nod.at; Mark Brown
> ; linux-kernel@vger.kernel.org;
> nicolas.fe...@microchip.com; marek.va...@gmail.com;
> cyrille.pitc...@microchip.com; linux-...@lists.infradead.org; Cyrille Pitchen
> ; computersforpe...@gmail.com;
> dw...@infradead.org; linux-arm-ker...@lists.infradead.org
> Subject: Re: [PATCH v3 1/2] mtd: spi-nor: add support to non-uniform SFDP SPI
> NOR flash memories
> 
> On Mon, 22 Oct 2018 11:03:09 +
> Yogesh Narayan Gaur  wrote:
> 
> > Hi,
> >
> > > -Original Message-
> > > From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> > > Sent: Monday, October 22, 2018 4:23 PM
> > > To: Yogesh Narayan Gaur ;
> > > cristian.bir...@microchip.com
> > > Cc: Tudor Ambarus ; rich...@nod.at;
> > > Mark Brown ; linux-kernel@vger.kernel.org;
> > > nicolas.fe...@microchip.com; marek.va...@gmail.com;
> > > cyrille.pitc...@microchip.com; linux-...@lists.infradead.org;
> > > Cyrille Pitchen ;
> > > computersforpe...@gmail.com; dw...@infradead.org;
> > > linux-arm-ker...@lists.infradead.org
> > > Subject: Re: [PATCH v3 1/2] mtd: spi-nor: add support to non-uniform
> > > SFDP SPI NOR flash memories
> > >
> > > On Mon, 22 Oct 2018 12:46:27 +0200
> > > Boris Brezillon  wrote:
> > >
> > > > On Mon, 22 Oct 2018 10:39:48 + Yogesh Narayan Gaur
> > > >  wrote:
> > > >
Patch used

--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -2863,26 +2863,39 @@ static u8 spi_nor_smpt_read_dummy(const struct spi_nor 
*nor, const u32 settings)
  * @nor:   pointer to a 'struct spi_nor'
  * @smpt:  pointer to the sector map parameter table
  */
-static const u32 *spi_nor_get_map_in_use(struct spi_nor *nor, const u32 *smpt)
+static const u32 *spi_nor_get_map_in_use(struct spi_nor *nor, const u32 *smpt, 
u32 smpt_len)
 {
const u32 *ret = NULL;
-   u32 i, addr;
+   u32 i, addr, nmaps;
int err;
u8 addr_width, read_opcode, read_dummy;
u8 read_data_mask, data_byte, map_id;
+   bool map_id_is_valid = false;

addr_width = nor->addr_width;
read_dummy = nor->read_dummy;
read_opcode = nor->read_opcode;

+   pr_info("Start [addr_width:%08x, read_dumy:%08x, read_opcode:%08x]\n", 
nor->addr_width, nor->read_dummy, nor->read_opcode);
+
+   for (i = 0; iaddr_width = spi_nor_smpt_addr_width(nor, smpt[i]);
-   nor->read_dummy = spi_nor_smpt_read_dummy(nor, smpt[i]);
+   if (!nor->addr_width)
+   nor->addr_width = 3;
+
+   nor->read_dummy = 8; //spi_nor_smpt_read_dummy(nor, smpt[i]);
nor->read_opcode = SMPT_CMD_OPCODE(smpt[i]);
+   pr_info("smpt[%d]=[addr_width:%08x, read_dumy:%08x, 
read_opcode:%08x]\n", i, nor->addr_width, nor->read_dummy, nor->read_opcode);
+
addr = smpt[i + 1];

err = spi_nor_read_raw(nor, addr, 1, _byte);
@@ -2894,18 +2907,37 @@ static const u32 *spi_nor_get_map_in_use(struct spi_nor 
*nor, const u32 *smpt)
 * Configuration that is currently in use.
 */
map_id = map_id << 1 | !!(data_byte & read_data_mask);
-   i = i + 2;
+   map_id_is_valid = true;
}

-   /* Find the matching configuration map */
-   while (SMPT_MAP_ID(smpt[i]) != map_id) {
-   if (smpt[i] & SMPT_DESC_END)
-   goto out;
+   if (map_id_is_valid)
+   pr_info("%s:%i map_id=%d smpt_len:%d i=:%d\n", __func__, 
__LINE__, map_id, smpt_len, i);
+   else
+   pr_info("%s:%i NO map_id\n", __func__, __LINE__);
+
+   for (nmaps = 0; i< smpt_len; nmaps++) {
+   if(!(smpt[i] & SMPT_DESC_TYPE_MAP)) {
+   i += 2;
+   continue;
+   }
+
+   if(!map_id_is_valid) {
+   if (nmaps) {
+   ret = NULL;
+   break;
+   }
+
+   ret = smpt+i;
+   } else if (map_id == SMPT_MAP_ID(smpt[i])) {
+   ret = smpt+i;
+   break;
+   }
+
/* increment the table index to the next map */
i += SMPT_MAP_REGION_COUNT(smpt[i]) + 1;
}

-   ret = smpt + i;
+   pr_info("End [addr_width:%08x, read_dumy:%08x, read_opcode:%08x]\n"

RE: [PATCH v4 0/5] spi: spi-mem: Add driver for NXP FlexSPI controller

[Yogesh Narayan Gaur]

> -Original Message-
> From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> Sent: Monday, October 22, 2018 5:20 PM
> To: Yogesh Narayan Gaur 
> Cc: linux-...@lists.infradead.org; marek.va...@gmail.com; linux-
> s...@vger.kernel.org; devicet...@vger.kernel.org; Mark Brown
> ; r...@kernel.org; mark.rutl...@arm.com;
> shawn...@kernel.org; linux-arm-ker...@lists.infradead.org;
> computersforpe...@gmail.com; frieder.schre...@exceet.de; linux-
> ker...@vger.kernel.org
> Subject: Re: [PATCH v4 0/5] spi: spi-mem: Add driver for NXP FlexSPI 
> controller
> 
> On Mon, 22 Oct 2018 11:43:40 +
> Yogesh Narayan Gaur  wrote:
> 
> > + Mark Brown
> >
> > Complete patch series[1]
> > [1]
> > https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpat
> > chwork.ozlabs.org%2Fproject%2Flinux-
> mtd%2Flist%2F%3Fseries%3D70210
> > ;data=02%7C01%7Cyogeshnarayan.gaur%40nxp.com%7C97207a816c9049d3d
> 49b08d
> >
> 638148f67%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C636758058
> 298796
> >
> 837sdata=bRHDHAFzwrbeATicJUpv2WpFnxaeAD%2BnVHLAmsXKbKI%3D
> res
> > erved=0
> 
> Please resend the patch series with a "PATCH RESEND v4" prefix and explain why
> you resend it in the cover letter.
> 
Ok, sure.

Thanks

> >
> > --
> > Regards,
> > Yogesh Gaur
> >
> > > -Original Message-
> > > From: Yogesh Narayan Gaur [mailto:yogeshnarayan.g...@nxp.com]
> > > Sent: Thursday, October 11, 2018 4:30 PM
> > > To: linux-...@lists.infradead.org; boris.brezil...@bootlin.com;
> > > marek.va...@gmail.com; linux-...@vger.kernel.org;
> > > devicet...@vger.kernel.org
> > > Cc: r...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org;
> > > linux- arm-ker...@lists.infradead.org; computersforpe...@gmail.com;
> > > frieder.schre...@exceet.de; linux-kernel@vger.kernel.org; Yogesh
> > > Narayan Gaur 
> > > Subject: [PATCH v4 0/5] spi: spi-mem: Add driver for NXP FlexSPI
> > > controller
> > >
> > > - Add driver for NXP FlexSPI host controller
> > >
> > >  FlexSPI is a flexsible SPI host controller [1], Chapter 30 page
> > > 1475,  which supports two SPI channels and up to 4 external devices.
> > >  Each channel supports Single/Dual/Quad/Octal mode data transfer
> > > (1/2/4/8 bidirectional data lines)  i.e. FlexSPI acts as an
> > > interface to external devices, maximum 4, each with up to 8  bidirectional
> data lines.
> > >
> > > - Tested this driver with mtd_debug(Erase/Write/Read) utility and
> > > JFFS2 filesystem mounting and booting on NXP LX2160ARDB[2] and
> > > LX2160AQDS targets.
> > >  LX2160ARDB is having two NOR slave device connected on single bus A
> > > i.e. A0 and A1 (CS0 and CS1).
> > >  LX2160AQDS is having two NOR slave device connected on separate
> > > buses  one flash on A0 and second on B1 i.e. (CS0 and CS3).
> > >  Verified this driver on following SPI NOR flashes:
> > >Micron, mt35xu512aba[3], [Read - 1 bit mode]
> > >Cypress, s25fl512s, [Read - 1/2/4 bit mode]
> > >
> > > [1]
> > > https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fw
> > > ww.nxp.com%2Fdocs%2Fen%2Freference-
> manual%2FIMXRT1050RM.pdfdata
> > >
> =02%7C01%7Cyogeshnarayan.gaur%40nxp.com%7C97207a816c9049d3d49b08
> d638
> > >
> 148f67%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C636758058298
> 8068
> > >
> 45sdata=HpuTjqfMqDvobNPD5Ww3zIaotrBXFKgOIh2%2BQ%2BGSE1o%3
> D
> > > reserved=0 [2]
> > > https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fp
> > > atchwork.kernel.org%2Fproject%2Flinux-arm-kernel%2Flist%2F%3Fseries%
> > >
> 3D26689data=02%7C01%7Cyogeshnarayan.gaur%40nxp.com%7C97207a
> 816c
> > >
> 9049d3d49b08d638148f67%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C
> 0%7C
> > >
> 636758058298806845sdata=v1d%2Fe91xeDzhAUvz8X5ousbEPwwgMFxY1
> CBkc
> > > Dpuf70%3Dreserved=0 [3]
> > > https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fp
> > > atchwork.ozlabs.org%2Fproject%2Flinux-mtd%2Flist%2F%3Fseries%3D70179
> > >
> data=02%7C01%7Cyogeshnarayan.gaur%40nxp.com%7C97207a816c904
> 9d3d
> > >
> 49b08d638148f67%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C636
> 7580
> > >
> 58298806845sdata=vE%2FRQW9B4dU9rJqY2RZlNB1uH8smVKsCrGyEOs7
> 50Yk%
> > > 3Dreserved=0
> > >
> > > Yogesh Gaur (5):
> > >   spi: spi-mem: Add driver for NXP FlexSPI controller
> > >  

RE: [PATCH v3 1/2] mtd: spi-nor: add support to non-uniform SFDP SPI NOR flash memories

[Yogesh Narayan Gaur]

HI,

> -Original Message-
> From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> Sent: Tuesday, October 23, 2018 11:10 AM
> To: Yogesh Narayan Gaur 
> Cc: cristian.bir...@microchip.com; Tudor Ambarus
> ; rich...@nod.at; Mark Brown
> ; linux-kernel@vger.kernel.org;
> nicolas.fe...@microchip.com; marek.va...@gmail.com;
> cyrille.pitc...@microchip.com; linux-...@lists.infradead.org; Cyrille Pitchen
> ; computersforpe...@gmail.com;
> dw...@infradead.org; linux-arm-ker...@lists.infradead.org
> Subject: Re: [PATCH v3 1/2] mtd: spi-nor: add support to non-uniform SFDP SPI
> NOR flash memories
> 
> On Tue, 23 Oct 2018 04:47:33 +
> Yogesh Narayan Gaur  wrote:
> 
> > Hi,
> >
> > > -Original Message-
[]
> 
> Ok, so now the opcode and address are matching the values in the spec.
> Can you check what's sent to the SPI controller side (in your
> ->exec_op() implementation), just to make sure the m25p80 propagates
> the information correctly? When you do that, make sure you also print the
> buswidth of each element (op->cmd.buswidth, op->addr.buswidth,
> op->dummy.buswidth and op->data.buswidth).
> 
> Can you also print the read_data_mask value here.

I have added the prints in m25p80_read() and in flexspi controller prepare_lut 
and read_rxfifo() func.
In these have added prints for data variable of struct op and data which being 
read by the controller from the flash.

[2.091467] smpt[0]=[addr_width:0003, read_dumy:0008, 
read_opcode:0065, data_mask:0008]  
[2.099113] m25p80_read, nor[op:0065 addr_width:0003, 
dummy:0008, len:0001   
[2.107367] m25p80_read, cmd[opcode:65 bwidth:1] aadr[val:4, nbytes:3, 
bwidth:1] 
[2.114753] m25p80_read, dummy[nbytes:1 bwidth:1] data[bwidth:1, nbytes:1]   

[2.121706] nxp_fspi_prepare_lut cmd[opcode:65 bwidth:1] aadr[val:4, 
nbytes:3, bwidth:1] 
[2.129786] dummy[nbytes:1 bwidth:1] data[dir:0 bwidth:1, nbytes:1]  

[2.136132] nxp-fspi 20c.flexspi: CMD[65] lutval[0:8180465
1:24003008  2:0 3:0]   
[2.144223] nxp_fspi_read_rxfifo, ReadData op.buf[0x00]  
   
[2.151004] smpt_read[1] addr[0004], data_byte[] err:   

  
[2.157782] smpt[2]=[addr_width:0003, read_dumy:0008, 
read_opcode:0065, data_mask:0004]  
[2.165429] m25p80_read, nor[op:0065 addr_width:0003, 
dummy:0008, len:0001 
[2.173683] m25p80_read, cmd[opcode:65 bwidth:1] aadr[val:2, nbytes:3, 
bwidth:1]   
[2.181068] m25p80_read, dummy[nbytes:1 bwidth:1] data[bwidth:1, nbytes:1]   
  
[2.188021] nxp_fspi_prepare_lut cmd[opcode:65 bwidth:1] aadr[val:2, 
nbytes:3, bwidth:1]   
[2.196101] dummy[nbytes:1 bwidth:1] data[dir:0 bwidth:1, nbytes:1]  
 
[2.202447] nxp-fspi 20c.flexspi: CMD[65] lutval[0:8180465
1:24003008  2:0 3:0]   
[2.210539] nxp_fspi_read_rxfifo, ReadData op.buf[0x02]  
  
[2.217319] smpt_read[3] addr[0002], data_byte[0002] err:
 


[2.224098] smpt[4]=[addr_width:0003, read_dumy:0008, 
read_opcode:0065, data_mask:0002] 
[2.231744] m25p80_read, nor[op:0065 addr_width:0003, 
dummy:0008, len:0001  
[2.239998] m25p80_read, cmd[opcode:65 bwidth:1] aadr[val:4, nbytes:3, 
bwidth:1] 
[2.247383] m25p80_read, dummy[nbytes:1 bwidth:1] data[bwidth:1, nbytes:1]   
  
[2.254336] nxp_fspi_prepare_lut cmd[opcode:65 bwidth:1] aadr[val:4, 
nbytes:3, bwidth:1]
[2.262416] dummy[nbytes:1 bwidth:1] data[dir:0 bwidth:1, nbytes:1]  
  
[2.268762] nxp-fspi 20c.flexspi: CMD[65] lutval[0:8180465
1:24003008  2:0 3:0] 
[2.276854] nxp_fspi_read_rxfifo, ReadData op.buf[0x00]  
   
[2.283634] smpt_read[5] addr[0004], data_byte[] err:
 


[2.290412] spi_nor_get_map_in_use:2915 map_id=0 smpt_len:16 i=:6
 
[2.296496] End [addr_width:0003, read_dumy:0008, 
read_opcode:0065] ReturnVal:
[2.305444] spi_nor_parse_smpt:3065  
 
[2.308924] m25p80 spi0.0: failed to parse SMPT (err = -22)  
 

RE: [PATCH v3 1/2] mtd: spi-nor: add support to non-uniform SFDP SPI NOR flash memories

[Yogesh Narayan Gaur]

Hi Boris,

> -Original Message-
> From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> Sent: Wednesday, October 17, 2018 1:00 PM
> To: Yogesh Narayan Gaur 
> Cc: Cyrille Pitchen ; Tudor Ambarus
> ; marek.va...@gmail.com;
> dw...@infradead.org; computersforpe...@gmail.com; rich...@nod.at;
> linux-kernel@vger.kernel.org; nicolas.fe...@microchip.com;
> cyrille.pitc...@microchip.com; linux-...@lists.infradead.org; linux-arm-
> ker...@lists.infradead.org; cristian.bir...@microchip.com
> Subject: Re: [PATCH v3 1/2] mtd: spi-nor: add support to non-uniform SFDP SPI
> NOR flash memories
> 
> On Wed, 17 Oct 2018 09:10:45 +0200
> Boris Brezillon  wrote:
> 
> > On Wed, 17 Oct 2018 09:07:24 +0200
> > Boris Brezillon  wrote:
> >
> > > On Wed, 17 Oct 2018 02:07:43 +
> > > Yogesh Narayan Gaur  wrote:
> > >
> > > > >
> > > > Actually there is no entry of s25fs512s in current spi-nor.c file.
> > > > For my connected flash part, jedec ID read points to s25fl512s. I
> > > > have asked my board team to confirm the name of exact connected
> > > > flash part. When I check the data sheet of s25fs512s, it also
> > > > points to the same Jedec ID information. { "s25fl512s",
> > > > INFO(0x010220, 0x4d00, 256
> > > > * 1024, 256, }
> > > >
> > > > But as stated earlier, if I skip reading SFDP or read using 1-1-1
> > > > protocol then read are always correct. For 1-4-4 protocol read are
> > > > wrong and on further debugging found that Read code of 0x6C is
> > > > being send as opcode instead of 0xEC.
> > > >
> > > > If I revert this patch, reads are working fine.
> > >
> > > Can you try with the following patch?
> > >
> >
> > Hm, nevermind. The problem is actually not related to 4B vs non-4B
> > mode but 1-1-4 vs 1-4-4 modes.
Yes, that's only I have stated in my first mail that instead of 1-4-4 mode read 
opcode is being sent for 1-1-4 mode.
> >
> 
> Can you try with this patch applied?
> 
With suggested patch, read for protocol 1-4-4 working correctly.

[1.625360] m25p80 spi0.0: found s25fl512s, expected m25p80  
 
[1.631094] m25p80 spi0.0: failed to parse SMPT (err = -22)  
 
[1.636661] 261 8c4c780 opcode(read:eb, pp:2, erase:d8)  
 
[1.641878] 266 8c4c780 opcode(read:ec, pp:12, erase:dc) 
 
[1.647200] m25p80 spi0.0: s25fl512s (65536 Kbytes) 

Without this patch, param_headers are getting freed and restoring previous 
erase map i.e. opcode related to 1-1-4 protocol.

--
Regards
Yogesh Gaur

> --->8---
> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c 
> index
> 9407ca5f9443..cf33d834698c 100644
> --- a/drivers/mtd/spi-nor/spi-nor.c
> +++ b/drivers/mtd/spi-nor/spi-nor.c
> @@ -3132,6 +3132,17 @@ static int spi_nor_parse_sfdp(struct spi_nor *nor,
> switch (SFDP_PARAM_HEADER_ID(param_header)) {
> case SFDP_SECTOR_MAP_ID:
> err = spi_nor_parse_smpt(nor, param_header);
> +   if (err) {
> +   dev_warn(dev,
> +"failed to parse SMPT (err = %d)\n",
> +err);
> +   /*
> +* SMPT parsing is optional, let's not drop
> +* all information we extracted so far just
> +* because it failed.
> +*/
> +   err = 0;
> +   }
> break;
> 
> default:

RE: [PATCH v3 1/2] mtd: spi-nor: add support to non-uniform SFDP SPI NOR flash memories

[Yogesh Narayan Gaur]

Hi Tudor,

> -Original Message-
> From: Tudor Ambarus [mailto:tudor.amba...@microchip.com]
> Sent: Wednesday, October 17, 2018 1:31 PM
> To: Yogesh Narayan Gaur ; Boris Brezillon
> 
> Cc: Cyrille Pitchen ; marek.va...@gmail.com;
> dw...@infradead.org; computersforpe...@gmail.com; rich...@nod.at;
> linux-kernel@vger.kernel.org; nicolas.fe...@microchip.com;
> cyrille.pitc...@microchip.com; linux-...@lists.infradead.org; linux-arm-
> ker...@lists.infradead.org; cristian.bir...@microchip.com
> Subject: Re: [PATCH v3 1/2] mtd: spi-nor: add support to non-uniform SFDP SPI
> NOR flash memories
> 
> Hi, Yogesh,
> 
> On 10/17/2018 10:46 AM, Yogesh Narayan Gaur wrote:
> > Hi Boris,
> >
> >> -Original Message-
> >> From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> >> Sent: Wednesday, October 17, 2018 1:00 PM
> >> To: Yogesh Narayan Gaur 
> >> Cc: Cyrille Pitchen ; Tudor Ambarus
> >> ; marek.va...@gmail.com;
> >> dw...@infradead.org; computersforpe...@gmail.com; rich...@nod.at;
> >> linux-kernel@vger.kernel.org; nicolas.fe...@microchip.com;
> >> cyrille.pitc...@microchip.com; linux-...@lists.infradead.org;
> >> linux-arm- ker...@lists.infradead.org; cristian.bir...@microchip.com
> >> Subject: Re: [PATCH v3 1/2] mtd: spi-nor: add support to non-uniform
> >> SFDP SPI NOR flash memories
> >>
> >> On Wed, 17 Oct 2018 09:10:45 +0200
> >> Boris Brezillon  wrote:
> >>
> >>> On Wed, 17 Oct 2018 09:07:24 +0200
> >>> Boris Brezillon  wrote:
> >>>
> >>>> On Wed, 17 Oct 2018 02:07:43 +
> >>>> Yogesh Narayan Gaur  wrote:
> >>>>
> >>>>>>
> >>>>> Actually there is no entry of s25fs512s in current spi-nor.c file.
> >>>>> For my connected flash part, jedec ID read points to s25fl512s. I
> >>>>> have asked my board team to confirm the name of exact connected
> >>>>> flash part. When I check the data sheet of s25fs512s, it also
> >>>>> points to the same Jedec ID information. { "s25fl512s",
> >>>>> INFO(0x010220, 0x4d00, 256
> >>>>> * 1024, 256, }
> >>>>>
> >>>>> But as stated earlier, if I skip reading SFDP or read using 1-1-1
> >>>>> protocol then read are always correct. For 1-4-4 protocol read are
> >>>>> wrong and on further debugging found that Read code of 0x6C is
> >>>>> being send as opcode instead of 0xEC.
> >>>>>
> >>>>> If I revert this patch, reads are working fine.
> >>>>
> >>>> Can you try with the following patch?
> >>>>
> >>>
> >>> Hm, nevermind. The problem is actually not related to 4B vs non-4B
> >>> mode but 1-1-4 vs 1-4-4 modes.
> > Yes, that's only I have stated in my first mail that instead of 1-4-4 mode 
> > read
> opcode is being sent for 1-1-4 mode.
> >>>
> >>
> >> Can you try with this patch applied?
> >>
> > With suggested patch, read for protocol 1-4-4 working correctly.
> >
> > [1.625360] m25p80 spi0.0: found s25fl512s, expected m25p80
> > [1.631094] m25p80 spi0.0: failed to parse SMPT (err = -22)
> > [1.636661] 261 8c4c780 opcode(read:eb, pp:2, erase:d8)
> > [1.641878] 266 8c4c780 opcode(read:ec, pp:12, erase:dc)
> > [1.647200] m25p80 spi0.0: s25fl512s (65536 Kbytes)
> >
> > Without this patch, param_headers are getting freed and restoring previous
> erase map i.e. opcode related to 1-1-4 protocol.
> >
> 
> Can you add some prints in spi_nor_parse_smpt() to isolate what's failing? We
> should understand whether it's something wrong in spi_nor_parse_smpt() or the
> s25fs512s smpt table does not respect the standard.
> 

It's returning failure from below point in func spi_nor_get_map_in_use()

/* Find the matching configuration map */
while (SMPT_MAP_ID(smpt[i]) != map_id) {
if (smpt[i] & SMPT_DESC_END) {
printk("%d %s \n", __LINE__, __func__);
goto out;
}
--
Regards
Yogesh Gaur.

> Thanks,
> ta
> 

RE: [PATCH v3 1/2] mtd: spi-nor: add macros related to MICRON flash

[Yogesh Narayan Gaur]

Hi Boris,

> -Original Message-
> From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> Sent: Friday, October 12, 2018 11:38 AM
> To: Yogesh Narayan Gaur 
> Cc: linux-...@lists.infradead.org; linux-...@vger.kernel.org;
> tudor.amba...@microchip.com; marek.va...@gmail.com;
> cyrille.pitc...@wedev4u.fr; computersforpe...@gmail.com;
> frieder.schre...@exceet.de; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH v3 1/2] mtd: spi-nor: add macros related to MICRON flash
> 
> On Fri, 12 Oct 2018 02:23:08 +
> Yogesh Narayan Gaur  wrote:
> 
> > Some MICRON related macros in spi-nor domain were ST.
> > Rename entries related to STMicroelectronics under macro SNOR_MFR_ST.
> >
> > Added entry of MFR Id for Micron flashes, 0x002C.
> >
> > Signed-off-by: Yogesh Gaur 
> > Reviewed-by: Tudor Ambarus 
> > ---
> > Changes for v3:
> > - None
> > Changes for v2:
> > - None
> >
> >  drivers/mtd/spi-nor/spi-nor.c | 9 ++---
> >  include/linux/mtd/cfi.h   | 1 +
> >  include/linux/mtd/spi-nor.h   | 3 ++-
> >  3 files changed, 9 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/mtd/spi-nor/spi-nor.c
> > b/drivers/mtd/spi-nor/spi-nor.c index 9407ca5..b8b494f 100644
> > --- a/drivers/mtd/spi-nor/spi-nor.c
> > +++ b/drivers/mtd/spi-nor/spi-nor.c
> > @@ -284,6 +284,7 @@ static inline int set_4byte(struct spi_nor *nor, const
> struct flash_info *info,
> > u8 cmd;
> >
> > switch (JEDEC_MFR(info)) {
> > +   case SNOR_MFR_ST:
> > case SNOR_MFR_MICRON:
> > /* Some Micron need WREN command; all will accept it */
> > need_wren = true;
> > @@ -1388,7 +1389,7 @@ static int spi_nor_is_locked(struct mtd_info *mtd,
> loff_t ofs, uint64_t len)
> > { "mx66l1g45g",  INFO(0xc2201b, 0, 64 * 1024, 2048, SECT_4K |
> SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> > { "mx66l1g55g",  INFO(0xc2261b, 0, 64 * 1024, 2048,
> > SPI_NOR_QUAD_READ) },
> >
> > -   /* Micron */
> > +   /* Micron <--> ST Micro */
> > { "n25q016a",INFO(0x20bb15, 0, 64 * 1024,   32, SECT_4K |
> SPI_NOR_QUAD_READ) },
> > { "n25q032", INFO(0x20ba16, 0, 64 * 1024,   64,
> SPI_NOR_QUAD_READ) },
> > { "n25q032a",INFO(0x20bb16, 0, 64 * 1024,   64,
> SPI_NOR_QUAD_READ) },
> > @@ -3223,6 +3224,7 @@ static int spi_nor_init_params(struct spi_nor *nor,
> > params->quad_enable = macronix_quad_enable;
> > break;
> >
> > +   case SNOR_MFR_ST:
> > case SNOR_MFR_MICRON:
> > break;
> >
> > @@ -3671,8 +3673,9 @@ int spi_nor_scan(struct spi_nor *nor, const char
> *name,
> > mtd->_resume = spi_nor_resume;
> >
> > /* NOR protection support for STmicro/Micron chips and similar */
> > -   if (JEDEC_MFR(info) == SNOR_MFR_MICRON ||
> > -   info->flags & SPI_NOR_HAS_LOCK) {
> > +   if (JEDEC_MFR(info) == SNOR_MFR_ST ||
> > +   JEDEC_MFR(info) == SNOR_MFR_MICRON ||
> > +   info->flags & SPI_NOR_HAS_LOCK) {
> > nor->flash_lock = stm_lock;
> > nor->flash_unlock = stm_unlock;
> > nor->flash_is_locked = stm_is_locked;
> 
> Are you sure ST and Micron NORs work the same way WRT locking, 4-byte
> addressing mode and Quad enable?

Have checked for the Micron flash, MT35x wrt locking, 4-byte addressing mode.
For Macronix and Spansion flash there is special handling required for quad 
mode but not needed for ST flash.
This flash didn't support quad mode and have checked that other Micron flash 
also didn't need special handling for quad mode.
--
Regards
Yogesh Gaur.
> 
> > diff --git a/include/linux/mtd/cfi.h b/include/linux/mtd/cfi.h index
> > 9b57a9b..cbf7716 100644
> > --- a/include/linux/mtd/cfi.h
> > +++ b/include/linux/mtd/cfi.h
> > @@ -377,6 +377,7 @@ struct cfi_fixup {
> >  #define CFI_MFR_SHARP  0x00B0
> >  #define CFI_MFR_SST0x00BF
> >  #define CFI_MFR_ST 0x0020 /* STMicroelectronics */
> > +#define CFI_MFR_MICRON 0x002C /* Micron */
> >  #define CFI_MFR_TOSHIBA0x0098
> >  #define CFI_MFR_WINBOND0x00DA
> >
> > diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
> > index 7f0c730..8b1acf6 100644
> > --- a/include/linux/mtd/spi-nor.h
> > +++ b/include/linux/mtd/spi-nor.h
> > @@ -23,7 +23,8 @@
> >  #define SNOR_MFR_ATMEL CFI_MFR_ATMEL
> >  #define SNOR_MFR_GIGADEVICE0xc8
> >  #define SNOR_MFR_INTEL CFI_MFR_INTEL
> > -#define SNOR_MFR_MICRONCFI_MFR_ST /* ST Micro <--> Micron
> */
> > +#define SNOR_MFR_STCFI_MFR_ST  /* ST Micro */
> > +#define SNOR_MFR_MICRONCFI_MFR_MICRON  /* Micron */
> >  #define SNOR_MFR_MACRONIX  CFI_MFR_MACRONIX
> >  #define SNOR_MFR_SPANSION  CFI_MFR_AMD
> >  #define SNOR_MFR_SST   CFI_MFR_SST

RE: [PATCH RESEND v4 1/5] spi: spi-mem: Add driver for NXP FlexSPI controller

[Yogesh Narayan Gaur]

Hi,

> -Original Message-
> From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> Sent: Tuesday, October 23, 2018 2:37 PM
> To: Yogesh Narayan Gaur 
> Cc: linux-...@lists.infradead.org; marek.va...@gmail.com;
> broo...@kernel.org; linux-...@vger.kernel.org; devicet...@vger.kernel.org;
> r...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org; linux-arm-
> ker...@lists.infradead.org; computersforpe...@gmail.com;
> frieder.schre...@exceet.de; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH RESEND v4 1/5] spi: spi-mem: Add driver for NXP FlexSPI
> controller
> 
> On Tue, 23 Oct 2018 08:56:46 +
> Yogesh Narayan Gaur  wrote:
> 
> > +struct nxp_fspi {
> > +   void __iomem *iobase;
> > +   void __iomem *ahb_addr;
> > +   u32 memmap_phy;
> > +   u32 memmap_phy_size;
> > +   struct clk *clk, *clk_en;
> > +   struct device *dev;
> > +   struct completion c;
> > +   const struct nxp_fspi_devtype_data *devtype_data;
> > +   struct mutex lock;
> > +   struct pm_qos_request pm_qos_req;
> > +   int selected;
> > +   void (*write)(u32 val, void __iomem *addr);
> > +   u32 (*read)(void __iomem *addr);
> 
> I think I already commented on this aspect, and I keep thinking having a 
> function
> pointer is overkill here.
> Just declare 2 functions and do the f->devtype_data->little_endian check in
> there:
> 
> static u32 fspi_readl(struct nxp_fspi *f, void __iomem *addr) {
>   if (f->devtype_data->little_endian)
>   return ioread32(addr);
> 
>   return ioread32be(addr);
> }
> 
> static void fspi_writel(struct nxp_fspi *f, u32 val, void __iomem *addr) {
>   if (f->devtype_data->little_endian)
>   iowrite32(val, addr);
> 
>   iowrite32be(val, addr);
> }

This, I have kept same as being done in spi-fsl-qspi.c driver file as Frieder 
have got the comment to remove the condition in read/write path and he has 
introduced these hooks there.

Would remove in next version. Please review other changes and complete driver 
file.

--
Regards
Yogesh Gaur

RE: [PATCH v3 1/2] mtd: spi-nor: add macros related to MICRON flash

[Yogesh Narayan Gaur]

Hi,

Did we have have any comments or remarks about this patch-series,  if not 
please apply.

Both patches in the series been reviewed by Tudor.

--
Regards
Yogesh Gaur

> -Original Message-
> From: Yogesh Narayan Gaur
> Sent: Friday, October 12, 2018 12:02 PM
> To: 'Boris Brezillon' 
> Cc: linux-...@lists.infradead.org; linux-...@vger.kernel.org;
> tudor.amba...@microchip.com; marek.va...@gmail.com;
> cyrille.pitc...@wedev4u.fr; computersforpe...@gmail.com;
> frieder.schre...@exceet.de; linux-kernel@vger.kernel.org
> Subject: RE: [PATCH v3 1/2] mtd: spi-nor: add macros related to MICRON flash
> 
> Hi Boris,
> 
> > -Original Message-
> > From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> > Sent: Friday, October 12, 2018 11:38 AM
> > To: Yogesh Narayan Gaur 
> > Cc: linux-...@lists.infradead.org; linux-...@vger.kernel.org;
> > tudor.amba...@microchip.com; marek.va...@gmail.com;
> > cyrille.pitc...@wedev4u.fr; computersforpe...@gmail.com;
> > frieder.schre...@exceet.de; linux-kernel@vger.kernel.org
> > Subject: Re: [PATCH v3 1/2] mtd: spi-nor: add macros related to MICRON
> > flash
> >
> > On Fri, 12 Oct 2018 02:23:08 +
> > Yogesh Narayan Gaur  wrote:
> >
> > > Some MICRON related macros in spi-nor domain were ST.
> > > Rename entries related to STMicroelectronics under macro SNOR_MFR_ST.
> > >
> > > Added entry of MFR Id for Micron flashes, 0x002C.
> > >
> > > Signed-off-by: Yogesh Gaur 
> > > Reviewed-by: Tudor Ambarus 
> > > ---
> > > Changes for v3:
> > > - None
> > > Changes for v2:
> > > - None
> > >
> > >  drivers/mtd/spi-nor/spi-nor.c | 9 ++---
> > >  include/linux/mtd/cfi.h   | 1 +
> > >  include/linux/mtd/spi-nor.h   | 3 ++-
> > >  3 files changed, 9 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/drivers/mtd/spi-nor/spi-nor.c
> > > b/drivers/mtd/spi-nor/spi-nor.c index 9407ca5..b8b494f 100644
> > > --- a/drivers/mtd/spi-nor/spi-nor.c
> > > +++ b/drivers/mtd/spi-nor/spi-nor.c
> > > @@ -284,6 +284,7 @@ static inline int set_4byte(struct spi_nor *nor,
> > > const
> > struct flash_info *info,
> > >   u8 cmd;
> > >
> > >   switch (JEDEC_MFR(info)) {
> > > + case SNOR_MFR_ST:
> > >   case SNOR_MFR_MICRON:
> > >   /* Some Micron need WREN command; all will accept it */
> > >   need_wren = true;
> > > @@ -1388,7 +1389,7 @@ static int spi_nor_is_locked(struct mtd_info
> > > *mtd,
> > loff_t ofs, uint64_t len)
> > >   { "mx66l1g45g",  INFO(0xc2201b, 0, 64 * 1024, 2048, SECT_4K |
> > SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> > >   { "mx66l1g55g",  INFO(0xc2261b, 0, 64 * 1024, 2048,
> > > SPI_NOR_QUAD_READ) },
> > >
> > > - /* Micron */
> > > + /* Micron <--> ST Micro */
> > >   { "n25q016a",INFO(0x20bb15, 0, 64 * 1024,   32, SECT_4K |
> > SPI_NOR_QUAD_READ) },
> > >   { "n25q032", INFO(0x20ba16, 0, 64 * 1024,   64,
> > SPI_NOR_QUAD_READ) },
> > >   { "n25q032a",INFO(0x20bb16, 0, 64 * 1024,   64,
> > SPI_NOR_QUAD_READ) },
> > > @@ -3223,6 +3224,7 @@ static int spi_nor_init_params(struct spi_nor *nor,
> > >   params->quad_enable = macronix_quad_enable;
> > >   break;
> > >
> > > + case SNOR_MFR_ST:
> > >   case SNOR_MFR_MICRON:
> > >   break;
> > >
> > > @@ -3671,8 +3673,9 @@ int spi_nor_scan(struct spi_nor *nor, const
> > > char
> > *name,
> > >   mtd->_resume = spi_nor_resume;
> > >
> > >   /* NOR protection support for STmicro/Micron chips and similar */
> > > - if (JEDEC_MFR(info) == SNOR_MFR_MICRON ||
> > > - info->flags & SPI_NOR_HAS_LOCK) {
> > > + if (JEDEC_MFR(info) == SNOR_MFR_ST ||
> > > + JEDEC_MFR(info) == SNOR_MFR_MICRON ||
> > > + info->flags & SPI_NOR_HAS_LOCK) {
> > >   nor->flash_lock = stm_lock;
> > >   nor->flash_unlock = stm_unlock;
> > >   nor->flash_is_locked = stm_is_locked;
> >
> > Are you sure ST and Micron NORs work the same way WRT locking, 4-byte
> > addressing mode and Quad enable?
> 
> Have checked for the Micron flash, MT35x wrt locking, 4-byte addressing mode.
> For Macronix and Spansion flash there is special handling required for quad
> mode but not n

RE: [PATCH v3 1/2] mtd: spi-nor: add support to non-uniform SFDP SPI NOR flash memories

[Yogesh Narayan Gaur]

Hi, 

> -Original Message-
> From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> Sent: Tuesday, October 23, 2018 2:18 PM
> To: Yogesh Narayan Gaur 
> Cc: cristian.bir...@microchip.com; Tudor Ambarus
> ; rich...@nod.at; Mark Brown
> ; linux-kernel@vger.kernel.org;
> nicolas.fe...@microchip.com; marek.va...@gmail.com;
> cyrille.pitc...@microchip.com; linux-...@lists.infradead.org; Cyrille Pitchen
> ; computersforpe...@gmail.com;
> dw...@infradead.org; linux-arm-ker...@lists.infradead.org
> Subject: Re: [PATCH v3 1/2] mtd: spi-nor: add support to non-uniform SFDP SPI
> NOR flash memories
> 
> On Tue, 23 Oct 2018 08:18:35 +
> Yogesh Narayan Gaur  wrote:
> 
> >
> > I have added the prints in m25p80_read() and in flexspi controller 
> > prepare_lut
> and read_rxfifo() func.
> > In these have added prints for data variable of struct op and data which 
> > being
> read by the controller from the flash.
> >
> > [2.091467] smpt[0]=[addr_width:0003, read_dumy:0008,
> read_opcode:0065, data_mask:0008]
> > [2.099113] m25p80_read, nor[op:0065 addr_width:0003,
> dummy:0008, len:0001
> > [2.107367] m25p80_read, cmd[opcode:65 bwidth:1] aadr[val:4, nbytes:3,
> bwidth:1]
> > [2.114753] m25p80_read, dummy[nbytes:1 bwidth:1] data[bwidth:1,
> nbytes:1]
> > [2.121706] nxp_fspi_prepare_lut cmd[opcode:65 bwidth:1] aadr[val:4,
> nbytes:3, bwidth:1]
> > [2.129786] dummy[nbytes:1 bwidth:1] data[dir:0 bwidth:1, nbytes:1]
> > [2.136132] nxp-fspi 20c.flexspi: CMD[65] lutval[0:8180465
> 1:24003008  2:0 3:0]
> > [2.144223] nxp_fspi_read_rxfifo, ReadData op.buf[0x00]
> > [2.151004] smpt_read[1] addr[0004], data_byte[]
> err:
> >
> >
> > [2.157782] smpt[2]=[addr_width:0003, read_dumy:0008,
> read_opcode:0065, data_mask:0004]
> > [2.165429] m25p80_read, nor[op:0065 addr_width:0003,
> dummy:0008, len:0001
> > [2.173683] m25p80_read, cmd[opcode:65 bwidth:1] aadr[val:2, nbytes:3,
> bwidth:1]
> > [2.181068] m25p80_read, dummy[nbytes:1 bwidth:1] data[bwidth:1,
> nbytes:1]
> > [2.188021] nxp_fspi_prepare_lut cmd[opcode:65 bwidth:1] aadr[val:2,
> nbytes:3, bwidth:1]
> > [2.196101] dummy[nbytes:1 bwidth:1] data[dir:0 bwidth:1, nbytes:1]
> > [2.202447] nxp-fspi 20c.flexspi: CMD[65] lutval[0:8180465
> 1:24003008  2:0 3:0]
> > [2.210539] nxp_fspi_read_rxfifo, ReadData op.buf[0x02]
> > [2.217319] smpt_read[3] addr[0002], data_byte[0002]
> err:
> >
> >
> > [2.224098] smpt[4]=[addr_width:0003, read_dumy:0008,
> read_opcode:0065, data_mask:0002]
> > [2.231744] m25p80_read, nor[op:0065 addr_width:0003,
> dummy:0008, len:0001
> > [2.239998] m25p80_read, cmd[opcode:65 bwidth:1] aadr[val:4, nbytes:3,
> bwidth:1]
> > [2.247383] m25p80_read, dummy[nbytes:1 bwidth:1] data[bwidth:1,
> nbytes:1]
> > [2.254336] nxp_fspi_prepare_lut cmd[opcode:65 bwidth:1] aadr[val:4,
> nbytes:3, bwidth:1]
> > [2.262416] dummy[nbytes:1 bwidth:1] data[dir:0 bwidth:1, nbytes:1]
> > [2.268762] nxp-fspi 20c.flexspi: CMD[65] lutval[0:8180465
> 1:24003008  2:0 3:0]
> > [2.276854] nxp_fspi_read_rxfifo, ReadData op.buf[0x00]
> > [2.283634] smpt_read[5] addr[0004], data_byte[]
> err:
> >
> >
> > [2.290412] spi_nor_get_map_in_use:2915 map_id=0 smpt_len:16 i=:6
> > [2.296496] End [addr_width:0003, read_dumy:0008,
> read_opcode:0065] ReturnVal:
> > [2.305444] spi_nor_parse_smpt:3065
> > [2.308924] m25p80 spi0.0: failed to parse SMPT (err = -22)
> >
> >
> > >
> > > Next thing you can do is read the CR2NV reg (using the RDAR command)
> > > and check the RL (Read Latency) and AL (Address Length) values.
> >
> > Please let me know how to read CR2NV register.
> 
> Actually, RDAR is already what you use to read the map_id, and we need to use
> it to read the register that contains the number of dummy cycles and the 
> number
> of address bytes to use for RDAR operations. Looks like we have a chicken and
> egg situation here :-).
> 
> Let's try something else:
> 
> 1/ create an u8 array of 16 entries named data_bytes
> 
> for each loop iteration (the first for loop):
> 2/ set ->addr_width to 3 and ->read_dummy to 0 3/ call spi_nor_read_raw(nor,
> addr, ARRAY_SIZE(data_bytes), data_bytes) 4/ dump the data_bytes buf 5/ set -
> >addr_width to 4 6/ call spi_nor_read_raw(nor, a

RE: [PATCH v3 1/2] mtd: spi-nor: add support to non-uniform SFDP SPI NOR flash memories

[Yogesh Narayan Gaur]

Hi,

> -Original Message-
> From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> Sent: Tuesday, October 23, 2018 2:31 PM
> To: Yogesh Narayan Gaur 
> Cc: cristian.bir...@microchip.com; Tudor Ambarus
> ; rich...@nod.at; Mark Brown
> ; linux-kernel@vger.kernel.org;
> nicolas.fe...@microchip.com; marek.va...@gmail.com;
> cyrille.pitc...@microchip.com; linux-...@lists.infradead.org; Cyrille Pitchen
> ; computersforpe...@gmail.com;
> dw...@infradead.org; linux-arm-ker...@lists.infradead.org
> Subject: Re: [PATCH v3 1/2] mtd: spi-nor: add support to non-uniform SFDP SPI
> NOR flash memories
> 
> On Tue, 23 Oct 2018 10:48:27 +0200
> Boris Brezillon  wrote:
> 
> > On Tue, 23 Oct 2018 08:18:35 +
> > Yogesh Narayan Gaur  wrote:
> >
> > >
> > > I have added the prints in m25p80_read() and in flexspi controller 
> > > prepare_lut
> and read_rxfifo() func.
> > > In these have added prints for data variable of struct op and data which
> being read by the controller from the flash.
> > >
> > > [2.091467] smpt[0]=[addr_width:0003, read_dumy:0008,
> read_opcode:0065, data_mask:0008]
> > > [2.099113] m25p80_read, nor[op:0065 addr_width:0003,
> dummy:0008, len:0001
> > > [2.107367] m25p80_read, cmd[opcode:65 bwidth:1] aadr[val:4, nbytes:3,
> bwidth:1]
> > > [2.114753] m25p80_read, dummy[nbytes:1 bwidth:1] data[bwidth:1,
> nbytes:1]
> > > [2.121706] nxp_fspi_prepare_lut cmd[opcode:65 bwidth:1] aadr[val:4,
> nbytes:3, bwidth:1]
> > > [2.129786] dummy[nbytes:1 bwidth:1] data[dir:0 bwidth:1, nbytes:1]
> > > [2.136132] nxp-fspi 20c.flexspi: CMD[65] lutval[0:8180465
> 1:24003008  2:0 3:0]
> > > [2.144223] nxp_fspi_read_rxfifo, ReadData op.buf[0x00]
> > > [2.151004] smpt_read[1] addr[0004], data_byte[]
> err:
> > >
> > >
> > > [2.157782] smpt[2]=[addr_width:0003, read_dumy:0008,
> read_opcode:0065, data_mask:0004]
> > > [2.165429] m25p80_read, nor[op:0065 addr_width:0003,
> dummy:0008, len:0001
> > > [2.173683] m25p80_read, cmd[opcode:65 bwidth:1] aadr[val:2, nbytes:3,
> bwidth:1]
> > > [2.181068] m25p80_read, dummy[nbytes:1 bwidth:1] data[bwidth:1,
> nbytes:1]
> > > [2.188021] nxp_fspi_prepare_lut cmd[opcode:65 bwidth:1] aadr[val:2,
> nbytes:3, bwidth:1]
> > > [2.196101] dummy[nbytes:1 bwidth:1] data[dir:0 bwidth:1, nbytes:1]
> > > [2.202447] nxp-fspi 20c.flexspi: CMD[65] lutval[0:8180465
> 1:24003008  2:0 3:0]
> > > [2.210539] nxp_fspi_read_rxfifo, ReadData op.buf[0x02]
> > > [2.217319] smpt_read[3] addr[0002], data_byte[0002]
> err:
> > >
> > >
> > > [2.224098] smpt[4]=[addr_width:0003, read_dumy:0008,
> read_opcode:0065, data_mask:0002]
> > > [2.231744] m25p80_read, nor[op:0065 addr_width:0003,
> dummy:0008, len:0001
> > > [2.239998] m25p80_read, cmd[opcode:65 bwidth:1] aadr[val:4, nbytes:3,
> bwidth:1]
> > > [2.247383] m25p80_read, dummy[nbytes:1 bwidth:1] data[bwidth:1,
> nbytes:1]
> > > [2.254336] nxp_fspi_prepare_lut cmd[opcode:65 bwidth:1] aadr[val:4,
> nbytes:3, bwidth:1]
> > > [2.262416] dummy[nbytes:1 bwidth:1] data[dir:0 bwidth:1, nbytes:1]
> > > [2.268762] nxp-fspi 20c.flexspi: CMD[65] lutval[0:8180465
> 1:24003008  2:0 3:0]
> > > [2.276854] nxp_fspi_read_rxfifo, ReadData op.buf[0x00]
> > > [2.283634] smpt_read[5] addr[0004], data_byte[]
> err:
> > >
> > >
> > > [2.290412] spi_nor_get_map_in_use:2915 map_id=0 smpt_len:16 i=:6
> > > [2.296496] End [addr_width:0003, read_dumy:0008,
> read_opcode:0065] ReturnVal:
> > > [2.305444] spi_nor_parse_smpt:3065
> > > [2.308924] m25p80 spi0.0: failed to parse SMPT (err = -22)
> > >
> > >
> > > >
> > > > Next thing you can do is read the CR2NV reg (using the RDAR command)
> and
> > > > check the RL (Read Latency) and AL (Address Length) values.
> > >
> > > Please let me know how to read CR2NV register.
> >
> > Actually, RDAR is already what you use to read the map_id, and we need
> > to use it to read the register that contains the number of dummy
> > cycles and the number of address bytes to use for RDAR operations.
> > Looks like we have a chicken and egg situation here :-).
> >
> > Let's try something els

RE: [PATCH v3 1/2] mtd: spi-nor: add macros related to MICRON flash

[Yogesh Narayan Gaur]

Hi Boris,

> -Original Message-
> From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> Sent: Tuesday, October 23, 2018 3:27 PM
> To: Yogesh Narayan Gaur 
> Cc: Mark Brown ; Tudor Ambarus
> ; linux-...@lists.infradead.org; linux-
> s...@vger.kernel.org; marek.va...@gmail.com; cyrille.pitc...@wedev4u.fr;
> computersforpe...@gmail.com; frieder.schre...@exceet.de; linux-
> ker...@vger.kernel.org
> Subject: Re: [PATCH v3 1/2] mtd: spi-nor: add macros related to MICRON flash
> 
> Hi Yogesh,
> 
> On Tue, 23 Oct 2018 09:39:25 +
> Yogesh Narayan Gaur  wrote:
> 
> > Hi,
> >
> > Did we have have any comments or remarks about this patch-series,  if not
> please apply.
> 
> Sorry, but it was already too late for this release, and the merge window just
> started, so it will have to wait at least 2 more weeks.
Ok.

> 
> We've been lagging with SPI NOR patches for the last couple releases because I
> clearly don't have time to review those contributions, and it seems Marek does
> not have time either.
> 
> >
> > Both patches in the series been reviewed by Tudor.
> 
> Things are improving a bit thanks to Tudor's involvement in the review 
> process,
> but I'd like to remember you that you, as a regular contributor to the spi-nor
> subsystem, can help us with that too. That is, help review patches coming from
> others instead of only focusing on your own contributions.
> 
Sure, I would start doing the review of other contributor patches.

--
Regards
Yogesh Gaur.

> Regards,
> 
> Boris

[PATCH v3 0/7] spi: add support for octo mode

[Yogesh Narayan Gaur]

Add support for octo mode IO data transfer.
Micron flash, mt35xu512aba, supports octal mode data transfer and
NXP FlexSPI controller supports 8 data lines for data transfer (Rx/Tx).

Patch series
* Add support for octo mode flags and parsing of same in spi driver.
* Add parsing logic for spi-mem framework and m25p80.c device file.
* Add opcodes for octo I/O commands in spi-nor framework, Read and Write proto 
for (1-1-8/1-8-8) mode.
  Opcodes are added as per octal data IO commands required for mt35xu512aba [1] 
flash.
* Add mode bit required for octo mode in nxp-fspi driver [2].
* Define binding property 'spi-rx/tx-bus-width' for LX2160ARDB target [2].

Cherry pick below 2 patches (from: 
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git):
c639f871febe6667d9afce28108c634e5636c735 spi: spi-mem: Fix inverted logic 
in op sanity check
db122eb8a749a1eff038f9a282c620ab16c4be1d spi: spi-mem: Add extra sanity 
checks on the op param

Tested on LX2160ARDB target with nxp-fspi driver, below are
Read performance number of 1-1-1 and 1-1-8 read protocol.

 root@lxxx:~# cat /proc/mtd
 dev:size   erasesize  name
 mtd0: 0400 1000 "spi0.0"
 mtd1: 0400 1000 "spi0.1"
 root@lxxx:~# time mtd_debug read /dev/mtd0 0x0 0x100 0read
 Copied 16777216 bytes from address 0x in flash to 0read

 real0m2.792s
 user0m0.000s
 sys 0m2.790s
 root@lxxx:~# time mtd_debug read /dev/mtd1 0x0 0x100 0read
 Copied 16777216 bytes from address 0x in flash to 0read

 real0m0.441s
 user0m0.000s
 sys 0m0.440s
 root@ls1012ardb:~#

 Flash device MTD0 configured in 1-1-1 protocol.
 Flash device MTD1 configured in 1-1-8 protocol.

[1] https://patchwork.ozlabs.org/project/linux-mtd/list/?series=70384
[2] https://patchwork.ozlabs.org/project/linux-mtd/list/?series=72181

Yogesh Gaur (7):
  spi: add support for octo mode I/O data transfer
  spi: spi-mem: add support for octo mode I/O data transfer
  mtd: spi-nor: add opcodes for octo Read/Write commands
  mtd: spi-nor: add octo read flag for flash mt35xu512aba
  mtd: m25p80: add support of octo mode I/O transfer
  spi: nxp-fspi: add octo mode flag bit for octal support
  arm64: dts: lx2160a: update fspi node

Changes for v3:
- Add octo mode support in spi_setup().
- Rename all patches with 'octal' string modified as 'octo'.
Changes for v2:
- Incorporated review comments of Boris and Vignesh.

 arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts |  4 
 drivers/mtd/devices/m25p80.c  |  9 -
 drivers/mtd/spi-nor/spi-nor.c | 15 ++-
 drivers/spi/spi-mem.c |  9 -
 drivers/spi/spi-nxp-fspi.c|  4 ++--
 drivers/spi/spi.c | 12 ++--
 include/linux/mtd/spi-nor.h   |  8 
 include/linux/spi/spi.h   |  2 ++
 8 files changed, 56 insertions(+), 7 deletions(-)

-- 
2.7.4

[PATCH v3 6/7] spi: nxp-fspi: add octo mode flag bit for octal support

[Yogesh Narayan Gaur]

Add octo mode flags for octal I/O data transfer support.
NXP FlexSPI controller supports 8 lines Rx/Tx data transfer.

Signed-off-by: Yogesh Gaur 
---
Changes for v3:
- Modified string 'octal' with 'octo'.
Changes for v2:
- None

 drivers/spi/spi-nxp-fspi.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c
index 67eea88..332b730 100644
--- a/drivers/spi/spi-nxp-fspi.c
+++ b/drivers/spi/spi-nxp-fspi.c
@@ -993,8 +993,8 @@ static int nxp_fspi_probe(struct platform_device *pdev)
if (!ctlr)
return -ENOMEM;
 
-   ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD |
- SPI_TX_DUAL | SPI_TX_QUAD;
+   ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_RX_OCTO |
+ SPI_TX_DUAL | SPI_TX_QUAD | SPI_TX_OCTO;
 
f = spi_controller_get_devdata(ctlr);
f->dev = dev;
-- 
2.7.4

[PATCH v3 7/7] arm64: dts: lx2160a: update fspi node

[Yogesh Narayan Gaur]

Flash mt35xu512aba connected to FlexSPI controller supports
1-1-8/1-8-8 protocol.
Added flag spi-rx-bus-width and spi-tx-bus-width with values as
8 and 8 respectively for both flashes connected at CS0 and CS1.

Signed-off-by: Yogesh Gaur 
---
Changes for v3:
- None
Changes for v2:
- None

 arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts 
b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
index 3b20c97..24cc41c 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -45,6 +45,8 @@
m25p,fast-read;
spi-max-frequency = <2000>;
reg = <0>;
+   spi-rx-bus-width = <8>;
+   spi-tx-bus-width = <8>;
};
 
mt35xu512aba1: flash@1 {
@@ -54,6 +56,8 @@
m25p,fast-read;
spi-max-frequency = <2000>;
reg = <1>;
+   spi-rx-bus-width = <8>;
+   spi-tx-bus-width = <8>;
};
 };
 
-- 
2.7.4

[PATCH RESEND v4 2/5] dt-bindings: spi: add binding file for NXP FlexSPI controller

[Yogesh Narayan Gaur]

Add binding file for NXP FlexSPI controller

Signed-off-by: Yogesh Gaur 
Reviewed-by: Rob Herring 
---
Changes for v4:
- Incorporated Rob review comments.
Changes for v3:
- Removed node property 'big-endian'.
Changes for v2:
- Incorporated Rob review comments.

 .../devicetree/bindings/spi/spi-nxp-fspi.txt   | 39 ++
 1 file changed, 39 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/spi/spi-nxp-fspi.txt

diff --git a/Documentation/devicetree/bindings/spi/spi-nxp-fspi.txt 
b/Documentation/devicetree/bindings/spi/spi-nxp-fspi.txt
new file mode 100644
index 000..2cd67eb
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/spi-nxp-fspi.txt
@@ -0,0 +1,39 @@
+* NXP Flex Serial Peripheral Interface (FSPI)
+
+Required properties:
+  - compatible : Should be "nxp,lx2160a-fspi"
+  - reg :First contains the register location and length,
+ Second contains the memory mapping address and length
+  - reg-names :  Should contain the resource reg names:
+- fspi_base: configuration register address space
+ - fspi_mmap: memory mapped address space
+  - interrupts : Should contain the interrupt for the device
+
+Required SPI slave node properties:
+  - reg :There are two buses (A and B) with two chip selects each.
+ This encodes to which bus and CS the flash is connected:
+ - <0>: Bus A, CS 0
+ - <1>: Bus A, CS 1
+ - <2>: Bus B, CS 0
+ - <3>: Bus B, CS 1
+
+Example showing the usage of two SPI NOR slave devices on bus A:
+
+fspi0: spi@20c {
+   compatible = "nxp,lx2160a-fspi";
+   reg = <0x0 0x20c 0x0 0x1>, <0x0 0x2000 0x0 0x1000>;
+   reg-names = "fspi_base", "fspi_mmap";
+   interrupts = <0 25 0x4>; /* Level high type */
+   clocks = < 4 3>, < 4 3>;
+   clock-names = "fspi_en", "fspi";
+
+   mt35xu512aba0: flash@0 {
+   reg = <0>;
+   
+   };
+
+   mt35xu512aba1: flash@1 {
+   reg = <1>;
+   
+   };
+};
-- 
2.7.4

[PATCH RESEND v4 3/5] arm64: dts: lx2160a: add FlexSPI node property

[Yogesh Narayan Gaur]

Add fspi node property for LX2160A SoC for FlexSPI driver.
Property added for the FlexSPI controller and for the connected
slave device for the LX2160ARDB target.
This is having two SPI-NOR flash device, mt35xu512aba, connected
at CS0 and CS1.

Signed-off-by: Yogesh Gaur 
---
Changes for v4:
- Incorporated Rob review comments.
Changes for v3:
- None.
Changes for v2:
- - Incorporated Shawn review comments.

 arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 22 ++
 arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi| 12 
 2 files changed, 34 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts 
b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
index 70fad20..901ca346 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -32,6 +32,28 @@
status = "okay";
 };
 
+ {
+   status = "okay";
+
+   mt35xu512aba0: flash@0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "spansion,m25p80";
+   m25p,fast-read;
+   spi-max-frequency = <2000>;
+   reg = <0>;
+   };
+
+   mt35xu512aba1: flash@1 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "spansion,m25p80";
+   m25p,fast-read;
+   spi-max-frequency = <2000>;
+   reg = <1>;
+   };
+};
+
  {
status = "okay";
pca9547@77 {
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index e35e494..ba2a247 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -568,5 +568,17 @@
timeout-sec = <30>;
};
 
+   fspi: spi@20c {
+   compatible = "nxp,lx2160a-fspi";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0x0 0x20c 0x0 0x1>,
+   <0x0 0x2000 0x0 0x1000>;
+   reg-names = "fspi_base", "fspi_mmap";
+   interrupts = <0 25 0x4>; /* Level high type */
+   clocks = < 4 3>, < 4 3>;
+   clock-names = "fspi_en", "fspi";
+   status = "disabled";
+   };
};
 };
-- 
2.7.4

[PATCH RESEND v4 0/5] spi: spi-mem: Add driver for NXP FlexSPI controller

[Yogesh Narayan Gaur]

- Add driver for NXP FlexSPI host controller

 FlexSPI is a flexsible SPI host controller [1], Chapter 30 page 1475,
 which supports two SPI channels and up to 4 external devices.
 Each channel supports Single/Dual/Quad/Octal mode data transfer (1/2/4/8 
bidirectional data lines)
 i.e. FlexSPI acts as an interface to external devices, maximum 4, each with up 
to 8
 bidirectional data lines.

- Tested this driver with mtd_debug(Erase/Write/Read) utility and JFFS2
 filesystem mounting and booting on NXP LX2160ARDB[2] and LX2160AQDS targets.
 LX2160ARDB is having two NOR slave device connected on single bus A
 i.e. A0 and A1 (CS0 and CS1).
 LX2160AQDS is having two NOR slave device connected on separate buses
 one flash on A0 and second on B1 i.e. (CS0 and CS3).
 Verified this driver on following SPI NOR flashes:
   Micron, mt35xu512aba[3], [Read - 1 bit mode]
   Cypress, s25fl512s, [Read - 1/2/4 bit mode]

[1] https://www.nxp.com/docs/en/reference-manual/IMXRT1050RM.pdf
[2] https://patchwork.kernel.org/project/linux-arm-kernel/list/?series=26689
[3] https://patchwork.ozlabs.org/project/linux-mtd/list/?series=70179

Yogesh Gaur (5):
  spi: spi-mem: Add driver for NXP FlexSPI controller
  dt-bindings: spi: add binding file for NXP FlexSPI controller
  arm64: dts: lx2160a: add FlexSPI node property
  arm64: defconfig: enable NXP FlexSPI driver
  MAINTAINERS: add maintainers for the NXP FlexSPI driver

Added Mark Brown as reviewer in to list, thus sending patches again.

Changes for v4:
- Incorporated review comments for
  patch 'spi: spi-mem: Add driver for NXP FlexSPI controller'.
- Incorporated binding file review comments.
Changes for v3:
- Incorporated review comments for
  patch 'spi: spi-mem: Add driver for NXP FlexSPI controller'.
Changes for v2:
- Incorporated Boris review comments and drop below patches as per the comments.
 - Patch 'spi: add slave device size in spi_device struct'
 - Patch 'spi: add flags for octal I/O data transfer'
- Incorporated DTS and Binding file review comments of Shawn Guo and Rob 
Herring.

 .../devicetree/bindings/spi/spi-nxp-fspi.txt   |   39 +
 MAINTAINERS|6 +
 arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts  |   22 +
 arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi |   12 +
 arch/arm64/configs/defconfig   |1 +
 drivers/spi/Kconfig|   10 +
 drivers/spi/Makefile   |1 +
 drivers/spi/spi-nxp-fspi.c | 1158 
 8 files changed, 1249 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/spi/spi-nxp-fspi.txt
 create mode 100644 drivers/spi/spi-nxp-fspi.c

-- 
2.7.4

[PATCH RESEND v4 4/5] arm64: defconfig: enable NXP FlexSPI driver

[Yogesh Narayan Gaur]

Enable driver support of NXP FlexSPI controller.

Signed-off-by: Yogesh Gaur 
---
Changes for v4:
- None
Changes for v3:
- None
Changes for v2:
- None

 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 3cfa8ca..75ceddf 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -335,6 +335,7 @@ CONFIG_SPI_QUP=y
 CONFIG_SPI_ROCKCHIP=y
 CONFIG_SPI_S3C64XX=y
 CONFIG_SPI_SPIDEV=m
+CONFIG_SPI_NXP_FLEXSPI=y
 CONFIG_SPMI=y
 CONFIG_PINCTRL_IPQ8074=y
 CONFIG_PINCTRL_SINGLE=y
-- 
2.7.4

[PATCH v3 2/7] spi: spi-mem: add support for octo mode I/O data transfer

[Yogesh Narayan Gaur]

Add support for octo mode I/O data transfer in spi-mem framework.

Signed-off-by: Yogesh Gaur 
---
Changes for v3:
- Modified string 'octal' with 'octo'.
Changes for v2:
- Patch added in v2 version.

 drivers/spi/spi-mem.c | 9 -
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index c6bdea7..2379efc 100644
--- a/drivers/spi/spi-mem.c
+++ b/drivers/spi/spi-mem.c
@@ -12,7 +12,7 @@
 
 #include "internals.h"
 
-#define SPI_MEM_MAX_BUSWIDTH   4
+#define SPI_MEM_MAX_BUSWIDTH   8
 
 /**
  * spi_controller_dma_map_mem_op_data() - DMA-map the buffer attached to a
@@ -121,6 +121,13 @@ static int spi_check_buswidth_req(struct spi_mem *mem, u8 
buswidth, bool tx)
 
break;
 
+   case 8:
+   if ((tx && (mode & SPI_TX_OCTO)) ||
+   (!tx && (mode & SPI_RX_OCTO)))
+   return 0;
+
+   break;
+
default:
break;
}
-- 
2.7.4

[PATCH v3 1/7] spi: add support for octo mode I/O data transfer

[Yogesh Narayan Gaur]

Add flags for Octo mode I/O data transfer
Required for the SPI controller which can do the data transfer (TX/RX)
on 8 data lines e.g. NXP FlexSPI controller.
 SPI_TX_OCTO: transmit with 8 wires
 SPI_RX_OCTO: receive with 8 wires

Signed-off-by: Yogesh Gaur 
---
Changes for v3:
- Modified string 'octal' with 'octo'.
- Add octo mode support in spi_setup().
Changes for v2:
- Incorporated review comments of Boris.

 drivers/spi/spi.c   | 12 ++--
 include/linux/spi/spi.h |  2 ++
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index ec395a6..6d57fa7 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -1573,6 +1573,9 @@ static int of_spi_parse_dt(struct spi_controller *ctlr, 
struct spi_device *spi,
case 4:
spi->mode |= SPI_TX_QUAD;
break;
+   case 8:
+   spi->mode |= SPI_TX_OCTO;
+   break;
default:
dev_warn(>dev,
"spi-tx-bus-width %d not supported\n",
@@ -1591,6 +1594,9 @@ static int of_spi_parse_dt(struct spi_controller *ctlr, 
struct spi_device *spi,
case 4:
spi->mode |= SPI_RX_QUAD;
break;
+   case 8:
+   spi->mode |= SPI_RX_OCTO;
+   break;
default:
dev_warn(>dev,
"spi-rx-bus-width %d not supported\n",
@@ -2770,14 +2776,16 @@ int spi_setup(struct spi_device *spi)
/* if it is SPI_3WIRE mode, DUAL and QUAD should be forbidden
 */
if ((spi->mode & SPI_3WIRE) && (spi->mode &
-   (SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD)))
+   (SPI_TX_DUAL | SPI_TX_QUAD | SPI_TX_OCTO |
+SPI_RX_DUAL | SPI_RX_QUAD | SPI_RX_OCTO)))
return -EINVAL;
/* help drivers fail *cleanly* when they need options
 * that aren't supported with their current controller
 */
bad_bits = spi->mode & ~spi->controller->mode_bits;
ugly_bits = bad_bits &
-   (SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD);
+   (SPI_TX_DUAL | SPI_TX_QUAD | SPI_TX_OCTO |
+SPI_RX_DUAL | SPI_RX_QUAD | SPI_RX_OCTO);
if (ugly_bits) {
dev_warn(>dev,
 "setup: ignoring unsupported mode bits %x\n",
diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index a64235e..cea4e49 100644
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -163,6 +163,8 @@ struct spi_device {
 #defineSPI_TX_QUAD 0x200   /* transmit with 4 
wires */
 #defineSPI_RX_DUAL 0x400   /* receive with 2 wires 
*/
 #defineSPI_RX_QUAD 0x800   /* receive with 4 wires 
*/
+#defineSPI_TX_OCTO 0x1000  /* transmit with 8 
wires */
+#defineSPI_RX_OCTO 0x2000  /* receive with 8 wires 
*/
int irq;
void*controller_state;
void*controller_data;
-- 
2.7.4

[PATCH v3 3/7] mtd: spi-nor: add opcodes for octo Read/Write commands

[Yogesh Narayan Gaur]

- Add opcodes for octo I/O commands
  * Read  : 1-1-8 and 1-8-8 protocol
  * Write : 1-1-8 and 1-8-8 protocol
  * opcodes for 4-byte address mode command

- Entry of macros in _convert_3to4_xxx function

- Add flag specifying flash support octo read commands.

Signed-off-by: Vignesh R 
Signed-off-by: Yogesh Gaur 
---
Changes for v3:
- Modified string 'octal' with 'octo'.
Changes for v2:
- Incorporated review comments of Boris and Vignesh

 drivers/mtd/spi-nor/spi-nor.c | 12 
 include/linux/mtd/spi-nor.h   |  8 
 2 files changed, 20 insertions(+)

diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 0b8a6e0..120c3bc 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -90,6 +90,7 @@ struct flash_info {
 #define NO_CHIP_ERASE  BIT(12) /* Chip does not support chip erase */
 #define SPI_NOR_SKIP_SFDP  BIT(13) /* Skip parsing of SFDP tables */
 #define USE_CLSR   BIT(14) /* use CLSR command */
+#define SPI_NOR_OCTO_READ  BIT(15) /* Flash supports Octal Read */
 
int (*quad_enable)(struct spi_nor *nor);
 };
@@ -209,6 +210,8 @@ static inline u8 spi_nor_convert_3to4_read(u8 opcode)
{ SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B },
{ SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },
{ SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },
+   { SPINOR_OP_READ_1_1_8, SPINOR_OP_READ_1_1_8_4B },
+   { SPINOR_OP_READ_1_8_8, SPINOR_OP_READ_1_8_8_4B },
 
{ SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B },
{ SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B },
@@ -225,6 +228,8 @@ static inline u8 spi_nor_convert_3to4_program(u8 opcode)
{ SPINOR_OP_PP, SPINOR_OP_PP_4B },
{ SPINOR_OP_PP_1_1_4,   SPINOR_OP_PP_1_1_4_4B },
{ SPINOR_OP_PP_1_4_4,   SPINOR_OP_PP_1_4_4_4B },
+   { SPINOR_OP_PP_1_1_8,   SPINOR_OP_PP_1_1_8_4B },
+   { SPINOR_OP_PP_1_8_8,   SPINOR_OP_PP_1_8_8_4B },
};
 
return spi_nor_convert_opcode(opcode, spi_nor_3to4_program,
@@ -3195,6 +3200,13 @@ static int spi_nor_init_params(struct spi_nor *nor,
  SNOR_PROTO_1_1_4);
}
 
+   if (info->flags & SPI_NOR_OCTO_READ) {
+   params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
+   spi_nor_set_read_settings(>reads[SNOR_CMD_READ_1_1_8],
+ 0, 8, SPINOR_OP_READ_1_1_8,
+ SNOR_PROTO_1_1_8);
+   }
+
/* Page Program settings. */
params->hwcaps.mask |= SNOR_HWCAPS_PP;
spi_nor_set_pp_settings(>page_programs[SNOR_CMD_PP],
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index 8b1acf6..019f534 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -50,9 +50,13 @@
 #define SPINOR_OP_READ_1_2_2   0xbb/* Read data bytes (Dual I/O SPI) */
 #define SPINOR_OP_READ_1_1_4   0x6b/* Read data bytes (Quad Output SPI) */
 #define SPINOR_OP_READ_1_4_4   0xeb/* Read data bytes (Quad I/O SPI) */
+#define SPINOR_OP_READ_1_1_8   0x8b/* Read data bytes (Octal Output SPI) */
+#define SPINOR_OP_READ_1_8_8   0xcb/* Read data bytes (Octal I/O SPI) */
 #define SPINOR_OP_PP   0x02/* Page program (up to 256 bytes) */
 #define SPINOR_OP_PP_1_1_4 0x32/* Quad page program */
 #define SPINOR_OP_PP_1_4_4 0x38/* Quad page program */
+#define SPINOR_OP_PP_1_1_8 0x82/* Octal page program */
+#define SPINOR_OP_PP_1_8_8 0xc2/* Octal page program */
 #define SPINOR_OP_BE_4K0x20/* Erase 4KiB block */
 #define SPINOR_OP_BE_4K_PMC0xd7/* Erase 4KiB block on PMC chips */
 #define SPINOR_OP_BE_32K   0x52/* Erase 32KiB block */
@@ -73,9 +77,13 @@
 #define SPINOR_OP_READ_1_2_2_4B0xbc/* Read data bytes (Dual I/O 
SPI) */
 #define SPINOR_OP_READ_1_1_4_4B0x6c/* Read data bytes (Quad Output 
SPI) */
 #define SPINOR_OP_READ_1_4_4_4B0xec/* Read data bytes (Quad I/O 
SPI) */
+#define SPINOR_OP_READ_1_1_8_4B0x7c/* Read data bytes (Octal 
Output SPI) */
+#define SPINOR_OP_READ_1_8_8_4B0xcc/* Read data bytes (Octal I/O 
SPI) */
 #define SPINOR_OP_PP_4B0x12/* Page program (up to 256 
bytes) */
 #define SPINOR_OP_PP_1_1_4_4B  0x34/* Quad page program */
 #define SPINOR_OP_PP_1_4_4_4B  0x3e/* Quad page program */
+#define SPINOR_OP_PP_1_1_8_4B  0x84/* Octal page program */
+#define SPINOR_OP_PP_1_8_8_4B  0x8e/* Octal page program */
 #define SPINOR_OP_BE_4K_4B 0x21/* Erase 4KiB block */
 #define SPINOR_OP_BE_32K_4B0x5c/* Erase 32KiB block */
 #define SPINOR_OP_SE_4B0xdc/* Sector erase (usually 64KiB) 
*/
-- 
2.7.4

[PATCH v3 4/7] mtd: spi-nor: add octo read flag for flash mt35xu512aba

[Yogesh Narayan Gaur]

Add octo read flag for flash mt35xu512aba.
This flash, mt35xu512aba, is only complaint to SFDP JESD216B and does
not seem to support newer JESD216C standard that provides auto
detection of Octal mode capabilities and opcodes. Therefore, this
capability is manually added using new SPI_NOR_OCTO_READ flag.

Signed-off-by: Vignesh R 
Signed-off-by: Yogesh Gaur 
---
Changes for v3:
- Modified string 'octal' with 'octo'.
Changes for v2:
- Incorporated review comments of Boris and Vignesh

 drivers/mtd/spi-nor/spi-nor.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 120c3bc..a04f579 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -1413,7 +1413,8 @@ static const struct flash_info spi_nor_ids[] = {
/* Micron */
{
"mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512,
-   SECT_4K | USE_FSR | SPI_NOR_4B_OPCODES)
+   SECT_4K | USE_FSR | SPI_NOR_OCTO_READ |
+   SPI_NOR_4B_OPCODES)
},
 
/* PMC */
-- 
2.7.4

[PATCH v3 5/7] mtd: m25p80: add support of octo mode I/O transfer

[Yogesh Narayan Gaur]

Add support for octo mode I/O data transfer based on the controller (spi)
mode.
Assign hw-capability mask bits for octo transfer.

Signed-off-by: Yogesh Gaur 
---
Changes for v3:
- Modified string 'octal' with 'octo'.
Changes for v2:
- Incorporated review comments of Boris.

 drivers/mtd/devices/m25p80.c | 9 -
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
index cb14cf9..7d5c3a1 100644
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -175,7 +175,14 @@ static int m25p_probe(struct spi_mem *spimem)
spi_mem_set_drvdata(spimem, flash);
flash->spimem = spimem;
 
-   if (spi->mode & SPI_RX_QUAD) {
+   if (spi->mode & SPI_RX_OCTO) {
+   hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
+
+   if (spi->mode & SPI_TX_OCTO)
+   hwcaps.mask |= (SNOR_HWCAPS_READ_1_8_8 |
+   SNOR_HWCAPS_PP_1_1_8 |
+   SNOR_HWCAPS_PP_1_8_8);
+   } else if (spi->mode & SPI_RX_QUAD) {
hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
 
if (spi->mode & SPI_TX_QUAD)
-- 
2.7.4

[PATCH RESEND v4 5/5] MAINTAINERS: add maintainers for the NXP FlexSPI driver

[Yogesh Narayan Gaur]

Add maintainers for the NXP FlexSPI driver

Signed-off-by: Yogesh Gaur 
---
Changes for v4:
- None
Changes for v3:
- None
Changes for v2:
- None

 MAINTAINERS | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 9d5eeff..2696898 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -10228,6 +10228,12 @@ L: linux-...@lists.01.org (moderated for 
non-subscribers)
 S: Supported
 F: drivers/nfc/nxp-nci
 
+NXP FSPI DRIVER
+M: Yogesh Gaur 
+L: linux-...@vger.kernel.org
+S: Maintained
+F: drivers/spi/spi-nxp-fspi.c
+
 OBJTOOL
 M: Josh Poimboeuf 
 M: Peter Zijlstra 
-- 
2.7.4

[PATCH RESEND v4 1/5] spi: spi-mem: Add driver for NXP FlexSPI controller

[Yogesh Narayan Gaur]

- Add driver for NXP FlexSPI host controller

(0) What is the FlexSPI controller?
 FlexSPI is a flexsible SPI host controller which supports two SPI
 channels and up to 4 external devices. Each channel supports
 Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional
 data lines) i.e. FlexSPI acts as an interface to external devices,
 maximum 4, each with up to 8 bidirectional data lines.

 It uses new SPI memory interface of the SPI framework to issue
 flash memory operations to up to four connected flash
 devices (2 buses with 2 CS each).

(1) Tested this driver with the mtd_debug and JFFS2 filesystem utility
 on NXP LX2160ARDB and LX2160AQDS targets.
 LX2160ARDB is having two NOR slave device connected on single bus A
 i.e. A0 and A1 (CS0 and CS1).
 LX2160AQDS is having two NOR slave device connected on separate buses
 one flash on A0 and second on B1 i.e. (CS0 and CS3).
 Verified this driver on following SPI NOR flashes:
Micron, mt35xu512ab, [Read - 1 bit mode]
Cypress, s25fl512s, [Read - 1/2/4 bit mode]

Signed-off-by: Yogesh Gaur 
---
Changes for v4:
- Incorporate Boris review comments
  * Use readl_poll_timeout() instead of busy looping.
  * Re-define register masking as per comment.
  * Drop fspi_devtype enum.
Changes for v3:
- Added endianness flag in platform specific structure instead of DTS.
- Modified nxp_fspi_read_ahb(), removed remapping code.
- Added Boris and Frieder as Author and provided reference of spi-fsl-qspi.c
Changes for v2:
- Incorporated Boris review comments.
- Remove dependency of driver over connected flash device size.
- Modified the logic to select requested CS.
- Remove SPI-Octal Macros.

 drivers/spi/Kconfig|   10 +
 drivers/spi/Makefile   |1 +
 drivers/spi/spi-nxp-fspi.c | 1158 
 3 files changed, 1169 insertions(+)
 create mode 100644 drivers/spi/spi-nxp-fspi.c

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index ad5d68e..68da874 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -251,6 +251,16 @@ config SPI_FSL_LPSPI
help
  This enables Freescale i.MX LPSPI controllers in master mode.
 
+config SPI_NXP_FLEXSPI
+   tristate "NXP Flex SPI controller"
+   depends on ARCH_LAYERSCAPE || HAS_IOMEM
+   help
+ This enables support for the Flex SPI controller in master mode.
+ Up to four slave devices can be connected on two buses with two
+ chipselects each.
+ This controller does not support generic SPI messages and only
+ supports the high-level SPI memory interface.
+
 config SPI_GPIO
tristate "GPIO-based bitbanging SPI Master"
depends on GPIOLIB || COMPILE_TEST
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index cb1f437..52c9f18 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -59,6 +59,7 @@ obj-$(CONFIG_SPI_MPC52xx) += spi-mpc52xx.o
 obj-$(CONFIG_SPI_MT65XX)+= spi-mt65xx.o
 obj-$(CONFIG_SPI_MXS)  += spi-mxs.o
 obj-$(CONFIG_SPI_NUC900)   += spi-nuc900.o
+obj-$(CONFIG_SPI_NXP_FLEXSPI)  += spi-nxp-fspi.o
 obj-$(CONFIG_SPI_OC_TINY)  += spi-oc-tiny.o
 spi-octeon-objs:= spi-cavium.o 
spi-cavium-octeon.o
 obj-$(CONFIG_SPI_OCTEON)   += spi-octeon.o
diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c
new file mode 100644
index 000..e5188b2
--- /dev/null
+++ b/drivers/spi/spi-nxp-fspi.c
@@ -0,0 +1,1158 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * NXP FlexSPI(FSPI) controller driver.
+ *
+ * Copyright 2018 NXP.
+ *
+ * FlexSPI is a flexsible SPI host controller which supports two SPI
+ * channels and up to 4 external devices. Each channel supports
+ * Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional
+ * data lines).
+ *
+ * FlexSPI controller is driven by the LUT(Look-up Table) registers
+ * LUT registers are a look-up-table for sequences of instructions.
+ * A valid sequence consists of four LUT registers.
+ * Maximum 32 LUT sequences can be programmed simultaneously.
+ *
+ * LUTs are being created at run-time based on the commands passed
+ * from the spi-mem framework, thus using single LUT index.
+ *
+ * Software triggered Flash read/write access by IP Bus.
+ *
+ * Memory mapped read access by AHB Bus.
+ *
+ * Based on SPI MEM interface and spi-fsl-qspi.c driver.
+ *
+ * Author:
+ * Yogesh Gaur 
+ * Boris Brezillion 
+ * Frieder Schrempf 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+/*
+ * The driver only uses one single LUT entry, that is updated on
+ * each call of exec_op(). Index 0 is preset at boot with a basic
+ * read operation, so let's use the last entry (31).
+ */
+#defineSEQID_LUT   

RE: [PATCH v3 1/2] mtd: spi-nor: add support to non-uniform SFDP SPI NOR flash memories

[Yogesh Narayan Gaur]

Hi,

> -Original Message-
> From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> Sent: Tuesday, October 23, 2018 2:40 PM
> To: Yogesh Narayan Gaur 
> Cc: cristian.bir...@microchip.com; Tudor Ambarus
> ; rich...@nod.at; Mark Brown
> ; linux-kernel@vger.kernel.org;
> nicolas.fe...@microchip.com; marek.va...@gmail.com;
> cyrille.pitc...@microchip.com; linux-...@lists.infradead.org; Cyrille Pitchen
> ; computersforpe...@gmail.com;
> dw...@infradead.org; linux-arm-ker...@lists.infradead.org
> Subject: Re: [PATCH v3 1/2] mtd: spi-nor: add support to non-uniform SFDP SPI
> NOR flash memories
> 
> On Tue, 23 Oct 2018 09:05:23 +
> Yogesh Narayan Gaur  wrote:
> 
> > Hi,
> >
> > > -Original Message-
> > > From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> > > Sent: Tuesday, October 23, 2018 2:31 PM
> > > To: Yogesh Narayan Gaur 
> > > Cc: cristian.bir...@microchip.com; Tudor Ambarus
> > > ; rich...@nod.at; Mark Brown
> > > ; linux-kernel@vger.kernel.org;
> > > nicolas.fe...@microchip.com; marek.va...@gmail.com;
> > > cyrille.pitc...@microchip.com; linux-...@lists.infradead.org;
> > > Cyrille Pitchen ;
> > > computersforpe...@gmail.com; dw...@infradead.org;
> > > linux-arm-ker...@lists.infradead.org
> > > Subject: Re: [PATCH v3 1/2] mtd: spi-nor: add support to non-uniform
> > > SFDP SPI NOR flash memories
> > >
> > > On Tue, 23 Oct 2018 10:48:27 +0200
> > > Boris Brezillon  wrote:
> > >
> > > > On Tue, 23 Oct 2018 08:18:35 + Yogesh Narayan Gaur
> > > >  wrote:
> > > >
> > > > >
> > > > > I have added the prints in m25p80_read() and in flexspi
> > > > > controller prepare_lut
> > > and read_rxfifo() func.
> > > > > In these have added prints for data variable of struct op and
> > > > > data which
> > > being read by the controller from the flash.
> > > > >
> > > > > [2.091467] smpt[0]=[addr_width:0003, read_dumy:0008,
> > > read_opcode:0065, data_mask:0008]
> > > > > [2.099113] m25p80_read, nor[op:0065 addr_width:0003,
> > > dummy:0008, len:0001
> > > > > [2.107367] m25p80_read, cmd[opcode:65 bwidth:1] aadr[val:4,
> nbytes:3,
> > > bwidth:1]
> > > > > [2.114753] m25p80_read, dummy[nbytes:1 bwidth:1] data[bwidth:1,
> > > nbytes:1]
> > > > > [2.121706] nxp_fspi_prepare_lut cmd[opcode:65 bwidth:1] 
> > > > > aadr[val:4,
> > > nbytes:3, bwidth:1]
> > > > > [2.129786] dummy[nbytes:1 bwidth:1] data[dir:0 bwidth:1, nbytes:1]
> > > > > [2.136132] nxp-fspi 20c.flexspi: CMD[65] lutval[0:8180465
> > > 1:24003008  2:0 3:0]
> > > > > [2.144223] nxp_fspi_read_rxfifo, ReadData op.buf[0x00]
> > > > > [2.151004] smpt_read[1] addr[0004], data_byte[]
> > > err:
> > > > >
> > > > >
> > > > > [2.157782] smpt[2]=[addr_width:0003, read_dumy:0008,
> > > read_opcode:0065, data_mask:0004]
> > > > > [2.165429] m25p80_read, nor[op:0065 addr_width:0003,
> > > dummy:0008, len:0001
> > > > > [2.173683] m25p80_read, cmd[opcode:65 bwidth:1] aadr[val:2,
> nbytes:3,
> > > bwidth:1]
> > > > > [2.181068] m25p80_read, dummy[nbytes:1 bwidth:1] data[bwidth:1,
> > > nbytes:1]
> > > > > [2.188021] nxp_fspi_prepare_lut cmd[opcode:65 bwidth:1] 
> > > > > aadr[val:2,
> > > nbytes:3, bwidth:1]
> > > > > [2.196101] dummy[nbytes:1 bwidth:1] data[dir:0 bwidth:1, nbytes:1]
> > > > > [2.202447] nxp-fspi 20c.flexspi: CMD[65] lutval[0:8180465
> > > 1:24003008  2:0 3:0]
> > > > > [2.210539] nxp_fspi_read_rxfifo, ReadData op.buf[0x02]
> > > > > [2.217319] smpt_read[3] addr[0002], data_byte[0002]
> > > err:
> > > > >
> > > > >
> > > > > [2.224098] smpt[4]=[addr_width:0003, read_dumy:0008,
> > > read_opcode:0065, data_mask:0002]
> > > > > [2.231744] m25p80_read, nor[op:0065 addr_width:0003,
> > > dummy:0008, len:0001
> > > > > [2.239998] m25p80_read, cmd[opcode:65 bwidth:1] aadr[val:4,
> nbytes:3,
> > > bwidth:1]
> > > > > [2.247383] m25p80_read, dummy[nbyte

RE: [PATCH v2 1/5] mtd: spi-nor: don't drop sfdp data if optional parsers fail

[Yogesh Narayan Gaur]

> -Original Message-
> From: tudor.amba...@microchip.com [mailto:tudor.amba...@microchip.com]
> Sent: Friday, November 9, 2018 10:27 PM
> To: boris.brezil...@bootlin.com; marek.va...@gmail.com;
> dw...@infradead.org; computersforpe...@gmail.com; rich...@nod.at
> Cc: linux-...@lists.infradead.org; linux-kernel@vger.kernel.org; Yogesh
> Narayan Gaur ; cyrille.pitc...@wedev4u.fr;
> tudor.amba...@microchip.com
> Subject: [PATCH v2 1/5] mtd: spi-nor: don't drop sfdp data if optional 
> parsers fail
> 
> JESD216C states that just the Basic Flash Parameter Table is mandatory.
> Already defined (or future) additional parameter headers and tables are 
> optional.
> 
> Don't drop already collected sfdp data in case an optional table parser 
> fails. In
> case of failing, each optional parser is responsible to roll back to the 
> previously
> known spi_nor data.
> 
> Fixes: b038e8e3be72 ("mtd: spi-nor: parse SFDP Sector Map Parameter Table")
> Reported-by: Yogesh Gaur 
Tested-by: Yogesh Gaur 

> Suggested-by: Boris Brezillon 
> Signed-off-by: Tudor Ambarus 
> ---
> v2: update Fixes tag to point to correct commit
> 
>  drivers/mtd/spi-nor/spi-nor.c | 15 ---
>  1 file changed, 12 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c 
> index
> 4a96ee719e5a..2cdf96013689 100644
> --- a/drivers/mtd/spi-nor/spi-nor.c
> +++ b/drivers/mtd/spi-nor/spi-nor.c
> @@ -3130,7 +3130,7 @@ static int spi_nor_parse_sfdp(struct spi_nor *nor,
>   if (err)
>   goto exit;
> 
> - /* Parse other parameter headers. */
> + /* Parse optional parameter tables. */
>   for (i = 0; i < header.nph; i++) {
>   param_header = _headers[i];
> 
> @@ -3143,8 +3143,17 @@ static int spi_nor_parse_sfdp(struct spi_nor *nor,
>   break;
>   }
> 
> - if (err)
> - goto exit;
> + if (err) {
> + dev_warn(dev, "Failed to parse optional parameter
> table: %04x\n",
> +  SFDP_PARAM_HEADER_ID(param_header));
> + /*
> +  * Let's not drop all information we extracted so far
> +  * if optional table parsers fail. In case of failing,
> +  * each optional parser is responsible to roll back to
> +  * the previously known spi_nor data.
> +  */
> + err = 0;
> + }
>   }
> 
>  exit:
> --
> 2.9.4

RE: [PATCH v4 01/10] spi: Add a driver for the Freescale/NXP QuadSPI controller

[Yogesh Narayan Gaur]

Hi,

> -Original Message-
> From: Frieder Schrempf [mailto:frieder.schre...@kontron.de]
> Sent: Wednesday, November 7, 2018 8:13 PM
> To: linux-...@lists.infradead.org; boris.brezil...@bootlin.com; linux-
> s...@vger.kernel.org
> Cc: dw...@infradead.org; computersforpe...@gmail.com;
> marek.va...@gmail.com; rich...@nod.at; miquel.ray...@bootlin.com;
> broo...@kernel.org; David Wolfe ; Fabio Estevam
> ; Prabhakar Kushwaha
> ; Yogesh Narayan Gaur
> ; Han Xu ;
> shawn...@kernel.org; Frieder Schrempf ; linux-
> ker...@vger.kernel.org
> Subject: [PATCH v4 01/10] spi: Add a driver for the Freescale/NXP QuadSPI
> controller
> 
> From: Frieder Schrempf 
> 
> This driver is derived from the SPI NOR driver at mtd/spi-nor/fsl-quadspi.c. 
> It
> uses the new SPI memory interface of the SPI framework to issue flash memory
> operations to up to four connected flash chips (2 buses with 2 CS each).
> 
> The controller does not support generic SPI messages.
> 
> Signed-off-by: Frieder Schrempf 
> ---
>  drivers/spi/Kconfig|  11 +
>  drivers/spi/Makefile   |   1 +
>  drivers/spi/spi-fsl-qspi.c | 948 
>  3 files changed, 960 insertions(+)
> 
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 7d3a5c9..52e2298
> 100644
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -259,6 +259,17 @@ config SPI_FSL_LPSPI
>   help
> This enables Freescale i.MX LPSPI controllers in master mode.
> 
> +config SPI_FSL_QSPI
> + tristate "Freescale QSPI controller"
> + depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE ||
> COMPILE_TEST
> + depends on HAS_IOMEM
> + help
> +   This enables support for the Quad SPI controller in master mode.
> +   Up to four flash chips can be connected on two buses with two
> +   chipselects each.
> +   This controller does not support generic SPI messages. It only
> +   supports the high-level SPI memory interface.
> +
>  config SPI_GPIO
>   tristate "GPIO-based bitbanging SPI Master"
>   depends on GPIOLIB || COMPILE_TEST
> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 
> 3575205..833b9e7
> 100644
> --- a/drivers/spi/Makefile
> +++ b/drivers/spi/Makefile
> @@ -44,6 +44,7 @@ obj-$(CONFIG_SPI_FSL_DSPI)  += spi-fsl-
> dspi.o
>  obj-$(CONFIG_SPI_FSL_LIB)+= spi-fsl-lib.o
>  obj-$(CONFIG_SPI_FSL_ESPI)   += spi-fsl-espi.o
>  obj-$(CONFIG_SPI_FSL_LPSPI)  += spi-fsl-lpspi.o
> +obj-$(CONFIG_SPI_FSL_QSPI)   += spi-fsl-qspi.o
>  obj-$(CONFIG_SPI_FSL_SPI)+= spi-fsl-spi.o
>  obj-$(CONFIG_SPI_GPIO)   += spi-gpio.o
>  obj-$(CONFIG_SPI_IMG_SPFI)   += spi-img-spfi.o
> diff --git a/drivers/spi/spi-fsl-qspi.c b/drivers/spi/spi-fsl-qspi.c new file 
> mode
> 100644 index 000..a43cfe8
> --- /dev/null
> +++ b/drivers/spi/spi-fsl-qspi.c
> @@ -0,0 +1,948 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +
> +/*
> + * Freescale QuadSPI driver.
> + *
> + * Copyright (C) 2013 Freescale Semiconductor, Inc.
> + * Copyright (C) 2018 Bootlin
> + * Copyright (C) 2018 exceet electronics GmbH
> + * Copyright (C) 2018 Kontron Electronics GmbH
> + *
> + * Transition to SPI MEM interface:
> + * Author:
> + * Boris Brezillion 
> + * Frieder Schrempf 
> + * Yogesh Gaur 
> + * Suresh Gupta 
> + *
> + * Based on the original fsl-quadspi.c spi-nor driver:
> + * Author: Freescale Semiconductor, Inc.
> + *
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include 
> +#include 
> +
> +/*
> + * The driver only uses one single LUT entry, that is updated on
> + * each call of exec_op(). Index 0 is preset at boot with a basic
> + * read operation, so let's use the last entry (15).
> + */
> +#define  SEQID_LUT   15
> +
> +/* Registers used by the driver */
> +#define QUADSPI_MCR  0x00
> +#define QUADSPI_MCR_RESERVED_MASKGENMASK(19, 16)
> +#define QUADSPI_MCR_MDIS_MASKBIT(14)
> +#define QUADSPI_MCR_CLR_TXF_MASK BIT(11)
> +#define QUADSPI_MCR_CLR_RXF_MASK BIT(10)
> +#define QUADSPI_MCR_DDR_EN_MASK  BIT(7)
> +#define QUADSPI_MCR_END_CFG_MASK GENMASK(3, 2)
> +#define QUADSPI_MCR_SWRSTHD_MASK BIT(1)
> +#define QUADSPI_MCR_SWRSTSD_MASK BIT(0)
> +
> +#define QUADSPI_IPCR 0x08
&g

RE: [PATCH] mtd: spi-nor: cast to u64 to avoid uint overflows

[Yogesh Narayan Gaur]

Hi Huijin,

I guess this is the v2 of previously send patch [1], please follow version 
information in patch submission.

--
Regards
Yogesh Gaur
[1] https://patchwork.ozlabs.org/patch/961197/


> -Original Message-
> From: linux-mtd [mailto:linux-mtd-boun...@lists.infradead.org] On Behalf Of
> Huijin Park
> Sent: Tuesday, November 13, 2018 10:49 AM
> To: Boris Brezillon 
> Cc: Marek Vasut ; linux-...@lists.infradead.org;
> linux-kernel@vger.kernel.org; bbanghj.p...@gmail.com; Huijin Park
> 
> Subject: [PATCH] mtd: spi-nor: cast to u64 to avoid uint overflows
> 
> From: "huijin.park" 
> 
> The "params->size" is defined as "u64".
> And "info->sector_size" and "info->n_sectors" are defined as unsigned int and
> u16.
> Thus, u64 data might have strange data(loss data) if the result overflows an
> unsigned int.
> This patch casts "info->sector_size" and "info->n_sectors" to an u64.
> 
> Signed-off-by: huijin.park 
> ---
>  drivers/mtd/spi-nor/spi-nor.c |2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c 
> index
> d9c368c..527f281 100644
> --- a/drivers/mtd/spi-nor/spi-nor.c
> +++ b/drivers/mtd/spi-nor/spi-nor.c
> @@ -2459,7 +2459,7 @@ static int spi_nor_init_params(struct spi_nor *nor,
>   memset(params, 0, sizeof(*params));
> 
>   /* Set SPI NOR sizes. */
> - params->size = info->sector_size * info->n_sectors;
> + params->size = (u64)info->sector_size * (u64)info->n_sectors;
>   params->page_size = info->page_size;
> 
>   /* (Fast) Read settings. */
> --
> 1.7.9.5
> 
> 
> __
> Linux MTD discussion mailing list
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> adead.org%2Fmailman%2Flistinfo%2Flinux-
> mtd%2Fdata=02%7C01%7Cyogeshnarayan.gaur%40nxp.com%7C5efd964
> 86c7244f430b408d649278b65%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%
> 7C1%7C636776831529836639sdata=A7hiJMpfxXKTyT6yacIougPRGdHg2o
> pL492y3sVtQek%3Dreserved=0

RE: [PATCH RESEND v4 1/5] spi: spi-mem: Add driver for NXP FlexSPI controller

[Yogesh Narayan Gaur]

Hi Frieder,

Thanks for review.

> -Original Message-
> From: Schrempf Frieder [mailto:frieder.schre...@kontron.de]
> Sent: Wednesday, November 7, 2018 9:52 PM
> To: Yogesh Narayan Gaur ; linux-
> m...@lists.infradead.org; boris.brezil...@bootlin.com; marek.va...@gmail.com;
> broo...@kernel.org; linux-...@vger.kernel.org; devicet...@vger.kernel.org
> Cc: r...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org; linux-
> arm-ker...@lists.infradead.org; computersforpe...@gmail.com;
> frieder.schre...@exceet.de; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH RESEND v4 1/5] spi: spi-mem: Add driver for NXP FlexSPI
> controller
> 
> Hi Yogesh,
> 
> I didn't have time to look at all of the code, but nevertheless here are some
> comments.
> 
> On 23.10.18 10:56, Yogesh Narayan Gaur wrote:
> > - Add driver for NXP FlexSPI host controller
> >
> > (0) What is the FlexSPI controller?
> >   FlexSPI is a flexsible SPI host controller which supports two SPI
> >   channels and up to 4 external devices. Each channel supports
> >   Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional
> >   data lines) i.e. FlexSPI acts as an interface to external devices,
> >   maximum 4, each with up to 8 bidirectional data lines.
> >
> >   It uses new SPI memory interface of the SPI framework to issue
> >   flash memory operations to up to four connected flash
> >   devices (2 buses with 2 CS each).
> >
> > (1) Tested this driver with the mtd_debug and JFFS2 filesystem utility
> >   on NXP LX2160ARDB and LX2160AQDS targets.
> >   LX2160ARDB is having two NOR slave device connected on single bus A
> >   i.e. A0 and A1 (CS0 and CS1).
> >   LX2160AQDS is having two NOR slave device connected on separate buses
> >   one flash on A0 and second on B1 i.e. (CS0 and CS3).
> >   Verified this driver on following SPI NOR flashes:
> >  Micron, mt35xu512ab, [Read - 1 bit mode]
> >  Cypress, s25fl512s, [Read - 1/2/4 bit mode]
> >
> > Signed-off-by: Yogesh Gaur 
> > ---
> > Changes for v4:
> > - Incorporate Boris review comments
> >* Use readl_poll_timeout() instead of busy looping.
> >* Re-define register masking as per comment.
> >* Drop fspi_devtype enum.
> > Changes for v3:
> > - Added endianness flag in platform specific structure instead of DTS.
> > - Modified nxp_fspi_read_ahb(), removed remapping code.
> > - Added Boris and Frieder as Author and provided reference of
> > spi-fsl-qspi.c Changes for v2:
> > - Incorporated Boris review comments.
> > - Remove dependency of driver over connected flash device size.
> > - Modified the logic to select requested CS.
> > - Remove SPI-Octal Macros.
> >
> >   drivers/spi/Kconfig|   10 +
> >   drivers/spi/Makefile   |1 +
> >   drivers/spi/spi-nxp-fspi.c | 1158
> 
> >   3 files changed, 1169 insertions(+)
> >   create mode 100644 drivers/spi/spi-nxp-fspi.c
> >
> > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index
> > ad5d68e..68da874 100644
> > --- a/drivers/spi/Kconfig
> > +++ b/drivers/spi/Kconfig
> > @@ -251,6 +251,16 @@ config SPI_FSL_LPSPI
> > help
> >   This enables Freescale i.MX LPSPI controllers in master mode.
> >
> > +config SPI_NXP_FLEXSPI
> > +   tristate "NXP Flex SPI controller"
> > +   depends on ARCH_LAYERSCAPE || HAS_IOMEM
> > +   help
> > + This enables support for the Flex SPI controller in master mode.
> > + Up to four slave devices can be connected on two buses with two
> > + chipselects each.
> > + This controller does not support generic SPI messages and only
> > + supports the high-level SPI memory interface.
> > +
> >   config SPI_GPIO
> > tristate "GPIO-based bitbanging SPI Master"
> > depends on GPIOLIB || COMPILE_TEST
> > diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index
> > cb1f437..52c9f18 100644
> > --- a/drivers/spi/Makefile
> > +++ b/drivers/spi/Makefile
> > @@ -59,6 +59,7 @@ obj-$(CONFIG_SPI_MPC52xx) += spi-
> mpc52xx.o
> >   obj-$(CONFIG_SPI_MT65XX)+= spi-mt65xx.o
> >   obj-$(CONFIG_SPI_MXS) += spi-mxs.o
> >   obj-$(CONFIG_SPI_NUC900)  += spi-nuc900.o
> > +obj-$(CONFIG_SPI_NXP_FLEXSPI)  += spi-nxp-fspi.o
> >   obj-$(CONFIG_SPI_OC_TINY) += spi-oc-tiny.o
> >   spi-octeon-objs   := spi-cavium.o spi-cavium-
> octeon.o
> >   obj-$(CONFIG_SPI_OCTEON)  += s

RE: [PATCH v4 01/10] spi: Add a driver for the Freescale/NXP QuadSPI controller

[Yogesh Narayan Gaur]

Hi,

> -Original Message-
> From: Yogesh Narayan Gaur
> Sent: Tuesday, November 13, 2018 1:53 PM
> To: 'Frieder Schrempf' ; linux-
> m...@lists.infradead.org; boris.brezil...@bootlin.com; linux-
> s...@vger.kernel.org
> Cc: dw...@infradead.org; computersforpe...@gmail.com;
> marek.va...@gmail.com; rich...@nod.at; miquel.ray...@bootlin.com;
> broo...@kernel.org; David Wolfe ; Fabio Estevam
> ; Prabhakar Kushwaha
> ; Han Xu ;
> shawn...@kernel.org; Frieder Schrempf ; linux-
> ker...@vger.kernel.org
> Subject: RE: [PATCH v4 01/10] spi: Add a driver for the Freescale/NXP QuadSPI
> controller
> 
> Hi,
> 
> > -Original Message-
> > From: Frieder Schrempf [mailto:frieder.schre...@kontron.de]
> > Sent: Wednesday, November 7, 2018 8:13 PM
> > To: linux-...@lists.infradead.org; boris.brezil...@bootlin.com; linux-
> > s...@vger.kernel.org
> > Cc: dw...@infradead.org; computersforpe...@gmail.com;
> > marek.va...@gmail.com; rich...@nod.at; miquel.ray...@bootlin.com;
> > broo...@kernel.org; David Wolfe ; Fabio Estevam
> > ; Prabhakar Kushwaha
> > ; Yogesh Narayan Gaur
> > ; Han Xu ;
> > shawn...@kernel.org; Frieder Schrempf ;
> > linux- ker...@vger.kernel.org
> > Subject: [PATCH v4 01/10] spi: Add a driver for the Freescale/NXP
> > QuadSPI controller
> >
> > From: Frieder Schrempf 
> >
> > This driver is derived from the SPI NOR driver at
> > mtd/spi-nor/fsl-quadspi.c. It uses the new SPI memory interface of the
> > SPI framework to issue flash memory operations to up to four connected flash
> chips (2 buses with 2 CS each).
> >
> > The controller does not support generic SPI messages.
> >
> > Signed-off-by: Frieder Schrempf 
> > ---
> >  drivers/spi/Kconfig|  11 +
> >  drivers/spi/Makefile   |   1 +
> >  drivers/spi/spi-fsl-qspi.c | 948
> > 
> >  3 files changed, 960 insertions(+)
> >
> > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index
> > 7d3a5c9..52e2298
> > 100644
> > --- a/drivers/spi/Kconfig
> > +++ b/drivers/spi/Kconfig
> > @@ -259,6 +259,17 @@ config SPI_FSL_LPSPI
> > help
> >   This enables Freescale i.MX LPSPI controllers in master mode.
> >
> > +config SPI_FSL_QSPI
> > +   tristate "Freescale QSPI controller"
> > +   depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE ||
> > COMPILE_TEST
> > +   depends on HAS_IOMEM
> > +   help
> > + This enables support for the Quad SPI controller in master mode.
> > + Up to four flash chips can be connected on two buses with two
> > + chipselects each.
> > + This controller does not support generic SPI messages. It only
> > + supports the high-level SPI memory interface.
> > +
> >  config SPI_GPIO
> > tristate "GPIO-based bitbanging SPI Master"
> > depends on GPIOLIB || COMPILE_TEST
> > diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index
> > 3575205..833b9e7
> > 100644
> > --- a/drivers/spi/Makefile
> > +++ b/drivers/spi/Makefile
> > @@ -44,6 +44,7 @@ obj-$(CONFIG_SPI_FSL_DSPI)+= spi-fsl-
> > dspi.o
> >  obj-$(CONFIG_SPI_FSL_LIB)  += spi-fsl-lib.o
> >  obj-$(CONFIG_SPI_FSL_ESPI) += spi-fsl-espi.o
> >  obj-$(CONFIG_SPI_FSL_LPSPI)+= spi-fsl-lpspi.o
> > +obj-$(CONFIG_SPI_FSL_QSPI) += spi-fsl-qspi.o
> >  obj-$(CONFIG_SPI_FSL_SPI)  += spi-fsl-spi.o
> >  obj-$(CONFIG_SPI_GPIO) += spi-gpio.o
> >  obj-$(CONFIG_SPI_IMG_SPFI) += spi-img-spfi.o
> > diff --git a/drivers/spi/spi-fsl-qspi.c b/drivers/spi/spi-fsl-qspi.c
> > new file mode
> > 100644 index 000..a43cfe8
> > --- /dev/null
> > +++ b/drivers/spi/spi-fsl-qspi.c
> > @@ -0,0 +1,948 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +
> > +/*
> > + * Freescale QuadSPI driver.
> > + *
> > + * Copyright (C) 2013 Freescale Semiconductor, Inc.
> > + * Copyright (C) 2018 Bootlin
> > + * Copyright (C) 2018 exceet electronics GmbH
> > + * Copyright (C) 2018 Kontron Electronics GmbH
> > + *
> > + * Transition to SPI MEM interface:
> > + * Author:
> > + * Boris Brezillion 
> > + * Frieder Schrempf 
> > + * Yogesh Gaur 
> > + * Suresh Gupta 
> > + *
> > + * Based on the original fsl-quadspi.c spi-nor driver:
> > + * Author: Freescale Semiconductor, Inc.
> > + *
> > + */
> > +
> > +#include 
> > +#include 
> > +#include 
>

RE: [PATCH v5 3/9] spi: Add a driver for the Freescale/NXP QuadSPI controller

[Yogesh Narayan Gaur]

Hi Frieder,

> -Original Message-
> From: Schrempf Frieder [mailto:frieder.schre...@kontron.de]
> Sent: Thursday, November 15, 2018 7:32 PM
> To: Yogesh Narayan Gaur 
> Cc: Boris Brezillon ; 
> linux-...@lists.infradead.org;
> linux-...@vger.kernel.org; Marek Vasut ; Mark
> Brown ; Han Xu ;
> dw...@infradead.org; computersforpe...@gmail.com; rich...@nod.at;
> miquel.ray...@bootlin.com; David Wolfe ; Fabio
> Estevam ; Prabhakar Kushwaha
> ; shawn...@kernel.org; linux-
> ker...@vger.kernel.org
> Subject: Re: [PATCH v5 3/9] spi: Add a driver for the Freescale/NXP QuadSPI
> controller
> 
> Hi Yogesh,
> 
> On 15.11.18 14:12, Boris Brezillon wrote:
> > On Thu, 15 Nov 2018 11:43:05 +
> > Schrempf Frieder  wrote:
> >
> >> On 15.11.18 07:22, Yogesh Narayan Gaur wrote:
> >>> Hi Frieder,
> >>>
> >>> With below patch on top of your v5, Read/Write/Erase on CS1 is working
> fine for me.
> >>
> >> Ok, are you sure, that AHB read is working too with this patch?
> >> You are removing the memmap_phy offset from SFAR and the SFXXAD
> >> register values.
> >>
> >> I can understand that selection of the CS and IP commands will work
> >> like this, but I can't understand how AHB read should work without
> >> the base address of the mapped memory.
> >>
> >> I'm afraid I still don't fully understand the background of these
> >> things,
> >
> > Same here. Yogesh, can you give us more detail on why you decided to
> > drop the memmap_phy offset?
> 
> Your changes do not work on my setup (i.MX6UL). It looks like your hardware is
> different.
> 
> I found this patch for LS2080A: [1]. This would explain why you need to remove
> the offset to make it work.
> 
> To verify this, could you please test your setup with the current spi-nor 
> driver
> (fsl_quadspi.c). If our assumptions are right, it should only work on CS0 and 
> CS1
> with [1] applied.
> 

Yes, I need to remove the offset to make it work and this is required for the 
NXP Layerscape-2.x SoCs like LS208x/Ls108x etc.

I have modified the patch and have introduced entry in quirks for ls2080a. With 
this Read/Write/Erase are working for me for both CS.

diff --git a/drivers/spi/spi-fsl-qspi.c b/drivers/spi/spi-fsl-qspi.c
index ce45e8e..5d26f73 100644
--- a/drivers/spi/spi-fsl-qspi.c
+++ b/drivers/spi/spi-fsl-qspi.c
@@ -175,6 +175,9 @@
 /* TKT245618, the controller cannot wake up from wait mode */
 #define QUADSPI_QUIRK_TKT245618BIT(3)

+/* QSPI_AMBA_BASE is internally added by SOC design for LS-2.x architecture */
+#define QUADSPI_AMBA_BASE_INTERNAL BIT(4)
+
 struct fsl_qspi_devtype_data {
unsigned int rxfifo;
unsigned int txfifo;
@@ -227,7 +230,7 @@ static const struct fsl_qspi_devtype_data ls2080a_data = {
.rxfifo = SZ_128,
.txfifo = SZ_64,
.ahb_buf_size = SZ_1K,
-   .quirks = QUADSPI_QUIRK_TKT253890,
+   .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_AMBA_BASE_INTERNAL,
.little_endian = true,
 };

@@ -235,6 +238,7 @@ struct fsl_qspi {
void __iomem *iobase;
void __iomem *ahb_addr;
u32 memmap_phy;
+   u32 amba_base_addr;
struct clk *clk, *clk_en;
struct device *dev;
struct completion c;
@@ -264,6 +268,11 @@ static inline int needs_wakeup_wait_mode(struct fsl_qspi 
*q)
return q->devtype_data->quirks & QUADSPI_QUIRK_TKT245618;
 }

+static inline int has_added_amba_base_internal(struct fsl_qspi *q)
+{
+   return q->devtype_data->quirks & QUADSPI_AMBA_BASE_INTERNAL;
+}
+
 /*
  * An IC bug makes it necessary to rearrange the 32-bit data.
  * Later chips, such as IMX6SLX, have fixed this bug.
@@ -489,29 +498,11 @@ static void fsl_qspi_invalidate(struct fsl_qspi *q)
 static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_device *spi)
 {
unsigned long rate = spi->max_speed_hz;
-   int ret, i;
-   u32 map_addr;
+   int ret;

if (q->selected == spi->chip_select)
return;

-   /*
-* In HW there can be a maximum of four chips on two buses with
-* two chip selects on each bus. We use four chip selects in SW
-* to differentiate between the four chips.
-* We use the SFA1AD, SFA2AD, SFB1AD, SFB2AD registers to select
-* the chip we want to access.
-*/
-   for (i = 0; i < 4; i++) {
-   if (i < spi->chip_select)
-   map_addr = q->memmap_phy;
-   else
-   map_addr = q->memmap_phy +
-  2 * q->devtype_data->ahb_buf_size;
-
-   qspi_writel(q, map_addr, q->iobase + QUADSPI_SFA1AD + (i * 4));
-   }
-
  

RE: [PATCH v5 3/9] spi: Add a driver for the Freescale/NXP QuadSPI controller

[Yogesh Narayan Gaur]

Hi Frieder,

> -Original Message-
> From: Schrempf Frieder [mailto:frieder.schre...@kontron.de]
> Sent: Friday, November 16, 2018 3:12 PM
> To: Yogesh Narayan Gaur 
> Cc: Boris Brezillon ; 
> linux-...@lists.infradead.org;
> linux-...@vger.kernel.org; Marek Vasut ; Mark
> Brown ; Han Xu ;
> dw...@infradead.org; computersforpe...@gmail.com; rich...@nod.at;
> miquel.ray...@bootlin.com; David Wolfe ; Fabio
> Estevam ; Prabhakar Kushwaha
> ; shawn...@kernel.org; linux-
> ker...@vger.kernel.org
> Subject: Re: [PATCH v5 3/9] spi: Add a driver for the Freescale/NXP QuadSPI
> controller
> 
> Hi Yogesh,
> 
> On 16.11.18 06:41, Yogesh Narayan Gaur wrote:
> > Hi Frieder,
> >
> >> -Original Message-
> >> From: Schrempf Frieder [mailto:frieder.schre...@kontron.de]
> >> Sent: Thursday, November 15, 2018 7:32 PM
> >> To: Yogesh Narayan Gaur 
> >> Cc: Boris Brezillon ;
> >> linux-...@lists.infradead.org; linux-...@vger.kernel.org; Marek Vasut
> >> ; Mark Brown ; Han Xu
> >> ; dw...@infradead.org;
> computersforpe...@gmail.com;
> >> rich...@nod.at; miquel.ray...@bootlin.com; David Wolfe
> >> ; Fabio Estevam ;
> >> Prabhakar Kushwaha ;
> shawn...@kernel.org;
> >> linux- ker...@vger.kernel.org
> >> Subject: Re: [PATCH v5 3/9] spi: Add a driver for the Freescale/NXP
> >> QuadSPI controller
> >>
> >> Hi Yogesh,
> >>
> >> On 15.11.18 14:12, Boris Brezillon wrote:
> >>> On Thu, 15 Nov 2018 11:43:05 +
> >>> Schrempf Frieder  wrote:
> >>>
> >>>> On 15.11.18 07:22, Yogesh Narayan Gaur wrote:
> >>>>> Hi Frieder,
> >>>>>
> >>>>> With below patch on top of your v5, Read/Write/Erase on CS1 is
> >>>>> working
> >> fine for me.
> >>>>
> >>>> Ok, are you sure, that AHB read is working too with this patch?
> >>>> You are removing the memmap_phy offset from SFAR and the SFXXAD
> >>>> register values.
> >>>>
> >>>> I can understand that selection of the CS and IP commands will work
> >>>> like this, but I can't understand how AHB read should work without
> >>>> the base address of the mapped memory.
> >>>>
> >>>> I'm afraid I still don't fully understand the background of these
> >>>> things,
> >>>
> >>> Same here. Yogesh, can you give us more detail on why you decided to
> >>> drop the memmap_phy offset?
> >>
> >> Your changes do not work on my setup (i.MX6UL). It looks like your
> >> hardware is different.
> >>
> >> I found this patch for LS2080A: [1]. This would explain why you need
> >> to remove the offset to make it work.
> >>
> >> To verify this, could you please test your setup with the current
> >> spi-nor driver (fsl_quadspi.c). If our assumptions are right, it
> >> should only work on CS0 and CS1 with [1] applied.
> >>
> >
> > Yes, I need to remove the offset to make it work and this is required for 
> > the
> NXP Layerscape-2.x SoCs like LS208x/Ls108x etc.
> >
> > I have modified the patch and have introduced entry in quirks for ls2080a. 
> > With
> this Read/Write/Erase are working for me for both CS.
> 
> Ok, what I was asking for is a test with the original, unmodified SPI NOR 
> driver in
> mtd/spi-nor/fsl-quadspi.c. We need this to confirm that the problem is really
> what we think, or to find out if we missed something.
> 
> Can you please do a quick test? If it confirms our assumptions, I will send a 
> new
> version with the quirk and hopefully we can then move on.
> 

Yes, problem exist with original un-modified upstread SPI-NOR driver also.
Actually, internally we are maintaining driver with some local change and one 
of the change is related to same i.e. making having map_addr as 0 for 
layerscape chips.

I have tested, that by removing that CS1 access shows error.

Please integrate these changes in your next version.

--
Regards
Yogesh Gaur

> Thanks,
> Frieder
> 
> >
> > diff --git a/drivers/spi/spi-fsl-qspi.c b/drivers/spi/spi-fsl-qspi.c
> > index ce45e8e..5d26f73 100644
> > --- a/drivers/spi/spi-fsl-qspi.c
> > +++ b/drivers/spi/spi-fsl-qspi.c
> > @@ -175,6 +175,9 @@
> >   /* TKT245618, the controller cannot wake up from wait mode */
> >   #define QUADSPI_QUIRK_TKT245618BIT(3)
> >
> > +/* QSPI_AMBA_BASE is internally added by SOC design for LS-2.x architecture
> */
> > +

RE: [PATCH v3 1/2] mtd: spi-nor: add macros related to MICRON flash

[Yogesh Narayan Gaur]

Hi Boris,

Please apply this patch series [1] in the coming release.

--
Regards
Yogesh Gaur
[1] https://patchwork.ozlabs.org/project/linux-mtd/list/?series=70384


> -Original Message-
> From: Yogesh Narayan Gaur
> Sent: Tuesday, October 23, 2018 3:31 PM
> To: 'Boris Brezillon' 
> Cc: Mark Brown ; Tudor Ambarus
> ; linux-...@lists.infradead.org; linux-
> s...@vger.kernel.org; marek.va...@gmail.com; cyrille.pitc...@wedev4u.fr;
> computersforpe...@gmail.com; frieder.schre...@exceet.de; linux-
> ker...@vger.kernel.org
> Subject: RE: [PATCH v3 1/2] mtd: spi-nor: add macros related to MICRON flash
> 
> Hi Boris,
> 
> > -Original Message-
> > From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> > Sent: Tuesday, October 23, 2018 3:27 PM
> > To: Yogesh Narayan Gaur 
> > Cc: Mark Brown ; Tudor Ambarus
> > ; linux-...@lists.infradead.org; linux-
> > s...@vger.kernel.org; marek.va...@gmail.com;
> > cyrille.pitc...@wedev4u.fr; computersforpe...@gmail.com;
> > frieder.schre...@exceet.de; linux- ker...@vger.kernel.org
> > Subject: Re: [PATCH v3 1/2] mtd: spi-nor: add macros related to MICRON
> > flash
> >
> > Hi Yogesh,
> >
> > On Tue, 23 Oct 2018 09:39:25 +
> > Yogesh Narayan Gaur  wrote:
> >
> > > Hi,
> > >
> > > Did we have have any comments or remarks about this patch-series,
> > > if not
> > please apply.
> >
> > Sorry, but it was already too late for this release, and the merge
> > window just started, so it will have to wait at least 2 more weeks.
> Ok.
> 
> >
> > We've been lagging with SPI NOR patches for the last couple releases
> > because I clearly don't have time to review those contributions, and
> > it seems Marek does not have time either.
> >
> > >
> > > Both patches in the series been reviewed by Tudor.
> >
> > Things are improving a bit thanks to Tudor's involvement in the review
> > process, but I'd like to remember you that you, as a regular
> > contributor to the spi-nor subsystem, can help us with that too. That
> > is, help review patches coming from others instead of only focusing on your
> own contributions.
> >
> Sure, I would start doing the review of other contributor patches.
> 
> --
> Regards
> Yogesh Gaur.
> 
> > Regards,
> >
> > Boris

[PATCH v5 1/5] spi: spi-mem: Add driver for NXP FlexSPI controller

[Yogesh Narayan Gaur]

- Add driver for NXP FlexSPI host controller

(0) What is the FlexSPI controller?
 FlexSPI is a flexsible SPI host controller which supports two SPI
 channels and up to 4 external devices. Each channel supports
 Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional
 data lines) i.e. FlexSPI acts as an interface to external devices,
 maximum 4, each with up to 8 bidirectional data lines.

 It uses new SPI memory interface of the SPI framework to issue
 flash memory operations to up to four connected flash
 devices (2 buses with 2 CS each).

(1) Tested this driver with the mtd_debug and JFFS2 filesystem utility
 on NXP LX2160ARDB and LX2160AQDS targets.
 LX2160ARDB is having two NOR slave device connected on single bus A
 i.e. A0 and A1 (CS0 and CS1).
 LX2160AQDS is having two NOR slave device connected on separate buses
 one flash on A0 and second on B1 i.e. (CS0 and CS3).
 Verified this driver on following SPI NOR flashes:
Micron, mt35xu512ab, [Read - 1 bit mode]
Cypress, s25fl512s, [Read - 1/2/4 bit mode]

Signed-off-by: Yogesh Gaur 
---
Changes for v5:
- Rebase on top of v4.20-rc2
- Modified fspi_readl_poll_tout() as per review comments
- Arrange header file in alphabetical order
- Removed usage of read()/write() function callback pointer
- Add support for 1 and 2 byte address length
- Change Frieder e-mail to new e-mail address
Changes for v4:
- Incorporate Boris review comments
  * Use readl_poll_timeout() instead of busy looping.
  * Re-define register masking as per comment.
  * Drop fspi_devtype enum.
Changes for v3:
- Added endianness flag in platform specific structure instead of DTS.
- Modified nxp_fspi_read_ahb(), removed remapping code.
- Added Boris and Frieder as Author and provided reference of spi-fsl-qspi.c
Changes for v2:
- Incorporated Boris review comments.
- Remove dependency of driver over connected flash device size.
- Modified the logic to select requested CS.
- Remove SPI-Octal Macros.

 drivers/spi/Kconfig|   10 +
 drivers/spi/Makefile   |1 +
 drivers/spi/spi-nxp-fspi.c | 1145 
 3 files changed, 1156 insertions(+)
 create mode 100644 drivers/spi/spi-nxp-fspi.c

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 7d3a5c9..36630a1 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -259,6 +259,16 @@ config SPI_FSL_LPSPI
help
  This enables Freescale i.MX LPSPI controllers in master mode.
 
+config SPI_NXP_FLEXSPI
+   tristate "NXP Flex SPI controller"
+   depends on ARCH_LAYERSCAPE || HAS_IOMEM
+   help
+ This enables support for the Flex SPI controller in master mode.
+ Up to four slave devices can be connected on two buses with two
+ chipselects each.
+ This controller does not support generic SPI messages and only
+ supports the high-level SPI memory interface.
+
 config SPI_GPIO
tristate "GPIO-based bitbanging SPI Master"
depends on GPIOLIB || COMPILE_TEST
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 3575205..55fec5c 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -60,6 +60,7 @@ obj-$(CONFIG_SPI_MPC52xx) += spi-mpc52xx.o
 obj-$(CONFIG_SPI_MT65XX)+= spi-mt65xx.o
 obj-$(CONFIG_SPI_MXS)  += spi-mxs.o
 obj-$(CONFIG_SPI_NUC900)   += spi-nuc900.o
+obj-$(CONFIG_SPI_NXP_FLEXSPI)  += spi-nxp-fspi.o
 obj-$(CONFIG_SPI_OC_TINY)  += spi-oc-tiny.o
 spi-octeon-objs:= spi-cavium.o 
spi-cavium-octeon.o
 obj-$(CONFIG_SPI_OCTEON)   += spi-octeon.o
diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c
new file mode 100644
index 000..a35013b
--- /dev/null
+++ b/drivers/spi/spi-nxp-fspi.c
@@ -0,0 +1,1145 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * NXP FlexSPI(FSPI) controller driver.
+ *
+ * Copyright 2018 NXP.
+ *
+ * FlexSPI is a flexsible SPI host controller which supports two SPI
+ * channels and up to 4 external devices. Each channel supports
+ * Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional
+ * data lines).
+ *
+ * FlexSPI controller is driven by the LUT(Look-up Table) registers
+ * LUT registers are a look-up-table for sequences of instructions.
+ * A valid sequence consists of four LUT registers.
+ * Maximum 32 LUT sequences can be programmed simultaneously.
+ *
+ * LUTs are being created at run-time based on the commands passed
+ * from the spi-mem framework, thus using single LUT index.
+ *
+ * Software triggered Flash read/write access by IP Bus.
+ *
+ * Memory mapped read access by AHB Bus.
+ *
+ * Based on SPI MEM interface and spi-fsl-qspi.c driver.
+ *
+ * Author:
+ * Yogesh Gaur 
+ * Boris Brezillion 
+ * Frieder Schrempf 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 

[PATCH v5 2/5] dt-bindings: spi: add binding file for NXP FlexSPI controller

[Yogesh Narayan Gaur]

Add binding file for NXP FlexSPI controller

Signed-off-by: Yogesh Gaur 
Reviewed-by: Rob Herring 
---
Changes for v5:
- None
Changes for v4:
- Incorporated Rob review comments.
Changes for v3:
- Removed node property 'big-endian'.
Changes for v2:
- Incorporated Rob review comments.
 .../devicetree/bindings/spi/spi-nxp-fspi.txt   | 39 ++
 1 file changed, 39 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/spi/spi-nxp-fspi.txt

diff --git a/Documentation/devicetree/bindings/spi/spi-nxp-fspi.txt 
b/Documentation/devicetree/bindings/spi/spi-nxp-fspi.txt
new file mode 100644
index 000..2cd67eb
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/spi-nxp-fspi.txt
@@ -0,0 +1,39 @@
+* NXP Flex Serial Peripheral Interface (FSPI)
+
+Required properties:
+  - compatible : Should be "nxp,lx2160a-fspi"
+  - reg :First contains the register location and length,
+ Second contains the memory mapping address and length
+  - reg-names :  Should contain the resource reg names:
+- fspi_base: configuration register address space
+ - fspi_mmap: memory mapped address space
+  - interrupts : Should contain the interrupt for the device
+
+Required SPI slave node properties:
+  - reg :There are two buses (A and B) with two chip selects each.
+ This encodes to which bus and CS the flash is connected:
+ - <0>: Bus A, CS 0
+ - <1>: Bus A, CS 1
+ - <2>: Bus B, CS 0
+ - <3>: Bus B, CS 1
+
+Example showing the usage of two SPI NOR slave devices on bus A:
+
+fspi0: spi@20c {
+   compatible = "nxp,lx2160a-fspi";
+   reg = <0x0 0x20c 0x0 0x1>, <0x0 0x2000 0x0 0x1000>;
+   reg-names = "fspi_base", "fspi_mmap";
+   interrupts = <0 25 0x4>; /* Level high type */
+   clocks = < 4 3>, < 4 3>;
+   clock-names = "fspi_en", "fspi";
+
+   mt35xu512aba0: flash@0 {
+   reg = <0>;
+   
+   };
+
+   mt35xu512aba1: flash@1 {
+   reg = <1>;
+   
+   };
+};
-- 
2.7.4

[PATCH v5 3/5] arm64: dts: lx2160a: add FlexSPI node property

[Yogesh Narayan Gaur]

Add fspi node property for LX2160A SoC for FlexSPI driver.
Property added for the FlexSPI controller and for the connected
slave device for the LX2160ARDB target.
This is having two SPI-NOR flash device, mt35xu512aba, connected
at CS0 and CS1.

Signed-off-by: Yogesh Gaur 
---
Changes for v5:
- None
Changes for v4:
- Incorporated Rob review comments.
Changes for v3:
- None.
Changes for v2:
- - Incorporated Shawn review comments.
---
 arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 22 ++
 arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi| 13 +
 2 files changed, 35 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts 
b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
index 1483071..3b20c97 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -35,6 +35,28 @@
status = "okay";
 };
 
+ {
+   status = "okay";
+
+   mt35xu512aba0: flash@0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "spansion,m25p80";
+   m25p,fast-read;
+   spi-max-frequency = <2000>;
+   reg = <0>;
+   };
+
+   mt35xu512aba1: flash@1 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "spansion,m25p80";
+   m25p,fast-read;
+   spi-max-frequency = <2000>;
+   reg = <1>;
+   };
+};
+
  {
status = "okay";
i2c-mux@77 {
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index c758268..5d0025a 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -698,5 +698,18 @@
interrupts = ;
timeout-sec = <30>;
};
+
+   fspi: spi@20c {
+   compatible = "nxp,lx2160a-fspi";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0x0 0x20c 0x0 0x1>,
+   <0x0 0x2000 0x0 0x1000>;
+   reg-names = "fspi_base", "fspi_mmap";
+   interrupts = <0 25 0x4>; /* Level high type */
+   clocks = < 4 3>, < 4 3>;
+   clock-names = "fspi_en", "fspi";
+   status = "disabled";
+   };
};
 };
-- 
2.7.4

[PATCH v5 0/5] spi: spi-mem: Add driver for NXP FlexSPI controller

[Yogesh Narayan Gaur]

- Add driver for NXP FlexSPI host controller

 FlexSPI is a flexsible SPI host controller [1], Chapter 30 page 1475,
 which supports two SPI channels and up to 4 external devices.
 Each channel supports Single/Dual/Quad/Octal mode data transfer (1/2/4/8 
bidirectional data lines)
 i.e. FlexSPI acts as an interface to external devices, maximum 4, each with up 
to 8
 bidirectional data lines.

- Tested this driver with mtd_debug(Erase/Write/Read) utility and JFFS2
 filesystem mounting and booting on NXP LX2160ARDB[2] and LX2160AQDS targets.
 LX2160ARDB is having two NOR slave device connected on single bus A
 i.e. A0 and A1 (CS0 and CS1).
 LX2160AQDS is having two NOR slave device connected on separate buses
 one flash on A0 and second on B1 i.e. (CS0 and CS3).
 Verified this driver on following SPI NOR flashes:
   Micron, mt35xu512aba[3], [Read - 1 bit mode]
   Cypress, s25fl512s, [Read - 1/2/4 bit mode]

[1] https://www.nxp.com/docs/en/reference-manual/IMXRT1050RM.pdf
[2] https://patchwork.kernel.org/project/linux-arm-kernel/list/?submitter=182097
[3] https://patchwork.ozlabs.org/project/linux-mtd/list/?series=70384

Yogesh Gaur (5):
  spi: spi-mem: Add driver for NXP FlexSPI controller
  dt-bindings: spi: add binding file for NXP FlexSPI controller
  arm64: dts: lx2160a: add FlexSPI node property
  arm64: defconfig: enable NXP FlexSPI driver
  MAINTAINERS: add maintainers for the NXP FlexSPI driver

Changes for v5:
- Rebase on top of v4.20-rc2
- Incorporated review comments for
  patch 'spi: spi-mem: Add driver for NXP FlexSPI controller'.
Changes for v4:
- Incorporated review comments for
  patch 'spi: spi-mem: Add driver for NXP FlexSPI controller'.
- Incorporated binding file review comments.
Changes for v3:
- Incorporated review comments for
  patch 'spi: spi-mem: Add driver for NXP FlexSPI controller'.
Changes for v2:
- Incorporated Boris review comments and drop below patches as per the comments.
 - Patch 'spi: add slave device size in spi_device struct'
 - Patch 'spi: add flags for octal I/O data transfer'
- Incorporated DTS and Binding file review comments of Shawn Guo and Rob 
Herring.

 .../devicetree/bindings/spi/spi-nxp-fspi.txt   |   39 +
 MAINTAINERS|7 +
 arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts  |   22 +
 arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi |   13 +
 arch/arm64/configs/defconfig   |1 +
 drivers/spi/Kconfig|   10 +
 drivers/spi/Makefile   |1 +
 drivers/spi/spi-nxp-fspi.c | 1145 
 8 files changed, 1238 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/spi/spi-nxp-fspi.txt
 create mode 100644 drivers/spi/spi-nxp-fspi.c

-- 
2.7.4

[PATCH v5 5/5] MAINTAINERS: add maintainers for the NXP FlexSPI driver

[Yogesh Narayan Gaur]

Add maintainers for the NXP FlexSPI driver

Signed-off-by: Yogesh Gaur 
---
Changes for v5:
- Add maintainers for binding file
Changes for v4:
- None
Changes for v3:
- None
Changes for v2:
- None

 MAINTAINERS | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 0abecc5..7076bf7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -10686,6 +10686,13 @@ L: linux-...@lists.01.org (moderated for 
non-subscribers)
 S: Supported
 F: drivers/nfc/nxp-nci
 
+NXP FSPI DRIVER
+M: Yogesh Gaur 
+L: linux-...@vger.kernel.org
+S: Maintained
+F: drivers/spi/spi-nxp-fspi.c
+F: Documentation/devicetree/bindings/spi/spi-nxp-fspi.txt
+
 OBJTOOL
 M: Josh Poimboeuf 
 M: Peter Zijlstra 
-- 
2.7.4

[PATCH v5 4/5] arm64: defconfig: enable NXP FlexSPI driver

[Yogesh Narayan Gaur]

Enable driver support of NXP FlexSPI controller.

Signed-off-by: Yogesh Gaur 
---
Changes for v5:
- None
Changes for v4:
- None
Changes for v3:
- None
Changes for v2:
- None
---
 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index c9a57d1..3d81e25 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -341,6 +341,7 @@ CONFIG_SPI_ROCKCHIP=y
 CONFIG_SPI_QUP=y
 CONFIG_SPI_S3C64XX=y
 CONFIG_SPI_SPIDEV=m
+CONFIG_SPI_NXP_FLEXSPI=y
 CONFIG_SPMI=y
 CONFIG_PINCTRL_SINGLE=y
 CONFIG_PINCTRL_MAX77620=y
-- 
2.7.4

RE: [PATCH v5 3/9] spi: Add a driver for the Freescale/NXP QuadSPI controller

[Yogesh Narayan Gaur]

Hi Frieder,

I have tried v5 version of the patch and have observed that Read is failing for 
CS1.

In my target 2 flash devices are connected on same bus i.e. A1 -> CS0 and A2 -> 
CS1.

On initial debugging, I figured that Read is failing for the AHB mode i.e. if I 
attempt to read data size less than rxfifo read is working fine without any 
issue.

For data size more than rxfifo Read out data is content of same requested 
address of CS0.
mtd_debug read /dev/mtd1 0xf0 0x70 read --> Data is correct
mtd_debug read /dev/mtd1 0xf0 0x100 read --> Data is in-correct and 
data content are of the address 0xf0 of CS0 connected flash device.

On the setup where you have done testing, did AHB mode read is being verified 
for CS1?

I am doing further debugging of this issue.

--
Regards
Yogesh Gaur

> -Original Message-
> From: Schrempf Frieder [mailto:frieder.schre...@kontron.de]
> Sent: Tuesday, November 13, 2018 7:18 PM
> To: linux-...@lists.infradead.org; boris.brezil...@bootlin.com; linux-
> s...@vger.kernel.org; Marek Vasut ; Mark Brown
> ; Han Xu 
> Cc: dw...@infradead.org; computersforpe...@gmail.com; rich...@nod.at;
> miquel.ray...@bootlin.com; David Wolfe ; Fabio
> Estevam ; Prabhakar Kushwaha
> ; Yogesh Narayan Gaur
> ; shawn...@kernel.org; Schrempf Frieder
> ; linux-kernel@vger.kernel.org
> Subject: [PATCH v5 3/9] spi: Add a driver for the Freescale/NXP QuadSPI
> controller
> 
> This driver is derived from the SPI NOR driver at mtd/spi-nor/fsl-quadspi.c. 
> It
> uses the new SPI memory interface of the SPI framework to issue flash memory
> operations to up to four connected flash chips (2 buses with 2 CS each).
> 
> The controller does not support generic SPI messages.
> 
> This patch also disables the build of the "old" driver and reuses its Kconfig 
> option
> CONFIG_SPI_FSL_QUADSPI to replace it.
> 
> Signed-off-by: Frieder Schrempf 
> ---
>  drivers/mtd/spi-nor/Kconfig  |   9 -
>  drivers/mtd/spi-nor/Makefile |   1 -
>  drivers/spi/Kconfig  |  11 +
>  drivers/spi/Makefile |   1 +
>  drivers/spi/spi-fsl-qspi.c   | 946 ++
>  5 files changed, 958 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig index
> 6cc9c92..d1ca307 100644
> --- a/drivers/mtd/spi-nor/Kconfig
> +++ b/drivers/mtd/spi-nor/Kconfig
> @@ -59,15 +59,6 @@ config SPI_CADENCE_QUADSPI
> device with a Cadence QSPI controller and want to access the
> Flash as an MTD device.
> 
> -config SPI_FSL_QUADSPI
> - tristate "Freescale Quad SPI controller"
> - depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE ||
> COMPILE_TEST
> - depends on HAS_IOMEM
> - help
> -   This enables support for the Quad SPI controller in master mode.
> -   This controller does not support generic SPI. It only supports
> -   SPI NOR.
> -
>  config SPI_HISI_SFC
>   tristate "Hisilicon SPI-NOR Flash Controller(SFC)"
>   depends on ARCH_HISI || COMPILE_TEST
> diff --git a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile index
> f4c61d2..3f160c2e3 100644
> --- a/drivers/mtd/spi-nor/Makefile
> +++ b/drivers/mtd/spi-nor/Makefile
> @@ -3,7 +3,6 @@ obj-$(CONFIG_MTD_SPI_NOR) += spi-nor.o
>  obj-$(CONFIG_SPI_ASPEED_SMC) += aspeed-smc.o
>  obj-$(CONFIG_SPI_ATMEL_QUADSPI)  += atmel-quadspi.o
>  obj-$(CONFIG_SPI_CADENCE_QUADSPI)+= cadence-quadspi.o
> -obj-$(CONFIG_SPI_FSL_QUADSPI)+= fsl-quadspi.o
>  obj-$(CONFIG_SPI_HISI_SFC)   += hisi-sfc.o
>  obj-$(CONFIG_MTD_MT81xx_NOR)+= mtk-quadspi.o
>  obj-$(CONFIG_SPI_NXP_SPIFI)  += nxp-spifi.o
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 7d3a5c9..8c84186
> 100644
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -259,6 +259,17 @@ config SPI_FSL_LPSPI
>   help
> This enables Freescale i.MX LPSPI controllers in master mode.
> 
> +config SPI_FSL_QUADSPI
> + tristate "Freescale QSPI controller"
> + depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE ||
> COMPILE_TEST
> + depends on HAS_IOMEM
> + help
> +   This enables support for the Quad SPI controller in master mode.
> +   Up to four flash chips can be connected on two buses with two
> +   chipselects each.
> +   This controller does not support generic SPI messages. It only
> +   supports the high-level SPI memory interface.
> +
>  config SPI_GPIO
>   tristate "GPIO-based bitbanging SPI Master"
>   depends on GPIOLIB || COMPILE_TEST
> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 
> 3575205..5377e61
> 100644
> --- a/drivers/

RE: [PATCH v5 3/9] spi: Add a driver for the Freescale/NXP QuadSPI controller

[Yogesh Narayan Gaur]

Hi Frieder,

[..]
> >
> > Ok, I will have a look at what could make the chip selection fail in
> > case of AHB read.
> 
> Could you try with this change applied:
> 
> @@ -503,7 +503,7 @@ static void fsl_qspi_select_mem(struct fsl_qspi *q, struct
> spi_device *spi)
>  map_addr = q->memmap_phy;
>  else
>  map_addr = q->memmap_phy +
> -  2 * q->devtype_data->ahb_buf_size;
> +  q->devtype_data->ahb_buf_size;
> 
>  qspi_writel(q, map_addr, q->iobase + QUADSPI_SFA1AD +
> (i * 4));
>  }
> 

I have tried above change and also have done few more changes but still AHB 
read for CS1 is falling.

I guess we need to implement dynamic memory mapping [1] for AHB Read as was 
being done in previous driver implementation.
Would try this and update you.

[1] https://patchwork.ozlabs.org/patch/503655/

--
Regards
Yogesh Gaur
[..]

RE: [PATCH v5 3/9] spi: Add a driver for the Freescale/NXP QuadSPI controller

[Yogesh Narayan Gaur]

Hi Frieder,

With below patch on top of your v5, Read/Write/Erase on CS1 is working fine for 
me.

I have tested with JFFS2 mounting and booting also for both CS0 and CS1.

diff --git a/drivers/spi/spi-fsl-qspi.c b/drivers/spi/spi-fsl-qspi.c
index ce45e8e..4467983 100644
--- a/drivers/spi/spi-fsl-qspi.c
+++ b/drivers/spi/spi-fsl-qspi.c
@@ -490,28 +490,10 @@ static void fsl_qspi_select_mem(struct fsl_qspi *q, 
struct spi_device *spi)
 {
unsigned long rate = spi->max_speed_hz;
int ret, i;
-   u32 map_addr;

if (q->selected == spi->chip_select)
return;

-   /*
-* In HW there can be a maximum of four chips on two buses with
-* two chip selects on each bus. We use four chip selects in SW
-* to differentiate between the four chips.
-* We use the SFA1AD, SFA2AD, SFB1AD, SFB2AD registers to select
-* the chip we want to access.
-*/
-   for (i = 0; i < 4; i++) {
-   if (i < spi->chip_select)
-   map_addr = q->memmap_phy;
-   else
-   map_addr = q->memmap_phy +
-  2 * q->devtype_data->ahb_buf_size;
-
-   qspi_writel(q, map_addr, q->iobase + QUADSPI_SFA1AD + (i * 4));
-   }
-
if (needs_4x_clock(q))
rate *= 4;

@@ -534,7 +516,9 @@ static void fsl_qspi_select_mem(struct fsl_qspi *q, struct 
spi_device *spi)

 static void fsl_qspi_read_ahb(struct fsl_qspi *q, const struct spi_mem_op *op)
 {
-   memcpy_fromio(op->data.buf.in, q->ahb_addr, op->data.nbytes);
+   memcpy_fromio(op->data.buf.in,
+ q->ahb_addr + q->selected * q->devtype_data->ahb_buf_size,
+ op->data.nbytes);
 }

 static void fsl_qspi_fill_txfifo(struct fsl_qspi *q,
@@ -634,7 +618,9 @@ static int fsl_qspi_exec_op(struct spi_mem *mem, const 
struct spi_mem_op *op)

fsl_qspi_select_mem(q, mem->spi);

-   qspi_writel(q, q->memmap_phy, base + QUADSPI_SFAR);
+   qspi_writel(q,
+   q->selected * q->devtype_data->ahb_buf_size,
+   base + QUADSPI_SFAR);

qspi_writel(q, qspi_readl(q, base + QUADSPI_MCR) |
QUADSPI_MCR_CLR_RXF_MASK | QUADSPI_MCR_CLR_TXF_MASK,
@@ -733,6 +719,19 @@ static int fsl_qspi_default_setup(struct fsl_qspi *q)
QUADSPI_BUF3CR_ADATSZ(q->devtype_data->ahb_buf_size / 8),
base + QUADSPI_BUF3CR);

+   /*
+* In HW there can be a maximum of four chips on two buses with
+* two chip selects on each bus. We use four chip selects in SW
+* to differentiate between the four chips.
+* We use the SFA1AD, SFA2AD, SFB1AD, SFB2AD registers to select
+* the chip we want to access.
+*/
+
+   qspi_writel(q, q->devtype_data->ahb_buf_size, base + QUADSPI_SFA1AD);
+   qspi_writel(q, q->devtype_data->ahb_buf_size * 2 , base + 
QUADSPI_SFA2AD);
+   qspi_writel(q, q->devtype_data->ahb_buf_size * 3 , base + 
QUADSPI_SFB1AD);
+   qspi_writel(q, q->devtype_data->ahb_buf_size * 4 , base + 
QUADSPI_SFB2AD);
+
q->selected = -1;

--
Regards
Yogesh Gaur

[..]

RE: [PATCH v3 1/5] spi: spi-mem: Add driver for NXP FlexSPI controller

[Yogesh Narayan Gaur]

Hi Boris,

> -Original Message-
> From: Frieder Schrempf [mailto:frieder.schre...@exceet.de]
> Sent: Monday, October 1, 2018 11:48 AM
> To: Boris Brezillon ; Yogesh Narayan Gaur
> 
> Cc: linux-...@lists.infradead.org; marek.va...@gmail.com; linux-
> s...@vger.kernel.org; devicet...@vger.kernel.org; r...@kernel.org;
> mark.rutl...@arm.com; shawn...@kernel.org; linux-arm-
> ker...@lists.infradead.org; computersforpe...@gmail.com; linux-
> ker...@vger.kernel.org
> Subject: Re: [PATCH v3 1/5] spi: spi-mem: Add driver for NXP FlexSPI 
> controller
> 
> Hi Boris,
> 
> On 29.09.2018 17:40, Boris Brezillon wrote:
> > Hi Yogesh,
> >
> > On Fri, 21 Sep 2018 15:51:59 +0530
> > Yogesh Gaur  wrote:
> >
> >> +/* Registers used by the driver */
> >> +#define FSPI_MCR0 0x00
> >> +#define FSPI_MCR0_AHB_TIMEOUT_SHIFT   24
> >> +#define FSPI_MCR0_AHB_TIMEOUT_MASK(0xFF <<
> FSPI_MCR0_AHB_TIMEOUT_SHIFT)
> >> +#define FSPI_MCR0_IP_TIMEOUT_SHIFT16
> >> +#define FSPI_MCR0_IP_TIMEOUT_MASK (0xFF <<
> FSPI_MCR0_IP_TIMEOUT_SHIFT)
> >> +#define FSPI_MCR0_LEARN_EN_SHIFT  15
> >> +#define FSPI_MCR0_LEARN_EN_MASK   (1 <<
> FSPI_MCR0_LEARN_EN_SHIFT)
> >> +#define FSPI_MCR0_SCRFRUN_EN_SHIFT14
> >> +#define FSPI_MCR0_SCRFRUN_EN_MASK (1 <<
> FSPI_MCR0_SCRFRUN_EN_SHIFT)
> >> +#define FSPI_MCR0_OCTCOMB_EN_SHIFT13
> >> +#define FSPI_MCR0_OCTCOMB_EN_MASK (1 <<
> FSPI_MCR0_OCTCOMB_EN_SHIFT)
> >> +#define FSPI_MCR0_DOZE_EN_SHIFT   12
> >> +#define FSPI_MCR0_DOZE_EN_MASK(1 <<
> FSPI_MCR0_DOZE_EN_SHIFT)
> >> +#define FSPI_MCR0_HSEN_SHIFT  11
> >> +#define FSPI_MCR0_HSEN_MASK   (1 << FSPI_MCR0_HSEN_SHIFT)
> >> +#define FSPI_MCR0_SERCLKDIV_SHIFT 8
> >> +#define FSPI_MCR0_SERCLKDIV_MASK  (7 <<
> FSPI_MCR0_SERCLKDIV_SHIFT)
> >> +#define FSPI_MCR0_ATDF_EN_SHIFT   7
> >> +#define FSPI_MCR0_ATDF_EN_MASK(1 <<
> FSPI_MCR0_ATDF_EN_SHIFT)
> >> +#define FSPI_MCR0_ARDF_EN_SHIFT   6
> >> +#define FSPI_MCR0_ARDF_EN_MASK(1 <<
> FSPI_MCR0_ARDF_EN_SHIFT)
> >> +#define FSPI_MCR0_RXCLKSRC_SHIFT  4
> >> +#define FSPI_MCR0_RXCLKSRC_MASK   (3 <<
> FSPI_MCR0_RXCLKSRC_SHIFT)
> >> +#define FSPI_MCR0_END_CFG_SHIFT   2
> >> +#define FSPI_MCR0_END_CFG_MASK(3 <<
> FSPI_MCR0_END_CFG_SHIFT)
> >> +#define FSPI_MCR0_MDIS_SHIFT  1
> >> +#define FSPI_MCR0_MDIS_MASK   (1 << FSPI_MCR0_MDIS_SHIFT)
> >> +#define FSPI_MCR0_SWRST_SHIFT 0
> >> +#define FSPI_MCR0_SWRST_MASK  (1 <<
> FSPI_MCR0_SWRST_SHIFT)
> >
> > Do we really need all those _SHIFT/_MASK defs? I mean
> >
> > #define FSPI_MCR0_SWRST BIT(0)
> >
> > or
> >
> > #define FSPI_MCR0_AHB_TIMEOUT(x)((x) << 24)
> > #define FSPI_MCR0_AHB_TIMEOUT_MASK  GENMASK(31, 24)
> >
> > are just fine.
> >
> >> +
> >> +enum nxp_fspi_devtype {
> >> +  NXP_FSPI_LX2160A,
> >> +};
> >
> > I'm pretty sure you don't need this enum if you describe all dev caps
> > in the nxp_fspi_devtype_data struct.
> >
> >> +
> >> +struct nxp_fspi_devtype_data {
> >> +  enum nxp_fspi_devtype devtype;
> >> +  unsigned int rxfifo;
> >> +  unsigned int txfifo;
> >> +  unsigned int ahb_buf_size;
> >> +  unsigned int quirks;
> >> +  bool endianness;
> >
> > How about renaming this variable big_endian and dropping the
> > {L,B}_ENDIAN macros?
> >
> >> +};
> >
> > [...]
> >
> >> +struct nxp_fspi {
> >> +  void __iomem *iobase;
> >> +  void __iomem *ahb_addr;
> >> +  u32 memmap_phy;
> >> +  u32 memmap_phy_size;
> >> +  struct clk *clk, *clk_en;
> >> +  struct device *dev;
> >> +  struct completion c;
> >> +  const struct nxp_fspi_devtype_data *devtype_data;
> >> +  struct mutex lock;
> >> +  struct pm_qos_request pm_qos_req;
> >> +  int selected;
> >> +  void (*write)(u32 val, void __iomem *addr);
> >> +  u32 (*read)(void __iomem *addr);
> >> +};
> >> +
> >> +static void fspi_writel_be(u32 val, void __iomem *addr) {
> >> +  iowrite32be(val, addr);
> >> +}
> >> +
> >> +static void fspi_writel(u32 val, void __iomem *addr) {
> >> +

[PATCH v2 1/2] mtd: spi-nor: add macros related to MICRON flash

[Yogesh Narayan Gaur]

Some MICRON related macros in spi-nor domain were ST.
Rename entries related to STMicroelectronics under macro SNOR_MFR_ST.

Added entry of MFR Id for Micron flashes, 0x002C.

Signed-off-by: Yogesh Gaur 
Reviewed-by: Tudor Ambarus 
---
Changes for v2:
- None

 drivers/mtd/spi-nor/spi-nor.c | 9 ++---
 include/linux/mtd/cfi.h   | 1 +
 include/linux/mtd/spi-nor.h   | 3 ++-
 3 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 9407ca5..b8b494f 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -284,6 +284,7 @@ static inline int set_4byte(struct spi_nor *nor, const 
struct flash_info *info,
u8 cmd;
 
switch (JEDEC_MFR(info)) {
+   case SNOR_MFR_ST:
case SNOR_MFR_MICRON:
/* Some Micron need WREN command; all will accept it */
need_wren = true;
@@ -1388,7 +1389,7 @@ static const struct flash_info spi_nor_ids[] = {
{ "mx66l1g45g",  INFO(0xc2201b, 0, 64 * 1024, 2048, SECT_4K | 
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ "mx66l1g55g",  INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) 
},
 
-   /* Micron */
+   /* Micron <--> ST Micro */
{ "n25q016a",INFO(0x20bb15, 0, 64 * 1024,   32, SECT_4K | 
SPI_NOR_QUAD_READ) },
{ "n25q032", INFO(0x20ba16, 0, 64 * 1024,   64, SPI_NOR_QUAD_READ) 
},
{ "n25q032a",INFO(0x20bb16, 0, 64 * 1024,   64, SPI_NOR_QUAD_READ) 
},
@@ -3223,6 +3224,7 @@ static int spi_nor_init_params(struct spi_nor *nor,
params->quad_enable = macronix_quad_enable;
break;
 
+   case SNOR_MFR_ST:
case SNOR_MFR_MICRON:
break;
 
@@ -3671,8 +3673,9 @@ int spi_nor_scan(struct spi_nor *nor, const char *name,
mtd->_resume = spi_nor_resume;
 
/* NOR protection support for STmicro/Micron chips and similar */
-   if (JEDEC_MFR(info) == SNOR_MFR_MICRON ||
-   info->flags & SPI_NOR_HAS_LOCK) {
+   if (JEDEC_MFR(info) == SNOR_MFR_ST ||
+   JEDEC_MFR(info) == SNOR_MFR_MICRON ||
+   info->flags & SPI_NOR_HAS_LOCK) {
nor->flash_lock = stm_lock;
nor->flash_unlock = stm_unlock;
nor->flash_is_locked = stm_is_locked;
diff --git a/include/linux/mtd/cfi.h b/include/linux/mtd/cfi.h
index 9b57a9b..cbf7716 100644
--- a/include/linux/mtd/cfi.h
+++ b/include/linux/mtd/cfi.h
@@ -377,6 +377,7 @@ struct cfi_fixup {
 #define CFI_MFR_SHARP  0x00B0
 #define CFI_MFR_SST0x00BF
 #define CFI_MFR_ST 0x0020 /* STMicroelectronics */
+#define CFI_MFR_MICRON 0x002C /* Micron */
 #define CFI_MFR_TOSHIBA0x0098
 #define CFI_MFR_WINBOND0x00DA
 
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index 7f0c730..8b1acf6 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -23,7 +23,8 @@
 #define SNOR_MFR_ATMEL CFI_MFR_ATMEL
 #define SNOR_MFR_GIGADEVICE0xc8
 #define SNOR_MFR_INTEL CFI_MFR_INTEL
-#define SNOR_MFR_MICRONCFI_MFR_ST /* ST Micro <--> Micron */
+#define SNOR_MFR_STCFI_MFR_ST  /* ST Micro */
+#define SNOR_MFR_MICRONCFI_MFR_MICRON  /* Micron */
 #define SNOR_MFR_MACRONIX  CFI_MFR_MACRONIX
 #define SNOR_MFR_SPANSION  CFI_MFR_AMD
 #define SNOR_MFR_SST   CFI_MFR_SST
-- 
2.7.4

[PATCH v2 2/2] mtd: spi-nor: add entry for mt35xu512aba flash

[Yogesh Narayan Gaur]

Add entry for mt35xu512aba Micron NOR flash.
This flash is having uniform sector erase size of 128KB, have
support of FSR(flag status register), flash size is 64MB and
supports 4-byte commands.

Signed-off-by: Yogesh Gaur 
---
Changes for v2:
- Removed checkpatch warning, 80 character limit.

 drivers/mtd/spi-nor/spi-nor.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index b8b494f..e0d95ac 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -1405,6 +1405,10 @@ static const struct flash_info spi_nor_ids[] = {
{ "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | 
SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
{ "mt25qu02g",   INFO(0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | 
SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
 
+   /* Micron */
+   { "mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512,
+   SECT_4K | USE_FSR | SPI_NOR_4B_OPCODES) },
+
/* PMC */
{ "pm25lv512",   INFO(0,0, 32 * 1024,2, SECT_4K_PMC) },
{ "pm25lv010",   INFO(0,0, 32 * 1024,4, SECT_4K_PMC) },
-- 
2.7.4

[PATCH v2 0/2] mtd: spi-nor: add entry for mt35xu512aba flash

[Yogesh Narayan Gaur]

Add MFR_ID information, 0x002C, related to the Micron flash.
Currently, MFR_ID 0x0020 is being specified as Micron flash ID but
these are actually CFI ID of STMicro flashes.

Rename SNOR_MFR_MICRON to SNOR_MFR_ST and add entry for
SNOR_MFR_MICRON having CFI ID value of Micron flash.
Add entry of mt35xu512aba [1] flash in spi_nor_ids table.

[1] https://www.micron.com/resource-details/0b74b806-bbf1-4c24-b07b-35e2799bb6ff

Yogesh Gaur (2):
  mtd: spi-nor: add macros related to MICRON flash
  mtd: spi-nor: add entry for mt35xu512aba flash

Changes for v2:
- Removed checkpatch warning, 80 character limit, in patch
 'mtd: spi-nor: add entry for mt35xu512aba flash'.

 drivers/mtd/spi-nor/spi-nor.c | 13 ++---
 include/linux/mtd/cfi.h   |  1 +
 include/linux/mtd/spi-nor.h   |  3 ++-
 3 files changed, 13 insertions(+), 4 deletions(-)

-- 
2.7.4

[PATCH v4 0/5] spi: spi-mem: Add driver for NXP FlexSPI controller

[Yogesh Narayan Gaur]

- Add driver for NXP FlexSPI host controller

 FlexSPI is a flexsible SPI host controller [1], Chapter 30 page 1475,
 which supports two SPI channels and up to 4 external devices.
 Each channel supports Single/Dual/Quad/Octal mode data transfer (1/2/4/8 
bidirectional data lines)
 i.e. FlexSPI acts as an interface to external devices, maximum 4, each with up 
to 8
 bidirectional data lines.

- Tested this driver with mtd_debug(Erase/Write/Read) utility and JFFS2
 filesystem mounting and booting on NXP LX2160ARDB[2] and LX2160AQDS targets.
 LX2160ARDB is having two NOR slave device connected on single bus A
 i.e. A0 and A1 (CS0 and CS1).
 LX2160AQDS is having two NOR slave device connected on separate buses
 one flash on A0 and second on B1 i.e. (CS0 and CS3).
 Verified this driver on following SPI NOR flashes:
   Micron, mt35xu512aba[3], [Read - 1 bit mode]
   Cypress, s25fl512s, [Read - 1/2/4 bit mode]

[1] https://www.nxp.com/docs/en/reference-manual/IMXRT1050RM.pdf
[2] https://patchwork.kernel.org/project/linux-arm-kernel/list/?series=26689
[3] https://patchwork.ozlabs.org/project/linux-mtd/list/?series=70179

Yogesh Gaur (5):
  spi: spi-mem: Add driver for NXP FlexSPI controller
  dt-bindings: spi: add binding file for NXP FlexSPI controller
  arm64: dts: lx2160a: add FlexSPI node property
  arm64: defconfig: enable NXP FlexSPI driver
  MAINTAINERS: add maintainers for the NXP FlexSPI driver

Changes for v4:
- Incorporated review comments for
  patch 'spi: spi-mem: Add driver for NXP FlexSPI controller'.
- Incorporated binding file review comments.
Changes for v3:
- Incorporated review comments for
  patch 'spi: spi-mem: Add driver for NXP FlexSPI controller'.
Changes for v2:
- Incorporated Boris review comments and drop below patches as per the comments.
 - Patch 'spi: add slave device size in spi_device struct'
 - Patch 'spi: add flags for octal I/O data transfer'
- Incorporated DTS and Binding file review comments of Shawn Guo and Rob 
Herring.

 .../devicetree/bindings/spi/spi-nxp-fspi.txt   |   39 +
 MAINTAINERS|6 +
 arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts  |   22 +
 arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi |   12 +
 arch/arm64/configs/defconfig   |1 +
 drivers/spi/Kconfig|   10 +
 drivers/spi/Makefile   |1 +
 drivers/spi/spi-nxp-fspi.c | 1158 
 8 files changed, 1249 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/spi/spi-nxp-fspi.txt
 create mode 100644 drivers/spi/spi-nxp-fspi.c

-- 
2.7.4

[PATCH v4 3/5] arm64: dts: lx2160a: add FlexSPI node property

[Yogesh Narayan Gaur]

Add fspi node property for LX2160A SoC for FlexSPI driver.
Property added for the FlexSPI controller and for the connected
slave device for the LX2160ARDB target.
This is having two SPI-NOR flash device, mt35xu512aba, connected
at CS0 and CS1.

Signed-off-by: Yogesh Gaur 
---
Changes for v4:
- Incorporated Rob review comments.
Changes for v3:
- None.
Changes for v2:
- - Incorporated Shawn review comments.

 arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 22 ++
 arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi| 12 
 2 files changed, 34 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts 
b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
index 70fad20..901ca346 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -32,6 +32,28 @@
status = "okay";
 };
 
+ {
+   status = "okay";
+
+   mt35xu512aba0: flash@0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "spansion,m25p80";
+   m25p,fast-read;
+   spi-max-frequency = <2000>;
+   reg = <0>;
+   };
+
+   mt35xu512aba1: flash@1 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "spansion,m25p80";
+   m25p,fast-read;
+   spi-max-frequency = <2000>;
+   reg = <1>;
+   };
+};
+
  {
status = "okay";
pca9547@77 {
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index e35e494..ba2a247 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -568,5 +568,17 @@
timeout-sec = <30>;
};
 
+   fspi: spi@20c {
+   compatible = "nxp,lx2160a-fspi";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0x0 0x20c 0x0 0x1>,
+   <0x0 0x2000 0x0 0x1000>;
+   reg-names = "fspi_base", "fspi_mmap";
+   interrupts = <0 25 0x4>; /* Level high type */
+   clocks = < 4 3>, < 4 3>;
+   clock-names = "fspi_en", "fspi";
+   status = "disabled";
+   };
};
 };
-- 
2.7.4