Basic support for the RZ/A2 (R7S9210) SoC.
Signed-off-by: Chris Brandt
---
v2:
* Fixed cpg node name to match reg address
* Removed the clocks subnode
* SCIF register range 18 to 0x18
* Removed 'reset-cells' from cpg because resets not supported (yet?)
* Sorted nodes by address (per group
.
Chris Brandt (2):
ARM: dts: r7s9210: Initial SoC device tree
ARM: dts: r7s9210-rza2mevb: Add support for RZ/A2M EVB
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/r7s9210-rza2mevb.dts | 98
arch/arm/boot/dts/r7s9210.dtsi | 204
Add support for Renesas RZ/A2M evaluation board.
Signed-off-by: Chris Brandt
---
v2:
* Removed patch for shmobile.txt
* Added SPDX
* Removed earlycon from bootargs
* Fixed address in memory node name
* Removed un-needed "okay" from leds node
* Added green LED node
* Dropped
Hi Geert,
Thanks for your review.
On Tuesday, December 04, 2018 1, Geert Uytterhoeven wrote:
> > + * This file is dual-licensed: you can use it either under the terms
> > + * of the GPL or the X11 license, at your option. Note that this dual
> > + * licensing only applies to this file, and not
From: Geert Uytterhoeven [mailto:ge...@linux-m68k.org]
Sent: Friday, November 30, 2018 11:03 AM
> BTW, I'd be surprised the hardware address decoder would route all
> addresses in the range 0xe803b000..0xe803b02f to the OSTM.
> 0xe803b000..0xe803b03f sounds more logical to me, as it requires less
Hi Geert,
On Friday, November 30, 2018 1, Geert wrote:
> > So in our RZ/A BSP that I release to customers I would use this dual
> > license. You can see the exact same license in a number of dts files in
> > mainline.
>
> Note that your file includes
>
> #include
> #include
>
> both
Hi Simon,
On Friday, November 30, 2018, Simon Horman wrote:
> > + - RZ/A2M Eval Board (RTK7921053S0BE)
> > +compatible = "renesas,rza2mevb", "renesas,r7s9210"
> >- RZN1D-DB (RZ/N1D Demo Board for the RZ/N1D 400 pins package)
> > compatible = "renesas,rzn1d400-db",
Hi Simon,
On Friday, November 30, 2018, Simon Horman wrote:
> > + cpg: clock-controller@fcfe0020 {
> > + compatible = "renesas,r7s9210-cpg-mssr";
> > + reg = <0xfcfe0010 0x455>;
>
> There is a discrepancy here between the base address, fcfe0020
> and the start address of
Add a Device Tree for RZ/A2 and the existing eval board.
Once these get approved, I'll start piling on the other drivers in
another patch series.
Chris Brandt (2):
ARM: dts: r7s9210: Initial SoC device tree
ARM: dts: r7s9210-rza2mevb: Add support for RZ/A2M EVB
Documentation/devicetree
Add support for Renesas RZ/A2M evaluation board.
Signed-off-by: Chris Brandt
---
Documentation/devicetree/bindings/arm/shmobile.txt | 2 +
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/r7s9210-rza2mevb.dts | 133 +
3 files
Basic support for the RZ/A2 (R7S9210) SoC.
Signed-off-by: Chris Brandt
---
arch/arm/boot/dts/r7s9210.dtsi | 211 +
1 file changed, 211 insertions(+)
create mode 100644 arch/arm/boot/dts/r7s9210.dtsi
diff --git a/arch/arm/boot/dts/r7s9210.dtsi b/arch/arm
Hi Shimodaさん
From: Yoshihiro Shimoda
Sent: Monday, November 19, 2018 3:58 AM
> And I read Figure 32.1 of the RZ/A2 documentation and I wonder if we need
> to release
> USBCTR.PLL_RST even if we use USB peripheral mode.
I will ask the RZ/A2 design team to confirm.
If this setting is required, I
Hi Geert,
On Friday, November 16, 2018, Geert Uytterhoeven wrote:
> > We can have Geert give his opinion on the topic since it was his
> > suggestion to begin with.
> >
> >
> > > I'm sorry this is more work, and again, it might be post-poned imo,
> > > provided you drop this change you have
Hi Jacopo,
On Thursday, November 15, 2018 1, jacopo mondi wrote:
> > v5:
> > * Specify number of ports using of_device_id.data and save as priv-
> >npins
> > * Use priv->npins everywhere instead of hard coded RZA2_NPINS
> > * Check gpio-ranges to make sure args matches SOC
>
> Sorry about
The pin controller in the RZ/A2 is nothing like the pin controller in
the RZ/A1. That's a good thing! This pin controller is much more simple
and easier to configure.
So, this driver is faily simple (I hope).
Chris Brandt (2):
pinctrl: Add RZ/A2 pin and gpio controller
dt-bindings: pinctrl
Adds support for the pin and gpio controller found in R7S9210 (RZ/A2) SoCs.
Signed-off-by: Chris Brandt
Reviewed-by: Jacopo Mondi
---
v6:
* Bug fix: Output value not being set in rza2_chip_direction_output()
v5:
* Specify number of ports using of_device_id.data and save as priv->npins
*
Add device tree binding documentation and header file for Renesas R7S9210
(RZ/A2) SoCs.
Signed-off-by: Chris Brandt
Reviewed-by: Rob Herring
Reviewed-by: Geert Uytterhoeven
Reviewed-by: Jacopo Mondi
---
v4:
* Converted Px to PORTx because of conflict with "PM"
* Rounded up
Adds support for the pin and gpio controller found in R7S9210 (RZ/A2) SoCs.
Signed-off-by: Chris Brandt
Reviewed-by: Jacopo Mondi
---
v5:
* Specify number of ports using of_device_id.data and save as priv->npins
* Use priv->npins everywhere instead of hard coded RZA2_NPINS
* Chec
The pin controller in the RZ/A2 is nothing like the pin controller in
the RZ/A1. That's a good thing! This pin controller is much more simple
and easier to configure.
So, this driver is faily simple (I hope).
Chris Brandt (2):
pinctrl: Add RZ/A2 pin and gpio controller
dt-bindings: pinctrl
Add device tree binding documentation and header file for Renesas R7S9210
(RZ/A2) SoCs.
Signed-off-by: Chris Brandt
Reviewed-by: Rob Herring
Reviewed-by: Geert Uytterhoeven
Reviewed-by: Jacopo Mondi
---
v4:
* Converted Px to PORTx because of conflict with "PM"
* Rounded up
Hi Shimodaさん
> From: Yoshihiro Shimoda
> Sent: Thursday, November 15, 2018 4:20 AM
> > Host does NOT work:
> > //else
> > // /* No otg, so default to host mode */
> > // writel(0x, usb2_base + USB2_COMMCTRL);
>
> I got it. However, I have a concern how to set the
Hi Geert,
On Thursday, November 15, 2018, Geert Uytterhoeven wrote:
> > As for validating the values, the only thing I can really check is that:
> > of_args.args[2] == RZA2_NPINS
> >
> > Of course, now that I say that, I realize that if/when it does come time
> > to expand this driver beyond
Add device tree binding documentation and header file for Renesas R7S9210
(RZ/A2) SoCs.
Signed-off-by: Chris Brandt
Reviewed-by: Rob Herring
Reviewed-by: Geert Uytterhoeven
Reviewed-by: Jacopo Mondi
---
v4:
* Converted Px to PORTx because of conflict with "PM"
* Rounded up
The pin controller in the RZ/A2 is nothing like the pin controller in
the RZ/A1. That's a good thing! This pin controller is much more simple
and easier to configure.
So, this driver is faily simple (I hope).
Chris Brandt (2):
pinctrl: Add RZ/A2 pin and gpio controller
dt-bindings: pinctrl
Adds support for the pin and gpio controller found in R7S9210 (RZ/A2) SoCs.
Signed-off-by: Chris Brandt
Reviewed-by: Jacopo Mondi
---
v4:
* Mention GPIO in Kconfig
* Removed port enum and just define RZA2_NPORTS
* Moved gpio_range from global to private data
* Condensed and simplify
Hi Jacopo,
Thank you for your reviewagain ;)
On Tuesday, November 13, 2018, jacopo mondi wrote:
> I would prefer the reverse xmas order too, but I'm not saying out loud
> as I understand is something hard to enforce, as it's a very minor
> issue :)
The next version will be very festive!
Hi Geert,
Just in case you were wondering...
On Monday, November 12, 2018, Geert Uytterhoeven wrote:
> > + "PJ_0", "PJ_1", "PJ_2", "PJ_3", "PJ_4", "PJ_5", "PJ_6", "PJ_7",
> > + "PK_0", "PK_1", "PK_2", "PK_3", "PK_4", "PK_5", "PK_6", "PK_7",
> > + "PL_0", "PL_1", "PL_2", "PL_3",
Hi Shimoda-san,
> From: Yoshihiro Shimoda
> Sent: Wednesday, November 14, 2018 7:24 AM
> > > > config PHY_RCAR_GEN3_USB2
> > > > tristate "Renesas R-Car generation 3 USB 2.0 PHY driver"
> > > > depends on ARCH_RENESAS
> > > > - depends on EXTCON
> > > > + depends on
Hi Geert,
On Wednesday, November 14, 2018, Geert Uytterhoeven wrote:
> > Required properties:
> > -- compatible: "renesas,usb2-phy-r8a774a1" if the device is a part of an
> R8A774A1
> > +- compatible: "renesas,usb2-phy-r7s9210" if the device is a part of an
> R7S9210
> > + SoC.
> > +
Hi Shimoda-san,
> From: Yoshihiro Shimoda
> Sent: Wednesday, November 14, 2018 5:50 AM
> > config PHY_RCAR_GEN3_USB2
> > tristate "Renesas R-Car generation 3 USB 2.0 PHY driver"
> > depends on ARCH_RENESAS
> > - depends on EXTCON
> > + depends on EXTCON || ARCH_R7S9210
>
> Does this
On Tuesday, November 13, 2018, jacopo mondi wrote:
> Just two minor things, so please add my
> Reviewed-by: Jacopo Mondi
Thanks Jacopo!
Chris
Hi Geert,
On Tuesday, November 13, 2018, Geert Uytterhoeven wrote:
> > It makes the files show up under /sys look nice.
> >
> > For example, P5_6 is button SW4:
> >
> > $ echo 912 > /sys/class/gpio/export
> >
> > Then you end up with "/sys/class/gpio/P5_6/"
> >
> > $ echo in >
Hi Geert,
As always, thank you for your review!
On Monday, November 12, 2018, Geert Uytterhoeven wrote:
> > +config PINCTRL_RZA2
> > + bool "Renesas RZ/A2 gpio and pinctrl driver"
> > + depends on OF
> > + depends on ARCH_R7S9210 || COMPILE_TEST
> > + select GPIOLIB
> >
Hi Geert,
On Tuesday, November 13, 2018 1, Geert Uytterhoeven wrote:
> Perhaps adding a convenience definition
>
> #define JP PM
>
> may be a good idea? Or just a comment?
>
> #define PM 21/* JP */
Either one is OK I guess. I'll see which one makes more sense as I
reworked
Hi Geert,
On Monday, November 12, 2018 1, Geert Uytterhoeven wrote:
> > +Required properties:
> > + - compatible: should be:
> > +- "renesas,r7s9210-pinctrl": for RZ/A2M
>
> On RZ/A1, the datasheet called this "Ports", and the corresponding
> compatible
> value is "renesas,r7s72100-ports".
Adds support for the pin and gpio controller found in R7S9210 (RZ/A2) SoCs.
Signed-off-by: Chris Brandt
---
v3:
- Changed names from Px to PORTx because "PC" is already defined
v2:
- fixed SOC part number in comments
- sorted #includes
- removed spaces in pfc_pin_port_name e
Add device tree binding documentation and header file for Renesas R7S9210
(RZ/A2) SoCs.
Signed-off-by: Chris Brandt
Reviewed-by: Rob Herring
---
v3:
- Added Reviewed-by
v2:
* Moved gpio-controller to required
* Wrote a better description of what the sub-nodes are for
* Added pinmux property
The pin controller in the RZ/A2 is nothing like the pin controller in
the RZ/A1. That's a good thing! This pin controller is much more simple
and easier to configure.
So, this driver is faily simple (I hope).
V3 -> V4: Sorry...I forgot Rob's Reviewed-by !!
Chris Brandt (2):
pinctrl:
Add device tree binding documentation and header file for Renesas R7S9210
(RZ/A2) SoCs.
Signed-off-by: Chris Brandt
---
v2:
* Moved gpio-controller to required
* Wrote a better description of what the sub-nodes are for
* Added pinmux property description
* Changed macro RZA2_PIN_ID
The pin controller in the RZ/A2 is nothing like the pin controller in
the RZ/A1. That's a good thing! This pin controller is much more simple
and easier to configure.
So, this driver is faily simple (I hope).
Chris Brandt (2):
pinctrl: Add RZ/A2 pin and gpio controller
dt-bindings: pinctrl
Adds support for the pin and gpio controller found in R7S9210 (RZ/A2) SoCs.
Signed-off-by: Chris Brandt
---
v3:
- Changed names from Px to PORTx because "PC" is already defined
v2:
- fixed SOC part number in comments
- sorted #includes
- removed spaces in pfc_pin_port_name e
Add USB clocks for RZ/A2
Signed-off-by: Chris Brandt
---
drivers/clk/renesas/r7s9210-cpg-mssr.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/renesas/r7s9210-cpg-mssr.c
b/drivers/clk/renesas/r7s9210-cpg-mssr.c
index 3922967ba811..efbbf56e6766 100644
--- a/drivers/clk
Document RZ/A2 (R7S9210) SoC bindings.
Signed-off-by: Chris Brandt
---
Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt
b/Documentation
The RZ/A2 has the same USB2 host controller as R-Car Gen3 with only some
minor differences.
Signed-off-by: Chris Brandt
---
drivers/phy/renesas/Kconfig | 2 +-
drivers/phy/renesas/phy-rcar-gen3-usb2.c | 12
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git
Add support for RZ/A2. Basically has the same IP as R-Car Gen3.
Chris Brandt (3):
clk: renesas: r7s9210: Add USB clocks
phy: renesas: rcar-gen3-usb2: Add support for R7S9210
dt-bindings: rcar-gen3-phy-usb2: Add r7s9210 support
Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt
Hi Geert,
> > Great, so MIPS defines PC, precluding it use in any driver that includes
> > in some way.
That really stinks!!!
> Anyway, drivers//pinctrl/pinctrl-rza2.c doesn't really use the enum
> values it defines,
> so they can be renamed (PC -> PORTC, or PORT_C).
Of course that means I
The RIIC I2C controller is used in Renesas RZ/A SoCs.
Signed-off-by: Chris Brandt
---
MAINTAINERS | 5 +
1 file changed, 5 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index e20d9af09573..c261135cd00c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -12599,6 +12599,11 @@ S
Add SDHI clocks for RZ/A2
Signed-off-by: Chris Brandt
Reviewed-by: Geert Uytterhoeven
---
(Geert will apply to his tree)
---
drivers/clk/renesas/r7s9210-cpg-mssr.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/clk/renesas/r7s9210-cpg-mssr.c
b/drivers/clk/renesas/r7s9210-cpg
Basically the same HW block that was used in R-Car Gen 3 is used in
RZ/A2 (with only a couple small differences).
V5 was just to rebase to fix merge conflicts
Chris Brandt (3):
clk: renesas: r7s9210: Add SDHI clocks
mmc: renesas_sdhi_internal_dmac: Add R7S9210 support
dt-bindings: mmc
The SDHI/MMC controller in the RZ/A2 is almost the same as R-Car gen3, but
with some minor differences.
Signed-off-by: Chris Brandt
---
v5:
* Rebased against -next to fix conficts with RZ/G1C patches
* Changed Kconfig message to say "found in some RZ" instead of just
"fo
Document support for the RZ/A2 (R7S9210) SoC.
Signed-off-by: Chris Brandt
Reviewed-by: Geert Uytterhoeven
Reviewed-by: Rob Herring
Reviewed-by: Simon Horman
---
v3:
* Added Reviewed-by from Rob and Simon
v2:
* Documented that R7S9210 has 2 clocks
---
Documentation/devicetree/bindings/mmc
On Tuesday, October 23, 2018, Ulf Hansson wrote:
> On 12 October 2018 at 14:29, Chris Brandt
> wrote:
> > Basically the same HW block that was used in R-Car Gen 3 is used in
> > RZ/A2 (with only a couple small differences).
> >
> > Not sure if you're go
The pin controller in the RZ/A2 is nothing like the pin controller in
the RZ/A1. That's a good thing! This pin controller is much more simple
and easier to configure.
So, this driver is faily simple (I hope).
Chris Brandt (2):
pinctrl: Add RZ/A2 pin and gpio controller
dt-bindings: pinctrl
Add device tree binding documentation and header file for Renesas R7S9210
(RZ/A2) SoCs.
Signed-off-by: Chris Brandt
---
v2:
* Moved gpio-controller to required
* Wrote a better description of what the sub-nodes are for
* Added pinmux property description
* Changed macro RZA2_PIN_ID
Hi Jacopo,
On Thursday, October 18, 2018, jacopo mondi wrote:
> Here you define bindings that allows you to have only one
> gpio-controller node for the whole system.
Correct. Since DT describes HW, we do only have one gpio-controller for
the entire chip. It is one piece of hardware, not many
Hi Jacopo,
On Thursday, October 18, 2018, jacopo mondi wrote:
> > + Example: Assigning a GPIO:
> > +
> > + leds {
> > + status = "okay";
> > + compatible = "gpio-leds";
> > +
> > + led0 {
> > + /* P6_0 */
> > + gpios = <
Hi Jacopo,
>thanks for the patches.
Thanks for the review!
On Thursday, October 18, 2018, jacopo mondi wrote:
> > + * Combined GPIO and pin controller support for Renesas RZ/A2
> (R7S72100) SoC
>
> R7S9210
Thanks.
hmm, I wonder what pinctrl driver I copied that from... ;)
> > +#include
On Tuesday, October 16, 2018, Rob Herring wrote:
> > +Optional properties:
> > + - gpio-controller
> > +Include this in order to enable GPIO functionality. When included,
> both
> > +gpio_cells and gpio_ranges are then required.
> > + - #gpio-cells
> > +Must be 2
> > + - gpio-ranges
Document support for the RZ/A2 (R7S9210) SoC.
Signed-off-by: Chris Brandt
Reviewed-by: Geert Uytterhoeven
---
v2:
* Documented that R7S9210 has 2 clocks
---
Documentation/devicetree/bindings/mmc/tmio_mmc.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation
The SDHI/MMC controller in the RZ/A2 is almost the same as R-Car gen3, but
with some minor differences.
Signed-off-by: Chris Brandt
---
v4:
* Fixed spelling in #define
v3:
* Removed extra space in Kconfig
* Removed unneeded parentheses
v2:
* Made comment clearer
---
drivers/mmc/host/Kconfig
Basically the same HW block that was used in R-Car Gen 3 is used in
RZ/A2 (with only a couple small differences).
Not sure if you're going to like the Kconfig change or not.
Chris Brandt (3):
clk: renesas: r7s9210: Add SDHI clocks
mmc: renesas_sdhi_internal_dmac: Add R7S9210 support
dt
Add SDHI clocks for RZ/A2
Signed-off-by: Chris Brandt
Reviewed-by: Geert Uytterhoeven
---
drivers/clk/renesas/r7s9210-cpg-mssr.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/clk/renesas/r7s9210-cpg-mssr.c
b/drivers/clk/renesas/r7s9210-cpg-mssr.c
index 5135f13ec628
Hi Wolfram,
On Friday, October 12, 2018, Wolfram Sang wrote:
> > +/* RZ/A2 does not have the ADRR_MODE bit */
> > +#define SDHI_INTERNAL_DMAC_ADRR_MODE_FIXED 2
>
> First, there is a typo: s/ADRR/ADDR/g
Thanks!
Even after you pointed that out...I had to stare real hard to see it. I
guess the
The SDHI/MMC controller in the RZ/A2 is almost the same as R-Car gen3, but
with some minor differences.
Signed-off-by: Chris Brandt
---
v3:
* Removed extra space in Kconfig
* Removed unneeded parentheses
v2:
* Made comment clearer
---
drivers/mmc/host/Kconfig | 5
Add SDHI clocks for RZ/A2
Signed-off-by: Chris Brandt
Reviewed-by: Geert Uytterhoeven
---
drivers/clk/renesas/r7s9210-cpg-mssr.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/clk/renesas/r7s9210-cpg-mssr.c
b/drivers/clk/renesas/r7s9210-cpg-mssr.c
index 5135f13ec628
Document support for the RZ/A2 (R7S9210) SoC.
Signed-off-by: Chris Brandt
Reviewed-by: Geert Uytterhoeven
---
v2:
* Documented that R7S9210 has 2 clocks
---
Documentation/devicetree/bindings/mmc/tmio_mmc.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation
Basically the same HW block that was used in R-Car Gen 3 is used in
RZ/A2 (with only a couple small differences).
Not sure if you're going to like the Kconfig change or not.
Chris Brandt (3):
clk: renesas: r7s9210: Add SDHI clocks
mmc: renesas_sdhi_internal_dmac: Add R7S9210 support
dt
On Wednesday, October 10, 2018 1, Sergei Shtylyov wrote:
> > config MMC_SDHI_INTERNAL_DMAC
> > tristate "DMA for SDHI SD/SDIO controllers using on-chip bus
> mastering"
> > - depends on ARM64 || COMPILE_TEST
> > + depends on ARM64 || ARCH_R7S9210 || COMPILE_TEST
>
>Double space
Add SDHI clocks for RZ/A2
Signed-off-by: Chris Brandt
Reviewed-by: Geert Uytterhoeven
---
drivers/clk/renesas/r7s9210-cpg-mssr.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/clk/renesas/r7s9210-cpg-mssr.c
b/drivers/clk/renesas/r7s9210-cpg-mssr.c
index 5135f13ec628
Basically the same HW block that was used in R-Car Gen 3 is used in
RZ/A2 (with only a couple small differences).
Not sure if you're going to like the Kconfig change or not.
Chris Brandt (3):
clk: renesas: r7s9210: Add SDHI clocks
mmc: renesas_sdhi_internal_dmac: Add R7S9210 support
dt
The SDHI/MMC controller in the RZ/A2 is almost the same as R-Car gen3, but
with some minor differences.
Signed-off-by: Chris Brandt
---
v2:
* Made comment clearer
---
drivers/mmc/host/Kconfig | 5 +++--
drivers/mmc/host/renesas_sdhi_internal_dmac.c | 28
Document support for the RZ/A2 (R7S9210) SoC.
Signed-off-by: Chris Brandt
Reviewed-by: Geert Uytterhoeven
---
v2:
* Documented that R7S9210 has 2 clocks
---
Documentation/devicetree/bindings/mmc/tmio_mmc.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation
Hi Geert,
On Wednesday, October 10, 2018, Geert Uytterhoeven wrote:
> Thanks for your patch!
Thanks for your review!
> > +/* RZ/A2 does not have this bit (not safe to set it) */
>
> This comment confused me, as SDHI_INTERNAL_DMAC_ADRR_MODE_FIXED is
> set for RZ/A2.
>
> s/this bit/the
The SDHI/MMC controller in the RZ/A2 is almost the same as R-Car gen3, but
with some minor differences.
Signed-off-by: Chris Brandt
---
drivers/mmc/host/Kconfig | 5 +++--
drivers/mmc/host/renesas_sdhi_internal_dmac.c | 28 +--
2 files changed, 29
Basically the same HW block that was used in R-Car Gen 3 is used in
RZ/A2 (with only a couple small differences).
Not sure if you're going to like the Kconfig change or not.
Chris Brandt (3):
clk: renesas: r7s9210: Add SDHI clocks
mmc: renesas_sdhi_internal_dmac: Add R7S9210 support
dt
Document support for the RZ/A2 (R7S9210) SoC.
Signed-off-by: Chris Brandt
---
Documentation/devicetree/bindings/mmc/tmio_mmc.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
index
Add SDHI clocks for RZ/A2
Signed-off-by: Chris Brandt
---
drivers/clk/renesas/r7s9210-cpg-mssr.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/clk/renesas/r7s9210-cpg-mssr.c
b/drivers/clk/renesas/r7s9210-cpg-mssr.c
index 5135f13ec628..9056da15dc72 100644
--- a/drivers/clk
Add device tree binding documentation and header file for Renesas R7S9210
(RZ/A2) SoCs.
Signed-off-by: Chris Brandt
---
.../bindings/pinctrl/renesas,rza2-pinctrl.txt | 76 ++
include/dt-bindings/pinctrl/r7s9210-pinctrl.h | 47 +
2 files changed, 123
Adds support for the pin and gpio controller found in R7S9210 (RZ/A2) SoCs.
Signed-off-by: Chris Brandt
---
drivers/pinctrl/Kconfig| 11 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/pinctrl-rza2.c | 519 +
3 files changed, 531
The pin controller in the RZ/A2 is nothing like the pin controller in
the RZ/A1. That's a good thing! This pin controller is much more simple
and easier to configure.
So, this driver is faily simple (I hope).
Chris Brandt (2):
pinctrl: Add RZ/A2 pin and gpio controller
dt-bindings: pinctrl
Hi Geert,
On Thursday, September 27, 2018 1, Geert Uytterhoeven wrote:
> Looks good, but you forgot to update the paragraph above (outside the
> quoted context).
OK, thanks.
Funny...even a 1-line patch requires 2 versions from me!
(I wish I got paid per revision)
Chris
Add support for RZ/A2
Signed-off-by: Chris Brandt
---
v2:
* Made instructions more generic for RZ/A devices
FYI: No driver changes were needed
---
Documentation/devicetree/bindings/spi/spi-rspi.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree
The R7S9210 belongs to the RZ/A2 SoC series
Signed-off-by: Chris Brandt
---
FYI: No driver changes were needed
---
Documentation/devicetree/bindings/timer/renesas,ostm.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/timer/renesas
Add support for RZ/A2
Signed-off-by: Chris Brandt
---
FYI: No driver changes were needed
---
Documentation/devicetree/bindings/spi/spi-rspi.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/spi/spi-rspi.txt
b/Documentation/devicetree/bindings/spi/spi
Add RSPI clocks for RZ/A2.
Signed-off-by: Chris Brandt
---
drivers/clk/renesas/r7s9210-cpg-mssr.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/clk/renesas/r7s9210-cpg-mssr.c
b/drivers/clk/renesas/r7s9210-cpg-mssr.c
index d8ff4cb0defc..5135f13ec628 100644
--- a/drivers/clk
Hi Geert,
On Wednesday, September 26, 2018, Geert Uytterhoeven wrote:
> > +/* The clock dividers in the table vary based on DT and register
> settings */
> > +static void r7s9210_update_clk_table(struct clk *extal_clk, void
> __iomem *base)
>
> Can be __init.
>
> Reviewed-by: Geert Uytterhoeven
Hi Geert
On Wednesday, September 26, 2018, Geert Uytterhoeven wrote:
> Thanks for the update!
> Works fine on R-Car Gen2 and Gen3.
Thank you for checking!
> > struct clk **clks;
>
> In v1, you initialized clks to NULL, which was needed ...
~~~
> > + priv->base = of_iomap(np, 0);
On Tuesday, September 25, 2018 1, Rob Herring wrote:
> I gave Reviewed-by on v3. Please add acks/reviewed-bys when posting new
> versions.
Sorry about that!
Chris
Same functionality, just easier to read.
Signed-off-by: Chris Brandt
---
drivers/clk/renesas/r7s9210-cpg-mssr.c | 94 ++
1 file changed, 49 insertions(+), 45 deletions(-)
diff --git a/drivers/clk/renesas/r7s9210-cpg-mssr.c
b/drivers/clk/renesas/r7s9210-cpg
The OSTM timer driver for RZ/A2 uses TIMER_OF_DECLARE which requires the
ostm module clocks to be registers early in boot.
Signed-off-by: Chris Brandt
---
v2:
* List early clocks first
* Remove unnecessary comments
* Removed new function r7s9210_update_clk_table (to be included
Add support for SoCs that need to register core and module clocks early in
order to use OF drivers that exclusively use macros such as
TIMER_OF_DECLARE.
Signed-off-by: Chris Brandt
---
v2:
* List early clocks first
* Renamed early_priv to cpg_mssr_priv and make it static
* Always set
eded for r8a7791 or r8a7793,
that line will need to be changed.
* In r7s9210-cpg-mssr.c, I moved updating the clock ratio table to a
separate function (r7s9210_update_table) because it looks cleaner.
Chris Brandt (3):
clk: renesas: cpg-mssr: Add early clock support
clk: renesas: r7s92
Hi Geert,
On Monday, September 24, 2018, Geert Uytterhoeven wrote:
> Thanks for your patch!
Thanks for your review!
> > +struct cpg_mssr_priv *early_priv;
>
> static
>
> Just call the pointer cpg_mssr_priv, as you're gonna need it in both
> cases
> (see below)?
Seems strange to have a
The RZ/A2 watchdog timer extends the clock source options in order to
allow for longer timeouts.
Signed-off-by: Chris Brandt
Reviewed-by: Guenter Roeck
---
v5:
* Added type casting as pointed out by kbuild test robot
* Added Reviewed-by
v4:
* Documented CKS_3BIT/CKS_4BIT better
* Changed
Document support for RZ/A2
Signed-off-by: Chris Brandt
Reviewed-by: Guenter Roeck
---
v2:
* Added Reviewed-by
---
Documentation/devicetree/bindings/watchdog/renesas-wdt.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/watchdog/renesas-wdt.txt
b
Slightly modify the rza_wdt.c driver and update the binding docs.
Chris Brandt (2):
watchdog: rza_wdt: Support longer timeouts
dt-bindings: watchdog: renesas-wdt: Add support for R7S9210
.../devicetree/bindings/watchdog/renesas-wdt.txt | 1 +
drivers/watchdog/rza_wdt.c
The OSTM timer driver for RZ/A2 uses TIMER_OF_DECLARE which requires the
ostm module clocks to be registers early in boot.
Signed-off-by: Chris Brandt
---
drivers/clk/renesas/r7s9210-cpg-mssr.c | 141 +
1 file changed, 90 insertions(+), 51 deletions(-)
diff
Add support for SoCs that need to register core and module clocks early in
order to use OF drivers that exclusively use macros such as
TIMER_OF_DECLARE.
Signed-off-by: Chris Brandt
---
drivers/clk/renesas/renesas-cpg-mssr.c | 106 ++---
drivers/clk/renesas/renesas
eded for r8a7791 or r8a7793,
that line will need to be changed.
* In r7s9210-cpg-mssr.c, I moved updating the clock ratio table to a
separate function (r7s9210_update_table) because it looks cleaner.
Chris Brandt (2):
clk: renesas: cpg-mssr: Add early clock support
clk: renesas: r7s92
Hi Geert,
On Tuesday, September 18, 2018 1, Geert Uytterhoeven wrote:
> > So I see what the mediatek is doing, but I can't seem to reproduce it.
> I
> > must be missing something.
>
> It's using CLK_OF_DECLARE_DRIVER(), which clears OF_POPULATED:
Yup, that's what I was missing.
Works now.
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